linux-kexecboot: add 2.6.29, currently only supports beagle

169 files changed, 157949 insertions, 0 deletions

diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/0001-ASoC-Add-support-for-OMAP3-EVM.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/0001-ASoC-Add-support-for-OMAP3-EVM.patch
new file mode 100644
index 0000000000..a76e96e444
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/0001-ASoC-Add-support-for-OMAP3-EVM.patch
@@ -0,0 +1,206 @@
+From c1dad0b6b434300ae64c902d11611c54c513ea10 Mon Sep 17 00:00:00 2001
+From: Anuj Aggarwal <anuj.aggarwal@ti.com>
+Date: Fri, 21 Nov 2008 17:41:03 +0530
+Subject: [PATCH] ASoC: Add support for OMAP3 EVM
+
+This patch adds ALSA SoC support for OMAP3 EVM using TWL4030 audio codec.
+
+Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com>
+---
+ sound/soc/omap/Kconfig    |    8 +++
+ sound/soc/omap/Makefile   |    3 +-
+ sound/soc/omap/omap3evm.c |  147 +++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 157 insertions(+), 1 deletions(-)
+ create mode 100644 sound/soc/omap/omap3evm.c
+
+diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
+index 0daeee4..deb6ba9 100644
+--- a/sound/soc/omap/Kconfig
++++ b/sound/soc/omap/Kconfig
+@@ -22,6 +22,14 @@ config SND_OMAP_SOC_OMAP3_BEAGLE
+ 	help
+ 	  Say Y if you want to add support for SoC audio on the Beagleboard.
+ 
++config SND_OMAP_SOC_OMAP3EVM
++        tristate "SoC Audio support for OMAP3EVM board"
++        depends on SND_OMAP_SOC && MACH_OMAP3EVM
++        select SND_OMAP_SOC_MCBSP
++        select SND_SOC_TWL4030
++        help
++          Say Y if you want to add support for SoC audio on the omap3evm board.
++
+ config SND_OMAP_SOC_OSK5912
+ 	tristate "SoC Audio support for omap osk5912"
+ 	depends on SND_OMAP_SOC && MACH_OMAP_OSK
+diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
+index 4bae404..ef31c25 100644
+--- a/sound/soc/omap/Makefile
++++ b/sound/soc/omap/Makefile
+@@ -10,9 +10,10 @@ snd-soc-n810-objs := n810.o
+ snd-soc-omap3beagle-objs := omap3beagle.o
+ snd-soc-osk5912-objs := osk5912.o
+ snd-soc-overo-objs := overo.o
++snd-soc-omap3evm-objs := omap3evm.o
+ 
+ obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o
+ obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
+ obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o
+ obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o
+-
++obj-$(CONFIG_MACH_OMAP3EVM) += snd-soc-omap3evm.o
+diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
+new file mode 100644
+index 0000000..570af55
+--- /dev/null
++++ b/sound/soc/omap/omap3evm.c
+@@ -0,0 +1,147 @@
++/*
++ * omap3evm.c  -- ALSA SoC support for OMAP3 EVM
++ *
++ * Author: Anuj Aggarwal <anuj.aggarwal@ti.com>
++ *
++ * Based on sound/soc/omap/beagle.c by Steve Sakoman
++ *
++ * Copyright (C) 2008 Texas Instruments, Incorporated
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
++ * whether express or implied; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <mach/hardware.h>
++#include <mach/gpio.h>
++#include <mach/mcbsp.h>
++
++#include "omap-mcbsp.h"
++#include "omap-pcm.h"
++#include "../codecs/twl4030.h"
++
++static int omap3evm_hw_params(struct snd_pcm_substream *substream,
++	struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
++	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
++	int ret;
++
++	/* Set codec DAI configuration */
++	ret = snd_soc_dai_set_fmt(codec_dai,
++				  SND_SOC_DAIFMT_I2S |
++				  SND_SOC_DAIFMT_NB_NF |
++				  SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0) {
++		printk(KERN_ERR "can't set codec DAI configuration\n");
++		return ret;
++	}
++
++	/* Set cpu DAI configuration */
++	ret = snd_soc_dai_set_fmt(cpu_dai,
++				  SND_SOC_DAIFMT_I2S |
++				  SND_SOC_DAIFMT_NB_NF |
++				  SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0) {
++		printk(KERN_ERR "can't set cpu DAI configuration\n");
++		return ret;
++	}
++
++	/* Set the codec system clock for DAC and ADC */
++	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
++				     SND_SOC_CLOCK_IN);
++	if (ret < 0) {
++		printk(KERN_ERR "can't set codec system clock\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static struct snd_soc_ops omap3evm_ops = {
++	.hw_params = omap3evm_hw_params,
++};
++
++/* Digital audio interface glue - connects codec <--> CPU */
++static struct snd_soc_dai_link omap3evm_dai = {
++	.name = "TWL4030",
++	.stream_name = "TWL4030",
++	.cpu_dai = &omap_mcbsp_dai[0],
++	.codec_dai = &twl4030_dai,
++	.ops = &omap3evm_ops,
++};
++
++/* Audio machine driver */
++static struct snd_soc_machine snd_soc_machine_omap3evm = {
++	.name = "omap3evm",
++	.dai_link = &omap3evm_dai,
++	.num_links = 1,
++};
++
++/* Audio subsystem */
++static struct snd_soc_device omap3evm_snd_devdata = {
++	.machine = &snd_soc_machine_omap3evm,
++	.platform = &omap_soc_platform,
++	.codec_dev = &soc_codec_dev_twl4030,
++};
++
++static struct platform_device *omap3evm_snd_device;
++
++static int __init omap3evm_soc_init(void)
++{
++	int ret;
++
++	if (!machine_is_omap3evm()) {
++		pr_debug("Not OMAP3 EVM!\n");
++		return -ENODEV;
++	}
++	pr_info("OMAP3 EVM SoC init\n");
++
++	omap3evm_snd_device = platform_device_alloc("soc-audio", -1);
++	if (!omap3evm_snd_device) {
++		printk(KERN_ERR "Platform device allocation failed\n");
++		return -ENOMEM;
++	}
++
++	platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata);
++	omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev;
++	*(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */
++
++	ret = platform_device_add(omap3evm_snd_device);
++	if (ret)
++		goto err1;
++
++	return 0;
++
++err1:
++	printk(KERN_ERR "Unable to add platform device\n");
++	platform_device_put(omap3evm_snd_device);
++
++	return ret;
++}
++
++static void __exit omap3evm_soc_exit(void)
++{
++	platform_device_unregister(omap3evm_snd_device);
++}
++
++module_init(omap3evm_soc_init);
++module_exit(omap3evm_soc_exit);
++
++MODULE_AUTHOR("Anuj Aggarwal <anuj.aggarwal@ti.com>");
++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM");
++MODULE_LICENSE("GPL");
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch
new file mode 100644
index 0000000000..d590f8ffb9
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch
@@ -0,0 +1,146 @@
+From f8f10f496bce396416d7156da876222c6ce8c341 Mon Sep 17 00:00:00 2001
+From: Steven Kipisz <skipisz@beagleboard.org>
+Date: Wed, 9 Jan 2009 12:01:11 -0600
+Subject: [PATCH-USB] Omap3 beagleboard: add support for EHCI in revision C1 boards
+
+Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   10 +---------
+ arch/arm/mach-omap2/usb-ehci.c          |    4 +---
+ drivers/usb/host/ehci-omap.c            |   26 ++++++++++++++++++++++++++
+ 3 files changed, 28 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index fe97bab..de81153 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -140,15 +140,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
+ 	 * power switch and overcurrent detect
+ 	 */
+ 
+-	gpio_request(gpio + 1, "EHCI_nOC");
+-	gpio_direction_input(gpio + 1);
+-
+-	/* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
+-	gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
+-	gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1);
+-
+-	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+-	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
++        /* TODO: This needs to be modified to not rely on u-boot */
+ 
+ 	return 0;
+ }
+diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
+index 489439d..2c6305b 100644
+--- a/arch/arm/mach-omap2/usb-ehci.c
++++ b/arch/arm/mach-omap2/usb-ehci.c
+@@ -152,9 +152,7 @@ static void setup_ehci_io_mux(void)
+ void __init usb_ehci_init(void)
+ {
+ #if     defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
+-	/* Setup Pin IO MUX for EHCI */
+-	if (cpu_is_omap34xx())
+-		setup_ehci_io_mux();
++	/* TODO: Setup Pin IO MUX for EHCI - moved this temporarily to U-boot */
+ 
+ 	if (platform_device_register(&ehci_device) < 0) {
+ 		printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
+
+diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
+index 1b3266c..8472996 100644
+--- a/drivers/usb/host/ehci-omap.c
++++ b/drivers/usb/host/ehci-omap.c
+@@ -48,16 +48,26 @@
+  *		to get the PHY state machine in working state
+  */
+ #define EXTERNAL_PHY_RESET
++#ifdef CONFIG_MACH_OMAP3_BEAGLE
++#define	EXT_PHY_RESET_GPIO_PORT2	(147)
++#else
+ #define	EXT_PHY_RESET_GPIO_PORT1	(57)
+ #define	EXT_PHY_RESET_GPIO_PORT2	(61)
++#endif
+ #define	EXT_PHY_RESET_DELAY		(10)
+ 
++#define PHY_STP_PULLUP_ENABLE           (0x10)
++#define PHY_STP_PULLUP_DISABLE          (0x90)
++
++
+ /* ISSUE2:
+  * USBHOST supports External charge pump PHYs only
+  * Use the VBUS from Port1 to power VBUS of Port2 externally
+  * So use Port2 as the working ULPI port
+  */
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ #define VBUS_INTERNAL_CHARGEPUMP_HACK
++#endif
+ 
+ #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
+ 
+@@ -225,14 +235,43 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 
+ #ifdef EXTERNAL_PHY_RESET
+ 	/* Refer: ISSUE1 */
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT1, "USB1 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT1, 0);
++#endif
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT2, "USB2 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT2, 0);
++	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 0);
+ 	/* Hold the PHY in RESET for enough time till DIR is high */
+ 	udelay(EXT_PHY_RESET_DELAY);
+ #endif
+ 
++        /*
++         * The PHY register 0x7 - Interface Control register is
++         * configured to disable the integrated STP pull-up resistor
++         * used for interface protection.
++	 *
++	 * May not need to be here.
++         */
++        omap_writel((0x7 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* interface reg */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (PHY_STP_PULLUP_DISABLE),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
++        /* Force PHY to HS */
++        omap_writel((0x4 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* function ctrl */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (0x40),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
+ 	/* Configure TLL for 60Mhz clk for ULPI */
+ 	ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
+ 	if (IS_ERR(ehci_clocks->usbtll_fck_clk))
+@@ -307,7 +346,9 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 	 * Hold the PHY in RESET for enough time till PHY is settled and ready
+ 	 */
+ 	udelay(EXT_PHY_RESET_DELAY);
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT1, 1);
++#endif
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 1);
+ #endif
+ 
+@@ -393,7 +434,9 @@ static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 
+ 
+ #ifdef EXTERNAL_PHY_RESET
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT1);
++#endif
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT2);
+ #endif
+
+--
+1.6.0.4.790.gaa14a 
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/0001-board-ldp-add-regulator-info-to-get-the-microSD-slo.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/0001-board-ldp-add-regulator-info-to-get-the-microSD-slo.patch
new file mode 100644
index 0000000000..49045f7bb1
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/0001-board-ldp-add-regulator-info-to-get-the-microSD-slo.patch
@@ -0,0 +1,90 @@
+From 7efa7cc5b807cb840c62b5bf54bf47181c9b95a6 Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@openembedded.org>
+Date: Mon, 30 Mar 2009 15:21:37 +0200
+Subject: [PATCH v2] ARM: OMAP: board-ldp: add regulator info to get the microSD slot working again
+
+The ldp board was left behind when other boards got updated. The ldp info was copied from the beagleboard board file and s/beagle/ldp/g
+
+Changes since v1:
+ * dropped vsim portion since only 4 pins are hooked up
+
+Signed-off-by: Koen Kooi <koen@beagleboard.org>
+---
+ arch/arm/mach-omap2/board-ldp.c |   32 ++++++++++++++++++++++++++++++++
+ 1 files changed, 32 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index 30926b0..19a5c15 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -22,6 +22,7 @@
+ #include <linux/clk.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
++#include <linux/regulator/machine.h>
+ #include <linux/i2c/twl4030.h>
+ 
+ #include <mach/hardware.h>
+@@ -450,7 +451,16 @@ static struct twl4030_script *twl4030_scripts[] __initdata = {
+ 	&wrst_script,
+ };
+ 
++static const struct twl4030_resconfig ldp_resconfig[] = {
++	/* disable regulators that u-boot left enabled; the
++	 * devices' drivers should be managing these.
++	 */
++	{ .resource = RES_VMMC1, },
++	{ 0, },
++};
++
+ static struct twl4030_power_data sdp3430_t2scripts_data __initdata = {
++	.resource_config	= ldp_resconfig,
+ 	.scripts	= twl4030_scripts,
+ 	.size		= ARRAY_SIZE(twl4030_scripts),
+ };
+@@ -474,6 +484,25 @@ static struct twl4030_madc_platform_data ldp_madc_data = {
+ 	.irq_line	= 1,
+ };
+ 
++static struct regulator_consumer_supply ldp_vmmc1_supply = {
++	.supply			= "vmmc",
++};
++
++/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
++static struct regulator_init_data ldp_vmmc1 = {
++	.constraints = {
++		.min_uV			= 1850000,
++		.max_uV			= 3150000,
++		.valid_modes_mask	= REGULATOR_MODE_NORMAL
++					| REGULATOR_MODE_STANDBY,
++		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE
++					| REGULATOR_CHANGE_MODE
++					| REGULATOR_CHANGE_STATUS,
++	},
++	.num_consumer_supplies	= 1,
++	.consumer_supplies	= &ldp_vmmc1_supply,
++};
++
+ static struct twl4030_platform_data ldp_twldata = {
+ 	.irq_base	= TWL4030_IRQ_BASE,
+ 	.irq_end	= TWL4030_IRQ_END,
+@@ -483,6 +512,7 @@ static struct twl4030_platform_data ldp_twldata = {
+ 	.madc		= &ldp_madc_data,
+ 	.usb		= &ldp_usb_data,
+ 	.power		= &sdp3430_t2scripts_data,
++	.vmmc1		= &ldp_vmmc1,
+ 	.gpio		= &ldp_gpio_data,
+ 	.keypad		= &ldp_kp_twl4030_data,
+ };
+@@ -530,6 +560,8 @@ static void __init omap_ldp_init(void)
+ 	omap_serial_init();
+ 	usb_musb_init();
+ 	twl4030_mmc_init(mmc);
++	/* link regulators to MMC adapters */
++	ldp_vmmc1_supply.dev = mmc[0].dev;
+ }
+ 
+ static void __init omap_ldp_map_io(void)
+-- 
+1.6.2
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/0001-implement-TIF_RESTORE_SIGMASK-support-and-enable-the.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/0001-implement-TIF_RESTORE_SIGMASK-support-and-enable-the.patch
new file mode 100644
index 0000000000..7852f0afdb
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/0001-implement-TIF_RESTORE_SIGMASK-support-and-enable-the.patch
@@ -0,0 +1,287 @@
+From 8a7643b09856f4f661403dcedbe0455b3cbeeea9 Mon Sep 17 00:00:00 2001
+From: Steven Newbury <s_j_newbury@yahoo.co.uk>
+Date: Fri, 22 May 2009 14:25:40 +0200
+Subject: [PATCH] implement TIF_RESTORE_SIGMASK support and enable the related
+ syscalls:
+
+pselect6
+ppoll
+epoll_pwait
+
+Based on http://www.spinics.net/lists/arm-kernel/msg38114.html
+---
+ arch/arm/include/asm/thread_info.h |    2 +
+ arch/arm/include/asm/unistd.h      |    7 ++-
+ arch/arm/kernel/calls.S            |    6 +-
+ arch/arm/kernel/signal.c           |   90 +++++++++++++++---------------------
+ 4 files changed, 46 insertions(+), 59 deletions(-)
+
+diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
+index 4f88482..2cf0917 100644
+--- a/arch/arm/include/asm/thread_info.h
++++ b/arch/arm/include/asm/thread_info.h
+@@ -136,6 +136,7 @@ extern void vfp_sync_state(struct thread_info *thread);
+ #define TIF_SIGPENDING		0
+ #define TIF_NEED_RESCHED	1
+ #define TIF_SYSCALL_TRACE	8
++#define TIF_RESTORE_SIGMASK	9       /* restore signal mask in do_signal */
+ #define TIF_POLLING_NRFLAG	16
+ #define TIF_USING_IWMMXT	17
+ #define TIF_MEMDIE		18
+@@ -144,6 +145,7 @@ extern void vfp_sync_state(struct thread_info *thread);
+ #define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
+ #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
+ #define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
++#define _TIF_RESTORE_SIGMASK	(1 << TIF_RESTORE_SIGMASK)
+ #define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
+ #define _TIF_USING_IWMMXT	(1 << TIF_USING_IWMMXT)
+ #define _TIF_FREEZE		(1 << TIF_FREEZE)
+diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
+index 94cc58e..cd1eaa0 100644
+--- a/arch/arm/include/asm/unistd.h
++++ b/arch/arm/include/asm/unistd.h
+@@ -360,8 +360,8 @@
+ #define __NR_readlinkat			(__NR_SYSCALL_BASE+332)
+ #define __NR_fchmodat			(__NR_SYSCALL_BASE+333)
+ #define __NR_faccessat			(__NR_SYSCALL_BASE+334)
+-					/* 335 for pselect6 */
+-					/* 336 for ppoll */
++#define __NR_pselect6			(__NR_SYSCALL_BASE+335)
++#define __NR_ppoll			(__NR_SYSCALL_BASE+336)
+ #define __NR_unshare			(__NR_SYSCALL_BASE+337)
+ #define __NR_set_robust_list		(__NR_SYSCALL_BASE+338)
+ #define __NR_get_robust_list		(__NR_SYSCALL_BASE+339)
+@@ -372,7 +372,7 @@
+ #define __NR_vmsplice			(__NR_SYSCALL_BASE+343)
+ #define __NR_move_pages			(__NR_SYSCALL_BASE+344)
+ #define __NR_getcpu			(__NR_SYSCALL_BASE+345)
+-					/* 346 for epoll_pwait */
++#define __NR_epoll_pwait		(__NR_SYSCALL_BASE+346)
+ #define __NR_kexec_load			(__NR_SYSCALL_BASE+347)
+ #define __NR_utimensat			(__NR_SYSCALL_BASE+348)
+ #define __NR_signalfd			(__NR_SYSCALL_BASE+349)
+@@ -430,6 +430,7 @@
+ #define __ARCH_WANT_SYS_SIGPENDING
+ #define __ARCH_WANT_SYS_SIGPROCMASK
+ #define __ARCH_WANT_SYS_RT_SIGACTION
++#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+ 
+ #if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT)
+ #define __ARCH_WANT_SYS_TIME
+diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
+index 1680e9e..534000d 100644
+--- a/arch/arm/kernel/calls.S
++++ b/arch/arm/kernel/calls.S
+@@ -344,8 +344,8 @@
+ 		CALL(sys_readlinkat)
+ 		CALL(sys_fchmodat)
+ 		CALL(sys_faccessat)
+-/* 335 */	CALL(sys_ni_syscall)		/* eventually pselect6 */
+-		CALL(sys_ni_syscall)		/* eventually ppoll */
++/* 335 */	CALL(sys_pselect6)
++		CALL(sys_ppoll)
+ 		CALL(sys_unshare)
+ 		CALL(sys_set_robust_list)
+ 		CALL(sys_get_robust_list)
+@@ -355,7 +355,7 @@
+ 		CALL(sys_vmsplice)
+ 		CALL(sys_move_pages)
+ /* 345 */	CALL(sys_getcpu)
+-		CALL(sys_ni_syscall)		/* eventually epoll_pwait */
++		CALL(sys_epoll_pwait)
+ 		CALL(sys_kexec_load)
+ 		CALL(sys_utimensat)
+ 		CALL(sys_signalfd)
+diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
+index 80b8b5c..7645048 100644
+--- a/arch/arm/kernel/signal.c
++++ b/arch/arm/kernel/signal.c
+@@ -47,57 +47,23 @@ const unsigned long sigreturn_codes[7] = {
+ 	MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN,
+ };
+ 
+-static int do_signal(sigset_t *oldset, struct pt_regs * regs, int syscall);
++static void do_signal(struct pt_regs * regs, int syscall);
+ 
+ /*
+  * atomically swap in the new signal mask, and wait for a signal.
+  */
+-asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask, struct pt_regs *regs)
++asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask)
+ {
+-	sigset_t saveset;
+-
+ 	mask &= _BLOCKABLE;
+ 	spin_lock_irq(&current->sighand->siglock);
+-	saveset = current->blocked;
++	current->saved_sigmask = current->blocked;
+ 	siginitset(&current->blocked, mask);
+ 	recalc_sigpending();
+ 	spin_unlock_irq(&current->sighand->siglock);
+-	regs->ARM_r0 = -EINTR;
+-
+-	while (1) {
+-		current->state = TASK_INTERRUPTIBLE;
+-		schedule();
+-		if (do_signal(&saveset, regs, 0))
+-			return regs->ARM_r0;
+-	}
+-}
+-
+-asmlinkage int
+-sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize, struct pt_regs *regs)
+-{
+-	sigset_t saveset, newset;
+-
+-	/* XXX: Don't preclude handling different sized sigset_t's. */
+-	if (sigsetsize != sizeof(sigset_t))
+-		return -EINVAL;
+-
+-	if (copy_from_user(&newset, unewset, sizeof(newset)))
+-		return -EFAULT;
+-	sigdelsetmask(&newset, ~_BLOCKABLE);
+-
+-	spin_lock_irq(&current->sighand->siglock);
+-	saveset = current->blocked;
+-	current->blocked = newset;
+-	recalc_sigpending();
+-	spin_unlock_irq(&current->sighand->siglock);
+-	regs->ARM_r0 = -EINTR;
+-
+-	while (1) {
+-		current->state = TASK_INTERRUPTIBLE;
+-		schedule();
+-		if (do_signal(&saveset, regs, 0))
+-			return regs->ARM_r0;
+-	}
++	current->state = TASK_INTERRUPTIBLE;
++	schedule();
++	set_thread_flag(TIF_RESTORE_SIGMASK);
++	return -ERESTARTNOHAND;
+ }
+ 
+ asmlinkage int 
+@@ -290,7 +256,7 @@ asmlinkage int sys_sigreturn(struct pt_regs *regs)
+ 
+ badframe:
+ 	force_sig(SIGSEGV, current);
+-	return 0;
++	return -EFAULT;
+ }
+ 
+ asmlinkage int sys_rt_sigreturn(struct pt_regs *regs)
+@@ -325,7 +291,7 @@ asmlinkage int sys_rt_sigreturn(struct pt_regs *regs)
+ 
+ badframe:
+ 	force_sig(SIGSEGV, current);
+-	return 0;
++	return -EFAULT;
+ }
+ 
+ static int
+@@ -541,7 +507,7 @@ static inline void restart_syscall(struct pt_regs *regs)
+ /*
+  * OK, we're invoking a handler
+  */	
+-static void
++static int
+ handle_signal(unsigned long sig, struct k_sigaction *ka,
+ 	      siginfo_t *info, sigset_t *oldset,
+ 	      struct pt_regs * regs, int syscall)
+@@ -592,7 +558,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
+ 
+ 	if (ret != 0) {
+ 		force_sigsegv(sig, tsk);
+-		return;
++		return ret;
+ 	}
+ 
+ 	/*
+@@ -606,6 +572,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
+ 	recalc_sigpending();
+ 	spin_unlock_irq(&tsk->sighand->siglock);
+ 
++	return ret;
+ }
+ 
+ /*
+@@ -617,11 +584,12 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
+  * the kernel can handle, and then we build all the user-level signal handling
+  * stack-frames in one go after that.
+  */
+-static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
++static void do_signal(struct pt_regs *regs, int syscall)
+ {
+ 	struct k_sigaction ka;
+ 	siginfo_t info;
+ 	int signr;
++	sigset_t *oldset;
+ 
+ 	/*
+ 	 * We want the common case to go fast, which
+@@ -630,18 +598,29 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
+ 	 * if so.
+ 	 */
+ 	if (!user_mode(regs))
+-		return 0;
++		return;
+ 
+ 	if (try_to_freeze())
+ 		goto no_signal;
+ 
+ 	single_step_clear(current);
+ 
++	if (test_thread_flag(TIF_RESTORE_SIGMASK))
++		oldset = &current->saved_sigmask;
++	else
++		oldset = &current->blocked;
++
+ 	signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+ 	if (signr > 0) {
+-		handle_signal(signr, &ka, &info, oldset, regs, syscall);
++		if (handle_signal(signr, &ka, &info, oldset, regs, syscall) == 0) {
++			/* a signal was successfully delivered; the saved
++			 * sigmask will have been stored in the signal frame,
++			 * and will be restored by sigreturn, so we can simply
++			 * clear the TIF_RESTORE_SIGMASK flag */
++			clear_thread_flag(TIF_RESTORE_SIGMASK);
++		}
+ 		single_step_set(current);
+-		return 1;
++		return;
+ 	}
+ 
+  no_signal:
+@@ -665,7 +644,7 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
+ 				usp = (u32 __user *)regs->ARM_sp;
+ 
+ 				/*
+-				 * Either we supports OABI only, or we have
++				 * Either we support OABI only, or we have
+ 				 * EABI with the OABI compat layer enabled.
+ 				 * In the later case we don't know if user
+ 				 * space is EABI or not, and if not we must
+@@ -695,12 +674,17 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
+ 		}
+ 	}
+ 	single_step_set(current);
+-	return 0;
++        /* if there's no signal to deliver, we just put the saved sigmask
++           back. */
++		if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
++			clear_thread_flag(TIF_RESTORE_SIGMASK);
++			sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
++		}
+ }
+ 
+ asmlinkage void
+ do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall)
+ {
+-	if (thread_flags & _TIF_SIGPENDING)
+-		do_signal(&current->blocked, regs, syscall);
++	if (thread_flags & (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK))
++		do_signal(regs, syscall);
+ }
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/0124-leds-gpio-broken-with-current-git.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/0124-leds-gpio-broken-with-current-git.patch
new file mode 100644
index 0000000000..dc6e190e89
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/0124-leds-gpio-broken-with-current-git.patch
@@ -0,0 +1,79 @@
+From c810e850d830330cf04225a4cff8e981e153f269 Mon Sep 17 00:00:00 2001
+From: David Brownell <david-b@pacbell.net>
+Date: Mon, 23 Feb 2009 14:08:14 -0800
+Subject: [PATCH 124/133] leds-gpio broken with current git?
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+On Monday 23 February 2009, David Brownell wrote:
+>
+> > Perhaps something broke with Tony's RC1 merge?
+> > The LEDs are broken for me as well.
+>
+> Still works for me.  Did you maybe not enable the twl4030
+> GPIO support in Kconfig?
+
+Oh, and if you did *not*, please give this patch a try.
+I've been meaning to test it.
+
+- Dave
+
+==============
+Sometimes it's awkward to make sure that the array in the
+platform_data handed to the leds-gpio driver has only valid
+data ... some leds may not be always available, and coping
+with that currently requires patching or rebuilding the array.
+
+This patch fixes that by making it be OK to pass an invalid
+GPIO (such as "-EINVAL") ... such table entries are skipped.
+---
+ drivers/leds/leds-gpio.c |   12 +++++++++++-
+ 1 files changed, 11 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
+index b13bd29..83737e6 100644
+--- a/drivers/leds/leds-gpio.c
++++ b/drivers/leds/leds-gpio.c
+@@ -90,13 +90,19 @@ static int gpio_led_probe(struct platform_device *pdev)
+ 		cur_led = &pdata->leds[i];
+ 		led_dat = &leds_data[i];
+ 
++		/* skip leds that aren't available */
++		led_dat->gpio = cur_led->gpio;
++		if (!gpio_is_valid(led_dat->gpio)) {
++			dev_dbg(&pdev->dev, "skipping %s\n", cur_led->name);
++			continue;
++		}
++
+ 		ret = gpio_request(cur_led->gpio, cur_led->name);
+ 		if (ret < 0)
+ 			goto err;
+ 
+ 		led_dat->cdev.name = cur_led->name;
+ 		led_dat->cdev.default_trigger = cur_led->default_trigger;
+-		led_dat->gpio = cur_led->gpio;
+ 		led_dat->can_sleep = gpio_cansleep(cur_led->gpio);
+ 		led_dat->active_low = cur_led->active_low;
+ 		if (pdata->gpio_blink_set) {
+@@ -124,6 +130,8 @@ static int gpio_led_probe(struct platform_device *pdev)
+ err:
+ 	if (i > 0) {
+ 		for (i = i - 1; i >= 0; i--) {
++			if (!gpio_is_valid(leds_data[i].gpio))
++				continue;
+ 			led_classdev_unregister(&leds_data[i].cdev);
+ 			cancel_work_sync(&leds_data[i].work);
+ 			gpio_free(leds_data[i].gpio);
+@@ -144,6 +152,8 @@ static int __devexit gpio_led_remove(struct platform_device *pdev)
+ 	leds_data = platform_get_drvdata(pdev);
+ 
+ 	for (i = 0; i < pdata->num_leds; i++) {
++		if (!gpio_is_valid(leds_data[i].gpio))
++			continue;
+ 		led_classdev_unregister(&leds_data[i].cdev);
+ 		cancel_work_sync(&leds_data[i].work);
+ 		gpio_free(leds_data[i].gpio);
+-- 
+1.6.0.4.790.gaa14a
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/ads7846-detection.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/ads7846-detection.patch
new file mode 100644
index 0000000000..25a1cb052c
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/ads7846-detection.patch
@@ -0,0 +1,41 @@
+diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c
+index 2ae5ab8..a68b0a6 100644
+--- a/drivers/input/touchscreen/ads7846.c
++++ b/drivers/input/touchscreen/ads7846.c
+@@ -1154,9 +1154,16 @@ static int __devinit ads7846_probe(struct spi_device *spi)
+ 	/* take a first sample, leaving nPENIRQ active and vREF off; avoid
+ 	 * the touchscreen, in case it's not connected.
+ 	 */
+-	(void) ads7846_read12_ser(&spi->dev,
++	err = ads7846_read12_ser(&spi->dev,
+ 			  READ_12BIT_SER(vaux) | ADS_PD10_ALL_ON);
+ 
++	/* if sample is all 0's or all 1's then there is no device on spi */	
++	if ( (err == 0x000) || (err == 0xfff)) {
++		dev_info(&spi->dev, "no device detected, test read result was 0x%08X\n", err);
++		err = -ENODEV;
++		goto err_free_irq;
++	}
++
+ 	err = sysfs_create_group(&spi->dev.kobj, &ads784x_attr_group);
+ 	if (err)
+ 		goto err_remove_hwmon;
+@@ -1174,7 +1181,7 @@ static int __devinit ads7846_probe(struct spi_device *spi)
+  err_free_irq:
+ 	free_irq(spi->irq, ts);
+  err_free_gpio:
+-	if (ts->gpio_pendown != -1)
++	if (!ts->get_pendown_state && ts->gpio_pendown != -1)
+ 		gpio_free(ts->gpio_pendown);
+  err_cleanup_filter:
+ 	if (ts->filter_cleanup)
+@@ -1201,7 +1208,7 @@ static int __devexit ads7846_remove(struct spi_device *spi)
+ 	/* suspend left the IRQ disabled */
+ 	enable_irq(ts->spi->irq);
+ 
+-	if (ts->gpio_pendown != -1)
++	if (!ts->get_pendown_state && ts->gpio_pendown != -1)
+ 		gpio_free(ts->gpio_pendown);
+ 
+ 	if (ts->filter_cleanup)
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/beagle-asoc.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/beagle-asoc.patch
new file mode 100644
index 0000000000..b2b920037e
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/beagle-asoc.patch
@@ -0,0 +1,35 @@
+diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
+index 4f7f040..ccd8973 100644
+--- a/sound/soc/omap/Kconfig
++++ b/sound/soc/omap/Kconfig
+@@ -55,3 +55,13 @@ config SND_OMAP_SOC_OMAP3_PANDORA
+ 	select SND_SOC_TWL4030
+ 	help
+ 	  Say Y if you want to add support for SoC audio on the OMAP3 Pandora.
++
++config SND_OMAP_SOC_OMAP3_BEAGLE
++	tristate "SoC Audio support for OMAP3 Beagle"
++	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP3_BEAGLE
++	select SND_OMAP_SOC_MCBSP
++	select SND_SOC_TWL4030
++	help
++	  Say Y if you want to add support for SoC audio on the Beagleboard.
++
++
+diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
+index 76fedd9..0c9e4ac 100644
+--- a/sound/soc/omap/Makefile
++++ b/sound/soc/omap/Makefile
+@@ -12,6 +12,7 @@ snd-soc-overo-objs := overo.o
+ snd-soc-omap2evm-objs := omap2evm.o
+ snd-soc-sdp3430-objs := sdp3430.o
+ snd-soc-omap3pandora-objs := omap3pandora.o
++snd-soc-omap3beagle-objs := omap3beagle.o
+ 
+ obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o
+ obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o
+@@ -19,3 +20,4 @@ obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o
+ obj-$(CONFIG_MACH_OMAP2EVM) += snd-soc-omap2evm.o
+ obj-$(CONFIG_SND_OMAP_SOC_SDP3430) += snd-soc-sdp3430.o
+ obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o
++obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/defconfig
new file mode 100644
index 0000000000..7bb7f39d9f
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/defconfig
@@ -0,0 +1,2741 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-omap1
+# Thu Jul 16 15:21:36 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+# CONFIG_OMAP_SMARTREFLEX is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_IOMMU=y
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_TICK_GPTIMER=12
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+CONFIG_MACH_OMAP3EVM=y
+CONFIG_MACH_OMAP3_BEAGLE=y
+CONFIG_MACH_OVERO=y
+# CONFIG_MACH_OMAP3_PANDORA is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+# CONFIG_ARM_ERRATUM_451034 is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_VERBOSE is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+# CONFIG_IPV6_PIMSM_V2 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_DEBUG=y
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_IDLETIMER=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=y
+
+#
+# DCCP Kernel Hacking
+#
+# CONFIG_IP_DCCP_DEBUG is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+CONFIG_TIPC=m
+# CONFIG_TIPC_ADVANCED is not set
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRNET=m
+CONFIG_IRCOMM=m
+CONFIG_IRDA_ULTRA=y
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+CONFIG_IRDA_DEBUG=y
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+
+#
+# Dongle support
+#
+CONFIG_DONGLE=y
+CONFIG_ESI_DONGLE=m
+CONFIG_ACTISYS_DONGLE=m
+CONFIG_TEKRAM_DONGLE=m
+CONFIG_TOIM3232_DONGLE=m
+CONFIG_LITELINK_DONGLE=m
+CONFIG_MA600_DONGLE=m
+CONFIG_GIRBIL_DONGLE=m
+CONFIG_MCP2120_DONGLE=m
+CONFIG_OLD_BELKIN_DONGLE=m
+# CONFIG_ACT200L_DONGLE is not set
+CONFIG_KINGSUN_DONGLE=m
+CONFIG_KSDAZZLE_DONGLE=m
+CONFIG_KS959_DONGLE=m
+
+#
+# FIR device drivers
+#
+CONFIG_USB_IRDA=m
+CONFIG_SIGMATEL_FIR=m
+CONFIG_MCS_FIR=m
+# CONFIG_OMAP_IR is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+CONFIG_BT_HCIBTSDIO=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+CONFIG_BT_HCIBFUSB=y
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+# CONFIG_PHONET is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+CONFIG_LIB80211_CRYPT_WEP=y
+CONFIG_LIB80211_CRYPT_CCMP=y
+CONFIG_LIB80211_CRYPT_TKIP=y
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_WIMAX=m
+CONFIG_WIMAX_DEBUG_LEVEL=8
+# CONFIG_RFKILL is not set
+CONFIG_NET_9P=m
+# CONFIG_NET_9P_DEBUG is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+CONFIG_EEPROM_93CX6=y
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=y
+CONFIG_LIBERTAS_USB=y
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=y
+CONFIG_USB_NET_RNDIS_WLAN=y
+CONFIG_RTL8187=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_P54_COMMON=y
+CONFIG_P54_USB=y
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_B43=y
+CONFIG_B43_LEDS=y
+# CONFIG_B43_DEBUG is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_ZD1211RW=y
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_RT2X00=y
+CONFIG_RT2500USB=y
+CONFIG_RT73USB=y
+CONFIG_RT2X00_LIB_USB=y
+CONFIG_RT2X00_LIB=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+
+#
+# WiMAX Wireless Broadband devices
+#
+# CONFIG_WIMAX_I2400M_USB is not set
+# CONFIG_WIMAX_I2400M_SDIO is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_GL620A=y
+CONFIG_USB_NET_NET1080=y
+CONFIG_USB_NET_PLUSB=y
+CONFIG_USB_NET_MCS7830=y
+CONFIG_USB_NET_RNDIS_HOST=y
+CONFIG_USB_NET_CDC_SUBSET=y
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=y
+# CONFIG_WAN is not set
+CONFIG_ATM_DRIVERS=y
+# CONFIG_ATM_DUMMY is not set
+# CONFIG_ATM_TCP is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOATM is not set
+CONFIG_PPPOL2TP=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_TWL4030_PWRBUTTON=n
+CONFIG_INPUT_UINPUT=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_OMAP24XX is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB=y
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_POWER is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_DMA_SG=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEO_IR=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=m
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_VIVI=m
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+CONFIG_VIDEO_OMAP3=m
+CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=m
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_USBVIDEO=m
+CONFIG_USB_VICAM=m
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_KONICAWC=m
+CONFIG_USB_QUICKCAM_MESSENGER=m
+CONFIG_USB_ET61X251=m
+CONFIG_VIDEO_OVCAMCHIP=m
+CONFIG_USB_W9968CF=m
+CONFIG_USB_OV511=m
+CONFIG_USB_SE401=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_STV680=m
+CONFIG_USB_ZC0301=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_SIANO_SMS1XXX=m
+CONFIG_DVB_SIANO_SMS1XXX_SMS_IDS=y
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_DRX397XD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3304=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_LGS8GL5=m
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+CONFIG_DVB_AF9013=m
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_VRAM_SIZE=14
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+CONFIG_OMAP2_DSS_VENC=y
+# CONFIG_OMAP2_DSS_SDI is not set
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_USE_DSI_PLL=y
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_GENERIC=y
+CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C=m
+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_PANEL_N800 is not set
+# CONFIG_CTRL_BLIZZARD is not set
+CONFIG_FB_OMAP2=y
+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
+CONFIG_FB_OMAP2_NUM_FBS=3
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+# CONFIG_SND_OMAP_SOC_OVERO is not set
+CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TWL4030=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_TOPSEED=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_OMAP_EHCI_PHY_MODE=y
+# CONFIG_OMAP_EHCI_TLL_MODE is not set
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_OXU210HP_HCD=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_U132_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+CONFIG_USB_BERRY_CHARGE=m
+CONFIG_USB_LED=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_PHIDGET=m
+CONFIG_USB_PHIDGETKIT=m
+CONFIG_USB_PHIDGETMOTORCONTROL=m
+CONFIG_USB_PHIDGETSERVO=m
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_FTDI_ELAN=m
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SISUSBVGA_CON=y
+CONFIG_USB_LD=m
+CONFIG_USB_TRANCEVIBRATOR=m
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_VST=m
+CONFIG_USB_ATM=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_CXACRU=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_XUSBATM=m
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ZERO_HNPTEST=y
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_GPIO_VBUS=y
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+CONFIG_LEDS_OMAP=y
+# CONFIG_LEDS_OMAP_PWM is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_TWL4030=y
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_MEILHAUS is not set
+# CONFIG_USB_IP_COMMON is not set
+CONFIG_W35UND=m
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+CONFIG_USB_ATMEL=m
+# CONFIG_AGNX is not set
+CONFIG_OTUS=m
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=m
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+# CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION is not set
+# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
+CONFIG_ANDROID_TIMED_GPIO=m
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=m
+# CONFIG_EXT4DEV_COMPAT is not set
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=m
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=m
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+# CONFIG_REISERFS_FS_POSIX_ACL is not set
+# CONFIG_REISERFS_FS_SECURITY is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_FS_O2CB=m
+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+CONFIG_OCFS2_FS_STATS=y
+CONFIG_OCFS2_DEBUG_MASKLOG=y
+# CONFIG_OCFS2_DEBUG_FS is not set
+# CONFIG_OCFS2_FS_POSIX_ACL is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_ADFS_FS=m
+# CONFIG_ADFS_FS_RW is not set
+CONFIG_AFFS_FS=m
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_BEFS_FS=m
+# CONFIG_BEFS_DEBUG is not set
+CONFIG_BFS_FS=m
+CONFIG_EFS_FS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_VXFS_FS=m
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
+CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_ROMFS_FS=m
+CONFIG_SYSV_FS=m
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS=y
+CONFIG_CIFS_STATS2=y
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+CONFIG_CIFS_EXPERIMENTAL=y
+# CONFIG_CIFS_DFS_UPCALL is not set
+CONFIG_NCP_FS=m
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+CONFIG_9P_FS=m
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LDM_DEBUG=y
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=n
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_FIPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/ehci.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/ehci.patch
new file mode 100644
index 0000000000..5a8c84471b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/ehci.patch
@@ -0,0 +1,131 @@
+Index: git/arch/arm/mach-omap2/board-omap3beagle.c
+===================================================================
+--- git.orig/arch/arm/mach-omap2/board-omap3beagle.c
++++ git/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -154,6 +154,7 @@ static int beagle_twl_gpio_setup(struct
+ 	 * power switch and overcurrent detect
+ 	 */
+ 
++#if 0 /* TODO: This needs to be modified to not rely on u-boot */
+ 	gpio_request(gpio + 1, "EHCI_nOC");
+ 	gpio_direction_input(gpio + 1);
+ 
+@@ -163,7 +164,7 @@ static int beagle_twl_gpio_setup(struct
+ 
+ 	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+ 	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+-
++#endif
+ 	return 0;
+ }
+ 
+Index: git/arch/arm/mach-omap2/usb-ehci.c
+===================================================================
+--- git.orig/arch/arm/mach-omap2/usb-ehci.c
++++ git/arch/arm/mach-omap2/usb-ehci.c
+@@ -147,9 +147,11 @@ static void setup_ehci_io_mux(void)
+ 
+ void __init usb_ehci_init(void)
+ {
++#if 0 /* TODO: Setup Pin IO MUX for EHCI - moved this temporarily to U-boot */
+ 	/* Setup Pin IO MUX for EHCI */
+ 	if (cpu_is_omap34xx())
+ 		setup_ehci_io_mux();
++#endif
+ 
+ 	if (platform_device_register(&ehci_device) < 0) {
+ 		printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
+Index: git/drivers/usb/host/ehci-omap.c
+===================================================================
+--- git.orig/drivers/usb/host/ehci-omap.c
++++ git/drivers/usb/host/ehci-omap.c
+@@ -48,16 +48,25 @@
+  *		to get the PHY state machine in working state
+  */
+ #define EXTERNAL_PHY_RESET
++#ifdef CONFIG_MACH_OMAP3_BEAGLE
++#define        EXT_PHY_RESET_GPIO_PORT2        (147)
++#else
+ #define	EXT_PHY_RESET_GPIO_PORT1	(57)
+ #define	EXT_PHY_RESET_GPIO_PORT2	(61)
++#endif
+ #define	EXT_PHY_RESET_DELAY		(10)
+ 
++#define PHY_STP_PULLUP_ENABLE           (0x10)
++#define PHY_STP_PULLUP_DISABLE          (0x90)
++
+ /* ISSUE2:
+  * USBHOST supports External charge pump PHYs only
+  * Use the VBUS from Port1 to power VBUS of Port2 externally
+  * So use Port2 as the working ULPI port
+  */
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ #define VBUS_INTERNAL_CHARGEPUMP_HACK
++#endif
+ 
+ #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
+ 
+@@ -225,14 +234,43 @@ static int omap_start_ehc(struct platfor
+ 
+ #ifdef EXTERNAL_PHY_RESET
+ 	/* Refer: ISSUE1 */
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT1, "USB1 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT1, 0);
++#endif
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT2, "USB2 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT2, 0);
++	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 0);
+ 	/* Hold the PHY in RESET for enough time till DIR is high */
+ 	udelay(EXT_PHY_RESET_DELAY);
+ #endif
+ 
++        /*
++         * The PHY register 0x7 - Interface Control register is
++         * configured to disable the integrated STP pull-up resistor
++         * used for interface protection.
++        *
++        * May not need to be here.
++         */
++        omap_writel((0x7 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* interface reg */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (PHY_STP_PULLUP_DISABLE),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
++        /* Force PHY to HS */
++        omap_writel((0x4 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* function ctrl */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (0x40),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
+ 	/* Configure TLL for 60Mhz clk for ULPI */
+ 	ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
+ 	if (IS_ERR(ehci_clocks->usbtll_fck_clk))
+@@ -307,7 +345,9 @@ static int omap_start_ehc(struct platfor
+ 	 * Hold the PHY in RESET for enough time till PHY is settled and ready
+ 	 */
+ 	udelay(EXT_PHY_RESET_DELAY);
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT1, 1);
++#endif
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 1);
+ #endif
+ 
+@@ -393,7 +433,9 @@ static void omap_stop_ehc(struct platfor
+ 
+ 
+ #ifdef EXTERNAL_PHY_RESET
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT1);
++#endif
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT2);
+ #endif
+ 
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/logo_linux_clut224.ppm b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/logo_linux_clut224.ppm
new file mode 100644
index 0000000000..d29fc1c544
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/logo_linux_clut224.ppm
@@ -0,0 +1,73147 @@
+P3
+# CREATOR: GIMP PNM Filter Version 1.1
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diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/tincantools-puppy.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/tincantools-puppy.diff
new file mode 100644
index 0000000000..c7856731e5
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/beagleboard/tincantools-puppy.diff
@@ -0,0 +1,66 @@
+--- /tmp/board-omap3beagle.c	2009-07-01 01:06:44.000000000 +0200
++++ git/arch/arm/mach-omap2/board-omap3beagle.c	2009-07-01 01:06:50.000000000 +0200
+@@ -125,6 +125,13 @@
+ 		.wires		= 8,
+ 		.gpio_wp	= 29,
+ 	},
++	{
++		.mmc		= 2,
++		.wires		= 4,
++		.gpio_wp	= 141,
++		.gpio_cd	= 162,
++        .transceiver    = true,
++	},
+ 	{}	/* Terminator */
+ };
+ 
+@@ -132,6 +139,11 @@
+ 	.supply			= "vmmc",
+ };
+ 
++static struct regulator_consumer_supply beagle_vmmc2_supply = {
++    .supply         = "vmmc",
++};
++
++
+ static struct regulator_consumer_supply beagle_vsim_supply = {
+ 	.supply			= "vmmc_aux",
+ };
+@@ -148,6 +160,7 @@
+ 
+ 	/* link regulators to MMC adapters */
+ 	beagle_vmmc1_supply.dev = mmc[0].dev;
++	beagle_vmmc2_supply.dev = mmc[1].dev;
+ 	beagle_vsim_supply.dev = mmc[0].dev;
+ 
+ 	/* REVISIT: need ehci-omap hooks for external VBUS
+@@ -209,6 +222,21 @@
+ 	.consumer_supplies	= &beagle_vmmc1_supply,
+ };
+ 
++/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */
++static struct regulator_init_data beagle_vmmc2 = {
++	.constraints = {
++		.min_uV			= 2700000,
++		.max_uV			= 3150000,
++		.valid_modes_mask	= REGULATOR_MODE_NORMAL
++					| REGULATOR_MODE_STANDBY,
++		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE
++					| REGULATOR_CHANGE_MODE
++					| REGULATOR_CHANGE_STATUS,
++	},
++	.num_consumer_supplies	= 1,
++	.consumer_supplies	= &beagle_vmmc2_supply,
++};
++
+ /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+ static struct regulator_init_data beagle_vsim = {
+ 	.constraints = {
+@@ -284,6 +312,7 @@
+ 	.gpio		= &beagle_gpio_data,
+ 	.power		= &beagle_power_data,
+ 	.vmmc1		= &beagle_vmmc1,
++	.vmmc2		= &beagle_vmmc2,
+ 	.vsim		= &beagle_vsim,
+ 	.vdac		= &beagle_vdac,
+ 	.vpll2		= &beagle_vpll2,
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/cache-display-fix.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/cache-display-fix.patch
new file mode 100644
index 0000000000..019fd5acf1
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/cache-display-fix.patch
@@ -0,0 +1,238 @@
+On Tue, 2008-07-01 at 06:23 +0100, Dirk Behme wrote:
+> Catalin Marinas wrote:
+> > But, anyway, if you want a patch, Harry is updating it to a recent
+> > kernel.
+> 
+> Any news on this? I think there are some people wanting a patch ;)
+
+See below for a preliminary patch updated to 2.6.26-rc8. Note that I
+don't plan to submit it in its current form but clean it up a bit first.
+
+
+Show the cache type of ARMv7 CPUs
+
+From: Catalin Marinas <catalin.marinas@arm.com>
+
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+---
+
+ arch/arm/kernel/setup.c  |  137 +++++++++++++++++++++++++++++++++++++++++++++-
+ include/asm-arm/system.h |   18 ++++++
+ 2 files changed, 153 insertions(+), 2 deletions(-)
+
+
+diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
+index 5ae0eb2..0cd238d 100644
+--- a/arch/arm/kernel/setup.c
++++ b/arch/arm/kernel/setup.c
+@@ -256,6 +256,24 @@ static const char *proc_arch[] = {
+ 	"?(17)",
+ };
+ 
++static const char *v7_cache_policy[4] = {
++	"reserved",
++	"AVIVT",
++	"VIPT",
++	"PIPT",
++};
++
++static const char *v7_cache_type[8] = {
++	"none",
++	"instruction only",
++	"data only",
++	"separate instruction and data",
++	"unified",
++	"unknown type",
++	"unknown type",
++	"unknown type",
++};
++
+ #define CACHE_TYPE(x)	(((x) >> 25) & 15)
+ #define CACHE_S(x)	((x) & (1 << 24))
+ #define CACHE_DSIZE(x)	(((x) >> 12) & 4095)	/* only if S=1 */
+@@ -266,6 +284,22 @@ static const char *proc_arch[] = {
+ #define CACHE_M(y)	((y) & (1 << 2))
+ #define CACHE_LINE(y)	((y) & 3)
+ 
++#define CACHE_TYPE_V7(x)	(((x) >> 14) & 3)
++#define CACHE_UNIFIED(x)	((((x) >> 27) & 7)+1)
++#define CACHE_COHERENT(x)	((((x) >> 24) & 7)+1)
++
++#define CACHE_ID_LEVEL_MASK	7
++#define CACHE_ID_LEVEL_BITS	3
++
++#define CACHE_LINE_V7(v)	((1 << (((v) & 7)+4)))
++#define CACHE_ASSOC_V7(v)	((((v) >> 3) & ((1<<10)-1))+1)
++#define CACHE_SETS_V7(v)	((((v) >> 13) & ((1<<15)-1))+1)
++#define CACHE_SIZE_V7(v)	(CACHE_LINE_V7(v)*CACHE_ASSOC_V7(v)*CACHE_SETS_V7(v))
++#define CACHE_WA_V7(v)		(((v) & (1<<28)) != 0)
++#define CACHE_RA_V7(v)		(((v) & (1<<29)) != 0)
++#define CACHE_WB_V7(v)		(((v) & (1<<30)) != 0)
++#define CACHE_WT_V7(v)		(((v) & (1<<31)) != 0)
++
+ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
+ {
+ 	unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
+@@ -279,11 +313,57 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
+ 			CACHE_LINE(cache)));
+ }
+ 
++static void dump_v7_cache(const char *type, int cpu, unsigned int level)
++{
++	unsigned int cachesize;
++                    
++	write_extended_cpuid(2,0,0,0,level);  /* Set the cache size selection register */
++	write_extended_cpuid(0,7,5,4,0);      /* Prefetch flush to wait for above */
++	cachesize = read_extended_cpuid(1,0,0,0);
++
++	printk("CPU%u: %s cache: %d bytes, associativity %d, %d byte lines, %d sets,\n      supports%s%s%s%s\n",
++	       cpu, type,
++	       CACHE_SIZE_V7(cachesize),CACHE_ASSOC_V7(cachesize),
++	       CACHE_LINE_V7(cachesize),CACHE_SETS_V7(cachesize),
++	       CACHE_WA_V7(cachesize) ? " WA" : "",
++	       CACHE_RA_V7(cachesize) ? " RA" : "",
++	       CACHE_WB_V7(cachesize) ? " WB" : "",
++	       CACHE_WT_V7(cachesize) ? " WT" : "");
++}
++
+ static void __init dump_cpu_info(int cpu)
+ {
+ 	unsigned int info = read_cpuid(CPUID_CACHETYPE);
+ 
+-	if (info != processor_id) {
++	if (info != processor_id && (info & (1 << 31))) {
++		/* ARMv7 style of cache info register */
++		unsigned int id = read_extended_cpuid(1,0,0,1);
++		unsigned int level = 0;
++		printk("CPU%u: L1 I %s cache. Caches unified at level %u, coherent at level %u\n",
++		       cpu,
++		       v7_cache_policy[CACHE_TYPE_V7(info)],
++		       CACHE_UNIFIED(id),
++		       CACHE_COHERENT(id));
++
++		while (id & CACHE_ID_LEVEL_MASK) {
++			printk("CPU%u: Level %u cache is %s\n",
++			       cpu, (level >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]);
++
++			if (id & 1) {
++				/* Dump I at this level */
++				dump_v7_cache("I", cpu, level | 1);
++			}
++
++			if (id & (4 | 2)) {
++				/* Dump D or unified at this level */
++				dump_v7_cache((id & 4) ? "unified" : "D", cpu, level);
++			}
++
++			/* Next level out */
++			level += 2;
++			id >>= CACHE_ID_LEVEL_BITS;
++		}
++	} else if (info != processor_id) {
+ 		printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
+ 		       cache_types[CACHE_TYPE(info)]);
+ 		if (CACHE_S(info)) {
+@@ -916,6 +996,30 @@ c_show_cache(struct seq_file *m, const char *type, unsigned int cache)
+ 			    CACHE_LINE(cache)));
+ }
+ 
++static void c_show_v7_cache(struct seq_file *m, const char *type, unsigned int levelselect)
++{
++	unsigned int cachesize;
++	unsigned int level = (levelselect >> 1) + 1;
++                    
++	write_extended_cpuid(2,0,0,0,levelselect);  /* Set the cache size selection register */
++	write_extended_cpuid(0,7,5,4,0);      /* Prefetch flush to wait for above */
++	cachesize = read_extended_cpuid(1,0,0,0);
++
++	seq_printf(m, "L%u %s size\t\t: %d bytes\n"
++		   "L%u %s assoc\t\t: %d\n"
++		   "L%u %s line length\t: %d\n"
++		   "L%u %s sets\t\t: %d\n"
++		   "L%u %s supports\t\t:%s%s%s%s\n",
++		   level, type, CACHE_SIZE_V7(cachesize),
++		   level, type, CACHE_ASSOC_V7(cachesize),
++		   level, type, CACHE_LINE_V7(cachesize),
++		   level, type, CACHE_SETS_V7(cachesize),
++		   level, type, CACHE_WA_V7(cachesize) ? " WA" : "",
++		   CACHE_RA_V7(cachesize) ? " RA" : "",
++		   CACHE_WB_V7(cachesize) ? " WB" : "",
++		   CACHE_WT_V7(cachesize) ? " WT" : "");
++}
++
+ static int c_show(struct seq_file *m, void *v)
+ {
+ 	int i;
+@@ -971,7 +1075,36 @@ static int c_show(struct seq_file *m, void *v)
+ 
+ 	{
+ 		unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
+-		if (cache_info != processor_id) {
++		if (cache_info != processor_id && (cache_info & (1<<31))) {
++			/* V7 style of cache info register */
++			unsigned int id = read_extended_cpuid(1,0,0,1);
++			unsigned int levelselect = 0;
++			seq_printf(m, "L1 I cache\t:%s\n"
++				   "Cache unification level\t: %u\n"
++				   "Cache coherency level\t: %u\n",
++				   v7_cache_policy[CACHE_TYPE_V7(cache_info)],
++				   CACHE_UNIFIED(id),
++				   CACHE_COHERENT(id));
++
++			while (id & CACHE_ID_LEVEL_MASK) {
++				seq_printf(m, "Level %u cache\t\t: %s\n",
++					   (levelselect >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]);
++
++				if (id & 1) {
++					/* Dump I at this level */
++					c_show_v7_cache(m, "I", levelselect | 1);
++				}
++
++				if (id & (4 | 2)) {
++					/* Dump D or unified at this level */
++					c_show_v7_cache(m, (id & 4) ? "cache" : "D", levelselect);
++				}
++
++				/* Next level out */
++				levelselect += 2;
++				id >>= CACHE_ID_LEVEL_BITS;
++			}
++		} else if (cache_info != processor_id) {
+ 			seq_printf(m, "Cache type\t: %s\n"
+ 				      "Cache clean\t: %s\n"
+ 				      "Cache lockdown\t: %s\n"
+diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
+index 514af79..704738e 100644
+--- a/arch/arm/include/asm/system.h
++++ b/arch/arm/include/asm/system.h
+@@ -74,6 +74,24 @@
+ 		    : "cc");						\
+ 		__val;							\
+ 	})
++#define read_extended_cpuid(op1,op2,op3,op4)		\
++	({								\
++		unsigned int __val;					\
++		asm("mrc p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4)	\
++		    : "=r" (__val)					\
++		    :							\
++		    : "cc");						\
++		__val;							\
++	})
++
++#define write_extended_cpuid(op1,op2,op3,op4,v)		\
++	({								\
++		unsigned int __val = v;					\
++		asm("mcr p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4)	\
++		    :							\
++		    : "r" (__val)					\
++		    : "cc");						\
++	})
+ #else
+ extern unsigned int processor_id;
+ #define read_cpuid(reg) (processor_id)
+
+
+-- 
+Catalin
+
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch
new file mode 100644
index 0000000000..ac26554845
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch
@@ -0,0 +1,39 @@
+From 26abf45ac80be4c54a63fecf1c3c1e1efb416e0a Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 1 Apr 2009 18:27:09 +0300
+Subject: [PATCH 01/69] Revert "gro: Fix legacy path napi_complete crash"
+
+This reverts commit 303c6a0251852ecbdc5c15e466dcaff5971f7517.
+
+Fixes USB network problems
+---
+ net/core/dev.c |    5 ++---
+ 1 files changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/net/core/dev.c b/net/core/dev.c
+index e3fe5c7..c1e9dc0 100644
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -2588,9 +2588,9 @@ static int process_backlog(struct napi_struct *napi, int quota)
+ 		local_irq_disable();
+ 		skb = __skb_dequeue(&queue->input_pkt_queue);
+ 		if (!skb) {
++			__napi_complete(napi);
+ 			local_irq_enable();
+-			napi_complete(napi);
+-			goto out;
++			break;
+ 		}
+ 		local_irq_enable();
+ 
+@@ -2599,7 +2599,6 @@ static int process_backlog(struct napi_struct *napi, int quota)
+ 
+ 	napi_gro_flush(napi);
+ 
+-out:
+ 	return work;
+ }
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch
new file mode 100644
index 0000000000..5c86e6a654
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch
@@ -0,0 +1,1316 @@
+From 02243f13eec816e11d16676a131bc04b8a0666ab Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 11 Feb 2009 16:33:02 +0200
+Subject: [PATCH 02/69] OMAPFB: move omapfb.h to include/linux/
+
+This is needed so that omapfb.h is automatically exported to user space.
+
+omapfb.h should be cleaned up later. Some stuff can probably be moved
+to omapfb's private include file.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/mach-omap1/board-nokia770.c     |    2 +-
+ arch/arm/mach-omap2/board-n800.c         |    2 +-
+ arch/arm/mach-omap2/io.c                 |    2 +-
+ arch/arm/plat-omap/fb.c                  |    2 +-
+ arch/arm/plat-omap/include/mach/omapfb.h |  398 ------------------------------
+ drivers/video/omap/blizzard.c            |    2 +-
+ drivers/video/omap/dispc.c               |    2 +-
+ drivers/video/omap/hwa742.c              |    2 +-
+ drivers/video/omap/lcd_2430sdp.c         |    2 +-
+ drivers/video/omap/lcd_ams_delta.c       |    2 +-
+ drivers/video/omap/lcd_apollon.c         |    2 +-
+ drivers/video/omap/lcd_h3.c              |    2 +-
+ drivers/video/omap/lcd_h4.c              |    3 +-
+ drivers/video/omap/lcd_inn1510.c         |    2 +-
+ drivers/video/omap/lcd_inn1610.c         |    2 +-
+ drivers/video/omap/lcd_ldp.c             |    2 +-
+ drivers/video/omap/lcd_mipid.c           |    2 +-
+ drivers/video/omap/lcd_omap2evm.c        |    2 +-
+ drivers/video/omap/lcd_omap3beagle.c     |    2 +-
+ drivers/video/omap/lcd_omap3evm.c        |    2 +-
+ drivers/video/omap/lcd_osk.c             |    2 +-
+ drivers/video/omap/lcd_overo.c           |    2 +-
+ drivers/video/omap/lcd_p2.c              |    2 +-
+ drivers/video/omap/lcd_palmte.c          |    2 +-
+ drivers/video/omap/lcd_palmtt.c          |    2 +-
+ drivers/video/omap/lcd_palmz71.c         |    3 +-
+ drivers/video/omap/lcdc.c                |    2 +-
+ drivers/video/omap/omapfb_main.c         |    2 +-
+ drivers/video/omap/rfbi.c                |    3 +-
+ drivers/video/omap/sossi.c               |    2 +-
+ include/linux/omapfb.h                   |  398 ++++++++++++++++++++++++++++++
+ 31 files changed, 427 insertions(+), 430 deletions(-)
+ delete mode 100644 arch/arm/plat-omap/include/mach/omapfb.h
+ create mode 100644 include/linux/omapfb.h
+
+diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
+index 8780ca6..ca4680a 100644
+--- a/arch/arm/mach-omap1/board-nokia770.c
++++ b/arch/arm/mach-omap1/board-nokia770.c
+@@ -18,6 +18,7 @@
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
+ #include <linux/workqueue.h>
++#include <linux/omapfb.h>
+ #include <linux/delay.h>
+ 
+ #include <mach/hardware.h>
+@@ -32,7 +33,6 @@
+ #include <mach/keypad.h>
+ #include <mach/common.h>
+ #include <mach/dsp_common.h>
+-#include <mach/omapfb.h>
+ #include <mach/lcd_mipid.h>
+ #include <mach/mmc.h>
+ #include <mach/usb.h>
+diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
+index cb32b61..f6f6571 100644
+--- a/arch/arm/mach-omap2/board-n800.c
++++ b/arch/arm/mach-omap2/board-n800.c
+@@ -27,6 +27,7 @@
+ #include <linux/i2c/lm8323.h>
+ #include <linux/i2c/menelaus.h>
+ #include <linux/i2c/lp5521.h>
++#include <linux/omapfb.h>
+ #include <mach/hardware.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -39,7 +40,6 @@
+ #include <mach/lcd_mipid.h>
+ #include <mach/clock.h>
+ #include <mach/gpio-switch.h>
+-#include <mach/omapfb.h>
+ #include <mach/blizzard.h>
+ 
+ #include <../drivers/cbus/tahvo.h>
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index adbe21f..a04e3ee 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -18,13 +18,13 @@
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
++#include <linux/omapfb.h>
+ #include <linux/io.h>
+ 
+ #include <asm/tlb.h>
+ 
+ #include <asm/mach/map.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <mach/sram.h>
+ #include <mach/sdrc.h>
+ #include <mach/gpmc.h>
+diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
+index 3746222..40615a6 100644
+--- a/arch/arm/plat-omap/fb.c
++++ b/arch/arm/plat-omap/fb.c
+@@ -28,13 +28,13 @@
+ #include <linux/platform_device.h>
+ #include <linux/bootmem.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/hardware.h>
+ #include <asm/mach/map.h>
+ 
+ #include <mach/board.h>
+ #include <mach/sram.h>
+-#include <mach/omapfb.h>
+ 
+ #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
+ 
+diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
+deleted file mode 100644
+index b226bdf..0000000
+--- a/arch/arm/plat-omap/include/mach/omapfb.h
++++ /dev/null
+@@ -1,398 +0,0 @@
+-/*
+- * File: arch/arm/plat-omap/include/mach/omapfb.h
+- *
+- * Framebuffer driver for TI OMAP boards
+- *
+- * Copyright (C) 2004 Nokia Corporation
+- * Author: Imre Deak <imre.deak@nokia.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+- * General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License along
+- * with this program; if not, write to the Free Software Foundation, Inc.,
+- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+- */
+-
+-#ifndef __OMAPFB_H
+-#define __OMAPFB_H
+-
+-#include <asm/ioctl.h>
+-#include <asm/types.h>
+-
+-/* IOCTL commands. */
+-
+-#define OMAP_IOW(num, dtype)	_IOW('O', num, dtype)
+-#define OMAP_IOR(num, dtype)	_IOR('O', num, dtype)
+-#define OMAP_IOWR(num, dtype)	_IOWR('O', num, dtype)
+-#define OMAP_IO(num)		_IO('O', num)
+-
+-#define OMAPFB_MIRROR		OMAP_IOW(31, int)
+-#define OMAPFB_SYNC_GFX		OMAP_IO(37)
+-#define OMAPFB_VSYNC		OMAP_IO(38)
+-#define OMAPFB_SET_UPDATE_MODE	OMAP_IOW(40, int)
+-#define OMAPFB_GET_CAPS		OMAP_IOR(42, struct omapfb_caps)
+-#define OMAPFB_GET_UPDATE_MODE	OMAP_IOW(43, int)
+-#define OMAPFB_LCD_TEST		OMAP_IOW(45, int)
+-#define OMAPFB_CTRL_TEST	OMAP_IOW(46, int)
+-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
+-#define OMAPFB_SET_COLOR_KEY	OMAP_IOW(50, struct omapfb_color_key)
+-#define OMAPFB_GET_COLOR_KEY	OMAP_IOW(51, struct omapfb_color_key)
+-#define OMAPFB_SETUP_PLANE	OMAP_IOW(52, struct omapfb_plane_info)
+-#define OMAPFB_QUERY_PLANE	OMAP_IOW(53, struct omapfb_plane_info)
+-#define OMAPFB_UPDATE_WINDOW	OMAP_IOW(54, struct omapfb_update_window)
+-#define OMAPFB_SETUP_MEM	OMAP_IOW(55, struct omapfb_mem_info)
+-#define OMAPFB_QUERY_MEM	OMAP_IOW(56, struct omapfb_mem_info)
+-
+-#define OMAPFB_CAPS_GENERIC_MASK	0x00000fff
+-#define OMAPFB_CAPS_LCDC_MASK		0x00fff000
+-#define OMAPFB_CAPS_PANEL_MASK		0xff000000
+-
+-#define OMAPFB_CAPS_MANUAL_UPDATE	0x00001000
+-#define OMAPFB_CAPS_TEARSYNC		0x00002000
+-#define OMAPFB_CAPS_PLANE_RELOCATE_MEM	0x00004000
+-#define OMAPFB_CAPS_PLANE_SCALE		0x00008000
+-#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE	0x00010000
+-#define OMAPFB_CAPS_WINDOW_SCALE	0x00020000
+-#define OMAPFB_CAPS_WINDOW_OVERLAY	0x00040000
+-#define OMAPFB_CAPS_WINDOW_ROTATE	0x00080000
+-#define OMAPFB_CAPS_SET_BACKLIGHT	0x01000000
+-
+-/* Values from DSP must map to lower 16-bits */
+-#define OMAPFB_FORMAT_MASK		0x00ff
+-#define OMAPFB_FORMAT_FLAG_DOUBLE	0x0100
+-#define OMAPFB_FORMAT_FLAG_TEARSYNC	0x0200
+-#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC	0x0400
+-#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY	0x0800
+-#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY	0x1000
+-
+-#define OMAPFB_EVENT_READY	1
+-#define OMAPFB_EVENT_DISABLED	2
+-
+-#define OMAPFB_MEMTYPE_SDRAM		0
+-#define OMAPFB_MEMTYPE_SRAM		1
+-#define OMAPFB_MEMTYPE_MAX		1
+-
+-enum omapfb_color_format {
+-	OMAPFB_COLOR_RGB565 = 0,
+-	OMAPFB_COLOR_YUV422,
+-	OMAPFB_COLOR_YUV420,
+-	OMAPFB_COLOR_CLUT_8BPP,
+-	OMAPFB_COLOR_CLUT_4BPP,
+-	OMAPFB_COLOR_CLUT_2BPP,
+-	OMAPFB_COLOR_CLUT_1BPP,
+-	OMAPFB_COLOR_RGB444,
+-	OMAPFB_COLOR_YUY422,
+-};
+-
+-struct omapfb_update_window {
+-	__u32 x, y;
+-	__u32 width, height;
+-	__u32 format;
+-	__u32 out_x, out_y;
+-	__u32 out_width, out_height;
+-	__u32 reserved[8];
+-};
+-
+-struct omapfb_update_window_old {
+-	__u32 x, y;
+-	__u32 width, height;
+-	__u32 format;
+-};
+-
+-enum omapfb_plane {
+-	OMAPFB_PLANE_GFX = 0,
+-	OMAPFB_PLANE_VID1,
+-	OMAPFB_PLANE_VID2,
+-};
+-
+-enum omapfb_channel_out {
+-	OMAPFB_CHANNEL_OUT_LCD = 0,
+-	OMAPFB_CHANNEL_OUT_DIGIT,
+-};
+-
+-struct omapfb_plane_info {
+-	__u32 pos_x;
+-	__u32 pos_y;
+-	__u8  enabled;
+-	__u8  channel_out;
+-	__u8  mirror;
+-	__u8  reserved1;
+-	__u32 out_width;
+-	__u32 out_height;
+-	__u32 reserved2[12];
+-};
+-
+-struct omapfb_mem_info {
+-	__u32 size;
+-	__u8  type;
+-	__u8  reserved[3];
+-};
+-
+-struct omapfb_caps {
+-	__u32 ctrl;
+-	__u32 plane_color;
+-	__u32 wnd_color;
+-};
+-
+-enum omapfb_color_key_type {
+-	OMAPFB_COLOR_KEY_DISABLED = 0,
+-	OMAPFB_COLOR_KEY_GFX_DST,
+-	OMAPFB_COLOR_KEY_VID_SRC,
+-};
+-
+-struct omapfb_color_key {
+-	__u8  channel_out;
+-	__u32 background;
+-	__u32 trans_key;
+-	__u8  key_type;
+-};
+-
+-enum omapfb_update_mode {
+-	OMAPFB_UPDATE_DISABLED = 0,
+-	OMAPFB_AUTO_UPDATE,
+-	OMAPFB_MANUAL_UPDATE
+-};
+-
+-#ifdef __KERNEL__
+-
+-#include <linux/completion.h>
+-#include <linux/interrupt.h>
+-#include <linux/fb.h>
+-#include <linux/mutex.h>
+-
+-#include <mach/board.h>
+-
+-#define OMAP_LCDC_INV_VSYNC             0x0001
+-#define OMAP_LCDC_INV_HSYNC             0x0002
+-#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
+-#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
+-#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
+-#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
+-
+-#define OMAP_LCDC_SIGNAL_MASK		0x003f
+-
+-#define OMAP_LCDC_PANEL_TFT		0x0100
+-
+-#define OMAPFB_PLANE_XRES_MIN		8
+-#define OMAPFB_PLANE_YRES_MIN		8
+-
+-#ifdef CONFIG_ARCH_OMAP1
+-#define OMAPFB_PLANE_NUM		1
+-#else
+-#define OMAPFB_PLANE_NUM		3
+-#endif
+-
+-struct omapfb_device;
+-
+-struct lcd_panel {
+-	const char	*name;
+-	int		config;		/* TFT/STN, signal inversion */
+-	int		bpp;		/* Pixel format in fb mem */
+-	int		data_lines;	/* Lines on LCD HW interface */
+-
+-	int		x_res, y_res;
+-	int		pixel_clock;	/* In kHz */
+-	int		hsw;		/* Horizontal synchronization
+-					   pulse width */
+-	int		hfp;		/* Horizontal front porch */
+-	int		hbp;		/* Horizontal back porch */
+-	int		vsw;		/* Vertical synchronization
+-					   pulse width */
+-	int		vfp;		/* Vertical front porch */
+-	int		vbp;		/* Vertical back porch */
+-	int		acb;		/* ac-bias pin frequency */
+-	int		pcd;		/* pixel clock divider.
+-					   Obsolete use pixel_clock instead */
+-
+-	int		(*init)		(struct lcd_panel *panel,
+-					 struct omapfb_device *fbdev);
+-	void		(*cleanup)	(struct lcd_panel *panel);
+-	int		(*enable)	(struct lcd_panel *panel);
+-	void		(*disable)	(struct lcd_panel *panel);
+-	unsigned long	(*get_caps)	(struct lcd_panel *panel);
+-	int		(*set_bklight_level)(struct lcd_panel *panel,
+-					     unsigned int level);
+-	unsigned int	(*get_bklight_level)(struct lcd_panel *panel);
+-	unsigned int	(*get_bklight_max)  (struct lcd_panel *panel);
+-	int		(*run_test)	(struct lcd_panel *panel, int test_num);
+-};
+-
+-struct extif_timings {
+-	int cs_on_time;
+-	int cs_off_time;
+-	int we_on_time;
+-	int we_off_time;
+-	int re_on_time;
+-	int re_off_time;
+-	int we_cycle_time;
+-	int re_cycle_time;
+-	int cs_pulse_width;
+-	int access_time;
+-
+-	int clk_div;
+-
+-	u32 tim[5];		/* set by extif->convert_timings */
+-
+-	int converted;
+-};
+-
+-struct lcd_ctrl_extif {
+-	int  (*init)		(struct omapfb_device *fbdev);
+-	void (*cleanup)		(void);
+-	void (*get_clk_info)	(u32 *clk_period, u32 *max_clk_div);
+-	unsigned long (*get_max_tx_rate)(void);
+-	int  (*convert_timings)	(struct extif_timings *timings);
+-	void (*set_timings)	(const struct extif_timings *timings);
+-	void (*set_bits_per_cycle)(int bpc);
+-	void (*write_command)	(const void *buf, unsigned int len);
+-	void (*read_data)	(void *buf, unsigned int len);
+-	void (*write_data)	(const void *buf, unsigned int len);
+-	void (*transfer_area)	(int width, int height,
+-				 void (callback)(void * data), void *data);
+-	int  (*setup_tearsync)	(unsigned pin_cnt,
+-				 unsigned hs_pulse_time, unsigned vs_pulse_time,
+-				 int hs_pol_inv, int vs_pol_inv, int div);
+-	int  (*enable_tearsync) (int enable, unsigned line);
+-
+-	unsigned long		max_transmit_size;
+-};
+-
+-struct omapfb_notifier_block {
+-	struct notifier_block	nb;
+-	void			*data;
+-	int			plane_idx;
+-};
+-
+-typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
+-					  unsigned long event,
+-					  void *fbi);
+-
+-struct omapfb_mem_region {
+-	u32		paddr;
+-	void __iomem	*vaddr;
+-	unsigned long	size;
+-	u8		type;		/* OMAPFB_PLANE_MEM_* */
+-	unsigned	alloc:1;	/* allocated by the driver */
+-	unsigned	map:1;		/* kernel mapped by the driver */
+-};
+-
+-struct omapfb_mem_desc {
+-	int				region_cnt;
+-	struct omapfb_mem_region	region[OMAPFB_PLANE_NUM];
+-};
+-
+-struct lcd_ctrl {
+-	const char	*name;
+-	void		*data;
+-
+-	int		(*init)		  (struct omapfb_device *fbdev,
+-					   int ext_mode,
+-					   struct omapfb_mem_desc *req_md);
+-	void		(*cleanup)	  (void);
+-	void		(*bind_client)	  (struct omapfb_notifier_block *nb);
+-	void		(*get_caps)	  (int plane, struct omapfb_caps *caps);
+-	int		(*set_update_mode)(enum omapfb_update_mode mode);
+-	enum omapfb_update_mode (*get_update_mode)(void);
+-	int		(*setup_plane)	  (int plane, int channel_out,
+-					   unsigned long offset,
+-					   int screen_width,
+-					   int pos_x, int pos_y, int width,
+-					   int height, int color_mode);
+-	int		(*set_rotate)	  (int angle);
+-	int		(*setup_mem)	  (int plane, size_t size,
+-					   int mem_type, unsigned long *paddr);
+-	int		(*mmap)		  (struct fb_info *info,
+-					   struct vm_area_struct *vma);
+-	int		(*set_scale)	  (int plane,
+-					   int orig_width, int orig_height,
+-					   int out_width, int out_height);
+-	int		(*enable_plane)	  (int plane, int enable);
+-	int		(*update_window)  (struct fb_info *fbi,
+-					   struct omapfb_update_window *win,
+-					   void (*callback)(void *),
+-					   void *callback_data);
+-	void		(*sync)		  (void);
+-	void		(*suspend)	  (void);
+-	void		(*resume)	  (void);
+-	int		(*run_test)	  (int test_num);
+-	int		(*setcolreg)	  (u_int regno, u16 red, u16 green,
+-					   u16 blue, u16 transp,
+-					   int update_hw_mem);
+-	int		(*set_color_key)  (struct omapfb_color_key *ck);
+-	int		(*get_color_key)  (struct omapfb_color_key *ck);
+-};
+-
+-enum omapfb_state {
+-	OMAPFB_DISABLED	= 0,
+-	OMAPFB_SUSPENDED= 99,
+-	OMAPFB_ACTIVE	= 100
+-};
+-
+-struct omapfb_plane_struct {
+-	int				idx;
+-	struct omapfb_plane_info	info;
+-	enum omapfb_color_format	color_mode;
+-	struct omapfb_device		*fbdev;
+-};
+-
+-struct omapfb_device {
+-	int			state;
+-	int                     ext_lcdc;               /* Using external
+-                                                           LCD controller */
+-	struct mutex		rqueue_mutex;
+-
+-	int			palette_size;
+-	u32			pseudo_palette[17];
+-
+-	struct lcd_panel	*panel;			/* LCD panel */
+-	const struct lcd_ctrl	*ctrl;			/* LCD controller */
+-	const struct lcd_ctrl	*int_ctrl;		/* internal LCD ctrl */
+-	struct lcd_ctrl_extif	*ext_if;		/* LCD ctrl external
+-							   interface */
+-	struct device		*dev;
+-	struct fb_var_screeninfo	new_var;	/* for mode changes */
+-
+-	struct omapfb_mem_desc		mem_desc;
+-	struct fb_info			*fb_info[OMAPFB_PLANE_NUM];
+-};
+-
+-struct omapfb_platform_data {
+-	struct omap_lcd_config		lcd;
+-	struct omapfb_mem_desc		mem_desc;
+-	void				*ctrl_platform_data;
+-};
+-
+-#ifdef CONFIG_ARCH_OMAP1
+-extern struct lcd_ctrl omap1_lcd_ctrl;
+-#else
+-extern struct lcd_ctrl omap2_disp_ctrl;
+-#endif
+-
+-extern void omapfb_reserve_sdram(void);
+-extern void omapfb_register_panel(struct lcd_panel *panel);
+-extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
+-extern void omapfb_notify_clients(struct omapfb_device *fbdev,
+-				  unsigned long event);
+-extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
+-				   omapfb_notifier_callback_t callback,
+-				   void *callback_data);
+-extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
+-extern int  omapfb_update_window_async(struct fb_info *fbi,
+-				       struct omapfb_update_window *win,
+-				       void (*callback)(void *),
+-				       void *callback_data);
+-
+-/* in arch/arm/plat-omap/fb.c */
+-extern void omapfb_set_ctrl_platform_data(void *pdata);
+-
+-#endif /* __KERNEL__ */
+-
+-#endif /* __OMAPFB_H */
+diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c
+index f60a233..8121c09 100644
+--- a/drivers/video/omap/blizzard.c
++++ b/drivers/video/omap/blizzard.c
+@@ -25,9 +25,9 @@
+ #include <linux/fb.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ #include <mach/blizzard.h>
+ 
+ #include "dispc.h"
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index c140c21..1915af5 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -24,9 +24,9 @@
+ #include <linux/vmalloc.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/sram.h>
+-#include <mach/omapfb.h>
+ #include <mach/board.h>
+ 
+ #include "dispc.h"
+diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c
+index f24df0b..9b4c506 100644
+--- a/drivers/video/omap/hwa742.c
++++ b/drivers/video/omap/hwa742.c
+@@ -25,9 +25,9 @@
+ #include <linux/fb.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ #include <mach/hwa742.h>
+ 
+ #define HWA742_REV_CODE_REG       0x0
+diff --git a/drivers/video/omap/lcd_2430sdp.c b/drivers/video/omap/lcd_2430sdp.c
+index a22b452..1252cc3 100644
+--- a/drivers/video/omap/lcd_2430sdp.c
++++ b/drivers/video/omap/lcd_2430sdp.c
+@@ -26,9 +26,9 @@
+ #include <linux/delay.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+ 
+ #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO	91
+diff --git a/drivers/video/omap/lcd_ams_delta.c b/drivers/video/omap/lcd_ams_delta.c
+index 3fd5342..4d54725 100644
+--- a/drivers/video/omap/lcd_ams_delta.c
++++ b/drivers/video/omap/lcd_ams_delta.c
+@@ -24,13 +24,13 @@
+ 
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+ 
+ #include <asm/delay.h>
+ #include <asm/io.h>
+ 
+ #include <mach/board-ams-delta.h>
+ #include <mach/hardware.h>
+-#include <mach/omapfb.h>
+ 
+ #define AMS_DELTA_DEFAULT_CONTRAST	112
+ 
+diff --git a/drivers/video/omap/lcd_apollon.c b/drivers/video/omap/lcd_apollon.c
+index beae5d9..e3b2224 100644
+--- a/drivers/video/omap/lcd_apollon.c
++++ b/drivers/video/omap/lcd_apollon.c
+@@ -23,10 +23,10 @@
+ 
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ 
+ /* #define USE_35INCH_LCD 1 */
+ 
+diff --git a/drivers/video/omap/lcd_h3.c b/drivers/video/omap/lcd_h3.c
+index 2486237..f7264ea 100644
+--- a/drivers/video/omap/lcd_h3.c
++++ b/drivers/video/omap/lcd_h3.c
+@@ -22,9 +22,9 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c/tps65010.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
+ 
+ #define MODULE_NAME	"omapfb-lcd_h3"
+ 
+diff --git a/drivers/video/omap/lcd_h4.c b/drivers/video/omap/lcd_h4.c
+index 6ff5643..d72df0c 100644
+--- a/drivers/video/omap/lcd_h4.c
++++ b/drivers/video/omap/lcd_h4.c
+@@ -21,8 +21,7 @@
+ 
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+-
+-#include <mach/omapfb.h>
++#include <linux/omapfb.h>
+ 
+ static int h4_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
+ {
+diff --git a/drivers/video/omap/lcd_inn1510.c b/drivers/video/omap/lcd_inn1510.c
+index 6953ed4..f6e05d7 100644
+--- a/drivers/video/omap/lcd_inn1510.c
++++ b/drivers/video/omap/lcd_inn1510.c
+@@ -22,9 +22,9 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/fpga.h>
+-#include <mach/omapfb.h>
+ 
+ static int innovator1510_panel_init(struct lcd_panel *panel,
+ 				    struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_inn1610.c b/drivers/video/omap/lcd_inn1610.c
+index 4c4f7ee..c599e41 100644
+--- a/drivers/video/omap/lcd_inn1610.c
++++ b/drivers/video/omap/lcd_inn1610.c
+@@ -21,9 +21,9 @@
+ 
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
+ 
+ #define MODULE_NAME	"omapfb-lcd_h3"
+ 
+diff --git a/drivers/video/omap/lcd_ldp.c b/drivers/video/omap/lcd_ldp.c
+index 8925230..1c25186 100644
+--- a/drivers/video/omap/lcd_ldp.c
++++ b/drivers/video/omap/lcd_ldp.c
+@@ -25,10 +25,10 @@
+ #include <linux/platform_device.h>
+ #include <linux/delay.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+ 
+ #define LCD_PANEL_BACKLIGHT_GPIO 	(15 + OMAP_MAX_GPIO_LINES)
+diff --git a/drivers/video/omap/lcd_mipid.c b/drivers/video/omap/lcd_mipid.c
+index 1895997..4b28005 100644
+--- a/drivers/video/omap/lcd_mipid.c
++++ b/drivers/video/omap/lcd_mipid.c
+@@ -22,8 +22,8 @@
+ #include <linux/delay.h>
+ #include <linux/workqueue.h>
+ #include <linux/spi/spi.h>
++#include <linux/omapfb.h>
+ 
+-#include <mach/omapfb.h>
+ #include <mach/lcd_mipid.h>
+ 
+ #include "../../cbus/tahvo.h"
+diff --git a/drivers/video/omap/lcd_omap2evm.c b/drivers/video/omap/lcd_omap2evm.c
+index 2fc46c2..1908a2b 100644
+--- a/drivers/video/omap/lcd_omap2evm.c
++++ b/drivers/video/omap/lcd_omap2evm.c
+@@ -25,9 +25,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+ 
+ #define LCD_PANEL_ENABLE_GPIO	154
+diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c
+index eae43e4..6be117e 100644
+--- a/drivers/video/omap/lcd_omap3beagle.c
++++ b/drivers/video/omap/lcd_omap3beagle.c
+@@ -24,9 +24,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+ 
+ #define LCD_PANEL_ENABLE_GPIO       170
+diff --git a/drivers/video/omap/lcd_omap3evm.c b/drivers/video/omap/lcd_omap3evm.c
+index 1c3d814..10ba48c 100644
+--- a/drivers/video/omap/lcd_omap3evm.c
++++ b/drivers/video/omap/lcd_omap3evm.c
+@@ -24,9 +24,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+ 
+ #define LCD_PANEL_ENABLE_GPIO       153
+diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
+index 379c96d..d6b193e 100644
+--- a/drivers/video/omap/lcd_osk.c
++++ b/drivers/video/omap/lcd_osk.c
+@@ -22,10 +22,10 @@
+ 
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ 
+ static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
+ {
+diff --git a/drivers/video/omap/lcd_overo.c b/drivers/video/omap/lcd_overo.c
+index 2bc5c92..40c2026 100644
+--- a/drivers/video/omap/lcd_overo.c
++++ b/drivers/video/omap/lcd_overo.c
+@@ -22,10 +22,10 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+ 
+ #define LCD_ENABLE       144
+diff --git a/drivers/video/omap/lcd_p2.c b/drivers/video/omap/lcd_p2.c
+index dd40fd7..bc5abef 100644
+--- a/drivers/video/omap/lcd_p2.c
++++ b/drivers/video/omap/lcd_p2.c
+@@ -24,10 +24,10 @@
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/mux.h>
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
+ 
+ /*
+  * File: epson-md-tft.h
+diff --git a/drivers/video/omap/lcd_palmte.c b/drivers/video/omap/lcd_palmte.c
+index 2183173..dcb456c 100644
+--- a/drivers/video/omap/lcd_palmte.c
++++ b/drivers/video/omap/lcd_palmte.c
+@@ -22,9 +22,9 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/fpga.h>
+-#include <mach/omapfb.h>
+ 
+ static int palmte_panel_init(struct lcd_panel *panel,
+ 				struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_palmtt.c b/drivers/video/omap/lcd_palmtt.c
+index 57b0f6c..e8adab8 100644
+--- a/drivers/video/omap/lcd_palmtt.c
++++ b/drivers/video/omap/lcd_palmtt.c
+@@ -28,9 +28,9 @@ GPIO13 - screen blanking
+ #include <linux/platform_device.h>
+ #include <linux/module.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
+ 
+ static int palmtt_panel_init(struct lcd_panel *panel,
+ 	struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_palmz71.c b/drivers/video/omap/lcd_palmz71.c
+index d33d78b..d5b3f82 100644
+--- a/drivers/video/omap/lcd_palmz71.c
++++ b/drivers/video/omap/lcd_palmz71.c
+@@ -23,8 +23,7 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+-
+-#include <mach/omapfb.h>
++#include <linux/omapfb.h>
+ 
+ static int palmz71_panel_init(struct lcd_panel *panel,
+ 			      struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c
+index ab39492..633e33c 100644
+--- a/drivers/video/omap/lcdc.c
++++ b/drivers/video/omap/lcdc.c
+@@ -28,9 +28,9 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/vmalloc.h>
+ #include <linux/clk.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ 
+ #include <asm/mach-types.h>
+ 
+diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
+index 3bb4247..c6306af 100644
+--- a/drivers/video/omap/omapfb_main.c
++++ b/drivers/video/omap/omapfb_main.c
+@@ -27,9 +27,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/mm.h>
+ #include <linux/uaccess.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ 
+ #include "lcdc.h"
+ #include "dispc.h"
+diff --git a/drivers/video/omap/rfbi.c b/drivers/video/omap/rfbi.c
+index 29fa368..118cfa9 100644
+--- a/drivers/video/omap/rfbi.c
++++ b/drivers/video/omap/rfbi.c
+@@ -26,8 +26,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
+-
+-#include <mach/omapfb.h>
++#include <linux/omapfb.h>
+ 
+ #include "dispc.h"
+ 
+diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c
+index cc697cc..ff9dd71 100644
+--- a/drivers/video/omap/sossi.c
++++ b/drivers/video/omap/sossi.c
+@@ -23,9 +23,9 @@
+ #include <linux/clk.h>
+ #include <linux/irq.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ 
+ #include "lcdc.h"
+ 
+diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
+new file mode 100644
+index 0000000..b226bdf
+--- /dev/null
++++ b/include/linux/omapfb.h
+@@ -0,0 +1,398 @@
++/*
++ * File: arch/arm/plat-omap/include/mach/omapfb.h
++ *
++ * Framebuffer driver for TI OMAP boards
++ *
++ * Copyright (C) 2004 Nokia Corporation
++ * Author: Imre Deak <imre.deak@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++#ifndef __OMAPFB_H
++#define __OMAPFB_H
++
++#include <asm/ioctl.h>
++#include <asm/types.h>
++
++/* IOCTL commands. */
++
++#define OMAP_IOW(num, dtype)	_IOW('O', num, dtype)
++#define OMAP_IOR(num, dtype)	_IOR('O', num, dtype)
++#define OMAP_IOWR(num, dtype)	_IOWR('O', num, dtype)
++#define OMAP_IO(num)		_IO('O', num)
++
++#define OMAPFB_MIRROR		OMAP_IOW(31, int)
++#define OMAPFB_SYNC_GFX		OMAP_IO(37)
++#define OMAPFB_VSYNC		OMAP_IO(38)
++#define OMAPFB_SET_UPDATE_MODE	OMAP_IOW(40, int)
++#define OMAPFB_GET_CAPS		OMAP_IOR(42, struct omapfb_caps)
++#define OMAPFB_GET_UPDATE_MODE	OMAP_IOW(43, int)
++#define OMAPFB_LCD_TEST		OMAP_IOW(45, int)
++#define OMAPFB_CTRL_TEST	OMAP_IOW(46, int)
++#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
++#define OMAPFB_SET_COLOR_KEY	OMAP_IOW(50, struct omapfb_color_key)
++#define OMAPFB_GET_COLOR_KEY	OMAP_IOW(51, struct omapfb_color_key)
++#define OMAPFB_SETUP_PLANE	OMAP_IOW(52, struct omapfb_plane_info)
++#define OMAPFB_QUERY_PLANE	OMAP_IOW(53, struct omapfb_plane_info)
++#define OMAPFB_UPDATE_WINDOW	OMAP_IOW(54, struct omapfb_update_window)
++#define OMAPFB_SETUP_MEM	OMAP_IOW(55, struct omapfb_mem_info)
++#define OMAPFB_QUERY_MEM	OMAP_IOW(56, struct omapfb_mem_info)
++
++#define OMAPFB_CAPS_GENERIC_MASK	0x00000fff
++#define OMAPFB_CAPS_LCDC_MASK		0x00fff000
++#define OMAPFB_CAPS_PANEL_MASK		0xff000000
++
++#define OMAPFB_CAPS_MANUAL_UPDATE	0x00001000
++#define OMAPFB_CAPS_TEARSYNC		0x00002000
++#define OMAPFB_CAPS_PLANE_RELOCATE_MEM	0x00004000
++#define OMAPFB_CAPS_PLANE_SCALE		0x00008000
++#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE	0x00010000
++#define OMAPFB_CAPS_WINDOW_SCALE	0x00020000
++#define OMAPFB_CAPS_WINDOW_OVERLAY	0x00040000
++#define OMAPFB_CAPS_WINDOW_ROTATE	0x00080000
++#define OMAPFB_CAPS_SET_BACKLIGHT	0x01000000
++
++/* Values from DSP must map to lower 16-bits */
++#define OMAPFB_FORMAT_MASK		0x00ff
++#define OMAPFB_FORMAT_FLAG_DOUBLE	0x0100
++#define OMAPFB_FORMAT_FLAG_TEARSYNC	0x0200
++#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC	0x0400
++#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY	0x0800
++#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY	0x1000
++
++#define OMAPFB_EVENT_READY	1
++#define OMAPFB_EVENT_DISABLED	2
++
++#define OMAPFB_MEMTYPE_SDRAM		0
++#define OMAPFB_MEMTYPE_SRAM		1
++#define OMAPFB_MEMTYPE_MAX		1
++
++enum omapfb_color_format {
++	OMAPFB_COLOR_RGB565 = 0,
++	OMAPFB_COLOR_YUV422,
++	OMAPFB_COLOR_YUV420,
++	OMAPFB_COLOR_CLUT_8BPP,
++	OMAPFB_COLOR_CLUT_4BPP,
++	OMAPFB_COLOR_CLUT_2BPP,
++	OMAPFB_COLOR_CLUT_1BPP,
++	OMAPFB_COLOR_RGB444,
++	OMAPFB_COLOR_YUY422,
++};
++
++struct omapfb_update_window {
++	__u32 x, y;
++	__u32 width, height;
++	__u32 format;
++	__u32 out_x, out_y;
++	__u32 out_width, out_height;
++	__u32 reserved[8];
++};
++
++struct omapfb_update_window_old {
++	__u32 x, y;
++	__u32 width, height;
++	__u32 format;
++};
++
++enum omapfb_plane {
++	OMAPFB_PLANE_GFX = 0,
++	OMAPFB_PLANE_VID1,
++	OMAPFB_PLANE_VID2,
++};
++
++enum omapfb_channel_out {
++	OMAPFB_CHANNEL_OUT_LCD = 0,
++	OMAPFB_CHANNEL_OUT_DIGIT,
++};
++
++struct omapfb_plane_info {
++	__u32 pos_x;
++	__u32 pos_y;
++	__u8  enabled;
++	__u8  channel_out;
++	__u8  mirror;
++	__u8  reserved1;
++	__u32 out_width;
++	__u32 out_height;
++	__u32 reserved2[12];
++};
++
++struct omapfb_mem_info {
++	__u32 size;
++	__u8  type;
++	__u8  reserved[3];
++};
++
++struct omapfb_caps {
++	__u32 ctrl;
++	__u32 plane_color;
++	__u32 wnd_color;
++};
++
++enum omapfb_color_key_type {
++	OMAPFB_COLOR_KEY_DISABLED = 0,
++	OMAPFB_COLOR_KEY_GFX_DST,
++	OMAPFB_COLOR_KEY_VID_SRC,
++};
++
++struct omapfb_color_key {
++	__u8  channel_out;
++	__u32 background;
++	__u32 trans_key;
++	__u8  key_type;
++};
++
++enum omapfb_update_mode {
++	OMAPFB_UPDATE_DISABLED = 0,
++	OMAPFB_AUTO_UPDATE,
++	OMAPFB_MANUAL_UPDATE
++};
++
++#ifdef __KERNEL__
++
++#include <linux/completion.h>
++#include <linux/interrupt.h>
++#include <linux/fb.h>
++#include <linux/mutex.h>
++
++#include <mach/board.h>
++
++#define OMAP_LCDC_INV_VSYNC             0x0001
++#define OMAP_LCDC_INV_HSYNC             0x0002
++#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
++#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
++#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
++#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
++
++#define OMAP_LCDC_SIGNAL_MASK		0x003f
++
++#define OMAP_LCDC_PANEL_TFT		0x0100
++
++#define OMAPFB_PLANE_XRES_MIN		8
++#define OMAPFB_PLANE_YRES_MIN		8
++
++#ifdef CONFIG_ARCH_OMAP1
++#define OMAPFB_PLANE_NUM		1
++#else
++#define OMAPFB_PLANE_NUM		3
++#endif
++
++struct omapfb_device;
++
++struct lcd_panel {
++	const char	*name;
++	int		config;		/* TFT/STN, signal inversion */
++	int		bpp;		/* Pixel format in fb mem */
++	int		data_lines;	/* Lines on LCD HW interface */
++
++	int		x_res, y_res;
++	int		pixel_clock;	/* In kHz */
++	int		hsw;		/* Horizontal synchronization
++					   pulse width */
++	int		hfp;		/* Horizontal front porch */
++	int		hbp;		/* Horizontal back porch */
++	int		vsw;		/* Vertical synchronization
++					   pulse width */
++	int		vfp;		/* Vertical front porch */
++	int		vbp;		/* Vertical back porch */
++	int		acb;		/* ac-bias pin frequency */
++	int		pcd;		/* pixel clock divider.
++					   Obsolete use pixel_clock instead */
++
++	int		(*init)		(struct lcd_panel *panel,
++					 struct omapfb_device *fbdev);
++	void		(*cleanup)	(struct lcd_panel *panel);
++	int		(*enable)	(struct lcd_panel *panel);
++	void		(*disable)	(struct lcd_panel *panel);
++	unsigned long	(*get_caps)	(struct lcd_panel *panel);
++	int		(*set_bklight_level)(struct lcd_panel *panel,
++					     unsigned int level);
++	unsigned int	(*get_bklight_level)(struct lcd_panel *panel);
++	unsigned int	(*get_bklight_max)  (struct lcd_panel *panel);
++	int		(*run_test)	(struct lcd_panel *panel, int test_num);
++};
++
++struct extif_timings {
++	int cs_on_time;
++	int cs_off_time;
++	int we_on_time;
++	int we_off_time;
++	int re_on_time;
++	int re_off_time;
++	int we_cycle_time;
++	int re_cycle_time;
++	int cs_pulse_width;
++	int access_time;
++
++	int clk_div;
++
++	u32 tim[5];		/* set by extif->convert_timings */
++
++	int converted;
++};
++
++struct lcd_ctrl_extif {
++	int  (*init)		(struct omapfb_device *fbdev);
++	void (*cleanup)		(void);
++	void (*get_clk_info)	(u32 *clk_period, u32 *max_clk_div);
++	unsigned long (*get_max_tx_rate)(void);
++	int  (*convert_timings)	(struct extif_timings *timings);
++	void (*set_timings)	(const struct extif_timings *timings);
++	void (*set_bits_per_cycle)(int bpc);
++	void (*write_command)	(const void *buf, unsigned int len);
++	void (*read_data)	(void *buf, unsigned int len);
++	void (*write_data)	(const void *buf, unsigned int len);
++	void (*transfer_area)	(int width, int height,
++				 void (callback)(void * data), void *data);
++	int  (*setup_tearsync)	(unsigned pin_cnt,
++				 unsigned hs_pulse_time, unsigned vs_pulse_time,
++				 int hs_pol_inv, int vs_pol_inv, int div);
++	int  (*enable_tearsync) (int enable, unsigned line);
++
++	unsigned long		max_transmit_size;
++};
++
++struct omapfb_notifier_block {
++	struct notifier_block	nb;
++	void			*data;
++	int			plane_idx;
++};
++
++typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
++					  unsigned long event,
++					  void *fbi);
++
++struct omapfb_mem_region {
++	u32		paddr;
++	void __iomem	*vaddr;
++	unsigned long	size;
++	u8		type;		/* OMAPFB_PLANE_MEM_* */
++	unsigned	alloc:1;	/* allocated by the driver */
++	unsigned	map:1;		/* kernel mapped by the driver */
++};
++
++struct omapfb_mem_desc {
++	int				region_cnt;
++	struct omapfb_mem_region	region[OMAPFB_PLANE_NUM];
++};
++
++struct lcd_ctrl {
++	const char	*name;
++	void		*data;
++
++	int		(*init)		  (struct omapfb_device *fbdev,
++					   int ext_mode,
++					   struct omapfb_mem_desc *req_md);
++	void		(*cleanup)	  (void);
++	void		(*bind_client)	  (struct omapfb_notifier_block *nb);
++	void		(*get_caps)	  (int plane, struct omapfb_caps *caps);
++	int		(*set_update_mode)(enum omapfb_update_mode mode);
++	enum omapfb_update_mode (*get_update_mode)(void);
++	int		(*setup_plane)	  (int plane, int channel_out,
++					   unsigned long offset,
++					   int screen_width,
++					   int pos_x, int pos_y, int width,
++					   int height, int color_mode);
++	int		(*set_rotate)	  (int angle);
++	int		(*setup_mem)	  (int plane, size_t size,
++					   int mem_type, unsigned long *paddr);
++	int		(*mmap)		  (struct fb_info *info,
++					   struct vm_area_struct *vma);
++	int		(*set_scale)	  (int plane,
++					   int orig_width, int orig_height,
++					   int out_width, int out_height);
++	int		(*enable_plane)	  (int plane, int enable);
++	int		(*update_window)  (struct fb_info *fbi,
++					   struct omapfb_update_window *win,
++					   void (*callback)(void *),
++					   void *callback_data);
++	void		(*sync)		  (void);
++	void		(*suspend)	  (void);
++	void		(*resume)	  (void);
++	int		(*run_test)	  (int test_num);
++	int		(*setcolreg)	  (u_int regno, u16 red, u16 green,
++					   u16 blue, u16 transp,
++					   int update_hw_mem);
++	int		(*set_color_key)  (struct omapfb_color_key *ck);
++	int		(*get_color_key)  (struct omapfb_color_key *ck);
++};
++
++enum omapfb_state {
++	OMAPFB_DISABLED	= 0,
++	OMAPFB_SUSPENDED= 99,
++	OMAPFB_ACTIVE	= 100
++};
++
++struct omapfb_plane_struct {
++	int				idx;
++	struct omapfb_plane_info	info;
++	enum omapfb_color_format	color_mode;
++	struct omapfb_device		*fbdev;
++};
++
++struct omapfb_device {
++	int			state;
++	int                     ext_lcdc;               /* Using external
++                                                           LCD controller */
++	struct mutex		rqueue_mutex;
++
++	int			palette_size;
++	u32			pseudo_palette[17];
++
++	struct lcd_panel	*panel;			/* LCD panel */
++	const struct lcd_ctrl	*ctrl;			/* LCD controller */
++	const struct lcd_ctrl	*int_ctrl;		/* internal LCD ctrl */
++	struct lcd_ctrl_extif	*ext_if;		/* LCD ctrl external
++							   interface */
++	struct device		*dev;
++	struct fb_var_screeninfo	new_var;	/* for mode changes */
++
++	struct omapfb_mem_desc		mem_desc;
++	struct fb_info			*fb_info[OMAPFB_PLANE_NUM];
++};
++
++struct omapfb_platform_data {
++	struct omap_lcd_config		lcd;
++	struct omapfb_mem_desc		mem_desc;
++	void				*ctrl_platform_data;
++};
++
++#ifdef CONFIG_ARCH_OMAP1
++extern struct lcd_ctrl omap1_lcd_ctrl;
++#else
++extern struct lcd_ctrl omap2_disp_ctrl;
++#endif
++
++extern void omapfb_reserve_sdram(void);
++extern void omapfb_register_panel(struct lcd_panel *panel);
++extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
++extern void omapfb_notify_clients(struct omapfb_device *fbdev,
++				  unsigned long event);
++extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
++				   omapfb_notifier_callback_t callback,
++				   void *callback_data);
++extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
++extern int  omapfb_update_window_async(struct fb_info *fbi,
++				       struct omapfb_update_window *win,
++				       void (*callback)(void *),
++				       void *callback_data);
++
++/* in arch/arm/plat-omap/fb.c */
++extern void omapfb_set_ctrl_platform_data(void *pdata);
++
++#endif /* __KERNEL__ */
++
++#endif /* __OMAPFB_H */
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch
new file mode 100644
index 0000000000..4610e28704
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch
@@ -0,0 +1,14450 @@
+From 284deec412f9c6f15c971d8eaf4d0156a51a2f3b Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 10:23:42 +0300
+Subject: [PATCH 03/69] DSS2: OMAP2/3 Display Subsystem driver
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ Documentation/arm/OMAP/DSS                |  311 +++
+ arch/arm/plat-omap/Makefile               |    2 +-
+ arch/arm/plat-omap/include/mach/display.h |  520 ++++
+ arch/arm/plat-omap/include/mach/vram.h    |   33 +
+ arch/arm/plat-omap/include/mach/vrfb.h    |   47 +
+ arch/arm/plat-omap/vram.c                 |  615 +++++
+ arch/arm/plat-omap/vrfb.c                 |  159 ++
+ drivers/video/Kconfig                     |    1 +
+ drivers/video/Makefile                    |    1 +
+ drivers/video/omap2/Kconfig               |    3 +
+ drivers/video/omap2/Makefile              |    4 +
+ drivers/video/omap2/dss/Kconfig           |   89 +
+ drivers/video/omap2/dss/Makefile          |    6 +
+ drivers/video/omap2/dss/core.c            |  641 +++++
+ drivers/video/omap2/dss/dispc.c           | 2968 +++++++++++++++++++++++
+ drivers/video/omap2/dss/display.c         |  693 ++++++
+ drivers/video/omap2/dss/dpi.c             |  393 +++
+ drivers/video/omap2/dss/dsi.c             | 3752 +++++++++++++++++++++++++++++
+ drivers/video/omap2/dss/dss.c             |  345 +++
+ drivers/video/omap2/dss/dss.h             |  331 +++
+ drivers/video/omap2/dss/manager.c         |  576 +++++
+ drivers/video/omap2/dss/overlay.c         |  587 +++++
+ drivers/video/omap2/dss/rfbi.c            | 1304 ++++++++++
+ drivers/video/omap2/dss/sdi.c             |  245 ++
+ drivers/video/omap2/dss/venc.c            |  600 +++++
+ 25 files changed, 14225 insertions(+), 1 deletions(-)
+ create mode 100644 Documentation/arm/OMAP/DSS
+ create mode 100644 arch/arm/plat-omap/include/mach/display.h
+ create mode 100644 arch/arm/plat-omap/include/mach/vram.h
+ create mode 100644 arch/arm/plat-omap/include/mach/vrfb.h
+ create mode 100644 arch/arm/plat-omap/vram.c
+ create mode 100644 arch/arm/plat-omap/vrfb.c
+ create mode 100644 drivers/video/omap2/Kconfig
+ create mode 100644 drivers/video/omap2/Makefile
+ create mode 100644 drivers/video/omap2/dss/Kconfig
+ create mode 100644 drivers/video/omap2/dss/Makefile
+ create mode 100644 drivers/video/omap2/dss/core.c
+ create mode 100644 drivers/video/omap2/dss/dispc.c
+ create mode 100644 drivers/video/omap2/dss/display.c
+ create mode 100644 drivers/video/omap2/dss/dpi.c
+ create mode 100644 drivers/video/omap2/dss/dsi.c
+ create mode 100644 drivers/video/omap2/dss/dss.c
+ create mode 100644 drivers/video/omap2/dss/dss.h
+ create mode 100644 drivers/video/omap2/dss/manager.c
+ create mode 100644 drivers/video/omap2/dss/overlay.c
+ create mode 100644 drivers/video/omap2/dss/rfbi.c
+ create mode 100644 drivers/video/omap2/dss/sdi.c
+ create mode 100644 drivers/video/omap2/dss/venc.c
+
+diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
+new file mode 100644
+index 0000000..9e902a2
+--- /dev/null
++++ b/Documentation/arm/OMAP/DSS
+@@ -0,0 +1,311 @@
++OMAP2/3 Display Subsystem
++-------------------------
++
++This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
++(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
++TV-out and multiple display support, but there are lots of small improvements
++also.
++
++The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
++panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
++currently side by side, you can choose which one to use.
++
++Features
++--------
++
++Working and tested features include:
++
++- MIPI DPI (parallel) output
++- MIPI DSI output in command mode
++- MIPI DBI (RFBI) output
++- SDI output
++- TV output
++- All pieces can be compiled as a module or inside kernel
++- Use DISPC to update any of the outputs
++- Use CPU to update RFBI or DSI output
++- OMAP DISPC planes
++- RGB16, RGB24 packed, RGB24 unpacked
++- YUV2, UYVY
++- Scaling
++- Adjusting DSS FCK to find a good pixel clock
++- Use DSI DPLL to create DSS FCK
++
++Tested boards include:
++- OMAP3 SDP board
++- Beagle board
++- N810
++
++omapdss driver
++--------------
++
++The DSS driver does not itself have any support for Linux framebuffer, V4L or
++such like the current ones, but it has an internal kernel API that upper level
++drivers can use.
++
++The DSS driver models OMAP's overlays, overlay managers and displays in a
++flexible way to enable non-common multi-display configuration. In addition to
++modelling the hardware overlays, omapdss supports virtual overlays and overlay
++managers. These can be used when updating a display with CPU or system DMA.
++
++Panel and controller drivers
++----------------------------
++
++The drivers implement panel or controller specific functionality and are not
++usually visible to users except through omapfb driver.  They register
++themselves to the DSS driver.
++
++omapfb driver
++-------------
++
++The omapfb driver implements arbitrary number of standard linux framebuffers.
++These framebuffers can be routed flexibly to any overlays, thus allowing very
++dynamic display architecture.
++
++The driver exports some omapfb specific ioctls, which are compatible with the
++ioctls in the old driver.
++
++The rest of the non standard features are exported via sysfs. Whether the final
++implementation will use sysfs, or ioctls, is still open.
++
++V4L2 drivers
++------------
++
++V4L2 is being implemented in TI.
++
++From omapdss point of view the V4L2 drivers should be similar to framebuffer
++driver.
++
++Architecture
++--------------------
++
++Some clarification what the different components do:
++
++    - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the
++      pixel data for the image. Framebuffer has width and height and color
++      depth.
++    - Overlay defines where the pixels are read from and where they go on the
++      screen. The overlay may be smaller than framebuffer, thus displaying only
++      part of the framebuffer. The position of the overlay may be changed if
++      the overlay is smaller than the display.
++    - Overlay manager combines the overlays in to one image and feeds them to
++      display.
++    - Display is the actual physical display device.
++
++A framebuffer can be connected to multiple overlays to show the same pixel data
++on all of the overlays. Note that in this case the overlay input sizes must be
++the same, but, in case of video overlays, the output size can be different. Any
++framebuffer can be connected to any overlay.
++
++An overlay can be connected to one overlay manager. Also DISPC overlays can be
++connected only to DISPC overlay managers, and virtual overlays can be only
++connected to virtual overlays.
++
++An overlay manager can be connected to one display. There are certain
++restrictions which kinds of displays an overlay manager can be connected:
++
++    - DISPC TV overlay manager can be only connected to TV display.
++    - Virtual overlay managers can only be connected to DBI or DSI displays.
++    - DISPC LCD overlay manager can be connected to all displays, except TV
++      display.
++
++Sysfs
++-----
++The sysfs interface is mainly used for testing. I don't think sysfs
++interface is the best for this in the final version, but I don't quite know
++what would be the best interfaces for these things.
++
++The sysfs interface is divided to two parts: DSS and FB.
++
++/sys/class/graphics/fb? directory:
++mirror		0=off, 1=on
++rotate		Rotation 0-3 for 0, 90, 180, 270 degrees
++rotate_type	0 = DMA rotation, 1 = VRFB rotation
++overlays	List of overlay numbers to which framebuffer pixels go
++phys_addr	Physical address of the framebuffer
++virt_addr	Virtual address of the framebuffer
++size		Size of the framebuffer
++
++/sys/devices/platform/omapdss/overlay? directory:
++enabled		0=off, 1=on
++input_size	width,height (ie. the framebuffer size)
++manager		Destination overlay manager name
++name
++output_size	width,height
++position	x,y
++screen_width	width
++
++/sys/devices/platform/omapdss/manager? directory:
++display		Destination display
++name
++
++/sys/devices/platform/omapdss/display? directory:
++ctrl_name	Controller name
++mirror		0=off, 1=on
++update_mode	0=off, 1=auto, 2=manual
++enabled		0=off, 1=on
++name
++rotate		Rotation 0-3 for 0, 90, 180, 270 degrees
++timings		Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw)
++		When writing, two special timings are accepted for tv-out:
++		"pal" and "ntsc"
++panel_name
++tear_elim	Tearing elimination 0=off, 1=on
++
++There are also some debugfs files at <debugfs>/omapdss/ which show information
++about clocks and registers.
++
++Examples
++--------
++
++The following definitions have been made for the examples below:
++
++ovl0=/sys/devices/platform/omapdss/overlay0
++ovl1=/sys/devices/platform/omapdss/overlay1
++ovl2=/sys/devices/platform/omapdss/overlay2
++
++mgr0=/sys/devices/platform/omapdss/manager0
++mgr1=/sys/devices/platform/omapdss/manager1
++
++lcd=/sys/devices/platform/omapdss/display0
++dvi=/sys/devices/platform/omapdss/display1
++tv=/sys/devices/platform/omapdss/display2
++
++fb0=/sys/class/graphics/fb0
++fb1=/sys/class/graphics/fb1
++fb2=/sys/class/graphics/fb2
++
++Default setup on OMAP3 SDP
++--------------------------
++
++Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
++and TV-out are not in use. The columns from left to right are:
++framebuffers, overlays, overlay managers, displays. Framebuffers are
++handled by omapfb, and the rest by the DSS.
++
++FB0 --- GFX  -\            DVI
++FB1 --- VID1 --+- LCD ---- LCD
++FB2 --- VID2 -/   TV ----- TV
++
++Example: Switch from LCD to DVI
++----------------------
++
++w=`cat $dvi/horizontal | cut -d "," -f 1`
++h=`cat $dvi/vertical | cut -d "," -f 1`
++
++echo "0" > $lcd/enabled
++echo "" > $mgr0/display
++fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h
++# at this point you have to switch the dvi/lcd dip-switch from the omap board
++echo "dvi" > $mgr0/display
++echo "1" > $dvi/enabled
++
++After this the configuration looks like:
++
++FB0 --- GFX  -\         -- DVI
++FB1 --- VID1 --+- LCD -/   LCD
++FB2 --- VID2 -/   TV ----- TV
++
++Example: Clone GFX overlay to LCD and TV
++-------------------------------
++
++w=`cat $tv/horizontal | cut -d "," -f 1`
++h=`cat $tv/vertical | cut -d "," -f 1`
++
++echo "0" > $ovl0/enabled
++echo "0" > $ovl1/enabled
++
++echo "" > $fb1/overlays
++echo "0,1" > $fb0/overlays
++
++echo "$w,$h" > $ovl1/output_size
++echo "tv" > $ovl1/manager
++
++echo "1" > $ovl0/enabled
++echo "1" > $ovl1/enabled
++
++echo "1" > $tv/enabled
++
++After this the configuration looks like (only relevant parts shown):
++
++FB0 +-- GFX  ---- LCD ---- LCD
++     \- VID1 ---- TV  ---- TV
++
++Misc notes
++----------
++
++OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.
++
++Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
++of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
++
++Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB
++does not support mirroring.
++
++VRFB rotation requires much more memory than non-rotated framebuffer, so you
++probably need to increase your vram setting before using VRFB rotation. Also,
++many applications may not work with VRFB if they do not pay attention to all
++framebuffer parameters.
++
++Kernel boot arguments
++---------------------
++
++vram=<size>
++	- Amount of total VRAM to preallocate. For example, "10M". omapfb
++	  allocates memory for framebuffers from VRAM.
++
++omapfb.mode=<display>:<mode>[,...]
++	- Default video mode for specified displays. For example,
++	  "dvi:800x400MR-24@60".  See drivers/video/modedb.c.
++	  There are also two special modes: "pal" and "ntsc" that
++	  can be used to tv out.
++
++omapfb.vram=<fbnum>:<size>[@<physaddr>][,...]
++	- VRAM allocated for a framebuffer. Normally omapfb allocates vram
++	  depending on the display size. With this you can manually allocate
++	  more or define the physical address of each framebuffer. For example,
++	  "1:4M" to allocate 4M for fb1.
++
++omapfb.debug=<y|n>
++	- Enable debug printing. You have to have OMAPFB debug support enabled
++	  in kernel config.
++
++omapfb.test=<y|n>
++	- Draw test pattern to framebuffer whenever framebuffer settings change.
++	  You need to have OMAPFB debug support enabled in kernel config.
++
++omapfb.vrfb=<y|n>
++	- Use VRFB rotation for all framebuffers.
++
++omapfb.rotate=<angle>
++	- Default rotation applied to all framebuffers.
++	  0 - 0 degree rotation
++	  1 - 90 degree rotation
++	  2 - 180 degree rotation
++	  3 - 270 degree rotation
++
++omapfb.mirror=<y|n>
++	- Default mirror for all framebuffers. Only works with DMA rotation.
++
++omapdss.def_disp=<display>
++	- Name of default display, to which all overlays will be connected.
++	  Common examples are "lcd" or "tv".
++
++omapdss.debug=<y|n>
++	- Enable debug printing. You have to have DSS debug support enabled in
++	  kernel config.
++
++TODO
++----
++
++DSS locking
++
++Error checking
++- Lots of checks are missing or implemented just as BUG()
++
++System DMA update for DSI
++- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
++  to skip the empty byte?)
++
++OMAP1 support
++- Not sure if needed
++
+diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
+index 3ebc09e..e6146b2 100644
+--- a/arch/arm/plat-omap/Makefile
++++ b/arch/arm/plat-omap/Makefile
+@@ -4,7 +4,7 @@
+ 
+ # Common support
+ obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
+-	 usb.o fb.o io.o
++	 usb.o fb.o vram.o vrfb.o io.o
+ obj-m :=
+ obj-n :=
+ obj-  :=
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+new file mode 100644
+index 0000000..6288353
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -0,0 +1,520 @@
++/*
++ * linux/include/asm-arm/arch-omap/display.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __ASM_ARCH_OMAP_DISPLAY_H
++#define __ASM_ARCH_OMAP_DISPLAY_H
++
++#include <linux/list.h>
++#include <linux/kobject.h>
++#include <asm/atomic.h>
++
++#define DISPC_IRQ_FRAMEDONE		(1 << 0)
++#define DISPC_IRQ_VSYNC			(1 << 1)
++#define DISPC_IRQ_EVSYNC_EVEN		(1 << 2)
++#define DISPC_IRQ_EVSYNC_ODD		(1 << 3)
++#define DISPC_IRQ_ACBIAS_COUNT_STAT	(1 << 4)
++#define DISPC_IRQ_PROG_LINE_NUM		(1 << 5)
++#define DISPC_IRQ_GFX_FIFO_UNDERFLOW	(1 << 6)
++#define DISPC_IRQ_GFX_END_WIN		(1 << 7)
++#define DISPC_IRQ_PAL_GAMMA_MASK	(1 << 8)
++#define DISPC_IRQ_OCP_ERR		(1 << 9)
++#define DISPC_IRQ_VID1_FIFO_UNDERFLOW	(1 << 10)
++#define DISPC_IRQ_VID1_END_WIN		(1 << 11)
++#define DISPC_IRQ_VID2_FIFO_UNDERFLOW	(1 << 12)
++#define DISPC_IRQ_VID2_END_WIN		(1 << 13)
++#define DISPC_IRQ_SYNC_LOST		(1 << 14)
++#define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
++#define DISPC_IRQ_WAKEUP		(1 << 16)
++
++enum omap_display_type {
++	OMAP_DISPLAY_TYPE_NONE		= 0,
++	OMAP_DISPLAY_TYPE_DPI		= 1 << 0,
++	OMAP_DISPLAY_TYPE_DBI		= 1 << 1,
++	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
++	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
++	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
++};
++
++enum omap_plane {
++	OMAP_DSS_GFX	= 0,
++	OMAP_DSS_VIDEO1	= 1,
++	OMAP_DSS_VIDEO2	= 2
++};
++
++enum omap_channel {
++	OMAP_DSS_CHANNEL_LCD	= 0,
++	OMAP_DSS_CHANNEL_DIGIT	= 1,
++};
++
++enum omap_color_mode {
++	OMAP_DSS_COLOR_CLUT1	= 1 << 0,  /* BITMAP 1 */
++	OMAP_DSS_COLOR_CLUT2	= 1 << 1,  /* BITMAP 2 */
++	OMAP_DSS_COLOR_CLUT4	= 1 << 2,  /* BITMAP 4 */
++	OMAP_DSS_COLOR_CLUT8	= 1 << 3,  /* BITMAP 8 */
++	OMAP_DSS_COLOR_RGB12U	= 1 << 4,  /* RGB12, 16-bit container */
++	OMAP_DSS_COLOR_ARGB16	= 1 << 5,  /* ARGB16 */
++	OMAP_DSS_COLOR_RGB16	= 1 << 6,  /* RGB16 */
++	OMAP_DSS_COLOR_RGB24U	= 1 << 7,  /* RGB24, 32-bit container */
++	OMAP_DSS_COLOR_RGB24P	= 1 << 8,  /* RGB24, 24-bit container */
++	OMAP_DSS_COLOR_YUV2	= 1 << 9,  /* YUV2 4:2:2 co-sited */
++	OMAP_DSS_COLOR_UYVY	= 1 << 10, /* UYVY 4:2:2 co-sited */
++	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
++	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
++	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
++
++	OMAP_DSS_COLOR_GFX_OMAP3 =
++		OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
++		OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
++		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
++		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
++		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
++		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
++
++	OMAP_DSS_COLOR_VID_OMAP3 =
++		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
++		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
++		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
++		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
++		OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
++};
++
++enum omap_lcd_display_type {
++	OMAP_DSS_LCD_DISPLAY_STN,
++	OMAP_DSS_LCD_DISPLAY_TFT,
++};
++
++enum omap_dss_load_mode {
++	OMAP_DSS_LOAD_CLUT_AND_FRAME	= 0,
++	OMAP_DSS_LOAD_CLUT_ONLY		= 1,
++	OMAP_DSS_LOAD_FRAME_ONLY	= 2,
++	OMAP_DSS_LOAD_CLUT_ONCE_FRAME	= 3,
++};
++
++enum omap_dss_color_key_type {
++	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
++	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
++};
++
++enum omap_rfbi_te_mode {
++	OMAP_DSS_RFBI_TE_MODE_1 = 1,
++	OMAP_DSS_RFBI_TE_MODE_2 = 2,
++};
++
++enum omap_panel_config {
++	OMAP_DSS_LCD_IVS		= 1<<0,
++	OMAP_DSS_LCD_IHS		= 1<<1,
++	OMAP_DSS_LCD_IPC		= 1<<2,
++	OMAP_DSS_LCD_IEO		= 1<<3,
++	OMAP_DSS_LCD_RF			= 1<<4,
++	OMAP_DSS_LCD_ONOFF		= 1<<5,
++
++	OMAP_DSS_LCD_TFT		= 1<<20,
++};
++
++enum omap_dss_venc_type {
++	OMAP_DSS_VENC_TYPE_COMPOSITE,
++	OMAP_DSS_VENC_TYPE_SVIDEO,
++};
++
++struct omap_display;
++struct omap_panel;
++struct omap_ctrl;
++
++/* RFBI */
++
++struct rfbi_timings {
++	int cs_on_time;
++	int cs_off_time;
++	int we_on_time;
++	int we_off_time;
++	int re_on_time;
++	int re_off_time;
++	int we_cycle_time;
++	int re_cycle_time;
++	int cs_pulse_width;
++	int access_time;
++
++	int clk_div;
++
++	u32 tim[5];             /* set by rfbi_convert_timings() */
++
++	int converted;
++};
++
++void omap_rfbi_write_command(const void *buf, u32 len);
++void omap_rfbi_read_data(void *buf, u32 len);
++void omap_rfbi_write_data(const void *buf, u32 len);
++void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
++		u16 x, u16 y,
++		u16 w, u16 h);
++int omap_rfbi_enable_te(bool enable, unsigned line);
++int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
++			     unsigned hs_pulse_time, unsigned vs_pulse_time,
++			     int hs_pol_inv, int vs_pol_inv, int extif_div);
++
++/* DSI */
++int dsi_vc_dcs_write(int channel, u8 *data, int len);
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
++int dsi_vc_send_null(int channel);
++
++/* Board specific data */
++struct omap_dss_display_config {
++	enum omap_display_type type;
++
++	union {
++		struct {
++			u8 data_lines;
++		} dpi;
++
++		struct {
++			u8 channel;
++			u8 data_lines;
++		} rfbi;
++
++		struct {
++			u8 datapairs;
++		} sdi;
++
++		struct {
++			u8 clk_lane;
++			u8 clk_pol;
++			u8 data1_lane;
++			u8 data1_pol;
++			u8 data2_lane;
++			u8 data2_pol;
++			unsigned long ddr_clk_hz;
++		} dsi;
++
++		struct {
++			enum omap_dss_venc_type type;
++		} venc;
++	} u;
++
++	int panel_reset_gpio;
++	int ctrl_reset_gpio;
++
++	const char *name;		/* for debug */
++	const char *ctrl_name;
++	const char *panel_name;
++
++	void *panel_data;
++	void *ctrl_data;
++
++	/* platform specific enable/disable */
++	int (*panel_enable)(struct omap_display *display);
++	void (*panel_disable)(struct omap_display *display);
++	int (*ctrl_enable)(struct omap_display *display);
++	void (*ctrl_disable)(struct omap_display *display);
++	int (*set_backlight)(struct omap_display *display,
++			int level);
++};
++
++struct device;
++
++/* Board specific data */
++struct  omap_dss_board_info {
++	unsigned (*get_last_off_on_transaction_id)(struct device *dev);
++	int (*dsi_power_up)(void);
++	void (*dsi_power_down)(void);
++	int num_displays;
++	struct omap_dss_display_config *displays[];
++};
++
++struct omap_ctrl {
++	struct module *owner;
++
++	const char *name;
++
++	int (*init)(struct omap_display *display);
++	void (*cleanup)(struct omap_display *display);
++	int (*enable)(struct omap_display *display);
++	void (*disable)(struct omap_display *display);
++	int (*suspend)(struct omap_display *display);
++	int (*resume)(struct omap_display *display);
++	void (*setup_update)(struct omap_display *display,
++			     u16 x, u16 y, u16 w, u16 h);
++
++	int (*enable_te)(struct omap_display *display, bool enable);
++
++	u8 (*get_rotate)(struct omap_display *display);
++	int (*set_rotate)(struct omap_display *display, u8 rotate);
++
++	bool (*get_mirror)(struct omap_display *display);
++	int (*set_mirror)(struct omap_display *display, bool enable);
++
++	int (*run_test)(struct omap_display *display, int test);
++	int (*memory_read)(struct omap_display *display,
++			void *buf, size_t size,
++			u16 x, u16 y, u16 w, u16 h);
++
++	u8 pixel_size;
++
++	struct rfbi_timings timings;
++
++	void *priv;
++};
++
++struct omap_video_timings {
++	/* Unit: pixels */
++	u16 x_res;
++	/* Unit: pixels */
++	u16 y_res;
++	/* Unit: KHz */
++	u32 pixel_clock;
++	/* Unit: pixel clocks */
++	u16 hsw;	/* Horizontal synchronization pulse width */
++	/* Unit: pixel clocks */
++	u16 hfp;	/* Horizontal front porch */
++	/* Unit: pixel clocks */
++	u16 hbp;	/* Horizontal back porch */
++	/* Unit: line clocks */
++	u16 vsw;	/* Vertical synchronization pulse width */
++	/* Unit: line clocks */
++	u16 vfp;	/* Vertical front porch */
++	/* Unit: line clocks */
++	u16 vbp;	/* Vertical back porch */
++
++};
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++/* Hardcoded timings for tv modes. Venc only uses these to
++ * identify the mode, and does not actually use the configs
++ * itself. However, the configs should be something that
++ * a normal monitor can also show */
++const extern struct omap_video_timings omap_dss_pal_timings;
++const extern struct omap_video_timings omap_dss_ntsc_timings;
++#endif
++
++struct omap_panel {
++	struct module *owner;
++
++	const char *name;
++
++	int (*init)(struct omap_display *display);
++	void (*cleanup)(struct omap_display *display);
++	int (*remove)(struct omap_display *display);
++	int (*enable)(struct omap_display *display);
++	void (*disable)(struct omap_display *display);
++	int (*suspend)(struct omap_display *display);
++	int (*resume)(struct omap_display *display);
++	int (*run_test)(struct omap_display *display, int test);
++
++	struct omap_video_timings timings;
++
++	int acbi;	/* ac-bias pin transitions per interrupt */
++	/* Unit: line clocks */
++	int acb;	/* ac-bias pin frequency */
++
++	enum omap_panel_config config;
++
++	u8 recommended_bpp;
++
++	void *priv;
++};
++
++/* XXX perhaps this should be removed */
++enum omap_dss_overlay_managers {
++	OMAP_DSS_OVL_MGR_LCD,
++	OMAP_DSS_OVL_MGR_TV,
++};
++
++struct omap_overlay_manager;
++
++struct omap_overlay_info {
++	bool enabled;
++
++	u32 paddr;
++	void __iomem *vaddr;
++	u16 screen_width;
++	u16 width;
++	u16 height;
++	enum omap_color_mode color_mode;
++	u8 rotation;
++	bool mirror;
++
++	u16 pos_x;
++	u16 pos_y;
++	u16 out_width;	/* if 0, out_width == width */
++	u16 out_height;	/* if 0, out_height == height */
++};
++
++enum omap_overlay_caps {
++	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
++	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
++};
++
++struct omap_overlay {
++	struct kobject kobj;
++	struct list_head list;
++
++	const char *name;
++	int id;
++	struct omap_overlay_manager *manager;
++	enum omap_color_mode supported_modes;
++	struct omap_overlay_info info;
++	enum omap_overlay_caps caps;
++
++	int (*set_manager)(struct omap_overlay *ovl,
++		struct omap_overlay_manager *mgr);
++	int (*unset_manager)(struct omap_overlay *ovl);
++
++	int (*set_overlay_info)(struct omap_overlay *ovl,
++			struct omap_overlay_info *info);
++	void (*get_overlay_info)(struct omap_overlay *ovl,
++			struct omap_overlay_info *info);
++};
++
++enum omap_overlay_manager_caps {
++	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
++};
++
++struct omap_overlay_manager {
++	struct kobject kobj;
++	struct list_head list;
++
++	const char *name;
++	int id;
++	enum omap_overlay_manager_caps caps;
++	struct omap_display *display;
++	int num_overlays;
++	struct omap_overlay **overlays;
++	enum omap_display_type supported_displays;
++
++	int (*set_display)(struct omap_overlay_manager *mgr,
++		struct omap_display *display);
++	int (*unset_display)(struct omap_overlay_manager *mgr);
++
++	int (*apply)(struct omap_overlay_manager *mgr);
++
++	void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
++	void (*set_trans_key)(struct omap_overlay_manager *mgr,
++		enum omap_dss_color_key_type type,
++		u32 trans_key);
++	void (*enable_trans_key)(struct omap_overlay_manager *mgr,
++		bool enable);
++};
++
++enum omap_display_caps {
++	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
++};
++
++enum omap_dss_update_mode {
++	OMAP_DSS_UPDATE_DISABLED = 0,
++	OMAP_DSS_UPDATE_AUTO,
++	OMAP_DSS_UPDATE_MANUAL,
++};
++
++enum omap_dss_display_state {
++	OMAP_DSS_DISPLAY_DISABLED = 0,
++	OMAP_DSS_DISPLAY_ACTIVE,
++	OMAP_DSS_DISPLAY_SUSPENDED,
++};
++
++struct omap_display {
++	struct kobject kobj;
++	struct list_head list;
++
++	/*atomic_t ref_count;*/
++	int ref_count;
++	/* helper variable for driver suspend/resume */
++	int activate_after_resume;
++
++	enum omap_display_type type;
++	const char *name;
++
++	enum omap_display_caps caps;
++
++	struct omap_overlay_manager *manager;
++
++	enum omap_dss_display_state state;
++
++	struct omap_dss_display_config hw_config; /* board specific data */
++	struct omap_ctrl *ctrl;			/* static common data */
++	struct omap_panel *panel;		/* static common data */
++
++	int (*enable)(struct omap_display *display);
++	void (*disable)(struct omap_display *display);
++
++	int (*suspend)(struct omap_display *display);
++	int (*resume)(struct omap_display *display);
++
++	void (*get_resolution)(struct omap_display *display,
++			u16 *xres, u16 *yres);
++	int (*get_recommended_bpp)(struct omap_display *display);
++
++	int (*check_timings)(struct omap_display *display,
++			struct omap_video_timings *timings);
++	void (*set_timings)(struct omap_display *display,
++			struct omap_video_timings *timings);
++	void (*get_timings)(struct omap_display *display,
++			struct omap_video_timings *timings);
++	int (*update)(struct omap_display *display,
++			       u16 x, u16 y, u16 w, u16 h);
++	int (*sync)(struct omap_display *display);
++	int (*wait_vsync)(struct omap_display *display);
++
++	int (*set_update_mode)(struct omap_display *display,
++			enum omap_dss_update_mode);
++	enum omap_dss_update_mode (*get_update_mode)
++		(struct omap_display *display);
++
++	int (*enable_te)(struct omap_display *display, bool enable);
++	int (*get_te)(struct omap_display *display);
++
++	u8 (*get_rotate)(struct omap_display *display);
++	int (*set_rotate)(struct omap_display *display, u8 rotate);
++
++	bool (*get_mirror)(struct omap_display *display);
++	int (*set_mirror)(struct omap_display *display, bool enable);
++
++	int (*run_test)(struct omap_display *display, int test);
++	int (*memory_read)(struct omap_display *display,
++			void *buf, size_t size,
++			u16 x, u16 y, u16 w, u16 h);
++
++	void (*configure_overlay)(struct omap_overlay *overlay);
++};
++
++int omap_dss_get_num_displays(void);
++struct omap_display *omap_dss_get_display(int no);
++void omap_dss_put_display(struct omap_display *display);
++
++void omap_dss_register_ctrl(struct omap_ctrl *ctrl);
++void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl);
++
++void omap_dss_register_panel(struct omap_panel *panel);
++void omap_dss_unregister_panel(struct omap_panel *panel);
++
++int omap_dss_get_num_overlay_managers(void);
++struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
++
++int omap_dss_get_num_overlays(void);
++struct omap_overlay *omap_dss_get_overlay(int num);
++
++typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
++int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
++int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
++
++int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
++int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
++		unsigned long timeout);
++
++#endif
+diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
+new file mode 100644
+index 0000000..f176562
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/vram.h
+@@ -0,0 +1,33 @@
++/*
++ * File: arch/arm/plat-omap/include/mach/vram.h
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++#ifndef __OMAPVRAM_H
++#define __OMAPVRAM_H
++
++#include <asm/types.h>
++
++extern int omap_vram_free(unsigned long paddr, size_t size);
++extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
++extern int omap_vram_reserve(unsigned long paddr, size_t size);
++extern void omap2_set_sdram_vram(u32 size, u32 start);
++extern void omap2_set_sram_vram(u32 size, u32 start);
++
++#endif
+diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
+new file mode 100644
+index 0000000..2047862
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/vrfb.h
+@@ -0,0 +1,47 @@
++/*
++ * File: arch/arm/plat-omap/include/mach/vrfb.h
++ *
++ * VRFB
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++#ifndef __VRFB_H
++#define __VRFB_H
++
++#define OMAP_VRFB_LINE_LEN 2048
++
++struct vrfb
++{
++	u8 context;
++	void __iomem *vaddr[4];
++	unsigned long paddr[4];
++	u16 xoffset;
++	u16 yoffset;
++	u8 bytespp;
++};
++
++extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
++		u8 bytespp);
++extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
++		u16 width, u16 height,
++		u8 bytespp);
++
++#endif /* __VRFB_H */
+diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
+new file mode 100644
+index 0000000..f24a110
+--- /dev/null
++++ b/arch/arm/plat-omap/vram.c
+@@ -0,0 +1,615 @@
++/*
++ * linux/arch/arm/plat-omap/vram.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++/*#define DEBUG*/
++
++#include <linux/vmalloc.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++#include <linux/dma-mapping.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/bootmem.h>
++#include <linux/omapfb.h>
++
++#include <asm/setup.h>
++
++#include <mach/sram.h>
++#include <mach/vram.h>
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define OMAP2_SRAM_START		0x40200000
++/* Maximum size, in reality this is smaller if SRAM is partially locked. */
++#define OMAP2_SRAM_SIZE			0xa0000		/* 640k */
++
++#define REG_MAP_SIZE(_page_cnt) \
++	((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
++#define REG_MAP_PTR(_rg, _page_nr) \
++	(((_rg)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
++#define REG_MAP_MASK(_page_nr) \
++	(1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
++
++#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
++
++/* postponed regions are used to temporarily store region information at boot
++ * time when we cannot yet allocate the region list */
++#define MAX_POSTPONED_REGIONS 10
++
++static int postponed_cnt __initdata;
++static struct {
++	unsigned long paddr;
++	size_t size;
++} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
++
++struct vram_alloc {
++	struct list_head list;
++	unsigned long paddr;
++	unsigned pages;
++};
++
++struct vram_region {
++	struct list_head list;
++	struct list_head alloc_list;
++	unsigned long paddr;
++	unsigned pages;
++};
++
++static DEFINE_MUTEX(region_mutex);
++static LIST_HEAD(region_list);
++
++static inline int region_mem_type(unsigned long paddr)
++{
++	if (paddr >= OMAP2_SRAM_START &&
++	    paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
++		return OMAPFB_MEMTYPE_SRAM;
++	else
++		return OMAPFB_MEMTYPE_SDRAM;
++}
++
++static struct vram_region *omap_vram_create_region(unsigned long paddr,
++		unsigned pages)
++{
++	struct vram_region *rm;
++
++	rm = kzalloc(sizeof(*rm), GFP_KERNEL);
++
++	if (rm) {
++		INIT_LIST_HEAD(&rm->alloc_list);
++		rm->paddr = paddr;
++		rm->pages = pages;
++	}
++
++	return rm;
++}
++
++#if 0
++static void omap_vram_free_region(struct vram_region *vr)
++{
++	list_del(&vr->list);
++	kfree(vr);
++}
++#endif
++
++static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr,
++		unsigned long paddr, unsigned pages)
++{
++	struct vram_alloc *va;
++	struct vram_alloc *new;
++
++	new = kzalloc(sizeof(*va), GFP_KERNEL);
++
++	if (!new)
++		return NULL;
++
++	new->paddr = paddr;
++	new->pages = pages;
++
++	list_for_each_entry(va, &vr->alloc_list, list) {
++		if (va->paddr > new->paddr)
++			break;
++	}
++
++	list_add_tail(&new->list, &va->list);
++
++	return new;
++}
++
++static void omap_vram_free_allocation(struct vram_alloc *va)
++{
++	list_del(&va->list);
++	kfree(va);
++}
++
++static __init int omap_vram_add_region_postponed(unsigned long paddr,
++		size_t size)
++{
++	if (postponed_cnt == MAX_POSTPONED_REGIONS)
++		return -ENOMEM;
++
++	postponed_regions[postponed_cnt].paddr = paddr;
++	postponed_regions[postponed_cnt].size = size;
++
++	++postponed_cnt;
++
++	return 0;
++}
++
++/* add/remove_region can be exported if there's need to add/remove regions
++ * runtime */
++static int omap_vram_add_region(unsigned long paddr, size_t size)
++{
++	struct vram_region *rm;
++	unsigned pages;
++
++	DBG("adding region paddr %08lx size %d\n",
++			paddr, size);
++
++	size &= PAGE_MASK;
++	pages = size >> PAGE_SHIFT;
++
++	rm = omap_vram_create_region(paddr, pages);
++	if (rm == NULL)
++		return -ENOMEM;
++
++	list_add(&rm->list, &region_list);
++
++	return 0;
++}
++
++int omap_vram_free(unsigned long paddr, size_t size)
++{
++	struct vram_region *rm;
++	struct vram_alloc *alloc;
++	unsigned start, end;
++
++	DBG("free mem paddr %08lx size %d\n", paddr, size);
++
++	size = PAGE_ALIGN(size);
++
++	mutex_lock(&region_mutex);
++
++	list_for_each_entry(rm, &region_list, list) {
++		list_for_each_entry(alloc, &rm->alloc_list, list) {
++			start = alloc->paddr;
++			end = alloc->paddr + (alloc->pages >> PAGE_SHIFT);
++
++			if (start >= paddr && end < paddr + size)
++				goto found;
++		}
++	}
++
++	mutex_unlock(&region_mutex);
++	return -EINVAL;
++
++found:
++	omap_vram_free_allocation(alloc);
++
++	mutex_unlock(&region_mutex);
++	return 0;
++}
++EXPORT_SYMBOL(omap_vram_free);
++
++static int _omap_vram_reserve(unsigned long paddr, unsigned pages)
++{
++	struct vram_region *rm;
++	struct vram_alloc *alloc;
++	size_t size;
++
++	size = pages << PAGE_SHIFT;
++
++	list_for_each_entry(rm, &region_list, list) {
++		unsigned long start, end;
++
++		DBG("checking region %lx %d\n", rm->paddr, rm->pages);
++
++		if (region_mem_type(rm->paddr) != region_mem_type(paddr))
++			continue;
++
++		start = rm->paddr;
++		end = start + (rm->pages << PAGE_SHIFT) - 1;
++		if (start > paddr || end < paddr + size - 1)
++			continue;
++
++		DBG("block ok, checking allocs\n");
++
++		list_for_each_entry(alloc, &rm->alloc_list, list) {
++			end = alloc->paddr - 1;
++
++			if (start <= paddr && end >= paddr + size - 1)
++				goto found;
++
++			start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
++		}
++
++		end = rm->paddr + (rm->pages << PAGE_SHIFT) - 1;
++
++		if (!(start <= paddr && end >= paddr + size - 1))
++			continue;
++found:
++		DBG("FOUND area start %lx, end %lx\n", start, end);
++
++		if (omap_vram_create_allocation(rm, paddr, pages) == NULL)
++			return -ENOMEM;
++
++		return 0;
++	}
++
++	return -ENOMEM;
++}
++
++int omap_vram_reserve(unsigned long paddr, size_t size)
++{
++	unsigned pages;
++	int r;
++
++	DBG("reserve mem paddr %08lx size %d\n", paddr, size);
++
++	size = PAGE_ALIGN(size);
++	pages = size >> PAGE_SHIFT;
++
++	mutex_lock(&region_mutex);
++
++	r = _omap_vram_reserve(paddr, pages);
++
++	mutex_unlock(&region_mutex);
++
++	return r;
++}
++EXPORT_SYMBOL(omap_vram_reserve);
++
++static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
++{
++	struct vram_region *rm;
++	struct vram_alloc *alloc;
++
++	list_for_each_entry(rm, &region_list, list) {
++		unsigned long start, end;
++
++		DBG("checking region %lx %d\n", rm->paddr, rm->pages);
++
++		if (region_mem_type(rm->paddr) != mtype)
++			continue;
++
++		start = rm->paddr;
++
++		list_for_each_entry(alloc, &rm->alloc_list, list) {
++			end = alloc->paddr;
++
++			if (end - start >= pages << PAGE_SHIFT)
++				goto found;
++
++			start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
++		}
++
++		end = rm->paddr + (rm->pages << PAGE_SHIFT);
++found:
++		if (end - start < pages << PAGE_SHIFT)
++			continue;
++
++		DBG("FOUND %lx, end %lx\n", start, end);
++
++		alloc = omap_vram_create_allocation(rm, start, pages);
++		if (alloc == NULL)
++			return -ENOMEM;
++
++		*paddr = start;
++
++		return 0;
++	}
++
++	return -ENOMEM;
++}
++
++int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
++{
++	unsigned pages;
++	int r;
++
++	BUG_ON(mtype > OMAPFB_MEMTYPE_MAX || !size);
++
++	DBG("alloc mem type %d size %d\n", mtype, size);
++
++	size = PAGE_ALIGN(size);
++	pages = size >> PAGE_SHIFT;
++
++	mutex_lock(&region_mutex);
++
++	r = _omap_vram_alloc(mtype, pages, paddr);
++
++	mutex_unlock(&region_mutex);
++
++	return r;
++}
++EXPORT_SYMBOL(omap_vram_alloc);
++
++#ifdef CONFIG_PROC_FS
++static void *r_next(struct seq_file *m, void *v, loff_t *pos)
++{
++	struct list_head *l = v;
++
++	(*pos)++;
++
++	if (list_is_last(l, &region_list))
++		return NULL;
++
++	return l->next;
++}
++
++static void *r_start(struct seq_file *m, loff_t *pos)
++{
++	loff_t p = *pos;
++	struct list_head *l = &region_list;
++
++	mutex_lock(&region_mutex);
++
++	do {
++		l = l->next;
++		if (l == &region_list)
++			return NULL;
++	} while (p--);
++
++	return l;
++}
++
++static void r_stop(struct seq_file *m, void *v)
++{
++	mutex_unlock(&region_mutex);
++}
++
++static int r_show(struct seq_file *m, void *v)
++{
++	struct vram_region *vr;
++	struct vram_alloc *va;
++	unsigned size;
++
++	vr = list_entry(v, struct vram_region, list);
++
++	size = vr->pages << PAGE_SHIFT;
++
++	seq_printf(m, "%08lx-%08lx (%d bytes)\n",
++			vr->paddr, vr->paddr + size - 1,
++			size);
++
++	list_for_each_entry(va, &vr->alloc_list, list) {
++		size = va->pages << PAGE_SHIFT;
++		seq_printf(m, "    %08lx-%08lx (%d bytes)\n",
++				va->paddr, va->paddr + size - 1,
++				size);
++	}
++
++
++
++	return 0;
++}
++
++static const struct seq_operations resource_op = {
++	.start	= r_start,
++	.next	= r_next,
++	.stop	= r_stop,
++	.show	= r_show,
++};
++
++static int vram_open(struct inode *inode, struct file *file)
++{
++	return seq_open(file, &resource_op);
++}
++
++static const struct file_operations proc_vram_operations = {
++	.open		= vram_open,
++	.read		= seq_read,
++	.llseek		= seq_lseek,
++	.release	= seq_release,
++};
++
++static int __init omap_vram_create_proc(void)
++{
++	proc_create("omap-vram", 0, NULL, &proc_vram_operations);
++
++	return 0;
++}
++#endif
++
++static __init int omap_vram_init(void)
++{
++	int i, r;
++
++	for (i = 0; i < postponed_cnt; i++)
++		omap_vram_add_region(postponed_regions[i].paddr,
++				postponed_regions[i].size);
++
++#ifdef CONFIG_PROC_FS
++	r = omap_vram_create_proc();
++	if (r)
++		return -ENOMEM;
++#endif
++
++	return 0;
++}
++
++arch_initcall(omap_vram_init);
++
++/* boottime vram alloc stuff */
++
++/* set from board file */
++static u32 omapfb_sram_vram_start __initdata;
++static u32 omapfb_sram_vram_size __initdata;
++
++/* set from board file */
++static u32 omapfb_sdram_vram_start __initdata;
++static u32 omapfb_sdram_vram_size __initdata;
++
++/* set from kernel cmdline */
++static u32 omapfb_def_sdram_vram_size __initdata;
++static u32 omapfb_def_sdram_vram_start __initdata;
++
++static void __init omapfb_early_vram(char **p)
++{
++	omapfb_def_sdram_vram_size = memparse(*p, p);
++	if (**p == ',')
++		omapfb_def_sdram_vram_start = simple_strtoul((*p) + 1, p, 16);
++
++	printk("omapfb_early_vram, %d, 0x%x\n",
++			omapfb_def_sdram_vram_size,
++			omapfb_def_sdram_vram_start);
++}
++__early_param("vram=", omapfb_early_vram);
++
++/*
++ * Called from map_io. We need to call to this early enough so that we
++ * can reserve the fixed SDRAM regions before VM could get hold of them.
++ */
++void __init omapfb_reserve_sdram(void)
++{
++	struct bootmem_data	*bdata;
++	unsigned long		sdram_start, sdram_size;
++	u32 paddr;
++	u32 size = 0;
++
++	/* cmdline arg overrides the board file definition */
++	if (omapfb_def_sdram_vram_size) {
++		size = omapfb_def_sdram_vram_size;
++		paddr = omapfb_def_sdram_vram_start;
++	}
++
++	if (!size) {
++		size = omapfb_sdram_vram_size;
++		paddr = omapfb_sdram_vram_start;
++	}
++
++#ifdef CONFIG_OMAP2_DSS_VRAM_SIZE
++	if (!size) {
++		size = CONFIG_OMAP2_DSS_VRAM_SIZE * 1024 * 1024;
++		paddr = 0;
++	}
++#endif
++
++	if (!size)
++		return;
++
++	size = PAGE_ALIGN(size);
++
++	bdata = NODE_DATA(0)->bdata;
++	sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
++	sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
++
++	if (paddr) {
++		if ((paddr & ~PAGE_MASK) || paddr < sdram_start ||
++				paddr + size > sdram_start + sdram_size) {
++			printk(KERN_ERR "Illegal SDRAM region for VRAM\n");
++			return;
++		}
++
++		reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
++	} else {
++		if (size > sdram_size) {
++			printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
++			return;
++		}
++
++		paddr = virt_to_phys(alloc_bootmem_pages(size));
++		BUG_ON(paddr & ~PAGE_MASK);
++	}
++
++	omap_vram_add_region_postponed(paddr, size);
++
++	pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
++}
++
++/*
++ * Called at sram init time, before anything is pushed to the SRAM stack.
++ * Because of the stack scheme, we will allocate everything from the
++ * start of the lowest address region to the end of SRAM. This will also
++ * include padding for page alignment and possible holes between regions.
++ *
++ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
++ * this point, since the driver built as a module would have problem with
++ * freeing / reallocating the regions.
++ */
++unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
++				  unsigned long sram_vstart,
++				  unsigned long sram_size,
++				  unsigned long pstart_avail,
++				  unsigned long size_avail)
++{
++	unsigned long			pend_avail;
++	unsigned long			reserved;
++	u32 paddr;
++	u32 size;
++
++	paddr = omapfb_sram_vram_start;
++	size = omapfb_sram_vram_size;
++
++	if (!size)
++		return 0;
++
++	reserved = 0;
++	pend_avail = pstart_avail + size_avail;
++
++	if (!paddr) {
++		/* Dynamic allocation */
++		if ((size_avail & PAGE_MASK) < size) {
++			printk(KERN_ERR "Not enough SRAM for VRAM\n");
++			return 0;
++		}
++		size_avail = (size_avail - size) & PAGE_MASK;
++		paddr = pstart_avail + size_avail;
++	}
++
++	if (paddr < sram_pstart ||
++			paddr + size > sram_pstart + sram_size) {
++		printk(KERN_ERR "Illegal SRAM region for VRAM\n");
++		return 0;
++	}
++
++	/* Reserve everything above the start of the region. */
++	if (pend_avail - paddr > reserved)
++		reserved = pend_avail - paddr;
++	size_avail = pend_avail - reserved - pstart_avail;
++
++	omap_vram_add_region_postponed(paddr, size);
++
++	if (reserved)
++		pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
++
++	return reserved;
++}
++
++void __init omap2_set_sdram_vram(u32 size, u32 start)
++{
++	omapfb_sdram_vram_start = start;
++	omapfb_sdram_vram_size = size;
++}
++
++void __init omap2_set_sram_vram(u32 size, u32 start)
++{
++	omapfb_sram_vram_start = start;
++	omapfb_sram_vram_size = size;
++}
++
++#endif
++
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+new file mode 100644
+index 0000000..7e0f8fc
+--- /dev/null
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -0,0 +1,159 @@
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++
++#include <mach/io.h>
++#include <mach/vrfb.h>
++
++/*#define DEBUG*/
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "VRFB: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define SMS_ROT_VIRT_BASE(context, rot) \
++	(((context >= 4) ? 0xD0000000 : 0x70000000) \
++	 | 0x4000000 * (context) \
++	 | 0x1000000 * (rot))
++
++#define OMAP_VRFB_SIZE			(2048 * 2048 * 4)
++
++#define VRFB_PAGE_WIDTH_EXP	5 /* Assuming SDRAM pagesize= 1024 */
++#define VRFB_PAGE_HEIGHT_EXP	5 /* 1024 = 2^5 * 2^5 */
++#define VRFB_PAGE_WIDTH		(1 << VRFB_PAGE_WIDTH_EXP)
++#define VRFB_PAGE_HEIGHT	(1 << VRFB_PAGE_HEIGHT_EXP)
++#define SMS_IMAGEHEIGHT_OFFSET	16
++#define SMS_IMAGEWIDTH_OFFSET	0
++#define SMS_PH_OFFSET		8
++#define SMS_PW_OFFSET		4
++#define SMS_PS_OFFSET		0
++
++#define OMAP_SMS_BASE		0x6C000000
++#define SMS_ROT_CONTROL(context)	(OMAP_SMS_BASE + 0x180 + 0x10 * context)
++#define SMS_ROT_SIZE(context)		(OMAP_SMS_BASE + 0x184 + 0x10 * context)
++#define SMS_ROT_PHYSICAL_BA(context)	(OMAP_SMS_BASE + 0x188 + 0x10 * context)
++
++#define VRFB_NUM_CTXS 12
++/* bitmap of reserved contexts */
++static unsigned ctx_map;
++
++void omap_vrfb_adjust_size(u16 *width, u16 *height,
++		u8 bytespp)
++{
++	*width = ALIGN(*width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
++	*height = ALIGN(*height, VRFB_PAGE_HEIGHT);
++}
++EXPORT_SYMBOL(omap_vrfb_adjust_size);
++
++void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
++		u16 width, u16 height,
++		u8 bytespp)
++{
++	unsigned pixel_size_exp;
++	u16 vrfb_width;
++	u16 vrfb_height;
++	u8 ctx = vrfb->context;
++
++	DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
++			width, height, bytespp);
++
++	if (bytespp == 4)
++		pixel_size_exp = 2;
++	else if (bytespp == 2)
++		pixel_size_exp = 1;
++	else
++		BUG();
++
++	vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
++	vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
++
++	DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
++
++	omap_writel(paddr, SMS_ROT_PHYSICAL_BA(ctx));
++	omap_writel((vrfb_width << SMS_IMAGEWIDTH_OFFSET) |
++			(vrfb_height << SMS_IMAGEHEIGHT_OFFSET),
++			SMS_ROT_SIZE(ctx));
++
++	omap_writel(pixel_size_exp << SMS_PS_OFFSET |
++			VRFB_PAGE_WIDTH_EXP  << SMS_PW_OFFSET |
++			VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET,
++			SMS_ROT_CONTROL(ctx));
++
++	DBG("vrfb offset pixels %d, %d\n",
++			vrfb_width - width, vrfb_height - height);
++
++	vrfb->xoffset = vrfb_width - width;
++	vrfb->yoffset = vrfb_height - height;
++	vrfb->bytespp = bytespp;
++}
++EXPORT_SYMBOL(omap_vrfb_setup);
++
++void omap_vrfb_release_ctx(struct vrfb *vrfb)
++{
++	int rot;
++
++	if (vrfb->context == 0xff)
++		return;
++
++	DBG("release ctx %d\n", vrfb->context);
++
++	ctx_map &= ~(1 << vrfb->context);
++
++	for (rot = 0; rot < 4; ++rot) {
++		if(vrfb->paddr[rot]) {
++			release_mem_region(vrfb->paddr[rot], OMAP_VRFB_SIZE);
++			vrfb->paddr[rot] = 0;
++		}
++	}
++
++	vrfb->context = 0xff;
++}
++EXPORT_SYMBOL(omap_vrfb_release_ctx);
++
++int omap_vrfb_request_ctx(struct vrfb *vrfb)
++{
++	int rot;
++	u32 paddr;
++	u8 ctx;
++
++	DBG("request ctx\n");
++
++	for (ctx = 0; ctx < VRFB_NUM_CTXS; ++ctx)
++		if ((ctx_map & (1 << ctx)) == 0)
++			break;
++
++	if (ctx == VRFB_NUM_CTXS) {
++		printk(KERN_ERR "vrfb: no free contexts\n");
++		return -EBUSY;
++	}
++
++	DBG("found free ctx %d\n", ctx);
++
++	ctx_map |= 1 << ctx;
++
++	memset(vrfb, 0, sizeof(*vrfb));
++
++	vrfb->context = ctx;
++
++	for (rot = 0; rot < 4; ++rot) {
++		paddr = SMS_ROT_VIRT_BASE(ctx, rot);
++		if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) {
++			printk(KERN_ERR "vrfb: failed to reserve VRFB "
++					"area for ctx %d, rotation %d\n",
++					ctx, rot * 90);
++			omap_vrfb_release_ctx(vrfb);
++			return -ENOMEM;
++		}
++
++		vrfb->paddr[rot] = paddr;
++
++		DBG("VRFB %d/%d: %lx\n", ctx, rot*90, vrfb->paddr[rot]);
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(omap_vrfb_request_ctx);
++
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index fb19803..8b3752b 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -2132,6 +2132,7 @@ config FB_MX3
+          an LCD display with your i.MX31 system, say Y here.
+ 
+ source "drivers/video/omap/Kconfig"
++source "drivers/video/omap2/Kconfig"
+ 
+ source "drivers/video/backlight/Kconfig"
+ source "drivers/video/display/Kconfig"
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index 2a998ca..1db8dd4 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_SM501)            += sm501fb.o
+ obj-$(CONFIG_FB_XILINX)           += xilinxfb.o
+ obj-$(CONFIG_FB_SH_MOBILE_LCDC)	  += sh_mobile_lcdcfb.o
+ obj-$(CONFIG_FB_OMAP)             += omap/
++obj-$(CONFIG_OMAP2_DSS)           += omap2/
+ obj-$(CONFIG_XEN_FBDEV_FRONTEND)  += xen-fbfront.o
+ obj-$(CONFIG_FB_CARMINE)          += carminefb.o
+ obj-$(CONFIG_FB_MB862XX)	  += mb862xx/
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+new file mode 100644
+index 0000000..89bf210
+--- /dev/null
++++ b/drivers/video/omap2/Kconfig
+@@ -0,0 +1,3 @@
++source "drivers/video/omap2/dss/Kconfig"
++source "drivers/video/omap2/displays/Kconfig"
++source "drivers/video/omap2/omapfb/Kconfig"
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+new file mode 100644
+index 0000000..72134db
+--- /dev/null
++++ b/drivers/video/omap2/Makefile
+@@ -0,0 +1,4 @@
++# OMAP2/3 Display Subsystem
++obj-y += dss/
++obj-y += displays/
++obj-y += omapfb/
+diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
+new file mode 100644
+index 0000000..f2ce068
+--- /dev/null
++++ b/drivers/video/omap2/dss/Kconfig
+@@ -0,0 +1,89 @@
++menuconfig OMAP2_DSS
++        tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
++        depends on ARCH_OMAP2 || ARCH_OMAP3
++        help
++          OMAP2/3 Display Subsystem support.
++
++if OMAP2_DSS
++
++config OMAP2_DSS_VRAM_SIZE
++	int "VRAM size (MB)"
++	range 0 32
++	default 4
++	help
++	  The amount of SDRAM to reserve at boot time for video RAM use.
++	  This VRAM will be used by omapfb and other drivers that need
++	  large continuous RAM area for video use.
++
++	  You can also set this with "vram=<bytes>" kernel argument, or
++	  in the board file.
++
++config OMAP2_DSS_DEBUG_SUPPORT
++        bool "Debug support"
++	default y
++	help
++	  This enables debug messages. You need to enable printing
++	  with 'debug' module parameter.
++
++config OMAP2_DSS_RFBI
++	bool "RFBI support"
++        default n
++	help
++	  MIPI DBI, or RFBI (Remote Framebuffer Interface), support.
++
++config OMAP2_DSS_VENC
++	bool "VENC support"
++        default y
++	help
++	  OMAP Video Encoder support.
++
++config OMAP2_DSS_SDI
++	bool "SDI support"
++	depends on ARCH_OMAP3
++        default n
++	help
++	  SDI (Serial Display Interface) support.
++
++config OMAP2_DSS_DSI
++	bool "DSI support"
++	depends on ARCH_OMAP3
++        default n
++	help
++	  MIPI DSI support.
++
++config OMAP2_DSS_USE_DSI_PLL
++	bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
++	default n
++	depends on OMAP2_DSS_DSI
++	help
++	  Use DSI PLL to generate pixel clock.  Currently only for DPI output.
++	  DSI PLL can be used to generate higher and more precise pixel clocks.
++
++config OMAP2_DSS_FAKE_VSYNC
++	bool "Fake VSYNC irq from manual update displays"
++	default n
++	help
++	  If this is selected, DSI will generate a fake DISPC VSYNC interrupt
++	  when DSI has sent a frame. This is only needed with DSI or RFBI
++	  displays using manual mode, and you want VSYNC to, for example,
++	  time animation.
++
++config OMAP2_DSS_MIN_FCK_PER_PCK
++	int "Minimum FCK/PCK ratio (for scaling)"
++	range 0 32
++	default 0
++	help
++	  This can be used to adjust the minimum FCK/PCK ratio.
++
++	  With this you can make sure that DISPC FCK is at least
++	  n x PCK. Video plane scaling requires higher FCK than
++	  normally.
++
++	  If this is set to 0, there's no extra constraint on the
++	  DISPC FCK. However, the FCK will at minimum be
++	  2xPCK (if active matrix) or 3xPCK (if passive matrix).
++
++	  Max FCK is 173MHz, so this doesn't work if your PCK
++	  is very high.
++
++endif
+diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
+new file mode 100644
+index 0000000..980c72c
+--- /dev/null
++++ b/drivers/video/omap2/dss/Makefile
+@@ -0,0 +1,6 @@
++obj-$(CONFIG_OMAP2_DSS) += omapdss.o
++omapdss-y := core.o dss.o dispc.o dpi.o display.o manager.o overlay.o
++omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
++omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
++omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
++omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
+diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
+new file mode 100644
+index 0000000..ae7cd06
+--- /dev/null
++++ b/drivers/video/omap2/dss/core.c
+@@ -0,0 +1,641 @@
++/*
++ * linux/drivers/video/omap2/dss/core.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "CORE"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/seq_file.h>
++#include <linux/debugfs.h>
++#include <linux/io.h>
++
++#include <mach/display.h>
++#include <mach/clock.h>
++
++#include "dss.h"
++
++static struct {
++	struct platform_device *pdev;
++	unsigned	ctx_id;
++
++	struct clk      *dss_ick;
++	struct clk	*dss1_fck;
++	struct clk	*dss2_fck;
++	struct clk      *dss_54m_fck;
++	struct clk	*dss_96m_fck;
++	unsigned	num_clks_enabled;
++} core;
++
++static void dss_clk_enable_all_no_ctx(void);
++static void dss_clk_disable_all_no_ctx(void);
++static void dss_clk_enable_no_ctx(enum dss_clock clks);
++static void dss_clk_disable_no_ctx(enum dss_clock clks);
++
++static char *def_disp_name;
++module_param_named(def_disp, def_disp_name, charp, 0);
++MODULE_PARM_DESC(def_disp_name, "default display name");
++
++#ifdef DEBUG
++unsigned int dss_debug;
++module_param_named(debug, dss_debug, bool, 0644);
++#endif
++
++/* CONTEXT */
++static unsigned dss_get_ctx_id(void)
++{
++	struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++
++	if (!pdata->get_last_off_on_transaction_id)
++		return 0;
++
++	return pdata->get_last_off_on_transaction_id(&core.pdev->dev);
++}
++
++int dss_need_ctx_restore(void)
++{
++	int id = dss_get_ctx_id();
++
++	if (id != core.ctx_id) {
++		DSSDBG("ctx id %u -> id %u\n",
++				core.ctx_id, id);
++		core.ctx_id = id;
++		return 1;
++	} else {
++		return 0;
++	}
++}
++
++static void save_all_ctx(void)
++{
++	DSSDBG("save context\n");
++
++	dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	dss_save_context();
++	dispc_save_context();
++#ifdef CONFIG_OMAP2_DSS_DSI
++	dsi_save_context();
++#endif
++
++	dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++static void restore_all_ctx(void)
++{
++	DSSDBG("restore context\n");
++
++	dss_clk_enable_all_no_ctx();
++
++	dss_restore_context();
++	dispc_restore_context();
++#ifdef CONFIG_OMAP2_DSS_DSI
++	dsi_restore_context();
++#endif
++
++	dss_clk_disable_all_no_ctx();
++}
++
++/* CLOCKS */
++void dss_dump_clocks(struct seq_file *s)
++{
++	int i;
++	struct clk *clocks[5] = {
++		core.dss_ick,
++		core.dss1_fck,
++		core.dss2_fck,
++		core.dss_54m_fck,
++		core.dss_96m_fck
++	};
++
++	seq_printf(s, "- dss -\n");
++
++	seq_printf(s, "internal clk count\t%u\n", core.num_clks_enabled);
++
++	for (i = 0; i < 5; i++) {
++		if (!clocks[i])
++			continue;
++		seq_printf(s, "%-15s\t%lu\t%d\n",
++				clocks[i]->name,
++				clk_get_rate(clocks[i]),
++				clocks[i]->usecount);
++	}
++}
++
++static int dss_get_clocks(void)
++{
++	const struct {
++		struct clk **clock;
++		char *omap2_name;
++		char *omap3_name;
++	} clocks[5] = {
++		{ &core.dss_ick, "dss_ick", "dss_ick" },	/* L3 & L4 ick */
++		{ &core.dss1_fck, "dss1_fck", "dss1_alwon_fck" },
++		{ &core.dss2_fck, "dss2_fck", "dss2_alwon_fck" },
++		{ &core.dss_54m_fck, "dss_54m_fck", "dss_tv_fck" },
++		{ &core.dss_96m_fck, NULL, "dss_96m_fck" },
++	};
++
++	int r = 0;
++	int i;
++	const int num_clocks = 5;
++
++	for (i = 0; i < num_clocks; i++)
++		*clocks[i].clock = NULL;
++
++	for (i = 0; i < num_clocks; i++) {
++		struct clk *clk;
++		const char *clk_name;
++
++		clk_name = cpu_is_omap34xx() ? clocks[i].omap3_name
++			: clocks[i].omap2_name;
++
++		if (!clk_name)
++			continue;
++
++		clk = clk_get(NULL, clk_name);
++
++		if (IS_ERR(clk)) {
++			DSSERR("can't get clock %s", clk_name);
++			r = PTR_ERR(clk);
++			goto err;
++		}
++
++		DSSDBG("clk %s, rate %ld\n",
++				clk_name, clk_get_rate(clk));
++
++		*clocks[i].clock = clk;
++	}
++
++	return 0;
++
++err:
++	for (i = 0; i < num_clocks; i++) {
++		if (!IS_ERR(*clocks[i].clock))
++			clk_put(*clocks[i].clock);
++	}
++
++	return r;
++}
++
++static void dss_put_clocks(void)
++{
++	if (core.dss_96m_fck)
++		clk_put(core.dss_96m_fck);
++	clk_put(core.dss_54m_fck);
++	clk_put(core.dss1_fck);
++	clk_put(core.dss2_fck);
++	clk_put(core.dss_ick);
++}
++
++unsigned long dss_clk_get_rate(enum dss_clock clk)
++{
++	switch (clk) {
++	case DSS_CLK_ICK:
++		return clk_get_rate(core.dss_ick);
++	case DSS_CLK_FCK1:
++		return clk_get_rate(core.dss1_fck);
++	case DSS_CLK_FCK2:
++		return clk_get_rate(core.dss2_fck);
++	case DSS_CLK_54M:
++		return clk_get_rate(core.dss_54m_fck);
++	case DSS_CLK_96M:
++		return clk_get_rate(core.dss_96m_fck);
++	}
++
++	BUG();
++	return 0;
++}
++
++static unsigned count_clk_bits(enum dss_clock clks)
++{
++	unsigned num_clks = 0;
++
++	if (clks & DSS_CLK_ICK)
++		++num_clks;
++	if (clks & DSS_CLK_FCK1)
++		++num_clks;
++	if (clks & DSS_CLK_FCK2)
++		++num_clks;
++	if (clks & DSS_CLK_54M)
++		++num_clks;
++	if (clks & DSS_CLK_96M)
++		++num_clks;
++
++	return num_clks;
++}
++
++static void dss_clk_enable_no_ctx(enum dss_clock clks)
++{
++	unsigned num_clks = count_clk_bits(clks);
++
++	if (clks & DSS_CLK_ICK)
++		clk_enable(core.dss_ick);
++	if (clks & DSS_CLK_FCK1)
++		clk_enable(core.dss1_fck);
++	if (clks & DSS_CLK_FCK2)
++		clk_enable(core.dss2_fck);
++	if (clks & DSS_CLK_54M)
++		clk_enable(core.dss_54m_fck);
++	if (clks & DSS_CLK_96M)
++		clk_enable(core.dss_96m_fck);
++
++	core.num_clks_enabled += num_clks;
++}
++
++void dss_clk_enable(enum dss_clock clks)
++{
++	dss_clk_enable_no_ctx(clks);
++
++	if (cpu_is_omap34xx() && dss_need_ctx_restore())
++		restore_all_ctx();
++}
++
++static void dss_clk_disable_no_ctx(enum dss_clock clks)
++{
++	unsigned num_clks = count_clk_bits(clks);
++
++	if (clks & DSS_CLK_ICK)
++		clk_disable(core.dss_ick);
++	if (clks & DSS_CLK_FCK1)
++		clk_disable(core.dss1_fck);
++	if (clks & DSS_CLK_FCK2)
++		clk_disable(core.dss2_fck);
++	if (clks & DSS_CLK_54M)
++		clk_disable(core.dss_54m_fck);
++	if (clks & DSS_CLK_96M)
++		clk_disable(core.dss_96m_fck);
++
++	core.num_clks_enabled -= num_clks;
++}
++
++void dss_clk_disable(enum dss_clock clks)
++{
++	if (cpu_is_omap34xx()) {
++		unsigned num_clks = count_clk_bits(clks);
++
++		BUG_ON(core.num_clks_enabled < num_clks);
++
++		if (core.num_clks_enabled == num_clks)
++			save_all_ctx();
++	}
++
++	dss_clk_disable_no_ctx(clks);
++}
++
++static void dss_clk_enable_all_no_ctx(void)
++{
++	enum dss_clock clks;
++
++	clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++	if (cpu_is_omap34xx())
++		clks |= DSS_CLK_96M;
++	dss_clk_enable_no_ctx(clks);
++}
++
++static void dss_clk_disable_all_no_ctx(void)
++{
++	enum dss_clock clks;
++
++	clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++	if (cpu_is_omap34xx())
++		clks |= DSS_CLK_96M;
++	dss_clk_disable_no_ctx(clks);
++}
++
++static void dss_clk_disable_all(void)
++{
++	enum dss_clock clks;
++
++	clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++	if (cpu_is_omap34xx())
++		clks |= DSS_CLK_96M;
++	dss_clk_disable(clks);
++}
++
++/* DEBUGFS */
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++static void dss_debug_dump_clocks(struct seq_file *s)
++{
++	dss_dump_clocks(s);
++	dispc_dump_clocks(s);
++#ifdef CONFIG_OMAP2_DSS_DSI
++	dsi_dump_clocks(s);
++#endif
++}
++
++static int dss_debug_show(struct seq_file *s, void *unused)
++{
++	void (*func)(struct seq_file *) = s->private;
++	func(s);
++	return 0;
++}
++
++static int dss_debug_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, dss_debug_show, inode->i_private);
++}
++
++static const struct file_operations dss_debug_fops = {
++	.open           = dss_debug_open,
++	.read           = seq_read,
++	.llseek         = seq_lseek,
++	.release        = single_release,
++};
++
++static struct dentry *dss_debugfs_dir;
++
++static int dss_initialize_debugfs(void)
++{
++	dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
++	if (IS_ERR(dss_debugfs_dir)) {
++		int err = PTR_ERR(dss_debugfs_dir);
++		dss_debugfs_dir = NULL;
++		return err;
++	}
++
++	debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
++			&dss_debug_dump_clocks, &dss_debug_fops);
++
++	debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
++			&dss_dump_regs, &dss_debug_fops);
++	debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
++			&dispc_dump_regs, &dss_debug_fops);
++#ifdef CONFIG_OMAP2_DSS_RFBI
++	debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
++			&rfbi_dump_regs, &dss_debug_fops);
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++	debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
++			&dsi_dump_regs, &dss_debug_fops);
++#endif
++	return 0;
++}
++
++static void dss_uninitialize_debugfs(void)
++{
++	if (dss_debugfs_dir)
++		debugfs_remove_recursive(dss_debugfs_dir);
++}
++#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
++
++
++/* DSI powers */
++int dss_dsi_power_up(void)
++{
++	struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++
++	if (!pdata->dsi_power_up)
++		return 0; /* presume power is always on then */
++
++	return pdata->dsi_power_up();
++}
++
++void dss_dsi_power_down(void)
++{
++	struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++
++	if (!pdata->dsi_power_down)
++		return;
++
++	pdata->dsi_power_down();
++}
++
++
++
++/* PLATFORM DEVICE */
++static int omap_dss_probe(struct platform_device *pdev)
++{
++	int skip_init = 0;
++	int r;
++
++	core.pdev = pdev;
++
++	r = dss_get_clocks();
++	if (r)
++		goto fail0;
++
++	dss_clk_enable_all_no_ctx();
++
++	core.ctx_id = dss_get_ctx_id();
++	DSSDBG("initial ctx id %u\n", core.ctx_id);
++
++#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
++	/* DISPC_CONTROL */
++	if (omap_readl(0x48050440) & 1)	/* LCD enabled? */
++		skip_init = 1;
++#endif
++
++	r = dss_init(skip_init);
++	if (r) {
++		DSSERR("Failed to initialize DSS\n");
++		goto fail0;
++	}
++
++#ifdef CONFIG_OMAP2_DSS_RFBI
++	r = rfbi_init();
++	if (r) {
++		DSSERR("Failed to initialize rfbi\n");
++		goto fail0;
++	}
++#endif
++
++	r = dpi_init();
++	if (r) {
++		DSSERR("Failed to initialize dpi\n");
++		goto fail0;
++	}
++
++	r = dispc_init();
++	if (r) {
++		DSSERR("Failed to initialize dispc\n");
++		goto fail0;
++	}
++#ifdef CONFIG_OMAP2_DSS_VENC
++	r = venc_init();
++	if (r) {
++		DSSERR("Failed to initialize venc\n");
++		goto fail0;
++	}
++#endif
++	if (cpu_is_omap34xx()) {
++#ifdef CONFIG_OMAP2_DSS_SDI
++		r = sdi_init(skip_init);
++		if (r) {
++			DSSERR("Failed to initialize SDI\n");
++			goto fail0;
++		}
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++		r = dsi_init();
++		if (r) {
++			DSSERR("Failed to initialize DSI\n");
++			goto fail0;
++		}
++#endif
++	}
++
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++	r = dss_initialize_debugfs();
++	if (r)
++		goto fail0;
++#endif
++
++	dss_init_displays(pdev);
++	dss_init_overlay_managers(pdev);
++	dss_init_overlays(pdev, def_disp_name);
++
++	dss_clk_disable_all();
++
++	return 0;
++
++	/* XXX fail correctly */
++fail0:
++	return r;
++}
++
++static int omap_dss_remove(struct platform_device *pdev)
++{
++	int c;
++
++	dss_uninit_overlays(pdev);
++	dss_uninit_overlay_managers(pdev);
++	dss_uninit_displays(pdev);
++
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++	dss_uninitialize_debugfs();
++#endif
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++	venc_exit();
++#endif
++	dispc_exit();
++	dpi_exit();
++#ifdef CONFIG_OMAP2_DSS_RFBI
++	rfbi_exit();
++#endif
++	if (cpu_is_omap34xx()) {
++#ifdef CONFIG_OMAP2_DSS_DSI
++		dsi_exit();
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++		sdi_exit();
++#endif
++	}
++
++	dss_exit();
++
++	/* these should be removed at some point */
++	c = core.dss_ick->usecount;
++	if (c > 0) {
++		DSSERR("warning: dss_ick usecount %d, disabling\n", c);
++		while (c-- > 0)
++			clk_disable(core.dss_ick);
++	}
++
++	c = core.dss1_fck->usecount;
++	if (c > 0) {
++		DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
++		while (c-- > 0)
++			clk_disable(core.dss1_fck);
++	}
++
++	c = core.dss2_fck->usecount;
++	if (c > 0) {
++		DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
++		while (c-- > 0)
++			clk_disable(core.dss2_fck);
++	}
++
++	c = core.dss_54m_fck->usecount;
++	if (c > 0) {
++		DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
++		while (c-- > 0)
++			clk_disable(core.dss_54m_fck);
++	}
++
++	if (core.dss_96m_fck) {
++		c = core.dss_96m_fck->usecount;
++		if (c > 0) {
++			DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
++					c);
++			while (c-- > 0)
++				clk_disable(core.dss_96m_fck);
++		}
++	}
++
++	dss_put_clocks();
++
++	return 0;
++}
++
++static void omap_dss_shutdown(struct platform_device *pdev)
++{
++	DSSDBG("shutdown\n");
++}
++
++static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	DSSDBG("suspend %d\n", state.event);
++
++	return dss_suspend_all_displays();
++}
++
++static int omap_dss_resume(struct platform_device *pdev)
++{
++	DSSDBG("resume\n");
++
++	return dss_resume_all_displays();
++}
++
++static struct platform_driver omap_dss_driver = {
++	.probe          = omap_dss_probe,
++	.remove         = omap_dss_remove,
++	.shutdown	= omap_dss_shutdown,
++	.suspend	= omap_dss_suspend,
++	.resume		= omap_dss_resume,
++	.driver         = {
++		.name   = "omapdss",
++		.owner  = THIS_MODULE,
++	},
++};
++
++static int __init omap_dss_init(void)
++{
++	return platform_driver_register(&omap_dss_driver);
++}
++
++static void __exit omap_dss_exit(void)
++{
++	platform_driver_unregister(&omap_dss_driver);
++}
++
++subsys_initcall(omap_dss_init);
++module_exit(omap_dss_exit);
++
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+new file mode 100644
+index 0000000..ffb5648
+--- /dev/null
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -0,0 +1,2968 @@
++/*
++ * linux/drivers/video/omap2/dss/dispc.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DISPC"
++
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/jiffies.h>
++#include <linux/seq_file.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++
++#include <mach/sram.h>
++#include <mach/board.h>
++#include <mach/clock.h>
++
++#include <mach/display.h>
++
++#include "dss.h"
++
++/* DISPC */
++#define DISPC_BASE			0x48050400
++
++#define DISPC_SZ_REGS			SZ_1K
++
++struct dispc_reg { u16 idx; };
++
++#define DISPC_REG(idx)			((const struct dispc_reg) { idx })
++
++/* DISPC common */
++#define DISPC_REVISION			DISPC_REG(0x0000)
++#define DISPC_SYSCONFIG			DISPC_REG(0x0010)
++#define DISPC_SYSSTATUS			DISPC_REG(0x0014)
++#define DISPC_IRQSTATUS			DISPC_REG(0x0018)
++#define DISPC_IRQENABLE			DISPC_REG(0x001C)
++#define DISPC_CONTROL			DISPC_REG(0x0040)
++#define DISPC_CONFIG			DISPC_REG(0x0044)
++#define DISPC_CAPABLE			DISPC_REG(0x0048)
++#define DISPC_DEFAULT_COLOR0		DISPC_REG(0x004C)
++#define DISPC_DEFAULT_COLOR1		DISPC_REG(0x0050)
++#define DISPC_TRANS_COLOR0		DISPC_REG(0x0054)
++#define DISPC_TRANS_COLOR1		DISPC_REG(0x0058)
++#define DISPC_LINE_STATUS		DISPC_REG(0x005C)
++#define DISPC_LINE_NUMBER		DISPC_REG(0x0060)
++#define DISPC_TIMING_H			DISPC_REG(0x0064)
++#define DISPC_TIMING_V			DISPC_REG(0x0068)
++#define DISPC_POL_FREQ			DISPC_REG(0x006C)
++#define DISPC_DIVISOR			DISPC_REG(0x0070)
++#define DISPC_GLOBAL_ALPHA		DISPC_REG(0x0074)
++#define DISPC_SIZE_DIG			DISPC_REG(0x0078)
++#define DISPC_SIZE_LCD			DISPC_REG(0x007C)
++
++/* DISPC GFX plane */
++#define DISPC_GFX_BA0			DISPC_REG(0x0080)
++#define DISPC_GFX_BA1			DISPC_REG(0x0084)
++#define DISPC_GFX_POSITION		DISPC_REG(0x0088)
++#define DISPC_GFX_SIZE			DISPC_REG(0x008C)
++#define DISPC_GFX_ATTRIBUTES		DISPC_REG(0x00A0)
++#define DISPC_GFX_FIFO_THRESHOLD	DISPC_REG(0x00A4)
++#define DISPC_GFX_FIFO_SIZE_STATUS	DISPC_REG(0x00A8)
++#define DISPC_GFX_ROW_INC		DISPC_REG(0x00AC)
++#define DISPC_GFX_PIXEL_INC		DISPC_REG(0x00B0)
++#define DISPC_GFX_WINDOW_SKIP		DISPC_REG(0x00B4)
++#define DISPC_GFX_TABLE_BA		DISPC_REG(0x00B8)
++
++#define DISPC_DATA_CYCLE1		DISPC_REG(0x01D4)
++#define DISPC_DATA_CYCLE2		DISPC_REG(0x01D8)
++#define DISPC_DATA_CYCLE3		DISPC_REG(0x01DC)
++
++#define DISPC_CPR_COEF_R		DISPC_REG(0x0220)
++#define DISPC_CPR_COEF_G		DISPC_REG(0x0224)
++#define DISPC_CPR_COEF_B		DISPC_REG(0x0228)
++
++#define DISPC_GFX_PRELOAD		DISPC_REG(0x022C)
++
++/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
++#define DISPC_VID_REG(n, idx)		DISPC_REG(0x00BC + (n)*0x90 + idx)
++
++#define DISPC_VID_BA0(n)		DISPC_VID_REG(n, 0x0000)
++#define DISPC_VID_BA1(n)		DISPC_VID_REG(n, 0x0004)
++#define DISPC_VID_POSITION(n)		DISPC_VID_REG(n, 0x0008)
++#define DISPC_VID_SIZE(n)		DISPC_VID_REG(n, 0x000C)
++#define DISPC_VID_ATTRIBUTES(n)		DISPC_VID_REG(n, 0x0010)
++#define DISPC_VID_FIFO_THRESHOLD(n)	DISPC_VID_REG(n, 0x0014)
++#define DISPC_VID_FIFO_SIZE_STATUS(n)	DISPC_VID_REG(n, 0x0018)
++#define DISPC_VID_ROW_INC(n)		DISPC_VID_REG(n, 0x001C)
++#define DISPC_VID_PIXEL_INC(n)		DISPC_VID_REG(n, 0x0020)
++#define DISPC_VID_FIR(n)		DISPC_VID_REG(n, 0x0024)
++#define DISPC_VID_PICTURE_SIZE(n)	DISPC_VID_REG(n, 0x0028)
++#define DISPC_VID_ACCU0(n)		DISPC_VID_REG(n, 0x002C)
++#define DISPC_VID_ACCU1(n)		DISPC_VID_REG(n, 0x0030)
++
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_H(n, i)	DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_HV(n, i)	DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
++/* coef index i = {0, 1, 2, 3, 4} */
++#define DISPC_VID_CONV_COEF(n, i)	DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_V(n, i)	DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
++
++#define DISPC_VID_PRELOAD(n)		DISPC_REG(0x230 + (n)*0x04)
++
++
++#define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
++					 DISPC_IRQ_OCP_ERR | \
++					 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
++					 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
++					 DISPC_IRQ_SYNC_LOST | \
++					 DISPC_IRQ_SYNC_LOST_DIGIT)
++
++#define DISPC_MAX_NR_ISRS		8
++
++struct omap_dispc_isr_data {
++	omap_dispc_isr_t	isr;
++	void			*arg;
++	u32			mask;
++};
++
++#define REG_GET(idx, start, end) \
++	FLD_GET(dispc_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end)				\
++	dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
++
++static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
++	DISPC_VID_ATTRIBUTES(0),
++	DISPC_VID_ATTRIBUTES(1) };
++
++static struct {
++	void __iomem    *base;
++
++	struct clk	*dpll4_m4_ck;
++
++	spinlock_t	irq_lock;
++
++	unsigned long	cache_req_pck;
++	unsigned long	cache_prate;
++	struct dispc_clock_info cache_cinfo;
++
++	u32		irq_error_mask;
++	struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
++
++	spinlock_t error_lock;
++	u32 error_irqs;
++	struct work_struct error_work;
++
++	u32		ctx[DISPC_SZ_REGS / sizeof(u32)];
++} dispc;
++
++static void omap_dispc_set_irqs(void);
++
++static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
++{
++	__raw_writel(val, dispc.base + idx.idx);
++}
++
++static inline u32 dispc_read_reg(const struct dispc_reg idx)
++{
++	return __raw_readl(dispc.base + idx.idx);
++}
++
++#define SR(reg) \
++	dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
++#define RR(reg) \
++	dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
++
++void dispc_save_context(void)
++{
++	if (cpu_is_omap24xx())
++		return;
++
++	SR(SYSCONFIG);
++	SR(IRQENABLE);
++	SR(CONTROL);
++	SR(CONFIG);
++	SR(DEFAULT_COLOR0);
++	SR(DEFAULT_COLOR1);
++	SR(TRANS_COLOR0);
++	SR(TRANS_COLOR1);
++	SR(LINE_NUMBER);
++	SR(TIMING_H);
++	SR(TIMING_V);
++	SR(POL_FREQ);
++	SR(DIVISOR);
++	SR(GLOBAL_ALPHA);
++	SR(SIZE_DIG);
++	SR(SIZE_LCD);
++
++	SR(GFX_BA0);
++	SR(GFX_BA1);
++	SR(GFX_POSITION);
++	SR(GFX_SIZE);
++	SR(GFX_ATTRIBUTES);
++	SR(GFX_FIFO_THRESHOLD);
++	SR(GFX_ROW_INC);
++	SR(GFX_PIXEL_INC);
++	SR(GFX_WINDOW_SKIP);
++	SR(GFX_TABLE_BA);
++
++	SR(DATA_CYCLE1);
++	SR(DATA_CYCLE2);
++	SR(DATA_CYCLE3);
++
++	SR(CPR_COEF_R);
++	SR(CPR_COEF_G);
++	SR(CPR_COEF_B);
++
++	SR(GFX_PRELOAD);
++
++	/* VID1 */
++	SR(VID_BA0(0));
++	SR(VID_BA1(0));
++	SR(VID_POSITION(0));
++	SR(VID_SIZE(0));
++	SR(VID_ATTRIBUTES(0));
++	SR(VID_FIFO_THRESHOLD(0));
++	SR(VID_ROW_INC(0));
++	SR(VID_PIXEL_INC(0));
++	SR(VID_FIR(0));
++	SR(VID_PICTURE_SIZE(0));
++	SR(VID_ACCU0(0));
++	SR(VID_ACCU1(0));
++
++	SR(VID_FIR_COEF_H(0, 0));
++	SR(VID_FIR_COEF_H(0, 1));
++	SR(VID_FIR_COEF_H(0, 2));
++	SR(VID_FIR_COEF_H(0, 3));
++	SR(VID_FIR_COEF_H(0, 4));
++	SR(VID_FIR_COEF_H(0, 5));
++	SR(VID_FIR_COEF_H(0, 6));
++	SR(VID_FIR_COEF_H(0, 7));
++
++	SR(VID_FIR_COEF_HV(0, 0));
++	SR(VID_FIR_COEF_HV(0, 1));
++	SR(VID_FIR_COEF_HV(0, 2));
++	SR(VID_FIR_COEF_HV(0, 3));
++	SR(VID_FIR_COEF_HV(0, 4));
++	SR(VID_FIR_COEF_HV(0, 5));
++	SR(VID_FIR_COEF_HV(0, 6));
++	SR(VID_FIR_COEF_HV(0, 7));
++
++	SR(VID_CONV_COEF(0, 0));
++	SR(VID_CONV_COEF(0, 1));
++	SR(VID_CONV_COEF(0, 2));
++	SR(VID_CONV_COEF(0, 3));
++	SR(VID_CONV_COEF(0, 4));
++
++	SR(VID_FIR_COEF_V(0, 0));
++	SR(VID_FIR_COEF_V(0, 1));
++	SR(VID_FIR_COEF_V(0, 2));
++	SR(VID_FIR_COEF_V(0, 3));
++	SR(VID_FIR_COEF_V(0, 4));
++	SR(VID_FIR_COEF_V(0, 5));
++	SR(VID_FIR_COEF_V(0, 6));
++	SR(VID_FIR_COEF_V(0, 7));
++
++	SR(VID_PRELOAD(0));
++
++	/* VID2 */
++	SR(VID_BA0(1));
++	SR(VID_BA1(1));
++	SR(VID_POSITION(1));
++	SR(VID_SIZE(1));
++	SR(VID_ATTRIBUTES(1));
++	SR(VID_FIFO_THRESHOLD(1));
++	SR(VID_ROW_INC(1));
++	SR(VID_PIXEL_INC(1));
++	SR(VID_FIR(1));
++	SR(VID_PICTURE_SIZE(1));
++	SR(VID_ACCU0(1));
++	SR(VID_ACCU1(1));
++
++	SR(VID_FIR_COEF_H(1, 0));
++	SR(VID_FIR_COEF_H(1, 1));
++	SR(VID_FIR_COEF_H(1, 2));
++	SR(VID_FIR_COEF_H(1, 3));
++	SR(VID_FIR_COEF_H(1, 4));
++	SR(VID_FIR_COEF_H(1, 5));
++	SR(VID_FIR_COEF_H(1, 6));
++	SR(VID_FIR_COEF_H(1, 7));
++
++	SR(VID_FIR_COEF_HV(1, 0));
++	SR(VID_FIR_COEF_HV(1, 1));
++	SR(VID_FIR_COEF_HV(1, 2));
++	SR(VID_FIR_COEF_HV(1, 3));
++	SR(VID_FIR_COEF_HV(1, 4));
++	SR(VID_FIR_COEF_HV(1, 5));
++	SR(VID_FIR_COEF_HV(1, 6));
++	SR(VID_FIR_COEF_HV(1, 7));
++
++	SR(VID_CONV_COEF(1, 0));
++	SR(VID_CONV_COEF(1, 1));
++	SR(VID_CONV_COEF(1, 2));
++	SR(VID_CONV_COEF(1, 3));
++	SR(VID_CONV_COEF(1, 4));
++
++	SR(VID_FIR_COEF_V(1, 0));
++	SR(VID_FIR_COEF_V(1, 1));
++	SR(VID_FIR_COEF_V(1, 2));
++	SR(VID_FIR_COEF_V(1, 3));
++	SR(VID_FIR_COEF_V(1, 4));
++	SR(VID_FIR_COEF_V(1, 5));
++	SR(VID_FIR_COEF_V(1, 6));
++	SR(VID_FIR_COEF_V(1, 7));
++
++	SR(VID_PRELOAD(1));
++}
++
++void dispc_restore_context(void)
++{
++	RR(SYSCONFIG);
++	RR(IRQENABLE);
++	/*RR(CONTROL);*/
++	RR(CONFIG);
++	RR(DEFAULT_COLOR0);
++	RR(DEFAULT_COLOR1);
++	RR(TRANS_COLOR0);
++	RR(TRANS_COLOR1);
++	RR(LINE_NUMBER);
++	RR(TIMING_H);
++	RR(TIMING_V);
++	RR(POL_FREQ);
++	RR(DIVISOR);
++	RR(GLOBAL_ALPHA);
++	RR(SIZE_DIG);
++	RR(SIZE_LCD);
++
++	RR(GFX_BA0);
++	RR(GFX_BA1);
++	RR(GFX_POSITION);
++	RR(GFX_SIZE);
++	RR(GFX_ATTRIBUTES);
++	RR(GFX_FIFO_THRESHOLD);
++	RR(GFX_ROW_INC);
++	RR(GFX_PIXEL_INC);
++	RR(GFX_WINDOW_SKIP);
++	RR(GFX_TABLE_BA);
++
++	RR(DATA_CYCLE1);
++	RR(DATA_CYCLE2);
++	RR(DATA_CYCLE3);
++
++	RR(CPR_COEF_R);
++	RR(CPR_COEF_G);
++	RR(CPR_COEF_B);
++
++	RR(GFX_PRELOAD);
++
++	/* VID1 */
++	RR(VID_BA0(0));
++	RR(VID_BA1(0));
++	RR(VID_POSITION(0));
++	RR(VID_SIZE(0));
++	RR(VID_ATTRIBUTES(0));
++	RR(VID_FIFO_THRESHOLD(0));
++	RR(VID_ROW_INC(0));
++	RR(VID_PIXEL_INC(0));
++	RR(VID_FIR(0));
++	RR(VID_PICTURE_SIZE(0));
++	RR(VID_ACCU0(0));
++	RR(VID_ACCU1(0));
++
++	RR(VID_FIR_COEF_H(0, 0));
++	RR(VID_FIR_COEF_H(0, 1));
++	RR(VID_FIR_COEF_H(0, 2));
++	RR(VID_FIR_COEF_H(0, 3));
++	RR(VID_FIR_COEF_H(0, 4));
++	RR(VID_FIR_COEF_H(0, 5));
++	RR(VID_FIR_COEF_H(0, 6));
++	RR(VID_FIR_COEF_H(0, 7));
++
++	RR(VID_FIR_COEF_HV(0, 0));
++	RR(VID_FIR_COEF_HV(0, 1));
++	RR(VID_FIR_COEF_HV(0, 2));
++	RR(VID_FIR_COEF_HV(0, 3));
++	RR(VID_FIR_COEF_HV(0, 4));
++	RR(VID_FIR_COEF_HV(0, 5));
++	RR(VID_FIR_COEF_HV(0, 6));
++	RR(VID_FIR_COEF_HV(0, 7));
++
++	RR(VID_CONV_COEF(0, 0));
++	RR(VID_CONV_COEF(0, 1));
++	RR(VID_CONV_COEF(0, 2));
++	RR(VID_CONV_COEF(0, 3));
++	RR(VID_CONV_COEF(0, 4));
++
++	RR(VID_FIR_COEF_V(0, 0));
++	RR(VID_FIR_COEF_V(0, 1));
++	RR(VID_FIR_COEF_V(0, 2));
++	RR(VID_FIR_COEF_V(0, 3));
++	RR(VID_FIR_COEF_V(0, 4));
++	RR(VID_FIR_COEF_V(0, 5));
++	RR(VID_FIR_COEF_V(0, 6));
++	RR(VID_FIR_COEF_V(0, 7));
++
++	RR(VID_PRELOAD(0));
++
++	/* VID2 */
++	RR(VID_BA0(1));
++	RR(VID_BA1(1));
++	RR(VID_POSITION(1));
++	RR(VID_SIZE(1));
++	RR(VID_ATTRIBUTES(1));
++	RR(VID_FIFO_THRESHOLD(1));
++	RR(VID_ROW_INC(1));
++	RR(VID_PIXEL_INC(1));
++	RR(VID_FIR(1));
++	RR(VID_PICTURE_SIZE(1));
++	RR(VID_ACCU0(1));
++	RR(VID_ACCU1(1));
++
++	RR(VID_FIR_COEF_H(1, 0));
++	RR(VID_FIR_COEF_H(1, 1));
++	RR(VID_FIR_COEF_H(1, 2));
++	RR(VID_FIR_COEF_H(1, 3));
++	RR(VID_FIR_COEF_H(1, 4));
++	RR(VID_FIR_COEF_H(1, 5));
++	RR(VID_FIR_COEF_H(1, 6));
++	RR(VID_FIR_COEF_H(1, 7));
++
++	RR(VID_FIR_COEF_HV(1, 0));
++	RR(VID_FIR_COEF_HV(1, 1));
++	RR(VID_FIR_COEF_HV(1, 2));
++	RR(VID_FIR_COEF_HV(1, 3));
++	RR(VID_FIR_COEF_HV(1, 4));
++	RR(VID_FIR_COEF_HV(1, 5));
++	RR(VID_FIR_COEF_HV(1, 6));
++	RR(VID_FIR_COEF_HV(1, 7));
++
++	RR(VID_CONV_COEF(1, 0));
++	RR(VID_CONV_COEF(1, 1));
++	RR(VID_CONV_COEF(1, 2));
++	RR(VID_CONV_COEF(1, 3));
++	RR(VID_CONV_COEF(1, 4));
++
++	RR(VID_FIR_COEF_V(1, 0));
++	RR(VID_FIR_COEF_V(1, 1));
++	RR(VID_FIR_COEF_V(1, 2));
++	RR(VID_FIR_COEF_V(1, 3));
++	RR(VID_FIR_COEF_V(1, 4));
++	RR(VID_FIR_COEF_V(1, 5));
++	RR(VID_FIR_COEF_V(1, 6));
++	RR(VID_FIR_COEF_V(1, 7));
++
++	RR(VID_PRELOAD(1));
++
++	/* enable last, because LCD & DIGIT enable are here */
++	RR(CONTROL);
++}
++
++#undef SR
++#undef RR
++
++static inline void enable_clocks(bool enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	else
++		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++void dispc_go(enum omap_channel channel)
++{
++	int bit;
++	unsigned long tmo;
++
++	enable_clocks(1);
++
++	if (channel == OMAP_DSS_CHANNEL_LCD)
++		bit = 0; /* LCDENABLE */
++	else
++		bit = 1; /* DIGITALENABLE */
++
++	/* if the channel is not enabled, we don't need GO */
++	if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
++		goto end;
++
++	if (channel == OMAP_DSS_CHANNEL_LCD)
++		bit = 5; /* GOLCD */
++	else
++		bit = 6; /* GODIGIT */
++
++	tmo = jiffies + msecs_to_jiffies(200);
++	while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
++		if (time_after(jiffies, tmo)) {
++			DSSERR("timeout waiting GO flag\n");
++			goto end;
++		}
++		cpu_relax();
++	}
++
++	DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
++
++	REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
++end:
++	enable_clocks(0);
++}
++
++static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
++{
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
++}
++
++static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
++{
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
++}
++
++static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
++{
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
++}
++
++static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
++		int vscaleup, int five_taps)
++{
++	/* Coefficients for horizontal up-sampling */
++	static const u32 coef_hup[8] = {
++		0x00800000,
++		0x0D7CF800,
++		0x1E70F5FF,
++		0x335FF5FE,
++		0xF74949F7,
++		0xF55F33FB,
++		0xF5701EFE,
++		0xF87C0DFF,
++	};
++
++	/* Coefficients for horizontal down-sampling */
++	static const u32 coef_hdown[8] = {
++		0x24382400,
++		0x28371FFE,
++		0x2C361BFB,
++		0x303516F9,
++		0x11343311,
++		0x1635300C,
++		0x1B362C08,
++		0x1F372804,
++	};
++
++	/* Coefficients for horizontal and vertical up-sampling */
++	static const u32 coef_hvup[2][8] = {
++		{
++		0x00800000,
++		0x037B02FF,
++		0x0C6F05FE,
++		0x205907FB,
++		0x00404000,
++		0x075920FE,
++		0x056F0CFF,
++		0x027B0300,
++		},
++		{
++		0x00800000,
++		0x0D7CF8FF,
++		0x1E70F5FE,
++		0x335FF5FB,
++		0xF7404000,
++		0xF55F33FE,
++		0xF5701EFF,
++		0xF87C0D00,
++		},
++	};
++
++	/* Coefficients for horizontal and vertical down-sampling */
++	static const u32 coef_hvdown[2][8] = {
++		{
++		0x24382400,
++		0x28391F04,
++		0x2D381B08,
++		0x3237170C,
++		0x123737F7,
++		0x173732F9,
++		0x1B382DFB,
++		0x1F3928FE,
++		},
++		{
++		0x24382400,
++		0x28371F04,
++		0x2C361B08,
++		0x3035160C,
++		0x113433F7,
++		0x163530F9,
++		0x1B362CFB,
++		0x1F3728FE,
++		},
++	};
++
++	/* Coefficients for vertical up-sampling */
++	static const u32 coef_vup[8] = {
++		0x00000000,
++		0x0000FF00,
++		0x0000FEFF,
++		0x0000FBFE,
++		0x000000F7,
++		0x0000FEFB,
++		0x0000FFFE,
++		0x000000FF,
++	};
++
++
++	/* Coefficients for vertical down-sampling */
++	static const u32 coef_vdown[8] = {
++		0x00000000,
++		0x000004FE,
++		0x000008FB,
++		0x00000CF9,
++		0x0000F711,
++		0x0000F90C,
++		0x0000FB08,
++		0x0000FE04,
++	};
++
++	const u32 *h_coef;
++	const u32 *hv_coef;
++	const u32 *hv_coef_mod;
++	const u32 *v_coef;
++	int i;
++
++	if (hscaleup)
++		h_coef = coef_hup;
++	else
++		h_coef = coef_hdown;
++
++	if (vscaleup) {
++		hv_coef = coef_hvup[five_taps];
++		v_coef = coef_vup;
++
++		if (hscaleup)
++			hv_coef_mod = NULL;
++		else
++			hv_coef_mod = coef_hvdown[five_taps];
++	} else {
++		hv_coef = coef_hvdown[five_taps];
++		v_coef = coef_vdown;
++
++		if (hscaleup)
++			hv_coef_mod = coef_hvup[five_taps];
++		else
++			hv_coef_mod = NULL;
++	}
++
++	for (i = 0; i < 8; i++) {
++		u32 h, hv;
++
++		h = h_coef[i];
++
++		hv = hv_coef[i];
++
++		if (hv_coef_mod) {
++			hv &= 0xffffff00;
++			hv |= (hv_coef_mod[i] & 0xff);
++		}
++
++		_dispc_write_firh_reg(plane, i, h);
++		_dispc_write_firhv_reg(plane, i, hv);
++	}
++
++	if (!five_taps)
++		return;
++
++	for (i = 0; i < 8; i++) {
++		u32 v;
++		v = v_coef[i];
++		_dispc_write_firv_reg(plane, i, v);
++	}
++}
++
++static void _dispc_setup_color_conv_coef(void)
++{
++	const struct color_conv_coef {
++		int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
++		int  full_range;
++	}  ctbl_bt601_5 = {
++		298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
++	};
++
++	const struct color_conv_coef *ct;
++
++#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
++
++	ct = &ctbl_bt601_5;
++
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,	 ct->rcb));
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
++
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,	 ct->rcb));
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
++
++#undef CVAL
++
++	REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
++	REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
++}
++
++
++static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
++{
++	const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
++		DISPC_VID_BA0(0),
++		DISPC_VID_BA0(1) };
++
++	dispc_write_reg(ba0_reg[plane], paddr);
++}
++
++static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
++{
++	const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
++				      DISPC_VID_BA1(0),
++				      DISPC_VID_BA1(1) };
++
++	dispc_write_reg(ba1_reg[plane], paddr);
++}
++
++static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
++{
++	const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
++				      DISPC_VID_POSITION(0),
++				      DISPC_VID_POSITION(1) };
++
++	u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
++	dispc_write_reg(pos_reg[plane], val);
++}
++
++static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
++{
++	const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
++				      DISPC_VID_PICTURE_SIZE(0),
++				      DISPC_VID_PICTURE_SIZE(1) };
++	u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++	dispc_write_reg(siz_reg[plane], val);
++}
++
++static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
++{
++	u32 val;
++	const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
++				      DISPC_VID_SIZE(1) };
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++	dispc_write_reg(vsi_reg[plane-1], val);
++}
++
++static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
++{
++	const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
++				     DISPC_VID_PIXEL_INC(0),
++				     DISPC_VID_PIXEL_INC(1) };
++
++	dispc_write_reg(ri_reg[plane], inc);
++}
++
++static void _dispc_set_row_inc(enum omap_plane plane, u16 inc)
++{
++	const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
++				     DISPC_VID_ROW_INC(0),
++				     DISPC_VID_ROW_INC(1) };
++
++	dispc_write_reg(ri_reg[plane], inc);
++}
++
++static void _dispc_set_color_mode(enum omap_plane plane,
++		enum omap_color_mode color_mode)
++{
++	u32 m = 0;
++
++	switch (color_mode) {
++	case OMAP_DSS_COLOR_CLUT1:
++		m = 0x0; break;
++	case OMAP_DSS_COLOR_CLUT2:
++		m = 0x1; break;
++	case OMAP_DSS_COLOR_CLUT4:
++		m = 0x2; break;
++	case OMAP_DSS_COLOR_CLUT8:
++		m = 0x3; break;
++	case OMAP_DSS_COLOR_RGB12U:
++		m = 0x4; break;
++	case OMAP_DSS_COLOR_ARGB16:
++		m = 0x5; break;
++	case OMAP_DSS_COLOR_RGB16:
++		m = 0x6; break;
++	case OMAP_DSS_COLOR_RGB24U:
++		m = 0x8; break;
++	case OMAP_DSS_COLOR_RGB24P:
++		m = 0x9; break;
++	case OMAP_DSS_COLOR_YUV2:
++		m = 0xa; break;
++	case OMAP_DSS_COLOR_UYVY:
++		m = 0xb; break;
++	case OMAP_DSS_COLOR_ARGB32:
++		m = 0xc; break;
++	case OMAP_DSS_COLOR_RGBA32:
++		m = 0xd; break;
++	case OMAP_DSS_COLOR_RGBX32:
++		m = 0xe; break;
++	default:
++		BUG(); break;
++	}
++
++	REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
++}
++
++static void _dispc_set_channel_out(enum omap_plane plane,
++		enum omap_channel channel)
++{
++	int shift;
++	u32 val;
++
++	switch (plane) {
++	case OMAP_DSS_GFX:
++		shift = 8;
++		break;
++	case OMAP_DSS_VIDEO1:
++	case OMAP_DSS_VIDEO2:
++		shift = 16;
++		break;
++	default:
++		BUG();
++		return;
++	}
++
++	val = dispc_read_reg(dispc_reg_att[plane]);
++	val = FLD_MOD(val, channel, shift, shift);
++	dispc_write_reg(dispc_reg_att[plane], val);
++}
++
++void dispc_set_burst_size(enum omap_plane plane,
++		enum omap_burst_size burst_size)
++{
++	int shift;
++	u32 val;
++
++	enable_clocks(1);
++
++	switch (plane) {
++	case OMAP_DSS_GFX:
++		shift = 6;
++		break;
++	case OMAP_DSS_VIDEO1:
++	case OMAP_DSS_VIDEO2:
++		shift = 14;
++		break;
++	default:
++		BUG();
++		return;
++	}
++
++	val = dispc_read_reg(dispc_reg_att[plane]);
++	val = FLD_MOD(val, burst_size, shift+1, shift);
++	dispc_write_reg(dispc_reg_att[plane], val);
++
++	enable_clocks(0);
++}
++
++static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
++{
++	u32 val;
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = dispc_read_reg(dispc_reg_att[plane]);
++	val = FLD_MOD(val, enable, 9, 9);
++	dispc_write_reg(dispc_reg_att[plane], val);
++}
++
++void dispc_set_lcd_size(u16 width, u16 height)
++{
++	u32 val;
++	BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
++	val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++	enable_clocks(1);
++	dispc_write_reg(DISPC_SIZE_LCD, val);
++	enable_clocks(0);
++}
++
++void dispc_set_digit_size(u16 width, u16 height)
++{
++	u32 val;
++	BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
++	val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++	enable_clocks(1);
++	dispc_write_reg(DISPC_SIZE_DIG, val);
++	enable_clocks(0);
++}
++
++u32 dispc_get_plane_fifo_size(enum omap_plane plane)
++{
++	const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
++				      DISPC_VID_FIFO_SIZE_STATUS(0),
++				      DISPC_VID_FIFO_SIZE_STATUS(1) };
++	u32 size;
++
++	enable_clocks(1);
++
++	if (cpu_is_omap24xx())
++		size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
++	else if (cpu_is_omap34xx())
++		size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
++	else
++		BUG();
++
++	if (cpu_is_omap34xx()) {
++		/* FIFOMERGE */
++		if (REG_GET(DISPC_CONFIG, 14, 14))
++			size *= 3;
++	}
++
++	enable_clocks(0);
++
++	return size;
++}
++
++void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
++{
++	const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
++				       DISPC_VID_FIFO_THRESHOLD(0),
++				       DISPC_VID_FIFO_THRESHOLD(1) };
++	u32 size;
++
++	enable_clocks(1);
++
++	size = dispc_get_plane_fifo_size(plane);
++
++	BUG_ON(low > size || high > size);
++
++	DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
++			plane, size,
++			REG_GET(ftrs_reg[plane], 11, 0),
++			REG_GET(ftrs_reg[plane], 27, 16),
++			low, high);
++
++	if (cpu_is_omap24xx())
++		dispc_write_reg(ftrs_reg[plane],
++				FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
++	else
++		dispc_write_reg(ftrs_reg[plane],
++				FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
++
++	enable_clocks(0);
++}
++
++void dispc_enable_fifomerge(bool enable)
++{
++	enable_clocks(1);
++
++	DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
++	REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
++
++	enable_clocks(0);
++}
++
++static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
++{
++	u32 val;
++	const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
++				      DISPC_VID_FIR(1) };
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
++	dispc_write_reg(fir_reg[plane-1], val);
++}
++
++static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
++{
++	u32 val;
++	const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
++				      DISPC_VID_ACCU0(1) };
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
++	dispc_write_reg(ac0_reg[plane-1], val);
++}
++
++static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
++{
++	u32 val;
++	const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
++				      DISPC_VID_ACCU1(1) };
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
++	dispc_write_reg(ac1_reg[plane-1], val);
++}
++
++
++static void _dispc_set_scaling(enum omap_plane plane,
++		u16 orig_width, u16 orig_height,
++		u16 out_width, u16 out_height,
++		bool ilace)
++{
++	int fir_hinc;
++	int fir_vinc;
++	int hscaleup, vscaleup, five_taps;
++	int fieldmode = 0;
++	int accu0 = 0;
++	int accu1 = 0;
++	u32 l;
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	hscaleup = orig_width <= out_width;
++	vscaleup = orig_height <= out_height;
++	five_taps = orig_height > out_height * 2;
++
++	_dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
++
++	if (!orig_width || orig_width == out_width)
++		fir_hinc = 0;
++	else
++		fir_hinc = 1024 * orig_width / out_width;
++
++	if (!orig_height || orig_height == out_height)
++		fir_vinc = 0;
++	else
++		fir_vinc = 1024 * orig_height / out_height;
++
++	_dispc_set_fir(plane, fir_hinc, fir_vinc);
++
++	l = dispc_read_reg(dispc_reg_att[plane]);
++	l &= ~((0x0f << 5) | (0x3 << 21));
++
++	l |= fir_hinc ? (1 << 5) : 0;
++	l |= fir_vinc ? (1 << 6) : 0;
++
++	l |= hscaleup ? 0 : (1 << 7);
++	l |= vscaleup ? 0 : (1 << 8);
++
++	l |= five_taps ? (1 << 21) : 0;
++	l |= five_taps ? (1 << 22) : 0;
++
++	dispc_write_reg(dispc_reg_att[plane], l);
++
++	if (ilace) {
++		if (fieldmode) {
++			accu0 = fir_vinc / 2;
++			accu1 = 0;
++		} else {
++			accu0 = 0;
++			accu1 = fir_vinc / 2;
++			if (accu1 >= 1024/2) {
++				accu0 = 1024/2;
++				accu1 -= accu0;
++			}
++		}
++	}
++
++	_dispc_set_vid_accu0(plane, 0, accu0);
++	_dispc_set_vid_accu1(plane, 0, accu1);
++}
++
++static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
++		bool mirroring, enum omap_color_mode color_mode)
++{
++	if (color_mode == OMAP_DSS_COLOR_YUV2 ||
++			color_mode == OMAP_DSS_COLOR_UYVY) {
++		int vidrot = 0;
++
++		if (mirroring) {
++			switch (rotation) {
++			case 0: vidrot = 2; break;
++			case 1: vidrot = 3; break;
++			case 2: vidrot = 0; break;
++			case 3: vidrot = 1; break;
++			}
++		} else {
++			switch (rotation) {
++			case 0: vidrot = 0; break;
++			case 1: vidrot = 1; break;
++			case 2: vidrot = 2; break;
++			case 3: vidrot = 1; break;
++			}
++		}
++
++		REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
++
++		if (rotation == 1 || rotation == 3)
++			REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
++		else
++			REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
++	} else {
++		REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
++		REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
++	}
++}
++
++static int pixinc(int pixels, u8 ps)
++{
++	if (pixels == 1)
++		return 1;
++	else if (pixels > 1)
++		return 1 + (pixels - 1) * ps;
++	else if (pixels < 0)
++		return 1 - (-pixels + 1) * ps;
++	else
++		BUG();
++}
++
++static void calc_rotation_offset(u8 rotation, bool mirror,
++		u16 screen_width,
++		u16 width, u16 height,
++		enum omap_color_mode color_mode, bool fieldmode,
++		unsigned *offset0, unsigned *offset1,
++		u16 *row_inc, u16 *pix_inc)
++{
++	u8 ps;
++	u16 fbw, fbh;
++
++	switch (color_mode) {
++	case OMAP_DSS_COLOR_RGB16:
++	case OMAP_DSS_COLOR_ARGB16:
++		ps = 2;
++		break;
++
++	case OMAP_DSS_COLOR_RGB24P:
++		ps = 3;
++		break;
++
++	case OMAP_DSS_COLOR_RGB24U:
++	case OMAP_DSS_COLOR_ARGB32:
++	case OMAP_DSS_COLOR_RGBA32:
++	case OMAP_DSS_COLOR_RGBX32:
++		ps = 4;
++		break;
++
++	case OMAP_DSS_COLOR_YUV2:
++	case OMAP_DSS_COLOR_UYVY:
++		ps = 2;
++		break;
++	default:
++		BUG();
++		return;
++	}
++
++	DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
++			width, height);
++
++	/* width & height are overlay sizes, convert to fb sizes */
++
++	if (rotation == 0 || rotation == 2) {
++		fbw = width;
++		fbh = height;
++	} else {
++		fbw = height;
++		fbh = width;
++	}
++
++	switch (rotation + mirror * 4) {
++	case 0:
++		*offset0 = 0;
++		if (fieldmode)
++			*offset1 = screen_width * ps;
++		else
++			*offset1 = 0;
++		*row_inc = pixinc(1 + (screen_width - fbw) +
++				(fieldmode ? screen_width : 0),
++				ps);
++		*pix_inc = pixinc(1, ps);
++		break;
++	case 1:
++		*offset0 = screen_width * (fbh - 1) * ps;
++		if (fieldmode)
++			*offset1 = *offset0 + ps;
++		else
++			*offset1 = *offset0;
++		*row_inc = pixinc(screen_width * (fbh - 1) + 1 +
++				(fieldmode ? 1 : 0), ps);
++		*pix_inc = pixinc(-screen_width, ps);
++		break;
++	case 2:
++		*offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
++		if (fieldmode)
++			*offset1 = *offset0 - screen_width * ps;
++		else
++			*offset1 = *offset0;
++		*row_inc = pixinc(-1 -
++				(screen_width - fbw) -
++				(fieldmode ? screen_width : 0),
++				ps);
++		*pix_inc = pixinc(-1, ps);
++		break;
++	case 3:
++		*offset0 = (fbw - 1) * ps;
++		if (fieldmode)
++			*offset1 = *offset0 - ps;
++		else
++			*offset1 = *offset0;
++		*row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
++				(fieldmode ? 1 : 0), ps);
++		*pix_inc = pixinc(screen_width, ps);
++		break;
++
++	/* mirroring */
++	case 0 + 4:
++		*offset0 = (fbw - 1) * ps;
++		if (fieldmode)
++			*offset1 = *offset0 + screen_width * ps;
++		else
++			*offset1 = *offset0;
++		*row_inc = pixinc(screen_width * 2 - 1 +
++				(fieldmode ? screen_width : 0),
++				ps);
++		*pix_inc = pixinc(-1, ps);
++		break;
++
++	case 1 + 4:
++		*offset0 = 0;
++		if (fieldmode)
++			*offset1 = *offset0 + screen_width * ps;
++		else
++			*offset1 = *offset0;
++		*row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
++				(fieldmode ? 1 : 0),
++				ps);
++		*pix_inc = pixinc(screen_width, ps);
++		break;
++
++	case 2 + 4:
++		*offset0 = screen_width * (fbh - 1) * ps;
++		if (fieldmode)
++			*offset1 = *offset0 + screen_width * ps;
++		else
++			*offset1 = *offset0;
++		*row_inc = pixinc(1 - screen_width * 2 -
++				(fieldmode ? screen_width : 0),
++				ps);
++		*pix_inc = pixinc(1, ps);
++		break;
++
++	case 3 + 4:
++		*offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
++		if (fieldmode)
++			*offset1 = *offset0 + screen_width * ps;
++		else
++			*offset1 = *offset0;
++		*row_inc = pixinc(screen_width * (fbh - 1) - 1 -
++				(fieldmode ? 1 : 0),
++				ps);
++		*pix_inc = pixinc(-screen_width, ps);
++		break;
++
++	default:
++		BUG();
++	}
++}
++
++static int _dispc_setup_plane(enum omap_plane plane,
++		enum omap_channel channel_out,
++		u32 paddr, u16 screen_width,
++		u16 pos_x, u16 pos_y,
++		u16 width, u16 height,
++		u16 out_width, u16 out_height,
++		enum omap_color_mode color_mode,
++		bool ilace,
++		u8 rotation, int mirror)
++{
++	const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
++	bool five_taps = height > out_height * 2;
++	bool fieldmode = 0;
++	int cconv = 0;
++	unsigned offset0, offset1;
++	u16 row_inc;
++	u16 pix_inc;
++
++	if (plane == OMAP_DSS_GFX) {
++		if (width != out_width || height != out_height)
++			return -EINVAL;
++
++		switch (color_mode) {
++		case OMAP_DSS_COLOR_ARGB16:
++		case OMAP_DSS_COLOR_RGB16:
++		case OMAP_DSS_COLOR_RGB24P:
++		case OMAP_DSS_COLOR_RGB24U:
++		case OMAP_DSS_COLOR_ARGB32:
++		case OMAP_DSS_COLOR_RGBA32:
++		case OMAP_DSS_COLOR_RGBX32:
++			break;
++
++		default:
++			return -EINVAL;
++		}
++	} else {
++		/* video plane */
++		if (width > (2048 >> five_taps))
++			return -EINVAL;
++
++		if (out_width < width / maxdownscale ||
++		   out_width > width * 8)
++			return -EINVAL;
++
++		if (out_height < height / maxdownscale ||
++		   out_height > height * 8)
++			return -EINVAL;
++
++		switch (color_mode) {
++		case OMAP_DSS_COLOR_RGB16:
++		case OMAP_DSS_COLOR_RGB24P:
++		case OMAP_DSS_COLOR_RGB24U:
++		case OMAP_DSS_COLOR_RGBX32:
++			break;
++
++		case OMAP_DSS_COLOR_ARGB16:
++		case OMAP_DSS_COLOR_ARGB32:
++		case OMAP_DSS_COLOR_RGBA32:
++			if (plane == OMAP_DSS_VIDEO1)
++				return -EINVAL;
++			break;
++
++		case OMAP_DSS_COLOR_YUV2:
++		case OMAP_DSS_COLOR_UYVY:
++			cconv = 1;
++			break;
++
++		default:
++			return -EINVAL;
++		}
++	}
++
++	if (ilace && height >= out_height)
++		fieldmode = 1;
++
++	calc_rotation_offset(rotation, mirror,
++			screen_width, width, height, color_mode,
++			fieldmode,
++			&offset0, &offset1, &row_inc, &pix_inc);
++
++	DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
++			offset0, offset1, row_inc, pix_inc);
++
++	if (ilace) {
++		if (fieldmode)
++			height /= 2;
++		pos_y /= 2;
++		out_height /= 2;
++
++		DSSDBG("adjusting for ilace: height %d, pos_y %d, "
++				"out_height %d\n",
++				height, pos_y, out_height);
++	}
++
++	_dispc_set_channel_out(plane, channel_out);
++	_dispc_set_color_mode(plane, color_mode);
++
++	_dispc_set_plane_ba0(plane, paddr + offset0);
++	_dispc_set_plane_ba1(plane, paddr + offset1);
++
++	_dispc_set_row_inc(plane, row_inc);
++	_dispc_set_pix_inc(plane, pix_inc);
++
++	DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
++			out_width, out_height);
++
++	_dispc_set_plane_pos(plane, pos_x, pos_y);
++
++	_dispc_set_pic_size(plane, width, height);
++
++	if (plane != OMAP_DSS_GFX) {
++		_dispc_set_scaling(plane, width, height,
++				   out_width, out_height,
++				   ilace);
++		_dispc_set_vid_size(plane, out_width, out_height);
++		_dispc_set_vid_color_conv(plane, cconv);
++	}
++
++	_dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
++
++	return 0;
++}
++
++static void _dispc_enable_plane(enum omap_plane plane, bool enable)
++{
++	REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
++}
++
++static void dispc_disable_isr(void *data, u32 mask)
++{
++	struct completion *compl = data;
++	complete(compl);
++}
++
++static void _enable_lcd_out(bool enable)
++{
++	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
++}
++
++void dispc_enable_lcd_out(bool enable)
++{
++	struct completion frame_done_completion;
++	bool is_on;
++	int r;
++
++	enable_clocks(1);
++
++	/* When we disable LCD output, we need to wait until frame is done.
++	 * Otherwise the DSS is still working, and turning off the clocks
++	 * prevents DSS from going to OFF mode */
++	is_on = REG_GET(DISPC_CONTROL, 0, 0);
++
++	if (!enable && is_on) {
++		init_completion(&frame_done_completion);
++
++		r = omap_dispc_register_isr(dispc_disable_isr,
++				&frame_done_completion,
++				DISPC_IRQ_FRAMEDONE);
++
++		if (r)
++			DSSERR("failed to register FRAMEDONE isr\n");
++	}
++
++	_enable_lcd_out(enable);
++
++	if (!enable && is_on) {
++		if (!wait_for_completion_timeout(&frame_done_completion,
++					msecs_to_jiffies(100)))
++			DSSERR("timeout waiting for FRAME DONE\n");
++
++		r = omap_dispc_unregister_isr(dispc_disable_isr,
++				&frame_done_completion,
++				DISPC_IRQ_FRAMEDONE);
++
++		if (r)
++			DSSERR("failed to unregister FRAMEDONE isr\n");
++	}
++
++	enable_clocks(0);
++}
++
++static void _enable_digit_out(bool enable)
++{
++	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
++}
++
++void dispc_enable_digit_out(bool enable)
++{
++	struct completion frame_done_completion;
++	int r;
++
++	enable_clocks(1);
++
++	if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
++		enable_clocks(0);
++		return;
++	}
++
++	if (enable) {
++		/* When we enable digit output, we'll get an extra digit
++		 * sync lost interrupt, that we need to ignore */
++		dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
++		omap_dispc_set_irqs();
++	}
++
++	/* When we disable digit output, we need to wait until fields are done.
++	 * Otherwise the DSS is still working, and turning off the clocks
++	 * prevents DSS from going to OFF mode. And when enabling, we need to
++	 * wait for the extra sync losts */
++	init_completion(&frame_done_completion);
++
++	r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
++			DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
++	if (r)
++		DSSERR("failed to register EVSYNC isr\n");
++
++	_enable_digit_out(enable);
++
++	/* XXX I understand from TRM that we should only wait for the
++	 * current field to complete. But it seems we have to wait
++	 * for both fields */
++	if (!wait_for_completion_timeout(&frame_done_completion,
++				msecs_to_jiffies(100)))
++		DSSERR("timeout waiting for EVSYNC\n");
++
++	if (!wait_for_completion_timeout(&frame_done_completion,
++				msecs_to_jiffies(100)))
++		DSSERR("timeout waiting for EVSYNC\n");
++
++	r = omap_dispc_unregister_isr(dispc_disable_isr,
++			&frame_done_completion,
++			DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
++	if (r)
++		DSSERR("failed to unregister EVSYNC isr\n");
++
++	if (enable) {
++		dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
++		dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
++		omap_dispc_set_irqs();
++	}
++
++	enable_clocks(0);
++}
++
++void dispc_lcd_enable_signal_polarity(bool act_high)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
++	enable_clocks(0);
++}
++
++void dispc_lcd_enable_signal(bool enable)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
++	enable_clocks(0);
++}
++
++void dispc_pck_free_enable(bool enable)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
++	enable_clocks(0);
++}
++
++void dispc_enable_fifohandcheck(bool enable)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
++	enable_clocks(0);
++}
++
++
++void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
++{
++	int mode;
++
++	switch (type) {
++	case OMAP_DSS_LCD_DISPLAY_STN:
++		mode = 0;
++		break;
++
++	case OMAP_DSS_LCD_DISPLAY_TFT:
++		mode = 1;
++		break;
++
++	default:
++		BUG();
++		return;
++	}
++
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
++	enable_clocks(0);
++}
++
++void dispc_set_loadmode(enum omap_dss_load_mode mode)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
++	enable_clocks(0);
++}
++
++
++void dispc_set_default_color(enum omap_channel channel, u32 color)
++{
++	const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
++				DISPC_DEFAULT_COLOR1 };
++
++	enable_clocks(1);
++	dispc_write_reg(def_reg[channel], color);
++	enable_clocks(0);
++}
++
++u32 dispc_get_default_color(enum omap_channel channel)
++{
++	const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
++				DISPC_DEFAULT_COLOR1 };
++	u32 l;
++
++	BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
++	       channel != OMAP_DSS_CHANNEL_LCD);
++
++	enable_clocks(1);
++	l = dispc_read_reg(def_reg[channel]);
++	enable_clocks(0);
++
++	return l;
++}
++
++void dispc_set_trans_key(enum omap_channel ch,
++		enum omap_dss_color_key_type type,
++		u32 trans_key)
++{
++	const struct dispc_reg tr_reg[] = {
++		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
++
++	enable_clocks(1);
++	if (ch == OMAP_DSS_CHANNEL_LCD)
++		REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
++	else /* OMAP_DSS_CHANNEL_DIGIT */
++		REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
++
++	dispc_write_reg(tr_reg[ch], trans_key);
++	enable_clocks(0);
++}
++
++void dispc_get_trans_key(enum omap_channel ch,
++		enum omap_dss_color_key_type *type,
++		u32 *trans_key)
++{
++	const struct dispc_reg tr_reg[] = {
++		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
++
++	enable_clocks(1);
++	if (type) {
++		if (ch == OMAP_DSS_CHANNEL_LCD)
++			*type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
++		else if (ch == OMAP_DSS_CHANNEL_DIGIT)
++			*type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
++		else
++			BUG();
++	}
++
++	if (trans_key)
++		*trans_key = dispc_read_reg(tr_reg[ch]);
++	enable_clocks(0);
++}
++
++void dispc_enable_trans_key(enum omap_channel ch, bool enable)
++{
++	enable_clocks(1);
++	if (ch == OMAP_DSS_CHANNEL_LCD)
++		REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
++	else /* OMAP_DSS_CHANNEL_DIGIT */
++		REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
++	enable_clocks(0);
++}
++
++bool dispc_trans_key_enabled(enum omap_channel ch)
++{
++	bool enabled;
++
++	enable_clocks(1);
++	if (ch == OMAP_DSS_CHANNEL_LCD)
++		enabled = REG_GET(DISPC_CONFIG, 10, 10);
++	else if (ch == OMAP_DSS_CHANNEL_DIGIT)
++		enabled = REG_GET(DISPC_CONFIG, 12, 12);
++	else BUG();
++	enable_clocks(0);
++
++	return enabled;
++}
++
++
++void dispc_set_tft_data_lines(u8 data_lines)
++{
++	int code;
++
++	switch (data_lines) {
++	case 12:
++		code = 0;
++		break;
++	case 16:
++		code = 1;
++		break;
++	case 18:
++		code = 2;
++		break;
++	case 24:
++		code = 3;
++		break;
++	default:
++		BUG();
++		return;
++	}
++
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
++	enable_clocks(0);
++}
++
++void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
++{
++	u32 l;
++	int stallmode;
++	int gpout0 = 1;
++	int gpout1;
++
++	switch (mode) {
++	case OMAP_DSS_PARALLELMODE_BYPASS:
++		stallmode = 0;
++		gpout1 = 1;
++		break;
++
++	case OMAP_DSS_PARALLELMODE_RFBI:
++		stallmode = 1;
++		gpout1 = 0;
++		break;
++
++	case OMAP_DSS_PARALLELMODE_DSI:
++		stallmode = 1;
++		gpout1 = 1;
++		break;
++
++	default:
++		BUG();
++		return;
++	}
++
++	enable_clocks(1);
++
++	l = dispc_read_reg(DISPC_CONTROL);
++
++	l = FLD_MOD(l, stallmode, 11, 11);
++	l = FLD_MOD(l, gpout0, 15, 15);
++	l = FLD_MOD(l, gpout1, 16, 16);
++
++	dispc_write_reg(DISPC_CONTROL, l);
++
++	enable_clocks(0);
++}
++
++static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
++				   int vsw, int vfp, int vbp)
++{
++	u32 timing_h, timing_v;
++
++	if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
++		BUG_ON(hsw < 1 || hsw > 64);
++		BUG_ON(hfp < 1 || hfp > 256);
++		BUG_ON(hbp < 1 || hbp > 256);
++
++		BUG_ON(vsw < 1 || vsw > 64);
++		BUG_ON(vfp < 0 || vfp > 255);
++		BUG_ON(vbp < 0 || vbp > 255);
++
++		timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
++			FLD_VAL(hbp-1, 27, 20);
++
++		timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
++			FLD_VAL(vbp, 27, 20);
++	} else {
++		BUG_ON(hsw < 1 || hsw > 256);
++		BUG_ON(hfp < 1 || hfp > 4096);
++		BUG_ON(hbp < 1 || hbp > 4096);
++
++		BUG_ON(vsw < 1 || vsw > 256);
++		BUG_ON(vfp < 0 || vfp > 4095);
++		BUG_ON(vbp < 0 || vbp > 4095);
++
++		timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
++			FLD_VAL(hbp-1, 31, 20);
++
++		timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
++			FLD_VAL(vbp, 31, 20);
++	}
++
++	enable_clocks(1);
++	dispc_write_reg(DISPC_TIMING_H, timing_h);
++	dispc_write_reg(DISPC_TIMING_V, timing_v);
++	enable_clocks(0);
++}
++
++/* change name to mode? */
++void dispc_set_lcd_timings(struct omap_video_timings *timings)
++{
++	unsigned xtot, ytot;
++	unsigned long ht, vt;
++
++	_dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
++			timings->vsw, timings->vfp, timings->vbp);
++
++	dispc_set_lcd_size(timings->x_res, timings->y_res);
++
++	xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
++	ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
++
++	ht = (timings->pixel_clock * 1000) / xtot;
++	vt = (timings->pixel_clock * 1000) / xtot / ytot;
++
++	DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
++	DSSDBG("pck %u\n", timings->pixel_clock);
++	DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
++			timings->hsw, timings->hfp, timings->hbp,
++			timings->vsw, timings->vfp, timings->vbp);
++
++	DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
++}
++
++void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
++{
++	BUG_ON(lck_div < 1);
++	BUG_ON(pck_div < 2);
++
++	enable_clocks(1);
++	dispc_write_reg(DISPC_DIVISOR,
++			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
++	enable_clocks(0);
++}
++
++static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
++{
++	u32 l;
++	l = dispc_read_reg(DISPC_DIVISOR);
++	*lck_div = FLD_GET(l, 23, 16);
++	*pck_div = FLD_GET(l, 7, 0);
++}
++
++unsigned long dispc_fclk_rate(void)
++{
++	unsigned long r = 0;
++
++	if (dss_get_dispc_clk_source() == 0)
++		r = dss_clk_get_rate(DSS_CLK_FCK1);
++	else
++#ifdef CONFIG_OMAP2_DSS_DSI
++		r = dsi_get_dsi1_pll_rate();
++#else
++	BUG();
++#endif
++	return r;
++}
++
++unsigned long dispc_pclk_rate(void)
++{
++	int lcd, pcd;
++	unsigned long r;
++	u32 l;
++
++	l = dispc_read_reg(DISPC_DIVISOR);
++
++	lcd = FLD_GET(l, 23, 16);
++	pcd = FLD_GET(l, 7, 0);
++
++	r = dispc_fclk_rate();
++
++	return r / lcd / pcd;
++}
++
++void dispc_dump_clocks(struct seq_file *s)
++{
++	int lcd, pcd;
++
++	enable_clocks(1);
++
++	dispc_get_lcd_divisor(&lcd, &pcd);
++
++	seq_printf(s, "- dispc -\n");
++
++	seq_printf(s, "dispc fclk source = %s\n",
++			dss_get_dispc_clk_source() == 0 ?
++			"dss1_alwon_fclk" : "dsi1_pll_fclk");
++
++	seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
++			dispc_fclk_rate(),
++			lcd, pcd,
++			dispc_pclk_rate());
++
++	enable_clocks(0);
++}
++
++void dispc_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	DUMPREG(DISPC_REVISION);
++	DUMPREG(DISPC_SYSCONFIG);
++	DUMPREG(DISPC_SYSSTATUS);
++	DUMPREG(DISPC_IRQSTATUS);
++	DUMPREG(DISPC_IRQENABLE);
++	DUMPREG(DISPC_CONTROL);
++	DUMPREG(DISPC_CONFIG);
++	DUMPREG(DISPC_CAPABLE);
++	DUMPREG(DISPC_DEFAULT_COLOR0);
++	DUMPREG(DISPC_DEFAULT_COLOR1);
++	DUMPREG(DISPC_TRANS_COLOR0);
++	DUMPREG(DISPC_TRANS_COLOR1);
++	DUMPREG(DISPC_LINE_STATUS);
++	DUMPREG(DISPC_LINE_NUMBER);
++	DUMPREG(DISPC_TIMING_H);
++	DUMPREG(DISPC_TIMING_V);
++	DUMPREG(DISPC_POL_FREQ);
++	DUMPREG(DISPC_DIVISOR);
++	DUMPREG(DISPC_GLOBAL_ALPHA);
++	DUMPREG(DISPC_SIZE_DIG);
++	DUMPREG(DISPC_SIZE_LCD);
++
++	DUMPREG(DISPC_GFX_BA0);
++	DUMPREG(DISPC_GFX_BA1);
++	DUMPREG(DISPC_GFX_POSITION);
++	DUMPREG(DISPC_GFX_SIZE);
++	DUMPREG(DISPC_GFX_ATTRIBUTES);
++	DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
++	DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
++	DUMPREG(DISPC_GFX_ROW_INC);
++	DUMPREG(DISPC_GFX_PIXEL_INC);
++	DUMPREG(DISPC_GFX_WINDOW_SKIP);
++	DUMPREG(DISPC_GFX_TABLE_BA);
++
++	DUMPREG(DISPC_DATA_CYCLE1);
++	DUMPREG(DISPC_DATA_CYCLE2);
++	DUMPREG(DISPC_DATA_CYCLE3);
++
++	DUMPREG(DISPC_CPR_COEF_R);
++	DUMPREG(DISPC_CPR_COEF_G);
++	DUMPREG(DISPC_CPR_COEF_B);
++
++	DUMPREG(DISPC_GFX_PRELOAD);
++
++	DUMPREG(DISPC_VID_BA0(0));
++	DUMPREG(DISPC_VID_BA1(0));
++	DUMPREG(DISPC_VID_POSITION(0));
++	DUMPREG(DISPC_VID_SIZE(0));
++	DUMPREG(DISPC_VID_ATTRIBUTES(0));
++	DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
++	DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
++	DUMPREG(DISPC_VID_ROW_INC(0));
++	DUMPREG(DISPC_VID_PIXEL_INC(0));
++	DUMPREG(DISPC_VID_FIR(0));
++	DUMPREG(DISPC_VID_PICTURE_SIZE(0));
++	DUMPREG(DISPC_VID_ACCU0(0));
++	DUMPREG(DISPC_VID_ACCU1(0));
++
++	DUMPREG(DISPC_VID_BA0(1));
++	DUMPREG(DISPC_VID_BA1(1));
++	DUMPREG(DISPC_VID_POSITION(1));
++	DUMPREG(DISPC_VID_SIZE(1));
++	DUMPREG(DISPC_VID_ATTRIBUTES(1));
++	DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
++	DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
++	DUMPREG(DISPC_VID_ROW_INC(1));
++	DUMPREG(DISPC_VID_PIXEL_INC(1));
++	DUMPREG(DISPC_VID_FIR(1));
++	DUMPREG(DISPC_VID_PICTURE_SIZE(1));
++	DUMPREG(DISPC_VID_ACCU0(1));
++	DUMPREG(DISPC_VID_ACCU1(1));
++
++	DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
++	DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
++	DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
++	DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
++	DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
++	DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
++	DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
++	DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
++	DUMPREG(DISPC_VID_CONV_COEF(0, 0));
++	DUMPREG(DISPC_VID_CONV_COEF(0, 1));
++	DUMPREG(DISPC_VID_CONV_COEF(0, 2));
++	DUMPREG(DISPC_VID_CONV_COEF(0, 3));
++	DUMPREG(DISPC_VID_CONV_COEF(0, 4));
++	DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
++	DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
++	DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
++	DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
++	DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
++	DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
++	DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
++	DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
++
++	DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
++	DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
++	DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
++	DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
++	DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
++	DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
++	DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
++	DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
++	DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
++	DUMPREG(DISPC_VID_CONV_COEF(1, 0));
++	DUMPREG(DISPC_VID_CONV_COEF(1, 1));
++	DUMPREG(DISPC_VID_CONV_COEF(1, 2));
++	DUMPREG(DISPC_VID_CONV_COEF(1, 3));
++	DUMPREG(DISPC_VID_CONV_COEF(1, 4));
++	DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
++	DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
++	DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
++	DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
++	DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
++	DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
++	DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
++	DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
++
++	DUMPREG(DISPC_VID_PRELOAD(0));
++	DUMPREG(DISPC_VID_PRELOAD(1));
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
++				bool ihs, bool ivs, u8 acbi, u8 acb)
++{
++	u32 l = 0;
++
++	DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
++			onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
++
++	l |= FLD_VAL(onoff, 17, 17);
++	l |= FLD_VAL(rf, 16, 16);
++	l |= FLD_VAL(ieo, 15, 15);
++	l |= FLD_VAL(ipc, 14, 14);
++	l |= FLD_VAL(ihs, 13, 13);
++	l |= FLD_VAL(ivs, 12, 12);
++	l |= FLD_VAL(acbi, 11, 8);
++	l |= FLD_VAL(acb, 7, 0);
++
++	enable_clocks(1);
++	dispc_write_reg(DISPC_POL_FREQ, l);
++	enable_clocks(0);
++}
++
++void dispc_set_pol_freq(struct omap_panel *panel)
++{
++	_dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
++				 (panel->config & OMAP_DSS_LCD_RF) != 0,
++				 (panel->config & OMAP_DSS_LCD_IEO) != 0,
++				 (panel->config & OMAP_DSS_LCD_IPC) != 0,
++				 (panel->config & OMAP_DSS_LCD_IHS) != 0,
++				 (panel->config & OMAP_DSS_LCD_IVS) != 0,
++				 panel->acbi, panel->acb);
++}
++
++void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
++		u16 *lck_div, u16 *pck_div)
++{
++	u16 pcd_min = is_tft ? 2 : 3;
++	unsigned long best_pck;
++	u16 best_ld, cur_ld;
++	u16 best_pd, cur_pd;
++
++	best_pck = 0;
++	best_ld = 0;
++	best_pd = 0;
++
++	for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
++		unsigned long lck = fck / cur_ld;
++
++		for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
++			unsigned long pck = lck / cur_pd;
++			long old_delta = abs(best_pck - req_pck);
++			long new_delta = abs(pck - req_pck);
++
++			if (best_pck == 0 || new_delta < old_delta) {
++				best_pck = pck;
++				best_ld = cur_ld;
++				best_pd = cur_pd;
++
++				if (pck == req_pck)
++					goto found;
++			}
++
++			if (pck < req_pck)
++				break;
++		}
++
++		if (lck / pcd_min < req_pck)
++			break;
++	}
++
++found:
++	*lck_div = best_ld;
++	*pck_div = best_pd;
++}
++
++int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
++		struct dispc_clock_info *cinfo)
++{
++	unsigned long prate;
++	struct dispc_clock_info cur, best;
++	int match = 0;
++	int min_fck_per_pck;
++	unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
++
++	if (cpu_is_omap34xx())
++		prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++	else
++		prate = 0;
++
++	if (req_pck == dispc.cache_req_pck &&
++			((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
++			 dispc.cache_cinfo.fck == fck_rate)) {
++		DSSDBG("dispc clock info found from cache.\n");
++		*cinfo = dispc.cache_cinfo;
++		return 0;
++	}
++
++	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++	if (min_fck_per_pck &&
++		req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++		DSSERR("Requested pixel clock not possible with the current "
++				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++				"the constraint off.\n");
++		min_fck_per_pck = 0;
++	}
++
++retry:
++	memset(&cur, 0, sizeof(cur));
++	memset(&best, 0, sizeof(best));
++
++	if (cpu_is_omap24xx()) {
++		/* XXX can we change the clock on omap2? */
++		cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
++		cur.fck_div = 1;
++
++		match = 1;
++
++		find_lck_pck_divs(is_tft, req_pck, cur.fck,
++				&cur.lck_div, &cur.pck_div);
++
++		cur.lck = cur.fck / cur.lck_div;
++		cur.pck = cur.lck / cur.pck_div;
++
++		best = cur;
++
++		goto found;
++	} else if (cpu_is_omap34xx()) {
++		for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
++			cur.fck = prate / cur.fck_div * 2;
++
++			if (cur.fck > DISPC_MAX_FCK)
++				continue;
++
++			if (min_fck_per_pck &&
++					cur.fck < req_pck * min_fck_per_pck)
++				continue;
++
++			match = 1;
++
++			find_lck_pck_divs(is_tft, req_pck, cur.fck,
++					&cur.lck_div, &cur.pck_div);
++
++			cur.lck = cur.fck / cur.lck_div;
++			cur.pck = cur.lck / cur.pck_div;
++
++			if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
++				best = cur;
++
++				if (cur.pck == req_pck)
++					goto found;
++			}
++		}
++	} else {
++		BUG();
++	}
++
++found:
++	if (!match) {
++		if (min_fck_per_pck) {
++			DSSERR("Could not find suitable clock settings.\n"
++					"Turning FCK/PCK constraint off and"
++					"trying again.\n");
++			min_fck_per_pck = 0;
++			goto retry;
++		}
++
++		DSSERR("Could not find suitable clock settings.\n");
++
++		return -EINVAL;
++	}
++
++	if (cinfo)
++		*cinfo = best;
++
++	dispc.cache_req_pck = req_pck;
++	dispc.cache_prate = prate;
++	dispc.cache_cinfo = best;
++
++	return 0;
++}
++
++int dispc_set_clock_div(struct dispc_clock_info *cinfo)
++{
++	unsigned long prate;
++	int r;
++
++	if (cpu_is_omap34xx()) {
++		prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++		DSSDBG("dpll4_m4 = %ld\n", prate);
++	}
++
++	DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
++	DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
++	DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
++
++	if (cpu_is_omap34xx()) {
++		r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
++		if (r)
++			return r;
++	}
++
++	dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
++
++	return 0;
++}
++
++int dispc_get_clock_div(struct dispc_clock_info *cinfo)
++{
++	cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
++
++	if (cpu_is_omap34xx()) {
++		unsigned long prate;
++		prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++		cinfo->fck_div = prate / (cinfo->fck / 2);
++	} else {
++		cinfo->fck_div = 0;
++	}
++
++	cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
++	cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
++
++	cinfo->lck = cinfo->fck / cinfo->lck_div;
++	cinfo->pck = cinfo->lck / cinfo->pck_div;
++
++	return 0;
++}
++
++static void omap_dispc_set_irqs(void)
++{
++	unsigned long flags;
++	u32 mask = dispc.irq_error_mask;
++	int i;
++	struct omap_dispc_isr_data *isr_data;
++
++	spin_lock_irqsave(&dispc.irq_lock, flags);
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		isr_data = &dispc.registered_isr[i];
++
++		if (isr_data->isr == NULL)
++			continue;
++
++		mask |= isr_data->mask;
++	}
++
++	enable_clocks(1);
++	dispc_write_reg(DISPC_IRQENABLE, mask);
++	enable_clocks(0);
++
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
++}
++
++int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
++{
++	int i;
++	int ret;
++	unsigned long flags;
++	struct omap_dispc_isr_data *isr_data;
++
++	if (isr == NULL)
++		return -EINVAL;
++
++	spin_lock_irqsave(&dispc.irq_lock, flags);
++
++	/* check for duplicate entry */
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		isr_data = &dispc.registered_isr[i];
++		if (isr_data->isr == isr && isr_data->arg == arg &&
++				isr_data->mask == mask) {
++			ret = -EINVAL;
++			goto err;
++		}
++	}
++
++	isr_data = NULL;
++	ret = -EBUSY;
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		isr_data = &dispc.registered_isr[i];
++
++		if (isr_data->isr != NULL)
++			continue;
++
++		isr_data->isr = isr;
++		isr_data->arg = arg;
++		isr_data->mask = mask;
++		ret = 0;
++
++		break;
++	}
++err:
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++	if (ret == 0)
++		omap_dispc_set_irqs();
++
++	return ret;
++}
++EXPORT_SYMBOL(omap_dispc_register_isr);
++
++int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
++{
++	int i;
++	unsigned long flags;
++	int ret = -EINVAL;
++	struct omap_dispc_isr_data *isr_data;
++
++	spin_lock_irqsave(&dispc.irq_lock, flags);
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		isr_data = &dispc.registered_isr[i];
++		if (isr_data->isr != isr || isr_data->arg != arg ||
++				isr_data->mask != mask)
++			continue;
++
++		/* found the correct isr */
++
++		isr_data->isr = NULL;
++		isr_data->arg = NULL;
++		isr_data->mask = 0;
++
++		ret = 0;
++		break;
++	}
++
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++	if (ret == 0)
++		omap_dispc_set_irqs();
++
++	return ret;
++}
++EXPORT_SYMBOL(omap_dispc_unregister_isr);
++
++#ifdef DEBUG
++static void print_irq_status(u32 status)
++{
++	if ((status & dispc.irq_error_mask) == 0)
++		return;
++
++	printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++	if (status & DISPC_IRQ_##x) \
++		printk(#x " ");
++	PIS(GFX_FIFO_UNDERFLOW);
++	PIS(OCP_ERR);
++	PIS(VID1_FIFO_UNDERFLOW);
++	PIS(VID2_FIFO_UNDERFLOW);
++	PIS(SYNC_LOST);
++	PIS(SYNC_LOST_DIGIT);
++#undef PIS
++
++	printk("\n");
++}
++#endif
++
++/* Called from dss.c. Note that we don't touch clocks here,
++ * but we presume they are on because we got an IRQ. However,
++ * an irq handler may turn the clocks off, so we may not have
++ * clock later in the function. */
++void dispc_irq_handler(void)
++{
++	int i;
++	u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
++	u32 handledirqs = 0;
++	u32 unhandled_errors;
++	struct omap_dispc_isr_data *isr_data;
++
++#ifdef DEBUG
++	if (dss_debug)
++		print_irq_status(irqstatus);
++#endif
++	/* Ack the interrupt. Do it here before clocks are possibly turned
++	 * off */
++	dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		isr_data = &dispc.registered_isr[i];
++
++		if (!isr_data->isr)
++			continue;
++
++		if (isr_data->mask & irqstatus) {
++			isr_data->isr(isr_data->arg, irqstatus);
++			handledirqs |= isr_data->mask;
++		}
++	}
++
++	unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
++
++	if (unhandled_errors) {
++		spin_lock(&dispc.error_lock);
++		dispc.error_irqs |= unhandled_errors;
++		spin_unlock(&dispc.error_lock);
++
++		dispc.irq_error_mask &= ~unhandled_errors;
++		omap_dispc_set_irqs();
++
++		schedule_work(&dispc.error_work);
++	}
++}
++
++static void dispc_error_worker(struct work_struct *work)
++{
++	int i;
++	u32 errors;
++	unsigned long flags;
++
++	spin_lock_irqsave(&dispc.error_lock, flags);
++	errors = dispc.error_irqs;
++	dispc.error_irqs = 0;
++	spin_unlock_irqrestore(&dispc.error_lock, flags);
++
++	if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
++		DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
++		for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++			struct omap_overlay *ovl;
++			ovl = omap_dss_get_overlay(i);
++
++			if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++				continue;
++
++			if (ovl->id == 0) {
++				dispc_enable_plane(ovl->id, 0);
++				dispc_go(ovl->manager->id);
++				mdelay(50);
++				break;
++			}
++		}
++	}
++
++	if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
++		DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
++		for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++			struct omap_overlay *ovl;
++			ovl = omap_dss_get_overlay(i);
++
++			if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++				continue;
++
++			if (ovl->id == 1) {
++				dispc_enable_plane(ovl->id, 0);
++				dispc_go(ovl->manager->id);
++				mdelay(50);
++				break;
++			}
++		}
++	}
++
++	if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
++		DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
++		for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++			struct omap_overlay *ovl;
++			ovl = omap_dss_get_overlay(i);
++
++			if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++				continue;
++
++			if (ovl->id == 2) {
++				dispc_enable_plane(ovl->id, 0);
++				dispc_go(ovl->manager->id);
++				mdelay(50);
++				break;
++			}
++		}
++	}
++
++	if (errors & DISPC_IRQ_SYNC_LOST) {
++		DSSERR("SYNC_LOST, disabling LCD\n");
++		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
++			struct omap_overlay_manager *mgr;
++			mgr = omap_dss_get_overlay_manager(i);
++
++			if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
++				mgr->display->disable(mgr->display);
++				break;
++			}
++		}
++	}
++
++	if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
++		DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
++		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
++			struct omap_overlay_manager *mgr;
++			mgr = omap_dss_get_overlay_manager(i);
++
++			if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
++				mgr->display->disable(mgr->display);
++				break;
++			}
++		}
++	}
++
++	if (errors & DISPC_IRQ_OCP_ERR) {
++		DSSERR("OCP_ERR\n");
++		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
++			struct omap_overlay_manager *mgr;
++			mgr = omap_dss_get_overlay_manager(i);
++
++			if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
++				mgr->display->disable(mgr->display);
++		}
++	}
++
++	dispc.irq_error_mask |= errors;
++	omap_dispc_set_irqs();
++}
++
++int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
++{
++	void dispc_irq_wait_handler(void *data, u32 mask)
++	{
++		complete((struct completion *)data);
++	}
++
++	int r;
++	DECLARE_COMPLETION_ONSTACK(completion);
++
++	r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
++			irqmask);
++
++	if (r)
++		return r;
++
++	timeout = wait_for_completion_timeout(&completion, timeout);
++
++	omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
++
++	if (timeout == 0)
++		return -ETIMEDOUT;
++
++	if (timeout == -ERESTARTSYS)
++		return -ERESTARTSYS;
++
++	return 0;
++}
++
++int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
++		unsigned long timeout)
++{
++	void dispc_irq_wait_handler(void *data, u32 mask)
++	{
++		complete((struct completion *)data);
++	}
++
++	int r;
++	DECLARE_COMPLETION_ONSTACK(completion);
++
++	r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
++			irqmask);
++
++	if (r)
++		return r;
++
++	timeout = wait_for_completion_interruptible_timeout(&completion,
++			timeout);
++
++	omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
++
++	if (timeout == 0)
++		return -ETIMEDOUT;
++
++	if (timeout == -ERESTARTSYS)
++		return -ERESTARTSYS;
++
++	return 0;
++}
++
++#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
++void dispc_fake_vsync_irq(void)
++{
++	u32 irqstatus = DISPC_IRQ_VSYNC;
++	int i;
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		struct omap_dispc_isr_data *isr_data;
++		isr_data = &dispc.registered_isr[i];
++
++		if (!isr_data->isr)
++			continue;
++
++		if (isr_data->mask & irqstatus)
++			isr_data->isr(isr_data->arg, irqstatus);
++	}
++}
++#endif
++
++static void _omap_dispc_initialize_irq(void)
++{
++	memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
++
++	dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
++
++	/* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
++	 * so clear it */
++	dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
++
++	omap_dispc_set_irqs();
++}
++
++static void _omap_dispc_initial_config(void)
++{
++	u32 l;
++
++	l = dispc_read_reg(DISPC_SYSCONFIG);
++	l = FLD_MOD(l, 2, 13, 12);	/* MIDLEMODE: smart standby */
++	l = FLD_MOD(l, 2, 4, 3);	/* SIDLEMODE: smart idle */
++	l = FLD_MOD(l, 1, 2, 2);	/* ENWAKEUP */
++	l = FLD_MOD(l, 1, 0, 0);	/* AUTOIDLE */
++	dispc_write_reg(DISPC_SYSCONFIG, l);
++
++	/* FUNCGATED */
++	REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
++
++	/* L3 firewall setting: enable access to OCM RAM */
++	if (cpu_is_omap24xx())
++		__raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
++
++	_dispc_setup_color_conv_coef();
++
++	dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
++}
++
++int dispc_init(void)
++{
++	u32 rev;
++
++	spin_lock_init(&dispc.irq_lock);
++	spin_lock_init(&dispc.error_lock);
++
++	INIT_WORK(&dispc.error_work, dispc_error_worker);
++
++	dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
++	if (!dispc.base) {
++		DSSERR("can't ioremap DISPC\n");
++		return -ENOMEM;
++	}
++
++	if (cpu_is_omap34xx()) {
++		dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
++		if (IS_ERR(dispc.dpll4_m4_ck)) {
++			DSSERR("Failed to get dpll4_m4_ck\n");
++			return -ENODEV;
++		}
++	}
++
++	enable_clocks(1);
++
++	_omap_dispc_initial_config();
++
++	_omap_dispc_initialize_irq();
++
++	dispc_save_context();
++
++	rev = dispc_read_reg(DISPC_REVISION);
++	printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
++	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++	enable_clocks(0);
++
++	return 0;
++}
++
++void dispc_exit(void)
++{
++	if (cpu_is_omap34xx())
++		clk_put(dispc.dpll4_m4_ck);
++	iounmap(dispc.base);
++}
++
++int dispc_enable_plane(enum omap_plane plane, bool enable)
++{
++	DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
++
++	enable_clocks(1);
++	_dispc_enable_plane(plane, enable);
++	enable_clocks(0);
++
++	return 0;
++}
++
++int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
++		       u32 paddr, u16 screen_width,
++		       u16 pos_x, u16 pos_y,
++		       u16 width, u16 height,
++		       u16 out_width, u16 out_height,
++		       enum omap_color_mode color_mode,
++		       bool ilace,
++		       u8 rotation, bool mirror)
++{
++	int r = 0;
++
++	DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
++	       "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
++	       plane, channel_out, paddr, screen_width, pos_x, pos_y,
++	       width, height,
++	       out_width, out_height,
++	       ilace, color_mode,
++	       rotation, mirror);
++
++	enable_clocks(1);
++
++	r = _dispc_setup_plane(plane, channel_out,
++			   paddr, screen_width,
++			   pos_x, pos_y,
++			   width, height,
++			   out_width, out_height,
++			   color_mode, ilace,
++			   rotation, mirror);
++
++	enable_clocks(0);
++
++	return r;
++}
++
++static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
++				 int x2, int y2, int w2, int h2)
++{
++	if (x1 >= (x2+w2))
++		return 0;
++
++	if ((x1+w1) <= x2)
++		return 0;
++
++	if (y1 >= (y2+h2))
++		return 0;
++
++	if ((y1+h1) <= y2)
++		return 0;
++
++	return 1;
++}
++
++static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
++{
++	if (pi->width != pi->out_width)
++		return 1;
++
++	if (pi->height != pi->out_height)
++		return 1;
++
++	return 0;
++}
++
++/* returns the area that needs updating */
++void dispc_setup_partial_planes(struct omap_display *display,
++				    u16 *xi, u16 *yi, u16 *wi, u16 *hi)
++{
++	struct omap_overlay_manager *mgr;
++	int i;
++
++	int x, y, w, h;
++
++	x = *xi;
++	y = *yi;
++	w = *wi;
++	h = *hi;
++
++	DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
++		*xi, *yi, *wi, *hi);
++
++
++	mgr = display->manager;
++
++	if (!mgr) {
++		DSSDBG("no manager\n");
++		return;
++	}
++
++	for (i = 0; i < mgr->num_overlays; i++) {
++		struct omap_overlay *ovl;
++		struct omap_overlay_info *pi;
++		ovl = mgr->overlays[i];
++
++		if (ovl->manager != mgr)
++			continue;
++
++		if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
++			continue;
++
++		pi = &ovl->info;
++
++		if (!pi->enabled)
++			continue;
++		/*
++		 * If the plane is intersecting and scaled, we
++		 * enlarge the update region to accomodate the
++		 * whole area
++		 */
++
++		if (dispc_is_intersecting(x, y, w, h,
++					  pi->pos_x, pi->pos_y,
++					  pi->out_width, pi->out_height)) {
++			if (dispc_is_overlay_scaled(pi)) {
++
++				int x1, y1, x2, y2;
++
++				if (x > pi->pos_x)
++					x1 = pi->pos_x;
++				else
++					x1 = x;
++
++				if (y > pi->pos_y)
++					y1 = pi->pos_y;
++				else
++					y1 = y;
++
++				if ((x + w) < (pi->pos_x + pi->out_width))
++					x2 = pi->pos_x + pi->out_width;
++				else
++					x2 = x + w;
++
++				if ((y + h) < (pi->pos_y + pi->out_height))
++					y2 = pi->pos_y + pi->out_height;
++				else
++					y2 = y + h;
++
++				x = x1;
++				y = y1;
++				w = x2 - x1;
++				h = y2 - y1;
++
++				DSSDBG("Update area after enlarge due to "
++					"scaling %d, %d %dx%d\n",
++					x, y, w, h);
++			}
++		}
++	}
++
++	for (i = 0; i < mgr->num_overlays; i++) {
++		struct omap_overlay *ovl = mgr->overlays[i];
++		struct omap_overlay_info *pi = &ovl->info;
++
++		int px = pi->pos_x;
++		int py = pi->pos_y;
++		int pw = pi->width;
++		int ph = pi->height;
++		int pow = pi->out_width;
++		int poh = pi->out_height;
++		u32 pa = pi->paddr;
++		int psw = pi->screen_width;
++		int bpp;
++
++		if (ovl->manager != mgr)
++			continue;
++
++		/*
++		 * If plane is not enabled or the update region
++		 * does not intersect with the plane in question,
++		 * we really disable the plane from hardware
++		 */
++
++		if (!pi->enabled ||
++		    !dispc_is_intersecting(x, y, w, h,
++					   px, py, pow, poh)) {
++			dispc_enable_plane(ovl->id, 0);
++			continue;
++		}
++
++		switch (pi->color_mode) {
++		case OMAP_DSS_COLOR_RGB16:
++		case OMAP_DSS_COLOR_ARGB16:
++		case OMAP_DSS_COLOR_YUV2:
++		case OMAP_DSS_COLOR_UYVY:
++			bpp = 16;
++			break;
++
++		case OMAP_DSS_COLOR_RGB24P:
++			bpp = 24;
++			break;
++
++		case OMAP_DSS_COLOR_RGB24U:
++		case OMAP_DSS_COLOR_ARGB32:
++		case OMAP_DSS_COLOR_RGBA32:
++		case OMAP_DSS_COLOR_RGBX32:
++			bpp = 32;
++			break;
++
++		default:
++			BUG();
++			return;
++		}
++
++		if (x > pi->pos_x) {
++			px = 0;
++			pw -= (x - pi->pos_x);
++			pa += (x - pi->pos_x) * bpp / 8;
++		} else {
++			px = pi->pos_x - x;
++		}
++
++		if (y > pi->pos_y) {
++			py = 0;
++			ph -= (y - pi->pos_y);
++			pa += (y - pi->pos_y) * psw * bpp / 8;
++		} else {
++			py = pi->pos_y - y;
++		}
++
++		if (w < (px+pw))
++			pw -= (px+pw) - (w);
++
++		if (h < (py+ph))
++			ph -= (py+ph) - (h);
++
++		/* Can't scale the GFX plane */
++		if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
++				dispc_is_overlay_scaled(pi) == 0) {
++			pow = pw;
++			poh = ph;
++		}
++
++		DSSDBG("calc  plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
++				ovl->id, pa, psw, px, py, pw, ph, pow, poh);
++
++		dispc_setup_plane(ovl->id, mgr->id,
++				pa, psw,
++				px, py,
++				pw, ph,
++				pow, poh,
++				pi->color_mode, 0,
++				pi->rotation, // XXX rotation probably wrong
++				pi->mirror);
++
++		dispc_enable_plane(ovl->id, 1);
++	}
++
++	*xi = x;
++	*yi = y;
++	*wi = w;
++	*hi = h;
++
++}
++
+diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
+new file mode 100644
+index 0000000..9aaf392
+--- /dev/null
++++ b/drivers/video/omap2/dss/display.c
+@@ -0,0 +1,693 @@
++/*
++ * linux/drivers/video/omap2/dss/display.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DISPLAY"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/jiffies.h>
++#include <linux/list.h>
++#include <linux/platform_device.h>
++
++#include <mach/display.h>
++#include "dss.h"
++
++static int num_displays;
++static LIST_HEAD(display_list);
++
++static ssize_t display_name_show(struct omap_display *display, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%s\n", display->name);
++}
++
++static ssize_t display_enabled_show(struct omap_display *display, char *buf)
++{
++	bool enabled = display->state != OMAP_DSS_DISPLAY_DISABLED;
++
++	return snprintf(buf, PAGE_SIZE, "%d\n", enabled);
++}
++
++static ssize_t display_enabled_store(struct omap_display *display,
++		const char *buf, size_t size)
++{
++	bool enabled, r;
++
++	enabled = simple_strtoul(buf, NULL, 10);
++
++	if (enabled != (display->state != OMAP_DSS_DISPLAY_DISABLED)) {
++		if (enabled) {
++			r = display->enable(display);
++			if (r)
++				return r;
++		} else {
++			display->disable(display);
++		}
++	}
++
++	return size;
++}
++
++static ssize_t display_upd_mode_show(struct omap_display *display, char *buf)
++{
++	enum omap_dss_update_mode mode = OMAP_DSS_UPDATE_AUTO;
++	if (display->get_update_mode)
++		mode = display->get_update_mode(display);
++	return snprintf(buf, PAGE_SIZE, "%d\n", mode);
++}
++
++static ssize_t display_upd_mode_store(struct omap_display *display,
++		const char *buf, size_t size)
++{
++	int val, r;
++	enum omap_dss_update_mode mode;
++
++	val = simple_strtoul(buf, NULL, 10);
++
++	switch (val) {
++		case OMAP_DSS_UPDATE_DISABLED:
++		case OMAP_DSS_UPDATE_AUTO:
++		case OMAP_DSS_UPDATE_MANUAL:
++			mode = (enum omap_dss_update_mode)val;
++			break;
++		default:
++			return -EINVAL;
++	}
++
++	if ((r = display->set_update_mode(display, mode)))
++		return r;
++
++	return size;
++}
++
++static ssize_t display_tear_show(struct omap_display *display, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d\n",
++			display->get_te ? display->get_te(display) : 0);
++}
++
++static ssize_t display_tear_store(struct omap_display *display,
++		const char *buf, size_t size)
++{
++	unsigned long te;
++	int r;
++
++	if (!display->enable_te || !display->get_te)
++		return -ENOENT;
++
++	te = simple_strtoul(buf, NULL, 0);
++
++	if ((r = display->enable_te(display, te)))
++		return r;
++
++	return size;
++}
++
++static ssize_t display_timings_show(struct omap_display *display, char *buf)
++{
++	struct omap_video_timings t;
++
++	if (!display->get_timings)
++		return -ENOENT;
++
++	display->get_timings(display, &t);
++
++	return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n",
++			t.pixel_clock,
++			t.x_res, t.hfp, t.hbp, t.hsw,
++			t.y_res, t.vfp, t.vbp, t.vsw);
++}
++
++static ssize_t display_timings_store(struct omap_display *display,
++		const char *buf, size_t size)
++{
++	struct omap_video_timings t;
++	int r, found;
++
++	if (!display->set_timings || !display->check_timings)
++		return -ENOENT;
++
++	found = 0;
++#ifdef CONFIG_OMAP2_DSS_VENC
++	if (strncmp("pal", buf, 3) == 0) {
++		t = omap_dss_pal_timings;
++		found = 1;
++	} else if (strncmp("ntsc", buf, 4) == 0) {
++		t = omap_dss_ntsc_timings;
++		found = 1;
++	}
++#endif
++	if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu",
++				&t.pixel_clock,
++				&t.x_res, &t.hfp, &t.hbp, &t.hsw,
++				&t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9)
++		return -EINVAL;
++
++	if ((r = display->check_timings(display, &t)))
++		return r;
++
++	display->set_timings(display, &t);
++
++	return size;
++}
++
++static ssize_t display_rotate_show(struct omap_display *display, char *buf)
++{
++	int rotate;
++	if (!display->get_rotate)
++		return -ENOENT;
++	rotate = display->get_rotate(display);
++	return snprintf(buf, PAGE_SIZE, "%u\n", rotate);
++}
++
++static ssize_t display_rotate_store(struct omap_display *display,
++		const char *buf, size_t size)
++{
++	unsigned long rot;
++	int r;
++
++	if (!display->set_rotate || !display->get_rotate)
++		return -ENOENT;
++
++	rot = simple_strtoul(buf, NULL, 0);
++
++	if ((r = display->set_rotate(display, rot)))
++		return r;
++
++	return size;
++}
++
++static ssize_t display_mirror_show(struct omap_display *display, char *buf)
++{
++	int mirror;
++	if (!display->get_mirror)
++		return -ENOENT;
++	mirror = display->get_mirror(display);
++	return snprintf(buf, PAGE_SIZE, "%u\n", mirror);
++}
++
++static ssize_t display_mirror_store(struct omap_display *display,
++		const char *buf, size_t size)
++{
++	unsigned long mirror;
++	int r;
++
++	if (!display->set_mirror || !display->get_mirror)
++		return -ENOENT;
++
++	mirror = simple_strtoul(buf, NULL, 0);
++
++	if ((r = display->set_mirror(display, mirror)))
++		return r;
++
++	return size;
++}
++
++static ssize_t display_panel_name_show(struct omap_display *display, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%s\n",
++			display->panel ? display->panel->name : "");
++}
++
++static ssize_t display_ctrl_name_show(struct omap_display *display, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%s\n",
++			display->ctrl ? display->ctrl->name : "");
++}
++
++struct display_attribute {
++	struct attribute attr;
++	ssize_t (*show)(struct omap_display *, char *);
++	ssize_t	(*store)(struct omap_display *, const char *, size_t);
++};
++
++#define DISPLAY_ATTR(_name, _mode, _show, _store) \
++	struct display_attribute display_attr_##_name = \
++	__ATTR(_name, _mode, _show, _store)
++
++static DISPLAY_ATTR(name, S_IRUGO, display_name_show, NULL);
++static DISPLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
++		display_enabled_show, display_enabled_store);
++static DISPLAY_ATTR(update_mode, S_IRUGO|S_IWUSR,
++		display_upd_mode_show, display_upd_mode_store);
++static DISPLAY_ATTR(tear_elim, S_IRUGO|S_IWUSR,
++		display_tear_show, display_tear_store);
++static DISPLAY_ATTR(timings, S_IRUGO|S_IWUSR,
++		display_timings_show, display_timings_store);
++static DISPLAY_ATTR(rotate, S_IRUGO|S_IWUSR,
++		display_rotate_show, display_rotate_store);
++static DISPLAY_ATTR(mirror, S_IRUGO|S_IWUSR,
++		display_mirror_show, display_mirror_store);
++static DISPLAY_ATTR(panel_name, S_IRUGO, display_panel_name_show, NULL);
++static DISPLAY_ATTR(ctrl_name, S_IRUGO, display_ctrl_name_show, NULL);
++
++static struct attribute *display_sysfs_attrs[] = {
++	&display_attr_name.attr,
++	&display_attr_enabled.attr,
++	&display_attr_update_mode.attr,
++	&display_attr_tear_elim.attr,
++	&display_attr_timings.attr,
++	&display_attr_rotate.attr,
++	&display_attr_mirror.attr,
++	&display_attr_panel_name.attr,
++	&display_attr_ctrl_name.attr,
++	NULL
++};
++
++static ssize_t display_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
++{
++	struct omap_display *display;
++	struct display_attribute *display_attr;
++
++	display = container_of(kobj, struct omap_display, kobj);
++	display_attr = container_of(attr, struct display_attribute, attr);
++
++	if (!display_attr->show)
++		return -ENOENT;
++
++	return display_attr->show(display, buf);
++}
++
++static ssize_t display_attr_store(struct kobject *kobj, struct attribute *attr,
++		const char *buf, size_t size)
++{
++	struct omap_display *display;
++	struct display_attribute *display_attr;
++
++	display = container_of(kobj, struct omap_display, kobj);
++	display_attr = container_of(attr, struct display_attribute, attr);
++
++	if (!display_attr->store)
++		return -ENOENT;
++
++	return display_attr->store(display, buf, size);
++}
++
++static struct sysfs_ops display_sysfs_ops = {
++	.show = display_attr_show,
++	.store = display_attr_store,
++};
++
++static struct kobj_type display_ktype = {
++	.sysfs_ops = &display_sysfs_ops,
++	.default_attrs = display_sysfs_attrs,
++};
++
++static void default_get_resolution(struct omap_display *display,
++			u16 *xres, u16 *yres)
++{
++	*xres = display->panel->timings.x_res;
++	*yres = display->panel->timings.y_res;
++}
++
++static void default_configure_overlay(struct omap_overlay *ovl)
++{
++	unsigned low, high, size;
++	enum omap_burst_size burst;
++	enum omap_plane plane = ovl->id;
++
++	burst = OMAP_DSS_BURST_16x32;
++	size = 16 * 32 / 8;
++
++	dispc_set_burst_size(plane, burst);
++
++	high = dispc_get_plane_fifo_size(plane) - 1;
++	low = dispc_get_plane_fifo_size(plane) - size;
++
++	dispc_setup_plane_fifo(plane, low, high);
++}
++
++static int default_wait_vsync(struct omap_display *display)
++{
++	unsigned long timeout = msecs_to_jiffies(500);
++	u32 irq;
++
++	if (display->type == OMAP_DISPLAY_TYPE_VENC)
++		irq = DISPC_IRQ_EVSYNC_ODD;
++	else
++		irq = DISPC_IRQ_VSYNC;
++
++	return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
++}
++
++static int default_get_recommended_bpp(struct omap_display *display)
++{
++	if (display->panel->recommended_bpp)
++		return display->panel->recommended_bpp;
++
++	switch (display->type) {
++	case OMAP_DISPLAY_TYPE_DPI:
++		if (display->hw_config.u.dpi.data_lines == 24)
++			return 24;
++		else
++			return 16;
++
++	case OMAP_DISPLAY_TYPE_DBI:
++	case OMAP_DISPLAY_TYPE_DSI:
++		if (display->ctrl->pixel_size == 24)
++			return 24;
++		else
++			return 16;
++	case OMAP_DISPLAY_TYPE_VENC:
++	case OMAP_DISPLAY_TYPE_SDI:
++		return 24;
++		return 24;
++	default:
++		BUG();
++	}
++}
++
++void dss_init_displays(struct platform_device *pdev)
++{
++	struct omap_dss_board_info *pdata = pdev->dev.platform_data;
++	int i, r;
++
++	INIT_LIST_HEAD(&display_list);
++
++	num_displays = 0;
++
++	for (i = 0; i < pdata->num_displays; ++i) {
++		struct omap_display *display;
++
++		switch (pdata->displays[i]->type) {
++		case OMAP_DISPLAY_TYPE_DPI:
++#ifdef CONFIG_OMAP2_DSS_RFBI
++		case OMAP_DISPLAY_TYPE_DBI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++		case OMAP_DISPLAY_TYPE_SDI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++		case OMAP_DISPLAY_TYPE_DSI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_VENC
++		case OMAP_DISPLAY_TYPE_VENC:
++#endif
++			break;
++		default:
++			DSSERR("Support for display '%s' not compiled in.\n",
++					pdata->displays[i]->name);
++			continue;
++		}
++
++		display = kzalloc(sizeof(*display), GFP_KERNEL);
++
++		/*atomic_set(&display->ref_count, 0);*/
++		display->ref_count = 0;
++
++		display->hw_config = *pdata->displays[i];
++		display->type = pdata->displays[i]->type;
++		display->name = pdata->displays[i]->name;
++
++		display->get_resolution = default_get_resolution;
++		display->get_recommended_bpp = default_get_recommended_bpp;
++		display->configure_overlay = default_configure_overlay;
++		display->wait_vsync = default_wait_vsync;
++
++		switch (display->type) {
++		case OMAP_DISPLAY_TYPE_DPI:
++			dpi_init_display(display);
++			break;
++#ifdef CONFIG_OMAP2_DSS_RFBI
++		case OMAP_DISPLAY_TYPE_DBI:
++			rfbi_init_display(display);
++			break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_VENC
++		case OMAP_DISPLAY_TYPE_VENC:
++			venc_init_display(display);
++			break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++		case OMAP_DISPLAY_TYPE_SDI:
++			sdi_init_display(display);
++			break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++		case OMAP_DISPLAY_TYPE_DSI:
++			dsi_init_display(display);
++			break;
++#endif
++		default:
++			BUG();
++		}
++
++		r = kobject_init_and_add(&display->kobj, &display_ktype,
++				&pdev->dev.kobj, "display%d", num_displays);
++
++		if (r) {
++			DSSERR("failed to create sysfs file\n");
++			continue;
++		}
++
++		num_displays++;
++
++		list_add_tail(&display->list, &display_list);
++	}
++}
++
++void dss_uninit_displays(struct platform_device *pdev)
++{
++	struct omap_display *display;
++
++	while (!list_empty(&display_list)) {
++		display = list_first_entry(&display_list,
++				struct omap_display, list);
++		list_del(&display->list);
++		kobject_del(&display->kobj);
++		kobject_put(&display->kobj);
++		kfree(display);
++	}
++
++	num_displays = 0;
++}
++
++int dss_suspend_all_displays(void)
++{
++	int r;
++	struct omap_display *display;
++
++	list_for_each_entry(display, &display_list, list) {
++		if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
++			display->activate_after_resume = 0;
++			continue;
++		}
++
++		if (!display->suspend) {
++			DSSERR("display '%s' doesn't implement suspend\n",
++					display->name);
++			r = -ENOSYS;
++			goto err;
++		}
++
++		r = display->suspend(display);
++
++		if (r)
++			goto err;
++
++		display->activate_after_resume = 1;
++	}
++
++	return 0;
++err:
++	/* resume all displays that were suspended */
++	dss_resume_all_displays();
++	return r;
++}
++
++int dss_resume_all_displays(void)
++{
++	int r;
++	struct omap_display *display;
++
++	list_for_each_entry(display, &display_list, list) {
++		if (display->activate_after_resume && display->resume) {
++			r = display->resume(display);
++			if (r)
++				return r;
++		}
++
++		display->activate_after_resume = 0;
++	}
++
++	return 0;
++}
++
++int omap_dss_get_num_displays(void)
++{
++	return num_displays;
++}
++EXPORT_SYMBOL(omap_dss_get_num_displays);
++
++struct omap_display *dss_get_display(int no)
++{
++	int i = 0;
++	struct omap_display *display;
++
++	list_for_each_entry(display, &display_list, list) {
++		if (i++ == no)
++			return display;
++	}
++
++	return NULL;
++}
++
++struct omap_display *omap_dss_get_display(int no)
++{
++	struct omap_display *display;
++
++	display = dss_get_display(no);
++
++	if (!display)
++		return NULL;
++
++	switch (display->type) {
++	case OMAP_DISPLAY_TYPE_VENC:
++		break;
++
++	case OMAP_DISPLAY_TYPE_DPI:
++	case OMAP_DISPLAY_TYPE_SDI:
++		if (display->panel == NULL)
++			return NULL;
++		break;
++
++	case OMAP_DISPLAY_TYPE_DBI:
++	case OMAP_DISPLAY_TYPE_DSI:
++		if (display->panel == NULL || display->ctrl == NULL)
++			return NULL;
++		break;
++
++	default:
++		return NULL;
++	}
++
++	if (display->ctrl) {
++		if (!try_module_get(display->ctrl->owner))
++			goto err0;
++
++		if (display->ctrl->init)
++			if (display->ctrl->init(display) != 0)
++				goto err1;
++	}
++
++	if (display->panel) {
++		if (!try_module_get(display->panel->owner))
++			goto err2;
++
++		if (display->panel->init)
++			if (display->panel->init(display) != 0)
++				goto err3;
++	}
++
++	display->ref_count++;
++	/*
++	if (atomic_cmpxchg(&display->ref_count, 0, 1) != 0)
++		return 0;
++*/
++
++	return display;
++err3:
++	if (display->panel)
++		module_put(display->panel->owner);
++err2:
++	if (display->ctrl && display->ctrl->cleanup)
++		display->ctrl->cleanup(display);
++err1:
++	if (display->ctrl)
++		module_put(display->ctrl->owner);
++err0:
++	return NULL;
++}
++EXPORT_SYMBOL(omap_dss_get_display);
++
++void omap_dss_put_display(struct omap_display *display)
++{
++	if (--display->ref_count > 0)
++		return;
++/*
++	if (atomic_cmpxchg(&display->ref_count, 1, 0) != 1)
++		return;
++*/
++	if (display->ctrl) {
++		if (display->ctrl->cleanup)
++			display->ctrl->cleanup(display);
++		module_put(display->ctrl->owner);
++	}
++
++	if (display->panel) {
++		if (display->panel->cleanup)
++			display->panel->cleanup(display);
++		module_put(display->panel->owner);
++	}
++}
++EXPORT_SYMBOL(omap_dss_put_display);
++
++void omap_dss_register_ctrl(struct omap_ctrl *ctrl)
++{
++	struct omap_display *display;
++
++	list_for_each_entry(display, &display_list, list) {
++		if (display->hw_config.ctrl_name &&
++		    strcmp(display->hw_config.ctrl_name, ctrl->name) == 0) {
++			display->ctrl = ctrl;
++			DSSDBG("ctrl '%s' registered\n", ctrl->name);
++		}
++	}
++}
++EXPORT_SYMBOL(omap_dss_register_ctrl);
++
++void omap_dss_register_panel(struct omap_panel *panel)
++{
++	struct omap_display *display;
++
++	list_for_each_entry(display, &display_list, list) {
++		if (display->hw_config.panel_name &&
++		    strcmp(display->hw_config.panel_name, panel->name) == 0) {
++			display->panel = panel;
++			DSSDBG("panel '%s' registered\n", panel->name);
++		}
++	}
++}
++EXPORT_SYMBOL(omap_dss_register_panel);
++
++void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl)
++{
++	struct omap_display *display;
++
++	list_for_each_entry(display, &display_list, list) {
++		if (display->hw_config.ctrl_name &&
++		    strcmp(display->hw_config.ctrl_name, ctrl->name) == 0)
++			display->ctrl = NULL;
++	}
++}
++EXPORT_SYMBOL(omap_dss_unregister_ctrl);
++
++void omap_dss_unregister_panel(struct omap_panel *panel)
++{
++	struct omap_display *display;
++
++	list_for_each_entry(display, &display_list, list) {
++		if (display->hw_config.panel_name &&
++		    strcmp(display->hw_config.panel_name, panel->name) == 0)
++			display->panel = NULL;
++	}
++}
++EXPORT_SYMBOL(omap_dss_unregister_panel);
+diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
+new file mode 100644
+index 0000000..71fffca
+--- /dev/null
++++ b/drivers/video/omap2/dss/dpi.c
+@@ -0,0 +1,393 @@
++/*
++ * linux/drivers/video/omap2/dss/dpi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include <mach/cpu.h>
++
++#include "dss.h"
++
++static struct {
++	int update_enabled;
++} dpi;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
++		unsigned long *fck, int *lck_div, int *pck_div)
++{
++	struct dsi_clock_info cinfo;
++	int r;
++
++	r = dsi_pll_calc_pck(is_tft, pck_req, &cinfo);
++	if (r)
++		return r;
++
++	r = dsi_pll_program(&cinfo);
++	if (r)
++		return r;
++
++	dss_select_clk_source(0, 1);
++
++	dispc_set_lcd_divisor(cinfo.lck_div, cinfo.pck_div);
++
++	*fck = cinfo.dsi1_pll_fclk;
++	*lck_div = cinfo.lck_div;
++	*pck_div = cinfo.pck_div;
++
++	return 0;
++}
++#else
++static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
++		unsigned long *fck, int *lck_div, int *pck_div)
++{
++	struct dispc_clock_info cinfo;
++	int r;
++
++	r = dispc_calc_clock_div(is_tft, pck_req, &cinfo);
++	if (r)
++		return r;
++
++	r = dispc_set_clock_div(&cinfo);
++	if (r)
++		return r;
++
++	*fck = cinfo.fck;
++	*lck_div = cinfo.lck_div;
++	*pck_div = cinfo.pck_div;
++
++	return 0;
++}
++#endif
++
++static int dpi_set_mode(struct omap_display *display)
++{
++	struct omap_panel *panel = display->panel;
++	int lck_div, pck_div;
++	unsigned long fck;
++	unsigned long pck;
++	bool is_tft;
++	int r = 0;
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	dispc_set_pol_freq(panel);
++
++	is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	r = dpi_set_dsi_clk(is_tft, panel->timings.pixel_clock * 1000,
++			&fck, &lck_div, &pck_div);
++#else
++	r = dpi_set_dispc_clk(is_tft, panel->timings.pixel_clock * 1000,
++			&fck, &lck_div, &pck_div);
++#endif
++	if (r)
++		goto err0;
++
++	pck = fck / lck_div / pck_div / 1000;
++
++	if (pck != panel->timings.pixel_clock) {
++		DSSWARN("Could not find exact pixel clock. "
++				"Requested %d kHz, got %lu kHz\n",
++				panel->timings.pixel_clock, pck);
++
++		panel->timings.pixel_clock = pck;
++	}
++
++	dispc_set_lcd_timings(&panel->timings);
++
++err0:
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	return r;
++}
++
++static int dpi_basic_init(struct omap_display *display)
++{
++	bool is_tft;
++
++	is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
++	dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
++			OMAP_DSS_LCD_DISPLAY_STN);
++	dispc_set_tft_data_lines(display->hw_config.u.dpi.data_lines);
++
++	return 0;
++}
++
++static int dpi_display_enable(struct omap_display *display)
++{
++	struct omap_panel *panel = display->panel;
++	int r;
++
++	if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++		DSSERR("display already enabled\n");
++		return -EINVAL;
++	}
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	r = dpi_basic_init(display);
++	if (r)
++		goto err0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	dss_clk_enable(DSS_CLK_FCK2);
++	r = dsi_pll_init(0, 1);
++	if (r)
++		goto err1;
++#endif
++	r = dpi_set_mode(display);
++	if (r)
++		goto err2;
++
++	mdelay(2);
++
++	dispc_enable_lcd_out(1);
++
++	r = panel->enable(display);
++	if (r)
++		goto err3;
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	return 0;
++
++err3:
++	dispc_enable_lcd_out(0);
++err2:
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	dsi_pll_uninit();
++err1:
++	dss_clk_disable(DSS_CLK_FCK2);
++#endif
++err0:
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	return r;
++}
++
++static int dpi_display_resume(struct omap_display *display);
++
++static void dpi_display_disable(struct omap_display *display)
++{
++	if (display->state == OMAP_DSS_DISPLAY_DISABLED)
++		return;
++
++	if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
++		dpi_display_resume(display);
++
++	display->panel->disable(display);
++
++	dispc_enable_lcd_out(0);
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	dss_select_clk_source(0, 0);
++	dsi_pll_uninit();
++	dss_clk_disable(DSS_CLK_FCK2);
++#endif
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++}
++
++static int dpi_display_suspend(struct omap_display *display)
++{
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return -EINVAL;
++
++	DSSDBG("dpi_display_suspend\n");
++
++	if (display->panel->suspend)
++		display->panel->suspend(display);
++
++	dispc_enable_lcd_out(0);
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	display->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++	return 0;
++}
++
++static int dpi_display_resume(struct omap_display *display)
++{
++	if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
++		return -EINVAL;
++
++	DSSDBG("dpi_display_resume\n");
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	dispc_enable_lcd_out(1);
++
++	if (display->panel->resume)
++		display->panel->resume(display);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	return 0;
++}
++
++static void dpi_set_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	DSSDBG("dpi_set_timings\n");
++	display->panel->timings = *timings;
++	if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
++		dpi_set_mode(display);
++		dispc_go(OMAP_DSS_CHANNEL_LCD);
++	}
++}
++
++static int dpi_check_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	bool is_tft;
++	int r;
++	int lck_div, pck_div;
++	unsigned long fck;
++	unsigned long pck;
++
++	if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
++		if (timings->hsw < 1 || timings->hsw > 64 ||
++				timings->hfp < 1 || timings->hfp > 256 ||
++				timings->hbp < 1 || timings->hbp > 256) {
++			return -EINVAL;
++		}
++
++		if (timings->vsw < 1 || timings->vsw > 64 ||
++				timings->vfp > 255 || timings->vbp > 255) {
++			return -EINVAL;
++		}
++	} else {
++		if (timings->hsw < 1 || timings->hsw > 256 ||
++				timings->hfp < 1 || timings->hfp > 4096 ||
++				timings->hbp < 1 || timings->hbp > 4096) {
++			return -EINVAL;
++		}
++
++		if (timings->vsw < 1 || timings->vsw > 64 ||
++				timings->vfp > 4095 || timings->vbp > 4095) {
++			return -EINVAL;
++		}
++	}
++
++	if (timings->pixel_clock == 0)
++		return -EINVAL;
++
++	is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	{
++		struct dsi_clock_info cinfo;
++		r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
++				&cinfo);
++
++		if (r)
++			return r;
++
++		fck = cinfo.dsi1_pll_fclk;
++		lck_div = cinfo.lck_div;
++		pck_div = cinfo.pck_div;
++	}
++#else
++	{
++		struct dispc_clock_info cinfo;
++		r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
++				&cinfo);
++
++		if (r)
++			return r;
++
++		fck = cinfo.fck;
++		lck_div = cinfo.lck_div;
++		pck_div = cinfo.pck_div;
++	}
++#endif
++
++	pck = fck / lck_div / pck_div / 1000;
++
++	timings->pixel_clock = pck;
++
++	return 0;
++}
++
++static void dpi_get_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	*timings = display->panel->timings;
++}
++
++static int dpi_display_set_update_mode(struct omap_display *display,
++		enum omap_dss_update_mode mode)
++{
++	if (mode == OMAP_DSS_UPDATE_MANUAL)
++		return -EINVAL;
++
++	if (mode == OMAP_DSS_UPDATE_DISABLED) {
++		dispc_enable_lcd_out(0);
++		dpi.update_enabled = 0;
++	} else {
++		dispc_enable_lcd_out(1);
++		dpi.update_enabled = 1;
++	}
++
++	return 0;
++}
++
++static enum omap_dss_update_mode dpi_display_get_update_mode(
++		struct omap_display *display)
++{
++	return dpi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
++		OMAP_DSS_UPDATE_DISABLED;
++}
++
++void dpi_init_display(struct omap_display *display)
++{
++	DSSDBG("DPI init_display\n");
++
++	display->enable = dpi_display_enable;
++	display->disable = dpi_display_disable;
++	display->suspend = dpi_display_suspend;
++	display->resume = dpi_display_resume;
++	display->set_timings = dpi_set_timings;
++	display->check_timings = dpi_check_timings;
++	display->get_timings = dpi_get_timings;
++	display->set_update_mode = dpi_display_set_update_mode;
++	display->get_update_mode = dpi_display_get_update_mode;
++}
++
++int dpi_init(void)
++{
++	return 0;
++}
++
++void dpi_exit(void)
++{
++}
++
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+new file mode 100644
+index 0000000..4442931
+--- /dev/null
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -0,0 +1,3752 @@
++/*
++ * linux/drivers/video/omap2/dss/dsi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DSI"
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++#include <linux/mutex.h>
++#include <linux/seq_file.h>
++#include <linux/kfifo.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include <mach/clock.h>
++
++#include "dss.h"
++
++/*#define VERBOSE_IRQ*/
++
++#define DSI_BASE		0x4804FC00
++
++struct dsi_reg { u16 idx; };
++
++#define DSI_REG(idx)		((const struct dsi_reg) { idx })
++
++#define DSI_SZ_REGS		SZ_1K
++/* DSI Protocol Engine */
++
++#define DSI_REVISION			DSI_REG(0x0000)
++#define DSI_SYSCONFIG			DSI_REG(0x0010)
++#define DSI_SYSSTATUS			DSI_REG(0x0014)
++#define DSI_IRQSTATUS			DSI_REG(0x0018)
++#define DSI_IRQENABLE			DSI_REG(0x001C)
++#define DSI_CTRL			DSI_REG(0x0040)
++#define DSI_COMPLEXIO_CFG1		DSI_REG(0x0048)
++#define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(0x004C)
++#define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(0x0050)
++#define DSI_CLK_CTRL			DSI_REG(0x0054)
++#define DSI_TIMING1			DSI_REG(0x0058)
++#define DSI_TIMING2			DSI_REG(0x005C)
++#define DSI_VM_TIMING1			DSI_REG(0x0060)
++#define DSI_VM_TIMING2			DSI_REG(0x0064)
++#define DSI_VM_TIMING3			DSI_REG(0x0068)
++#define DSI_CLK_TIMING			DSI_REG(0x006C)
++#define DSI_TX_FIFO_VC_SIZE		DSI_REG(0x0070)
++#define DSI_RX_FIFO_VC_SIZE		DSI_REG(0x0074)
++#define DSI_COMPLEXIO_CFG2		DSI_REG(0x0078)
++#define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(0x007C)
++#define DSI_VM_TIMING4			DSI_REG(0x0080)
++#define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(0x0084)
++#define DSI_VM_TIMING5			DSI_REG(0x0088)
++#define DSI_VM_TIMING6			DSI_REG(0x008C)
++#define DSI_VM_TIMING7			DSI_REG(0x0090)
++#define DSI_STOPCLK_TIMING		DSI_REG(0x0094)
++#define DSI_VC_CTRL(n)			DSI_REG(0x0100 + (n * 0x20))
++#define DSI_VC_TE(n)			DSI_REG(0x0104 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(0x0108 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(0x010C + (n * 0x20))
++#define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(0x0110 + (n * 0x20))
++#define DSI_VC_IRQSTATUS(n)		DSI_REG(0x0118 + (n * 0x20))
++#define DSI_VC_IRQENABLE(n)		DSI_REG(0x011C + (n * 0x20))
++
++/* DSIPHY_SCP */
++
++#define DSI_DSIPHY_CFG0			DSI_REG(0x200 + 0x0000)
++#define DSI_DSIPHY_CFG1			DSI_REG(0x200 + 0x0004)
++#define DSI_DSIPHY_CFG2			DSI_REG(0x200 + 0x0008)
++#define DSI_DSIPHY_CFG5			DSI_REG(0x200 + 0x0014)
++
++/* DSI_PLL_CTRL_SCP */
++
++#define DSI_PLL_CONTROL			DSI_REG(0x300 + 0x0000)
++#define DSI_PLL_STATUS			DSI_REG(0x300 + 0x0004)
++#define DSI_PLL_GO			DSI_REG(0x300 + 0x0008)
++#define DSI_PLL_CONFIGURATION1		DSI_REG(0x300 + 0x000C)
++#define DSI_PLL_CONFIGURATION2		DSI_REG(0x300 + 0x0010)
++
++#define REG_GET(idx, start, end) \
++	FLD_GET(dsi_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++	dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
++
++/* Global interrupts */
++#define DSI_IRQ_VC0		(1 << 0)
++#define DSI_IRQ_VC1		(1 << 1)
++#define DSI_IRQ_VC2		(1 << 2)
++#define DSI_IRQ_VC3		(1 << 3)
++#define DSI_IRQ_WAKEUP		(1 << 4)
++#define DSI_IRQ_RESYNC		(1 << 5)
++#define DSI_IRQ_PLL_LOCK	(1 << 7)
++#define DSI_IRQ_PLL_UNLOCK	(1 << 8)
++#define DSI_IRQ_PLL_RECALL	(1 << 9)
++#define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
++#define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
++#define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
++#define DSI_IRQ_TE_TRIGGER	(1 << 16)
++#define DSI_IRQ_ACK_TRIGGER	(1 << 17)
++#define DSI_IRQ_SYNC_LOST	(1 << 18)
++#define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
++#define DSI_IRQ_TA_TIMEOUT	(1 << 20)
++#define DSI_IRQ_ERROR_MASK \
++	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
++	DSI_IRQ_TA_TIMEOUT)
++#define DSI_IRQ_CHANNEL_MASK	0xf
++
++/* Virtual channel interrupts */
++#define DSI_VC_IRQ_CS		(1 << 0)
++#define DSI_VC_IRQ_ECC_CORR	(1 << 1)
++#define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
++#define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
++#define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
++#define DSI_VC_IRQ_BTA		(1 << 5)
++#define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
++#define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
++#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
++#define DSI_VC_IRQ_ERROR_MASK \
++	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
++	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
++	DSI_VC_IRQ_FIFO_TX_UDF)
++
++/* ComplexIO interrupts */
++#define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
++#define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
++#define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
++#define DSI_CIO_IRQ_ERRESC1		(1 << 5)
++#define DSI_CIO_IRQ_ERRESC2		(1 << 6)
++#define DSI_CIO_IRQ_ERRESC3		(1 << 7)
++#define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
++#define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
++#define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
++#define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
++#define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
++#define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
++
++#define DSI_DT_DCS_SHORT_WRITE_0	0x05
++#define DSI_DT_DCS_SHORT_WRITE_1	0x15
++#define DSI_DT_DCS_READ			0x06
++#define DSI_DT_SET_MAX_RET_PKG_SIZE	0x37
++#define DSI_DT_NULL_PACKET		0x09
++#define DSI_DT_DCS_LONG_WRITE		0x39
++
++#define DSI_DT_RX_ACK_WITH_ERR		0x02
++#define DSI_DT_RX_DCS_LONG_READ		0x1c
++#define DSI_DT_RX_SHORT_READ_1		0x21
++#define DSI_DT_RX_SHORT_READ_2		0x22
++
++#define FINT_MAX 2100000
++#define FINT_MIN 750000
++#define REGN_MAX (1 << 7)
++#define REGM_MAX ((1 << 11) - 1)
++#define REGM3_MAX (1 << 4)
++#define REGM4_MAX (1 << 4)
++
++enum fifo_size {
++	DSI_FIFO_SIZE_0		= 0,
++	DSI_FIFO_SIZE_32	= 1,
++	DSI_FIFO_SIZE_64	= 2,
++	DSI_FIFO_SIZE_96	= 3,
++	DSI_FIFO_SIZE_128	= 4,
++};
++
++#define DSI_CMD_FIFO_LEN 16
++
++struct dsi_cmd_update {
++	int bytespp;
++	u16 x;
++	u16 y;
++	u16 w;
++	u16 h;
++};
++
++struct dsi_cmd_mem_read {
++	void *buf;
++	size_t size;
++	u16 x;
++	u16 y;
++	u16 w;
++	u16 h;
++	size_t *ret_size;
++	struct completion *completion;
++};
++
++struct dsi_cmd_test {
++	int test_num;
++	int *result;
++	struct completion *completion;
++};
++
++enum dsi_cmd {
++	DSI_CMD_UPDATE,
++	DSI_CMD_AUTOUPDATE,
++	DSI_CMD_SYNC,
++	DSI_CMD_MEM_READ,
++	DSI_CMD_TEST,
++	DSI_CMD_SET_TE,
++	DSI_CMD_SET_UPDATE_MODE,
++	DSI_CMD_SET_ROTATE,
++	DSI_CMD_SET_MIRROR,
++};
++
++struct dsi_cmd_item {
++	struct omap_display *display;
++
++	enum dsi_cmd cmd;
++
++	union {
++		struct dsi_cmd_update r;
++		struct completion *sync;
++		struct dsi_cmd_mem_read mem_read;
++		struct dsi_cmd_test test;
++		int te;
++		enum omap_dss_update_mode update_mode;
++		int rotate;
++		int mirror;
++	} u;
++};
++
++static struct
++{
++	void __iomem	*base;
++
++	unsigned long	dsi1_pll_fclk;	/* Hz */
++	unsigned long	dsi2_pll_fclk;	/* Hz */
++	unsigned long	dsiphy;		/* Hz */
++	unsigned long	ddr_clk;	/* Hz */
++
++	struct {
++		struct omap_display *display;
++		enum fifo_size fifo_size;
++		int dest_per;	/* destination peripheral 0-3 */
++	} vc[4];
++
++	struct mutex lock;
++
++	unsigned pll_locked;
++
++	struct completion bta_completion;
++
++	struct work_struct framedone_work;
++	struct work_struct process_work;
++	struct workqueue_struct *workqueue;
++
++	enum omap_dss_update_mode user_update_mode;
++	enum omap_dss_update_mode target_update_mode;
++	enum omap_dss_update_mode update_mode;
++	int use_te;
++	int framedone_scheduled; /* helps to catch strange framedone bugs */
++
++	unsigned long cache_req_pck;
++	unsigned long cache_clk_freq;
++	struct dsi_clock_info cache_cinfo;
++
++	struct kfifo      *cmd_fifo;
++	spinlock_t        cmd_lock;
++	struct completion cmd_done;
++	atomic_t          cmd_fifo_full;
++	atomic_t          cmd_pending;
++
++	bool autoupdate_setup;
++
++#ifdef DEBUG
++	ktime_t perf_setup_time;
++	ktime_t perf_start_time;
++	int perf_measure_frames;
++
++	struct {
++		int x, y, w, h;
++		int bytespp;
++	} update_region;
++
++#endif
++	int debug_process;
++	int debug_read;
++	int debug_write;
++} dsi;
++
++#ifdef DEBUG
++static unsigned int dsi_perf;
++module_param_named(dsi_perf, dsi_perf, bool, 0644);
++#endif
++
++static void dsi_process_cmd_fifo(struct work_struct *work);
++static void dsi_push_update(struct omap_display *display,
++		int x, int y, int w, int h);
++static void dsi_push_autoupdate(struct omap_display *display);
++
++static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
++{
++	__raw_writel(val, dsi.base + idx.idx);
++}
++
++static inline u32 dsi_read_reg(const struct dsi_reg idx)
++{
++	return __raw_readl(dsi.base + idx.idx);
++}
++
++
++void dsi_save_context(void)
++{
++}
++
++void dsi_restore_context(void)
++{
++}
++
++static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
++		int value)
++{
++	int t = 100000;
++
++	while (REG_GET(idx, bitnum, bitnum) != value) {
++		if (--t == 0)
++			return !value;
++	}
++
++	return value;
++}
++
++#ifdef DEBUG
++static void perf_mark_setup(void)
++{
++	dsi.perf_setup_time = ktime_get();
++}
++
++static void perf_mark_start(void)
++{
++	dsi.perf_start_time = ktime_get();
++}
++
++static void perf_show(const char *name)
++{
++	ktime_t t, setup_time, trans_time;
++	u32 total_bytes;
++	u32 setup_us, trans_us, total_us;
++	const int numframes = 100;
++	static u32 s_trans_us, s_min_us = 0xffffffff, s_max_us;
++
++	if (!dsi_perf)
++		return;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
++		return;
++
++	t = ktime_get();
++
++	setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
++	setup_us = (u32)ktime_to_us(setup_time);
++	if (setup_us == 0)
++		setup_us = 1;
++
++	trans_time = ktime_sub(t, dsi.perf_start_time);
++	trans_us = (u32)ktime_to_us(trans_time);
++	if (trans_us == 0)
++		trans_us = 1;
++
++	total_us = setup_us + trans_us;
++
++	total_bytes = dsi.update_region.w *
++		dsi.update_region.h *
++		dsi.update_region.bytespp;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++		dsi.perf_measure_frames++;
++
++		if (trans_us < s_min_us)
++			s_min_us = trans_us;
++
++		if (trans_us > s_max_us)
++			s_max_us = trans_us;
++
++		s_trans_us += trans_us;
++
++		if (dsi.perf_measure_frames < numframes)
++			return;
++
++		DSSINFO("%s update: %d frames in %u us "
++				"(min/max/avg %u/%u/%u), %u fps\n",
++				name, numframes,
++				s_trans_us,
++				s_min_us,
++				s_max_us,
++				s_trans_us / numframes,
++				1000*1000 / (s_trans_us / numframes));
++
++		dsi.perf_measure_frames = 0;
++		s_trans_us = 0;
++		s_min_us = 0xffffffff;
++		s_max_us = 0;
++	} else {
++		DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
++				"%u kbytes/sec\n",
++				name,
++				setup_us,
++				trans_us,
++				total_us,
++				1000*1000 / total_us,
++				total_bytes,
++				total_bytes * 1000 / total_us);
++	}
++}
++#else
++#define perf_mark_setup()
++#define perf_mark_start()
++#define perf_show(x)
++#endif
++
++static void print_irq_status(u32 status)
++{
++#ifndef VERBOSE_IRQ
++	if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
++		return;
++#endif
++	printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++	if (status & DSI_IRQ_##x) \
++		printk(#x " ");
++#ifdef VERBOSE_IRQ
++	PIS(VC0);
++	PIS(VC1);
++	PIS(VC2);
++	PIS(VC3);
++#endif
++	PIS(WAKEUP);
++	PIS(RESYNC);
++	PIS(PLL_LOCK);
++	PIS(PLL_UNLOCK);
++	PIS(PLL_RECALL);
++	PIS(COMPLEXIO_ERR);
++	PIS(HS_TX_TIMEOUT);
++	PIS(LP_RX_TIMEOUT);
++	PIS(TE_TRIGGER);
++	PIS(ACK_TRIGGER);
++	PIS(SYNC_LOST);
++	PIS(LDO_POWER_GOOD);
++	PIS(TA_TIMEOUT);
++#undef PIS
++
++	printk("\n");
++}
++
++static void print_irq_status_vc(int channel, u32 status)
++{
++#ifndef VERBOSE_IRQ
++	if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
++		return;
++#endif
++	printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
++
++#define PIS(x) \
++	if (status & DSI_VC_IRQ_##x) \
++		printk(#x " ");
++	PIS(CS);
++	PIS(ECC_CORR);
++#ifdef VERBOSE_IRQ
++	PIS(PACKET_SENT);
++#endif
++	PIS(FIFO_TX_OVF);
++	PIS(FIFO_RX_OVF);
++	PIS(BTA);
++	PIS(ECC_NO_CORR);
++	PIS(FIFO_TX_UDF);
++	PIS(PP_BUSY_CHANGE);
++#undef PIS
++	printk("\n");
++}
++
++static void print_irq_status_cio(u32 status)
++{
++	printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
++
++#define PIS(x) \
++	if (status & DSI_CIO_IRQ_##x) \
++		printk(#x " ");
++	PIS(ERRSYNCESC1);
++	PIS(ERRSYNCESC2);
++	PIS(ERRSYNCESC3);
++	PIS(ERRESC1);
++	PIS(ERRESC2);
++	PIS(ERRESC3);
++	PIS(ERRCONTROL1);
++	PIS(ERRCONTROL2);
++	PIS(ERRCONTROL3);
++	PIS(STATEULPS1);
++	PIS(STATEULPS2);
++	PIS(STATEULPS3);
++	PIS(ERRCONTENTIONLP0_1);
++	PIS(ERRCONTENTIONLP1_1);
++	PIS(ERRCONTENTIONLP0_2);
++	PIS(ERRCONTENTIONLP1_2);
++	PIS(ERRCONTENTIONLP0_3);
++	PIS(ERRCONTENTIONLP1_3);
++	PIS(ULPSACTIVENOT_ALL0);
++	PIS(ULPSACTIVENOT_ALL1);
++#undef PIS
++
++	printk("\n");
++}
++
++static int debug_irq;
++
++/* called from dss */
++void dsi_irq_handler(void)
++{
++	u32 irqstatus, vcstatus, ciostatus;
++	int i;
++
++	irqstatus = dsi_read_reg(DSI_IRQSTATUS);
++
++	if (irqstatus & DSI_IRQ_ERROR_MASK) {
++		DSSERR("DSI error, irqstatus %x\n", irqstatus);
++		print_irq_status(irqstatus);
++	} else if (debug_irq) {
++		print_irq_status(irqstatus);
++	}
++
++	for (i = 0; i < 4; ++i) {
++		if ((irqstatus & (1<<i)) == 0)
++			continue;
++
++		vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++
++		if (vcstatus & DSI_VC_IRQ_BTA)
++			complete(&dsi.bta_completion);
++
++		if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
++			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
++				       i, vcstatus);
++			print_irq_status_vc(i, vcstatus);
++		} else if (debug_irq) {
++			print_irq_status_vc(i, vcstatus);
++		}
++
++		dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
++	}
++
++	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
++		ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++
++		dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
++
++		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
++		print_irq_status_cio(ciostatus);
++	}
++
++	dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
++}
++
++
++static void _dsi_initialize_irq(void)
++{
++	u32 l;
++	int i;
++
++	/* disable all interrupts */
++	dsi_write_reg(DSI_IRQENABLE, 0);
++	for (i = 0; i < 4; ++i)
++		dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
++	dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
++
++	/* clear interrupt status */
++	l = dsi_read_reg(DSI_IRQSTATUS);
++	dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
++
++	for (i = 0; i < 4; ++i) {
++		l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++		dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
++	}
++
++	l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++	dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
++
++	/* enable error irqs */
++	l = DSI_IRQ_ERROR_MASK;
++	dsi_write_reg(DSI_IRQENABLE, l);
++
++	l = DSI_VC_IRQ_ERROR_MASK;
++	for (i = 0; i < 4; ++i)
++		dsi_write_reg(DSI_VC_IRQENABLE(i), l);
++
++	/* XXX zonda responds incorrectly, causing control error:
++	   Exit from LP-ESC mode to LP11 uses wrong transition states on the
++	   data lines LP0 and LN0. */
++	dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
++			-1 & (~DSI_CIO_IRQ_ERRCONTROL2));
++}
++
++static void dsi_vc_enable_bta_irq(int channel)
++{
++	u32 l;
++
++	l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++	l |= DSI_VC_IRQ_BTA;
++	dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++static void dsi_vc_disable_bta_irq(int channel)
++{
++	u32 l;
++
++	l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++	l &= ~DSI_VC_IRQ_BTA;
++	dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++/* DSI func clock. this could also be DSI2_PLL_FCLK */
++static inline void enable_clocks(bool enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	else
++		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++/* source clock for DSI PLL. this could also be PCLKFREE */
++static inline void dsi_enable_pll_clock(bool enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_FCK2);
++	else
++		dss_clk_disable(DSS_CLK_FCK2);
++
++	if (enable && dsi.pll_locked) {
++		if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
++			DSSERR("cannot lock PLL when enabling clocks\n");
++	}
++}
++
++#ifdef DEBUG
++static void _dsi_print_reset_status(void)
++{
++	u32 l;
++
++	if (!dss_debug)
++		return;
++
++	/* A dummy read using the SCP interface to any DSIPHY register is
++	 * required after DSIPHY reset to complete the reset of the DSI complex
++	 * I/O. */
++	l = dsi_read_reg(DSI_DSIPHY_CFG5);
++
++	printk(KERN_DEBUG "DSI resets: ");
++
++	l = dsi_read_reg(DSI_PLL_STATUS);
++	printk("PLL (%d) ", FLD_GET(l, 0, 0));
++
++	l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++	printk("CIO (%d) ", FLD_GET(l, 29, 29));
++
++	l = dsi_read_reg(DSI_DSIPHY_CFG5);
++	printk("PHY (%x, %d, %d, %d)\n",
++			FLD_GET(l, 28, 26),
++			FLD_GET(l, 29, 29),
++			FLD_GET(l, 30, 30),
++			FLD_GET(l, 31, 31));
++}
++#else
++#define _dsi_print_reset_status()
++#endif
++
++static inline int dsi_if_enable(bool enable)
++{
++	DSSDBG("dsi_if_enable(%d)\n", enable);
++
++	enable = enable ? 1 : 0;
++	REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
++
++	if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
++			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
++			return -EIO;
++	}
++
++	return 0;
++}
++
++static unsigned long dsi_fclk_rate(void)
++{
++	unsigned long r;
++
++	if (dss_get_dsi_clk_source() == 0) {
++		/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
++		r = dss_clk_get_rate(DSS_CLK_FCK1);
++	} else {
++		/* DSI FCLK source is DSI2_PLL_FCLK */
++		r = dsi.dsi2_pll_fclk;
++	}
++
++	return r;
++}
++
++static int dsi_set_lp_clk_divisor(void)
++{
++	int n;
++	unsigned long dsi_fclk;
++	unsigned long mhz;
++
++	/* LP_CLK_DIVISOR, DSI fclk/n, should be 20MHz - 32kHz */
++
++	dsi_fclk = dsi_fclk_rate();
++
++	for (n = 1; n < (1 << 13) - 1; ++n) {
++		mhz = dsi_fclk / n;
++		if (mhz <= 20*1000*1000)
++			break;
++	}
++
++	if (n == (1 << 13) - 1) {
++		DSSERR("Failed to find LP_CLK_DIVISOR\n");
++		return -EINVAL;
++	}
++
++	DSSDBG("LP_CLK_DIV %d, LP_CLK %ld\n", n, mhz);
++
++	REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0);	/* LP_CLK_DIVISOR */
++	if (dsi_fclk > 30*1000*1000)
++		REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
++
++	return 0;
++}
++
++
++enum dsi_pll_power_state {
++	DSI_PLL_POWER_OFF	= 0x0,
++	DSI_PLL_POWER_ON_HSCLK	= 0x1,
++	DSI_PLL_POWER_ON_ALL	= 0x2,
++	DSI_PLL_POWER_ON_DIV	= 0x3,
++};
++
++static int dsi_pll_power(enum dsi_pll_power_state state)
++{
++	int t = 0;
++
++	REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30);	/* PLL_PWR_CMD */
++
++	/* PLL_PWR_STATUS */
++	while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
++		udelay(1);
++		if (t++ > 1000) {
++			DSSERR("Failed to set DSI PLL power mode to %d\n",
++					state);
++			return -ENODEV;
++		}
++	}
++
++	return 0;
++}
++
++int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
++		struct dsi_clock_info *cinfo)
++{
++	struct dsi_clock_info cur, best;
++	int min_fck_per_pck;
++	int match = 0;
++
++	if (req_pck == dsi.cache_req_pck &&
++			dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
++		DSSDBG("DSI clock info found from cache\n");
++		*cinfo = dsi.cache_cinfo;
++		return 0;
++	}
++
++	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++	if (min_fck_per_pck &&
++		req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++		DSSERR("Requested pixel clock not possible with the current "
++				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++				"the constraint off.\n");
++		min_fck_per_pck = 0;
++	}
++
++	DSSDBG("dsi_pll_calc\n");
++
++retry:
++	memset(&best, 0, sizeof(best));
++
++	memset(&cur, 0, sizeof(cur));
++	cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
++	cur.use_dss2_fck = 1;
++	cur.highfreq = 0;
++
++	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++	for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++		if (cur.highfreq == 0)
++			cur.fint = cur.clkin / cur.regn;
++		else
++			cur.fint = cur.clkin / (2 * cur.regn);
++
++		if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++			continue;
++
++		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++		for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++			unsigned long a, b;
++
++			a = 2 * cur.regm * (cur.clkin/1000);
++			b = cur.regn * (cur.highfreq + 1);
++			cur.dsiphy = a / b * 1000;
++
++			if (cur.dsiphy > 1800 * 1000 * 1000)
++				break;
++
++			/* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3  < 173MHz */
++			for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
++					++cur.regm3) {
++				cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3;
++
++				/* this will narrow down the search a bit,
++				 * but still give pixclocks below what was
++				 * requested */
++				if (cur.dsi1_pll_fclk  < req_pck)
++					break;
++
++				if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
++					continue;
++
++				if (min_fck_per_pck &&
++					cur.dsi1_pll_fclk <
++						req_pck * min_fck_per_pck)
++					continue;
++
++				match = 1;
++
++				find_lck_pck_divs(is_tft, req_pck,
++						cur.dsi1_pll_fclk,
++						&cur.lck_div,
++						&cur.pck_div);
++
++				cur.lck = cur.dsi1_pll_fclk / cur.lck_div;
++				cur.pck = cur.lck / cur.pck_div;
++
++				if (abs(cur.pck - req_pck) <
++						abs(best.pck - req_pck)) {
++					best = cur;
++
++					if (cur.pck == req_pck)
++						goto found;
++				}
++			}
++		}
++	}
++found:
++	if (!match) {
++		if (min_fck_per_pck) {
++			DSSERR("Could not find suitable clock settings.\n"
++					"Turning FCK/PCK constraint off and"
++					"trying again.\n");
++			min_fck_per_pck = 0;
++			goto retry;
++		}
++
++		DSSERR("Could not find suitable clock settings.\n");
++
++		return -EINVAL;
++	}
++
++	/* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
++	best.regm4 = best.dsiphy / 48000000;
++	if (best.regm4 > REGM4_MAX)
++		best.regm4 = REGM4_MAX;
++	else if (best.regm4 == 0)
++		best.regm4 = 1;
++	best.dsi2_pll_fclk = best.dsiphy / best.regm4;
++
++	if (cinfo)
++		*cinfo = best;
++
++	dsi.cache_req_pck = req_pck;
++	dsi.cache_clk_freq = 0;
++	dsi.cache_cinfo = best;
++
++	return 0;
++}
++
++static int dsi_pll_calc_ddrfreq(unsigned long clk_freq,
++		struct dsi_clock_info *cinfo)
++{
++	struct dsi_clock_info cur, best;
++	const bool use_dss2_fck = 1;
++	unsigned long datafreq;
++
++	DSSDBG("dsi_pll_calc_ddrfreq\n");
++
++	if (clk_freq == dsi.cache_clk_freq &&
++			dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
++		DSSDBG("DSI clock info found from cache\n");
++		*cinfo = dsi.cache_cinfo;
++		return 0;
++	}
++
++	datafreq = clk_freq * 4;
++
++	memset(&best, 0, sizeof(best));
++
++	memset(&cur, 0, sizeof(cur));
++	cur.use_dss2_fck = use_dss2_fck;
++	if (use_dss2_fck) {
++		cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
++		cur.highfreq = 0;
++	} else {
++		cur.clkin = dispc_pclk_rate();
++		if (cur.clkin < 32000000)
++			cur.highfreq = 0;
++		else
++			cur.highfreq = 1;
++	}
++
++	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++	for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++		if (cur.highfreq == 0)
++			cur.fint = cur.clkin / cur.regn;
++		else
++			cur.fint = cur.clkin / (2 * cur.regn);
++
++		if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++			continue;
++
++		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++		for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++			unsigned long a, b;
++
++			a = 2 * cur.regm * (cur.clkin/1000);
++			b = cur.regn * (cur.highfreq + 1);
++			cur.dsiphy = a / b * 1000;
++
++			if (cur.dsiphy > 1800 * 1000 * 1000)
++				break;
++
++			if (abs(cur.dsiphy - datafreq) <
++					abs(best.dsiphy - datafreq)) {
++				best = cur;
++				/* DSSDBG("best %ld\n", best.dsiphy); */
++			}
++
++			if (cur.dsiphy == datafreq)
++				goto found;
++		}
++	}
++found:
++	/* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */
++	best.regm3 = best.dsiphy / 48000000;
++	if (best.regm3 > REGM3_MAX)
++		best.regm3 = REGM3_MAX;
++	else if (best.regm3 == 0)
++		best.regm3 = 1;
++	best.dsi1_pll_fclk = best.dsiphy / best.regm3;
++
++	/* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
++	best.regm4 = best.dsiphy / 48000000;
++	if (best.regm4 > REGM4_MAX)
++		best.regm4 = REGM4_MAX;
++	else if (best.regm4 == 0)
++		best.regm4 = 1;
++	best.dsi2_pll_fclk = best.dsiphy / best.regm4;
++
++	if (cinfo)
++		*cinfo = best;
++
++	dsi.cache_clk_freq = clk_freq;
++	dsi.cache_req_pck = 0;
++	dsi.cache_cinfo = best;
++
++	return 0;
++}
++
++int dsi_pll_program(struct dsi_clock_info *cinfo)
++{
++	int r = 0;
++	u32 l;
++
++	DSSDBG("dsi_pll_program\n");
++
++	dsi.dsiphy = cinfo->dsiphy;
++	dsi.ddr_clk = dsi.dsiphy / 4;
++	dsi.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
++	dsi.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
++
++	DSSDBG("DSI Fint %ld\n", cinfo->fint);
++
++	DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
++			cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
++			cinfo->clkin,
++			cinfo->highfreq);
++
++	/* DSIPHY == CLKIN4DDR */
++	DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
++			cinfo->regm,
++			cinfo->regn,
++			cinfo->clkin,
++			cinfo->highfreq + 1,
++			cinfo->dsiphy);
++
++	DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
++			dsi.dsiphy / 1000 / 1000 / 2);
++
++	DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
++
++	DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
++			cinfo->regm3, cinfo->dsi1_pll_fclk);
++	DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
++			cinfo->regm4, cinfo->dsi2_pll_fclk);
++
++	REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
++
++	l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
++	l = FLD_MOD(l, 1, 0, 0);		/* DSI_PLL_STOPMODE */
++	l = FLD_MOD(l, cinfo->regn - 1, 7, 1);	/* DSI_PLL_REGN */
++	l = FLD_MOD(l, cinfo->regm, 18, 8);	/* DSI_PLL_REGM */
++	l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19);	/* DSI_CLOCK_DIV */
++	l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23);	/* DSIPROTO_CLOCK_DIV */
++	dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
++
++	l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++	l = FLD_MOD(l, 7, 4, 1);		/* DSI_PLL_FREQSEL */
++	/* DSI_PLL_CLKSEL */
++	l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
++	l = FLD_MOD(l, cinfo->highfreq, 12, 12);	/* DSI_PLL_HIGHFREQ */
++	l = FLD_MOD(l, 1, 13, 13);		/* DSI_PLL_REFEN */
++	l = FLD_MOD(l, 0, 14, 14);		/* DSIPHY_CLKINEN */
++	l = FLD_MOD(l, 1, 20, 20);		/* DSI_HSDIVBYPASS */
++	dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++	REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
++
++	if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
++		DSSERR("dsi pll go bit not going down.\n");
++		r = -EIO;
++		goto err;
++	}
++
++	if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
++		DSSERR("cannot lock PLL\n");
++		r = -EIO;
++		goto err;
++	}
++
++	dsi.pll_locked = 1;
++
++	l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++	l = FLD_MOD(l, 0, 0, 0);	/* DSI_PLL_IDLE */
++	l = FLD_MOD(l, 0, 5, 5);	/* DSI_PLL_PLLLPMODE */
++	l = FLD_MOD(l, 0, 6, 6);	/* DSI_PLL_LOWCURRSTBY */
++	l = FLD_MOD(l, 0, 7, 7);	/* DSI_PLL_TIGHTPHASELOCK */
++	l = FLD_MOD(l, 0, 8, 8);	/* DSI_PLL_DRIFTGUARDEN */
++	l = FLD_MOD(l, 0, 10, 9);	/* DSI_PLL_LOCKSEL */
++	l = FLD_MOD(l, 1, 13, 13);	/* DSI_PLL_REFEN */
++	l = FLD_MOD(l, 1, 14, 14);	/* DSIPHY_CLKINEN */
++	l = FLD_MOD(l, 0, 15, 15);	/* DSI_BYPASSEN */
++	l = FLD_MOD(l, 1, 16, 16);	/* DSS_CLOCK_EN */
++	l = FLD_MOD(l, 0, 17, 17);	/* DSS_CLOCK_PWDN */
++	l = FLD_MOD(l, 1, 18, 18);	/* DSI_PROTO_CLOCK_EN */
++	l = FLD_MOD(l, 0, 19, 19);	/* DSI_PROTO_CLOCK_PWDN */
++	l = FLD_MOD(l, 0, 20, 20);	/* DSI_HSDIVBYPASS */
++	dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++	DSSDBG("PLL config done\n");
++err:
++	return r;
++}
++
++int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
++{
++	int r = 0;
++	enum dsi_pll_power_state pwstate;
++	struct dispc_clock_info cinfo;
++
++	DSSDBG("PLL init\n");
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	/* configure dispc fck and pixel clock to something sane */
++	r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
++	if (r)
++		goto err0;
++
++	r = dispc_set_clock_div(&cinfo);
++	if (r) {
++		DSSERR("Failed to set basic clocks\n");
++		goto err0;
++	}
++
++	r = dss_dsi_power_up();
++	if (r)
++		goto err0;
++
++	/* PLL does not come out of reset without this... */
++	dispc_pck_free_enable(1);
++
++	if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
++		DSSERR("PLL not coming out of reset.\n");
++		r = -ENODEV;
++		goto err1;
++	}
++
++	/* ... but if left on, we get problems when planes do not
++	 * fill the whole display. No idea about this XXX */
++	dispc_pck_free_enable(0);
++
++	if (enable_hsclk && enable_hsdiv)
++		pwstate = DSI_PLL_POWER_ON_ALL;
++	else if (enable_hsclk)
++		pwstate = DSI_PLL_POWER_ON_HSCLK;
++	else if (enable_hsdiv)
++		pwstate = DSI_PLL_POWER_ON_DIV;
++	else
++		pwstate = DSI_PLL_POWER_OFF;
++
++	r = dsi_pll_power(pwstate);
++
++	if (r)
++		goto err1;
++
++	DSSDBG("PLL init done\n");
++
++	return 0;
++err1:
++	dss_dsi_power_down();
++err0:
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++	return r;
++}
++
++void dsi_pll_uninit(void)
++{
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++
++	dsi.pll_locked = 0;
++	dsi_pll_power(DSI_PLL_POWER_OFF);
++	dss_dsi_power_down();
++	DSSDBG("PLL uninit done\n");
++}
++
++unsigned long dsi_get_dsi1_pll_rate(void)
++{
++	return dsi.dsi1_pll_fclk;
++}
++
++unsigned long dsi_get_dsi2_pll_rate(void)
++{
++	return dsi.dsi2_pll_fclk;
++}
++
++void dsi_dump_clocks(struct seq_file *s)
++{
++	int clksel;
++
++	enable_clocks(1);
++
++	clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
++
++	seq_printf(s, "- dsi -\n");
++
++	seq_printf(s, "dsi fclk source = %s\n",
++			dss_get_dsi_clk_source() == 0 ?
++			"dss1_alwon_fclk" : "dsi2_pll_fclk");
++
++	seq_printf(s, "dsi pll source = %s\n",
++			clksel == 0 ?
++			"dss2_alwon_fclk" : "pclkfree");
++
++	seq_printf(s,	"DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
++			dsi.dsiphy, dsi.ddr_clk);
++
++	seq_printf(s,	"dsi1_pll_fck\t%lu (%s)\n"
++			"dsi2_pll_fck\t%lu (%s)\n",
++			dsi.dsi1_pll_fclk,
++			dss_get_dispc_clk_source() == 0 ? "off" : "on",
++			dsi.dsi2_pll_fclk,
++			dss_get_dsi_clk_source() == 0 ? "off" : "on");
++
++	enable_clocks(0);
++}
++
++void dsi_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	DUMPREG(DSI_REVISION);
++	DUMPREG(DSI_SYSCONFIG);
++	DUMPREG(DSI_SYSSTATUS);
++	DUMPREG(DSI_IRQSTATUS);
++	DUMPREG(DSI_IRQENABLE);
++	DUMPREG(DSI_CTRL);
++	DUMPREG(DSI_COMPLEXIO_CFG1);
++	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
++	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
++	DUMPREG(DSI_CLK_CTRL);
++	DUMPREG(DSI_TIMING1);
++	DUMPREG(DSI_TIMING2);
++	DUMPREG(DSI_VM_TIMING1);
++	DUMPREG(DSI_VM_TIMING2);
++	DUMPREG(DSI_VM_TIMING3);
++	DUMPREG(DSI_CLK_TIMING);
++	DUMPREG(DSI_TX_FIFO_VC_SIZE);
++	DUMPREG(DSI_RX_FIFO_VC_SIZE);
++	DUMPREG(DSI_COMPLEXIO_CFG2);
++	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
++	DUMPREG(DSI_VM_TIMING4);
++	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
++	DUMPREG(DSI_VM_TIMING5);
++	DUMPREG(DSI_VM_TIMING6);
++	DUMPREG(DSI_VM_TIMING7);
++	DUMPREG(DSI_STOPCLK_TIMING);
++
++	DUMPREG(DSI_VC_CTRL(0));
++	DUMPREG(DSI_VC_TE(0));
++	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
++	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
++	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
++	DUMPREG(DSI_VC_IRQSTATUS(0));
++	DUMPREG(DSI_VC_IRQENABLE(0));
++
++	DUMPREG(DSI_VC_CTRL(1));
++	DUMPREG(DSI_VC_TE(1));
++	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
++	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
++	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
++	DUMPREG(DSI_VC_IRQSTATUS(1));
++	DUMPREG(DSI_VC_IRQENABLE(1));
++
++	DUMPREG(DSI_VC_CTRL(2));
++	DUMPREG(DSI_VC_TE(2));
++	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
++	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
++	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
++	DUMPREG(DSI_VC_IRQSTATUS(2));
++	DUMPREG(DSI_VC_IRQENABLE(2));
++
++	DUMPREG(DSI_VC_CTRL(3));
++	DUMPREG(DSI_VC_TE(3));
++	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
++	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
++	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
++	DUMPREG(DSI_VC_IRQSTATUS(3));
++	DUMPREG(DSI_VC_IRQENABLE(3));
++
++	DUMPREG(DSI_DSIPHY_CFG0);
++	DUMPREG(DSI_DSIPHY_CFG1);
++	DUMPREG(DSI_DSIPHY_CFG2);
++	DUMPREG(DSI_DSIPHY_CFG5);
++
++	DUMPREG(DSI_PLL_CONTROL);
++	DUMPREG(DSI_PLL_STATUS);
++	DUMPREG(DSI_PLL_GO);
++	DUMPREG(DSI_PLL_CONFIGURATION1);
++	DUMPREG(DSI_PLL_CONFIGURATION2);
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++enum dsi_complexio_power_state {
++	DSI_COMPLEXIO_POWER_OFF		= 0x0,
++	DSI_COMPLEXIO_POWER_ON		= 0x1,
++	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
++};
++
++static int dsi_complexio_power(enum dsi_complexio_power_state state)
++{
++	int t = 0;
++
++	/* PWR_CMD */
++	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
++
++	/* PWR_STATUS */
++	while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
++		udelay(1);
++		if (t++ > 1000) {
++			DSSERR("failed to set complexio power state to "
++					"%d\n", state);
++			return -ENODEV;
++		}
++	}
++
++	return 0;
++}
++
++static void dsi_complexio_config(struct omap_display *display)
++{
++	u32 r;
++
++	int clk_lane   = display->hw_config.u.dsi.clk_lane;
++	int data1_lane = display->hw_config.u.dsi.data1_lane;
++	int data2_lane = display->hw_config.u.dsi.data2_lane;
++	int clk_pol    = display->hw_config.u.dsi.clk_pol;
++	int data1_pol  = display->hw_config.u.dsi.data1_pol;
++	int data2_pol  = display->hw_config.u.dsi.data2_pol;
++
++	r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++	r = FLD_MOD(r, clk_lane, 2, 0);
++	r = FLD_MOD(r, clk_pol, 3, 3);
++	r = FLD_MOD(r, data1_lane, 6, 4);
++	r = FLD_MOD(r, data1_pol, 7, 7);
++	r = FLD_MOD(r, data2_lane, 10, 8);
++	r = FLD_MOD(r, data2_pol, 11, 11);
++	dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
++
++	/* The configuration of the DSI complex I/O (number of data lanes,
++	   position, differential order) should not be changed while
++	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
++	   the hardware to take into account a new configuration of the complex
++	   I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
++	   follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
++	   then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
++	   DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
++	   DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
++	   DSI complex I/O configuration is unknown. */
++
++	/*
++	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++	REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
++	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
++	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++	*/
++}
++
++static inline unsigned ns2ddr(unsigned ns)
++{
++	/* convert time in ns to ddr ticks, rounding up */
++	return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
++}
++
++static inline unsigned ddr2ns(unsigned ddr)
++{
++	return ddr * 1000 * 1000 / (dsi.ddr_clk / 1000);
++}
++
++static void dsi_complexio_timings(void)
++{
++	u32 r;
++	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
++	u32 tlpx_half, tclk_trail, tclk_zero;
++	u32 tclk_prepare;
++
++	/* calculate timings */
++
++	/* 1 * DDR_CLK = 2 * UI */
++
++	/* min 40ns + 4*UI	max 85ns + 6*UI */
++	ths_prepare = ns2ddr(59) + 2;
++
++	/* min 145ns + 10*UI */
++	ths_prepare_ths_zero = ns2ddr(145) + 5;
++
++	/* min max(8*UI, 60ns+4*UI) */
++	ths_trail = max((unsigned)4, ns2ddr(60) + 2);
++
++	/* min 100ns */
++	ths_exit = ns2ddr(100);
++
++	/* tlpx min 50n */
++	tlpx_half = ns2ddr(25);
++
++	/* min 60ns */
++	tclk_trail = ns2ddr(60);
++
++	/* min 38ns, max 95ns */
++	tclk_prepare = ns2ddr(38);
++
++	/* min tclk-prepare + tclk-zero = 300ns */
++	tclk_zero = ns2ddr(300 - 38);
++
++	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
++		ths_prepare, ddr2ns(ths_prepare),
++		ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
++	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
++			ths_trail, ddr2ns(ths_trail),
++			ths_exit, ddr2ns(ths_exit));
++
++	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
++			"tclk_zero %u (%uns)\n",
++			tlpx_half, ddr2ns(tlpx_half),
++			tclk_trail, ddr2ns(tclk_trail),
++			tclk_zero, ddr2ns(tclk_zero));
++	DSSDBG("tclk_prepare %u (%uns)\n",
++			tclk_prepare, ddr2ns(tclk_prepare));
++
++	/* program timings */
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG0);
++	r = FLD_MOD(r, ths_prepare, 31, 24);
++	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
++	r = FLD_MOD(r, ths_trail, 15, 8);
++	r = FLD_MOD(r, ths_exit, 7, 0);
++	dsi_write_reg(DSI_DSIPHY_CFG0, r);
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG1);
++	r = FLD_MOD(r, tlpx_half, 22, 16);
++	r = FLD_MOD(r, tclk_trail, 15, 8);
++	r = FLD_MOD(r, tclk_zero, 7, 0);
++	dsi_write_reg(DSI_DSIPHY_CFG1, r);
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG2);
++	r = FLD_MOD(r, tclk_prepare, 7, 0);
++	dsi_write_reg(DSI_DSIPHY_CFG2, r);
++}
++
++
++static int dsi_complexio_init(struct omap_display *display)
++{
++	int r = 0;
++
++	DSSDBG("dsi_complexio_init\n");
++
++	/* CIO_CLK_ICG, enable L3 clk to CIO */
++	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
++
++	/* A dummy read using the SCP interface to any DSIPHY register is
++	 * required after DSIPHY reset to complete the reset of the DSI complex
++	 * I/O. */
++	dsi_read_reg(DSI_DSIPHY_CFG5);
++
++	if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
++		DSSERR("ComplexIO PHY not coming out of reset.\n");
++		r = -ENODEV;
++		goto err;
++	}
++
++	dsi_complexio_config(display);
++
++	r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
++
++	if (r)
++		goto err;
++
++	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
++		DSSERR("ComplexIO not coming out of reset.\n");
++		r = -ENODEV;
++		goto err;
++	}
++
++	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
++		DSSERR("ComplexIO LDO power down.\n");
++		r = -ENODEV;
++		goto err;
++	}
++
++	dsi_complexio_timings();
++
++	/*
++	   The configuration of the DSI complex I/O (number of data lanes,
++	   position, differential order) should not be changed while
++	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
++	   hardware to recognize a new configuration of the complex I/O (done
++	   in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
++	   this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
++	   reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
++	   LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
++	   bit to 1. If the sequence is not followed, the DSi complex I/O
++	   configuration is undetermined.
++	   */
++	dsi_if_enable(1);
++	dsi_if_enable(0);
++	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
++	dsi_if_enable(1);
++	dsi_if_enable(0);
++
++	DSSDBG("CIO init done\n");
++err:
++	return r;
++}
++
++static void dsi_complexio_uninit(void)
++{
++	dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
++}
++
++static int _dsi_wait_reset(void)
++{
++	int i = 0;
++
++	while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
++		if (i++ > 5) {
++			DSSERR("soft reset failed\n");
++			return -ENODEV;
++		}
++		udelay(1);
++	}
++
++	return 0;
++}
++
++static int _dsi_reset(void)
++{
++	/* Soft reset */
++	REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
++	return _dsi_wait_reset();
++}
++
++
++static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
++		enum fifo_size size3, enum fifo_size size4)
++{
++	u32 r = 0;
++	int add = 0;
++	int i;
++
++	dsi.vc[0].fifo_size = size1;
++	dsi.vc[1].fifo_size = size2;
++	dsi.vc[2].fifo_size = size3;
++	dsi.vc[3].fifo_size = size4;
++
++	for (i = 0; i < 4; i++) {
++		u8 v;
++		int size = dsi.vc[i].fifo_size;
++
++		if (add + size > 4) {
++			DSSERR("Illegal FIFO configuration\n");
++			BUG();
++		}
++
++		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++		r |= v << (8 * i);
++		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
++		add += size;
++	}
++
++	dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
++}
++
++static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
++		enum fifo_size size3, enum fifo_size size4)
++{
++	u32 r = 0;
++	int add = 0;
++	int i;
++
++	dsi.vc[0].fifo_size = size1;
++	dsi.vc[1].fifo_size = size2;
++	dsi.vc[2].fifo_size = size3;
++	dsi.vc[3].fifo_size = size4;
++
++	for (i = 0; i < 4; i++) {
++		u8 v;
++		int size = dsi.vc[i].fifo_size;
++
++		if (add + size > 4) {
++			DSSERR("Illegal FIFO configuration\n");
++			BUG();
++		}
++
++		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++		r |= v << (8 * i);
++		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
++		add += size;
++	}
++
++	dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
++}
++
++static int dsi_force_tx_stop_mode_io(void)
++{
++	u32 r;
++
++	r = dsi_read_reg(DSI_TIMING1);
++	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
++	dsi_write_reg(DSI_TIMING1, r);
++
++	if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
++		DSSERR("TX_STOP bit not going down\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static void dsi_vc_print_status(int channel)
++{
++	u32 r;
++
++	r = dsi_read_reg(DSI_VC_CTRL(channel));
++	DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
++			"TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
++			channel,
++			FLD_GET(r, 5, 5),
++			FLD_GET(r, 6, 6),
++			FLD_GET(r, 15, 15),
++			FLD_GET(r, 16, 16),
++			FLD_GET(r, 20, 20));
++
++	r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
++	DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
++}
++
++static void dsi_vc_config(int channel)
++{
++	u32 r;
++
++	DSSDBG("dsi_vc_config %d\n", channel);
++
++	r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
++	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
++	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
++
++	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++	dsi_write_reg(DSI_VC_CTRL(channel), r);
++}
++
++static void dsi_vc_config_vp(int channel)
++{
++	u32 r;
++
++	DSSDBG("dsi_vc_config_vp\n");
++
++	r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++	r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
++	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
++	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++	r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
++
++	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++	dsi_write_reg(DSI_VC_CTRL(channel), r);
++}
++
++
++static int dsi_vc_enable(int channel, bool enable)
++{
++	DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable);
++
++	enable = enable ? 1 : 0;
++
++	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
++
++	if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
++			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
++			return -EIO;
++	}
++
++	return 0;
++}
++
++static void dsi_vc_enable_hs(int channel, bool enable)
++{
++	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
++
++	dsi_vc_enable(channel, 0);
++	dsi_if_enable(0);
++
++	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
++
++	dsi_vc_enable(channel, 1);
++	dsi_if_enable(1);
++
++	dsi_force_tx_stop_mode_io();
++}
++
++static void dsi_vc_flush_long_data(int channel)
++{
++	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++		u32 val;
++		val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
++				(val >> 0) & 0xff,
++				(val >> 8) & 0xff,
++				(val >> 16) & 0xff,
++				(val >> 24) & 0xff);
++	}
++}
++
++static void dsi_show_rx_ack_with_err(u16 err)
++{
++	DSSERR("\tACK with ERROR (%#x):\n", err);
++	if (err & (1 << 0))
++		DSSERR("\t\tSoT Error\n");
++	if (err & (1 << 1))
++		DSSERR("\t\tSoT Sync Error\n");
++	if (err & (1 << 2))
++		DSSERR("\t\tEoT Sync Error\n");
++	if (err & (1 << 3))
++		DSSERR("\t\tEscape Mode Entry Command Error\n");
++	if (err & (1 << 4))
++		DSSERR("\t\tLP Transmit Sync Error\n");
++	if (err & (1 << 5))
++		DSSERR("\t\tHS Receive Timeout Error\n");
++	if (err & (1 << 6))
++		DSSERR("\t\tFalse Control Error\n");
++	if (err & (1 << 7))
++		DSSERR("\t\t(reserved7)\n");
++	if (err & (1 << 8))
++		DSSERR("\t\tECC Error, single-bit (corrected)\n");
++	if (err & (1 << 9))
++		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
++	if (err & (1 << 10))
++		DSSERR("\t\tChecksum Error\n");
++	if (err & (1 << 11))
++		DSSERR("\t\tData type not recognized\n");
++	if (err & (1 << 12))
++		DSSERR("\t\tInvalid VC ID\n");
++	if (err & (1 << 13))
++		DSSERR("\t\tInvalid Transmission Length\n");
++	if (err & (1 << 14))
++		DSSERR("\t\t(reserved14)\n");
++	if (err & (1 << 15))
++		DSSERR("\t\tDSI Protocol Violation\n");
++}
++
++static u16 dsi_vc_flush_receive_data(int channel)
++{
++	/* RX_FIFO_NOT_EMPTY */
++	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++		u32 val;
++		u8 dt;
++		val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++		DSSDBG("\trawval %#08x\n", val);
++		dt = FLD_GET(val, 5, 0);
++		if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++			u16 err = FLD_GET(val, 23, 8);
++			dsi_show_rx_ack_with_err(err);
++		} else if (dt == DSI_DT_RX_SHORT_READ_1) {
++			DSSDBG("\tDCS short response, 1 byte: %#x\n",
++					FLD_GET(val, 23, 8));
++		} else if (dt == DSI_DT_RX_SHORT_READ_2) {
++			DSSDBG("\tDCS short response, 2 byte: %#x\n",
++					FLD_GET(val, 23, 8));
++		} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++			DSSDBG("\tDCS long response, len %d\n",
++					FLD_GET(val, 23, 8));
++			dsi_vc_flush_long_data(channel);
++		} else {
++			DSSERR("\tunknown datatype 0x%02x\n", dt);
++		}
++	}
++	return 0;
++}
++
++static int dsi_vc_send_bta(int channel)
++{
++	unsigned long tmo;
++
++	/*DSSDBG("dsi_vc_send_bta_sync %d\n", channel); */
++
++	if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {	/* RX_FIFO_NOT_EMPTY */
++		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
++		dsi_vc_flush_receive_data(channel);
++	}
++
++	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
++
++	tmo = jiffies + msecs_to_jiffies(10);
++	while (REG_GET(DSI_VC_CTRL(channel), 6, 6) == 1) {
++		if (time_after(jiffies, tmo)) {
++			DSSERR("Failed to send BTA\n");
++			return -EIO;
++		}
++	}
++
++	return 0;
++}
++
++static int dsi_vc_send_bta_sync(int channel)
++{
++	int r = 0;
++
++	init_completion(&dsi.bta_completion);
++
++	dsi_vc_enable_bta_irq(channel);
++
++	r = dsi_vc_send_bta(channel);
++	if (r)
++		goto err;
++
++	if (wait_for_completion_timeout(&dsi.bta_completion,
++				msecs_to_jiffies(500)) == 0) {
++		DSSERR("Failed to receive BTA\n");
++		r = -EIO;
++		goto err;
++	}
++err:
++	dsi_vc_disable_bta_irq(channel);
++
++	return r;
++}
++
++static inline void dsi_vc_write_long_header(int channel, u8 data_type,
++		u16 len, u8 ecc)
++{
++	u32 val;
++	u8 data_id;
++
++	/*data_id = data_type | channel << 6; */
++	data_id = data_type | dsi.vc[channel].dest_per << 6;
++
++	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
++		FLD_VAL(ecc, 31, 24);
++
++	dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
++}
++
++static inline void dsi_vc_write_long_payload(int channel,
++		u8 b1, u8 b2, u8 b3, u8 b4)
++{
++	u32 val;
++
++	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
++
++/*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
++			b1, b2, b3, b4, val); */
++
++	dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
++}
++
++static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
++		u8 ecc)
++{
++	/*u32 val; */
++	int i;
++	u8 *p;
++	int r = 0;
++	u8 b1, b2, b3, b4;
++
++	if (dsi.debug_write)
++		DSSDBG("dsi_vc_send_long, %d bytes\n", len);
++
++	/* len + header */
++	if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
++		DSSERR("unable to send long packet: packet too long.\n");
++		return -EINVAL;
++	}
++
++	dsi_vc_write_long_header(channel, data_type, len, ecc);
++
++	/*dsi_vc_print_status(0); */
++
++	p = data;
++	for (i = 0; i < len >> 2; i++) {
++		if (dsi.debug_write)
++			DSSDBG("\tsending full packet %d\n", i);
++		/*dsi_vc_print_status(0); */
++
++		b1 = *p++;
++		b2 = *p++;
++		b3 = *p++;
++		b4 = *p++;
++
++		dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
++	}
++
++	i = len % 4;
++	if (i) {
++		b1 = 0; b2 = 0; b3 = 0;
++
++		if (dsi.debug_write)
++			DSSDBG("\tsending remainder bytes %d\n", i);
++
++		switch (i) {
++		case 3:
++			b1 = *p++;
++			b2 = *p++;
++			b3 = *p++;
++			break;
++		case 2:
++			b1 = *p++;
++			b2 = *p++;
++			break;
++		case 1:
++			b1 = *p++;
++			break;
++		}
++
++		dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
++	}
++
++	return r;
++}
++
++static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
++{
++	u32 r;
++	u8 data_id;
++
++	if (dsi.debug_write)
++		DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
++				channel,
++				data_type, data & 0xff, (data >> 8) & 0xff);
++
++	if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
++		DSSERR("ERROR FIFO FULL, aborting transfer\n");
++		return -EINVAL;
++	}
++
++	data_id = data_type | channel << 6;
++
++	r = (data_id << 0) | (data << 8) | (ecc << 24);
++
++	dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
++
++	return 0;
++}
++
++int dsi_vc_send_null(int channel)
++{
++	u8 nullpkg[] = {0, 0, 0, 0};
++	return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
++}
++EXPORT_SYMBOL(dsi_vc_send_null);
++
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
++{
++	int r;
++
++	BUG_ON(len == 0);
++
++	if (len == 1) {
++		r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
++				data[0], 0);
++	} else if (len == 2) {
++		r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
++				data[0] | (data[1] << 8), 0);
++	} else {
++		/* 0x39 = DCS Long Write */
++		r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
++				data, len, 0);
++	}
++
++	return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
++
++int dsi_vc_dcs_write(int channel, u8 *data, int len)
++{
++	int r;
++
++	r = dsi_vc_dcs_write_nosync(channel, data, len);
++	if (r)
++		return r;
++
++	/* Some devices need time to process the msg in low power mode.
++	   This also makes the write synchronous, and checks that
++	   the peripheral is still alive */
++	r = dsi_vc_send_bta_sync(channel);
++
++	return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write);
++
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
++{
++	u32 val;
++	u8 dt;
++	int r;
++
++	if (dsi.debug_read)
++		DSSDBG("dsi_vc_dcs_read\n");
++
++	r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
++	if (r)
++		return r;
++
++	r = dsi_vc_send_bta_sync(channel);
++	if (r)
++		return r;
++
++	if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {	/* RX_FIFO_NOT_EMPTY */
++		DSSERR("RX fifo empty when trying to read.\n");
++		return -EIO;
++	}
++
++	val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++	if (dsi.debug_read)
++		DSSDBG("\theader: %08x\n", val);
++	dt = FLD_GET(val, 5, 0);
++	if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++		u16 err = FLD_GET(val, 23, 8);
++		dsi_show_rx_ack_with_err(err);
++		return -1;
++
++	} else if (dt == DSI_DT_RX_SHORT_READ_1) {
++		u8 data = FLD_GET(val, 15, 8);
++		if (dsi.debug_read)
++			DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
++
++		if (buflen < 1)
++			return -1;
++
++		buf[0] = data;
++
++		return 1;
++	} else if (dt == DSI_DT_RX_SHORT_READ_2) {
++		u16 data = FLD_GET(val, 23, 8);
++		if (dsi.debug_read)
++			DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
++
++		if (buflen < 2)
++			return -1;
++
++		buf[0] = data & 0xff;
++		buf[1] = (data >> 8) & 0xff;
++
++		return 2;
++	} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++		int w;
++		int len = FLD_GET(val, 23, 8);
++		if (dsi.debug_read)
++			DSSDBG("\tDCS long response, len %d\n", len);
++
++		if (len > buflen)
++			return -1;
++
++		/* two byte checksum ends the packet, not included in len */
++		for (w = 0; w < len + 2;) {
++			int b;
++			val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++			if (dsi.debug_read)
++				DSSDBG("\t\t%02x %02x %02x %02x\n",
++						(val >> 0) & 0xff,
++						(val >> 8) & 0xff,
++						(val >> 16) & 0xff,
++						(val >> 24) & 0xff);
++
++			for (b = 0; b < 4; ++b) {
++				if (w < len)
++					buf[w] = (val >> (b * 8)) & 0xff;
++				/* we discard the 2 byte checksum */
++				++w;
++			}
++		}
++
++		return len;
++
++	} else {
++		DSSERR("\tunknown datatype 0x%02x\n", dt);
++		return -1;
++	}
++}
++EXPORT_SYMBOL(dsi_vc_dcs_read);
++
++
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
++{
++	return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
++			len, 0);
++}
++EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
++
++
++static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
++{
++	u32 r;
++	unsigned long fck;
++	int ticks;
++
++	/* ticks in DSI_FCK */
++
++	fck = dsi_fclk_rate();
++	ticks = (fck / 1000 / 1000) * ns / 1000;
++
++	if (ticks > 0x1fff) {
++		DSSERR("LP_TX_TO too high\n");
++		return -EINVAL;
++	}
++
++	r = dsi_read_reg(DSI_TIMING2);
++	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
++	r = FLD_MOD(r, x16, 14, 14);	/* LP_RX_TO_X16 */
++	r = FLD_MOD(r, x4, 13, 13);	/* LP_RX_TO_X4 */
++	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
++	dsi_write_reg(DSI_TIMING2, r);
++
++	DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
++			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++			(fck / 1000 / 1000),
++			ticks);
++
++	return 0;
++}
++
++static int dsi_set_ta_timeout(int ns, int x8, int x16)
++{
++	u32 r;
++	unsigned long fck;
++	int ticks;
++
++	/* ticks in DSI_FCK */
++
++	fck = dsi_fclk_rate();
++	ticks = (fck / 1000 / 1000) * ns / 1000;
++
++	if (ticks > 0x1fff) {
++		DSSERR("TA_TO too high\n");
++		return -EINVAL;
++	}
++
++	r = dsi_read_reg(DSI_TIMING1);
++	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
++	r = FLD_MOD(r, x16, 30, 30);	/* TA_TO_X16 */
++	r = FLD_MOD(r, x8, 29, 29);	/* TA_TO_X8 */
++	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
++	dsi_write_reg(DSI_TIMING1, r);
++
++	DSSDBG("TA_TO %ld ns (%#x ticks)\n",
++			(ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
++			(fck / 1000 / 1000),
++			ticks);
++
++	return 0;
++}
++
++static int dsi_set_stop_state_counter(int ns, int x4, int x16)
++{
++	u32 r;
++	unsigned long fck;
++	int ticks;
++
++	/* ticks in DSI_FCK */
++
++	fck = dsi_fclk_rate();
++	ticks = (fck / 1000 / 1000) * ns / 1000;
++
++	if (ticks > 0x1fff) {
++		DSSERR("STOP_STATE_COUNTER_IO too high\n");
++		return -EINVAL;
++	}
++
++	r = dsi_read_reg(DSI_TIMING1);
++	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
++	r = FLD_MOD(r, x16, 14, 14);	/* STOP_STATE_X16_IO */
++	r = FLD_MOD(r, x4, 13, 13);	/* STOP_STATE_X4_IO */
++	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
++	dsi_write_reg(DSI_TIMING1, r);
++
++	DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
++			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++			(fck / 1000 / 1000),
++			ticks);
++
++	return 0;
++}
++
++static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
++{
++	u32 r;
++	unsigned long fck;
++	int ticks;
++
++	/* ticks in TxByteClkHS */
++
++	fck = dsi.ddr_clk / 4;
++	ticks = (fck / 1000 / 1000) * ns / 1000;
++
++	if (ticks > 0x1fff) {
++		DSSERR("HS_TX_TO too high\n");
++		return -EINVAL;
++	}
++
++	r = dsi_read_reg(DSI_TIMING2);
++	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
++	r = FLD_MOD(r, x16, 30, 30);	/* HS_TX_TO_X16 */
++	r = FLD_MOD(r, x4, 29, 29);	/* HS_TX_TO_X8 (4 really) */
++	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
++	dsi_write_reg(DSI_TIMING2, r);
++
++	DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
++			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++			(fck / 1000 / 1000),
++			ticks);
++
++	return 0;
++}
++static int dsi_proto_config(struct omap_display *display)
++{
++	u32 r;
++	int buswidth = 0;
++
++	dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
++			DSI_FIFO_SIZE_0,
++			DSI_FIFO_SIZE_0,
++			DSI_FIFO_SIZE_0);
++
++	dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
++			DSI_FIFO_SIZE_0,
++			DSI_FIFO_SIZE_0,
++			DSI_FIFO_SIZE_0);
++
++	/* XXX what values for the timeouts? */
++	dsi_set_stop_state_counter(1000, 0, 0);
++
++	dsi_set_ta_timeout(50000, 1, 1);
++
++	/* 3000ns * 16 */
++	dsi_set_lp_rx_timeout(3000, 0, 1);
++
++	/* 10000ns * 4 */
++	dsi_set_hs_tx_timeout(10000, 1, 0);
++
++	switch (display->ctrl->pixel_size) {
++	case 16:
++		buswidth = 0;
++		break;
++	case 18:
++		buswidth = 1;
++		break;
++	case 24:
++		buswidth = 2;
++		break;
++	default:
++		BUG();
++	}
++
++	r = dsi_read_reg(DSI_CTRL);
++	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
++	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
++	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
++	/* XXX what should the ratio be */
++	r = FLD_MOD(r, 0, 4, 4);	/* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
++	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
++	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
++	r = FLD_MOD(r, 2, 13, 12);	/* LINE_BUFFER, 2 lines */
++	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
++	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
++	r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
++	r = FLD_MOD(r, 0, 25, 25);	/* DCS_CMD_CODE, 1=start, 0=continue */
++
++	dsi_write_reg(DSI_CTRL, r);
++
++	/* we configure vc0 for L4 communication, and
++	 * vc1 for dispc */
++	dsi_vc_config(0);
++	dsi_vc_config_vp(1);
++
++	/* set all vc targets to peripheral 0 */
++	dsi.vc[0].dest_per = 0;
++	dsi.vc[1].dest_per = 0;
++	dsi.vc[2].dest_per = 0;
++	dsi.vc[3].dest_per = 0;
++
++	return 0;
++}
++
++static void dsi_proto_timings(void)
++{
++	int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
++	int tclk_pre, tclk_post;
++	int ddr_clk_pre, ddr_clk_post;
++	u32 r;
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG1);
++	tlpx_half = FLD_GET(r, 22, 16);
++	tclk_trail = FLD_GET(r, 15, 8);
++	tclk_zero = FLD_GET(r, 7, 0);
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG2);
++	tclk_prepare = FLD_GET(r, 7, 0);
++
++	/* min 8*UI */
++	tclk_pre = 20;
++	/* min 60ns + 52*UI */
++	tclk_post = ns2ddr(60) + 26;
++
++	ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
++	ddr_clk_post = (tclk_post + tclk_trail) / 4;
++
++	r = dsi_read_reg(DSI_CLK_TIMING);
++	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
++	r = FLD_MOD(r, ddr_clk_post, 7, 0);
++	dsi_write_reg(DSI_CLK_TIMING, r);
++
++	DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
++			ddr_clk_pre,
++			ddr_clk_post);
++}
++
++
++#define DSI_DECL_VARS \
++	int __dsi_cb = 0; u32 __dsi_cv = 0;
++
++#define DSI_FLUSH(ch) \
++	if (__dsi_cb > 0) { \
++		/*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
++		dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
++		__dsi_cb = __dsi_cv = 0; \
++	}
++
++#define DSI_PUSH(ch, data) \
++	do { \
++		__dsi_cv |= (data) << (__dsi_cb * 8); \
++		/*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
++		if (++__dsi_cb > 3) \
++			DSI_FLUSH(ch); \
++	} while (0)
++
++static int dsi_update_screen_l4(struct omap_display *display,
++			int x, int y, int w, int h)
++{
++	/* Note: supports only 24bit colors in 32bit container */
++	int first = 1;
++	int fifo_stalls = 0;
++	int max_dsi_packet_size;
++	int max_data_per_packet;
++	int max_pixels_per_packet;
++	int pixels_left;
++	int bytespp = 3;
++	int scr_width;
++	u32 __iomem *data;
++	int start_offset;
++	int horiz_inc;
++	int current_x;
++	struct omap_overlay *ovl;
++
++	debug_irq = 0;
++
++	DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
++			x, y, w, h);
++
++	ovl = display->manager->overlays[0];
++
++	if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
++		return -EINVAL;
++
++	if (display->ctrl->pixel_size != 24)
++		return -EINVAL;
++
++	scr_width = ovl->info.screen_width;
++	data = ovl->info.vaddr;
++
++	start_offset = scr_width * y + x;
++	horiz_inc = scr_width - w;
++	current_x = x;
++
++	/* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
++	 * in fifo */
++
++	/* When using CPU, max long packet size is TX buffer size */
++	max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
++
++	/* we seem to get better perf if we divide the tx fifo to half,
++	   and while the other half is being sent, we fill the other half
++	   max_dsi_packet_size /= 2; */
++
++	max_data_per_packet = max_dsi_packet_size - 4 - 1;
++
++	max_pixels_per_packet = max_data_per_packet / bytespp;
++
++	DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
++
++	display->ctrl->setup_update(display, x, y, w, h);
++
++	pixels_left = w * h;
++
++	DSSDBG("total pixels %d\n", pixels_left);
++
++	data += start_offset;
++
++#ifdef DEBUG
++	dsi.update_region.x = x;
++	dsi.update_region.y = y;
++	dsi.update_region.w = w;
++	dsi.update_region.h = h;
++	dsi.update_region.bytespp = bytespp;
++#endif
++
++	perf_mark_start();
++
++	while (pixels_left > 0) {
++		/* 0x2c = write_memory_start */
++		/* 0x3c = write_memory_continue */
++		u8 dcs_cmd = first ? 0x2c : 0x3c;
++		int pixels;
++		DSI_DECL_VARS;
++		first = 0;
++
++#if 1
++		/* using fifo not empty */
++		/* TX_FIFO_NOT_EMPTY */
++		while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
++			udelay(1);
++			fifo_stalls++;
++			if (fifo_stalls > 0xfffff) {
++				DSSERR("fifo stalls overflow, pixels left %d\n",
++						pixels_left);
++				dsi_if_enable(0);
++				return -EIO;
++			}
++		}
++#elif 1
++		/* using fifo emptiness */
++		while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
++				max_dsi_packet_size) {
++			fifo_stalls++;
++			if (fifo_stalls > 0xfffff) {
++				DSSERR("fifo stalls overflow, pixels left %d\n",
++					       pixels_left);
++				dsi_if_enable(0);
++				return -EIO;
++			}
++		}
++#else
++		while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
++			fifo_stalls++;
++			if (fifo_stalls > 0xfffff) {
++				DSSERR("fifo stalls overflow, pixels left %d\n",
++					       pixels_left);
++				dsi_if_enable(0);
++				return -EIO;
++			}
++		}
++#endif
++		pixels = min(max_pixels_per_packet, pixels_left);
++
++		pixels_left -= pixels;
++
++		dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
++				1 + pixels * bytespp, 0);
++
++		DSI_PUSH(0, dcs_cmd);
++
++		while (pixels-- > 0) {
++			u32 pix = __raw_readl(data++);
++
++			DSI_PUSH(0, (pix >> 16) & 0xff);
++			DSI_PUSH(0, (pix >> 8) & 0xff);
++			DSI_PUSH(0, (pix >> 0) & 0xff);
++
++			current_x++;
++			if (current_x == x+w) {
++				current_x = x;
++				data += horiz_inc;
++			}
++		}
++
++		DSI_FLUSH(0);
++	}
++
++	perf_show("L4");
++
++	return 0;
++}
++
++#if 0
++static void dsi_clear_screen_l4(struct omap_display *display,
++			int x, int y, int w, int h)
++{
++	int first = 1;
++	int fifo_stalls = 0;
++	int max_dsi_packet_size;
++	int max_data_per_packet;
++	int max_pixels_per_packet;
++	int pixels_left;
++	int bytespp = 3;
++	int pixnum;
++
++	debug_irq = 0;
++
++	DSSDBG("dsi_clear_screen_l4 (%d,%d %dx%d)\n",
++			x, y, w, h);
++
++	if (display->ctrl->bpp != 24)
++		return -EINVAL;
++
++	/* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp)
++	 * bytes in fifo */
++
++	/* When using CPU, max long packet size is TX buffer size */
++	max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
++
++	max_data_per_packet = max_dsi_packet_size - 4 - 1;
++
++	max_pixels_per_packet = max_data_per_packet / bytespp;
++
++	enable_clocks(1);
++
++	display->ctrl->setup_update(display, x, y, w, h);
++
++	pixels_left = w * h;
++
++	dsi.update_region.x = x;
++	dsi.update_region.y = y;
++	dsi.update_region.w = w;
++	dsi.update_region.h = h;
++	dsi.update_region.bytespp = bytespp;
++
++	start_measuring();
++
++	pixnum = 0;
++
++	while (pixels_left > 0) {
++		/* 0x2c = write_memory_start */
++		/* 0x3c = write_memory_continue */
++		u8 dcs_cmd = first ? 0x2c : 0x3c;
++		int pixels;
++		DSI_DECL_VARS;
++		first = 0;
++
++		/* TX_FIFO_NOT_EMPTY */
++		while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
++			fifo_stalls++;
++			if (fifo_stalls > 0xfffff) {
++				DSSERR("fifo stalls overflow\n");
++				dsi_if_enable(0);
++				enable_clocks(0);
++				return;
++			}
++		}
++
++		pixels = min(max_pixels_per_packet, pixels_left);
++
++		pixels_left -= pixels;
++
++		dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
++				1 + pixels * bytespp, 0);
++
++		DSI_PUSH(0, dcs_cmd);
++
++		while (pixels-- > 0) {
++			u32 pix;
++
++			pix = 0x000000;
++
++			DSI_PUSH(0, (pix >> 16) & 0xff);
++			DSI_PUSH(0, (pix >> 8) & 0xff);
++			DSI_PUSH(0, (pix >> 0) & 0xff);
++		}
++
++		DSI_FLUSH(0);
++	}
++
++	enable_clocks(0);
++
++	end_measuring("L4 CLEAR");
++}
++#endif
++
++static void dsi_setup_update_dispc(struct omap_display *display,
++			u16 x, u16 y, u16 w, u16 h)
++{
++	DSSDBG("dsi_setup_update_dispc(%d,%d %dx%d)\n",
++			x, y, w, h);
++
++#ifdef DEBUG
++	dsi.update_region.x = x;
++	dsi.update_region.y = y;
++	dsi.update_region.w = w;
++	dsi.update_region.h = h;
++	dsi.update_region.bytespp = 3; // XXX
++#endif
++
++	dispc_setup_partial_planes(display, &x, &y, &w, &h);
++
++	dispc_set_lcd_size(w, h);
++}
++
++static void dsi_setup_autoupdate_dispc(struct omap_display *display)
++{
++	u16 w, h;
++
++	display->get_resolution(display, &w, &h);
++
++#ifdef DEBUG
++	dsi.update_region.x = 0;
++	dsi.update_region.y = 0;
++	dsi.update_region.w = w;
++	dsi.update_region.h = h;
++	dsi.update_region.bytespp = 3; // XXX
++#endif
++
++	/* the overlay settings may not have been applied, if we were in manual
++	 * mode earlier, so do it here */
++	display->manager->apply(display->manager);
++
++	dispc_set_lcd_size(w, h);
++
++	dsi.autoupdate_setup = 0;
++}
++
++static void dsi_update_screen_dispc(struct omap_display *display,
++		u16 x, u16 y, u16 w, u16 h)
++{
++	int bytespp = 3;
++	int total_len;
++	int line_packet_len;
++	u32 l;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
++		DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
++				x, y, w, h);
++
++	/* TODO: one packet could be longer, I think? Max is the line buffer */
++	line_packet_len = w * bytespp + 1;	/* 1 byte for DCS cmd */
++	total_len = line_packet_len * h;
++
++	display->ctrl->setup_update(display, x, y, w, h);
++
++	if (0)
++		dsi_vc_print_status(1);
++
++	perf_mark_start();
++
++	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
++	dsi_write_reg(DSI_VC_TE(1), l);
++
++	dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
++
++	if (dsi.use_te)
++		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
++	else
++		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
++	dsi_write_reg(DSI_VC_TE(1), l);
++
++	dispc_enable_lcd_out(1);
++
++	if (dsi.use_te)
++		dsi_vc_send_bta(1);
++}
++
++static void framedone_callback(void *data, u32 mask)
++{
++	if (dsi.framedone_scheduled) {
++		DSSERR("Framedone already scheduled. Bogus FRAMEDONE IRQ?\n");
++		return;
++	}
++
++	dsi.framedone_scheduled = 1;
++
++	/* We get FRAMEDONE when DISPC has finished sending pixels and turns
++	 * itself off. However, DSI still has the pixels in its buffers, and
++	 * is sending the data. Thus we have to wait until we can do a new
++	 * transfer or turn the clocks off. We do that in a separate work
++	 * func. */
++	queue_work(dsi.workqueue, &dsi.framedone_work);
++}
++
++static void framedone_worker(struct work_struct *work)
++{
++	u32 l;
++	unsigned long tmo;
++	int i = 0;
++
++	l = REG_GET(DSI_VC_TE(1), 23, 0); /* TE_SIZE */
++
++	/* There shouldn't be much stuff in DSI buffers, if any, so we'll
++	 * just busyloop */
++	if (l > 0) {
++		tmo = jiffies + msecs_to_jiffies(50);
++		while (REG_GET(DSI_VC_TE(1), 23, 0) > 0) { /* TE_SIZE */
++			i++;
++			if (time_after(jiffies, tmo)) {
++				DSSERR("timeout waiting TE_SIZE to zero\n");
++				break;
++			}
++			cpu_relax();
++		}
++	}
++
++	if (REG_GET(DSI_VC_TE(1), 30, 30))
++		DSSERR("TE_EN not zero\n");
++
++	if (REG_GET(DSI_VC_TE(1), 31, 31))
++		DSSERR("TE_START not zero\n");
++
++	perf_show("DISPC");
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
++		DSSDBG("FRAMEDONE\n");
++
++#if 0
++	if (l)
++		DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
++#else
++	if (l > 1024*3)
++		DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
++#endif
++
++#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
++	dispc_fake_vsync_irq();
++#endif
++	dsi.framedone_scheduled = 0;
++
++	/* XXX check that fifo is not full. otherwise we would sleep and never
++	 * get to process_cmd_fifo below */
++	/* We check for target_update_mode, not update_mode. No reason to push
++	 * new updates if we're turning auto update off */
++	if (dsi.target_update_mode == OMAP_DSS_UPDATE_AUTO)
++		dsi_push_autoupdate(dsi.vc[1].display);
++
++	atomic_set(&dsi.cmd_pending, 0);
++	dsi_process_cmd_fifo(NULL);
++}
++
++static void dsi_start_auto_update(struct omap_display *display)
++{
++	DSSDBG("starting auto update\n");
++
++	dsi.autoupdate_setup = 1;
++
++	dsi_push_autoupdate(display);
++}
++
++
++
++
++
++
++
++
++
++
++
++
++
++/* FIFO functions */
++
++static void dsi_signal_fifo_waiters(void)
++{
++	if (atomic_read(&dsi.cmd_fifo_full) > 0) {
++		DSSDBG("SIGNALING: Fifo not full for waiter!\n");
++		complete(&dsi.cmd_done);
++		atomic_dec(&dsi.cmd_fifo_full);
++	}
++}
++
++/* returns 1 for async op, and 0 for sync op */
++static int dsi_do_update(struct omap_display *display,
++		struct dsi_cmd_update *upd)
++{
++	int r;
++	u16 x = upd->x, y = upd->y, w = upd->w, h = upd->h;
++	u16 dw, dh;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
++		return 0;
++
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return 0;
++
++	display->get_resolution(display, &dw, &dh);
++	if  (x > dw || y > dh)
++		return 0;
++
++	if (x + w > dw)
++		w = dw - x;
++
++	if (y + h > dh)
++		h = dh - y;
++
++	DSSDBGF("%d,%d %dx%d", x, y, w, h);
++
++	perf_mark_setup();
++
++	if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++		dsi_setup_update_dispc(display, x, y, w, h);
++		dsi_update_screen_dispc(display, x, y, w, h);
++		return 1;
++	} else {
++		r = dsi_update_screen_l4(display, x, y, w, h);
++		if (r)
++			DSSERR("L4 update failed\n");
++		return 0;
++	}
++}
++
++/* returns 1 for async op, and 0 for sync op */
++static int dsi_do_autoupdate(struct omap_display *display)
++{
++	int r;
++	u16 w, h;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
++		return 0;
++
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return 0;
++
++	display->get_resolution(display, &w, &h);
++
++	perf_mark_setup();
++
++	if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++		if (dsi.autoupdate_setup)
++			dsi_setup_autoupdate_dispc(display);
++		dsi_update_screen_dispc(display, 0, 0, w, h);
++		return 1;
++	} else {
++		r = dsi_update_screen_l4(display, 0, 0, w, h);
++		if (r)
++			DSSERR("L4 update failed\n");
++		return 0;
++	}
++}
++
++static void dsi_do_cmd_mem_read(struct omap_display *display,
++		struct dsi_cmd_mem_read *mem_read)
++{
++	int r;
++	r = display->ctrl->memory_read(display,
++			mem_read->buf,
++			mem_read->size,
++			mem_read->x,
++			mem_read->y,
++			mem_read->w,
++			mem_read->h);
++
++	*mem_read->ret_size = (size_t)r;
++	complete(mem_read->completion);
++}
++
++static void dsi_do_cmd_test(struct omap_display *display,
++		struct dsi_cmd_test *test)
++{
++	int r = 0;
++
++	DSSDBGF("");
++
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return;
++
++	/* run test first in low speed mode */
++	dsi_vc_enable_hs(0, 0);
++
++	if (display->ctrl->run_test) {
++		r = display->ctrl->run_test(display, test->test_num);
++		if (r)
++			goto end;
++	}
++
++	if (display->panel->run_test) {
++		r = display->panel->run_test(display, test->test_num);
++		if (r)
++			goto end;
++	}
++
++	/* then in high speed */
++	dsi_vc_enable_hs(0, 1);
++
++	if (display->ctrl->run_test) {
++		r = display->ctrl->run_test(display, test->test_num);
++		if (r)
++			goto end;
++	}
++
++	if (display->panel->run_test)
++		r = display->panel->run_test(display, test->test_num);
++
++end:
++	dsi_vc_enable_hs(0, 1);
++
++	*test->result = r;
++	complete(test->completion);
++
++	DSSDBG("test end\n");
++}
++
++static void dsi_do_cmd_set_te(struct omap_display *display, bool enable)
++{
++	dsi.use_te = enable;
++
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return;
++
++	display->ctrl->enable_te(display, enable);
++
++	if (enable) {
++		/* disable LP_RX_TO, so that we can receive TE.
++		 * Time to wait for TE is longer than the timer allows */
++		REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
++	} else {
++		REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
++	}
++}
++
++static void dsi_do_cmd_set_update_mode(struct omap_display *display,
++	       enum omap_dss_update_mode mode)
++{
++	dsi.update_mode = mode;
++
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return;
++
++	if (mode == OMAP_DSS_UPDATE_AUTO)
++		dsi_start_auto_update(display);
++}
++
++static void dsi_process_cmd_fifo(struct work_struct *work)
++{
++	int len;
++	struct dsi_cmd_item p;
++	unsigned long flags;
++	struct omap_display *display;
++	int exit = 0;
++
++	if (dsi.debug_process)
++		DSSDBGF("");
++
++	if (atomic_cmpxchg(&dsi.cmd_pending, 0, 1) == 1) {
++		if (dsi.debug_process)
++			DSSDBG("cmd pending, skip process\n");
++		return;
++	}
++
++	while (!exit) {
++		spin_lock_irqsave(dsi.cmd_fifo->lock, flags);
++
++		len = __kfifo_get(dsi.cmd_fifo, (unsigned char *)&p,
++				  sizeof(p));
++		if (len == 0) {
++			if (dsi.debug_process)
++				DSSDBG("nothing more in fifo, atomic clear\n");
++			atomic_set(&dsi.cmd_pending, 0);
++			spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
++			break;
++		}
++
++		spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
++
++		BUG_ON(len != sizeof(p));
++
++		display = p.display;
++
++		if (dsi.debug_process)
++			DSSDBG("processing cmd %d\n", p.cmd);
++
++		switch (p.cmd) {
++		case DSI_CMD_UPDATE:
++			if (dsi_do_update(display, &p.u.r)) {
++				if (dsi.debug_process)
++					DSSDBG("async update\n");
++				exit = 1;
++			} else {
++				if (dsi.debug_process)
++					DSSDBG("sync update\n");
++			}
++			break;
++
++		case DSI_CMD_AUTOUPDATE:
++			if (dsi_do_autoupdate(display)) {
++				if (dsi.debug_process)
++					DSSDBG("async autoupdate\n");
++				exit = 1;
++			} else {
++				if (dsi.debug_process)
++					DSSDBG("sync autoupdate\n");
++			}
++			break;
++
++		case DSI_CMD_SYNC:
++			if (dsi.debug_process)
++				DSSDBG("Signaling SYNC done!\n");
++			complete(p.u.sync);
++			break;
++
++		case DSI_CMD_MEM_READ:
++			dsi_do_cmd_mem_read(display, &p.u.mem_read);
++			break;
++
++		case DSI_CMD_TEST:
++			dsi_do_cmd_test(display, &p.u.test);
++			break;
++
++		case DSI_CMD_SET_TE:
++			dsi_do_cmd_set_te(display, p.u.te);
++			break;
++
++		case DSI_CMD_SET_UPDATE_MODE:
++			dsi_do_cmd_set_update_mode(display, p.u.update_mode);
++			break;
++
++		case DSI_CMD_SET_ROTATE:
++			display->ctrl->set_rotate(display, p.u.rotate);
++			if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++				dsi.autoupdate_setup = 1;
++			break;
++
++		case DSI_CMD_SET_MIRROR:
++			display->ctrl->set_mirror(display, p.u.mirror);
++			break;
++
++		default:
++			BUG();
++		}
++	}
++
++	if (dsi.debug_process)
++		DSSDBG("exit dsi_process_cmd_fifo\n");
++
++	dsi_signal_fifo_waiters();
++}
++
++static void dsi_push_cmd(struct dsi_cmd_item *p)
++{
++	int ret;
++
++	if (dsi.debug_process)
++		DSSDBGF("");
++
++	while (1) {
++		unsigned long flags;
++		unsigned avail, used;
++
++		spin_lock_irqsave(dsi.cmd_fifo->lock, flags);
++		used = __kfifo_len(dsi.cmd_fifo) / sizeof(struct dsi_cmd_item);
++		avail = DSI_CMD_FIFO_LEN - used;
++
++		if (dsi.debug_process)
++			DSSDBG("%u/%u items left in fifo\n", avail, used);
++
++		if (avail == 0) {
++			if (dsi.debug_process)
++				DSSDBG("cmd fifo full, waiting...\n");
++			spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
++			atomic_inc(&dsi.cmd_fifo_full);
++			wait_for_completion(&dsi.cmd_done);
++			if (dsi.debug_process)
++				DSSDBG("cmd fifo not full, woke up\n");
++			continue;
++		}
++
++		ret = __kfifo_put(dsi.cmd_fifo, (unsigned char *)p,
++				sizeof(*p));
++
++		spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
++
++		BUG_ON(ret != sizeof(*p));
++
++		break;
++	}
++
++	queue_work(dsi.workqueue, &dsi.process_work);
++}
++
++static void dsi_push_update(struct omap_display *display,
++		int x, int y, int w, int h)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_UPDATE;
++
++	p.u.r.x = x;
++	p.u.r.y = y;
++	p.u.r.w = w;
++	p.u.r.h = h;
++
++	DSSDBG("pushing UPDATE %d,%d %dx%d\n", x, y, w, h);
++
++	dsi_push_cmd(&p);
++}
++
++static void dsi_push_autoupdate(struct omap_display *display)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_AUTOUPDATE;
++
++	dsi_push_cmd(&p);
++}
++
++static void dsi_push_sync(struct omap_display *display,
++		struct completion *sync_comp)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_SYNC;
++	p.u.sync = sync_comp;
++
++	DSSDBG("pushing SYNC\n");
++
++	dsi_push_cmd(&p);
++}
++
++static void dsi_push_mem_read(struct omap_display *display,
++		struct dsi_cmd_mem_read *mem_read)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_MEM_READ;
++	p.u.mem_read = *mem_read;
++
++	DSSDBG("pushing MEM_READ\n");
++
++	dsi_push_cmd(&p);
++}
++
++static void dsi_push_test(struct omap_display *display, int test_num,
++		int *result, struct completion *completion)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_TEST;
++	p.u.test.test_num = test_num;
++	p.u.test.result = result;
++	p.u.test.completion = completion;
++
++	DSSDBG("pushing TEST\n");
++
++	dsi_push_cmd(&p);
++}
++
++static void dsi_push_set_te(struct omap_display *display, bool enable)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_SET_TE;
++	p.u.te = enable;
++
++	DSSDBG("pushing SET_TE\n");
++
++	dsi_push_cmd(&p);
++}
++
++static void dsi_push_set_update_mode(struct omap_display *display,
++		enum omap_dss_update_mode mode)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_SET_UPDATE_MODE;
++	p.u.update_mode = mode;
++
++	DSSDBG("pushing SET_UPDATE_MODE\n");
++
++	dsi_push_cmd(&p);
++}
++
++static void dsi_push_set_rotate(struct omap_display *display, int rotate)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_SET_ROTATE;
++	p.u.rotate = rotate;
++
++	DSSDBG("pushing SET_ROTATE\n");
++
++	dsi_push_cmd(&p);
++}
++
++static void dsi_push_set_mirror(struct omap_display *display, int mirror)
++{
++	struct dsi_cmd_item p;
++
++	p.display = display;
++	p.cmd = DSI_CMD_SET_MIRROR;
++	p.u.mirror = mirror;
++
++	DSSDBG("pushing SET_MIRROR\n");
++
++	dsi_push_cmd(&p);
++}
++
++static int dsi_wait_sync(struct omap_display *display)
++{
++	long wait = msecs_to_jiffies(60000);
++	struct completion compl;
++
++	DSSDBGF("");
++
++	init_completion(&compl);
++	dsi_push_sync(display, &compl);
++
++	DSSDBG("Waiting for SYNC to happen...\n");
++	wait = wait_for_completion_timeout(&compl, wait);
++	DSSDBG("Released from SYNC\n");
++
++	if (wait == 0) {
++		DSSERR("timeout waiting sync\n");
++		return -ETIME;
++	}
++
++	return 0;
++}
++
++
++
++
++
++
++
++
++
++
++
++
++/* Display funcs */
++
++static int dsi_display_init_dispc(struct omap_display *display)
++{
++	int r;
++
++	r = omap_dispc_register_isr(framedone_callback, NULL,
++			DISPC_IRQ_FRAMEDONE);
++	if (r) {
++		DSSERR("can't get FRAMEDONE irq\n");
++		return r;
++	}
++
++	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++
++	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
++	dispc_enable_fifohandcheck(1);
++
++	dispc_set_tft_data_lines(display->ctrl->pixel_size);
++
++	{
++		struct omap_video_timings timings = {
++			.hsw		= 1,
++			.hfp		= 1,
++			.hbp		= 1,
++			.vsw		= 1,
++			.vfp		= 0,
++			.vbp		= 0,
++		};
++
++		dispc_set_lcd_timings(&timings);
++	}
++
++	return 0;
++}
++
++static void dsi_display_uninit_dispc(struct omap_display *display)
++{
++	omap_dispc_unregister_isr(framedone_callback, NULL,
++			DISPC_IRQ_FRAMEDONE);
++}
++
++static int dsi_display_init_dsi(struct omap_display *display)
++{
++	struct dsi_clock_info cinfo;
++	int r;
++
++	_dsi_print_reset_status();
++
++	r = dsi_pll_init(1, 0);
++	if (r)
++		goto err0;
++
++	r = dsi_pll_calc_ddrfreq(display->hw_config.u.dsi.ddr_clk_hz, &cinfo);
++	if (r)
++		goto err1;
++
++	r = dsi_pll_program(&cinfo);
++	if (r)
++		goto err1;
++
++	DSSDBG("PLL OK\n");
++
++	r = dsi_complexio_init(display);
++	if (r)
++		goto err1;
++
++	_dsi_print_reset_status();
++
++	dsi_proto_timings();
++	dsi_set_lp_clk_divisor();
++
++	if (1)
++		_dsi_print_reset_status();
++
++	r = dsi_proto_config(display);
++	if (r)
++		goto err2;
++
++	/* enable interface */
++	dsi_vc_enable(0, 1);
++	dsi_vc_enable(1, 1);
++	dsi_if_enable(1);
++	dsi_force_tx_stop_mode_io();
++
++	if (display->ctrl && display->ctrl->enable) {
++		r = display->ctrl->enable(display);
++		if (r)
++			goto err3;
++	}
++
++	if (display->panel && display->panel->enable) {
++		r = display->panel->enable(display);
++		if (r)
++			goto err4;
++	}
++
++	/* enable high-speed after initial config */
++	dsi_vc_enable_hs(0, 1);
++
++	return 0;
++err4:
++	if (display->ctrl && display->ctrl->disable)
++		display->ctrl->disable(display);
++err3:
++	dsi_if_enable(0);
++err2:
++	dsi_complexio_uninit();
++err1:
++	dsi_pll_uninit();
++err0:
++	return r;
++}
++
++static void dsi_display_uninit_dsi(struct omap_display *display)
++{
++	if (display->panel && display->panel->disable)
++		display->panel->disable(display);
++	if (display->ctrl && display->ctrl->disable)
++		display->ctrl->disable(display);
++
++	dsi_complexio_uninit();
++	dsi_pll_uninit();
++}
++
++static int dsi_core_init(void)
++{
++	/* Autoidle */
++	REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
++
++	/* ENWAKEUP */
++	REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
++
++	/* SIDLEMODE smart-idle */
++	REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
++
++	_dsi_initialize_irq();
++
++	return 0;
++}
++
++static int dsi_display_enable(struct omap_display *display)
++{
++	int r = 0;
++
++	DSSDBG("dsi_display_enable\n");
++
++	mutex_lock(&dsi.lock);
++
++	if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++		DSSERR("display already enabled\n");
++		r = -EINVAL;
++		goto err0;
++	}
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	r = _dsi_reset();
++	if (r)
++		return r;
++
++	dsi_core_init();
++
++	r = dsi_display_init_dispc(display);
++	if (r)
++		goto err1;
++
++	r = dsi_display_init_dsi(display);
++	if (r)
++		goto err2;
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	if (dsi.use_te)
++		dsi_push_set_te(display, 1);
++
++	dsi_push_set_update_mode(display, dsi.user_update_mode);
++	dsi.target_update_mode = dsi.user_update_mode;
++
++	mutex_unlock(&dsi.lock);
++
++	return dsi_wait_sync(display);
++
++err2:
++	dsi_display_uninit_dispc(display);
++err1:
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++err0:
++	mutex_unlock(&dsi.lock);
++	DSSDBG("dsi_display_enable FAILED\n");
++	return r;
++}
++
++static void dsi_display_disable(struct omap_display *display)
++{
++	DSSDBG("dsi_display_disable\n");
++
++	mutex_lock(&dsi.lock);
++
++	if (display->state == OMAP_DSS_DISPLAY_DISABLED ||
++			display->state == OMAP_DSS_DISPLAY_SUSPENDED)
++		goto end;
++
++	if (dsi.target_update_mode != OMAP_DSS_UPDATE_DISABLED) {
++		dsi_push_set_update_mode(display, OMAP_DSS_UPDATE_DISABLED);
++		dsi.target_update_mode = OMAP_DSS_UPDATE_DISABLED;
++	}
++
++	dsi_wait_sync(display);
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++
++	dsi_display_uninit_dispc(display);
++
++	dsi_display_uninit_dsi(display);
++
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++end:
++	mutex_unlock(&dsi.lock);
++}
++
++static int dsi_display_suspend(struct omap_display *display)
++{
++	DSSDBG("dsi_display_suspend\n");
++
++	dsi_display_disable(display);
++
++	display->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++	return 0;
++}
++
++static int dsi_display_resume(struct omap_display *display)
++{
++	DSSDBG("dsi_display_resume\n");
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++	return dsi_display_enable(display);
++}
++
++static int dsi_display_update(struct omap_display *display,
++			u16 x, u16 y, u16 w, u16 h)
++{
++	DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
++
++	if (w == 0 || h == 0)
++		return 0;
++
++	mutex_lock(&dsi.lock);
++
++	if (dsi.target_update_mode == OMAP_DSS_UPDATE_MANUAL)
++		dsi_push_update(display, x, y, w, h);
++	/* XXX else return error? */
++
++	mutex_unlock(&dsi.lock);
++
++	return 0;
++}
++
++static int dsi_display_sync(struct omap_display *display)
++{
++	DSSDBGF("");
++	return dsi_wait_sync(display);
++}
++
++static int dsi_display_set_update_mode(struct omap_display *display,
++		enum omap_dss_update_mode mode)
++{
++	DSSDBGF("%d", mode);
++
++	mutex_lock(&dsi.lock);
++
++	if (dsi.target_update_mode != mode) {
++		dsi_push_set_update_mode(display, mode);
++
++		dsi.target_update_mode = mode;
++		dsi.user_update_mode = mode;
++	}
++
++	mutex_unlock(&dsi.lock);
++
++	return dsi_wait_sync(display);
++}
++
++static enum omap_dss_update_mode dsi_display_get_update_mode(
++		struct omap_display *display)
++{
++	return dsi.update_mode;
++}
++
++static int dsi_display_enable_te(struct omap_display *display, bool enable)
++{
++	DSSDBGF("%d", enable);
++
++	if (!display->ctrl->enable_te)
++		return -ENOENT;
++
++	dsi_push_set_te(display, enable);
++
++	return dsi_wait_sync(display);
++}
++
++static int dsi_display_get_te(struct omap_display *display)
++{
++	return dsi.use_te;
++}
++
++
++
++static int dsi_display_set_rotate(struct omap_display *display, u8 rotate)
++{
++	DSSDBGF("%d", rotate);
++
++	if (!display->ctrl->set_rotate || !display->ctrl->get_rotate)
++		return -EINVAL;
++
++	dsi_push_set_rotate(display, rotate);
++
++	return dsi_wait_sync(display);
++}
++
++static u8 dsi_display_get_rotate(struct omap_display *display)
++{
++	if (!display->ctrl->set_rotate || !display->ctrl->get_rotate)
++		return 0;
++
++	return display->ctrl->get_rotate(display);
++}
++
++static int dsi_display_set_mirror(struct omap_display *display, bool mirror)
++{
++	DSSDBGF("%d", mirror);
++
++	if (!display->ctrl->set_mirror || !display->ctrl->get_mirror)
++		return -EINVAL;
++
++	dsi_push_set_mirror(display, mirror);
++
++	return dsi_wait_sync(display);
++}
++
++static bool dsi_display_get_mirror(struct omap_display *display)
++{
++	if (!display->ctrl->set_mirror || !display->ctrl->get_mirror)
++		return 0;
++
++	return display->ctrl->get_mirror(display);
++}
++
++static int dsi_display_run_test(struct omap_display *display, int test_num)
++{
++	long wait = msecs_to_jiffies(60000);
++	struct completion compl;
++	int result;
++
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return -EIO;
++
++	DSSDBGF("%d", test_num);
++
++	init_completion(&compl);
++
++	dsi_push_test(display, test_num, &result, &compl);
++
++	DSSDBG("Waiting for SYNC to happen...\n");
++	wait = wait_for_completion_timeout(&compl, wait);
++	DSSDBG("Released from SYNC\n");
++
++	if (wait == 0) {
++		DSSERR("timeout waiting test sync\n");
++		return -ETIME;
++	}
++
++	return result;
++}
++
++static int dsi_display_memory_read(struct omap_display *display,
++		void *buf, size_t size,
++		u16 x, u16 y, u16 w, u16 h)
++{
++	long wait = msecs_to_jiffies(60000);
++	struct completion compl;
++	struct dsi_cmd_mem_read mem_read;
++	size_t ret_size;
++
++	DSSDBGF("");
++
++	if (!display->ctrl->memory_read)
++		return -EINVAL;
++
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return -EIO;
++
++	init_completion(&compl);
++
++	mem_read.x = x;
++	mem_read.y = y;
++	mem_read.w = w;
++	mem_read.h = h;
++	mem_read.buf = buf;
++	mem_read.size = size;
++	mem_read.ret_size = &ret_size;
++	mem_read.completion = &compl;
++
++	dsi_push_mem_read(display, &mem_read);
++
++	DSSDBG("Waiting for SYNC to happen...\n");
++	wait = wait_for_completion_timeout(&compl, wait);
++	DSSDBG("Released from SYNC\n");
++
++	if (wait == 0) {
++		DSSERR("timeout waiting mem read sync\n");
++		return -ETIME;
++	}
++
++	return ret_size;
++}
++
++static void dsi_configure_overlay(struct omap_overlay *ovl)
++{
++	unsigned low, high, size;
++	enum omap_burst_size burst;
++	enum omap_plane plane = ovl->id;
++
++	burst = OMAP_DSS_BURST_16x32;
++	size = 16 * 32 / 8;
++
++	dispc_set_burst_size(plane, burst);
++
++	high = dispc_get_plane_fifo_size(plane) - size;
++	low = 0;
++	dispc_setup_plane_fifo(plane, low, high);
++}
++
++void dsi_init_display(struct omap_display *display)
++{
++	DSSDBG("DSI init\n");
++
++	display->enable = dsi_display_enable;
++	display->disable = dsi_display_disable;
++	display->suspend = dsi_display_suspend;
++	display->resume = dsi_display_resume;
++	display->update = dsi_display_update;
++	display->sync = dsi_display_sync;
++	display->set_update_mode = dsi_display_set_update_mode;
++	display->get_update_mode = dsi_display_get_update_mode;
++	display->enable_te = dsi_display_enable_te;
++	display->get_te = dsi_display_get_te;
++
++	display->get_rotate = dsi_display_get_rotate;
++	display->set_rotate = dsi_display_set_rotate;
++
++	display->get_mirror = dsi_display_get_mirror;
++	display->set_mirror = dsi_display_set_mirror;
++
++	display->run_test = dsi_display_run_test;
++	display->memory_read = dsi_display_memory_read;
++
++	display->configure_overlay = dsi_configure_overlay;
++
++	display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++
++	dsi.vc[0].display = display;
++	dsi.vc[1].display = display;
++}
++
++int dsi_init(void)
++{
++	u32 rev;
++
++	spin_lock_init(&dsi.cmd_lock);
++	dsi.cmd_fifo = kfifo_alloc(
++			DSI_CMD_FIFO_LEN * sizeof(struct dsi_cmd_item),
++			GFP_KERNEL,
++			&dsi.cmd_lock);
++
++	init_completion(&dsi.cmd_done);
++	atomic_set(&dsi.cmd_fifo_full, 0);
++	atomic_set(&dsi.cmd_pending, 0);
++
++	init_completion(&dsi.bta_completion);
++
++	dsi.workqueue = create_singlethread_workqueue("dsi");
++	INIT_WORK(&dsi.framedone_work, framedone_worker);
++	INIT_WORK(&dsi.process_work, dsi_process_cmd_fifo);
++
++	mutex_init(&dsi.lock);
++
++	dsi.target_update_mode = OMAP_DSS_UPDATE_DISABLED;
++	dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
++
++	dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
++	if (!dsi.base) {
++		DSSERR("can't ioremap DSI\n");
++		return -ENOMEM;
++	}
++
++	enable_clocks(1);
++
++	rev = dsi_read_reg(DSI_REVISION);
++	printk(KERN_INFO "OMAP DSI rev %d.%d\n",
++	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++	enable_clocks(0);
++
++	return 0;
++}
++
++void dsi_exit(void)
++{
++	flush_workqueue(dsi.workqueue);
++	destroy_workqueue(dsi.workqueue);
++
++	iounmap(dsi.base);
++
++	kfifo_free(dsi.cmd_fifo);
++
++	DSSDBG("omap_dsi_exit\n");
++}
++
+diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
+new file mode 100644
+index 0000000..adc1f34
+--- /dev/null
++++ b/drivers/video/omap2/dss/dss.c
+@@ -0,0 +1,345 @@
++/*
++ * linux/drivers/video/omap2/dss/dss.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DSS"
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/seq_file.h>
++
++#include <mach/display.h>
++#include "dss.h"
++
++#define DSS_BASE			0x48050000
++
++#define DSS_SZ_REGS			SZ_512
++
++struct dss_reg {
++	u16 idx;
++};
++
++#define DSS_REG(idx)			((const struct dss_reg) { idx })
++
++#define DSS_REVISION			DSS_REG(0x0000)
++#define DSS_SYSCONFIG			DSS_REG(0x0010)
++#define DSS_SYSSTATUS			DSS_REG(0x0014)
++#define DSS_IRQSTATUS			DSS_REG(0x0018)
++#define DSS_CONTROL			DSS_REG(0x0040)
++#define DSS_SDI_CONTROL			DSS_REG(0x0044)
++#define DSS_PLL_CONTROL			DSS_REG(0x0048)
++#define DSS_SDI_STATUS			DSS_REG(0x005C)
++
++#define REG_GET(idx, start, end) \
++	FLD_GET(dss_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++	dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
++
++static struct {
++	void __iomem    *base;
++
++	u32		ctx[DSS_SZ_REGS / sizeof(u32)];
++} dss;
++
++static int _omap_dss_wait_reset(void);
++
++static inline void dss_write_reg(const struct dss_reg idx, u32 val)
++{
++	__raw_writel(val, dss.base + idx.idx);
++}
++
++static inline u32 dss_read_reg(const struct dss_reg idx)
++{
++	return __raw_readl(dss.base + idx.idx);
++}
++
++#define SR(reg) \
++	dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
++#define RR(reg) \
++	dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
++
++void dss_save_context(void)
++{
++	if (cpu_is_omap24xx())
++		return;
++
++	SR(SYSCONFIG);
++	SR(CONTROL);
++
++#ifdef CONFIG_OMAP2_DSS_SDI
++	SR(SDI_CONTROL);
++	SR(PLL_CONTROL);
++#endif
++}
++
++void dss_restore_context(void)
++{
++	if (_omap_dss_wait_reset())
++		DSSERR("DSS not coming out of reset after sleep\n");
++
++	RR(SYSCONFIG);
++	RR(CONTROL);
++
++#ifdef CONFIG_OMAP2_DSS_SDI
++	RR(SDI_CONTROL);
++	RR(PLL_CONTROL);
++#endif
++}
++
++#undef SR
++#undef RR
++
++void dss_sdi_init(u8 datapairs)
++{
++	u32 l;
++
++	BUG_ON(datapairs > 3 || datapairs < 1);
++
++	l = dss_read_reg(DSS_SDI_CONTROL);
++	l = FLD_MOD(l, 0xf, 19, 15);		/* SDI_PDIV */
++	l = FLD_MOD(l, datapairs-1, 3, 2);	/* SDI_PRSEL */
++	l = FLD_MOD(l, 2, 1, 0);		/* SDI_BWSEL */
++	dss_write_reg(DSS_SDI_CONTROL, l);
++
++	l = dss_read_reg(DSS_PLL_CONTROL);
++	l = FLD_MOD(l, 0x7, 25, 22);	/* SDI_PLL_FREQSEL */
++	l = FLD_MOD(l, 0xb, 16, 11);	/* SDI_PLL_REGN */
++	l = FLD_MOD(l, 0xb4, 10, 1);	/* SDI_PLL_REGM */
++	dss_write_reg(DSS_PLL_CONTROL, l);
++}
++
++void dss_sdi_enable(void)
++{
++	dispc_pck_free_enable(1);
++
++	/* Reset SDI PLL */
++	REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
++	udelay(1);	/* wait 2x PCLK */
++
++	/* Lock SDI PLL */
++	REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
++
++	/* Waiting for PLL lock request to complete */
++	while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6))
++		;
++
++	/* Clearing PLL_GO bit */
++	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
++
++	/* Waiting for PLL to lock */
++	while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5)))
++		;
++
++	dispc_lcd_enable_signal(1);
++
++	/* Waiting for SDI reset to complete */
++	while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2)))
++		;
++}
++
++void dss_sdi_disable(void)
++{
++	dispc_lcd_enable_signal(0);
++
++	dispc_pck_free_enable(0);
++
++	/* Reset SDI PLL */
++	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
++}
++
++void dss_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	DUMPREG(DSS_REVISION);
++	DUMPREG(DSS_SYSCONFIG);
++	DUMPREG(DSS_SYSSTATUS);
++	DUMPREG(DSS_IRQSTATUS);
++	DUMPREG(DSS_CONTROL);
++	DUMPREG(DSS_SDI_CONTROL);
++	DUMPREG(DSS_PLL_CONTROL);
++	DUMPREG(DSS_SDI_STATUS);
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++void dss_select_clk_source(bool dsi, bool dispc)
++{
++	u32 r;
++	r = dss_read_reg(DSS_CONTROL);
++	r = FLD_MOD(r, dsi, 1, 1);	/* DSI_CLK_SWITCH */
++	r = FLD_MOD(r, dispc, 0, 0);	/* DISPC_CLK_SWITCH */
++	dss_write_reg(DSS_CONTROL, r);
++}
++
++int dss_get_dsi_clk_source(void)
++{
++	return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1);
++}
++
++int dss_get_dispc_clk_source(void)
++{
++	return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0);
++}
++
++static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
++{
++	dispc_irq_handler();
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
++{
++	u32 irqstatus;
++
++	irqstatus = dss_read_reg(DSS_IRQSTATUS);
++
++	if (irqstatus & (1<<0))	/* DISPC_IRQ */
++		dispc_irq_handler();
++#ifdef CONFIG_OMAP2_DSS_DSI
++	if (irqstatus & (1<<1))	/* DSI_IRQ */
++		dsi_irq_handler();
++#endif
++
++	return IRQ_HANDLED;
++}
++
++static int _omap_dss_wait_reset(void)
++{
++	unsigned timeout = 1000;
++
++	while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
++		udelay(1);
++		if (!--timeout) {
++			DSSERR("soft reset failed\n");
++			return -ENODEV;
++		}
++	}
++
++	return 0;
++}
++
++static int _omap_dss_reset(void)
++{
++	/* Soft reset */
++	REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
++	return _omap_dss_wait_reset();
++}
++
++void dss_set_venc_output(enum omap_dss_venc_type type)
++{
++	int l = 0;
++
++	if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
++		l = 0;
++	else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
++		l = 1;
++	else
++		BUG();
++
++	/* venc out selection. 0 = comp, 1 = svideo */
++	REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
++}
++
++void dss_set_dac_pwrdn_bgz(bool enable)
++{
++	REG_FLD_MOD(DSS_CONTROL, enable, 5, 5);	/* DAC Power-Down Control */
++}
++
++int dss_init(bool skip_init)
++{
++	int r;
++	u32 rev;
++
++	dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
++	if (!dss.base) {
++		DSSERR("can't ioremap DSS\n");
++		r = -ENOMEM;
++		goto fail0;
++	}
++
++	if (!skip_init) {
++		/* We need to wait here a bit, otherwise we sometimes start to
++		 * get synclost errors, and after that only power cycle will
++		 * restore DSS functionality. I have no idea why this happens.
++		 * And we have to wait _before_ resetting the DSS, but after
++		 * enabling clocks.
++		 */
++		msleep(50);
++
++		_omap_dss_reset();
++
++	}
++	else
++		printk("DSS SKIP RESET\n");
++
++	/* autoidle */
++	REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
++
++	/* Select DPLL */
++	REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++	REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);	/* venc dac demen */
++	REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);	/* venc clock 4x enable */
++	REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */
++#endif
++
++	r = request_irq(INT_24XX_DSS_IRQ,
++			cpu_is_omap24xx()
++			? dss_irq_handler_omap2
++			: dss_irq_handler_omap3,
++			0, "OMAP DSS", NULL);
++
++	if (r < 0) {
++		DSSERR("omap2 dss: request_irq failed\n");
++		goto fail1;
++	}
++
++	dss_save_context();
++
++	rev = dss_read_reg(DSS_REVISION);
++	printk(KERN_INFO "OMAP DSS rev %d.%d\n",
++			FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++	return 0;
++
++fail1:
++	iounmap(dss.base);
++fail0:
++	return r;
++}
++
++void dss_exit(void)
++{
++	free_irq(INT_24XX_DSS_IRQ, NULL);
++
++	iounmap(dss.base);
++}
++
+diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
+new file mode 100644
+index 0000000..bac5ece
+--- /dev/null
++++ b/drivers/video/omap2/dss/dss.h
+@@ -0,0 +1,331 @@
++/*
++ * linux/drivers/video/omap2/dss/dss.h
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __OMAP2_DSS_H
++#define __OMAP2_DSS_H
++
++#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
++#define DEBUG
++#endif
++
++#ifdef DEBUG
++extern unsigned int dss_debug;
++#ifdef DSS_SUBSYS_NAME
++#define DSSDBG(format, ...) \
++	if (dss_debug) \
++		printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
++		## __VA_ARGS__)
++#else
++#define DSSDBG(format, ...) \
++	if (dss_debug) \
++		printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSDBGF(format, ...) \
++	if (dss_debug) \
++		printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
++				": %s(" format ")\n", \
++				__func__, \
++				## __VA_ARGS__)
++#else
++#define DSSDBGF(format, ...) \
++	if (dss_debug) \
++		printk(KERN_DEBUG "omapdss: " \
++				": %s(" format ")\n", \
++				__func__, \
++				## __VA_ARGS__)
++#endif
++
++#else /* DEBUG */
++#define DSSDBG(format, ...)
++#define DSSDBGF(format, ...)
++#endif
++
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSERR(format, ...) \
++	printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
++	## __VA_ARGS__)
++#else
++#define DSSERR(format, ...) \
++	printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSINFO(format, ...) \
++	printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
++	## __VA_ARGS__)
++#else
++#define DSSINFO(format, ...) \
++	printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSWARN(format, ...) \
++	printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
++	## __VA_ARGS__)
++#else
++#define DSSWARN(format, ...) \
++	printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
++#endif
++
++/* OMAP TRM gives bitfields as start:end, where start is the higher bit
++   number. For example 7:0 */
++#define FLD_MASK(start, end)	(((1 << (start - end + 1)) - 1) << (end))
++#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end))
++#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
++#define FLD_MOD(orig, val, start, end) \
++	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
++
++#define DISPC_MAX_FCK 173000000
++
++enum omap_burst_size {
++	OMAP_DSS_BURST_4x32 = 0,
++	OMAP_DSS_BURST_8x32 = 1,
++	OMAP_DSS_BURST_16x32 = 2,
++};
++
++enum omap_parallel_interface_mode {
++	OMAP_DSS_PARALLELMODE_BYPASS,		/* MIPI DPI */
++	OMAP_DSS_PARALLELMODE_RFBI,		/* MIPI DBI */
++	OMAP_DSS_PARALLELMODE_DSI,
++};
++
++enum dss_clock {
++	DSS_CLK_ICK	= 1 << 0,
++	DSS_CLK_FCK1	= 1 << 1,
++	DSS_CLK_FCK2	= 1 << 2,
++	DSS_CLK_54M	= 1 << 3,
++	DSS_CLK_96M	= 1 << 4,
++};
++
++struct dispc_clock_info {
++	/* rates that we get with dividers below */
++	unsigned long fck;
++	unsigned long lck;
++	unsigned long pck;
++
++	/* dividers */
++	u16 fck_div;
++	u16 lck_div;
++	u16 pck_div;
++};
++
++struct dsi_clock_info {
++	/* rates that we get with dividers below */
++	unsigned long fint;
++	unsigned long dsiphy;
++	unsigned long clkin;
++	unsigned long dsi1_pll_fclk;
++	unsigned long dsi2_pll_fclk;
++	unsigned long lck;
++	unsigned long pck;
++
++	/* dividers */
++	u16 regn;
++	u16 regm;
++	u16 regm3;
++	u16 regm4;
++
++	u16 lck_div;
++	u16 pck_div;
++
++	u8 highfreq;
++	bool use_dss2_fck;
++};
++
++struct seq_file;
++struct platform_device;
++
++/* core */
++void dss_clk_enable(enum dss_clock clks);
++void dss_clk_disable(enum dss_clock clks);
++unsigned long dss_clk_get_rate(enum dss_clock clk);
++int dss_need_ctx_restore(void);
++void dss_dump_clocks(struct seq_file *s);
++
++int dss_dsi_power_up(void);
++void dss_dsi_power_down(void);
++
++/* display */
++void dss_init_displays(struct platform_device *pdev);
++void dss_uninit_displays(struct platform_device *pdev);
++int dss_suspend_all_displays(void);
++int dss_resume_all_displays(void);
++struct omap_display *dss_get_display(int no);
++
++/* manager */
++int dss_init_overlay_managers(struct platform_device *pdev);
++void dss_uninit_overlay_managers(struct platform_device *pdev);
++
++/* overlay */
++void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name);
++void dss_uninit_overlays(struct platform_device *pdev);
++int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display);
++void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
++
++/* DSS */
++int dss_init(bool skip_init);
++void dss_exit(void);
++
++void dss_save_context(void);
++void dss_restore_context(void);
++
++void dss_dump_regs(struct seq_file *s);
++
++void dss_sdi_init(u8 datapairs);
++void dss_sdi_enable(void);
++void dss_sdi_disable(void);
++
++void dss_select_clk_source(bool dsi, bool dispc);
++int dss_get_dsi_clk_source(void);
++int dss_get_dispc_clk_source(void);
++void dss_set_venc_output(enum omap_dss_venc_type type);
++void dss_set_dac_pwrdn_bgz(bool enable);
++
++/* SDI */
++int sdi_init(bool skip_init);
++void sdi_exit(void);
++void sdi_init_display(struct omap_display *display);
++
++/* DSI */
++int dsi_init(void);
++void dsi_exit(void);
++
++void dsi_dump_clocks(struct seq_file *s);
++void dsi_dump_regs(struct seq_file *s);
++
++void dsi_save_context(void);
++void dsi_restore_context(void);
++
++void dsi_init_display(struct omap_display *display);
++void dsi_irq_handler(void);
++unsigned long dsi_get_dsi1_pll_rate(void);
++unsigned long dsi_get_dsi2_pll_rate(void);
++int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
++		struct dsi_clock_info *cinfo);
++int dsi_pll_program(struct dsi_clock_info *cinfo);
++int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv);
++void dsi_pll_uninit(void);
++
++/* DPI */
++int dpi_init(void);
++void dpi_exit(void);
++void dpi_init_display(struct omap_display *display);
++
++/* DISPC */
++int dispc_init(void);
++void dispc_exit(void);
++void dispc_dump_clocks(struct seq_file *s);
++void dispc_dump_regs(struct seq_file *s);
++void dispc_irq_handler(void);
++void dispc_fake_vsync_irq(void);
++
++void dispc_save_context(void);
++void dispc_restore_context(void);
++
++void dispc_lcd_enable_signal_polarity(bool act_high);
++void dispc_lcd_enable_signal(bool enable);
++void dispc_pck_free_enable(bool enable);
++void dispc_enable_fifohandcheck(bool enable);
++
++void dispc_set_lcd_size(u16 width, u16 height);
++void dispc_set_digit_size(u16 width, u16 height);
++u32 dispc_get_plane_fifo_size(enum omap_plane plane);
++void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
++void dispc_enable_fifomerge(bool enable);
++void dispc_set_burst_size(enum omap_plane plane,
++		enum omap_burst_size burst_size);
++
++void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
++void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
++void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
++void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
++
++int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
++		      u32 paddr, u16 screen_width,
++		      u16 pos_x, u16 pos_y,
++		      u16 width, u16 height,
++		      u16 out_width, u16 out_height,
++		      enum omap_color_mode color_mode,
++		      bool ilace,
++		      u8 rotation, bool mirror);
++
++void dispc_go(enum omap_channel channel);
++void dispc_enable_lcd_out(bool enable);
++void dispc_enable_digit_out(bool enable);
++int dispc_enable_plane(enum omap_plane plane, bool enable);
++
++void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
++void dispc_set_tft_data_lines(u8 data_lines);
++void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
++void dispc_set_loadmode(enum omap_dss_load_mode mode);
++
++void dispc_set_default_color(enum omap_channel channel, u32 color);
++u32 dispc_get_default_color(enum omap_channel channel);
++void dispc_set_trans_key(enum omap_channel ch,
++		enum omap_dss_color_key_type type,
++		u32 trans_key);
++void dispc_get_trans_key(enum omap_channel ch,
++		enum omap_dss_color_key_type *type,
++		u32 *trans_key);
++void dispc_enable_trans_key(enum omap_channel ch, bool enable);
++bool dispc_trans_key_enabled(enum omap_channel ch);
++
++void dispc_set_lcd_timings(struct omap_video_timings *timings);
++unsigned long dispc_fclk_rate(void);
++unsigned long dispc_pclk_rate(void);
++void dispc_set_pol_freq(struct omap_panel *panel);
++void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
++		u16 *lck_div, u16 *pck_div);
++int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
++		struct dispc_clock_info *cinfo);
++int dispc_set_clock_div(struct dispc_clock_info *cinfo);
++int dispc_get_clock_div(struct dispc_clock_info *cinfo);
++void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div);
++
++void dispc_setup_partial_planes(struct omap_display *display,
++				u16 *x, u16 *y, u16 *w, u16 *h);
++void dispc_draw_partial_planes(struct omap_display *display);
++
++
++/* VENC */
++int venc_init(void);
++void venc_exit(void);
++void venc_dump_regs(struct seq_file *s);
++void venc_init_display(struct omap_display *display);
++
++/* RFBI */
++int rfbi_init(void);
++void rfbi_exit(void);
++void rfbi_dump_regs(struct seq_file *s);
++
++int rfbi_configure(int rfbi_module, int bpp, int lines);
++void rfbi_enable_rfbi(bool enable);
++void rfbi_transfer_area(u16 width, u16 height,
++			     void (callback)(void *data), void *data);
++void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
++unsigned long rfbi_get_max_tx_rate(void);
++void rfbi_init_display(struct omap_display *display);
++
++#endif
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+new file mode 100644
+index 0000000..b0fee80
+--- /dev/null
++++ b/drivers/video/omap2/dss/manager.c
+@@ -0,0 +1,576 @@
++/*
++ * linux/drivers/video/omap2/dss/manager.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "MANAGER"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <mach/display.h>
++
++#include "dss.h"
++
++static int num_managers;
++static struct list_head manager_list;
++
++static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%s\n", mgr->name);
++}
++
++static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%s\n",
++			mgr->display ? mgr->display->name : "<none>");
++}
++
++static ssize_t manager_display_store(struct omap_overlay_manager *mgr, const char *buf, size_t size)
++{
++	int r, i;
++	int len = size;
++	struct omap_display *display = NULL;
++
++	if (buf[size-1] == '\n')
++		--len;
++
++	if (len > 0) {
++		for (i = 0; i < omap_dss_get_num_displays(); ++i) {
++			display = dss_get_display(i);
++
++			if (strncmp(buf, display->name, len) == 0)
++				break;
++
++			display = NULL;
++		}
++	}
++
++	if (len > 0 && display == NULL)
++		return -EINVAL;
++
++	if (display)
++		DSSDBG("display %s found\n", display->name);
++
++	if (mgr->display) {
++		r = mgr->unset_display(mgr);
++		if (r) {
++			DSSERR("failed to unset display\n");
++			return r;
++		}
++	}
++
++	if (display) {
++		r = mgr->set_display(mgr, display);
++		if (r) {
++			DSSERR("failed to set manager\n");
++			return r;
++		}
++
++		r = mgr->apply(mgr);
++		if (r) {
++			DSSERR("failed to apply dispc config\n");
++			return r;
++		}
++	}
++
++	return size;
++}
++
++static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
++					  char *buf)
++{
++	u32 default_color;
++
++	default_color = dispc_get_default_color(mgr->id);
++	return snprintf(buf, PAGE_SIZE, "%d", default_color);
++}
++
++static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
++					   const char *buf, size_t size)
++{
++	u32 default_color;
++
++	if (sscanf(buf, "%d", &default_color) != 1)
++		return -EINVAL;
++	dispc_set_default_color(mgr->id, default_color);
++
++	return size;
++}
++
++static const char *color_key_type_str[] = {
++	"gfx-destination",
++	"video-source",
++};
++
++static ssize_t manager_color_key_type_show(struct omap_overlay_manager *mgr,
++					   char *buf)
++{
++	enum omap_dss_color_key_type key_type;
++
++	dispc_get_trans_key(mgr->id, &key_type, NULL);
++	BUG_ON(key_type >= ARRAY_SIZE(color_key_type_str));
++
++	return snprintf(buf, PAGE_SIZE, "%s\n", color_key_type_str[key_type]);
++}
++
++static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
++					    const char *buf, size_t size)
++{
++	enum omap_dss_color_key_type key_type;
++	u32 key_value;
++
++	for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
++	     key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
++		if (sysfs_streq(buf, color_key_type_str[key_type]))
++			break;
++	}
++	if (key_type == ARRAY_SIZE(color_key_type_str))
++		return -EINVAL;
++	dispc_get_trans_key(mgr->id, NULL, &key_value);
++	dispc_set_trans_key(mgr->id, key_type, key_value);
++
++	return size;
++}
++
++static ssize_t manager_color_key_value_show(struct omap_overlay_manager *mgr,
++					    char *buf)
++{
++	u32 key_value;
++
++	dispc_get_trans_key(mgr->id, NULL, &key_value);
++
++	return snprintf(buf, PAGE_SIZE, "%d\n", key_value);
++}
++
++static ssize_t manager_color_key_value_store(struct omap_overlay_manager *mgr,
++					     const char *buf, size_t size)
++{
++	enum omap_dss_color_key_type key_type;
++	u32 key_value;
++
++	if (sscanf(buf, "%d", &key_value) != 1)
++		return -EINVAL;
++	dispc_get_trans_key(mgr->id, &key_type, NULL);
++	dispc_set_trans_key(mgr->id, key_type, key_value);
++
++	return size;
++}
++
++static ssize_t manager_color_key_enabled_show(struct omap_overlay_manager *mgr,
++					      char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d\n",
++			dispc_trans_key_enabled(mgr->id));
++}
++
++static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
++					       const char *buf, size_t size)
++{
++	int enable;
++
++	if (sscanf(buf, "%d", &enable) != 1)
++		return -EINVAL;
++
++	dispc_enable_trans_key(mgr->id, enable);
++
++	return size;
++}
++
++
++struct manager_attribute {
++	struct attribute attr;
++	ssize_t (*show)(struct omap_overlay_manager *, char *);
++	ssize_t	(*store)(struct omap_overlay_manager *, const char *, size_t);
++};
++
++#define MANAGER_ATTR(_name, _mode, _show, _store) \
++	struct manager_attribute manager_attr_##_name = \
++	__ATTR(_name, _mode, _show, _store)
++
++static MANAGER_ATTR(name, S_IRUGO, manager_name_show, NULL);
++static MANAGER_ATTR(display, S_IRUGO|S_IWUSR,
++		manager_display_show, manager_display_store);
++static MANAGER_ATTR(default_color, S_IRUGO|S_IWUSR,
++		manager_default_color_show, manager_default_color_store);
++static MANAGER_ATTR(color_key_type, S_IRUGO|S_IWUSR,
++		manager_color_key_type_show, manager_color_key_type_store);
++static MANAGER_ATTR(color_key_value, S_IRUGO|S_IWUSR,
++		manager_color_key_value_show, manager_color_key_value_store);
++static MANAGER_ATTR(color_key_enabled, S_IRUGO|S_IWUSR,
++		manager_color_key_enabled_show, manager_color_key_enabled_store);
++
++static struct attribute *manager_sysfs_attrs[] = {
++	&manager_attr_name.attr,
++	&manager_attr_display.attr,
++	&manager_attr_default_color.attr,
++	&manager_attr_color_key_type.attr,
++	&manager_attr_color_key_value.attr,
++	&manager_attr_color_key_enabled.attr,
++	NULL
++};
++
++static ssize_t manager_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
++{
++	struct omap_overlay_manager *manager;
++	struct manager_attribute *manager_attr;
++
++	manager = container_of(kobj, struct omap_overlay_manager, kobj);
++	manager_attr = container_of(attr, struct manager_attribute, attr);
++
++	if (!manager_attr->show)
++		return -ENOENT;
++
++	return manager_attr->show(manager, buf);
++}
++
++static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr,
++		const char *buf, size_t size)
++{
++	struct omap_overlay_manager *manager;
++	struct manager_attribute *manager_attr;
++
++	manager = container_of(kobj, struct omap_overlay_manager, kobj);
++	manager_attr = container_of(attr, struct manager_attribute, attr);
++
++	if (!manager_attr->store)
++		return -ENOENT;
++
++	return manager_attr->store(manager, buf, size);
++}
++
++static struct sysfs_ops manager_sysfs_ops = {
++	.show = manager_attr_show,
++	.store = manager_attr_store,
++};
++
++static struct kobj_type manager_ktype = {
++	.sysfs_ops = &manager_sysfs_ops,
++	.default_attrs = manager_sysfs_attrs,
++};
++
++static int omap_dss_set_display(struct omap_overlay_manager *mgr,
++		struct omap_display *display)
++{
++	int i;
++	int r;
++
++	if (display->manager) {
++		DSSERR("display '%s' already has a manager '%s'\n",
++			       display->name, display->manager->name);
++		return -EINVAL;
++	}
++
++	if ((mgr->supported_displays & display->type) == 0) {
++		DSSERR("display '%s' does not support manager '%s'\n",
++			       display->name, mgr->name);
++		return -EINVAL;
++	}
++
++	for (i = 0; i < mgr->num_overlays; i++) {
++		struct omap_overlay *ovl = mgr->overlays[i];
++
++		if (ovl->manager != mgr || !ovl->info.enabled)
++			continue;
++
++		r = dss_check_overlay(ovl, display);
++		if (r)
++			return r;
++	}
++
++	display->manager = mgr;
++	mgr->display = display;
++
++	return 0;
++}
++
++static int omap_dss_unset_display(struct omap_overlay_manager *mgr)
++{
++	if (!mgr->display) {
++		DSSERR("failed to unset display, display not set.\n");
++		return -EINVAL;
++	}
++
++	mgr->display->manager = NULL;
++	mgr->display = NULL;
++
++	return 0;
++}
++
++
++static int overlay_enabled(struct omap_overlay *ovl)
++{
++	return ovl->info.enabled && ovl->manager && ovl->manager->display;
++}
++
++/* We apply settings to both managers here so that we can use optimizations
++ * like fifomerge. Shadow registers can be changed first and the non-shadowed
++ * should be changed last, at the same time with GO */
++static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
++{
++	int i;
++	int ret = 0;
++	enum omap_dss_update_mode mode;
++	struct omap_display *display;
++	struct omap_overlay *ovl;
++	bool ilace = 0;
++	int outw, outh;
++	int r;
++	int num_planes_enabled = 0;
++
++	DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	/* Configure normal overlay parameters and disable unused overlays */
++	for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++		ovl = omap_dss_get_overlay(i);
++
++		if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++			continue;
++
++		if (!overlay_enabled(ovl)) {
++			dispc_enable_plane(ovl->id, 0);
++			continue;
++		}
++
++		display = ovl->manager->display;
++
++		if (dss_check_overlay(ovl, display)) {
++			dispc_enable_plane(ovl->id, 0);
++			continue;
++		}
++
++		++num_planes_enabled;
++
++		/* On a manual update display, in manual update mode, update()
++		 * handles configuring planes */
++		mode = OMAP_DSS_UPDATE_AUTO;
++		if (display->get_update_mode)
++			mode = display->get_update_mode(mgr->display);
++
++		if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE &&
++				mode != OMAP_DSS_UPDATE_AUTO)
++			continue;
++
++		if (display->type == OMAP_DISPLAY_TYPE_VENC)
++			ilace = 1;
++
++		if (ovl->info.out_width == 0)
++			outw = ovl->info.width;
++		else
++			outw = ovl->info.out_width;
++
++		if (ovl->info.out_height == 0)
++			outh = ovl->info.height;
++		else
++			outh = ovl->info.out_height;
++
++		r = dispc_setup_plane(ovl->id, ovl->manager->id,
++				ovl->info.paddr,
++				ovl->info.screen_width,
++				ovl->info.pos_x,
++				ovl->info.pos_y,
++				ovl->info.width,
++				ovl->info.height,
++				outw,
++				outh,
++				ovl->info.color_mode,
++				ilace,
++				ovl->info.rotation,
++				ovl->info.mirror);
++
++		if (r) {
++			DSSERR("dispc_setup_plane failed for ovl %d\n",
++					ovl->id);
++			dispc_enable_plane(ovl->id, 0);
++			continue;
++		}
++
++		dispc_enable_plane(ovl->id, 1);
++	}
++
++	/* Enable fifo merge if possible */
++	dispc_enable_fifomerge(num_planes_enabled == 1);
++
++	/* Go through overlays again. This time we configure fifos.  We have to
++	 * do this after enabling/disabling fifomerge so that we have correct
++	 * knowledge of fifo sizes */
++	for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++		ovl = omap_dss_get_overlay(i);
++
++		if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++			continue;
++
++		if (!overlay_enabled(ovl)) {
++			continue;
++		}
++
++		ovl->manager->display->configure_overlay(ovl);
++	}
++
++	/* Issue GO for managers */
++	list_for_each_entry(mgr, &manager_list, list) {
++		if (!(mgr->caps & OMAP_DSS_OVL_MGR_CAP_DISPC))
++			continue;
++
++		display = mgr->display;
++
++		if (!display)
++			continue;
++
++		/* We don't need GO with manual update display. LCD iface will
++		 * always be turned off after frame, and new settings will
++		 * be taken in to use at next update */
++		if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE)
++			continue;
++
++		dispc_go(mgr->id);
++	}
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	return ret;
++}
++
++static void omap_dss_mgr_set_def_color(struct omap_overlay_manager *mgr,
++		u32 color)
++{
++	dispc_set_default_color(mgr->id, color);
++}
++
++static void omap_dss_mgr_set_trans_key(struct omap_overlay_manager *mgr,
++		enum omap_dss_color_key_type type,
++		u32 trans_key)
++{
++	dispc_set_trans_key(mgr->id, type, trans_key);
++}
++
++static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
++		bool enable)
++{
++	dispc_enable_trans_key(mgr->id, enable);
++}
++
++static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
++{
++	++num_managers;
++	list_add_tail(&manager->list, &manager_list);
++}
++
++int dss_init_overlay_managers(struct platform_device *pdev)
++{
++	int i, r;
++
++	INIT_LIST_HEAD(&manager_list);
++
++	num_managers = 0;
++
++	for (i = 0; i < 2; ++i) {
++		struct omap_overlay_manager *mgr;
++		mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
++
++		BUG_ON(mgr == NULL);
++
++		switch (i) {
++		case 0:
++			mgr->name = "lcd";
++			mgr->id = OMAP_DSS_CHANNEL_LCD;
++			mgr->supported_displays =
++				OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
++				OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
++			break;
++		case 1:
++			mgr->name = "tv";
++			mgr->id = OMAP_DSS_CHANNEL_DIGIT;
++			mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
++			break;
++		}
++
++		mgr->set_display = &omap_dss_set_display,
++		mgr->unset_display = &omap_dss_unset_display,
++		mgr->apply = &omap_dss_mgr_apply,
++		mgr->set_default_color = &omap_dss_mgr_set_def_color,
++		mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
++		mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
++		mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
++
++		dss_overlay_setup_dispc_manager(mgr);
++
++		omap_dss_add_overlay_manager(mgr);
++
++		r = kobject_init_and_add(&mgr->kobj, &manager_ktype,
++				&pdev->dev.kobj, "manager%d", i);
++
++		if (r) {
++			DSSERR("failed to create sysfs file\n");
++			continue;
++		}
++	}
++
++	return 0;
++}
++
++void dss_uninit_overlay_managers(struct platform_device *pdev)
++{
++	struct omap_overlay_manager *mgr;
++
++	while (!list_empty(&manager_list)) {
++		mgr = list_first_entry(&manager_list,
++				struct omap_overlay_manager, list);
++		list_del(&mgr->list);
++		kobject_del(&mgr->kobj);
++		kobject_put(&mgr->kobj);
++		kfree(mgr);
++	}
++
++	num_managers = 0;
++}
++
++int omap_dss_get_num_overlay_managers(void)
++{
++	return num_managers;
++}
++EXPORT_SYMBOL(omap_dss_get_num_overlay_managers);
++
++struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
++{
++	int i = 0;
++	struct omap_overlay_manager *mgr;
++
++	list_for_each_entry(mgr, &manager_list, list) {
++		if (i++ == num)
++			return mgr;
++	}
++
++	return NULL;
++}
++EXPORT_SYMBOL(omap_dss_get_overlay_manager);
++
++#ifdef L4_EXAMPLE
++static int ovl_mgr_apply_l4(struct omap_overlay_manager *mgr)
++{
++	DSSDBG("omap_dss_mgr_apply_l4(%s)\n", mgr->name);
++
++	return 0;
++}
++#endif
++
+diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
+new file mode 100644
+index 0000000..968edbe
+--- /dev/null
++++ b/drivers/video/omap2/dss/overlay.c
+@@ -0,0 +1,587 @@
++/*
++ * linux/drivers/video/omap2/dss/overlay.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "OVERLAY"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/sysfs.h>
++#include <linux/kobject.h>
++#include <linux/platform_device.h>
++
++#include <mach/display.h>
++
++#include "dss.h"
++
++static int num_overlays;
++static struct list_head overlay_list;
++
++static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%s\n", ovl->name);
++}
++
++static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%s\n",
++			ovl->manager ? ovl->manager->name : "<none>");
++}
++
++static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf, size_t size)
++{
++	int i, r;
++	struct omap_overlay_manager *mgr = NULL;
++	int len = size;
++
++	if (buf[size-1] == '\n')
++		--len;
++
++	if (len > 0) {
++		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
++			mgr = omap_dss_get_overlay_manager(i);
++
++			if (strncmp(buf, mgr->name, len) == 0)
++				break;
++
++			mgr = NULL;
++		}
++	}
++
++	if (len > 0 && mgr == NULL)
++		return -EINVAL;
++
++	if (mgr)
++		DSSDBG("manager %s found\n", mgr->name);
++
++	if (mgr != ovl->manager) {
++		/* detach old manager */
++		if (ovl->manager) {
++			r = ovl->unset_manager(ovl);
++			if (r) {
++				DSSERR("detach failed\n");
++				return r;
++			}
++		}
++
++		if (mgr) {
++			r = ovl->set_manager(ovl, mgr);
++			if (r) {
++				DSSERR("Failed to attach overlay\n");
++				return r;
++			}
++		}
++	}
++
++	if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
++		return r;
++
++	return size;
++}
++
++static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d,%d\n",
++			ovl->info.width, ovl->info.height);
++}
++
++static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.screen_width);
++}
++
++static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d,%d\n",
++			ovl->info.pos_x, ovl->info.pos_y);
++}
++
++static ssize_t overlay_position_store(struct omap_overlay *ovl,
++		const char *buf, size_t size)
++{
++	int r;
++	char *last;
++	struct omap_overlay_info info;
++
++	ovl->get_overlay_info(ovl, &info);
++
++	info.pos_x = simple_strtoul(buf, &last, 10);
++	++last;
++	if (last - buf >= size)
++		return -EINVAL;
++
++	info.pos_y = simple_strtoul(last, &last, 10);
++
++	if ((r = ovl->set_overlay_info(ovl, &info)))
++		return r;
++
++	if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
++		return r;
++
++	return size;
++}
++
++static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d,%d\n",
++			ovl->info.out_width, ovl->info.out_height);
++}
++
++static ssize_t overlay_output_size_store(struct omap_overlay *ovl,
++		const char *buf, size_t size)
++{
++	int r;
++	char *last;
++	struct omap_overlay_info info;
++
++	ovl->get_overlay_info(ovl, &info);
++
++	info.out_width = simple_strtoul(buf, &last, 10);
++	++last;
++	if (last - buf >= size)
++		return -EINVAL;
++
++	info.out_height = simple_strtoul(last, &last, 10);
++
++	if ((r = ovl->set_overlay_info(ovl, &info)))
++		return r;
++
++	if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
++		return r;
++
++	return size;
++}
++
++static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.enabled);
++}
++
++static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf, size_t size)
++{
++	int r;
++	struct omap_overlay_info info;
++
++	ovl->get_overlay_info(ovl, &info);
++
++	info.enabled = simple_strtoul(buf, NULL, 10);
++
++	if ((r = ovl->set_overlay_info(ovl, &info)))
++		return r;
++
++	if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
++		return r;
++
++	return size;
++}
++
++struct overlay_attribute {
++	struct attribute attr;
++	ssize_t (*show)(struct omap_overlay *, char *);
++	ssize_t	(*store)(struct omap_overlay *, const char *, size_t);
++};
++
++#define OVERLAY_ATTR(_name, _mode, _show, _store) \
++	struct overlay_attribute overlay_attr_##_name = \
++	__ATTR(_name, _mode, _show, _store)
++
++static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL);
++static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR,
++		overlay_manager_show, overlay_manager_store);
++static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL);
++static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL);
++static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR,
++		overlay_position_show, overlay_position_store);
++static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
++		overlay_output_size_show, overlay_output_size_store);
++static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
++		overlay_enabled_show, overlay_enabled_store);
++
++static struct attribute *overlay_sysfs_attrs[] = {
++	&overlay_attr_name.attr,
++	&overlay_attr_manager.attr,
++	&overlay_attr_input_size.attr,
++	&overlay_attr_screen_width.attr,
++	&overlay_attr_position.attr,
++	&overlay_attr_output_size.attr,
++	&overlay_attr_enabled.attr,
++	NULL
++};
++
++static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
++{
++	struct omap_overlay *overlay;
++	struct overlay_attribute *overlay_attr;
++
++	overlay = container_of(kobj, struct omap_overlay, kobj);
++	overlay_attr = container_of(attr, struct overlay_attribute, attr);
++
++	if (!overlay_attr->show)
++		return -ENOENT;
++
++	return overlay_attr->show(overlay, buf);
++}
++
++static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr,
++		const char *buf, size_t size)
++{
++	struct omap_overlay *overlay;
++	struct overlay_attribute *overlay_attr;
++
++	overlay = container_of(kobj, struct omap_overlay, kobj);
++	overlay_attr = container_of(attr, struct overlay_attribute, attr);
++
++	if (!overlay_attr->store)
++		return -ENOENT;
++
++	return overlay_attr->store(overlay, buf, size);
++}
++
++static struct sysfs_ops overlay_sysfs_ops = {
++	.show = overlay_attr_show,
++	.store = overlay_attr_store,
++};
++
++static struct kobj_type overlay_ktype = {
++	.sysfs_ops = &overlay_sysfs_ops,
++	.default_attrs = overlay_sysfs_attrs,
++};
++
++/* Check if overlay parameters are compatible with display */
++int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display)
++{
++	struct omap_overlay_info *info;
++	u16 outw, outh;
++	u16 dw, dh;
++
++	if (!display)
++		return 0;
++
++	if (!ovl->info.enabled)
++		return 0;
++
++	info = &ovl->info;
++
++	display->get_resolution(display, &dw, &dh);
++
++	DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n",
++			ovl->id,
++			info->pos_x, info->pos_y,
++			info->width, info->height,
++			info->out_width, info->out_height,
++			dw, dh);
++
++	if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
++		outw = info->width;
++		outh = info->height;
++	} else {
++		if (info->out_width == 0)
++			outw = info->width;
++		else
++			outw = info->out_width;
++
++		if (info->out_height == 0)
++			outh = info->height;
++		else
++			outh = info->out_height;
++	}
++
++	if (dw < info->pos_x + outw) {
++		DSSDBG("check_overlay failed 1: %d < %d + %d\n",
++				dw, info->pos_x, outw);
++		return -EINVAL;
++	}
++
++	if (dh < info->pos_y + outh) {
++		DSSDBG("check_overlay failed 2: %d < %d + %d\n",
++				dh, info->pos_y, outh);
++		return -EINVAL;
++	}
++
++	if ((ovl->supported_modes & info->color_mode) == 0) {
++		DSSERR("overlay doesn't support mode %d\n", info->color_mode);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
++		struct omap_overlay_info *info)
++{
++	int r;
++	struct omap_overlay_info old_info;
++
++	old_info = ovl->info;
++	ovl->info = *info;
++
++	if (ovl->manager) {
++		r = dss_check_overlay(ovl, ovl->manager->display);
++		if (r) {
++			ovl->info = old_info;
++			return r;
++		}
++	}
++
++	return 0;
++}
++
++static void dss_ovl_get_overlay_info(struct omap_overlay *ovl,
++		struct omap_overlay_info *info)
++{
++	*info = ovl->info;
++}
++
++static int omap_dss_set_manager(struct omap_overlay *ovl,
++		struct omap_overlay_manager *mgr)
++{
++	int r;
++
++	if (ovl->manager) {
++		DSSERR("overlay '%s' already has a manager '%s'\n",
++				ovl->name, ovl->manager->name);
++	}
++
++	r = dss_check_overlay(ovl, mgr->display);
++	if (r)
++		return r;
++
++	ovl->manager = mgr;
++
++	return 0;
++}
++
++static int omap_dss_unset_manager(struct omap_overlay *ovl)
++{
++	if (!ovl->manager) {
++		DSSERR("failed to detach overlay: manager not set\n");
++		return -EINVAL;
++	}
++
++	ovl->manager = NULL;
++
++	return 0;
++}
++
++int omap_dss_get_num_overlays(void)
++{
++	return num_overlays;
++}
++EXPORT_SYMBOL(omap_dss_get_num_overlays);
++
++struct omap_overlay *omap_dss_get_overlay(int num)
++{
++	int i = 0;
++	struct omap_overlay *ovl;
++
++	list_for_each_entry(ovl, &overlay_list, list) {
++		if (i++ == num)
++			return ovl;
++	}
++
++	return NULL;
++}
++EXPORT_SYMBOL(omap_dss_get_overlay);
++
++static void omap_dss_add_overlay(struct omap_overlay *overlay)
++{
++	++num_overlays;
++	list_add_tail(&overlay->list, &overlay_list);
++}
++
++static struct omap_overlay *dispc_overlays[3];
++
++void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr)
++{
++	mgr->num_overlays = 3;
++	mgr->overlays = dispc_overlays;
++}
++
++void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
++{
++	int i, r;
++	struct omap_overlay_manager *lcd_mgr;
++	struct omap_overlay_manager *tv_mgr;
++	struct omap_overlay_manager *def_mgr = NULL;
++
++	INIT_LIST_HEAD(&overlay_list);
++
++	num_overlays = 0;
++
++	for (i = 0; i < 3; ++i) {
++		struct omap_overlay *ovl;
++		ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
++
++		BUG_ON(ovl == NULL);
++
++		switch (i) {
++		case 0:
++			ovl->name = "gfx";
++			ovl->id = OMAP_DSS_GFX;
++			ovl->supported_modes = OMAP_DSS_COLOR_GFX_OMAP3;
++			ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
++			break;
++		case 1:
++			ovl->name = "vid1";
++			ovl->id = OMAP_DSS_VIDEO1;
++			ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
++			ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
++				OMAP_DSS_OVL_CAP_DISPC;
++			break;
++		case 2:
++			ovl->name = "vid2";
++			ovl->id = OMAP_DSS_VIDEO2;
++			ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
++			ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
++				OMAP_DSS_OVL_CAP_DISPC;
++			break;
++		}
++
++		ovl->set_manager = &omap_dss_set_manager;
++		ovl->unset_manager = &omap_dss_unset_manager;
++		ovl->set_overlay_info = &dss_ovl_set_overlay_info;
++		ovl->get_overlay_info = &dss_ovl_get_overlay_info;
++
++		omap_dss_add_overlay(ovl);
++
++		r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
++				&pdev->dev.kobj, "overlay%d", i);
++
++		if (r) {
++			DSSERR("failed to create sysfs file\n");
++			continue;
++		}
++
++		dispc_overlays[i] = ovl;
++	}
++
++	lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
++	tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
++
++	if (def_disp_name) {
++		for (i = 0; i < omap_dss_get_num_displays() ; i++) {
++			struct omap_display *display = dss_get_display(i);
++
++			if (strcmp(display->name, def_disp_name) == 0) {
++				if (display->type != OMAP_DISPLAY_TYPE_VENC) {
++					lcd_mgr->set_display(lcd_mgr, display);
++					def_mgr = lcd_mgr;
++				} else {
++					lcd_mgr->set_display(tv_mgr, display);
++					def_mgr = tv_mgr;
++				}
++
++				break;
++			}
++		}
++
++		if (!def_mgr)
++			DSSWARN("default display %s not found\n",
++					def_disp_name);
++	}
++
++	if (def_mgr != lcd_mgr) {
++		/* connect lcd manager to first non-VENC display found */
++		for (i = 0; i < omap_dss_get_num_displays(); i++) {
++			struct omap_display *display = dss_get_display(i);
++			if (display->type != OMAP_DISPLAY_TYPE_VENC) {
++				lcd_mgr->set_display(lcd_mgr, display);
++
++				if (!def_mgr)
++					def_mgr = lcd_mgr;
++
++				break;
++			}
++		}
++	}
++
++	if (def_mgr != tv_mgr) {
++		/* connect tv manager to first VENC display found */
++		for (i = 0; i < omap_dss_get_num_displays(); i++) {
++			struct omap_display *display = dss_get_display(i);
++			if (display->type == OMAP_DISPLAY_TYPE_VENC) {
++				tv_mgr->set_display(tv_mgr, display);
++
++				if (!def_mgr)
++					def_mgr = tv_mgr;
++
++				break;
++			}
++		}
++	}
++
++	/* connect all dispc overlays to def_mgr */
++	if (def_mgr) {
++		for (i = 0; i < 3; i++) {
++			struct omap_overlay *ovl;
++			ovl = omap_dss_get_overlay(i);
++			omap_dss_set_manager(ovl, def_mgr);
++		}
++	}
++
++#ifdef L4_EXAMPLE
++	/* setup L4 overlay as an example */
++	{
++		static struct omap_overlay ovl = {
++			.name = "l4-ovl",
++			.supported_modes = OMAP_DSS_COLOR_RGB24U,
++			.set_manager = &omap_dss_set_manager,
++			.unset_manager = &omap_dss_unset_manager,
++			.setup_input = &omap_dss_setup_overlay_input,
++			.setup_output = &omap_dss_setup_overlay_output,
++			.enable = &omap_dss_enable_overlay,
++		};
++
++		static struct omap_overlay_manager mgr = {
++			.name = "l4",
++			.num_overlays = 1,
++			.overlays = &ovl,
++			.set_display = &omap_dss_set_display,
++			.unset_display = &omap_dss_unset_display,
++			.apply = &ovl_mgr_apply_l4,
++			.supported_displays =
++				OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
++		};
++
++		omap_dss_add_overlay(&ovl);
++		omap_dss_add_overlay_manager(&mgr);
++		omap_dss_set_manager(&ovl, &mgr);
++	}
++#endif
++}
++
++void dss_uninit_overlays(struct platform_device *pdev)
++{
++	struct omap_overlay *ovl;
++
++	while (!list_empty(&overlay_list)) {
++		ovl = list_first_entry(&overlay_list,
++				struct omap_overlay, list);
++		list_del(&ovl->list);
++		kobject_del(&ovl->kobj);
++		kobject_put(&ovl->kobj);
++		kfree(ovl);
++	}
++
++	num_overlays = 0;
++}
++
+diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
+new file mode 100644
+index 0000000..3e9ae1e
+--- /dev/null
++++ b/drivers/video/omap2/dss/rfbi.c
+@@ -0,0 +1,1304 @@
++/*
++ * linux/drivers/video/omap2/dss/rfbi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "RFBI"
++
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <linux/kfifo.h>
++#include <linux/ktime.h>
++#include <linux/hrtimer.h>
++#include <linux/seq_file.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++/*#define MEASURE_PERF*/
++
++#define RFBI_BASE               0x48050800
++
++struct rfbi_reg { u16 idx; };
++
++#define RFBI_REG(idx)		((const struct rfbi_reg) { idx })
++
++#define RFBI_REVISION		RFBI_REG(0x0000)
++#define RFBI_SYSCONFIG		RFBI_REG(0x0010)
++#define RFBI_SYSSTATUS		RFBI_REG(0x0014)
++#define RFBI_CONTROL		RFBI_REG(0x0040)
++#define RFBI_PIXEL_CNT		RFBI_REG(0x0044)
++#define RFBI_LINE_NUMBER	RFBI_REG(0x0048)
++#define RFBI_CMD		RFBI_REG(0x004c)
++#define RFBI_PARAM		RFBI_REG(0x0050)
++#define RFBI_DATA		RFBI_REG(0x0054)
++#define RFBI_READ		RFBI_REG(0x0058)
++#define RFBI_STATUS		RFBI_REG(0x005c)
++
++#define RFBI_CONFIG(n)		RFBI_REG(0x0060 + (n)*0x18)
++#define RFBI_ONOFF_TIME(n)	RFBI_REG(0x0064 + (n)*0x18)
++#define RFBI_CYCLE_TIME(n)	RFBI_REG(0x0068 + (n)*0x18)
++#define RFBI_DATA_CYCLE1(n)	RFBI_REG(0x006c + (n)*0x18)
++#define RFBI_DATA_CYCLE2(n)	RFBI_REG(0x0070 + (n)*0x18)
++#define RFBI_DATA_CYCLE3(n)	RFBI_REG(0x0074 + (n)*0x18)
++
++#define RFBI_VSYNC_WIDTH	RFBI_REG(0x0090)
++#define RFBI_HSYNC_WIDTH	RFBI_REG(0x0094)
++
++#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param))
++
++#define REG_FLD_MOD(idx, val, start, end) \
++	rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
++
++/* To work around an RFBI transfer rate limitation */
++#define OMAP_RFBI_RATE_LIMIT    1
++
++enum omap_rfbi_cycleformat {
++	OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
++	OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
++	OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
++	OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
++};
++
++enum omap_rfbi_datatype {
++	OMAP_DSS_RFBI_DATATYPE_12 = 0,
++	OMAP_DSS_RFBI_DATATYPE_16 = 1,
++	OMAP_DSS_RFBI_DATATYPE_18 = 2,
++	OMAP_DSS_RFBI_DATATYPE_24 = 3,
++};
++
++enum omap_rfbi_parallelmode {
++	OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
++	OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
++	OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
++	OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
++};
++
++enum update_cmd {
++	RFBI_CMD_UPDATE = 0,
++	RFBI_CMD_SYNC   = 1,
++};
++
++static int rfbi_convert_timings(struct rfbi_timings *t);
++static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
++static void process_cmd_fifo(void);
++
++static struct {
++	void __iomem	*base;
++
++	unsigned long	l4_khz;
++
++	enum omap_rfbi_datatype datatype;
++	enum omap_rfbi_parallelmode parallelmode;
++
++	enum omap_rfbi_te_mode te_mode;
++	int te_enabled;
++
++	void (*framedone_callback)(void *data);
++	void *framedone_callback_data;
++
++	struct omap_display *display[2];
++
++	struct kfifo      *cmd_fifo;
++	spinlock_t        cmd_lock;
++	struct completion cmd_done;
++	atomic_t          cmd_fifo_full;
++	atomic_t          cmd_pending;
++#ifdef MEASURE_PERF
++	unsigned perf_bytes;
++	ktime_t perf_setup_time;
++	ktime_t perf_start_time;
++#endif
++} rfbi;
++
++struct update_region {
++	u16	x;
++	u16     y;
++	u16     w;
++	u16     h;
++};
++
++struct update_param {
++	u8 rfbi_module;
++	u8 cmd;
++
++	union {
++		struct update_region r;
++		struct completion *sync;
++	} par;
++};
++
++static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
++{
++	__raw_writel(val, rfbi.base + idx.idx);
++}
++
++static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
++{
++	return __raw_readl(rfbi.base + idx.idx);
++}
++
++static void rfbi_enable_clocks(bool enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	else
++		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++void omap_rfbi_write_command(const void *buf, u32 len)
++{
++	rfbi_enable_clocks(1);
++	switch (rfbi.parallelmode) {
++	case OMAP_DSS_RFBI_PARALLELMODE_8:
++	{
++		const u8 *b = buf;
++		for (; len; len--)
++			rfbi_write_reg(RFBI_CMD, *b++);
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_16:
++	{
++		const u16 *w = buf;
++		BUG_ON(len & 1);
++		for (; len; len -= 2)
++			rfbi_write_reg(RFBI_CMD, *w++);
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_9:
++	case OMAP_DSS_RFBI_PARALLELMODE_12:
++	default:
++		BUG();
++	}
++	rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_command);
++
++void omap_rfbi_read_data(void *buf, u32 len)
++{
++	rfbi_enable_clocks(1);
++	switch (rfbi.parallelmode) {
++	case OMAP_DSS_RFBI_PARALLELMODE_8:
++	{
++		u8 *b = buf;
++		for (; len; len--) {
++			rfbi_write_reg(RFBI_READ, 0);
++			*b++ = rfbi_read_reg(RFBI_READ);
++		}
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_16:
++	{
++		u16 *w = buf;
++		BUG_ON(len & ~1);
++		for (; len; len -= 2) {
++			rfbi_write_reg(RFBI_READ, 0);
++			*w++ = rfbi_read_reg(RFBI_READ);
++		}
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_9:
++	case OMAP_DSS_RFBI_PARALLELMODE_12:
++	default:
++		BUG();
++	}
++	rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_read_data);
++
++void omap_rfbi_write_data(const void *buf, u32 len)
++{
++	rfbi_enable_clocks(1);
++	switch (rfbi.parallelmode) {
++	case OMAP_DSS_RFBI_PARALLELMODE_8:
++	{
++		const u8 *b = buf;
++		for (; len; len--)
++			rfbi_write_reg(RFBI_PARAM, *b++);
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_16:
++	{
++		const u16 *w = buf;
++		BUG_ON(len & 1);
++		for (; len; len -= 2)
++			rfbi_write_reg(RFBI_PARAM, *w++);
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_9:
++	case OMAP_DSS_RFBI_PARALLELMODE_12:
++	default:
++		BUG();
++
++	}
++	rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_data);
++
++void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
++		u16 x, u16 y,
++		u16 w, u16 h)
++{
++	int start_offset = scr_width * y + x;
++	int horiz_offset = scr_width - w;
++	int i;
++
++	rfbi_enable_clocks(1);
++
++	if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
++	   rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
++		const u16 __iomem *pd = buf;
++		pd += start_offset;
++
++		for (; h; --h) {
++			for (i = 0; i < w; ++i) {
++				const u8 __iomem *b = (const u8 __iomem *)pd;
++				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
++				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
++				++pd;
++			}
++			pd += horiz_offset;
++		}
++	} else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
++	   rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
++		const u32 __iomem *pd = buf;
++		pd += start_offset;
++
++		for (; h; --h) {
++			for (i = 0; i < w; ++i) {
++				const u8 __iomem *b = (const u8 __iomem *)pd;
++				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
++				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
++				rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
++				++pd;
++			}
++			pd += horiz_offset;
++		}
++	} else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
++	   rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
++		const u16 __iomem *pd = buf;
++		pd += start_offset;
++
++		for (; h; --h) {
++			for (i = 0; i < w; ++i) {
++				rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
++				++pd;
++			}
++			pd += horiz_offset;
++		}
++	} else {
++		BUG();
++	}
++
++	rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_pixels);
++
++#ifdef MEASURE_PERF
++static void perf_mark_setup(void)
++{
++	rfbi.perf_setup_time = ktime_get();
++}
++
++static void perf_mark_start(void)
++{
++	rfbi.perf_start_time = ktime_get();
++}
++
++static void perf_show(const char *name)
++{
++	ktime_t t, setup_time, trans_time;
++	u32 total_bytes;
++	u32 setup_us, trans_us, total_us;
++
++	t = ktime_get();
++
++	setup_time = ktime_sub(rfbi.perf_start_time, rfbi.perf_setup_time);
++	setup_us = (u32)ktime_to_us(setup_time);
++	if (setup_us == 0)
++		setup_us = 1;
++
++	trans_time = ktime_sub(t, rfbi.perf_start_time);
++	trans_us = (u32)ktime_to_us(trans_time);
++	if (trans_us == 0)
++		trans_us = 1;
++
++	total_us = setup_us + trans_us;
++
++	total_bytes = rfbi.perf_bytes;
++
++	DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
++			"%u kbytes/sec\n",
++			name,
++			setup_us,
++			trans_us,
++			total_us,
++			1000*1000 / total_us,
++			total_bytes,
++			total_bytes * 1000 / total_us);
++}
++#else
++#define perf_mark_setup()
++#define perf_mark_start()
++#define perf_show(x)
++#endif
++
++void rfbi_transfer_area(u16 width, u16 height,
++			     void (callback)(void *data), void *data)
++{
++	u32 l;
++
++	/*BUG_ON(callback == 0);*/
++	BUG_ON(rfbi.framedone_callback != NULL);
++
++	DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
++
++	dispc_set_lcd_size(width, height);
++
++	dispc_enable_lcd_out(1);
++
++	rfbi.framedone_callback = callback;
++	rfbi.framedone_callback_data = data;
++
++	rfbi_enable_clocks(1);
++
++	rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
++
++	l = rfbi_read_reg(RFBI_CONTROL);
++	l = FLD_MOD(l, 1, 0, 0); /* enable */
++	if (!rfbi.te_enabled)
++		l = FLD_MOD(l, 1, 4, 4); /* ITE */
++
++	perf_mark_start();
++
++	rfbi_write_reg(RFBI_CONTROL, l);
++}
++
++static void framedone_callback(void *data, u32 mask)
++{
++	void (*callback)(void *data);
++
++	DSSDBG("FRAMEDONE\n");
++
++	perf_show("DISPC");
++
++	REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
++
++	rfbi_enable_clocks(0);
++
++	callback = rfbi.framedone_callback;
++	rfbi.framedone_callback = NULL;
++
++	/*callback(rfbi.framedone_callback_data);*/
++
++	atomic_set(&rfbi.cmd_pending, 0);
++
++	process_cmd_fifo();
++}
++
++#if 1 /* VERBOSE */
++static void rfbi_print_timings(void)
++{
++	u32 l;
++	u32 time;
++
++	l = rfbi_read_reg(RFBI_CONFIG(0));
++	time = 1000000000 / rfbi.l4_khz;
++	if (l & (1 << 4))
++		time *= 2;
++
++	DSSDBG("Tick time %u ps\n", time);
++	l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
++	DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
++		"REONTIME %d, REOFFTIME %d\n",
++		l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
++		(l >> 20) & 0x0f, (l >> 24) & 0x3f);
++
++	l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
++	DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
++		"ACCESSTIME %d\n",
++		(l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
++		(l >> 22) & 0x3f);
++}
++#else
++static void rfbi_print_timings(void) {}
++#endif
++
++
++
++
++static u32 extif_clk_period;
++
++static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
++{
++	int bus_tick = extif_clk_period * div;
++	return (ps + bus_tick - 1) / bus_tick * bus_tick;
++}
++
++static int calc_reg_timing(struct rfbi_timings *t, int div)
++{
++	t->clk_div = div;
++
++	t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
++
++	t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
++	t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
++	t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
++
++	t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
++	t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
++	t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
++
++	t->access_time = round_to_extif_ticks(t->access_time, div);
++	t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
++	t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
++
++	DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
++	       t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
++	DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
++	       t->we_on_time, t->we_off_time, t->re_cycle_time,
++	       t->we_cycle_time);
++	DSSDBG("[reg]rdaccess %d cspulse %d\n",
++	       t->access_time, t->cs_pulse_width);
++
++	return rfbi_convert_timings(t);
++}
++
++static int calc_extif_timings(struct rfbi_timings *t)
++{
++	u32 max_clk_div;
++	int div;
++
++	rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
++	for (div = 1; div <= max_clk_div; div++) {
++		if (calc_reg_timing(t, div) == 0)
++			break;
++	}
++
++	if (div <= max_clk_div)
++		return 0;
++
++	DSSERR("can't setup timings\n");
++	return -1;
++}
++
++
++void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
++{
++	int r;
++
++	if (!t->converted) {
++		r = calc_extif_timings(t);
++		if (r < 0)
++			DSSERR("Failed to calc timings\n");
++	}
++
++	BUG_ON(!t->converted);
++
++	rfbi_enable_clocks(1);
++	rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
++	rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
++
++	/* TIMEGRANULARITY */
++	REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
++		    (t->tim[2] ? 1 : 0), 4, 4);
++
++	rfbi_print_timings();
++	rfbi_enable_clocks(0);
++}
++
++static int ps_to_rfbi_ticks(int time, int div)
++{
++	unsigned long tick_ps;
++	int ret;
++
++	/* Calculate in picosecs to yield more exact results */
++	tick_ps = 1000000000 / (rfbi.l4_khz) * div;
++
++	ret = (time + tick_ps - 1) / tick_ps;
++
++	return ret;
++}
++
++#ifdef OMAP_RFBI_RATE_LIMIT
++unsigned long rfbi_get_max_tx_rate(void)
++{
++	unsigned long   l4_rate, dss1_rate;
++	int             min_l4_ticks = 0;
++	int             i;
++
++	/* According to TI this can't be calculated so make the
++	 * adjustments for a couple of known frequencies and warn for
++	 * others.
++	 */
++	static const struct {
++		unsigned long l4_clk;           /* HZ */
++		unsigned long dss1_clk;         /* HZ */
++		unsigned long min_l4_ticks;
++	} ftab[] = {
++		{ 55,   132,    7, },           /* 7.86 MPix/s */
++		{ 110,  110,    12, },          /* 9.16 MPix/s */
++		{ 110,  132,    10, },          /* 11   Mpix/s */
++		{ 120,  120,    10, },          /* 12   Mpix/s */
++		{ 133,  133,    10, },          /* 13.3 Mpix/s */
++	};
++
++	l4_rate = rfbi.l4_khz / 1000;
++	dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
++
++	for (i = 0; i < ARRAY_SIZE(ftab); i++) {
++		/* Use a window instead of an exact match, to account
++		 * for different DPLL multiplier / divider pairs.
++		 */
++		if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
++		    abs(ftab[i].dss1_clk - dss1_rate) < 3) {
++			min_l4_ticks = ftab[i].min_l4_ticks;
++			break;
++		}
++	}
++	if (i == ARRAY_SIZE(ftab)) {
++		/* Can't be sure, return anyway the maximum not
++		 * rate-limited. This might cause a problem only for the
++		 * tearing synchronisation.
++		 */
++		DSSERR("can't determine maximum RFBI transfer rate\n");
++		return rfbi.l4_khz * 1000;
++	}
++	return rfbi.l4_khz * 1000 / min_l4_ticks;
++}
++#else
++int rfbi_get_max_tx_rate(void)
++{
++	return rfbi.l4_khz * 1000;
++}
++#endif
++
++static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
++{
++	*clk_period = 1000000000 / rfbi.l4_khz;
++	*max_clk_div = 2;
++}
++
++static int rfbi_convert_timings(struct rfbi_timings *t)
++{
++	u32 l;
++	int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
++	int actim, recyc, wecyc;
++	int div = t->clk_div;
++
++	if (div <= 0 || div > 2)
++		return -1;
++
++	/* Make sure that after conversion it still holds that:
++	 * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
++	 * csoff > cson, csoff >= max(weoff, reoff), actim > reon
++	 */
++	weon = ps_to_rfbi_ticks(t->we_on_time, div);
++	weoff = ps_to_rfbi_ticks(t->we_off_time, div);
++	if (weoff <= weon)
++		weoff = weon + 1;
++	if (weon > 0x0f)
++		return -1;
++	if (weoff > 0x3f)
++		return -1;
++
++	reon = ps_to_rfbi_ticks(t->re_on_time, div);
++	reoff = ps_to_rfbi_ticks(t->re_off_time, div);
++	if (reoff <= reon)
++		reoff = reon + 1;
++	if (reon > 0x0f)
++		return -1;
++	if (reoff > 0x3f)
++		return -1;
++
++	cson = ps_to_rfbi_ticks(t->cs_on_time, div);
++	csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
++	if (csoff <= cson)
++		csoff = cson + 1;
++	if (csoff < max(weoff, reoff))
++		csoff = max(weoff, reoff);
++	if (cson > 0x0f)
++		return -1;
++	if (csoff > 0x3f)
++		return -1;
++
++	l =  cson;
++	l |= csoff << 4;
++	l |= weon  << 10;
++	l |= weoff << 14;
++	l |= reon  << 20;
++	l |= reoff << 24;
++
++	t->tim[0] = l;
++
++	actim = ps_to_rfbi_ticks(t->access_time, div);
++	if (actim <= reon)
++		actim = reon + 1;
++	if (actim > 0x3f)
++		return -1;
++
++	wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
++	if (wecyc < weoff)
++		wecyc = weoff;
++	if (wecyc > 0x3f)
++		return -1;
++
++	recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
++	if (recyc < reoff)
++		recyc = reoff;
++	if (recyc > 0x3f)
++		return -1;
++
++	cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
++	if (cs_pulse > 0x3f)
++		return -1;
++
++	l =  wecyc;
++	l |= recyc    << 6;
++	l |= cs_pulse << 12;
++	l |= actim    << 22;
++
++	t->tim[1] = l;
++
++	t->tim[2] = div - 1;
++
++	t->converted = 1;
++
++	return 0;
++}
++
++/* xxx FIX module selection missing */
++int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
++			     unsigned hs_pulse_time, unsigned vs_pulse_time,
++			     int hs_pol_inv, int vs_pol_inv, int extif_div)
++{
++	int hs, vs;
++	int min;
++	u32 l;
++
++	hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
++	vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
++	if (hs < 2)
++		return -EDOM;
++	if (mode == OMAP_DSS_RFBI_TE_MODE_2)
++		min = 2;
++	else /* OMAP_DSS_RFBI_TE_MODE_1 */
++		min = 4;
++	if (vs < min)
++		return -EDOM;
++	if (vs == hs)
++		return -EINVAL;
++	rfbi.te_mode = mode;
++	DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
++		mode, hs, vs, hs_pol_inv, vs_pol_inv);
++
++	rfbi_enable_clocks(1);
++	rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
++	rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
++
++	l = rfbi_read_reg(RFBI_CONFIG(0));
++	if (hs_pol_inv)
++		l &= ~(1 << 21);
++	else
++		l |= 1 << 21;
++	if (vs_pol_inv)
++		l &= ~(1 << 20);
++	else
++		l |= 1 << 20;
++	rfbi_enable_clocks(0);
++
++	return 0;
++}
++EXPORT_SYMBOL(omap_rfbi_setup_te);
++
++/* xxx FIX module selection missing */
++int omap_rfbi_enable_te(bool enable, unsigned line)
++{
++	u32 l;
++
++	DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
++	if (line > (1 << 11) - 1)
++		return -EINVAL;
++
++	rfbi_enable_clocks(1);
++	l = rfbi_read_reg(RFBI_CONFIG(0));
++	l &= ~(0x3 << 2);
++	if (enable) {
++		rfbi.te_enabled = 1;
++		l |= rfbi.te_mode << 2;
++	} else
++		rfbi.te_enabled = 0;
++	rfbi_write_reg(RFBI_CONFIG(0), l);
++	rfbi_write_reg(RFBI_LINE_NUMBER, line);
++	rfbi_enable_clocks(0);
++
++	return 0;
++}
++EXPORT_SYMBOL(omap_rfbi_enable_te);
++
++#if 0
++static void rfbi_enable_config(int enable1, int enable2)
++{
++	u32 l;
++	int cs = 0;
++
++	if (enable1)
++		cs |= 1<<0;
++	if (enable2)
++		cs |= 1<<1;
++
++	rfbi_enable_clocks(1);
++
++	l = rfbi_read_reg(RFBI_CONTROL);
++
++	l = FLD_MOD(l, cs, 3, 2);
++	l = FLD_MOD(l, 0, 1, 1);
++
++	rfbi_write_reg(RFBI_CONTROL, l);
++
++
++	l = rfbi_read_reg(RFBI_CONFIG(0));
++	l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
++	/*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
++	/*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
++
++	l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
++	l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
++	l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
++
++	l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
++	rfbi_write_reg(RFBI_CONFIG(0), l);
++
++	rfbi_enable_clocks(0);
++}
++#endif
++
++int rfbi_configure(int rfbi_module, int bpp, int lines)
++{
++	u32 l;
++	int cycle1 = 0, cycle2 = 0, cycle3 = 0;
++	enum omap_rfbi_cycleformat cycleformat;
++	enum omap_rfbi_datatype datatype;
++	enum omap_rfbi_parallelmode parallelmode;
++
++	switch (bpp) {
++	case 12:
++		datatype = OMAP_DSS_RFBI_DATATYPE_12;
++		break;
++	case 16:
++		datatype = OMAP_DSS_RFBI_DATATYPE_16;
++		break;
++	case 18:
++		datatype = OMAP_DSS_RFBI_DATATYPE_18;
++		break;
++	case 24:
++		datatype = OMAP_DSS_RFBI_DATATYPE_24;
++		break;
++	default:
++		BUG();
++		return 1;
++	}
++	rfbi.datatype = datatype;
++
++	switch (lines) {
++	case 8:
++		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
++		break;
++	case 9:
++		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
++		break;
++	case 12:
++		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
++		break;
++	case 16:
++		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
++		break;
++	default:
++		BUG();
++		return 1;
++	}
++	rfbi.parallelmode = parallelmode;
++
++	if ((bpp % lines) == 0) {
++		switch (bpp / lines) {
++		case 1:
++			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
++			break;
++		case 2:
++			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
++			break;
++		case 3:
++			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
++			break;
++		default:
++			BUG();
++			return 1;
++		}
++	} else if ((2 * bpp % lines) == 0) {
++		if ((2 * bpp / lines) == 3)
++			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
++		else {
++			BUG();
++			return 1;
++		}
++	} else {
++		BUG();
++		return 1;
++	}
++
++	switch (cycleformat) {
++	case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
++		cycle1 = lines;
++		break;
++
++	case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
++		cycle1 = lines;
++		cycle2 = lines;
++		break;
++
++	case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
++		cycle1 = lines;
++		cycle2 = lines;
++		cycle3 = lines;
++		break;
++
++	case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
++		cycle1 = lines;
++		cycle2 = (lines / 2) | ((lines / 2) << 16);
++		cycle3 = (lines << 16);
++		break;
++	}
++
++	rfbi_enable_clocks(1);
++
++	REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
++
++	l = 0;
++	l |= FLD_VAL(parallelmode, 1, 0);
++	l |= FLD_VAL(0, 3, 2);		/* TRIGGERMODE: ITE */
++	l |= FLD_VAL(0, 4, 4);		/* TIMEGRANULARITY */
++	l |= FLD_VAL(datatype, 6, 5);
++	/* l |= FLD_VAL(2, 8, 7); */	/* L4FORMAT, 2pix/L4 */
++	l |= FLD_VAL(0, 8, 7);	/* L4FORMAT, 1pix/L4 */
++	l |= FLD_VAL(cycleformat, 10, 9);
++	l |= FLD_VAL(0, 12, 11);	/* UNUSEDBITS */
++	l |= FLD_VAL(0, 16, 16);	/* A0POLARITY */
++	l |= FLD_VAL(0, 17, 17);	/* REPOLARITY */
++	l |= FLD_VAL(0, 18, 18);	/* WEPOLARITY */
++	l |= FLD_VAL(0, 19, 19);	/* CSPOLARITY */
++	l |= FLD_VAL(1, 20, 20);	/* TE_VSYNC_POLARITY */
++	l |= FLD_VAL(1, 21, 21);	/* HSYNCPOLARITY */
++	rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
++
++	rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
++	rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
++	rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
++
++
++	l = rfbi_read_reg(RFBI_CONTROL);
++	l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
++	l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
++	rfbi_write_reg(RFBI_CONTROL, l);
++
++
++	DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
++	       bpp, lines, cycle1, cycle2, cycle3);
++
++	rfbi_enable_clocks(0);
++
++	return 0;
++}
++EXPORT_SYMBOL(rfbi_configure);
++
++static int rfbi_find_display(struct omap_display *disp)
++{
++	if (disp == rfbi.display[0])
++		return 0;
++
++	if (disp == rfbi.display[1])
++		return 1;
++
++	BUG();
++	return -1;
++}
++
++
++static void signal_fifo_waiters(void)
++{
++	if (atomic_read(&rfbi.cmd_fifo_full) > 0) {
++		/* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */
++		complete(&rfbi.cmd_done);
++		atomic_dec(&rfbi.cmd_fifo_full);
++	}
++}
++
++/* returns 1 for async op, and 0 for sync op */
++static int do_update(struct omap_display *display, struct update_region *upd)
++{
++	u16 x = upd->x;
++	u16 y = upd->y;
++	u16 w = upd->w;
++	u16 h = upd->h;
++
++	perf_mark_setup();
++
++	if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++		/*display->ctrl->enable_te(display, 1); */
++		dispc_setup_partial_planes(display, &x, &y, &w, &h);
++	}
++
++#ifdef MEASURE_PERF
++	rfbi.perf_bytes = w * h * 2; /* XXX always 16bit */
++#endif
++
++	display->ctrl->setup_update(display, x, y, w, h);
++
++	if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++		rfbi_transfer_area(w, h, NULL, NULL);
++		return 1;
++	} else {
++		struct omap_overlay *ovl;
++		void __iomem *addr;
++		int scr_width;
++
++		ovl = display->manager->overlays[0];
++		scr_width = ovl->info.screen_width;
++		addr = ovl->info.vaddr;
++
++		omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
++
++		perf_show("L4");
++
++		return 0;
++	}
++}
++
++static void process_cmd_fifo(void)
++{
++	int len;
++	struct update_param p;
++	struct omap_display *display;
++	unsigned long flags;
++
++	if (atomic_inc_return(&rfbi.cmd_pending) != 1)
++		return;
++
++	while (true) {
++		spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
++
++		len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p,
++				  sizeof(struct update_param));
++		if (len == 0) {
++			DSSDBG("nothing more in fifo\n");
++			atomic_set(&rfbi.cmd_pending, 0);
++			spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++			break;
++		}
++
++		/* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/
++
++		spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++
++		BUG_ON(len != sizeof(struct update_param));
++		BUG_ON(p.rfbi_module > 1);
++
++		display = rfbi.display[p.rfbi_module];
++
++		if (p.cmd == RFBI_CMD_UPDATE) {
++			if (do_update(display, &p.par.r))
++				break; /* async op */
++		} else if (p.cmd == RFBI_CMD_SYNC) {
++			DSSDBG("Signaling SYNC done!\n");
++			complete(p.par.sync);
++		} else
++			BUG();
++	}
++
++	signal_fifo_waiters();
++}
++
++static void rfbi_push_cmd(struct update_param *p)
++{
++	int ret;
++
++	while (1) {
++		unsigned long flags;
++		int available;
++
++		spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
++		available = RFBI_CMD_FIFO_LEN_BYTES -
++			__kfifo_len(rfbi.cmd_fifo);
++
++/*		DSSDBG("%d bytes left in fifo\n", available); */
++		if (available < sizeof(struct update_param)) {
++			DSSDBG("Going to wait because FIFO FULL..\n");
++			spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++			atomic_inc(&rfbi.cmd_fifo_full);
++			wait_for_completion(&rfbi.cmd_done);
++			/*DSSDBG("Woke up because fifo not full anymore\n");*/
++			continue;
++		}
++
++		ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p,
++				  sizeof(struct update_param));
++/*		DSSDBG("pushed %d bytes\n", ret);*/
++
++		spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++
++		BUG_ON(ret != sizeof(struct update_param));
++
++		break;
++	}
++}
++
++static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h)
++{
++	struct update_param p;
++
++	p.rfbi_module = rfbi_module;
++	p.cmd = RFBI_CMD_UPDATE;
++
++	p.par.r.x = x;
++	p.par.r.y = y;
++	p.par.r.w = w;
++	p.par.r.h = h;
++
++	DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h);
++
++	rfbi_push_cmd(&p);
++
++	process_cmd_fifo();
++}
++
++static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp)
++{
++	struct update_param p;
++
++	p.rfbi_module = rfbi_module;
++	p.cmd = RFBI_CMD_SYNC;
++	p.par.sync = sync_comp;
++
++	rfbi_push_cmd(&p);
++
++	DSSDBG("RFBI sync pushed to cmd fifo\n");
++
++	process_cmd_fifo();
++}
++
++void rfbi_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	DUMPREG(RFBI_REVISION);
++	DUMPREG(RFBI_SYSCONFIG);
++	DUMPREG(RFBI_SYSSTATUS);
++	DUMPREG(RFBI_CONTROL);
++	DUMPREG(RFBI_PIXEL_CNT);
++	DUMPREG(RFBI_LINE_NUMBER);
++	DUMPREG(RFBI_CMD);
++	DUMPREG(RFBI_PARAM);
++	DUMPREG(RFBI_DATA);
++	DUMPREG(RFBI_READ);
++	DUMPREG(RFBI_STATUS);
++
++	DUMPREG(RFBI_CONFIG(0));
++	DUMPREG(RFBI_ONOFF_TIME(0));
++	DUMPREG(RFBI_CYCLE_TIME(0));
++	DUMPREG(RFBI_DATA_CYCLE1(0));
++	DUMPREG(RFBI_DATA_CYCLE2(0));
++	DUMPREG(RFBI_DATA_CYCLE3(0));
++
++	DUMPREG(RFBI_CONFIG(1));
++	DUMPREG(RFBI_ONOFF_TIME(1));
++	DUMPREG(RFBI_CYCLE_TIME(1));
++	DUMPREG(RFBI_DATA_CYCLE1(1));
++	DUMPREG(RFBI_DATA_CYCLE2(1));
++	DUMPREG(RFBI_DATA_CYCLE3(1));
++
++	DUMPREG(RFBI_VSYNC_WIDTH);
++	DUMPREG(RFBI_HSYNC_WIDTH);
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++int rfbi_init(void)
++{
++	u32 rev;
++	u32 l;
++
++	spin_lock_init(&rfbi.cmd_lock);
++	rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL,
++				    &rfbi.cmd_lock);
++	if (IS_ERR(rfbi.cmd_fifo))
++		return -ENOMEM;
++
++	init_completion(&rfbi.cmd_done);
++	atomic_set(&rfbi.cmd_fifo_full, 0);
++	atomic_set(&rfbi.cmd_pending, 0);
++
++	rfbi.base = ioremap(RFBI_BASE, SZ_256);
++	if (!rfbi.base) {
++		DSSERR("can't ioremap RFBI\n");
++		return -ENOMEM;
++	}
++
++	rfbi_enable_clocks(1);
++
++	msleep(10);
++
++	rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
++
++	/* Enable autoidle and smart-idle */
++	l = rfbi_read_reg(RFBI_SYSCONFIG);
++	l |= (1 << 0) | (2 << 3);
++	rfbi_write_reg(RFBI_SYSCONFIG, l);
++
++	rev = rfbi_read_reg(RFBI_REVISION);
++	printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
++	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++	rfbi_enable_clocks(0);
++
++	return 0;
++}
++
++void rfbi_exit(void)
++{
++	DSSDBG("rfbi_exit\n");
++
++	kfifo_free(rfbi.cmd_fifo);
++
++	iounmap(rfbi.base);
++}
++
++/* struct omap_display support */
++static int rfbi_display_update(struct omap_display *display,
++			u16 x, u16 y, u16 w, u16 h)
++{
++	int rfbi_module;
++
++	if (w == 0 || h == 0)
++		return 0;
++
++	rfbi_module = rfbi_find_display(display);
++
++	rfbi_push_update(rfbi_module, x, y, w, h);
++
++	return 0;
++}
++
++static int rfbi_display_sync(struct omap_display *display)
++{
++	struct completion sync_comp;
++	int rfbi_module;
++
++	rfbi_module = rfbi_find_display(display);
++
++	init_completion(&sync_comp);
++	rfbi_push_sync(rfbi_module, &sync_comp);
++	DSSDBG("Waiting for SYNC to happen...\n");
++	wait_for_completion(&sync_comp);
++	DSSDBG("Released from SYNC\n");
++	return 0;
++}
++
++static int rfbi_display_enable_te(struct omap_display *display, bool enable)
++{
++	display->ctrl->enable_te(display, enable);
++	return 0;
++}
++
++static int rfbi_display_enable(struct omap_display *display)
++{
++	int r;
++
++	BUG_ON(display->panel == NULL || display->ctrl == NULL);
++
++	r = omap_dispc_register_isr(framedone_callback, NULL,
++			DISPC_IRQ_FRAMEDONE);
++	if (r) {
++		DSSERR("can't get FRAMEDONE irq\n");
++		return r;
++	}
++
++	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++
++	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
++
++	dispc_set_tft_data_lines(display->ctrl->pixel_size);
++
++	rfbi_configure(display->hw_config.u.rfbi.channel,
++			       display->ctrl->pixel_size,
++			       display->hw_config.u.rfbi.data_lines);
++
++	rfbi_set_timings(display->hw_config.u.rfbi.channel,
++			 &display->ctrl->timings);
++
++
++	if (display->ctrl && display->ctrl->enable) {
++		r = display->ctrl->enable(display);
++		if (r)
++			goto err;
++	}
++
++	if (display->panel && display->panel->enable) {
++		r = display->panel->enable(display);
++		if (r)
++			goto err;
++	}
++
++	return 0;
++err:
++	return -ENODEV;
++}
++
++static void rfbi_display_disable(struct omap_display *display)
++{
++	display->ctrl->disable(display);
++	omap_dispc_unregister_isr(framedone_callback, NULL,
++			DISPC_IRQ_FRAMEDONE);
++}
++
++void rfbi_init_display(struct omap_display *display)
++{
++	display->enable = rfbi_display_enable;
++	display->disable = rfbi_display_disable;
++	display->update = rfbi_display_update;
++	display->sync = rfbi_display_sync;
++	display->enable_te = rfbi_display_enable_te;
++
++	rfbi.display[display->hw_config.u.rfbi.channel] = display;
++
++	display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++}
+diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
+new file mode 100644
+index 0000000..fbff2b2
+--- /dev/null
++++ b/drivers/video/omap2/dss/sdi.c
+@@ -0,0 +1,245 @@
++/*
++ * linux/drivers/video/omap2/dss/sdi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "SDI"
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++
++static struct {
++	bool skip_init;
++	bool update_enabled;
++} sdi;
++
++static void sdi_basic_init(void)
++{
++	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
++
++	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++	dispc_set_tft_data_lines(24);
++	dispc_lcd_enable_signal_polarity(1);
++}
++
++static int sdi_display_enable(struct omap_display *display)
++{
++	struct dispc_clock_info cinfo;
++	u16 lck_div, pck_div;
++	unsigned long fck;
++	struct omap_panel *panel = display->panel;
++	unsigned long pck;
++	int r;
++
++	if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++		DSSERR("display already enabled\n");
++		return -EINVAL;
++	}
++
++	/* In case of skip_init sdi_init has already enabled the clocks */
++	if (!sdi.skip_init)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	sdi_basic_init();
++
++	/* 15.5.9.1.2 */
++	panel->config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
++
++	dispc_set_pol_freq(panel);
++
++	if (!sdi.skip_init)
++		r = dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000,
++				&cinfo);
++	else
++		r = dispc_get_clock_div(&cinfo);
++
++	if (r)
++		goto err0;
++
++	fck = cinfo.fck;
++	lck_div = cinfo.lck_div;
++	pck_div = cinfo.pck_div;
++
++	pck = fck / lck_div / pck_div / 1000;
++
++	if (pck != panel->timings.pixel_clock) {
++		DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
++				"got %lu kHz\n",
++				panel->timings.pixel_clock, pck);
++
++		panel->timings.pixel_clock = pck;
++	}
++
++
++	dispc_set_lcd_timings(&panel->timings);
++
++	r = dispc_set_clock_div(&cinfo);
++	if (r)
++		goto err1;
++
++	if (!sdi.skip_init) {
++		dss_sdi_init(display->hw_config.u.sdi.datapairs);
++		dss_sdi_enable();
++		mdelay(2);
++	}
++
++	dispc_enable_lcd_out(1);
++
++	r = panel->enable(display);
++	if (r)
++		goto err2;
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	sdi.skip_init = 0;
++
++	return 0;
++err2:
++	dispc_enable_lcd_out(0);
++err1:
++err0:
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	return r;
++}
++
++static int sdi_display_resume(struct omap_display *display);
++
++static void sdi_display_disable(struct omap_display *display)
++{
++	if (display->state == OMAP_DSS_DISPLAY_DISABLED)
++		return;
++
++	if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
++		sdi_display_resume(display);
++
++	display->panel->disable(display);
++
++	dispc_enable_lcd_out(0);
++
++	dss_sdi_disable();
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++}
++
++static int sdi_display_suspend(struct omap_display *display)
++{
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return -EINVAL;
++
++	if (display->panel->suspend)
++		display->panel->suspend(display);
++
++	dispc_enable_lcd_out(0);
++
++	dss_sdi_disable();
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	display->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++	return 0;
++}
++
++static int sdi_display_resume(struct omap_display *display)
++{
++	if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
++		return -EINVAL;
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	dss_sdi_enable();
++	mdelay(2);
++
++	dispc_enable_lcd_out(1);
++
++	if (display->panel->resume)
++		display->panel->resume(display);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	return 0;
++}
++
++static int sdi_display_set_update_mode(struct omap_display *display,
++		enum omap_dss_update_mode mode)
++{
++	if (mode == OMAP_DSS_UPDATE_MANUAL)
++		return -EINVAL;
++
++	if (mode == OMAP_DSS_UPDATE_DISABLED) {
++		dispc_enable_lcd_out(0);
++		sdi.update_enabled = 0;
++	} else {
++		dispc_enable_lcd_out(1);
++		sdi.update_enabled = 1;
++	}
++
++	return 0;
++}
++
++static enum omap_dss_update_mode sdi_display_get_update_mode(
++		struct omap_display *display)
++{
++	return sdi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
++		OMAP_DSS_UPDATE_DISABLED;
++}
++
++static void sdi_get_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	*timings = display->panel->timings;
++}
++
++void sdi_init_display(struct omap_display *display)
++{
++	DSSDBG("SDI init\n");
++
++	display->enable = sdi_display_enable;
++	display->disable = sdi_display_disable;
++	display->suspend = sdi_display_suspend;
++	display->resume = sdi_display_resume;
++	display->set_update_mode = sdi_display_set_update_mode;
++	display->get_update_mode = sdi_display_get_update_mode;
++	display->get_timings = sdi_get_timings;
++}
++
++int sdi_init(bool skip_init)
++{
++	/* we store this for first display enable, then clear it */
++	sdi.skip_init = skip_init;
++
++	/*
++	 * Enable clocks already here, otherwise there would be a toggle
++	 * of them until sdi_display_enable is called.
++	 */
++	if (skip_init)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	return 0;
++}
++
++void sdi_exit(void)
++{
++}
+diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
+new file mode 100644
+index 0000000..aceed9f
+--- /dev/null
++++ b/drivers/video/omap2/dss/venc.c
+@@ -0,0 +1,600 @@
++/*
++ * linux/drivers/video/omap2/dss/venc.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * VENC settings from TI's DSS driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "VENC"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/mutex.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++#include <linux/string.h>
++
++#include <mach/display.h>
++#include <mach/cpu.h>
++
++#include "dss.h"
++
++#define VENC_BASE	0x48050C00
++
++/* Venc registers */
++#define VENC_REV_ID				0x00
++#define VENC_STATUS				0x04
++#define VENC_F_CONTROL				0x08
++#define VENC_VIDOUT_CTRL			0x10
++#define VENC_SYNC_CTRL				0x14
++#define VENC_LLEN				0x1C
++#define VENC_FLENS				0x20
++#define VENC_HFLTR_CTRL				0x24
++#define VENC_CC_CARR_WSS_CARR			0x28
++#define VENC_C_PHASE				0x2C
++#define VENC_GAIN_U				0x30
++#define VENC_GAIN_V				0x34
++#define VENC_GAIN_Y				0x38
++#define VENC_BLACK_LEVEL			0x3C
++#define VENC_BLANK_LEVEL			0x40
++#define VENC_X_COLOR				0x44
++#define VENC_M_CONTROL				0x48
++#define VENC_BSTAMP_WSS_DATA			0x4C
++#define VENC_S_CARR				0x50
++#define VENC_LINE21				0x54
++#define VENC_LN_SEL				0x58
++#define VENC_L21__WC_CTL			0x5C
++#define VENC_HTRIGGER_VTRIGGER			0x60
++#define VENC_SAVID__EAVID			0x64
++#define VENC_FLEN__FAL				0x68
++#define VENC_LAL__PHASE_RESET			0x6C
++#define VENC_HS_INT_START_STOP_X		0x70
++#define VENC_HS_EXT_START_STOP_X		0x74
++#define VENC_VS_INT_START_X			0x78
++#define VENC_VS_INT_STOP_X__VS_INT_START_Y	0x7C
++#define VENC_VS_INT_STOP_Y__VS_EXT_START_X	0x80
++#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y	0x84
++#define VENC_VS_EXT_STOP_Y			0x88
++#define VENC_AVID_START_STOP_X			0x90
++#define VENC_AVID_START_STOP_Y			0x94
++#define VENC_FID_INT_START_X__FID_INT_START_Y	0xA0
++#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X	0xA4
++#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y	0xA8
++#define VENC_TVDETGP_INT_START_STOP_X		0xB0
++#define VENC_TVDETGP_INT_START_STOP_Y		0xB4
++#define VENC_GEN_CTRL				0xB8
++#define VENC_OUTPUT_CONTROL			0xC4
++#define VENC_DAC_B__DAC_C			0xC8
++
++struct venc_config {
++	u32 f_control;
++	u32 vidout_ctrl;
++	u32 sync_ctrl;
++	u32 llen;
++	u32 flens;
++	u32 hfltr_ctrl;
++	u32 cc_carr_wss_carr;
++	u32 c_phase;
++	u32 gain_u;
++	u32 gain_v;
++	u32 gain_y;
++	u32 black_level;
++	u32 blank_level;
++	u32 x_color;
++	u32 m_control;
++	u32 bstamp_wss_data;
++	u32 s_carr;
++	u32 line21;
++	u32 ln_sel;
++	u32 l21__wc_ctl;
++	u32 htrigger_vtrigger;
++	u32 savid__eavid;
++	u32 flen__fal;
++	u32 lal__phase_reset;
++	u32 hs_int_start_stop_x;
++	u32 hs_ext_start_stop_x;
++	u32 vs_int_start_x;
++	u32 vs_int_stop_x__vs_int_start_y;
++	u32 vs_int_stop_y__vs_ext_start_x;
++	u32 vs_ext_stop_x__vs_ext_start_y;
++	u32 vs_ext_stop_y;
++	u32 avid_start_stop_x;
++	u32 avid_start_stop_y;
++	u32 fid_int_start_x__fid_int_start_y;
++	u32 fid_int_offset_y__fid_ext_start_x;
++	u32 fid_ext_start_y__fid_ext_offset_y;
++	u32 tvdetgp_int_start_stop_x;
++	u32 tvdetgp_int_start_stop_y;
++	u32 gen_ctrl;
++};
++
++/* from TRM */
++static const struct venc_config venc_config_pal_trm = {
++	.f_control				= 0,
++	.vidout_ctrl				= 1,
++	.sync_ctrl				= 0x40,
++	.llen					= 0x35F, /* 863 */
++	.flens					= 0x270, /* 624 */
++	.hfltr_ctrl				= 0,
++	.cc_carr_wss_carr			= 0x2F7225ED,
++	.c_phase				= 0,
++	.gain_u					= 0x111,
++	.gain_v					= 0x181,
++	.gain_y					= 0x140,
++	.black_level				= 0x3B,
++	.blank_level				= 0x3B,
++	.x_color				= 0x7,
++	.m_control				= 0x2,
++	.bstamp_wss_data			= 0x3F,
++	.s_carr					= 0x2A098ACB,
++	.line21					= 0,
++	.ln_sel					= 0x01290015,
++	.l21__wc_ctl				= 0x0000F603,
++	.htrigger_vtrigger			= 0,
++
++	.savid__eavid				= 0x06A70108,
++	.flen__fal				= 0x00180270,
++	.lal__phase_reset			= 0x00040135,
++	.hs_int_start_stop_x			= 0x00880358,
++	.hs_ext_start_stop_x			= 0x000F035F,
++	.vs_int_start_x				= 0x01A70000,
++	.vs_int_stop_x__vs_int_start_y		= 0x000001A7,
++	.vs_int_stop_y__vs_ext_start_x		= 0x01AF0000,
++	.vs_ext_stop_x__vs_ext_start_y		= 0x000101AF,
++	.vs_ext_stop_y				= 0x00000025,
++	.avid_start_stop_x			= 0x03530083,
++	.avid_start_stop_y			= 0x026C002E,
++	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
++	.fid_int_offset_y__fid_ext_start_x	= 0x002E0138,
++	.fid_ext_start_y__fid_ext_offset_y	= 0x01380001,
++
++	.tvdetgp_int_start_stop_x		= 0x00140001,
++	.tvdetgp_int_start_stop_y		= 0x00010001,
++	.gen_ctrl				= 0x00FF0000,
++};
++
++/* from TRM */
++static const struct venc_config venc_config_ntsc_trm = {
++	.f_control				= 0,
++	.vidout_ctrl				= 1,
++	.sync_ctrl				= 0x8040,
++	.llen					= 0x359,
++	.flens					= 0x20C,
++	.hfltr_ctrl				= 0,
++	.cc_carr_wss_carr			= 0x043F2631,
++	.c_phase				= 0,
++	.gain_u					= 0x102,
++	.gain_v					= 0x16C,
++	.gain_y					= 0x12F,
++	.black_level				= 0x43,
++	.blank_level				= 0x38,
++	.x_color				= 0x7,
++	.m_control				= 0x1,
++	.bstamp_wss_data			= 0x38,
++	.s_carr					= 0x21F07C1F,
++	.line21					= 0,
++	.ln_sel					= 0x01310011,
++	.l21__wc_ctl				= 0x0000F003,
++	.htrigger_vtrigger			= 0,
++
++	.savid__eavid				= 0x069300F4,
++	.flen__fal				= 0x0016020C,
++	.lal__phase_reset			= 0x00060107,
++	.hs_int_start_stop_x			= 0x008E0350,
++	.hs_ext_start_stop_x			= 0x000F0359,
++	.vs_int_start_x				= 0x01A00000,
++	.vs_int_stop_x__vs_int_start_y		= 0x020701A0,
++	.vs_int_stop_y__vs_ext_start_x		= 0x01AC0024,
++	.vs_ext_stop_x__vs_ext_start_y		= 0x020D01AC,
++	.vs_ext_stop_y				= 0x00000006,
++	.avid_start_stop_x			= 0x03480078,
++	.avid_start_stop_y			= 0x02060024,
++	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
++	.fid_int_offset_y__fid_ext_start_x	= 0x01AC0106,
++	.fid_ext_start_y__fid_ext_offset_y	= 0x01060006,
++
++	.tvdetgp_int_start_stop_x		= 0x00140001,
++	.tvdetgp_int_start_stop_y		= 0x00010001,
++	.gen_ctrl				= 0x00F90000,
++};
++
++static const struct venc_config venc_config_pal_bdghi = {
++	.f_control				= 0,
++	.vidout_ctrl				= 0,
++	.sync_ctrl				= 0,
++	.hfltr_ctrl				= 0,
++	.x_color				= 0,
++	.line21					= 0,
++	.ln_sel					= 21,
++	.htrigger_vtrigger			= 0,
++	.tvdetgp_int_start_stop_x		= 0x00140001,
++	.tvdetgp_int_start_stop_y		= 0x00010001,
++	.gen_ctrl				= 0x00FB0000,
++
++	.llen					= 864-1,
++	.flens					= 625-1,
++	.cc_carr_wss_carr			= 0x2F7625ED,
++	.c_phase				= 0xDF,
++	.gain_u					= 0x111,
++	.gain_v					= 0x181,
++	.gain_y					= 0x140,
++	.black_level				= 0x3e,
++	.blank_level				= 0x3e,
++	.m_control				= 0<<2 | 1<<1,
++	.bstamp_wss_data			= 0x42,
++	.s_carr					= 0x2a098acb,
++	.l21__wc_ctl				= 0<<13 | 0x16<<8 | 0<<0,
++	.savid__eavid				= 0x06A70108,
++	.flen__fal				= 23<<16 | 624<<0,
++	.lal__phase_reset			= 2<<17 | 310<<0,
++	.hs_int_start_stop_x			= 0x00920358,
++	.hs_ext_start_stop_x			= 0x000F035F,
++	.vs_int_start_x				= 0x1a7<<16,
++	.vs_int_stop_x__vs_int_start_y		= 0x000601A7,
++	.vs_int_stop_y__vs_ext_start_x		= 0x01AF0036,
++	.vs_ext_stop_x__vs_ext_start_y		= 0x27101af,
++	.vs_ext_stop_y				= 0x05,
++	.avid_start_stop_x			= 0x03530082,
++	.avid_start_stop_y			= 0x0270002E,
++	.fid_int_start_x__fid_int_start_y	= 0x0005008A,
++	.fid_int_offset_y__fid_ext_start_x	= 0x002E0138,
++	.fid_ext_start_y__fid_ext_offset_y	= 0x01380005,
++};
++
++const struct omap_video_timings omap_dss_pal_timings = {
++	.x_res = 720,
++	.y_res = 574,
++	.pixel_clock = 26181,
++	.hsw = 32,
++	.hfp = 80,
++	.hbp = 48,
++	.vsw = 7,
++	.vfp = 3,
++	.vbp = 6,
++};
++EXPORT_SYMBOL(omap_dss_pal_timings);
++
++const struct omap_video_timings omap_dss_ntsc_timings = {
++	.x_res = 720,
++	.y_res = 482,
++	.pixel_clock = 22153,
++	.hsw = 32,
++	.hfp = 80,
++	.hbp = 48,
++	.vsw = 10,
++	.vfp = 3,
++	.vbp = 6,
++};
++EXPORT_SYMBOL(omap_dss_ntsc_timings);
++
++static struct {
++	void __iomem *base;
++	struct mutex venc_lock;
++} venc;
++
++static struct omap_panel venc_panel = {
++	.name = "tv-out",
++};
++
++static inline void venc_write_reg(int idx, u32 val)
++{
++	__raw_writel(val, venc.base + idx);
++}
++
++static inline u32 venc_read_reg(int idx)
++{
++	u32 l = __raw_readl(venc.base + idx);
++	return l;
++}
++
++static void venc_write_config(const struct venc_config *config)
++{
++	DSSDBG("write venc conf\n");
++
++	venc_write_reg(VENC_LLEN, config->llen);
++	venc_write_reg(VENC_FLENS, config->flens);
++	venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
++	venc_write_reg(VENC_C_PHASE, config->c_phase);
++	venc_write_reg(VENC_GAIN_U, config->gain_u);
++	venc_write_reg(VENC_GAIN_V, config->gain_v);
++	venc_write_reg(VENC_GAIN_Y, config->gain_y);
++	venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
++	venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
++	venc_write_reg(VENC_M_CONTROL, config->m_control);
++	venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
++	venc_write_reg(VENC_S_CARR, config->s_carr);
++	venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
++	venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
++	venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
++	venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
++	venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
++	venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
++	venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
++	venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
++		       config->vs_int_stop_x__vs_int_start_y);
++	venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
++		       config->vs_int_stop_y__vs_ext_start_x);
++	venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
++		       config->vs_ext_stop_x__vs_ext_start_y);
++	venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
++	venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
++	venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
++	venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
++		       config->fid_int_start_x__fid_int_start_y);
++	venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
++		       config->fid_int_offset_y__fid_ext_start_x);
++	venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
++		       config->fid_ext_start_y__fid_ext_offset_y);
++
++	venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
++	venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
++	venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
++	venc_write_reg(VENC_X_COLOR, config->x_color);
++	venc_write_reg(VENC_LINE21, config->line21);
++	venc_write_reg(VENC_LN_SEL, config->ln_sel);
++	venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
++	venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
++		       config->tvdetgp_int_start_stop_x);
++	venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
++		       config->tvdetgp_int_start_stop_y);
++	venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
++	venc_write_reg(VENC_F_CONTROL, config->f_control);
++	venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
++}
++
++static void venc_reset(void)
++{
++	int t = 1000;
++
++	venc_write_reg(VENC_F_CONTROL, 1<<8);
++	while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
++		if (--t == 0) {
++			DSSERR("Failed to reset venc\n");
++			return;
++		}
++	}
++
++	/* the magical sleep that makes things work */
++	msleep(20);
++}
++
++static void venc_enable_clocks(int enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
++				DSS_CLK_96M);
++	else
++		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
++				DSS_CLK_96M);
++}
++
++static const struct venc_config *venc_timings_to_config(
++		struct omap_video_timings *timings)
++{
++	if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
++		return &venc_config_pal_trm;
++
++	if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
++		return &venc_config_ntsc_trm;
++
++	BUG();
++}
++
++int venc_init(void)
++{
++	u8 rev_id;
++
++	mutex_init(&venc.venc_lock);
++
++	venc_panel.timings = omap_dss_pal_timings;
++
++	venc.base = ioremap(VENC_BASE, SZ_1K);
++	if (!venc.base) {
++		DSSERR("can't ioremap VENC\n");
++		return -ENOMEM;
++	}
++
++	venc_enable_clocks(1);
++
++	rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
++	printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
++
++	venc_enable_clocks(0);
++
++	return 0;
++}
++
++void venc_exit(void)
++{
++	iounmap(venc.base);
++}
++
++static void venc_power_on(struct omap_display *display)
++{
++	venc_enable_clocks(1);
++
++	venc_reset();
++	venc_write_config(venc_timings_to_config(&display->panel->timings));
++
++	dss_set_venc_output(display->hw_config.u.venc.type);
++	dss_set_dac_pwrdn_bgz(1);
++
++	if (display->hw_config.u.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) {
++		if (cpu_is_omap24xx())
++			venc_write_reg(VENC_OUTPUT_CONTROL, 0x2);
++		else
++			venc_write_reg(VENC_OUTPUT_CONTROL, 0xa);
++	} else { /* S-Video */
++		venc_write_reg(VENC_OUTPUT_CONTROL, 0xd);
++	}
++
++	dispc_set_digit_size(display->panel->timings.x_res,
++			display->panel->timings.y_res/2);
++
++	if (display->hw_config.panel_enable)
++		display->hw_config.panel_enable(display);
++
++	dispc_enable_digit_out(1);
++}
++
++static void venc_power_off(struct omap_display *display)
++{
++	venc_write_reg(VENC_OUTPUT_CONTROL, 0);
++	dss_set_dac_pwrdn_bgz(0);
++
++	dispc_enable_digit_out(0);
++
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++
++	venc_enable_clocks(0);
++}
++
++static int venc_enable_display(struct omap_display *display)
++{
++	int r = 0;
++
++	DSSDBG("venc_enable_display\n");
++
++	mutex_lock(&venc.venc_lock);
++
++	if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	venc_power_on(display);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++err:
++	mutex_unlock(&venc.venc_lock);
++
++	return r;
++}
++
++static void venc_disable_display(struct omap_display *display)
++{
++	DSSDBG("venc_disable_display\n");
++
++	mutex_lock(&venc.venc_lock);
++
++	if (display->state == OMAP_DSS_DISPLAY_DISABLED)
++		goto end;
++
++	if (display->state == OMAP_DSS_DISPLAY_SUSPENDED) {
++		/* suspended is the same as disabled with venc */
++		display->state = OMAP_DSS_DISPLAY_DISABLED;
++		goto end;
++	}
++
++	venc_power_off(display);
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++end:
++	mutex_unlock(&venc.venc_lock);
++}
++
++static int venc_display_suspend(struct omap_display *display)
++{
++	int r = 0;
++
++	DSSDBG("venc_display_suspend\n");
++
++	mutex_lock(&venc.venc_lock);
++
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	venc_power_off(display);
++
++	display->state = OMAP_DSS_DISPLAY_SUSPENDED;
++err:
++	mutex_unlock(&venc.venc_lock);
++
++	return r;
++}
++
++static int venc_display_resume(struct omap_display *display)
++{
++	int r = 0;
++
++	DSSDBG("venc_display_resume\n");
++
++	mutex_lock(&venc.venc_lock);
++
++	if (display->state != OMAP_DSS_DISPLAY_SUSPENDED) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	venc_power_on(display);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++err:
++	mutex_unlock(&venc.venc_lock);
++
++	return r;
++}
++
++static void venc_get_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	*timings = venc_panel.timings;
++}
++
++static void venc_set_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	DSSDBG("venc_set_timings\n");
++	display->panel->timings = *timings;
++	if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
++		/* turn the venc off and on to get new timings to use */
++		venc_disable_display(display);
++		venc_enable_display(display);
++	}
++}
++
++static int venc_check_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	DSSDBG("venc_check_timings\n");
++
++	if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
++		return 0;
++
++	if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
++		return 0;
++
++	return -EINVAL;
++}
++
++void venc_init_display(struct omap_display *display)
++{
++	display->panel = &venc_panel;
++	display->enable = venc_enable_display;
++	display->disable = venc_disable_display;
++	display->suspend = venc_display_suspend;
++	display->resume = venc_display_resume;
++	display->get_timings = venc_get_timings;
++	display->set_timings = venc_set_timings;
++	display->check_timings = venc_check_timings;
++}
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0004-DSS2-OMAP-framebuffer-driver.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0004-DSS2-OMAP-framebuffer-driver.patch
new file mode 100644
index 0000000000..877bb43c56
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0004-DSS2-OMAP-framebuffer-driver.patch
@@ -0,0 +1,3403 @@
+From db9314f01a207e256d545244d3d00dc4ce535280 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 10:25:48 +0300
+Subject: [PATCH 04/69] DSS2: OMAP framebuffer driver
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/plat-omap/fb.c                   |   28 +
+ drivers/video/omap/Kconfig                |    5 +-
+ drivers/video/omap2/omapfb/Kconfig        |   35 +
+ drivers/video/omap2/omapfb/Makefile       |    2 +
+ drivers/video/omap2/omapfb/omapfb-ioctl.c |  656 ++++++++++
+ drivers/video/omap2/omapfb/omapfb-main.c  | 2010 +++++++++++++++++++++++++++++
+ drivers/video/omap2/omapfb/omapfb-sysfs.c |  371 ++++++
+ drivers/video/omap2/omapfb/omapfb.h       |  153 +++
+ include/linux/omapfb.h                    |   20 +
+ 9 files changed, 3278 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/video/omap2/omapfb/Kconfig
+ create mode 100644 drivers/video/omap2/omapfb/Makefile
+ create mode 100644 drivers/video/omap2/omapfb/omapfb-ioctl.c
+ create mode 100644 drivers/video/omap2/omapfb/omapfb-main.c
+ create mode 100644 drivers/video/omap2/omapfb/omapfb-sysfs.c
+ create mode 100644 drivers/video/omap2/omapfb/omapfb.h
+
+diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
+index 40615a6..1dc3415 100644
+--- a/arch/arm/plat-omap/fb.c
++++ b/arch/arm/plat-omap/fb.c
+@@ -327,6 +327,34 @@ static inline int omap_init_fb(void)
+ 
+ arch_initcall(omap_init_fb);
+ 
++#elif defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
++
++static u64 omap_fb_dma_mask = ~(u32)0;
++static struct omapfb_platform_data omapfb_config;
++
++static struct platform_device omap_fb_device = {
++	.name		= "omapfb",
++	.id		= -1,
++	.dev = {
++		.dma_mask		= &omap_fb_dma_mask,
++		.coherent_dma_mask	= ~(u32)0,
++		.platform_data		= &omapfb_config,
++	},
++	.num_resources = 0,
++};
++
++void omapfb_set_platform_data(struct omapfb_platform_data *data)
++{
++	omapfb_config = *data;
++}
++
++static inline int omap_init_fb(void)
++{
++	return platform_device_register(&omap_fb_device);
++}
++
++arch_initcall(omap_init_fb);
++
+ #else
+ 
+ void omapfb_reserve_sdram(void) {}
+diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
+index c355b59..a1c10de 100644
+--- a/drivers/video/omap/Kconfig
++++ b/drivers/video/omap/Kconfig
+@@ -1,6 +1,7 @@
+ config FB_OMAP
+ 	tristate "OMAP frame buffer support (EXPERIMENTAL)"
+-	depends on FB && ARCH_OMAP
++	depends on FB && ARCH_OMAP && (OMAP2_DSS = "n")
++
+ 	select FB_CFB_FILLRECT
+ 	select FB_CFB_COPYAREA
+ 	select FB_CFB_IMAGEBLIT
+@@ -72,7 +73,7 @@ config FB_OMAP_LCD_MIPID
+ 
+ config FB_OMAP_BOOTLOADER_INIT
+ 	bool "Check bootloader initialization"
+-	depends on FB_OMAP
++	depends on FB_OMAP || FB_OMAP2
+ 	help
+ 	  Say Y here if you want to enable checking if the bootloader has
+ 	  already initialized the display controller. In this case the
+diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig
+new file mode 100644
+index 0000000..4f66033
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/Kconfig
+@@ -0,0 +1,35 @@
++menuconfig FB_OMAP2
++        tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)"
++        depends on FB && OMAP2_DSS
++
++        select FB_CFB_FILLRECT
++        select FB_CFB_COPYAREA
++        select FB_CFB_IMAGEBLIT
++        help
++          Frame buffer driver for OMAP2/3 based boards.
++
++config FB_OMAP2_DEBUG_SUPPORT
++	bool "Debug support for OMAP2/3 FB"
++	default y
++	depends on FB_OMAP2
++	help
++	  Support for debug output. You have to enable the actual printing
++	  with debug module parameter.
++
++config FB_OMAP2_FORCE_AUTO_UPDATE
++	bool "Force main display to automatic update mode"
++	depends on FB_OMAP2
++	help
++	  Forces main display to automatic update mode (if possible),
++	  and also enables tearsync (if possible). By default
++	  displays that support manual update are started in manual
++	  update mode.
++
++config FB_OMAP2_NUM_FBS
++	int "Number of framebuffers"
++	range 1 10
++	default 3
++	depends on FB_OMAP2
++	help
++	  Select the number of framebuffers created. OMAP2/3 has 3 overlays
++	  so normally this would be 3.
+diff --git a/drivers/video/omap2/omapfb/Makefile b/drivers/video/omap2/omapfb/Makefile
+new file mode 100644
+index 0000000..51c2e00
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_FB_OMAP2) += omapfb.o
++omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
+diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
+new file mode 100644
+index 0000000..7f18d2a
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
+@@ -0,0 +1,656 @@
++/*
++ * linux/drivers/video/omap2/omapfb-ioctl.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/fb.h>
++#include <linux/device.h>
++#include <linux/uaccess.h>
++#include <linux/platform_device.h>
++#include <linux/mm.h>
++#include <linux/omapfb.h>
++#include <linux/vmalloc.h>
++
++#include <mach/display.h>
++#include <mach/vrfb.h>
++
++#include "omapfb.h"
++
++static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	struct omap_overlay *ovl;
++	struct omap_overlay_info info;
++	int r = 0;
++
++	DBG("omapfb_setup_plane\n");
++
++	omapfb_lock(fbdev);
++
++	if (ofbi->num_overlays != 1) {
++		r = -EINVAL;
++		goto out;
++	}
++
++	/* XXX uses only the first overlay */
++	ovl = ofbi->overlays[0];
++
++	if (pi->enabled && !ofbi->region.size) {
++		/*
++		 * This plane's memory was freed, can't enable it
++		 * until it's reallocated.
++		 */
++		r = -EINVAL;
++		goto out;
++	}
++
++	ovl->get_overlay_info(ovl, &info);
++
++	info.pos_x = pi->pos_x;
++	info.pos_y = pi->pos_y;
++	info.out_width = pi->out_width;
++	info.out_height = pi->out_height;
++	info.enabled = pi->enabled;
++
++	r = ovl->set_overlay_info(ovl, &info);
++	if (r)
++		goto out;
++
++	if (ovl->manager) {
++		r = ovl->manager->apply(ovl->manager);
++		if (r)
++			goto out;
++	}
++
++	if (display) {
++		u16 w, h;
++
++		if (display->sync)
++			display->sync(display);
++
++		display->get_resolution(display, &w, &h);
++
++		if (display->update)
++			display->update(display, 0, 0, w, h);
++	}
++
++out:
++	omapfb_unlock(fbdev);
++	if (r)
++		dev_err(fbdev->dev, "setup_plane failed\n");
++	return r;
++}
++
++static int omapfb_query_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++
++	omapfb_lock(fbdev);
++
++	if (ofbi->num_overlays != 1) {
++		memset(pi, 0, sizeof(*pi));
++	} else {
++		struct omap_overlay_info *ovli;
++		struct omap_overlay *ovl;
++
++		ovl = ofbi->overlays[0];
++		ovli = &ovl->info;
++
++		pi->pos_x = ovli->pos_x;
++		pi->pos_y = ovli->pos_y;
++		pi->enabled = ovli->enabled;
++		pi->channel_out = 0; /* xxx */
++		pi->mirror = 0;
++		pi->out_width = ovli->out_width;
++		pi->out_height = ovli->out_height;
++	}
++
++	omapfb_unlock(fbdev);
++
++	return 0;
++}
++
++static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omapfb2_mem_region *rg;
++	int r, i;
++	size_t size;
++
++	if (mi->type > OMAPFB_MEMTYPE_MAX)
++		return -EINVAL;
++
++	size = PAGE_ALIGN(mi->size);
++
++	rg = &ofbi->region;
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i]->info.enabled) {
++			r = -EBUSY;
++			goto out;
++		}
++	}
++
++	if (rg->size != size || rg->type != mi->type) {
++		r = omapfb_realloc_fbmem(fbi, size, mi->type);
++		if (r) {
++			dev_err(fbdev->dev, "realloc fbmem failed\n");
++			goto out;
++		}
++	}
++
++	r = 0;
++out:
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omapfb2_mem_region *rg;
++
++	rg = &ofbi->region;
++	memset(mi, 0, sizeof(*mi));
++
++	omapfb_lock(fbdev);
++	mi->size = rg->size;
++	mi->type = rg->type;
++	omapfb_unlock(fbdev);
++
++	return 0;
++}
++
++static int omapfb_update_window(struct fb_info *fbi,
++		u32 x, u32 y, u32 w, u32 h)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	u16 dw, dh;
++
++	if (!display)
++		return 0;
++
++	if (w == 0 || h == 0)
++		return 0;
++
++	display->get_resolution(display, &dw, &dh);
++
++	if (x + w > dw || y + h > dh)
++		return -EINVAL;
++
++	omapfb_lock(fbdev);
++	display->update(display, x, y, w, h);
++	omapfb_unlock(fbdev);
++
++	return 0;
++}
++
++static int omapfb_set_update_mode(struct fb_info *fbi,
++				   enum omapfb_update_mode mode)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	enum omap_dss_update_mode um;
++	int r;
++
++	if (!display || !display->set_update_mode)
++		return -EINVAL;
++
++	switch (mode) {
++	case OMAPFB_UPDATE_DISABLED:
++		um = OMAP_DSS_UPDATE_DISABLED;
++		break;
++
++	case OMAPFB_AUTO_UPDATE:
++		um = OMAP_DSS_UPDATE_AUTO;
++		break;
++
++	case OMAPFB_MANUAL_UPDATE:
++		um = OMAP_DSS_UPDATE_MANUAL;
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	omapfb_lock(fbdev);
++	r = display->set_update_mode(display, um);
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static int omapfb_get_update_mode(struct fb_info *fbi,
++		enum omapfb_update_mode *mode)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	enum omap_dss_update_mode m;
++
++	if (!display || !display->get_update_mode)
++		return -EINVAL;
++
++	omapfb_lock(fbdev);
++	m = display->get_update_mode(display);
++	omapfb_unlock(fbdev);
++
++	switch (m) {
++	case OMAP_DSS_UPDATE_DISABLED:
++		*mode = OMAPFB_UPDATE_DISABLED;
++		break;
++	case OMAP_DSS_UPDATE_AUTO:
++		*mode = OMAPFB_AUTO_UPDATE;
++		break;
++	case OMAP_DSS_UPDATE_MANUAL:
++		*mode = OMAPFB_MANUAL_UPDATE;
++		break;
++	default:
++		BUG();
++	}
++
++	return 0;
++}
++
++/* XXX this color key handling is a hack... */
++static struct omapfb_color_key omapfb_color_keys[2];
++
++static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
++		struct omapfb_color_key *ck)
++{
++	enum omap_dss_color_key_type kt;
++
++	if(!mgr->set_default_color || !mgr->set_trans_key ||
++			!mgr->enable_trans_key)
++		return 0;
++
++	if (ck->key_type == OMAPFB_COLOR_KEY_DISABLED) {
++		mgr->enable_trans_key(mgr, 0);
++		omapfb_color_keys[mgr->id] = *ck;
++		return 0;
++	}
++
++	switch(ck->key_type) {
++	case OMAPFB_COLOR_KEY_GFX_DST:
++		kt = OMAP_DSS_COLOR_KEY_GFX_DST;
++		break;
++	case OMAPFB_COLOR_KEY_VID_SRC:
++		kt = OMAP_DSS_COLOR_KEY_VID_SRC;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	mgr->set_default_color(mgr, ck->background);
++	mgr->set_trans_key(mgr, kt, ck->trans_key);
++	mgr->enable_trans_key(mgr, 1);
++
++	omapfb_color_keys[mgr->id] = *ck;
++
++	return 0;
++}
++
++static int omapfb_set_color_key(struct fb_info *fbi,
++		struct omapfb_color_key *ck)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	int r;
++	int i;
++	struct omap_overlay_manager *mgr = NULL;
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i]->manager) {
++			mgr = ofbi->overlays[i]->manager;
++			break;
++		}
++	}
++
++	if (!mgr) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	if(!mgr->set_default_color || !mgr->set_trans_key ||
++			!mgr->enable_trans_key) {
++		r = -ENODEV;
++		goto err;
++	}
++
++	r = _omapfb_set_color_key(mgr, ck);
++err:
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static int omapfb_get_color_key(struct fb_info *fbi,
++		struct omapfb_color_key *ck)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_overlay_manager *mgr = NULL;
++	int r = 0;
++	int i;
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i]->manager) {
++			mgr = ofbi->overlays[i]->manager;
++			break;
++		}
++	}
++
++	if (!mgr) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	if(!mgr->set_default_color || !mgr->set_trans_key ||
++			!mgr->enable_trans_key) {
++		r = -ENODEV;
++		goto err;
++	}
++
++	*ck = omapfb_color_keys[mgr->id];
++err:
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static int omapfb_memory_read(struct fb_info *fbi,
++		struct omapfb_memory_read *mr)
++{
++	struct omap_display *display = fb2display(fbi);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	void *buf;
++	int r;
++
++	if (!display || !display->memory_read)
++		return -ENOENT;
++
++	if (!access_ok(VERIFY_WRITE, mr->buffer, mr->buffer_size))
++		return -EFAULT;
++
++	if (mr->w * mr->h * 3 > mr->buffer_size)
++		return -EINVAL;
++
++	buf = vmalloc(mr->buffer_size);
++	if (!buf) {
++		DBG("vmalloc failed\n");
++		return -ENOMEM;
++	}
++
++	omapfb_lock(fbdev);
++
++	r = display->memory_read(display, buf, mr->buffer_size,
++			mr->x, mr->y, mr->w, mr->h);
++
++	if (r > 0) {
++		if (copy_to_user(mr->buffer, buf, mr->buffer_size))
++			r = -EFAULT;
++	}
++
++	vfree(buf);
++
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++
++	union {
++		struct omapfb_update_window_old	uwnd_o;
++		struct omapfb_update_window	uwnd;
++		struct omapfb_plane_info	plane_info;
++		struct omapfb_caps		caps;
++		struct omapfb_mem_info          mem_info;
++		struct omapfb_color_key		color_key;
++		enum omapfb_update_mode		update_mode;
++		int test_num;
++		struct omapfb_memory_read	memory_read;
++	} p;
++
++	int r = 0;
++
++	switch (cmd) {
++	case OMAPFB_SYNC_GFX:
++		DBG("ioctl SYNC_GFX\n");
++		if (!display || !display->sync) {
++			/* DSS1 never returns an error here, so we neither */
++			/*r = -EINVAL;*/
++			break;
++		}
++
++		omapfb_lock(fbdev);
++		r = display->sync(display);
++		omapfb_unlock(fbdev);
++		break;
++
++	case OMAPFB_UPDATE_WINDOW_OLD:
++		DBG("ioctl UPDATE_WINDOW_OLD\n");
++		if (!display || !display->update) {
++			r = -EINVAL;
++			break;
++		}
++
++		if (copy_from_user(&p.uwnd_o,
++					(void __user *)arg,
++					sizeof(p.uwnd_o))) {
++			r = -EFAULT;
++			break;
++		}
++
++		r = omapfb_update_window(fbi, p.uwnd_o.x, p.uwnd_o.y,
++				p.uwnd_o.width, p.uwnd_o.height);
++		break;
++
++	case OMAPFB_UPDATE_WINDOW:
++		DBG("ioctl UPDATE_WINDOW\n");
++		if (!display || !display->update) {
++			r = -EINVAL;
++			break;
++		}
++
++		if (copy_from_user(&p.uwnd, (void __user *)arg,
++					sizeof(p.uwnd))) {
++			r = -EFAULT;
++			break;
++		}
++
++		r = omapfb_update_window(fbi, p.uwnd.x, p.uwnd.y,
++				p.uwnd.width, p.uwnd.height);
++		break;
++
++	case OMAPFB_SETUP_PLANE:
++		DBG("ioctl SETUP_PLANE\n");
++		if (copy_from_user(&p.plane_info, (void __user *)arg,
++					sizeof(p.plane_info)))
++			r = -EFAULT;
++		else
++			r = omapfb_setup_plane(fbi, &p.plane_info);
++		break;
++
++	case OMAPFB_QUERY_PLANE:
++		DBG("ioctl QUERY_PLANE\n");
++		r = omapfb_query_plane(fbi, &p.plane_info);
++		if (r < 0)
++			break;
++		if (copy_to_user((void __user *)arg, &p.plane_info,
++					sizeof(p.plane_info)))
++			r = -EFAULT;
++		break;
++
++	case OMAPFB_SETUP_MEM:
++		DBG("ioctl SETUP_MEM\n");
++		if (copy_from_user(&p.mem_info, (void __user *)arg,
++					sizeof(p.mem_info)))
++			r = -EFAULT;
++		else
++			r = omapfb_setup_mem(fbi, &p.mem_info);
++		break;
++
++	case OMAPFB_QUERY_MEM:
++		DBG("ioctl QUERY_MEM\n");
++		r = omapfb_query_mem(fbi, &p.mem_info);
++		if (r < 0)
++			break;
++		if (copy_to_user((void __user *)arg, &p.mem_info,
++					sizeof(p.mem_info)))
++			r = -EFAULT;
++		break;
++
++	case OMAPFB_GET_CAPS:
++		DBG("ioctl GET_CAPS\n");
++		if (!display) {
++			r = -EINVAL;
++			break;
++		}
++
++		p.caps.ctrl = display->caps;
++
++		if (copy_to_user((void __user *)arg, &p.caps, sizeof(p.caps)))
++			r = -EFAULT;
++		break;
++
++	case OMAPFB_SET_UPDATE_MODE:
++		DBG("ioctl SET_UPDATE_MODE\n");
++		if (get_user(p.update_mode, (int __user *)arg))
++			r = -EFAULT;
++		else
++			r = omapfb_set_update_mode(fbi, p.update_mode);
++		break;
++
++	case OMAPFB_GET_UPDATE_MODE:
++		DBG("ioctl GET_UPDATE_MODE\n");
++		r = omapfb_get_update_mode(fbi, &p.update_mode);
++		if (r)
++			break;
++		if (put_user(p.update_mode,
++					(enum omapfb_update_mode __user *)arg))
++			r = -EFAULT;
++		break;
++
++	case OMAPFB_SET_COLOR_KEY:
++		DBG("ioctl SET_COLOR_KEY\n");
++		if (copy_from_user(&p.color_key, (void __user *)arg,
++				   sizeof(p.color_key)))
++			r = -EFAULT;
++		else
++			r = omapfb_set_color_key(fbi, &p.color_key);
++		break;
++
++	case OMAPFB_GET_COLOR_KEY:
++		DBG("ioctl GET_COLOR_KEY\n");
++		if ((r = omapfb_get_color_key(fbi, &p.color_key)) < 0)
++			break;
++		if (copy_to_user((void __user *)arg, &p.color_key,
++				 sizeof(p.color_key)))
++			r = -EFAULT;
++		break;
++
++	case OMAPFB_WAITFORVSYNC:
++		DBG("ioctl WAITFORVSYNC\n");
++		if (!display) {
++			r = -EINVAL;
++			break;
++		}
++
++		r = display->wait_vsync(display);
++		break;
++
++	/* LCD and CTRL tests do the same thing for backward
++	 * compatibility */
++	case OMAPFB_LCD_TEST:
++		DBG("ioctl LCD_TEST\n");
++		if (get_user(p.test_num, (int __user *)arg)) {
++			r = -EFAULT;
++			break;
++		}
++		if (!display || !display->run_test) {
++			r = -EINVAL;
++			break;
++		}
++
++		r = display->run_test(display, p.test_num);
++
++		break;
++
++	case OMAPFB_CTRL_TEST:
++		DBG("ioctl CTRL_TEST\n");
++		if (get_user(p.test_num, (int __user *)arg)) {
++			r = -EFAULT;
++			break;
++		}
++		if (!display || !display->run_test) {
++			r = -EINVAL;
++			break;
++		}
++
++		r = display->run_test(display, p.test_num);
++
++		break;
++
++	case OMAPFB_MEMORY_READ:
++		DBG("ioctl MEMORY_READ\n");
++
++		if (copy_from_user(&p.memory_read, (void __user *)arg,
++					sizeof(p.memory_read))) {
++			r = -EFAULT;
++			break;
++		}
++
++		r = omapfb_memory_read(fbi, &p.memory_read);
++
++		break;
++
++	default:
++		dev_err(fbdev->dev, "Unknown ioctl 0x%x\n", cmd);
++		r = -EINVAL;
++	}
++
++	if (r < 0)
++		DBG("ioctl failed: %d\n", r);
++
++	return r;
++}
++
++
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+new file mode 100644
+index 0000000..852abe5
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -0,0 +1,2010 @@
++/*
++ * linux/drivers/video/omap2/omapfb-main.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/omapfb.h>
++
++#include <mach/display.h>
++#include <mach/vram.h>
++#include <mach/vrfb.h>
++
++#include "omapfb.h"
++
++#define MODULE_NAME     "omapfb"
++
++static char *def_mode;
++static char *def_vram;
++static int def_vrfb;
++static int def_rotate;
++static int def_mirror;
++
++#ifdef DEBUG
++unsigned int omapfb_debug;
++module_param_named(debug, omapfb_debug, bool, 0644);
++static unsigned int omapfb_test_pattern;
++module_param_named(test, omapfb_test_pattern, bool, 0644);
++#endif
++
++#ifdef DEBUG
++static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color)
++{
++	struct fb_var_screeninfo *var = &fbi->var;
++	struct fb_fix_screeninfo *fix = &fbi->fix;
++	void __iomem *addr = fbi->screen_base;
++	const unsigned bytespp = var->bits_per_pixel >> 3;
++	const unsigned line_len = fix->line_length / bytespp;
++
++	int r = (color >> 16) & 0xff;
++	int g = (color >> 8) & 0xff;
++	int b = (color >> 0) & 0xff;
++
++	if (var->bits_per_pixel == 16) {
++		u16 __iomem *p = (u16 __iomem *)addr;
++		p += y * line_len + x;
++
++		r = r * 32 / 256;
++		g = g * 64 / 256;
++		b = b * 32 / 256;
++
++		__raw_writew((r << 11) | (g << 5) | (b << 0), p);
++	} else if (var->bits_per_pixel == 24) {
++		u8 __iomem *p = (u8 __iomem *)addr;
++		p += (y * line_len + x) * 3;
++
++		__raw_writeb(b, p + 0);
++		__raw_writeb(g, p + 1);
++		__raw_writeb(r, p + 2);
++	} else if (var->bits_per_pixel == 32) {
++		u32 __iomem *p = (u32 __iomem *)addr;
++		p += y * line_len + x;
++		__raw_writel(color, p);
++	}
++}
++
++static void fill_fb(struct fb_info *fbi)
++{
++	struct fb_var_screeninfo *var = &fbi->var;
++	const short w = var->xres_virtual;
++	const short h = var->yres_virtual;
++	void __iomem *addr = fbi->screen_base;
++	int y, x;
++
++	if (!addr)
++		return;
++
++	DBG("fill_fb %dx%d, line_len %d bytes\n", w, h, fbi->fix.line_length);
++
++	for (y = 0; y < h; y++) {
++		for (x = 0; x < w; x++) {
++			if (x < 20 && y < 20)
++				draw_pixel(fbi, x, y, 0xffffff);
++			else if (x < 20 && (y > 20 && y < h - 20))
++				draw_pixel(fbi, x, y, 0xff);
++			else if (y < 20 && (x > 20 && x < w - 20))
++				draw_pixel(fbi, x, y, 0xff00);
++			else if (x > w - 20 && (y > 20 && y < h - 20))
++				draw_pixel(fbi, x, y, 0xff0000);
++			else if (y > h - 20 && (x > 20 && x < w - 20))
++				draw_pixel(fbi, x, y, 0xffff00);
++			else if (x == 20 || x == w - 20 ||
++					y == 20 || y == h - 20)
++				draw_pixel(fbi, x, y, 0xffffff);
++			else if (x == y || w - x == h - y)
++				draw_pixel(fbi, x, y, 0xff00ff);
++			else if (w - x == y || x == h - y)
++				draw_pixel(fbi, x, y, 0x00ffff);
++			else if (x > 20 && y > 20 && x < w - 20 && y < h - 20) {
++				int t = x * 3 / w;
++				unsigned r = 0, g = 0, b = 0;
++				unsigned c;
++				if (var->bits_per_pixel == 16) {
++					if (t == 0)
++						b = (y % 32) * 256 / 32;
++					else if (t == 1)
++						g = (y % 64) * 256 / 64;
++					else if (t == 2)
++						r = (y % 32) * 256 / 32;
++				} else {
++					if (t == 0)
++						b = (y % 256);
++					else if (t == 1)
++						g = (y % 256);
++					else if (t == 2)
++						r = (y % 256);
++				}
++				c = (r << 16) | (g << 8) | (b << 0);
++				draw_pixel(fbi, x, y, c);
++			} else {
++				draw_pixel(fbi, x, y, 0);
++			}
++		}
++	}
++}
++#endif
++
++static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot)
++{
++	struct vrfb *vrfb = &ofbi->region.vrfb;
++	unsigned offset;
++
++	switch (rot) {
++	case FB_ROTATE_UR:
++		offset = 0;
++		break;
++	case FB_ROTATE_CW:
++		offset = vrfb->yoffset;
++		break;
++	case FB_ROTATE_UD:
++		offset = vrfb->yoffset * OMAP_VRFB_LINE_LEN + vrfb->xoffset;
++		break;
++	case FB_ROTATE_CCW:
++		offset = vrfb->xoffset * OMAP_VRFB_LINE_LEN;
++		break;
++	default:
++		BUG();
++	}
++
++	offset *= vrfb->bytespp;
++
++	return offset;
++}
++
++static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
++{
++	if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++		unsigned offset;
++		int rot;
++
++		rot = ofbi->rotation;
++
++		offset = omapfb_get_vrfb_offset(ofbi, rot);
++
++		return ofbi->region.vrfb.paddr[rot] + offset;
++	} else {
++		return ofbi->region.paddr;
++	}
++}
++
++u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
++{
++	if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++		return ofbi->region.vrfb.paddr[0];
++	else
++		return ofbi->region.paddr;
++}
++
++void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi)
++{
++	if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++		return ofbi->region.vrfb.vaddr[0];
++	else
++		return ofbi->region.vaddr;
++}
++
++static struct omapfb_colormode omapfb_colormodes[] = {
++	{
++		.dssmode = OMAP_DSS_COLOR_UYVY,
++		.bits_per_pixel = 16,
++		.nonstd = OMAPFB_COLOR_YUV422,
++	}, {
++		.dssmode = OMAP_DSS_COLOR_YUV2,
++		.bits_per_pixel = 16,
++		.nonstd = OMAPFB_COLOR_YUY422,
++	}, {
++		.dssmode = OMAP_DSS_COLOR_ARGB16,
++		.bits_per_pixel = 16,
++		.red	= { .length = 4, .offset = 8, .msb_right = 0 },
++		.green	= { .length = 4, .offset = 4, .msb_right = 0 },
++		.blue	= { .length = 4, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 4, .offset = 12, .msb_right = 0 },
++	}, {
++		.dssmode = OMAP_DSS_COLOR_RGB16,
++		.bits_per_pixel = 16,
++		.red	= { .length = 5, .offset = 11, .msb_right = 0 },
++		.green	= { .length = 6, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.dssmode = OMAP_DSS_COLOR_RGB24P,
++		.bits_per_pixel = 24,
++		.red	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.dssmode = OMAP_DSS_COLOR_RGB24U,
++		.bits_per_pixel = 32,
++		.red	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.dssmode = OMAP_DSS_COLOR_ARGB32,
++		.bits_per_pixel = 32,
++		.red	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 8, .offset = 24, .msb_right = 0 },
++	}, {
++		.dssmode = OMAP_DSS_COLOR_RGBA32,
++		.bits_per_pixel = 32,
++		.red	= { .length = 8, .offset = 24, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.transp	= { .length = 8, .offset = 0, .msb_right = 0 },
++	}, {
++		.dssmode = OMAP_DSS_COLOR_RGBX32,
++		.bits_per_pixel = 32,
++		.red	= { .length = 8, .offset = 24, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	},
++};
++
++static bool cmp_var_to_colormode(struct fb_var_screeninfo *var,
++		struct omapfb_colormode *color)
++{
++	bool cmp_component(struct fb_bitfield *f1, struct fb_bitfield *f2)
++	{
++		return f1->length == f2->length &&
++			f1->offset == f2->offset &&
++			f1->msb_right == f2->msb_right;
++	}
++
++	if (var->bits_per_pixel == 0 ||
++			var->red.length == 0 ||
++			var->blue.length == 0 ||
++			var->green.length == 0)
++		return 0;
++
++	return var->bits_per_pixel == color->bits_per_pixel &&
++		cmp_component(&var->red, &color->red) &&
++		cmp_component(&var->green, &color->green) &&
++		cmp_component(&var->blue, &color->blue) &&
++		cmp_component(&var->transp, &color->transp);
++}
++
++static void assign_colormode_to_var(struct fb_var_screeninfo *var,
++		struct omapfb_colormode *color)
++{
++	var->bits_per_pixel = color->bits_per_pixel;
++	var->nonstd = color->nonstd;
++	var->red = color->red;
++	var->green = color->green;
++	var->blue = color->blue;
++	var->transp = color->transp;
++}
++
++static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var)
++{
++	enum omap_color_mode dssmode;
++	int i;
++
++	/* first match with nonstd field */
++	if (var->nonstd) {
++		for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
++			struct omapfb_colormode *mode = &omapfb_colormodes[i];
++			if (var->nonstd == mode->nonstd) {
++				assign_colormode_to_var(var, mode);
++				return mode->dssmode;
++			}
++		}
++
++		return -EINVAL;
++	}
++
++	/* then try exact match of bpp and colors */
++	for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
++		struct omapfb_colormode *mode = &omapfb_colormodes[i];
++		if (cmp_var_to_colormode(var, mode)) {
++			assign_colormode_to_var(var, mode);
++			return mode->dssmode;
++		}
++	}
++
++	/* match with bpp if user has not filled color fields
++	 * properly */
++	switch (var->bits_per_pixel) {
++	case 1:
++		dssmode = OMAP_DSS_COLOR_CLUT1;
++		break;
++	case 2:
++		dssmode = OMAP_DSS_COLOR_CLUT2;
++		break;
++	case 4:
++		dssmode = OMAP_DSS_COLOR_CLUT4;
++		break;
++	case 8:
++		dssmode = OMAP_DSS_COLOR_CLUT8;
++		break;
++	case 12:
++		dssmode = OMAP_DSS_COLOR_RGB12U;
++		break;
++	case 16:
++		dssmode = OMAP_DSS_COLOR_RGB16;
++		break;
++	case 24:
++		dssmode = OMAP_DSS_COLOR_RGB24P;
++		break;
++	case 32:
++		dssmode = OMAP_DSS_COLOR_RGB24U;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
++		struct omapfb_colormode *mode = &omapfb_colormodes[i];
++		if (dssmode == mode->dssmode) {
++			assign_colormode_to_var(var, mode);
++			return mode->dssmode;
++		}
++	}
++
++	return -EINVAL;
++}
++
++void set_fb_fix(struct fb_info *fbi)
++{
++	struct fb_fix_screeninfo *fix = &fbi->fix;
++	struct fb_var_screeninfo *var = &fbi->var;
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_mem_region *rg = &ofbi->region;
++
++	DBG("set_fb_fix\n");
++
++	/* used by open/write in fbmem.c */
++	fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
++
++	/* used by mmap in fbmem.c */
++	if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++		fix->line_length =
++			(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
++	else
++		fix->line_length =
++			(var->xres_virtual * var->bits_per_pixel) >> 3;
++	fix->smem_start = omapfb_get_region_paddr(ofbi);
++	fix->smem_len = rg->size;
++
++	fix->type = FB_TYPE_PACKED_PIXELS;
++
++	if (var->nonstd)
++		fix->visual = FB_VISUAL_PSEUDOCOLOR;
++	else {
++		switch (var->bits_per_pixel) {
++		case 32:
++		case 24:
++		case 16:
++		case 12:
++			fix->visual = FB_VISUAL_TRUECOLOR;
++			/* 12bpp is stored in 16 bits */
++			break;
++		case 1:
++		case 2:
++		case 4:
++		case 8:
++			fix->visual = FB_VISUAL_PSEUDOCOLOR;
++			break;
++		}
++	}
++
++	fix->accel = FB_ACCEL_NONE;
++
++	fix->xpanstep = 1;
++	fix->ypanstep = 1;
++
++	if (rg->size) {
++		if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++			omap_vrfb_setup(&rg->vrfb, rg->paddr,
++					var->xres_virtual, var->yres_virtual,
++					var->bits_per_pixel >> 3);
++	}
++}
++
++/* check new var and possibly modify it to be ok */
++int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omap_display *display = fb2display(fbi);
++	unsigned long max_frame_size;
++	unsigned long line_size;
++	int xres_min, yres_min;
++	int xres_max, yres_max;
++	enum omap_color_mode mode = 0;
++	int i;
++	int bytespp;
++
++	DBG("check_fb_var %d\n", ofbi->id);
++
++	if (ofbi->region.size == 0)
++		return 0;
++
++	mode = fb_mode_to_dss_mode(var);
++	if (mode < 0) {
++		DBG("cannot convert var to omap dss mode\n");
++		return -EINVAL;
++	}
++
++	for (i = 0; i < ofbi->num_overlays; ++i) {
++		if ((ofbi->overlays[i]->supported_modes & mode) == 0) {
++			DBG("invalid mode\n");
++			return -EINVAL;
++		}
++	}
++
++	if (var->rotate < 0 || var->rotate > 3)
++		return -EINVAL;
++
++	if (var->rotate != fbi->var.rotate) {
++		DBG("rotation changing\n");
++
++		ofbi->rotation = var->rotate;
++
++		if (abs(var->rotate - fbi->var.rotate) != 2) {
++			int tmp;
++			DBG("rotate changing 90/270 degrees. "
++					"swapping x/y res\n");
++
++			tmp = var->yres;
++			var->yres = var->xres;
++			var->xres = tmp;
++
++			tmp = var->yres_virtual;
++			var->yres_virtual = var->xres_virtual;
++			var->xres_virtual = tmp;
++		}
++	}
++
++	xres_min = OMAPFB_PLANE_XRES_MIN;
++	xres_max = 2048;
++	yres_min = OMAPFB_PLANE_YRES_MIN;
++	yres_max = 2048;
++
++	bytespp = var->bits_per_pixel >> 3;
++
++	/* XXX: some applications seem to set virtual res to 0. */
++	if (var->xres_virtual == 0)
++		var->xres_virtual = var->xres;
++
++	if (var->yres_virtual == 0)
++		var->yres_virtual = var->yres;
++
++	if (var->xres_virtual < xres_min || var->yres_virtual < yres_min)
++		return -EINVAL;
++
++	if (var->xres < xres_min)
++		var->xres = xres_min;
++	if (var->yres < yres_min)
++		var->yres = yres_min;
++	if (var->xres > xres_max)
++		var->xres = xres_max;
++	if (var->yres > yres_max)
++		var->yres = yres_max;
++
++	if (var->xres > var->xres_virtual)
++		var->xres = var->xres_virtual;
++	if (var->yres > var->yres_virtual)
++		var->yres = var->yres_virtual;
++
++	if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++		line_size = OMAP_VRFB_LINE_LEN * bytespp;
++	else
++		line_size = var->xres_virtual * bytespp;
++
++	max_frame_size = ofbi->region.size;
++
++	DBG("max frame size %lu, line size %lu\n", max_frame_size, line_size);
++
++	if (line_size * var->yres_virtual > max_frame_size) {
++		DBG("can't fit FB into memory, reducing y\n");
++		var->yres_virtual = max_frame_size / line_size;
++
++		if (var->yres_virtual < yres_min)
++			var->yres_virtual = yres_min;
++
++		if (var->yres > var->yres_virtual)
++			var->yres = var->yres_virtual;
++	}
++
++	if (line_size * var->yres_virtual > max_frame_size) {
++		DBG("can't fit FB into memory, reducing x\n");
++		if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++			return -EINVAL;
++
++		var->xres_virtual = max_frame_size / var->yres_virtual /
++			bytespp;
++
++		if (var->xres_virtual < xres_min)
++			var->xres_virtual = xres_min;
++
++		if (var->xres > var->xres_virtual)
++			var->xres = var->xres_virtual;
++
++		line_size = var->xres_virtual * bytespp;
++	}
++
++	if (line_size * var->yres_virtual > max_frame_size) {
++		DBG("cannot fit FB to memory\n");
++		return -EINVAL;
++	}
++
++	if (var->xres + var->xoffset > var->xres_virtual)
++		var->xoffset = var->xres_virtual - var->xres;
++	if (var->yres + var->yoffset > var->yres_virtual)
++		var->yoffset = var->yres_virtual - var->yres;
++
++	DBG("xres = %d, yres = %d, vxres = %d, vyres = %d\n",
++			var->xres, var->yres,
++			var->xres_virtual, var->yres_virtual);
++
++	var->height             = -1;
++	var->width              = -1;
++	var->grayscale          = 0;
++
++	if (display && display->get_timings) {
++		struct omap_video_timings timings;
++		display->get_timings(display, &timings);
++
++		/* pixclock in ps, the rest in pixclock */
++		var->pixclock = timings.pixel_clock != 0 ?
++			KHZ2PICOS(timings.pixel_clock) :
++			0;
++		var->left_margin = timings.hfp;
++		var->right_margin = timings.hbp;
++		var->upper_margin = timings.vfp;
++		var->lower_margin = timings.vbp;
++		var->hsync_len = timings.hsw;
++		var->vsync_len = timings.vsw;
++	} else {
++		var->pixclock = 0;
++		var->left_margin = 0;
++		var->right_margin = 0;
++		var->upper_margin = 0;
++		var->lower_margin = 0;
++		var->hsync_len = 0;
++		var->vsync_len = 0;
++	}
++
++	/* TODO: get these from panel->config */
++	var->vmode              = FB_VMODE_NONINTERLACED;
++	var->sync               = 0;
++
++	return 0;
++}
++
++/*
++ * ---------------------------------------------------------------------------
++ * fbdev framework callbacks
++ * ---------------------------------------------------------------------------
++ */
++static int omapfb_open(struct fb_info *fbi, int user)
++{
++	return 0;
++}
++
++static int omapfb_release(struct fb_info *fbi, int user)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++
++	DBG("Closing fb with plane index %d\n", ofbi->id);
++
++	omapfb_lock(fbdev);
++#if 1
++	if (display && display->get_update_mode && display->update) {
++		/* XXX this update should be removed, I think. But it's
++		 * good for debugging */
++		if (display->get_update_mode(display) ==
++				OMAP_DSS_UPDATE_MANUAL) {
++			u16 w, h;
++
++			if (display->sync)
++				display->sync(display);
++
++			display->get_resolution(display, &w, &h);
++			display->update(display, 0, 0, w, h);
++		}
++	}
++#endif
++
++	if (display && display->sync)
++		display->sync(display);
++
++	omapfb_unlock(fbdev);
++
++	return 0;
++}
++
++/* setup overlay according to the fb */
++static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
++		u16 posx, u16 posy, u16 outw, u16 outh)
++{
++	int r = 0;
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct fb_var_screeninfo *var = &fbi->var;
++	struct fb_fix_screeninfo *fix = &fbi->fix;
++	enum omap_color_mode mode = 0;
++	int offset;
++	u32 data_start_p;
++	void __iomem *data_start_v;
++	struct omap_overlay_info info;
++	int xres, yres;
++	int screen_width;
++	int rot, mirror;
++
++	DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
++			posx, posy, outw, outh);
++
++	if (ofbi->rotation == FB_ROTATE_CW || ofbi->rotation == FB_ROTATE_CCW) {
++		xres = var->yres;
++		yres = var->xres;
++	} else {
++		xres = var->xres;
++		yres = var->yres;
++	}
++
++	offset = ((var->yoffset * var->xres_virtual +
++				var->xoffset) * var->bits_per_pixel) >> 3;
++
++	if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++		data_start_p = omapfb_get_region_rot_paddr(ofbi);
++		data_start_v = NULL;
++	} else {
++		data_start_p = omapfb_get_region_paddr(ofbi);
++		data_start_v = omapfb_get_region_vaddr(ofbi);
++	}
++
++	data_start_p += offset;
++	data_start_v += offset;
++
++	mode = fb_mode_to_dss_mode(var);
++
++	if (mode == -EINVAL) {
++		DBG("fb_mode_to_dss_mode failed");
++		r = -EINVAL;
++		goto err;
++	}
++
++	screen_width = fix->line_length / (var->bits_per_pixel >> 3);
++
++	ovl->get_overlay_info(ovl, &info);
++
++	if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++		rot = 0;
++		mirror = 0;
++	} else {
++		rot = ofbi->rotation;
++		mirror = ofbi->mirror;
++	}
++
++	info.paddr = data_start_p;
++	info.vaddr = data_start_v;
++	info.screen_width = screen_width;
++	info.width = xres;
++	info.height = yres;
++	info.color_mode = mode;
++	info.rotation = rot;
++	info.mirror = mirror;
++
++	info.pos_x = posx;
++	info.pos_y = posy;
++	info.out_width = outw;
++	info.out_height = outh;
++
++	r = ovl->set_overlay_info(ovl, &info);
++	if (r) {
++		DBG("ovl->setup_overlay_info failed\n");
++		goto err;
++	}
++
++	return 0;
++
++err:
++	DBG("setup_overlay failed\n");
++	return r;
++}
++
++/* apply var to the overlay */
++int omapfb_apply_changes(struct fb_info *fbi, int init)
++{
++	int r = 0;
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct fb_var_screeninfo *var = &fbi->var;
++	struct omap_overlay *ovl;
++	u16 posx, posy;
++	u16 outw, outh;
++	int i;
++
++#ifdef DEBUG
++	if (omapfb_test_pattern)
++		fill_fb(fbi);
++#endif
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		ovl = ofbi->overlays[i];
++
++		DBG("apply_changes, fb %d, ovl %d\n", ofbi->id, ovl->id);
++
++		if (ofbi->region.size == 0) {
++			/* the fb is not available. disable the overlay */
++			omapfb_overlay_enable(ovl, 0);
++			if (!init && ovl->manager)
++				ovl->manager->apply(ovl->manager);
++			continue;
++		}
++
++		if (init || (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
++			if (ofbi->rotation == FB_ROTATE_CW ||
++					ofbi->rotation == FB_ROTATE_CCW) {
++				outw = var->yres;
++				outh = var->xres;
++			} else {
++				outw = var->xres;
++				outh = var->yres;
++			}
++		} else {
++			outw = ovl->info.out_width;
++			outh = ovl->info.out_height;
++		}
++
++		if (init) {
++			posx = 0;
++			posy = 0;
++		} else {
++			posx = ovl->info.pos_x;
++			posy = ovl->info.pos_y;
++		}
++
++		r = omapfb_setup_overlay(fbi, ovl, posx, posy, outw, outh);
++		if (r)
++			goto err;
++
++		if (!init && ovl->manager)
++			ovl->manager->apply(ovl->manager);
++	}
++	return 0;
++err:
++	DBG("apply_changes failed\n");
++	return r;
++}
++
++/* checks var and eventually tweaks it to something supported,
++ * DO NOT MODIFY PAR */
++static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
++{
++	int r;
++
++	DBG("check_var(%d)\n", FB2OFB(fbi)->id);
++
++	r = check_fb_var(fbi, var);
++
++	return r;
++}
++
++/* set the video mode according to info->var */
++static int omapfb_set_par(struct fb_info *fbi)
++{
++	int r;
++
++	DBG("set_par(%d)\n", FB2OFB(fbi)->id);
++
++	set_fb_fix(fbi);
++	r = omapfb_apply_changes(fbi, 0);
++
++	return r;
++}
++
++static int omapfb_pan_display(struct fb_var_screeninfo *var,
++		struct fb_info *fbi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	int r = 0;
++
++	DBG("pan_display(%d)\n", ofbi->id);
++
++	omapfb_lock(fbdev);
++
++	if (var->xoffset != fbi->var.xoffset ||
++	    var->yoffset != fbi->var.yoffset) {
++		struct fb_var_screeninfo new_var;
++
++		new_var = fbi->var;
++		new_var.xoffset = var->xoffset;
++		new_var.yoffset = var->yoffset;
++
++		r = check_fb_var(fbi, &new_var);
++
++		if (r == 0) {
++			fbi->var = new_var;
++			set_fb_fix(fbi);
++			r = omapfb_apply_changes(fbi, 0);
++		}
++	}
++
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static void mmap_user_open(struct vm_area_struct *vma)
++{
++	struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
++
++	atomic_inc(&ofbi->map_count);
++}
++
++static void mmap_user_close(struct vm_area_struct *vma)
++{
++	struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
++
++	atomic_dec(&ofbi->map_count);
++}
++
++static struct vm_operations_struct mmap_user_ops = {
++	.open = mmap_user_open,
++	.close = mmap_user_close,
++};
++
++static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct fb_fix_screeninfo *fix = &fbi->fix;
++	unsigned long off;
++	unsigned long start;
++	u32 len;
++
++	if (vma->vm_end - vma->vm_start == 0)
++		return 0;
++	if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
++		return -EINVAL;
++	off = vma->vm_pgoff << PAGE_SHIFT;
++
++	start = omapfb_get_region_paddr(ofbi);
++	len = fix->smem_len;
++	if (off >= len)
++		return -EINVAL;
++	if ((vma->vm_end - vma->vm_start + off) > len)
++		return -EINVAL;
++
++	off += start;
++
++	DBG("user mmap region start %lx, len %d, off %lx\n", start, len, off);
++
++	vma->vm_pgoff = off >> PAGE_SHIFT;
++	vma->vm_flags |= VM_IO | VM_RESERVED;
++	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++	vma->vm_ops = &mmap_user_ops;
++	vma->vm_private_data = ofbi;
++	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
++			     vma->vm_end - vma->vm_start, vma->vm_page_prot))
++		return -EAGAIN;
++	/* vm_ops.open won't be called for mmap itself. */
++	atomic_inc(&ofbi->map_count);
++	return 0;
++}
++
++/* Store a single color palette entry into a pseudo palette or the hardware
++ * palette if one is available. For now we support only 16bpp and thus store
++ * the entry only to the pseudo palette.
++ */
++static int _setcolreg(struct fb_info *fbi, u_int regno, u_int red, u_int green,
++		u_int blue, u_int transp, int update_hw_pal)
++{
++	/*struct omapfb_info *ofbi = FB2OFB(fbi);*/
++	/*struct omapfb2_device *fbdev = ofbi->fbdev;*/
++	struct fb_var_screeninfo *var = &fbi->var;
++	int r = 0;
++
++	enum omapfb_color_format mode = OMAPFB_COLOR_RGB24U; /* XXX */
++
++	/*switch (plane->color_mode) {*/
++	switch (mode) {
++	case OMAPFB_COLOR_YUV422:
++	case OMAPFB_COLOR_YUV420:
++	case OMAPFB_COLOR_YUY422:
++		r = -EINVAL;
++		break;
++	case OMAPFB_COLOR_CLUT_8BPP:
++	case OMAPFB_COLOR_CLUT_4BPP:
++	case OMAPFB_COLOR_CLUT_2BPP:
++	case OMAPFB_COLOR_CLUT_1BPP:
++		/*
++		   if (fbdev->ctrl->setcolreg)
++		   r = fbdev->ctrl->setcolreg(regno, red, green, blue,
++		   transp, update_hw_pal);
++		   */
++		/* Fallthrough */
++		r = -EINVAL;
++		break;
++	case OMAPFB_COLOR_RGB565:
++	case OMAPFB_COLOR_RGB444:
++	case OMAPFB_COLOR_RGB24P:
++	case OMAPFB_COLOR_RGB24U:
++		if (r != 0)
++			break;
++
++		if (regno < 0) {
++			r = -EINVAL;
++			break;
++		}
++
++		if (regno < 16) {
++			u16 pal;
++			pal = ((red >> (16 - var->red.length)) <<
++					var->red.offset) |
++				((green >> (16 - var->green.length)) <<
++				 var->green.offset) |
++				(blue >> (16 - var->blue.length));
++			((u32 *)(fbi->pseudo_palette))[regno] = pal;
++		}
++		break;
++	default:
++		BUG();
++	}
++	return r;
++}
++
++static int omapfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
++		u_int transp, struct fb_info *info)
++{
++	DBG("setcolreg\n");
++
++	return _setcolreg(info, regno, red, green, blue, transp, 1);
++}
++
++static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
++{
++	int count, index, r;
++	u16 *red, *green, *blue, *transp;
++	u16 trans = 0xffff;
++
++	DBG("setcmap\n");
++
++	red     = cmap->red;
++	green   = cmap->green;
++	blue    = cmap->blue;
++	transp  = cmap->transp;
++	index   = cmap->start;
++
++	for (count = 0; count < cmap->len; count++) {
++		if (transp)
++			trans = *transp++;
++		r = _setcolreg(info, index++, *red++, *green++, *blue++, trans,
++				count == cmap->len - 1);
++		if (r != 0)
++			return r;
++	}
++
++	return 0;
++}
++
++static int omapfb_blank(int blank, struct fb_info *fbi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	int do_update = 0;
++	int r = 0;
++
++	omapfb_lock(fbdev);
++
++	switch (blank) {
++	case FB_BLANK_UNBLANK:
++		if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
++			goto exit;
++
++		if (display->resume)
++			r = display->resume(display);
++
++		if (r == 0 && display->get_update_mode &&
++				display->get_update_mode(display) ==
++				OMAP_DSS_UPDATE_MANUAL)
++			do_update = 1;
++
++		break;
++
++	case FB_BLANK_NORMAL:
++		/* FB_BLANK_NORMAL could be implemented.
++		 * Needs DSS additions. */
++	case FB_BLANK_VSYNC_SUSPEND:
++	case FB_BLANK_HSYNC_SUSPEND:
++	case FB_BLANK_POWERDOWN:
++		if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++			goto exit;
++
++		if (display->suspend)
++			r = display->suspend(display);
++
++		break;
++
++	default:
++		r = -EINVAL;
++	}
++
++exit:
++	omapfb_unlock(fbdev);
++
++	if (r == 0 && do_update && display->update) {
++		u16 w, h;
++		display->get_resolution(display, &w, &h);
++
++		r = display->update(display, 0, 0, w, h);
++	}
++
++	return r;
++}
++
++#if 0
++/* XXX fb_read and fb_write are needed for VRFB */
++ssize_t omapfb_write(struct fb_info *info, const char __user *buf,
++		size_t count, loff_t *ppos)
++{
++	DBG("omapfb_write %d, %lu\n", count, (unsigned long)*ppos);
++	// XXX needed for VRFB
++	return count;
++}
++#endif
++
++static struct fb_ops omapfb_ops = {
++	.owner          = THIS_MODULE,
++	.fb_open        = omapfb_open,
++	.fb_release     = omapfb_release,
++	.fb_fillrect    = cfb_fillrect,
++	.fb_copyarea    = cfb_copyarea,
++	.fb_imageblit   = cfb_imageblit,
++	.fb_blank       = omapfb_blank,
++	.fb_ioctl       = omapfb_ioctl,
++	.fb_check_var   = omapfb_check_var,
++	.fb_set_par     = omapfb_set_par,
++	.fb_pan_display = omapfb_pan_display,
++	.fb_mmap	= omapfb_mmap,
++	.fb_setcolreg	= omapfb_setcolreg,
++	.fb_setcmap	= omapfb_setcmap,
++	//.fb_write	= omapfb_write,
++};
++
++static void omapfb_free_fbmem(struct fb_info *fbi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omapfb2_mem_region *rg;
++
++	rg = &ofbi->region;
++
++	if (rg->paddr)
++		if (omap_vram_free(rg->paddr, rg->size))
++			dev_err(fbdev->dev, "VRAM FREE failed\n");
++
++	if (rg->vaddr)
++		iounmap(rg->vaddr);
++
++	if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++		/* unmap the 0 angle rotation */
++		if (rg->vrfb.vaddr[0]) {
++			iounmap(rg->vrfb.vaddr[0]);
++			omap_vrfb_release_ctx(&rg->vrfb);
++		}
++	}
++
++	rg->vaddr = NULL;
++	rg->paddr = 0;
++	rg->alloc = 0;
++	rg->size = 0;
++}
++
++static int omapfb_free_all_fbmem(struct omapfb2_device *fbdev)
++{
++	int i;
++
++	DBG("free all fbmem\n");
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct fb_info *fbi = fbdev->fbs[i];
++		omapfb_free_fbmem(fbi);
++		memset(&fbi->fix, 0, sizeof(fbi->fix));
++		memset(&fbi->var, 0, sizeof(fbi->var));
++	}
++
++	return 0;
++}
++
++static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
++		unsigned long paddr)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omapfb2_mem_region *rg;
++	void __iomem *vaddr;
++	int r;
++	int clear = 0;
++
++	rg = &ofbi->region;
++	memset(rg, 0, sizeof(*rg));
++
++	size = PAGE_ALIGN(size);
++
++	if (!paddr) {
++		DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
++		r = omap_vram_alloc(OMAPFB_MEMTYPE_SDRAM, size, &paddr);
++		clear = 1;
++	} else {
++		DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
++				ofbi->id);
++		r = omap_vram_reserve(paddr, size);
++	}
++
++	if (r) {
++		dev_err(fbdev->dev, "failed to allocate framebuffer\n");
++		return -ENOMEM;
++	}
++
++	if (ofbi->rotation_type != OMAPFB_ROT_VRFB) {
++		vaddr = ioremap_wc(paddr, size);
++
++		if (!vaddr) {
++			dev_err(fbdev->dev, "failed to ioremap framebuffer\n");
++			omap_vram_free(paddr, size);
++			return -ENOMEM;
++		}
++
++		DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
++
++		if (clear)
++			memset_io(vaddr, 0, size);
++	} else {
++		void __iomem *va;
++
++		r = omap_vrfb_request_ctx(&rg->vrfb);
++		if (r) {
++			dev_err(fbdev->dev, "vrfb create ctx failed\n");
++			return r;
++		}
++
++		/* only ioremap the 0 angle view */
++		va = ioremap_wc(rg->vrfb.paddr[0], size);
++
++		if(!va) {
++			printk(KERN_ERR "vrfb: ioremap failed\n");
++			return -ENOMEM;
++		}
++
++		DBG("ioremapped vrfb area 0 to %p\n", va);
++
++		rg->vrfb.vaddr[0] = va;
++
++		vaddr = NULL;
++
++		if (clear)
++			memset_io(va, 0, size);
++	}
++
++	rg->paddr = paddr;
++	rg->vaddr = vaddr;
++	rg->size = size;
++	rg->alloc = 1;
++
++	return 0;
++}
++
++/* allocate fbmem using display resolution as reference */
++static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
++		unsigned long paddr)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omap_display *display;
++	int bytespp;
++
++	display =  fb2display(fbi);
++
++	if (!display)
++		return 0;
++
++	switch (display->get_recommended_bpp(display)) {
++	case 16:
++		bytespp = 2;
++		break;
++	case 24:
++		bytespp = 4;
++		break;
++	default:
++		bytespp = 4;
++		break;
++	}
++
++	if (!size) {
++		u16 w, h;
++
++		display->get_resolution(display, &w, &h);
++
++		if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++			int oldw = w, oldh = h;
++
++			omap_vrfb_adjust_size(&w, &h, bytespp);
++
++			/* Because we change the resolution of the 0 degree view,
++			 * we need to alloc max(w, h) for height */
++			h = max(w, h);
++			w = OMAP_VRFB_LINE_LEN;
++
++			DBG("adjusting fb mem size for VRFB, %dx%d -> %dx%d\n",
++					oldw, oldh, w, h);
++		}
++
++		size = w * h * bytespp;
++	}
++
++	return omapfb_alloc_fbmem(fbi, size, paddr);
++}
++
++static int omapfb_parse_vram_param(const char *param, int max_entries,
++		unsigned long *sizes, unsigned long *paddrs)
++{
++	int fbnum;
++	unsigned long size;
++	unsigned long paddr = 0;
++	char *p, *start;
++
++	start = (char *)param;
++
++	while (1) {
++		p = start;
++
++		fbnum = simple_strtoul(p, &p, 10);
++
++		if (p == param)
++			return -EINVAL;
++
++		if (*p != ':')
++			return -EINVAL;
++
++		if (fbnum >= max_entries)
++			return -EINVAL;
++
++		size = memparse(p + 1, &p);
++
++		if (!size)
++			return -EINVAL;
++
++		paddr = 0;
++
++		if (*p == '@') {
++			paddr = simple_strtoul(p + 1, &p, 16);
++
++			if (!paddr)
++				return -EINVAL;
++
++		}
++
++		paddrs[fbnum] = paddr;
++		sizes[fbnum] = size;
++
++		if (*p == 0)
++			break;
++
++		if (*p != ',')
++			return -EINVAL;
++
++		++p;
++
++		start = p;
++	}
++
++	return 0;
++}
++
++static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
++{
++	int i, r;
++	unsigned long vram_sizes[10];
++	unsigned long vram_paddrs[10];
++
++	memset(&vram_sizes, 0, sizeof(vram_sizes));
++	memset(&vram_paddrs, 0, sizeof(vram_paddrs));
++
++	if (def_vram &&	omapfb_parse_vram_param(def_vram, 10,
++				vram_sizes, vram_paddrs)) {
++		dev_err(fbdev->dev, "failed to parse vram parameter\n");
++
++		memset(&vram_sizes, 0, sizeof(vram_sizes));
++		memset(&vram_paddrs, 0, sizeof(vram_paddrs));
++	}
++
++	if (fbdev->dev->platform_data) {
++		struct omapfb_platform_data *opd;
++		opd = fbdev->dev->platform_data;
++		for (i = 0; i < opd->mem_desc.region_cnt; ++i) {
++			if (!vram_sizes[i]) {
++				unsigned long size;
++				unsigned long paddr;
++
++				size = opd->mem_desc.region[i].size;
++				paddr = opd->mem_desc.region[i].paddr;
++
++				vram_sizes[i] = size;
++				vram_paddrs[i] = paddr;
++			}
++		}
++	}
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		/* allocate memory automatically only for fb0, or if
++		 * excplicitly defined with vram or plat data option */
++		if (i == 0 || vram_sizes[i] != 0) {
++			r = omapfb_alloc_fbmem_display(fbdev->fbs[i],
++					vram_sizes[i], vram_paddrs[i]);
++
++			if (r)
++				return r;
++		}
++	}
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++		struct omapfb2_mem_region *rg;
++		rg = &ofbi->region;
++
++		DBG("region%d phys %08x virt %p size=%lu\n",
++				i,
++				rg->paddr,
++				rg->vaddr,
++				rg->size);
++	}
++
++	return 0;
++}
++
++int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	struct omapfb2_mem_region *rg = &ofbi->region;
++	unsigned long old_size = rg->size;
++	unsigned long old_paddr = rg->paddr;
++	int old_type = rg->type;
++	int r;
++
++	if (type > OMAPFB_MEMTYPE_MAX)
++		return -EINVAL;
++
++	size = PAGE_ALIGN(size);
++
++	if (old_size == size && old_type == type)
++		return 0;
++
++	if (display && display->sync)
++			display->sync(display);
++
++	omapfb_free_fbmem(fbi);
++
++	if (size == 0) {
++		memset(&fbi->fix, 0, sizeof(fbi->fix));
++		memset(&fbi->var, 0, sizeof(fbi->var));
++		return 0;
++	}
++
++	r = omapfb_alloc_fbmem(fbi, size, 0);
++
++	if (r) {
++		if (old_size)
++			omapfb_alloc_fbmem(fbi, old_size, old_paddr);
++
++		if (rg->size == 0) {
++			memset(&fbi->fix, 0, sizeof(fbi->fix));
++			memset(&fbi->var, 0, sizeof(fbi->var));
++		}
++
++		return r;
++	}
++
++	if (old_size == size)
++		return 0;
++
++	if (old_size == 0) {
++		DBG("initializing fb %d\n", ofbi->id);
++		r = omapfb_fb_init(fbdev, fbi);
++		if (r) {
++			DBG("omapfb_fb_init failed\n");
++			goto err;
++		}
++		r = omapfb_apply_changes(fbi, 1);
++		if (r) {
++			DBG("omapfb_apply_changes failed\n");
++			goto err;
++		}
++	} else {
++		struct fb_var_screeninfo new_var;
++		memcpy(&new_var, &fbi->var, sizeof(new_var));
++		r = check_fb_var(fbi, &new_var);
++		if (r)
++			goto err;
++		memcpy(&fbi->var, &new_var, sizeof(fbi->var));
++		set_fb_fix(fbi);
++	}
++
++	return 0;
++err:
++	omapfb_free_fbmem(fbi);
++	memset(&fbi->fix, 0, sizeof(fbi->fix));
++	memset(&fbi->var, 0, sizeof(fbi->var));
++	return r;
++}
++
++/* initialize fb_info, var, fix to something sane based on the display */
++int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
++{
++	struct fb_var_screeninfo *var = &fbi->var;
++	struct fb_fix_screeninfo *fix = &fbi->fix;
++	struct omap_display *display = fb2display(fbi);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	int r = 0;
++
++	fbi->fbops = &omapfb_ops;
++	fbi->flags = FBINFO_FLAG_DEFAULT;
++	fbi->pseudo_palette = fbdev->pseudo_palette;
++
++	strncpy(fix->id, MODULE_NAME, sizeof(fix->id));
++
++	if (ofbi->region.size == 0) {
++		memset(&fbi->fix, 0, sizeof(fbi->fix));
++		memset(&fbi->var, 0, sizeof(fbi->var));
++		return 0;
++	}
++
++	var->nonstd = 0;
++
++	var->rotate = ofbi->rotation;
++
++	if (display) {
++		u16 w, h;
++		display->get_resolution(display, &w, &h);
++
++		if (ofbi->rotation == FB_ROTATE_CW ||
++				ofbi->rotation == FB_ROTATE_CCW) {
++			var->xres = h;
++			var->yres = w;
++		} else {
++			var->xres = w;
++			var->yres = h;
++		}
++
++		var->xres_virtual = var->xres;
++		var->yres_virtual = var->yres;
++
++		switch (display->get_recommended_bpp(display)) {
++		case 16:
++			var->bits_per_pixel = 16;
++			break;
++		case 24:
++			var->bits_per_pixel = 32;
++			break;
++		default:
++			dev_err(fbdev->dev, "illegal display bpp\n");
++			return -EINVAL;
++		}
++	} else {
++		/* if there's no display, let's just guess some basic values */
++		var->xres = 320;
++		var->yres = 240;
++		var->xres_virtual = var->xres;
++		var->yres_virtual = var->yres;
++		var->bits_per_pixel = 16;
++	}
++
++	r = check_fb_var(fbi, var);
++	if (r)
++		goto err;
++
++	set_fb_fix(fbi);
++err:
++	return r;
++}
++
++static void fbinfo_cleanup(struct omapfb2_device *fbdev, struct fb_info *fbi)
++{
++	fb_dealloc_cmap(&fbi->cmap);
++}
++
++
++static void omapfb_free_resources(struct omapfb2_device *fbdev)
++{
++	int i;
++
++	DBG("free_resources\n");
++
++	if (fbdev == NULL)
++		return;
++
++	for (i = 0; i < fbdev->num_fbs; i++)
++		unregister_framebuffer(fbdev->fbs[i]);
++
++	/* free the reserved fbmem */
++	omapfb_free_all_fbmem(fbdev);
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		fbinfo_cleanup(fbdev, fbdev->fbs[i]);
++		framebuffer_release(fbdev->fbs[i]);
++	}
++
++	for (i = 0; i < fbdev->num_displays; i++) {
++		if (fbdev->displays[i]->state != OMAP_DSS_DISPLAY_DISABLED)
++			fbdev->displays[i]->disable(fbdev->displays[i]);
++
++		omap_dss_put_display(fbdev->displays[i]);
++	}
++
++	dev_set_drvdata(fbdev->dev, NULL);
++	kfree(fbdev);
++}
++
++static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
++{
++	int r, i;
++
++	fbdev->num_fbs = 0;
++
++	DBG("create %d framebuffers\n",	CONFIG_FB_OMAP2_NUM_FBS);
++
++	/* allocate fb_infos */
++	for (i = 0; i < CONFIG_FB_OMAP2_NUM_FBS; i++) {
++		struct fb_info *fbi;
++		struct omapfb_info *ofbi;
++
++		fbi = framebuffer_alloc(sizeof(struct omapfb_info),
++				fbdev->dev);
++
++		if (fbi == NULL) {
++			dev_err(fbdev->dev,
++				"unable to allocate memory for plane info\n");
++			return -ENOMEM;
++		}
++
++		fbdev->fbs[i] = fbi;
++
++		ofbi = FB2OFB(fbi);
++		ofbi->fbdev = fbdev;
++		ofbi->id = i;
++
++		/* assign these early, so that fb alloc can use them */
++		ofbi->rotation_type = def_vrfb ? OMAPFB_ROT_VRFB :
++			OMAPFB_ROT_DMA;
++		ofbi->rotation = def_rotate;
++		ofbi->mirror = def_mirror;
++
++		fbdev->num_fbs++;
++	}
++
++	DBG("fb_infos allocated\n");
++
++	/* assign overlays for the fbs */
++	for (i = 0; i < min(fbdev->num_fbs, fbdev->num_overlays); i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++		ofbi->overlays[0] = fbdev->overlays[i];
++		ofbi->num_overlays = 1;
++	}
++
++	/* allocate fb memories */
++	r = omapfb_allocate_all_fbs(fbdev);
++	if (r) {
++		dev_err(fbdev->dev, "failed to allocate fbmem\n");
++		return r;
++	}
++
++	DBG("fbmems allocated\n");
++
++	/* setup fb_infos */
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		r = omapfb_fb_init(fbdev, fbdev->fbs[i]);
++		if (r) {
++			dev_err(fbdev->dev, "failed to setup fb_info\n");
++			return r;
++		}
++	}
++
++	DBG("fb_infos initialized\n");
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		r = register_framebuffer(fbdev->fbs[i]);
++		if (r != 0) {
++			dev_err(fbdev->dev,
++				"registering framebuffer %d failed\n", i);
++			return r;
++		}
++	}
++
++	DBG("framebuffers registered\n");
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		r = omapfb_apply_changes(fbdev->fbs[i], 1);
++		if (r) {
++			dev_err(fbdev->dev, "failed to change mode\n");
++			return r;
++		}
++	}
++
++	DBG("create sysfs for fbs\n");
++	r = omapfb_create_sysfs(fbdev);
++	if (r) {
++		dev_err(fbdev->dev, "failed to create sysfs entries\n");
++		return r;
++	}
++
++	/* Enable fb0 */
++	if (fbdev->num_fbs > 0) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[0]);
++
++		if (ofbi->num_overlays > 0 ) {
++			struct omap_overlay *ovl = ofbi->overlays[0];
++
++			r = omapfb_overlay_enable(ovl, 1);
++
++			if (r) {
++				dev_err(fbdev->dev,
++						"failed to enable overlay\n");
++				return r;
++			}
++		}
++	}
++
++	DBG("create_framebuffers done\n");
++
++	return 0;
++}
++
++int omapfb_mode_to_timings(const char *mode_str,
++		struct omap_video_timings *timings, u8 *bpp)
++{
++	struct fb_info fbi;
++	struct fb_var_screeninfo var;
++	struct fb_ops fbops;
++	int r;
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++	if (strcmp(mode_str, "pal") == 0) {
++		*timings = omap_dss_pal_timings;
++		*bpp = 0;
++		return 0;
++	} else if (strcmp(mode_str, "ntsc") == 0) {
++		*timings = omap_dss_ntsc_timings;
++		*bpp = 0;
++		return 0;
++	}
++#endif
++
++	/* this is quite a hack, but I wanted to use the modedb and for
++	 * that we need fb_info and var, so we create dummy ones */
++
++	memset(&fbi, 0, sizeof(fbi));
++	memset(&var, 0, sizeof(var));
++	memset(&fbops, 0, sizeof(fbops));
++	fbi.fbops = &fbops;
++
++	r = fb_find_mode(&var, &fbi, mode_str, NULL, 0, NULL, 24);
++
++	if (r != 0) {
++		timings->pixel_clock = PICOS2KHZ(var.pixclock);
++		timings->hfp = var.left_margin;
++		timings->hbp = var.right_margin;
++		timings->vfp = var.upper_margin;
++		timings->vbp = var.lower_margin;
++		timings->hsw = var.hsync_len;
++		timings->vsw = var.vsync_len;
++		timings->x_res = var.xres;
++		timings->y_res = var.yres;
++
++		switch (var.bits_per_pixel) {
++		case 16:
++			*bpp = 16;
++			break;
++		case 24:
++		case 32:
++		default:
++			*bpp = 24;
++			break;
++		}
++
++		return 0;
++	} else {
++		return -EINVAL;
++	}
++}
++
++static int omapfb_set_def_mode(struct omap_display *display, char *mode_str)
++{
++	int r;
++	u8 bpp;
++	struct omap_video_timings timings;
++
++	r = omapfb_mode_to_timings(mode_str, &timings, &bpp);
++	if (r)
++		return r;
++
++	display->panel->recommended_bpp = bpp;
++
++	if (!display->check_timings || !display->set_timings)
++		return -EINVAL;
++
++	r = display->check_timings(display, &timings);
++	if (r)
++		return r;
++
++	display->set_timings(display, &timings);
++
++	return 0;
++}
++
++static int omapfb_parse_def_modes(struct omapfb2_device *fbdev)
++{
++	char *str, *options, *this_opt;
++	int r = 0;
++
++	str = kmalloc(strlen(def_mode) + 1, GFP_KERNEL);
++	strcpy(str, def_mode);
++	options = str;
++
++	while (!r && (this_opt = strsep(&options, ",")) != NULL) {
++		char *p, *display_str, *mode_str;
++		struct omap_display *display;
++		int i;
++
++		p = strchr(this_opt, ':');
++		if (!p) {
++			r = -EINVAL;
++			break;
++		}
++
++		*p = 0;
++		display_str = this_opt;
++		mode_str = p + 1;
++
++		display = NULL;
++		for (i = 0; i < fbdev->num_displays; ++i) {
++			if (strcmp(fbdev->displays[i]->name,
++						display_str) == 0) {
++				display = fbdev->displays[i];
++				break;
++			}
++		}
++
++		if (!display) {
++			r = -EINVAL;
++			break;
++		}
++
++		r = omapfb_set_def_mode(display, mode_str);
++		if (r)
++			break;
++	}
++
++	kfree(str);
++
++	return r;
++}
++
++static int omapfb_probe(struct platform_device *pdev)
++{
++	struct omapfb2_device *fbdev = NULL;
++	int r = 0;
++	int i, t;
++	struct omap_overlay *ovl;
++	struct omap_display *def_display;
++
++	DBG("omapfb_probe\n");
++
++	if (pdev->num_resources != 0) {
++		dev_err(&pdev->dev, "probed for an unknown device\n");
++		r = -ENODEV;
++		goto err0;
++	}
++
++	fbdev = kzalloc(sizeof(struct omapfb2_device), GFP_KERNEL);
++	if (fbdev == NULL) {
++		r = -ENOMEM;
++		goto err0;
++	}
++
++	mutex_init(&fbdev->mtx);
++
++	fbdev->dev = &pdev->dev;
++	platform_set_drvdata(pdev, fbdev);
++
++	fbdev->num_displays = 0;
++	t = omap_dss_get_num_displays();
++	for (i = 0; i < t; i++) {
++		struct omap_display *display;
++		display = omap_dss_get_display(i);
++		if (!display) {
++			dev_err(&pdev->dev, "can't get display %d\n", i);
++			r = -EINVAL;
++			goto cleanup;
++		}
++
++		fbdev->displays[fbdev->num_displays++] = display;
++	}
++
++	if (fbdev->num_displays == 0) {
++		dev_err(&pdev->dev, "no displays\n");
++		r = -EINVAL;
++		goto cleanup;
++	}
++
++	fbdev->num_overlays = omap_dss_get_num_overlays();
++	for (i = 0; i < fbdev->num_overlays; i++)
++		fbdev->overlays[i] = omap_dss_get_overlay(i);
++
++	fbdev->num_managers = omap_dss_get_num_overlay_managers();
++	for (i = 0; i < fbdev->num_managers; i++)
++		fbdev->managers[i] = omap_dss_get_overlay_manager(i);
++
++
++	/* gfx overlay should be the default one. find a display
++	 * connected to that, and use it as default display */
++	ovl = omap_dss_get_overlay(0);
++	if (ovl->manager && ovl->manager->display) {
++		def_display = ovl->manager->display;
++	} else {
++		dev_err(&pdev->dev, "cannot find default display\n");
++		r = -EINVAL;
++		goto cleanup;
++	}
++
++	if (def_mode && strlen(def_mode) > 0) {
++		if (omapfb_parse_def_modes(fbdev))
++			dev_err(&pdev->dev, "cannot parse default modes\n");
++	}
++
++	r = omapfb_create_framebuffers(fbdev);
++	if (r)
++		goto cleanup;
++
++	for (i = 0; i < fbdev->num_managers; i++) {
++		struct omap_overlay_manager *mgr;
++		mgr = fbdev->managers[i];
++		r = mgr->apply(mgr);
++		if (r) {
++			dev_err(fbdev->dev, "failed to apply dispc config\n");
++			goto cleanup;
++		}
++	}
++
++	DBG("mgr->apply'ed\n");
++
++	r = def_display->enable(def_display);
++	if (r) {
++		dev_err(fbdev->dev, "Failed to enable display '%s'\n",
++				def_display->name);
++		goto cleanup;
++	}
++
++	/* set the update mode */
++	if (def_display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
++#ifdef CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE
++		if (def_display->set_update_mode)
++			def_display->set_update_mode(def_display,
++					OMAP_DSS_UPDATE_AUTO);
++		if (def_display->enable_te)
++			def_display->enable_te(def_display, 1);
++#else
++		if (def_display->set_update_mode)
++			def_display->set_update_mode(def_display,
++					OMAP_DSS_UPDATE_MANUAL);
++		if (def_display->enable_te)
++			def_display->enable_te(def_display, 0);
++#endif
++	} else {
++		if (def_display->set_update_mode)
++			def_display->set_update_mode(def_display,
++					OMAP_DSS_UPDATE_AUTO);
++	}
++
++	for (i = 0; i < fbdev->num_displays; i++) {
++		struct omap_display *display = fbdev->displays[i];
++		u16 w, h;
++
++		if (!display->get_update_mode || !display->update)
++			continue;
++
++		if (display->get_update_mode(display) ==
++				OMAP_DSS_UPDATE_MANUAL) {
++
++			display->get_resolution(display, &w, &h);
++			display->update(display, 0, 0, w, h);
++		}
++	}
++
++	DBG("display->updated\n");
++
++	return 0;
++
++cleanup:
++	omapfb_free_resources(fbdev);
++err0:
++	dev_err(&pdev->dev, "failed to setup omapfb\n");
++	return r;
++}
++
++static int omapfb_remove(struct platform_device *pdev)
++{
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++
++	/* FIXME: wait till completion of pending events */
++
++	omapfb_remove_sysfs(fbdev);
++
++	omapfb_free_resources(fbdev);
++
++	return 0;
++}
++
++static struct platform_driver omapfb_driver = {
++	.probe          = omapfb_probe,
++	.remove         = omapfb_remove,
++	.driver         = {
++		.name   = "omapfb",
++		.owner  = THIS_MODULE,
++	},
++};
++
++static int __init omapfb_init(void)
++{
++	DBG("omapfb_init\n");
++
++	if (platform_driver_register(&omapfb_driver)) {
++		printk(KERN_ERR "failed to register omapfb driver\n");
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static void __exit omapfb_exit(void)
++{
++	DBG("omapfb_exit\n");
++	platform_driver_unregister(&omapfb_driver);
++}
++
++module_param_named(mode, def_mode, charp, 0);
++module_param_named(vram, def_vram, charp, 0);
++module_param_named(rotate, def_rotate, int, 0);
++module_param_named(vrfb, def_vrfb, bool, 0);
++module_param_named(mirror, def_mirror, bool, 0);
++
++/* late_initcall to let panel/ctrl drivers loaded first.
++ * I guess better option would be a more dynamic approach,
++ * so that omapfb reacts to new panels when they are loaded */
++late_initcall(omapfb_init);
++/*module_init(omapfb_init);*/
++module_exit(omapfb_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("OMAP2/3 Framebuffer");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+new file mode 100644
+index 0000000..2c88718
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+@@ -0,0 +1,371 @@
++/*
++ * linux/drivers/video/omap2/omapfb-sysfs.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/fb.h>
++#include <linux/sysfs.h>
++#include <linux/device.h>
++#include <linux/uaccess.h>
++#include <linux/platform_device.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/omapfb.h>
++
++#include <mach/display.h>
++#include <mach/vrfb.h>
++
++#include "omapfb.h"
++
++static ssize_t show_rotate_type(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++
++	return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->rotation_type);
++}
++
++static ssize_t show_mirror(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++
++	return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->mirror);
++}
++
++static ssize_t store_mirror(struct device *dev,
++		struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	bool mirror;
++	int r;
++	struct fb_var_screeninfo new_var;
++
++	mirror = simple_strtoul(buf, NULL, 0);
++
++	if (mirror != 0 && mirror != 1)
++		return -EINVAL;
++
++	omapfb_lock(fbdev);
++
++	ofbi->mirror = mirror;
++
++	memcpy(&new_var, &fbi->var, sizeof(new_var));
++	r = check_fb_var(fbi, &new_var);
++	if (r)
++		goto out;
++	memcpy(&fbi->var, &new_var, sizeof(fbi->var));
++
++	set_fb_fix(fbi);
++
++	r = omapfb_apply_changes(fbi, 0);
++	if (r)
++		goto out;
++
++	r = count;
++out:
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static ssize_t show_overlays(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	ssize_t l = 0;
++	int t;
++
++	for (t = 0; t < ofbi->num_overlays; t++) {
++		struct omap_overlay *ovl = ofbi->overlays[t];
++		int ovlnum;
++
++		for (ovlnum = 0; ovlnum < fbdev->num_overlays; ++ovlnum)
++			if (ovl == fbdev->overlays[ovlnum])
++				break;
++
++		l += snprintf(buf + l, PAGE_SIZE - l, "%s%d",
++				t == 0 ? "" : ",", ovlnum);
++	}
++
++	l += snprintf(buf + l, PAGE_SIZE - l, "\n");
++
++	return l;
++}
++
++static struct omapfb_info *get_overlay_fb(struct omapfb2_device *fbdev,
++		struct omap_overlay *ovl)
++{
++	int i, t;
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++		for (t = 0; t < ofbi->num_overlays; t++) {
++			if (ofbi->overlays[t] == ovl)
++				return ofbi;
++		}
++	}
++
++	return NULL;
++}
++
++static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_overlay *ovls[OMAPFB_MAX_OVL_PER_FB];
++	struct omap_overlay *ovl;
++	int num_ovls, r, i;
++	int len;
++
++	num_ovls = 0;
++
++	len = strlen(buf);
++	if (buf[len - 1] == '\n')
++		len = len - 1;
++
++	omapfb_lock(fbdev);
++
++	if (len > 0) {
++		char *p = (char *)buf;
++		int ovlnum;
++
++		while (p < buf + len) {
++			int found;
++			if (num_ovls == OMAPFB_MAX_OVL_PER_FB) {
++				r = -EINVAL;
++				goto out;
++			}
++
++			ovlnum = simple_strtoul(p, &p, 0);
++			if (ovlnum > fbdev->num_overlays) {
++				r = -EINVAL;
++				goto out;
++			}
++
++			found = 0;
++			for (i = 0; i < num_ovls; ++i) {
++				if (ovls[i] == fbdev->overlays[ovlnum]) {
++					found = 1;
++					break;
++				}
++			}
++
++			if (!found)
++				ovls[num_ovls++] = fbdev->overlays[ovlnum];
++
++			p++;
++		}
++	}
++
++	for (i = 0; i < num_ovls; ++i) {
++		struct omapfb_info *ofbi2 = get_overlay_fb(fbdev, ovls[i]);
++		if (ofbi2 && ofbi2 != ofbi) {
++			dev_err(fbdev->dev, "overlay already in use\n");
++			r = -EINVAL;
++			goto out;
++		}
++	}
++
++	/* detach unused overlays */
++	for (i = 0; i < ofbi->num_overlays; ++i) {
++		int t, found;
++
++		ovl = ofbi->overlays[i];
++
++		found = 0;
++
++		for (t = 0; t < num_ovls; ++t) {
++			if (ovl == ovls[t]) {
++				found = 1;
++				break;
++			}
++		}
++
++		if (found)
++			continue;
++
++		DBG("detaching %d\n", ofbi->overlays[i]->id);
++
++		omapfb_overlay_enable(ovl, 0);
++
++		if (ovl->manager)
++			ovl->manager->apply(ovl->manager);
++
++		for (t = i + 1; t < ofbi->num_overlays; t++)
++			ofbi->overlays[t-1] = ofbi->overlays[t];
++
++		ofbi->num_overlays--;
++		i--;
++	}
++
++	for (i = 0; i < num_ovls; ++i) {
++		int t, found;
++
++		ovl = ovls[i];
++
++		found = 0;
++
++		for (t = 0; t < ofbi->num_overlays; ++t) {
++			if (ovl == ofbi->overlays[t]) {
++				found = 1;
++				break;
++			}
++		}
++
++		if (found)
++			continue;
++
++		ofbi->overlays[ofbi->num_overlays++] = ovl;
++
++		r = omapfb_apply_changes(fbi, 1);
++		if (r)
++			goto out;
++
++		if (ovl->manager) {
++			r = ovl->manager->apply(ovl->manager);
++			if (r)
++				goto out;
++		}
++	}
++
++	r = count;
++out:
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static ssize_t show_size(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++
++	return snprintf(buf, PAGE_SIZE, "%lu\n", ofbi->region.size);
++}
++
++static ssize_t store_size(struct device *dev, struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	unsigned long size;
++	int r;
++	int i;
++
++	size = PAGE_ALIGN(simple_strtoul(buf, NULL, 0));
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i]->info.enabled) {
++			r = -EBUSY;
++			goto out;
++		}
++	}
++
++	if (size != ofbi->region.size) {
++		r = omapfb_realloc_fbmem(fbi, size, ofbi->region.type);
++		if (r) {
++			dev_err(dev, "realloc fbmem failed\n");
++			goto out;
++		}
++	}
++
++	r = count;
++out:
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static ssize_t show_phys(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++
++	return snprintf(buf, PAGE_SIZE, "%0x\n", ofbi->region.paddr);
++}
++
++static ssize_t show_virt(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++
++	return snprintf(buf, PAGE_SIZE, "%p\n", ofbi->region.vaddr);
++}
++
++static struct device_attribute omapfb_attrs[] = {
++	__ATTR(rotate_type, S_IRUGO, show_rotate_type, NULL),
++	__ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror),
++	__ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size),
++	__ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays),
++	__ATTR(phys_addr, S_IRUGO, show_phys, NULL),
++	__ATTR(virt_addr, S_IRUGO, show_virt, NULL),
++};
++
++int omapfb_create_sysfs(struct omapfb2_device *fbdev)
++{
++	int i;
++	int r;
++
++	DBG("create sysfs for fbs\n");
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		int t;
++		for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++) {
++			r = device_create_file(fbdev->fbs[i]->dev,
++					&omapfb_attrs[t]);
++
++			if (r) {
++				dev_err(fbdev->dev, "failed to create sysfs file\n");
++				return r;
++			}
++		}
++	}
++
++	return 0;
++}
++
++void omapfb_remove_sysfs(struct omapfb2_device *fbdev)
++{
++	int i, t;
++
++	DBG("remove sysfs for fbs\n");
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++)
++			device_remove_file(fbdev->fbs[i]->dev,
++					&omapfb_attrs[t]);
++	}
++}
++
+diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
+new file mode 100644
+index 0000000..65e9e6e
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/omapfb.h
+@@ -0,0 +1,153 @@
++/*
++ * linux/drivers/video/omap2/omapfb.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
++#define __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
++
++#ifdef CONFIG_FB_OMAP2_DEBUG_SUPPORT
++#define DEBUG
++#endif
++
++#ifdef DEBUG
++extern unsigned int omapfb_debug;
++#define DBG(format, ...) \
++	if (omapfb_debug) \
++		printk(KERN_DEBUG "OMAPFB: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define FB2OFB(fb_info) ((struct omapfb_info *)(fb_info->par))
++
++/* max number of overlays to which a framebuffer data can be direct */
++#define OMAPFB_MAX_OVL_PER_FB 3
++
++struct omapfb2_mem_region {
++	u32		paddr;
++	void __iomem	*vaddr;
++	struct vrfb	vrfb;
++	unsigned long	size;
++	u8		type;		/* OMAPFB_PLANE_MEM_* */
++	bool		alloc;		/* allocated by the driver */
++	bool		map;		/* kernel mapped by the driver */
++};
++
++enum omapfb_rotation_type {
++	OMAPFB_ROT_DMA = 0,
++	OMAPFB_ROT_VRFB = 1,
++};
++
++/* appended to fb_info */
++struct omapfb_info {
++	int id;
++	struct omapfb2_mem_region region;
++	atomic_t map_count;
++	int num_overlays;
++	struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB];
++	struct omapfb2_device *fbdev;
++	enum omapfb_rotation_type rotation_type;
++	u8 rotation;
++	bool mirror;
++};
++
++struct omapfb2_device {
++	struct device *dev;
++	struct mutex  mtx;
++
++	u32 pseudo_palette[17];
++
++	int state;
++
++	unsigned num_fbs;
++	struct fb_info *fbs[10];
++
++	unsigned num_displays;
++	struct omap_display *displays[10];
++	unsigned num_overlays;
++	struct omap_overlay *overlays[10];
++	unsigned num_managers;
++	struct omap_overlay_manager *managers[10];
++};
++
++struct omapfb_colormode {
++	enum omap_color_mode dssmode;
++	u32 bits_per_pixel;
++	u32 nonstd;
++	struct fb_bitfield red;
++	struct fb_bitfield green;
++	struct fb_bitfield blue;
++	struct fb_bitfield transp;
++};
++
++u32 omapfb_get_region_paddr(struct omapfb_info *ofbi);
++void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi);
++
++void set_fb_fix(struct fb_info *fbi);
++int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var);
++int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type);
++int omapfb_apply_changes(struct fb_info *fbi, int init);
++int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi);
++
++int omapfb_create_sysfs(struct omapfb2_device *fbdev);
++void omapfb_remove_sysfs(struct omapfb2_device *fbdev);
++
++int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg);
++
++int omapfb_mode_to_timings(const char *mode_str,
++		struct omap_video_timings *timings, u8 *bpp);
++
++/* find the display connected to this fb, if any */
++static inline struct omap_display *fb2display(struct fb_info *fbi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	int i;
++
++	/* XXX: returns the display connected to first attached overlay */
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i]->manager)
++			return ofbi->overlays[i]->manager->display;
++	}
++
++	return NULL;
++}
++
++static inline void omapfb_lock(struct omapfb2_device *fbdev)
++{
++	mutex_lock(&fbdev->mtx);
++}
++
++static inline void omapfb_unlock(struct omapfb2_device *fbdev)
++{
++	mutex_unlock(&fbdev->mtx);
++}
++
++static inline int omapfb_overlay_enable(struct omap_overlay *ovl,
++		int enable)
++{
++	struct omap_overlay_info info;
++
++	ovl->get_overlay_info(ovl, &info);
++	info.enabled = enable;
++	return ovl->set_overlay_info(ovl, &info);
++}
++
++#endif
+diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
+index b226bdf..96190b2 100644
+--- a/include/linux/omapfb.h
++++ b/include/linux/omapfb.h
+@@ -50,6 +50,8 @@
+ #define OMAPFB_UPDATE_WINDOW	OMAP_IOW(54, struct omapfb_update_window)
+ #define OMAPFB_SETUP_MEM	OMAP_IOW(55, struct omapfb_mem_info)
+ #define OMAPFB_QUERY_MEM	OMAP_IOW(56, struct omapfb_mem_info)
++#define OMAPFB_WAITFORVSYNC	OMAP_IO(57)
++#define OMAPFB_MEMORY_READ	OMAP_IOR(58, struct omapfb_memory_read)
+ 
+ #define OMAPFB_CAPS_GENERIC_MASK	0x00000fff
+ #define OMAPFB_CAPS_LCDC_MASK		0x00fff000
+@@ -90,6 +92,13 @@ enum omapfb_color_format {
+ 	OMAPFB_COLOR_CLUT_1BPP,
+ 	OMAPFB_COLOR_RGB444,
+ 	OMAPFB_COLOR_YUY422,
++
++	OMAPFB_COLOR_ARGB16,
++	OMAPFB_COLOR_RGB24U,	/* RGB24, 32-bit container */
++	OMAPFB_COLOR_RGB24P,	/* RGB24, 24-bit container */
++	OMAPFB_COLOR_ARGB32,
++	OMAPFB_COLOR_RGBA32,
++	OMAPFB_COLOR_RGBX32,
+ };
+ 
+ struct omapfb_update_window {
+@@ -161,6 +170,15 @@ enum omapfb_update_mode {
+ 	OMAPFB_MANUAL_UPDATE
+ };
+ 
++struct omapfb_memory_read {
++	__u16 x;
++	__u16 y;
++	__u16 w;
++	__u16 h;
++	size_t buffer_size;
++	void __user *buffer;
++};
++
+ #ifdef __KERNEL__
+ 
+ #include <linux/completion.h>
+@@ -376,6 +394,8 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
+ extern struct lcd_ctrl omap2_disp_ctrl;
+ #endif
+ 
++extern void omapfb_set_platform_data(struct omapfb_platform_data *data);
++
+ extern void omapfb_reserve_sdram(void);
+ extern void omapfb_register_panel(struct lcd_panel *panel);
+ extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0005-DSS2-Add-panel-drivers.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0005-DSS2-Add-panel-drivers.patch
new file mode 100644
index 0000000000..c68c89e171
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0005-DSS2-Add-panel-drivers.patch
@@ -0,0 +1,396 @@
+From 4cc0368574f587f448231ccd121266bed4bf9729 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 10:29:56 +0300
+Subject: [PATCH 05/69] DSS2: Add panel drivers
+
+- Generic panel
+- Samsung LTE430WQ-F0C LCD Panel
+- Sharp LS037V7DW01 LCD Panel
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/displays/Kconfig               |   21 ++++
+ drivers/video/omap2/displays/Makefile              |    3 +
+ drivers/video/omap2/displays/panel-generic.c       |   96 +++++++++++++++++
+ .../omap2/displays/panel-samsung-lte430wq-f0c.c    |  108 +++++++++++++++++++
+ .../video/omap2/displays/panel-sharp-ls037v7dw01.c |  112 ++++++++++++++++++++
+ 5 files changed, 340 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/displays/Kconfig
+ create mode 100644 drivers/video/omap2/displays/Makefile
+ create mode 100644 drivers/video/omap2/displays/panel-generic.c
+ create mode 100644 drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
+ create mode 100644 drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+
+diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
+new file mode 100644
+index 0000000..0419ec8
+--- /dev/null
++++ b/drivers/video/omap2/displays/Kconfig
+@@ -0,0 +1,21 @@
++menu "OMAP2/3 Display Device Drivers"
++        depends on OMAP2_DSS
++
++config PANEL_GENERIC
++        tristate "Generic Panel"
++        help
++	  Generic panel driver.
++	  Used for DVI output for Beagle and OMAP3 SDP.
++
++config PANEL_SAMSUNG_LTE430WQ_F0C
++        tristate "Samsung LTE430WQ-F0C LCD Panel"
++        depends on OMAP2_DSS
++        help
++          LCD Panel used on Overo Palo43
++
++config PANEL_SHARP_LS037V7DW01
++        tristate "Sharp LS037V7DW01 LCD Panel"
++        depends on OMAP2_DSS
++        help
++          LCD Panel used in TI's SDP3430 and EVM boards
++endmenu
+diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
+new file mode 100644
+index 0000000..a26bbd2
+--- /dev/null
++++ b/drivers/video/omap2/displays/Makefile
+@@ -0,0 +1,3 @@
++obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
++obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
++obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
+diff --git a/drivers/video/omap2/displays/panel-generic.c b/drivers/video/omap2/displays/panel-generic.c
+new file mode 100644
+index 0000000..8382acb
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-generic.c
+@@ -0,0 +1,96 @@
++/*
++ * Generic panel support
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int generic_panel_init(struct omap_display *display)
++{
++	return 0;
++}
++
++static int generic_panel_enable(struct omap_display *display)
++{
++	int r = 0;
++
++	if (display->hw_config.panel_enable)
++		r = display->hw_config.panel_enable(display);
++
++	return r;
++}
++
++static void generic_panel_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++}
++
++static int generic_panel_suspend(struct omap_display *display)
++{
++	generic_panel_disable(display);
++	return 0;
++}
++
++static int generic_panel_resume(struct omap_display *display)
++{
++	return generic_panel_enable(display);
++}
++
++static struct omap_panel generic_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "panel-generic",
++	.init		= generic_panel_init,
++	.enable		= generic_panel_enable,
++	.disable	= generic_panel_disable,
++	.suspend	= generic_panel_suspend,
++	.resume		= generic_panel_resume,
++
++	.timings = {
++		/* 640 x 480 @ 60 Hz  Reduced blanking VESA CVT 0.31M3-R */
++		.x_res		= 640,
++		.y_res		= 480,
++		.pixel_clock	= 23500,
++		.hfp		= 48,
++		.hsw		= 32,
++		.hbp		= 80,
++		.vfp		= 3,
++		.vsw		= 4,
++		.vbp		= 7,
++	},
++
++	.config		= OMAP_DSS_LCD_TFT,
++};
++
++
++static int __init generic_panel_drv_init(void)
++{
++	omap_dss_register_panel(&generic_panel);
++	return 0;
++}
++
++static void __exit generic_panel_drv_exit(void)
++{
++	omap_dss_unregister_panel(&generic_panel);
++}
++
++module_init(generic_panel_drv_init);
++module_exit(generic_panel_drv_exit);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
+new file mode 100644
+index 0000000..e4bb781
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
+@@ -0,0 +1,108 @@
++/*
++ * LCD panel driver for Samsung LTE430WQ-F0C
++ *
++ * Author: Steve Sakoman <steve@sakoman.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int samsung_lte_panel_init(struct omap_display *display)
++{
++	return 0;
++}
++
++static void samsung_lte_panel_cleanup(struct omap_display *display)
++{
++}
++
++static int samsung_lte_panel_enable(struct omap_display *display)
++{
++	int r = 0;
++
++	/* wait couple of vsyncs until enabling the LCD */
++	msleep(50);
++
++	if (display->hw_config.panel_enable)
++		r = display->hw_config.panel_enable(display);
++
++	return r;
++}
++
++static void samsung_lte_panel_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++
++	/* wait at least 5 vsyncs after disabling the LCD */
++	msleep(100);
++}
++
++static int samsung_lte_panel_suspend(struct omap_display *display)
++{
++	samsung_lte_panel_disable(display);
++	return 0;
++}
++
++static int samsung_lte_panel_resume(struct omap_display *display)
++{
++	return samsung_lte_panel_enable(display);
++}
++
++static struct omap_panel samsung_lte_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "samsung-lte430wq-f0c",
++	.init		= samsung_lte_panel_init,
++	.cleanup	= samsung_lte_panel_cleanup,
++	.enable		= samsung_lte_panel_enable,
++	.disable	= samsung_lte_panel_disable,
++	.suspend	= samsung_lte_panel_suspend,
++	.resume		= samsung_lte_panel_resume,
++
++	.timings = {
++		.x_res = 480,
++		.y_res = 272,
++
++		.pixel_clock	= 9200,
++
++		.hsw		= 41,
++		.hfp		= 8,
++		.hbp		= 45-41,
++
++		.vsw		= 10,
++		.vfp		= 4,
++		.vbp		= 12-10,
++	},
++
++	.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IVS,
++};
++
++
++static int __init samsung_lte_panel_drv_init(void)
++{
++	omap_dss_register_panel(&samsung_lte_panel);
++	return 0;
++}
++
++static void __exit samsung_lte_panel_drv_exit(void)
++{
++	omap_dss_unregister_panel(&samsung_lte_panel);
++}
++
++module_init(samsung_lte_panel_drv_init);
++module_exit(samsung_lte_panel_drv_exit);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+new file mode 100644
+index 0000000..1f99150
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+@@ -0,0 +1,112 @@
++/*
++ * LCD panel driver for Sharp LS037V7DW01
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int sharp_ls_panel_init(struct omap_display *display)
++{
++	return 0;
++}
++
++static void sharp_ls_panel_cleanup(struct omap_display *display)
++{
++}
++
++static int sharp_ls_panel_enable(struct omap_display *display)
++{
++	int r = 0;
++
++	/* wait couple of vsyncs until enabling the LCD */
++	msleep(50);
++
++	if (display->hw_config.panel_enable)
++		r = display->hw_config.panel_enable(display);
++
++	return r;
++}
++
++static void sharp_ls_panel_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++
++	/* wait at least 5 vsyncs after disabling the LCD */
++
++	msleep(100);
++}
++
++static int sharp_ls_panel_suspend(struct omap_display *display)
++{
++	sharp_ls_panel_disable(display);
++	return 0;
++}
++
++static int sharp_ls_panel_resume(struct omap_display *display)
++{
++	return sharp_ls_panel_enable(display);
++}
++
++static struct omap_panel sharp_ls_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "sharp-ls037v7dw01",
++	.init		= sharp_ls_panel_init,
++	.cleanup	= sharp_ls_panel_cleanup,
++	.enable		= sharp_ls_panel_enable,
++	.disable	= sharp_ls_panel_disable,
++	.suspend	= sharp_ls_panel_suspend,
++	.resume		= sharp_ls_panel_resume,
++
++	.timings = {
++		.x_res = 480,
++		.y_res = 640,
++
++		.pixel_clock	= 19200,
++
++		.hsw		= 2,
++		.hfp		= 1,
++		.hbp		= 28,
++
++		.vsw		= 1,
++		.vfp		= 1,
++		.vbp		= 1,
++	},
++
++	.acb		= 0x28,
++
++	.config	= OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |	OMAP_DSS_LCD_IHS,
++};
++
++
++static int __init sharp_ls_panel_drv_init(void)
++{
++	omap_dss_register_panel(&sharp_ls_panel);
++	return 0;
++}
++
++static void __exit sharp_ls_panel_drv_exit(void)
++{
++	omap_dss_unregister_panel(&sharp_ls_panel);
++}
++
++module_init(sharp_ls_panel_drv_init);
++module_exit(sharp_ls_panel_drv_exit);
++MODULE_LICENSE("GPL");
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch
new file mode 100644
index 0000000000..258b0b6531
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch
@@ -0,0 +1,1079 @@
+From 18a25382e81c03230e022ca2eb7e0fce24479d6a Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 10:31:57 +0300
+Subject: [PATCH 06/69] DSS2: HACK: Add DSS2 support for N800
+
+Works, but it an ugly quick hack.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/mach-omap2/board-n800.c             |  216 +++++++++++---
+ drivers/video/omap2/displays/Kconfig         |   10 +
+ drivers/video/omap2/displays/Makefile        |    3 +
+ drivers/video/omap2/displays/ctrl-blizzard.c |  279 +++++++++++++++++
+ drivers/video/omap2/displays/panel-n800.c    |  435 ++++++++++++++++++++++++++
+ 5 files changed, 905 insertions(+), 38 deletions(-)
+ create mode 100644 drivers/video/omap2/displays/ctrl-blizzard.c
+ create mode 100644 drivers/video/omap2/displays/panel-n800.c
+
+diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
+index f6f6571..6de60ae 100644
+--- a/arch/arm/mach-omap2/board-n800.c
++++ b/arch/arm/mach-omap2/board-n800.c
+@@ -41,6 +41,8 @@
+ #include <mach/clock.h>
+ #include <mach/gpio-switch.h>
+ #include <mach/blizzard.h>
++#include <mach/display.h>
++#include <mach/vram.h>
+ 
+ #include <../drivers/cbus/tahvo.h>
+ #include <../drivers/media/video/tcm825x.h>
+@@ -161,23 +163,176 @@ static struct omap_uart_config n800_uart_config __initdata = {
+ 
+ #include "../../../drivers/cbus/retu.h"
+ 
+-static struct omap_fbmem_config n800_fbmem0_config __initdata = {
+-	.size = 752 * 1024,
++static struct omap_tmp105_config n800_tmp105_config __initdata = {
++	.tmp105_irq_pin = 125,
++	.set_power = n800_tmp105_set_power,
+ };
+ 
+-static struct omap_fbmem_config n800_fbmem1_config __initdata = {
+-	.size = 752 * 1024,
+-};
+ 
+-static struct omap_fbmem_config n800_fbmem2_config __initdata = {
+-	.size = 752 * 1024,
++
++
++/* DISPLAY */
++static struct {
++	struct clk *sys_ck;
++} blizzard;
++
++static int blizzard_get_clocks(void)
++{
++	blizzard.sys_ck = clk_get(0, "osc_ck");
++	if (IS_ERR(blizzard.sys_ck)) {
++		printk(KERN_ERR "can't get Blizzard clock\n");
++		return PTR_ERR(blizzard.sys_ck);
++	}
++	return 0;
++}
++
++static unsigned long blizzard_get_clock_rate(void)
++{
++	return clk_get_rate(blizzard.sys_ck);
++}
++
++static int n800_pn800_enable(struct omap_display *display)
++{
++	if (display->hw_config.panel_reset_gpio != -1) {
++		printk("enabling panel gpio\n");
++		gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
++	}
++
++	return 0;
++}
++
++static void n800_pn800_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_reset_gpio != -1) {
++		printk("disabling panel gpio\n");
++		gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
++		msleep(120);
++	}
++}
++
++static int n800_blizzard_enable(struct omap_display *display)
++{
++	printk("enabling bliz powers\n");
++
++	/* Vcore to 1.475V */
++	tahvo_set_clear_reg_bits(0x07, 0, 0xf);
++	msleep(10);
++
++	clk_enable(blizzard.sys_ck);
++
++	if (display->hw_config.ctrl_reset_gpio != -1)
++		gpio_direction_output(display->hw_config.ctrl_reset_gpio, 1);
++
++	printk("osc_ck %lu\n", blizzard_get_clock_rate());
++
++	return 0;
++}
++
++static void n800_blizzard_disable(struct omap_display *display)
++{
++	printk("disabling bliz powers\n");
++
++	if (display->hw_config.ctrl_reset_gpio != -1)
++		gpio_direction_output(display->hw_config.ctrl_reset_gpio, 0);
++
++	clk_disable(blizzard.sys_ck);
++
++	/* Vcore to 1.005V */
++	tahvo_set_clear_reg_bits(0x07, 0xf, 0);
++}
++
++static int n800_set_backlight_level(struct omap_display *display, int level)
++{
++	return 0;
++}
++
++static struct omap_dss_display_config n800_dsi_display_data = {
++	.type = OMAP_DISPLAY_TYPE_DBI,
++	.name = "lcd",
++	.ctrl_name = "ctrl-blizzard",
++	.panel_name = "panel-pn800",
++	.panel_reset_gpio = -1,
++	.ctrl_reset_gpio = N800_BLIZZARD_POWERDOWN_GPIO,
++	.panel_enable = n800_pn800_enable,
++	.panel_disable = n800_pn800_disable,
++	.ctrl_enable = n800_blizzard_enable,
++	.ctrl_disable = n800_blizzard_disable,
++	.set_backlight = n800_set_backlight_level,
++	.u.rfbi = {
++		.channel = 0,
++		/* 8 for cmd mode, 16 for pixel data. ctrl-blizzard handles switching */
++		.data_lines = 8,
++	},
++	.panel_data = 0, // XXX used for panel datalines
++};
++static struct omap_dss_board_info n800_dss_data = {
++	.num_displays = 1,
++	.displays = {
++		&n800_dsi_display_data,
++	},
+ };
+ 
+-static struct omap_tmp105_config n800_tmp105_config __initdata = {
+-	.tmp105_irq_pin = 125,
+-	.set_power = n800_tmp105_set_power,
++static struct platform_device n800_dss_device = {
++	.name          = "omapdss",
++	.id            = -1,
++	.dev            = {
++		.platform_data = &n800_dss_data,
++	},
+ };
+ 
++static void __init n800_display_init(void)
++{
++	int r;
++	const struct omap_lcd_config *conf;
++
++	conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
++	if (conf != NULL) {
++		n800_dsi_display_data.panel_reset_gpio = conf->nreset_gpio;
++		n800_dsi_display_data.panel_data =
++			(void*)(u32)conf->data_lines; // XXX
++		//printk("\n\nTULI %d\n\n", conf->data_lines);
++	} else {
++		printk("\n\nEI TULLU MIOTÄÄÄ\n\n");
++	}
++
++	blizzard_get_clocks();
++	clk_enable(blizzard.sys_ck); // XXX always enable
++
++	//omapfb_set_ctrl_platform_data(&n800_blizzard_data);
++	//
++	if (n800_dsi_display_data.ctrl_reset_gpio != -1) {
++		r = gpio_request(n800_dsi_display_data.ctrl_reset_gpio,
++				"Blizzard pd");
++		if (r < 0) {
++			n800_dsi_display_data.ctrl_reset_gpio = -1;
++			printk(KERN_ERR "Unable to get Blizzard GPIO\n");
++		} else {
++			gpio_direction_output(n800_dsi_display_data.ctrl_reset_gpio,
++					1);
++			// XXX always enable
++		}
++	}
++
++	if (n800_dsi_display_data.panel_reset_gpio != -1) {
++		r = gpio_request(n800_dsi_display_data.panel_reset_gpio,
++				"panel reset");
++		if (r < 0) {
++			n800_dsi_display_data.panel_reset_gpio = -1;
++			printk(KERN_ERR "Unable to get pn800 GPIO\n");
++		} else {
++			gpio_direction_output(n800_dsi_display_data.panel_reset_gpio,
++					1);
++			// XXX always enable
++		}
++	}
++}
++
++/* DISPLAY END */
++
++
++
++
++
+ static void mipid_shutdown(struct mipid_platform_data *pdata)
+ {
+ 	if (pdata->nreset_gpio != -1) {
+@@ -191,6 +346,7 @@ static struct mipid_platform_data n800_mipid_platform_data = {
+ 	.shutdown = mipid_shutdown,
+ };
+ 
++#if 0
+ static void __init mipid_dev_init(void)
+ {
+ 	const struct omap_lcd_config *conf;
+@@ -201,26 +357,9 @@ static void __init mipid_dev_init(void)
+ 		n800_mipid_platform_data.data_lines = conf->data_lines;
+ 	}
+ }
++#endif
+ 
+-static struct {
+-	struct clk *sys_ck;
+-} blizzard;
+-
+-static int blizzard_get_clocks(void)
+-{
+-	blizzard.sys_ck = clk_get(0, "osc_ck");
+-	if (IS_ERR(blizzard.sys_ck)) {
+-		printk(KERN_ERR "can't get Blizzard clock\n");
+-		return PTR_ERR(blizzard.sys_ck);
+-	}
+-	return 0;
+-}
+-
+-static unsigned long blizzard_get_clock_rate(struct device *dev)
+-{
+-	return clk_get_rate(blizzard.sys_ck);
+-}
+-
++#if 0
+ static void blizzard_enable_clocks(int enable)
+ {
+ 	if (enable)
+@@ -265,14 +404,12 @@ static void __init blizzard_dev_init(void)
+ 	gpio_direction_output(N800_BLIZZARD_POWERDOWN_GPIO, 1);
+ 
+ 	blizzard_get_clocks();
+-	omapfb_set_ctrl_platform_data(&n800_blizzard_data);
++	//omapfb_set_ctrl_platform_data(&n800_blizzard_data);
+ }
++#endif
+ 
+ static struct omap_board_config_kernel n800_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	                &n800_uart_config },
+-	{ OMAP_TAG_FBMEM,			&n800_fbmem0_config },
+-	{ OMAP_TAG_FBMEM,			&n800_fbmem1_config },
+-	{ OMAP_TAG_FBMEM,			&n800_fbmem2_config },
+ 	{ OMAP_TAG_TMP105,			&n800_tmp105_config },
+ };
+ 
+@@ -379,7 +516,7 @@ static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
+ 
+ static struct spi_board_info n800_spi_board_info[] __initdata = {
+ 	{
+-		.modalias	= "lcd_mipid",
++		.modalias	= "panel-n800",
+ 		.bus_num	= 1,
+ 		.chip_select	= 1,
+ 		.max_speed_hz	= 4000000,
+@@ -404,7 +541,7 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
+ 
+ static struct spi_board_info n810_spi_board_info[] __initdata = {
+ 	{
+-		.modalias	 = "lcd_mipid",
++		.modalias	 = "panel-n800",
+ 		.bus_num	 = 1,
+ 		.chip_select	 = 1,
+ 		.max_speed_hz	 = 4000000,
+@@ -582,6 +719,7 @@ static struct platform_device *n800_devices[] __initdata = {
+ #if defined(CONFIG_CBUS_RETU_HEADSET)
+ 	&retu_headset_device,
+ #endif
++	&n800_dss_device,
+ };
+ 
+ #ifdef CONFIG_MENELAUS
+@@ -713,9 +851,10 @@ void __init nokia_n800_common_init(void)
+ 	if (machine_is_nokia_n810())
+ 		i2c_register_board_info(2, n810_i2c_board_info_2,
+ 			ARRAY_SIZE(n810_i2c_board_info_2));
+-		
+-	mipid_dev_init();
+-	blizzard_dev_init();
++
++	//mipid_dev_init();
++	//blizzard_dev_init();
++	n800_display_init();
+ }
+ 
+ static void __init nokia_n800_init(void)
+@@ -735,6 +874,7 @@ void __init nokia_n800_map_io(void)
+ 	omap_board_config_size = ARRAY_SIZE(n800_config);
+ 
+ 	omap2_set_globals_242x();
++	omap2_set_sdram_vram(800 * 480 * 2 * 3, 0);
+ 	omap2_map_common_io();
+ }
+ 
+diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
+index 0419ec8..356ceb1 100644
+--- a/drivers/video/omap2/displays/Kconfig
++++ b/drivers/video/omap2/displays/Kconfig
+@@ -18,4 +18,14 @@ config PANEL_SHARP_LS037V7DW01
+         depends on OMAP2_DSS
+         help
+           LCD Panel used in TI's SDP3430 and EVM boards
++
++config PANEL_N800
++        tristate "Panel N8x0"
++        help
++          N8x0 LCD (hack)
++
++config CTRL_BLIZZARD
++        tristate "Blizzard Controller"
++        help
++          Blizzard Controller (hack)
+ endmenu
+diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
+index a26bbd2..1b74b7e 100644
+--- a/drivers/video/omap2/displays/Makefile
++++ b/drivers/video/omap2/displays/Makefile
+@@ -1,3 +1,6 @@
+ obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
+ obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
+ obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
++
++obj-$(CONFIG_CTRL_BLIZZARD) += ctrl-blizzard.o
++obj-$(CONFIG_PANEL_N800) += panel-n800.o
+diff --git a/drivers/video/omap2/displays/ctrl-blizzard.c b/drivers/video/omap2/displays/ctrl-blizzard.c
+new file mode 100644
+index 0000000..6698e4d
+--- /dev/null
++++ b/drivers/video/omap2/displays/ctrl-blizzard.c
+@@ -0,0 +1,279 @@
++
++//#define DEBUG
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++
++#include <mach/display.h>
++#include <mach/dma.h>
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "Blizzard: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define BLIZZARD_REV_CODE			0x00
++#define BLIZZARD_CONFIG				0x02
++#define BLIZZARD_PLL_DIV			0x04
++#define BLIZZARD_PLL_LOCK_RANGE			0x06
++#define BLIZZARD_PLL_CLOCK_SYNTH_0		0x08
++#define BLIZZARD_PLL_CLOCK_SYNTH_1		0x0a
++#define BLIZZARD_PLL_MODE			0x0c
++#define BLIZZARD_CLK_SRC			0x0e
++#define BLIZZARD_MEM_BANK0_ACTIVATE		0x10
++#define BLIZZARD_MEM_BANK0_STATUS		0x14
++#define BLIZZARD_PANEL_CONFIGURATION		0x28
++#define BLIZZARD_HDISP				0x2a
++#define BLIZZARD_HNDP				0x2c
++#define BLIZZARD_VDISP0				0x2e
++#define BLIZZARD_VDISP1				0x30
++#define BLIZZARD_VNDP				0x32
++#define BLIZZARD_HSW				0x34
++#define BLIZZARD_VSW				0x38
++#define BLIZZARD_DISPLAY_MODE			0x68
++#define BLIZZARD_INPUT_WIN_X_START_0		0x6c
++#define BLIZZARD_DATA_SOURCE_SELECT		0x8e
++#define BLIZZARD_DISP_MEM_DATA_PORT		0x90
++#define BLIZZARD_DISP_MEM_READ_ADDR0		0x92
++#define BLIZZARD_POWER_SAVE			0xE6
++#define BLIZZARD_NDISP_CTRL_STATUS		0xE8
++
++/* Data source select */
++/* For S1D13745 */
++#define BLIZZARD_SRC_WRITE_LCD_BACKGROUND	0x00
++#define BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE	0x01
++#define BLIZZARD_SRC_WRITE_OVERLAY_ENABLE	0x04
++#define BLIZZARD_SRC_DISABLE_OVERLAY		0x05
++/* For S1D13744 */
++#define BLIZZARD_SRC_WRITE_LCD			0x00
++#define BLIZZARD_SRC_BLT_LCD			0x06
++
++#define BLIZZARD_COLOR_RGB565			0x01
++#define BLIZZARD_COLOR_YUV420			0x09
++
++#define BLIZZARD_VERSION_S1D13745		0x01	/* Hailstorm */
++#define BLIZZARD_VERSION_S1D13744		0x02	/* Blizzard */
++
++#define BLIZZARD_AUTO_UPDATE_TIME		(HZ / 20)
++
++
++
++static struct {
++	int			version;
++} blizzard;
++
++
++static inline void blizzard_cmd(u8 cmd)
++{
++        omap_rfbi_write_command(&cmd, 1);
++}
++
++static inline void blizzard_write(u8 cmd, const u8 *buf, int len)
++{
++        omap_rfbi_write_command(&cmd, 1);
++        omap_rfbi_write_data(buf, len);
++}
++
++static inline void blizzard_read(u8 cmd, u8 *buf, int len)
++{
++        omap_rfbi_write_command(&cmd, 1);
++        omap_rfbi_read_data(buf, len);
++}
++
++static u8 blizzard_read_reg(u8 cmd)
++{
++	u8 data;
++	blizzard_read(cmd, &data, 1);
++	return data;
++}
++
++static int blizzard_ctrl_init(struct omap_display *display)
++{
++	DBG("blizzard_ctrl_init\n");
++
++	return 0;
++}
++
++
++static int blizzard_ctrl_enable(struct omap_display *display)
++{
++	int r = 0;
++	u8 rev, conf;
++
++	DBG("blizzard_ctrl_enable\n");
++
++	if (display->hw_config.ctrl_enable) {
++		r = display->hw_config.ctrl_enable(display);
++		if (r)
++			return r;
++	}
++
++	msleep(100);
++
++	rev = blizzard_read_reg(BLIZZARD_CLK_SRC);
++	printk("CLK_SRC %x\n", rev);
++
++	rev = blizzard_read_reg(BLIZZARD_PLL_DIV);
++	printk("PLLDIV %x\n", rev);
++
++	rev = blizzard_read_reg(BLIZZARD_REV_CODE);
++	conf = blizzard_read_reg(BLIZZARD_CONFIG);
++
++	printk("rev %x, conf %x\n", rev, conf);
++
++	switch (rev & 0xfc) {
++	case 0x9c:
++		blizzard.version = BLIZZARD_VERSION_S1D13744;
++		pr_info("omapfb: s1d13744 LCD controller rev %d "
++			"initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
++		break;
++	case 0xa4:
++		blizzard.version = BLIZZARD_VERSION_S1D13745;
++		pr_info("omapfb: s1d13745 LCD controller rev %d "
++			"initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
++		break;
++	default:
++		printk("invalid s1d1374x revision %02x\n",
++			rev);
++		r = -ENODEV;
++	}
++
++	return r;
++}
++
++static void blizzard_ctrl_disable(struct omap_display *display)
++{
++	DBG("blizzard_ctrl_disable\n");
++
++	if (display->hw_config.ctrl_disable)
++		display->hw_config.ctrl_disable(display);
++}
++
++int rfbi_configure(int rfbi_module, int bpp, int lines);
++
++static void blizzard_ctrl_setup_update(struct omap_display *display,
++				    u16 x, u16 y, u16 w, u16 h)
++{
++	u8 tmp[18];
++	int x_end, y_end;
++
++	DBG("blizzard_ctrl_setup_update\n");
++
++	x_end = x + w - 1;
++	y_end = y + h - 1;
++
++	tmp[0] = x;
++	tmp[1] = x >> 8;
++	tmp[2] = y;
++	tmp[3] = y >> 8;
++	tmp[4] = x_end;
++	tmp[5] = x_end >> 8;
++	tmp[6] = y_end;
++	tmp[7] = y_end >> 8;
++
++	/* scaling? */
++	tmp[8] = x;
++	tmp[9] = x >> 8;
++	tmp[10] = y;
++	tmp[11] = y >> 8;
++	tmp[12] = x_end;
++	tmp[13] = x_end >> 8;
++	tmp[14] = y_end;
++	tmp[15] = y_end >> 8;
++
++	tmp[16] = BLIZZARD_COLOR_RGB565; //color_mode;
++
++	if (blizzard.version == BLIZZARD_VERSION_S1D13745)
++		tmp[17] = BLIZZARD_SRC_WRITE_LCD_BACKGROUND;
++	else
++		tmp[17] = blizzard.version == BLIZZARD_VERSION_S1D13744 ?
++				BLIZZARD_SRC_WRITE_LCD :
++				BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE;
++
++	rfbi_configure(display->hw_config.u.rfbi.channel,
++		       16,
++		       8);
++
++	blizzard_write(BLIZZARD_INPUT_WIN_X_START_0, tmp, 18);
++
++	rfbi_configure(display->hw_config.u.rfbi.channel,
++		       16,
++		       16);
++}
++
++static int blizzard_ctrl_enable_te(struct omap_display *display, bool enable)
++{
++	return 0;
++}
++
++static int blizzard_ctrl_rotate(struct omap_display *display, u8 rotate)
++{
++	return 0;
++}
++
++static int blizzard_ctrl_mirror(struct omap_display *display, bool enable)
++{
++	return 0;
++}
++
++static int blizzard_run_test(struct omap_display *display, int test_num)
++{
++	return 0;
++}
++
++static struct omap_ctrl blizzard_ctrl = {
++	.owner = THIS_MODULE,
++	.name = "ctrl-blizzard",
++	.init = blizzard_ctrl_init,
++	.enable = blizzard_ctrl_enable,
++	.disable = blizzard_ctrl_disable,
++	.setup_update = blizzard_ctrl_setup_update,
++	.enable_te = blizzard_ctrl_enable_te,
++	.set_rotate = blizzard_ctrl_rotate,
++	.set_mirror = blizzard_ctrl_mirror,
++	.run_test = blizzard_run_test,
++	.pixel_size = 16,
++
++	.timings = {
++                .cs_on_time     = 0,
++
++                .we_on_time     = 9000,
++                .we_off_time    = 18000,
++                .we_cycle_time  = 36000,
++
++                .re_on_time     = 9000,
++                .re_off_time    = 27000,
++                .re_cycle_time  = 36000,
++
++                .access_time    = 27000,
++                .cs_off_time    = 36000,
++
++                .cs_pulse_width = 0,
++        },
++};
++
++
++static int __init blizzard_init(void)
++{
++	DBG("blizzard_init\n");
++	omap_dss_register_ctrl(&blizzard_ctrl);
++	return 0;
++}
++
++static void __exit blizzard_exit(void)
++{
++	DBG("blizzard_exit\n");
++
++	omap_dss_unregister_ctrl(&blizzard_ctrl);
++}
++
++module_init(blizzard_init);
++module_exit(blizzard_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("Blizzard Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-n800.c b/drivers/video/omap2/displays/panel-n800.c
+new file mode 100644
+index 0000000..91d3e37
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-n800.c
+@@ -0,0 +1,435 @@
++
++/*#define DEBUG*/
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/spi/spi.h>
++#include <linux/jiffies.h>
++#include <linux/sched.h>
++#include <linux/backlight.h>
++#include <linux/fb.h>
++
++#include <mach/display.h>
++#include <mach/dma.h>
++
++#define MIPID_CMD_READ_DISP_ID		0x04
++#define MIPID_CMD_READ_RED		0x06
++#define MIPID_CMD_READ_GREEN		0x07
++#define MIPID_CMD_READ_BLUE		0x08
++#define MIPID_CMD_READ_DISP_STATUS	0x09
++#define MIPID_CMD_RDDSDR		0x0F
++#define MIPID_CMD_SLEEP_IN		0x10
++#define MIPID_CMD_SLEEP_OUT		0x11
++#define MIPID_CMD_DISP_OFF		0x28
++#define MIPID_CMD_DISP_ON		0x29
++
++#define MIPID_VER_LPH8923		3
++#define MIPID_VER_LS041Y3		4
++
++#define MIPID_ESD_CHECK_PERIOD		msecs_to_jiffies(5000)
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "PN800: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++struct pn800_device {
++	struct backlight_device *bl_dev;
++	int		enabled;
++	int		model;
++	int		revision;
++	u8		display_id[3];
++	unsigned int	saved_bklight_level;
++	unsigned long	hw_guard_end;		/* next value of jiffies
++						   when we can issue the
++						   next sleep in/out command */
++	unsigned long	hw_guard_wait;		/* max guard time in jiffies */
++
++	struct spi_device	*spi;
++	struct mutex		mutex;
++	struct omap_panel	panel;
++	struct omap_display	*display;
++};
++
++
++static void pn800_transfer(struct pn800_device *md, int cmd,
++			      const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
++{
++	struct spi_message	m;
++	struct spi_transfer	*x, xfer[4];
++	u16			w;
++	int			r;
++
++	BUG_ON(md->spi == NULL);
++
++	spi_message_init(&m);
++
++	memset(xfer, 0, sizeof(xfer));
++	x = &xfer[0];
++
++	cmd &=  0xff;
++	x->tx_buf = &cmd;
++	x->bits_per_word = 9;
++	x->len = 2;
++	spi_message_add_tail(x, &m);
++
++	if (wlen) {
++		x++;
++		x->tx_buf = wbuf;
++		x->len = wlen;
++		x->bits_per_word = 9;
++		spi_message_add_tail(x, &m);
++	}
++
++	if (rlen) {
++		x++;
++		x->rx_buf = &w;
++		x->len = 1;
++		spi_message_add_tail(x, &m);
++
++		if (rlen > 1) {
++			/* Arrange for the extra clock before the first
++			 * data bit.
++			 */
++			x->bits_per_word = 9;
++			x->len		 = 2;
++
++			x++;
++			x->rx_buf	 = &rbuf[1];
++			x->len		 = rlen - 1;
++			spi_message_add_tail(x, &m);
++		}
++	}
++
++	r = spi_sync(md->spi, &m);
++	if (r < 0)
++		dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
++
++	if (rlen)
++		rbuf[0] = w & 0xff;
++}
++
++static inline void pn800_cmd(struct pn800_device *md, int cmd)
++{
++	pn800_transfer(md, cmd, NULL, 0, NULL, 0);
++}
++
++static inline void pn800_write(struct pn800_device *md,
++			       int reg, const u8 *buf, int len)
++{
++	pn800_transfer(md, reg, buf, len, NULL, 0);
++}
++
++static inline void pn800_read(struct pn800_device *md,
++			      int reg, u8 *buf, int len)
++{
++	pn800_transfer(md, reg, NULL, 0, buf, len);
++}
++
++static void set_data_lines(struct pn800_device *md, int data_lines)
++{
++	u16 par;
++
++	switch (data_lines) {
++	case 16:
++		par = 0x150;
++		break;
++	case 18:
++		par = 0x160;
++		break;
++	case 24:
++		par = 0x170;
++		break;
++	}
++	pn800_write(md, 0x3a, (u8 *)&par, 2);
++}
++
++static void send_init_string(struct pn800_device *md)
++{
++	u16 initpar[] = { 0x0102, 0x0100, 0x0100 };
++	int data_lines;
++
++	pn800_write(md, 0xc2, (u8 *)initpar, sizeof(initpar));
++
++	data_lines = (int)md->display->hw_config.panel_data; // XXX
++
++	set_data_lines(md, data_lines);
++}
++
++static void hw_guard_start(struct pn800_device *md, int guard_msec)
++{
++	md->hw_guard_wait = msecs_to_jiffies(guard_msec);
++	md->hw_guard_end = jiffies + md->hw_guard_wait;
++}
++
++static void hw_guard_wait(struct pn800_device *md)
++{
++	unsigned long wait = md->hw_guard_end - jiffies;
++
++	if ((long)wait > 0 && wait <= md->hw_guard_wait) {
++		set_current_state(TASK_UNINTERRUPTIBLE);
++		schedule_timeout(wait);
++	}
++}
++
++static void set_sleep_mode(struct pn800_device *md, int on)
++{
++	int cmd, sleep_time = 50;
++
++	if (on)
++		cmd = MIPID_CMD_SLEEP_IN;
++	else
++		cmd = MIPID_CMD_SLEEP_OUT;
++	hw_guard_wait(md);
++	pn800_cmd(md, cmd);
++	hw_guard_start(md, 120);
++	/*
++	 * When we enable the panel, it seems we _have_ to sleep
++	 * 120 ms before sending the init string. When disabling the
++	 * panel we'll sleep for the duration of 2 frames, so that the
++	 * controller can still provide the PCLK,HS,VS signals. */
++	if (!on)
++		sleep_time = 120;
++	msleep(sleep_time);
++}
++
++static void set_display_state(struct pn800_device *md, int enabled)
++{
++	int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
++
++	pn800_cmd(md, cmd);
++}
++
++static int panel_enabled(struct pn800_device *md)
++{
++	u32 disp_status;
++	int enabled;
++
++	pn800_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
++	disp_status = __be32_to_cpu(disp_status);
++	enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
++	dev_dbg(&md->spi->dev,
++		"LCD panel %s enabled by bootloader (status 0x%04x)\n",
++		enabled ? "" : "not ", disp_status);
++	DBG("status %#08x\n", disp_status);
++	return enabled;
++}
++
++static int panel_detect(struct pn800_device *md)
++{
++	pn800_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
++	dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
++		md->display_id[0], md->display_id[1], md->display_id[2]);
++
++	switch (md->display_id[0]) {
++	case 0x45:
++		md->model = MIPID_VER_LPH8923;
++		md->panel.name = "lph8923";
++		break;
++	case 0x83:
++		md->model = MIPID_VER_LS041Y3;
++		md->panel.name = "ls041y3";
++		//md->esd_check = ls041y3_esd_check;
++		break;
++	default:
++		md->panel.name = "unknown";
++		dev_err(&md->spi->dev, "invalid display ID\n");
++		return -ENODEV;
++	}
++
++	md->revision = md->display_id[1];
++	pr_info("omapfb: %s rev %02x LCD detected\n",
++			md->panel.name, md->revision);
++
++	return 0;
++}
++
++
++
++static int pn800_panel_enable(struct omap_display *display)
++{
++	int r;
++	struct pn800_device *md =
++		(struct pn800_device *)display->panel->priv;
++
++	DBG("pn800_panel_enable\n");
++
++	mutex_lock(&md->mutex);
++
++	if (display->hw_config.panel_enable)
++		display->hw_config.panel_enable(display);
++
++	msleep(50); // wait for power up
++
++	r = panel_detect(md);
++	if (r) {
++		mutex_unlock(&md->mutex);
++		return r;
++	}
++
++	md->enabled = panel_enabled(md);
++
++	if (md->enabled) {
++		DBG("panel already enabled\n");
++		; /*pn800_esd_start_check(md);*/
++	} else {
++		; /*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
++	}
++
++
++	if (md->enabled) {
++		mutex_unlock(&md->mutex);
++		return 0;
++	}
++
++	set_sleep_mode(md, 0);
++	md->enabled = 1;
++	send_init_string(md);
++	set_display_state(md, 1);
++	//mipid_set_bklight_level(panel, md->saved_bklight_level);
++	//mipid_esd_start_check(md);
++
++	mutex_unlock(&md->mutex);
++	return 0;
++}
++
++static void pn800_panel_disable(struct omap_display *display)
++{
++	struct pn800_device *md =
++		(struct pn800_device *)display->panel->priv;
++
++	DBG("pn800_panel_disable\n");
++
++	mutex_lock(&md->mutex);
++
++	if (!md->enabled) {
++		mutex_unlock(&md->mutex);
++		return;
++	}
++	/*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
++	/*pn800_set_bklight_level(panel, 0);*/
++
++	set_display_state(md, 0);
++	set_sleep_mode(md, 1);
++	md->enabled = 0;
++
++
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++
++	mutex_unlock(&md->mutex);
++}
++
++static int pn800_panel_init(struct omap_display *display)
++{
++	struct pn800_device *md =
++		(struct pn800_device *)display->panel->priv;
++
++	DBG("pn800_panel_init\n");
++
++	mutex_init(&md->mutex);
++	md->display = display;
++
++	return 0;
++}
++
++static int pn800_run_test(struct omap_display *display, int test_num)
++{
++	return 0;
++}
++
++static struct omap_panel pn800_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "panel-pn800",
++	.init		= pn800_panel_init,
++	/*.remove	= pn800_cleanup,*/
++	.enable		= pn800_panel_enable,
++	.disable	= pn800_panel_disable,
++	//.set_mode	= pn800_set_mode,
++	.run_test	= pn800_run_test,
++
++	.timings = {
++		.x_res = 800,
++		.y_res = 480,
++
++		.pixel_clock	= 21940,
++		.hsw		= 50,
++		.hfp		= 20,
++		.hbp		= 15,
++
++		.vsw		= 2,
++		.vfp		= 1,
++		.vbp		= 3,
++	},
++	.config		= OMAP_DSS_LCD_TFT,
++};
++
++static int pn800_spi_probe(struct spi_device *spi)
++{
++	struct pn800_device *md;
++
++	DBG("pn800_spi_probe\n");
++
++	md = kzalloc(sizeof(*md), GFP_KERNEL);
++	if (md == NULL) {
++		dev_err(&spi->dev, "out of memory\n");
++		return -ENOMEM;
++	}
++
++	spi->mode = SPI_MODE_0;
++	md->spi = spi;
++	dev_set_drvdata(&spi->dev, md);
++	md->panel = pn800_panel;
++	pn800_panel.priv = md;
++
++	omap_dss_register_panel(&pn800_panel);
++
++	return 0;
++}
++
++static int pn800_spi_remove(struct spi_device *spi)
++{
++	struct pn800_device *md = dev_get_drvdata(&spi->dev);
++
++	DBG("pn800_spi_remove\n");
++
++	omap_dss_unregister_panel(&pn800_panel);
++
++	/*pn800_disable(&md->panel);*/
++	kfree(md);
++
++	return 0;
++}
++
++static struct spi_driver pn800_spi_driver = {
++	.driver = {
++		.name	= "panel-n800",
++		.bus	= &spi_bus_type,
++		.owner	= THIS_MODULE,
++	},
++	.probe	= pn800_spi_probe,
++	.remove	= __devexit_p(pn800_spi_remove),
++};
++
++static int __init pn800_init(void)
++{
++	DBG("pn800_init\n");
++	return spi_register_driver(&pn800_spi_driver);
++}
++
++static void __exit pn800_exit(void)
++{
++	DBG("pn800_exit\n");
++	spi_unregister_driver(&pn800_spi_driver);
++}
++
++module_init(pn800_init);
++module_exit(pn800_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("N800 LCD Driver");
++MODULE_LICENSE("GPL");
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch
new file mode 100644
index 0000000000..26d21d8744
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch
@@ -0,0 +1,5715 @@
+From 9292aae93419867b9d0fce5cf3b2697e9250f5b5 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 10:36:05 +0300
+Subject: [PATCH] DSS2: Add DSS2 support for SDP, Beagle, Overo, EVM
+
+Also custom dss_*_defconfigs as an example.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/configs/dss_omap3_beagle_defconfig | 1371 ++++++++++++++++++++
+ arch/arm/configs/dss_omap_3430sdp_defconfig | 1634 +++++++++++++++++++++++
+ arch/arm/configs/dss_overo_defconfig        | 1862 +++++++++++++++++++++++++++
+ arch/arm/mach-omap2/board-3430sdp.c         |  227 ++++-
+ arch/arm/mach-omap2/board-omap3beagle.c     |   95 ++-
+ arch/arm/mach-omap2/board-omap3evm.c        |  217 +++-
+ arch/arm/mach-omap2/board-overo.c           |   98 ++-
+ 7 files changed, 5475 insertions(+), 29 deletions(-)
+ create mode 100644 arch/arm/configs/dss_omap3_beagle_defconfig
+ create mode 100644 arch/arm/configs/dss_omap_3430sdp_defconfig
+ create mode 100644 arch/arm/configs/dss_overo_defconfig
+
+diff --git a/arch/arm/configs/dss_omap3_beagle_defconfig b/arch/arm/configs/dss_omap3_beagle_defconfig
+new file mode 100644
+index 0000000..7143168
+--- /dev/null
++++ b/arch/arm/configs/dss_omap3_beagle_defconfig
+@@ -0,0 +1,1371 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.29-omap1
++# Thu Apr  2 11:24:09 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_MMU=y
++# CONFIG_NO_IOPORT is not set
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_LATENCYTOP_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_CLASSIC_RCU=y
++# CONFIG_TREE_RCU is not set
++# CONFIG_PREEMPT_RCU is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_PREEMPT_RCU_TRACE is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_GROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_RT_GROUP_SCHED is not set
++CONFIG_USER_SCHED=y
++# CONFIG_CGROUP_SCHED is not set
++# CONFIG_CGROUPS is not set
++CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
++# CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_EMBEDDED=y
++CONFIG_UID16=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++CONFIG_KALLSYMS_EXTRA_PASS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_COMPAT_BRK=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++# CONFIG_FREEZER is not set
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++CONFIG_ARCH_OMAP=y
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_W90X900 is not set
++
++#
++# TI OMAP Implementations
++#
++CONFIG_ARCH_OMAP_OTG=y
++# CONFIG_ARCH_OMAP1 is not set
++# CONFIG_ARCH_OMAP2 is not set
++CONFIG_ARCH_OMAP3=y
++
++#
++# OMAP Feature Selections
++#
++# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
++# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
++# CONFIG_OMAP_SMARTREFLEX is not set
++# CONFIG_OMAP_RESET_CLOCKS is not set
++CONFIG_OMAP_BOOT_TAG=y
++CONFIG_OMAP_BOOT_REASON=y
++# CONFIG_OMAP_COMPONENT_VERSION is not set
++# CONFIG_OMAP_GPIO_SWITCH is not set
++# CONFIG_OMAP_MUX is not set
++# CONFIG_OMAP_MCBSP is not set
++# CONFIG_OMAP_MBOX_FWK is not set
++# CONFIG_OMAP_MPU_TIMER is not set
++CONFIG_OMAP_32K_TIMER=y
++CONFIG_OMAP_32K_TIMER_HZ=128
++CONFIG_OMAP_TICK_GPTIMER=12
++CONFIG_OMAP_DM_TIMER=y
++# CONFIG_OMAP_LL_DEBUG_UART1 is not set
++# CONFIG_OMAP_LL_DEBUG_UART2 is not set
++CONFIG_OMAP_LL_DEBUG_UART3=y
++CONFIG_ARCH_OMAP34XX=y
++CONFIG_ARCH_OMAP3430=y
++
++#
++# OMAP Board Type
++#
++# CONFIG_MACH_NOKIA_RX51 is not set
++# CONFIG_MACH_OMAP_LDP is not set
++# CONFIG_MACH_OMAP_3430SDP is not set
++# CONFIG_MACH_OMAP3EVM is not set
++CONFIG_MACH_OMAP3_BEAGLE=y
++# CONFIG_MACH_OVERO is not set
++# CONFIG_MACH_OMAP3_PANDORA is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_IFAR=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_HAS_TLS_REG=y
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=128
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++CONFIG_ARCH_FLATMEM_HAS_HOLES=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++CONFIG_UNEVICTABLE_LRU=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.2.14:/tftpboot/rootfs ip=192.168.2.15 nolock,rsize=1024,wsize=1024 rw"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# CPU Power Management
++#
++# CONFIG_CPU_FREQ is not set
++# CONFIG_CPU_IDLE is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++# CONFIG_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_MISC=y
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_SUSPEND is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_COMPAT_NET_DEV_OPS=y
++CONFIG_PACKET=y
++# CONFIG_PACKET_MMAP is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_NET_KEY=y
++# CONFIG_NET_KEY_MIGRATE is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_PHONET is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++CONFIG_WIRELESS_OLD_REGULATORY=y
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_LIB80211 is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=16384
++# CONFIG_BLK_DEV_XIP is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MISC_DEVICES is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_LIBFC is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_NET_ETHERNET is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_IWLWIFI_LEDS is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_DEVKMEM=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++CONFIG_I2C_OMAP=y
++# CONFIG_I2C_SIMTEC is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_STUB is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_DS1682 is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_PCF8575 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TWL4030_MADC is not set
++# CONFIG_TWL4030_POWEROFF is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++# CONFIG_SPI is not set
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++# CONFIG_DEBUG_GPIO is not set
++# CONFIG_GPIO_SYSFS is not set
++
++#
++# Memory mapped GPIO expanders:
++#
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++CONFIG_GPIO_TWL4030=y
++
++#
++# PCI GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_TPS65010 is not set
++CONFIG_TWL4030_CORE=y
++# CONFIG_TWL4030_POWER is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_PCF50633 is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_VIDEO_MEDIA is not set
++
++#
++# Multimedia drivers
++#
++CONFIG_DAB=y
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=m
++CONFIG_FB_CFB_COPYAREA=m
++CONFIG_FB_CFB_IMAGEBLIT=m
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
++CONFIG_OMAP2_DSS=m
++CONFIG_OMAP2_DSS_VRAM_SIZE=12
++CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_GENERIC=m
++# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set
++# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
++# CONFIG_PANEL_N800 is not set
++# CONFIG_CTRL_BLIZZARD is not set
++CONFIG_FB_OMAP2=m
++CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++CONFIG_FB_OMAP2_NUM_FBS=3
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++# CONFIG_HID_SUPPORT is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++# CONFIG_USB is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SOC=y
++
++#
++# OMAP 343x high speed USB support
++#
++# CONFIG_USB_MUSB_HOST is not set
++CONFIG_USB_MUSB_PERIPHERAL=y
++# CONFIG_USB_MUSB_OTG is not set
++CONFIG_USB_GADGET_MUSB_HDRC=y
++# CONFIG_MUSB_PIO_ONLY is not set
++CONFIG_USB_INVENTRA_DMA=y
++# CONFIG_USB_TI_CPPI_DMA is not set
++# CONFIG_USB_MUSB_DEBUG is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
++#
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_PXA25X is not set
++# CONFIG_USB_GADGET_PXA27X is not set
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_IMX is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_FSL_QE is not set
++# CONFIG_USB_GADGET_CI13XXX is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++CONFIG_USB_ETH=y
++CONFIG_USB_ETH_RNDIS=y
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_ISP1301_OMAP is not set
++CONFIG_TWL4030_USB=y
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_SDHCI is not set
++CONFIG_MMC_OMAP_HS=y
++# CONFIG_MEMSTICK is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_NEW_LEDS is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++CONFIG_RTC_DRV_TWL4030=y
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++
++#
++# SPI RTC drivers
++#
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_DMADEVICES is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_BQ24022 is not set
++CONFIG_REGULATOR_TWL4030=y
++# CONFIG_UIO is not set
++# CONFIG_STAGING is not set
++
++#
++# CBUS support
++#
++# CONFIG_CBUS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_FS_XATTR is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++CONFIG_QUOTA_TREE=y
++# CONFIG_QFMT_V1 is not set
++CONFIG_QFMT_V2=y
++CONFIG_QUOTACTL=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_REGISTER_V4 is not set
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++
++#
++# Tracers
++#
++# CONFIG_FUNCTION_TRACER is not set
++# CONFIG_IRQSOFF_TRACER is not set
++# CONFIG_SCHED_TRACER is not set
++# CONFIG_CONTEXT_SWITCH_TRACER is not set
++# CONFIG_BOOT_TRACER is not set
++# CONFIG_TRACE_BRANCH_PROFILING is not set
++# CONFIG_STACK_TRACER is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_ERRORS=y
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_LL is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++# CONFIG_CRYPTO_FIPS is not set
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=m
++# CONFIG_CRYPTO_LRW is not set
++CONFIG_CRYPTO_PCBC=m
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++# CONFIG_CRYPTO_AES is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_FIND_LAST_BIT=y
++CONFIG_CRC_CCITT=y
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=y
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/dss_omap_3430sdp_defconfig b/arch/arm/configs/dss_omap_3430sdp_defconfig
+new file mode 100644
+index 0000000..dc30dce
+--- /dev/null
++++ b/arch/arm/configs/dss_omap_3430sdp_defconfig
+@@ -0,0 +1,1634 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.29-omap1
++# Thu Apr  2 11:11:24 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_MMU=y
++# CONFIG_NO_IOPORT is not set
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_LATENCYTOP_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_CLASSIC_RCU=y
++# CONFIG_TREE_RCU is not set
++# CONFIG_PREEMPT_RCU is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_PREEMPT_RCU_TRACE is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_GROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_RT_GROUP_SCHED is not set
++CONFIG_USER_SCHED=y
++# CONFIG_CGROUP_SCHED is not set
++# CONFIG_CGROUPS is not set
++CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
++# CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_EMBEDDED=y
++CONFIG_UID16=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++CONFIG_KALLSYMS_EXTRA_PASS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_COMPAT_BRK=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++CONFIG_ARCH_OMAP=y
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_W90X900 is not set
++
++#
++# TI OMAP Implementations
++#
++CONFIG_ARCH_OMAP_OTG=y
++# CONFIG_ARCH_OMAP1 is not set
++# CONFIG_ARCH_OMAP2 is not set
++CONFIG_ARCH_OMAP3=y
++
++#
++# OMAP Feature Selections
++#
++# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
++# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
++CONFIG_OMAP_SMARTREFLEX=y
++# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
++CONFIG_OMAP_RESET_CLOCKS=y
++CONFIG_OMAP_BOOT_TAG=y
++CONFIG_OMAP_BOOT_REASON=y
++# CONFIG_OMAP_COMPONENT_VERSION is not set
++# CONFIG_OMAP_GPIO_SWITCH is not set
++CONFIG_OMAP_MUX=y
++CONFIG_OMAP_MUX_DEBUG=y
++CONFIG_OMAP_MUX_WARNINGS=y
++# CONFIG_OMAP_MCBSP is not set
++# CONFIG_OMAP_MBOX_FWK is not set
++# CONFIG_OMAP_MPU_TIMER is not set
++CONFIG_OMAP_32K_TIMER=y
++CONFIG_OMAP_32K_TIMER_HZ=128
++CONFIG_OMAP_TICK_GPTIMER=1
++CONFIG_OMAP_DM_TIMER=y
++CONFIG_OMAP_LL_DEBUG_UART1=y
++# CONFIG_OMAP_LL_DEBUG_UART2 is not set
++# CONFIG_OMAP_LL_DEBUG_UART3 is not set
++CONFIG_OMAP_SERIAL_WAKE=y
++CONFIG_ARCH_OMAP34XX=y
++CONFIG_ARCH_OMAP3430=y
++
++#
++# OMAP Board Type
++#
++# CONFIG_MACH_NOKIA_RX51 is not set
++# CONFIG_MACH_OMAP_LDP is not set
++CONFIG_MACH_OMAP_3430SDP=y
++# CONFIG_MACH_OMAP3EVM is not set
++# CONFIG_MACH_OMAP3_BEAGLE is not set
++# CONFIG_MACH_OVERO is not set
++# CONFIG_MACH_OMAP3_PANDORA is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_IFAR=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_HAS_TLS_REG=y
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=128
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++CONFIG_ARCH_FLATMEM_HAS_HOLES=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++CONFIG_UNEVICTABLE_LRU=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# CPU Power Management
++#
++# CONFIG_CPU_FREQ is not set
++# CONFIG_CPU_IDLE is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++# CONFIG_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_MISC=y
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_APM_EMULATION is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_COMPAT_NET_DEV_OPS=y
++CONFIG_PACKET=y
++# CONFIG_PACKET_MMAP is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_NET_KEY=y
++# CONFIG_NET_KEY_MIGRATE is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_PHONET is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++CONFIG_WIRELESS_OLD_REGULATORY=y
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_LIB80211 is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++CONFIG_MTD_CONCAT=y
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++# CONFIG_MTD_CFI_AMDSTD is not set
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++CONFIG_MTD_OMAP_NOR=y
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++CONFIG_MTD_NAND_ECC_SMC=y
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++CONFIG_MTD_ONENAND=y
++CONFIG_MTD_ONENAND_VERIFY_WRITE=y
++# CONFIG_MTD_ONENAND_GENERIC is not set
++CONFIG_MTD_ONENAND_OMAP2=y
++# CONFIG_MTD_ONENAND_OTP is not set
++# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
++# CONFIG_MTD_ONENAND_SIM is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=16384
++# CONFIG_BLK_DEV_XIP is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_ICS932S401 is not set
++# CONFIG_OMAP_STI is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_LIBFC is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++CONFIG_SMC91X=y
++# CONFIG_DM9000 is not set
++# CONFIG_ENC28J60 is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SMSC911X is not set
++# CONFIG_DNET is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
++# CONFIG_B44 is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_IWLWIFI_LEDS is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ATKBD is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++CONFIG_KEYBOARD_TWL4030=y
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ADS7846=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_INEXIO is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_TSC2005 is not set
++# CONFIG_TOUCHSCREEN_TSC210X is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
++# CONFIG_TOUCHSCREEN_TSC2007 is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_DEVKMEM=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++CONFIG_I2C_OMAP=y
++# CONFIG_I2C_SIMTEC is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_STUB is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_DS1682 is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_PCF8575 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TWL4030_MADC is not set
++# CONFIG_TWL4030_POWEROFF is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_GPIO is not set
++CONFIG_SPI_OMAP24XX=y
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_TSC210X is not set
++# CONFIG_SPI_TSC2301 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++# CONFIG_DEBUG_GPIO is not set
++# CONFIG_GPIO_SYSFS is not set
++
++#
++# Memory mapped GPIO expanders:
++#
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++CONFIG_GPIO_TWL4030=y
++
++#
++# PCI GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MCP23S08 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_NOWAYOUT=y
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_OMAP_WATCHDOG=y
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_TPS65010 is not set
++CONFIG_TWL4030_CORE=y
++# CONFIG_TWL4030_POWER is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_PCF50633 is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_VIDEO_MEDIA is not set
++
++#
++# Multimedia drivers
++#
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++CONFIG_VIDEO_OUTPUT_CONTROL=m
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=m
++CONFIG_FB_CFB_COPYAREA=m
++CONFIG_FB_CFB_IMAGEBLIT=m
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_OMAP_LCD_VGA is not set
++# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
++CONFIG_OMAP2_DSS=m
++CONFIG_OMAP2_DSS_VRAM_SIZE=8
++CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_GENERIC=m
++# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set
++CONFIG_PANEL_SHARP_LS037V7DW01=m
++# CONFIG_PANEL_N800 is not set
++# CONFIG_CTRL_BLIZZARD is not set
++CONFIG_FB_OMAP2=m
++CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++CONFIG_FB_OMAP2_NUM_FBS=3
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# Special HID drivers
++#
++CONFIG_HID_COMPAT=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SONY is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_GREENASIA_FF is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_THRUSTMASTER_FF is not set
++# CONFIG_ZEROPLUS_FF is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB=y
++CONFIG_USB_DEBUG=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_DEVICE_CLASS is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++CONFIG_USB_SUSPEND=y
++CONFIG_USB_OTG=y
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++CONFIG_USB_MON=y
++# CONFIG_USB_WUSB is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_EHCI_HCD=m
++CONFIG_OMAP_EHCI_PHY_MODE=y
++# CONFIG_OMAP_EHCI_TLL_MODE is not set
++# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
++# CONFIG_USB_EHCI_TT_NEWSCHED is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HWA_HCD is not set
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SOC=y
++
++#
++# OMAP 343x high speed USB support
++#
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_PERIPHERAL is not set
++CONFIG_USB_MUSB_OTG=y
++CONFIG_USB_GADGET_MUSB_HDRC=y
++CONFIG_USB_MUSB_HDRC_HCD=y
++# CONFIG_MUSB_PIO_ONLY is not set
++CONFIG_USB_INVENTRA_DMA=y
++# CONFIG_USB_TI_CPPI_DMA is not set
++# CONFIG_USB_MUSB_DEBUG is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
++#
++
++#
++# see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_DEBUG=y
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_SISUSBVGA is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++CONFIG_USB_TEST=y
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_VST is not set
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DEBUG=y
++CONFIG_USB_GADGET_DEBUG_FILES=y
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_PXA25X is not set
++# CONFIG_USB_GADGET_PXA27X is not set
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_IMX is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_FSL_QE is not set
++# CONFIG_USB_GADGET_CI13XXX is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++CONFIG_USB_ZERO=m
++# CONFIG_USB_ZERO_HNPTEST is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_ISP1301_OMAP is not set
++CONFIG_TWL4030_USB=y
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_SDHCI is not set
++CONFIG_MMC_OMAP_HS=m
++# CONFIG_MMC_SPI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_NEW_LEDS is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++CONFIG_RTC_DRV_TWL4030=y
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_DS3234 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_DMADEVICES is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_BQ24022 is not set
++CONFIG_REGULATOR_TWL4030=y
++# CONFIG_UIO is not set
++# CONFIG_STAGING is not set
++
++#
++# CBUS support
++#
++# CONFIG_CBUS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_FS_XATTR is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++CONFIG_QUOTA_TREE=y
++# CONFIG_QFMT_V1 is not set
++CONFIG_QFMT_V2=y
++CONFIG_QUOTACTL=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_JFFS2_CMODE_NONE is not set
++CONFIG_JFFS2_CMODE_PRIORITY=y
++# CONFIG_JFFS2_CMODE_SIZE is not set
++# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_REGISTER_V4 is not set
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++
++#
++# Tracers
++#
++# CONFIG_FUNCTION_TRACER is not set
++# CONFIG_IRQSOFF_TRACER is not set
++# CONFIG_SCHED_TRACER is not set
++# CONFIG_CONTEXT_SWITCH_TRACER is not set
++# CONFIG_BOOT_TRACER is not set
++# CONFIG_TRACE_BRANCH_PROFILING is not set
++# CONFIG_STACK_TRACER is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_ERRORS=y
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_LL is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++# CONFIG_CRYPTO_FIPS is not set
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=m
++# CONFIG_CRYPTO_LRW is not set
++CONFIG_CRYPTO_PCBC=m
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++# CONFIG_CRYPTO_AES is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_FIND_LAST_BIT=y
++CONFIG_CRC_CCITT=y
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=y
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/dss_overo_defconfig b/arch/arm/configs/dss_overo_defconfig
+new file mode 100644
+index 0000000..755a1b6
+--- /dev/null
++++ b/arch/arm/configs/dss_overo_defconfig
+@@ -0,0 +1,1862 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.29-omap1
++# Thu Apr  2 11:30:57 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_MMU=y
++# CONFIG_NO_IOPORT is not set
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_LATENCYTOP_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
++CONFIG_OPROFILE_ARMV7=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_CLASSIC_RCU=y
++# CONFIG_TREE_RCU is not set
++# CONFIG_PREEMPT_RCU is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_PREEMPT_RCU_TRACE is not set
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_GROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_RT_GROUP_SCHED is not set
++CONFIG_USER_SCHED=y
++# CONFIG_CGROUP_SCHED is not set
++# CONFIG_CGROUPS is not set
++CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
++# CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_EMBEDDED=y
++CONFIG_UID16=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++# CONFIG_ELF_CORE is not set
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++CONFIG_PROFILING=y
++CONFIG_TRACEPOINTS=y
++# CONFIG_MARKERS is not set
++CONFIG_OPROFILE=y
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_BLOCK=y
++CONFIG_LBD=y
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_AS is not set
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++CONFIG_ARCH_OMAP=y
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_W90X900 is not set
++
++#
++# TI OMAP Implementations
++#
++CONFIG_ARCH_OMAP_OTG=y
++# CONFIG_ARCH_OMAP1 is not set
++# CONFIG_ARCH_OMAP2 is not set
++CONFIG_ARCH_OMAP3=y
++
++#
++# OMAP Feature Selections
++#
++# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
++# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
++CONFIG_OMAP_SMARTREFLEX=y
++# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
++# CONFIG_OMAP_RESET_CLOCKS is not set
++CONFIG_OMAP_BOOT_TAG=y
++CONFIG_OMAP_BOOT_REASON=y
++# CONFIG_OMAP_COMPONENT_VERSION is not set
++# CONFIG_OMAP_GPIO_SWITCH is not set
++# CONFIG_OMAP_MUX is not set
++CONFIG_OMAP_MCBSP=y
++# CONFIG_OMAP_MBOX_FWK is not set
++# CONFIG_OMAP_MPU_TIMER is not set
++CONFIG_OMAP_32K_TIMER=y
++CONFIG_OMAP_32K_TIMER_HZ=128
++CONFIG_OMAP_TICK_GPTIMER=1
++CONFIG_OMAP_DM_TIMER=y
++# CONFIG_OMAP_LL_DEBUG_UART1 is not set
++# CONFIG_OMAP_LL_DEBUG_UART2 is not set
++CONFIG_OMAP_LL_DEBUG_UART3=y
++CONFIG_ARCH_OMAP34XX=y
++CONFIG_ARCH_OMAP3430=y
++
++#
++# OMAP Board Type
++#
++# CONFIG_MACH_NOKIA_RX51 is not set
++# CONFIG_MACH_OMAP_LDP is not set
++# CONFIG_MACH_OMAP_3430SDP is not set
++# CONFIG_MACH_OMAP3EVM is not set
++# CONFIG_MACH_OMAP3_BEAGLE is not set
++CONFIG_MACH_OVERO=y
++# CONFIG_MACH_OMAP3_PANDORA is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_IFAR=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++CONFIG_ARM_THUMBEE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_HAS_TLS_REG=y
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=128
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++CONFIG_ARCH_FLATMEM_HAS_HOLES=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++CONFIG_UNEVICTABLE_LRU=y
++CONFIG_LEDS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.2.14:/tftpboot/rootfs ip=192.168.2.15 nolock,rsize=1024,wsize=1024 rw"
++# CONFIG_XIP_KERNEL is not set
++CONFIG_KEXEC=y
++CONFIG_ATAGS_PROC=y
++
++#
++# CPU Power Management
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_TABLE=y
++# CONFIG_CPU_FREQ_DEBUG is not set
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_IDLE is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_HAVE_AOUT=y
++CONFIG_BINFMT_AOUT=m
++CONFIG_BINFMT_MISC=y
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_APM_EMULATION is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_COMPAT_NET_DEV_OPS=y
++CONFIG_PACKET=y
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_NET_KEY=y
++# CONFIG_NET_KEY_MIGRATE is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=m
++# CONFIG_IPV6_PRIVACY is not set
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++CONFIG_IPV6_SIT=m
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++CONFIG_BT=y
++CONFIG_BT_L2CAP=y
++CONFIG_BT_SCO=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++
++#
++# Bluetooth device drivers
++#
++# CONFIG_BT_HCIBTSDIO is not set
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_H4=y
++CONFIG_BT_HCIUART_BCSP=y
++# CONFIG_BT_HCIUART_LL is not set
++# CONFIG_BT_HCIBRF6150 is not set
++# CONFIG_BT_HCIH4P is not set
++# CONFIG_BT_HCIVHCI is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_PHONET is not set
++CONFIG_WIRELESS=y
++CONFIG_CFG80211=y
++# CONFIG_CFG80211_REG_DEBUG is not set
++CONFIG_NL80211=y
++CONFIG_WIRELESS_OLD_REGULATORY=y
++CONFIG_WIRELESS_EXT=y
++CONFIG_WIRELESS_EXT_SYSFS=y
++CONFIG_LIB80211=y
++CONFIG_LIB80211_CRYPT_WEP=m
++CONFIG_LIB80211_CRYPT_CCMP=m
++CONFIG_LIB80211_CRYPT_TKIP=m
++# CONFIG_LIB80211_DEBUG is not set
++CONFIG_MAC80211=y
++
++#
++# Rate control algorithm selection
++#
++CONFIG_MAC80211_RC_PID=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT_PID=y
++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
++CONFIG_MAC80211_RC_DEFAULT="pid"
++# CONFIG_MAC80211_MESH is not set
++CONFIG_MAC80211_LEDS=y
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++CONFIG_MTD_CONCAT=y
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_CRYPTOLOOP=m
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=16384
++# CONFIG_BLK_DEV_XIP is not set
++CONFIG_CDROM_PKTCDVD=m
++CONFIG_CDROM_PKTCDVD_BUFFERS=8
++# CONFIG_CDROM_PKTCDVD_WCACHE is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_ICS932S401 is not set
++# CONFIG_OMAP_STI is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++CONFIG_EEPROM_93CX6=m
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++CONFIG_RAID_ATTRS=m
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=m
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++CONFIG_SCSI_MULTI_LUN=y
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_LIBFC is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_ATA is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_MD=m
++CONFIG_MD_LINEAR=m
++CONFIG_MD_RAID0=m
++CONFIG_MD_RAID1=m
++CONFIG_MD_RAID10=m
++CONFIG_MD_RAID456=m
++CONFIG_MD_RAID5_RESHAPE=y
++CONFIG_MD_MULTIPATH=m
++CONFIG_MD_FAULTY=m
++CONFIG_BLK_DEV_DM=m
++# CONFIG_DM_DEBUG is not set
++CONFIG_DM_CRYPT=m
++CONFIG_DM_SNAPSHOT=m
++CONFIG_DM_MIRROR=m
++CONFIG_DM_ZERO=m
++CONFIG_DM_MULTIPATH=m
++CONFIG_DM_DELAY=m
++# CONFIG_DM_UEVENT is not set
++CONFIG_NETDEVICES=y
++CONFIG_DUMMY=m
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++CONFIG_TUN=m
++# CONFIG_VETH is not set
++# CONFIG_NET_ETHERNET is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++CONFIG_WLAN_80211=y
++CONFIG_LIBERTAS=y
++CONFIG_LIBERTAS_SDIO=y
++CONFIG_LIBERTAS_DEBUG=y
++# CONFIG_LIBERTAS_THINFIRM is not set
++# CONFIG_MAC80211_HWSIM is not set
++CONFIG_P54_COMMON=m
++# CONFIG_IWLWIFI_LEDS is not set
++CONFIG_HOSTAP=m
++CONFIG_HOSTAP_FIRMWARE=y
++CONFIG_HOSTAP_FIRMWARE_NVRAM=y
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_RT2X00 is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++CONFIG_PPP=m
++# CONFIG_PPP_MULTILINK is not set
++# CONFIG_PPP_FILTER is not set
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_MPPE=m
++CONFIG_PPPOE=m
++# CONFIG_PPPOL2TP is not set
++# CONFIG_SLIP is not set
++CONFIG_SLHC=m
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ATKBD is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_TWL4030 is not set
++# CONFIG_KEYBOARD_LM8323 is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++CONFIG_VT_HW_CONSOLE_BINDING=y
++CONFIG_DEVKMEM=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++CONFIG_I2C_OMAP=y
++# CONFIG_I2C_SIMTEC is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_STUB is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_DS1682 is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_PCF8575 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++CONFIG_TWL4030_MADC=m
++CONFIG_TWL4030_POWEROFF=y
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_TSL2563 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_GPIO is not set
++CONFIG_SPI_OMAP24XX=y
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_TSC210X is not set
++# CONFIG_SPI_TSC2301 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++CONFIG_DEBUG_GPIO=y
++CONFIG_GPIO_SYSFS=y
++
++#
++# Memory mapped GPIO expanders:
++#
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++CONFIG_GPIO_TWL4030=y
++
++#
++# PCI GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MCP23S08 is not set
++# CONFIG_W1 is not set
++CONFIG_POWER_SUPPLY=m
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_BATTERY_DS2760 is not set
++# CONFIG_TWL4030_BCI_BATTERY is not set
++# CONFIG_BATTERY_BQ27x00 is not set
++CONFIG_HWMON=y
++# CONFIG_HWMON_VID is not set
++# CONFIG_SENSORS_AD7414 is not set
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADCXX is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7462 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ADT7473 is not set
++# CONFIG_SENSORS_ADT7475 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++# CONFIG_SENSORS_LM75 is not set
++# CONFIG_SENSORS_LM77 is not set
++# CONFIG_SENSORS_LM78 is not set
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++# CONFIG_SENSORS_LM85 is not set
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_LTC4245 is not set
++# CONFIG_SENSORS_MAX1111 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_ADS7828 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83L786NG is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_SENSORS_TSC210X is not set
++CONFIG_SENSORS_OMAP34XX=y
++# CONFIG_HWMON_DEBUG_CHIP is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_NOWAYOUT=y
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_OMAP_WATCHDOG=y
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_TPS65010 is not set
++CONFIG_TWL4030_CORE=y
++# CONFIG_TWL4030_POWER is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_PCF50633 is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++CONFIG_VIDEO_DEV=m
++CONFIG_VIDEO_V4L2_COMMON=m
++CONFIG_VIDEO_ALLOW_V4L1=y
++CONFIG_VIDEO_V4L1_COMPAT=y
++CONFIG_DVB_CORE=m
++CONFIG_VIDEO_MEDIA=m
++
++#
++# Multimedia drivers
++#
++CONFIG_MEDIA_ATTACH=y
++CONFIG_MEDIA_TUNER=m
++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
++CONFIG_MEDIA_TUNER_SIMPLE=m
++CONFIG_MEDIA_TUNER_TDA8290=m
++CONFIG_MEDIA_TUNER_TDA9887=m
++CONFIG_MEDIA_TUNER_TEA5761=m
++CONFIG_MEDIA_TUNER_TEA5767=m
++CONFIG_MEDIA_TUNER_MT20XX=m
++CONFIG_MEDIA_TUNER_XC2028=m
++CONFIG_MEDIA_TUNER_XC5000=m
++CONFIG_VIDEO_V4L2=m
++CONFIG_VIDEO_V4L1=m
++CONFIG_VIDEO_CAPTURE_DRIVERS=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
++# CONFIG_VIDEO_VIVI is not set
++# CONFIG_VIDEO_CPIA is not set
++# CONFIG_VIDEO_SAA5246A is not set
++# CONFIG_VIDEO_SAA5249 is not set
++# CONFIG_SOC_CAMERA is not set
++CONFIG_RADIO_ADAPTERS=y
++# CONFIG_RADIO_TEA5764 is not set
++# CONFIG_DVB_DYNAMIC_MINORS is not set
++CONFIG_DVB_CAPTURE_DRIVERS=y
++# CONFIG_TTPCI_EEPROM is not set
++# CONFIG_DVB_B2C2_FLEXCOP is not set
++
++#
++# Supported DVB Frontends
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_FE_CUSTOMISE is not set
++
++#
++# Multistandard (satellite) frontends
++#
++# CONFIG_DVB_STB0899 is not set
++# CONFIG_DVB_STB6100 is not set
++
++#
++# DVB-S (satellite) frontends
++#
++CONFIG_DVB_CX24110=m
++CONFIG_DVB_CX24123=m
++CONFIG_DVB_MT312=m
++CONFIG_DVB_S5H1420=m
++# CONFIG_DVB_STV0288 is not set
++# CONFIG_DVB_STB6000 is not set
++CONFIG_DVB_STV0299=m
++CONFIG_DVB_TDA8083=m
++CONFIG_DVB_TDA10086=m
++# CONFIG_DVB_TDA8261 is not set
++CONFIG_DVB_VES1X93=m
++CONFIG_DVB_TUNER_ITD1000=m
++# CONFIG_DVB_TUNER_CX24113 is not set
++CONFIG_DVB_TDA826X=m
++CONFIG_DVB_TUA6100=m
++# CONFIG_DVB_CX24116 is not set
++# CONFIG_DVB_SI21XX is not set
++
++#
++# DVB-T (terrestrial) frontends
++#
++CONFIG_DVB_SP8870=m
++CONFIG_DVB_SP887X=m
++CONFIG_DVB_CX22700=m
++CONFIG_DVB_CX22702=m
++# CONFIG_DVB_DRX397XD is not set
++CONFIG_DVB_L64781=m
++CONFIG_DVB_TDA1004X=m
++CONFIG_DVB_NXT6000=m
++CONFIG_DVB_MT352=m
++CONFIG_DVB_ZL10353=m
++CONFIG_DVB_DIB3000MB=m
++CONFIG_DVB_DIB3000MC=m
++CONFIG_DVB_DIB7000M=m
++CONFIG_DVB_DIB7000P=m
++CONFIG_DVB_TDA10048=m
++
++#
++# DVB-C (cable) frontends
++#
++CONFIG_DVB_VES1820=m
++CONFIG_DVB_TDA10021=m
++CONFIG_DVB_TDA10023=m
++CONFIG_DVB_STV0297=m
++
++#
++# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
++#
++CONFIG_DVB_NXT200X=m
++# CONFIG_DVB_OR51211 is not set
++# CONFIG_DVB_OR51132 is not set
++CONFIG_DVB_BCM3510=m
++CONFIG_DVB_LGDT330X=m
++# CONFIG_DVB_LGDT3304 is not set
++CONFIG_DVB_S5H1409=m
++CONFIG_DVB_AU8522=m
++CONFIG_DVB_S5H1411=m
++
++#
++# ISDB-T (terrestrial) frontends
++#
++# CONFIG_DVB_S921 is not set
++
++#
++# Digital terrestrial only tuners/PLL
++#
++CONFIG_DVB_PLL=m
++CONFIG_DVB_TUNER_DIB0070=m
++
++#
++# SEC control devices for DVB-S
++#
++CONFIG_DVB_LNBP21=m
++# CONFIG_DVB_ISL6405 is not set
++CONFIG_DVB_ISL6421=m
++# CONFIG_DVB_LGS8GL5 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++# CONFIG_DVB_AF9013 is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=m
++CONFIG_FB_CFB_COPYAREA=m
++CONFIG_FB_CFB_IMAGEBLIT=m
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
++CONFIG_OMAP2_DSS=m
++CONFIG_OMAP2_DSS_VRAM_SIZE=12
++CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_GENERIC=m
++CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C=m
++# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
++# CONFIG_PANEL_N800 is not set
++# CONFIG_CTRL_BLIZZARD is not set
++CONFIG_FB_OMAP2=m
++CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++CONFIG_FB_OMAP2_NUM_FBS=3
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++CONFIG_DISPLAY_SUPPORT=y
++
++#
++# Display hardware drivers
++#
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++CONFIG_SOUND=y
++CONFIG_SOUND_OSS_CORE=y
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=m
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_HRTIMER is not set
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++CONFIG_SND_VERBOSE_PRINTK=y
++CONFIG_SND_DEBUG=y
++# CONFIG_SND_DEBUG_VERBOSE is not set
++# CONFIG_SND_PCM_XRUN_DEBUG is not set
++CONFIG_SND_DRIVERS=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++CONFIG_SND_ARM=y
++CONFIG_SND_SPI=y
++CONFIG_SND_SOC=y
++CONFIG_SND_OMAP_SOC=y
++CONFIG_SND_OMAP_SOC_MCBSP=y
++CONFIG_SND_OMAP_SOC_OVERO=y
++CONFIG_SND_SOC_I2C_AND_SPI=y
++# CONFIG_SND_SOC_ALL_CODECS is not set
++CONFIG_SND_SOC_TWL4030=y
++# CONFIG_SOUND_PRIME is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++CONFIG_HID_DEBUG=y
++# CONFIG_HIDRAW is not set
++# CONFIG_HID_PID is not set
++
++#
++# Special HID drivers
++#
++CONFIG_HID_COMPAT=y
++# CONFIG_HID_APPLE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++# CONFIG_USB is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SOC=y
++
++#
++# OMAP 343x high speed USB support
++#
++# CONFIG_USB_MUSB_HOST is not set
++CONFIG_USB_MUSB_PERIPHERAL=y
++# CONFIG_USB_MUSB_OTG is not set
++CONFIG_USB_GADGET_MUSB_HDRC=y
++# CONFIG_MUSB_PIO_ONLY is not set
++CONFIG_USB_INVENTRA_DMA=y
++# CONFIG_USB_TI_CPPI_DMA is not set
++# CONFIG_USB_MUSB_DEBUG is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
++#
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_PXA25X is not set
++# CONFIG_USB_GADGET_PXA27X is not set
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_IMX is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_FSL_QE is not set
++# CONFIG_USB_GADGET_CI13XXX is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++CONFIG_USB_ETH=y
++CONFIG_USB_ETH_RNDIS=y
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_ISP1301_OMAP is not set
++CONFIG_TWL4030_USB=y
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_UNSAFE_RESUME=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++CONFIG_SDIO_UART=y
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_SDHCI is not set
++CONFIG_MMC_OMAP_HS=y
++# CONFIG_MMC_SPI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++
++#
++# LED drivers
++#
++# CONFIG_LEDS_OMAP_DEBUG is not set
++# CONFIG_LEDS_OMAP is not set
++# CONFIG_LEDS_OMAP_PWM is not set
++# CONFIG_LEDS_PCA9532 is not set
++CONFIG_LEDS_GPIO=y
++# CONFIG_LEDS_LP5521 is not set
++# CONFIG_LEDS_PCA955X is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++CONFIG_RTC_DRV_TWL4030=y
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_DS3234 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_DMADEVICES is not set
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_BQ24022 is not set
++CONFIG_REGULATOR_TWL4030=y
++# CONFIG_UIO is not set
++# CONFIG_STAGING is not set
++
++#
++# CBUS support
++#
++# CONFIG_CBUS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_FS_XATTR is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_FILE_LOCKING=y
++CONFIG_XFS_FS=m
++# CONFIG_XFS_QUOTA is not set
++# CONFIG_XFS_POSIX_ACL is not set
++# CONFIG_XFS_RT is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++CONFIG_QUOTA_TREE=y
++# CONFIG_QFMT_V1 is not set
++CONFIG_QFMT_V2=y
++CONFIG_QUOTACTL=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++CONFIG_FUSE_FS=m
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++CONFIG_JFFS2_SUMMARY=y
++CONFIG_JFFS2_FS_XATTR=y
++CONFIG_JFFS2_FS_POSIX_ACL=y
++CONFIG_JFFS2_FS_SECURITY=y
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_ZLIB=y
++CONFIG_JFFS2_LZO=y
++CONFIG_JFFS2_RTIME=y
++CONFIG_JFFS2_RUBIN=y
++# CONFIG_JFFS2_CMODE_NONE is not set
++CONFIG_JFFS2_CMODE_PRIORITY=y
++# CONFIG_JFFS2_CMODE_SIZE is not set
++# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_EXPORTFS=m
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_REGISTER_V4 is not set
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHEDSTATS=y
++CONFIG_TIMER_STATS=y
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_INFO is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_NOP_TRACER=y
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_RING_BUFFER=y
++CONFIG_TRACING=y
++
++#
++# Tracers
++#
++# CONFIG_FUNCTION_TRACER is not set
++# CONFIG_IRQSOFF_TRACER is not set
++# CONFIG_SCHED_TRACER is not set
++# CONFIG_CONTEXT_SWITCH_TRACER is not set
++# CONFIG_BOOT_TRACER is not set
++# CONFIG_TRACE_BRANCH_PROFILING is not set
++# CONFIG_STACK_TRACER is not set
++# CONFIG_FTRACE_STARTUP_TEST is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_ERRORS=y
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_LL is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_XOR_BLOCKS=m
++CONFIG_ASYNC_CORE=m
++CONFIG_ASYNC_MEMCPY=m
++CONFIG_ASYNC_XOR=m
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++# CONFIG_CRYPTO_FIPS is not set
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++CONFIG_CRYPTO_GF128MUL=m
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_CRYPTD=m
++# CONFIG_CRYPTO_AUTHENC is not set
++CONFIG_CRYPTO_TEST=m
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=m
++CONFIG_CRYPTO_PCBC=m
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_HMAC=m
++CONFIG_CRYPTO_XCBC=m
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++CONFIG_CRYPTO_MD4=m
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_MICHAEL_MIC=y
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++CONFIG_CRYPTO_SHA1=m
++CONFIG_CRYPTO_SHA256=m
++CONFIG_CRYPTO_SHA512=m
++CONFIG_CRYPTO_TGR192=m
++CONFIG_CRYPTO_WP512=m
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++CONFIG_CRYPTO_ANUBIS=m
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_BLOWFISH=m
++CONFIG_CRYPTO_CAMELLIA=m
++CONFIG_CRYPTO_CAST5=m
++CONFIG_CRYPTO_CAST6=m
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_FCRYPT=m
++CONFIG_CRYPTO_KHAZAD=m
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++CONFIG_CRYPTO_SERPENT=m
++CONFIG_CRYPTO_TEA=m
++CONFIG_CRYPTO_TWOFISH=m
++CONFIG_CRYPTO_TWOFISH_COMMON=m
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=m
++# CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_FIND_LAST_BIT=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++CONFIG_CRC7=y
++CONFIG_LIBCRC32C=y
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 0a1099e..3c664a9 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -37,6 +37,7 @@
+ #include <mach/common.h>
+ #include <mach/dma.h>
+ #include <mach/gpmc.h>
++#include <mach/display.h>
+ 
+ #include <mach/control.h>
+ 
+@@ -242,6 +243,35 @@ static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
+ 	},
+ };
+ 
++
++#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO	91
++#define SDP2430_LCD_PANEL_ENABLE_GPIO		154
++#if 0
++#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO	24
++#define SDP3430_LCD_PANEL_ENABLE_GPIO		28
++#else
++#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO	8
++#define SDP3430_LCD_PANEL_ENABLE_GPIO		5
++#endif
++
++#define PM_RECEIVER             TWL4030_MODULE_PM_RECEIVER
++#define ENABLE_VAUX2_DEDICATED  0x09
++#define ENABLE_VAUX2_DEV_GRP    0x20
++#define ENABLE_VAUX3_DEDICATED	0x03
++#define ENABLE_VAUX3_DEV_GRP	0x20
++
++#define ENABLE_VPLL2_DEDICATED	0x05
++#define ENABLE_VPLL2_DEV_GRP	0xE0
++#define TWL4030_VPLL2_DEV_GRP	0x33
++#define TWL4030_VPLL2_DEDICATED	0x36
++
++#define t2_out(c, r, v) twl4030_i2c_write_u8(c, r, v)
++
++static unsigned backlight_gpio;
++static unsigned enable_gpio;
++static int lcd_enabled;
++static int dvi_enabled;
++
+ static struct platform_device sdp3430_lcd_device = {
+ 	.name		= "sdp2430_lcd",
+ 	.id		= -1,
+@@ -257,9 +287,198 @@ static struct regulator_consumer_supply sdp3430_vdvi_supply = {
+ 	.dev		= &sdp3430_lcd_device.dev,
+ };
+ 
++static void enable_vpll2(int enable)
++{
++	u8 ded_val, grp_val;
++
++	if (enable) {
++		ded_val = ENABLE_VPLL2_DEDICATED;
++		grp_val = ENABLE_VPLL2_DEV_GRP;
++	} else {
++		ded_val = 0;
++		grp_val = 0;
++	}
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ded_val, TWL4030_VPLL2_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			grp_val, TWL4030_VPLL2_DEV_GRP);
++}
++
++static int sdp3430_dsi_power_up(void)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0)
++		enable_vpll2(1);
++	return 0;
++}
++
++static void sdp3430_dsi_power_down(void)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0)
++		enable_vpll2(0);
++}
++
++static void __init sdp3430_display_init(void)
++{
++	int r;
++
++	enable_gpio    = SDP3430_LCD_PANEL_ENABLE_GPIO;
++	backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
++
++	r = gpio_request(enable_gpio, "LCD reset");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD reset GPIO\n");
++		goto err0;
++	}
++
++	r = gpio_request(backlight_gpio, "LCD Backlight");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD backlight GPIO\n");
++		goto err1;
++	}
++
++	gpio_direction_output(enable_gpio, 0);
++	gpio_direction_output(backlight_gpio, 0);
++
++	return;
++err1:
++	gpio_free(enable_gpio);
++err0:
++	return;
++}
++
++static int sdp3430_panel_enable_lcd(struct omap_display *display)
++{
++	u8 ded_val, ded_reg;
++	u8 grp_val, grp_reg;
++
++	if (dvi_enabled) {
++		printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++		return -EINVAL;
++	}
++
++	ded_reg = TWL4030_VAUX3_DEDICATED;
++	ded_val = ENABLE_VAUX3_DEDICATED;
++	grp_reg = TWL4030_VAUX3_DEV_GRP;
++	grp_val = ENABLE_VAUX3_DEV_GRP;
++
++	gpio_direction_output(enable_gpio, 1);
++	gpio_direction_output(backlight_gpio, 1);
++
++	if (0 != t2_out(PM_RECEIVER, ded_val, ded_reg))
++		return -EIO;
++	if (0 != t2_out(PM_RECEIVER, grp_val, grp_reg))
++		return -EIO;
++
++	sdp3430_dsi_power_up();
++
++	lcd_enabled = 1;
++
++	return 0;
++}
++
++static void sdp3430_panel_disable_lcd(struct omap_display *display)
++{
++	lcd_enabled = 0;
++
++	sdp3430_dsi_power_down();
++
++	gpio_direction_output(enable_gpio, 0);
++	gpio_direction_output(backlight_gpio, 0);
++}
++
++static struct omap_dss_display_config sdp3430_display_data = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "lcd",
++	.panel_name = "sharp-ls037v7dw01",
++	.u.dpi.data_lines = 16,
++	.panel_enable = sdp3430_panel_enable_lcd,
++	.panel_disable = sdp3430_panel_disable_lcd,
++};
++
++static int sdp3430_panel_enable_dvi(struct omap_display *display)
++{
++	if (lcd_enabled) {
++		printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++		return -EINVAL;
++	}
++
++	sdp3430_dsi_power_up();
++
++	dvi_enabled = 1;
++
++	return 0;
++}
++
++static void sdp3430_panel_disable_dvi(struct omap_display *display)
++{
++	sdp3430_dsi_power_down();
++
++	dvi_enabled = 0;
++}
++
++
++static struct omap_dss_display_config sdp3430_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-generic",
++	.u.dpi.data_lines = 24,
++	.panel_enable = sdp3430_panel_enable_dvi,
++	.panel_disable = sdp3430_panel_disable_dvi,
++};
++
++static int sdp3430_panel_enable_tv(struct omap_display *display)
++{
++#define ENABLE_VDAC_DEDICATED           0x03
++#define ENABLE_VDAC_DEV_GRP             0x20
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEDICATED,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++
++	return 0;
++}
++
++static void sdp3430_panel_disable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_dss_display_config sdp3430_display_data_tv = {
++	.type = OMAP_DISPLAY_TYPE_VENC,
++	.name = "tv",
++	.u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++	.panel_enable = sdp3430_panel_enable_tv,
++	.panel_disable = sdp3430_panel_disable_tv,
++};
++
++static struct omap_dss_board_info sdp3430_dss_data = {
++	.dsi_power_up = sdp3430_dsi_power_up,
++	.dsi_power_down = sdp3430_dsi_power_down,
++	.num_displays = 3,
++	.displays = {
++		&sdp3430_display_data,
++		&sdp3430_display_data_dvi,
++		&sdp3430_display_data_tv,
++	}
++};
++
++static struct platform_device sdp3430_dss_device = {
++	.name          = "omapdss",
++	.id            = -1,
++	.dev            = {
++		.platform_data = &sdp3430_dss_data,
++	},
++};
++
+ static struct platform_device *sdp3430_devices[] __initdata = {
+ 	&sdp3430_smc91x_device,
+-	&sdp3430_lcd_device,
++	&sdp3430_dss_device,
+ };
+ 
+ static inline void __init sdp3430_init_smc91x(void)
+@@ -306,13 +525,8 @@ static struct omap_uart_config sdp3430_uart_config __initdata = {
+ 	.enabled_uarts	= ((1 << 0) | (1 << 1) | (1 << 2)),
+ };
+ 
+-static struct omap_lcd_config sdp3430_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
+-};
+-
+ static struct omap_board_config_kernel sdp3430_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&sdp3430_uart_config },
+-	{ OMAP_TAG_LCD,		&sdp3430_lcd_config },
+ };
+ 
+ static int sdp3430_batt_table[] = {
+@@ -681,6 +895,7 @@ static void __init omap_3430sdp_init(void)
+ 	omap_serial_init();
+ 	usb_musb_init();
+ 	usb_ehci_init();
++	sdp3430_display_init();
+ }
+ 
+ static void __init omap_3430sdp_map_io(void)
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 346351e..b67e7a5 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -30,6 +30,7 @@
+ 
+ #include <linux/regulator/machine.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/hardware.h>
+ #include <asm/mach-types.h>
+@@ -43,6 +44,7 @@
+ #include <mach/gpmc.h>
+ #include <mach/nand.h>
+ #include <mach/mux.h>
++#include <mach/display.h>
+ 
+ #include "twl4030-generic-scripts.h"
+ #include "mmc-twl4030.h"
+@@ -312,10 +314,6 @@ static void __init omap3_beagle_init_irq(void)
+ 	omap_gpio_init();
+ }
+ 
+-static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
+-};
+-
+ static struct gpio_led gpio_leds[] = {
+ 	{
+ 		.name			= "beagleboard::usr0",
+@@ -369,13 +367,94 @@ static struct platform_device keys_gpio = {
+ 	},
+ };
+ 
++/* DSS */
++
++static int beagle_enable_dvi(struct omap_display *display)
++{
++	if (display->hw_config.panel_reset_gpio != -1)
++		gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
++
++	return 0;
++}
++
++static void beagle_disable_dvi(struct omap_display *display)
++{
++	if (display->hw_config.panel_reset_gpio != -1)
++		gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
++}
++
++static struct omap_dss_display_config beagle_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-generic",
++	.u.dpi.data_lines = 24,
++	.panel_reset_gpio = 170,
++	.panel_enable = beagle_enable_dvi,
++	.panel_disable = beagle_disable_dvi,
++};
++
++
++static int beagle_panel_enable_tv(struct omap_display *display)
++{
++#define ENABLE_VDAC_DEDICATED           0x03
++#define ENABLE_VDAC_DEV_GRP             0x20
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEDICATED,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++
++	return 0;
++}
++
++static void beagle_panel_disable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_dss_display_config beagle_display_data_tv = {
++	.type = OMAP_DISPLAY_TYPE_VENC,
++	.name = "tv",
++	.u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++	.panel_enable = beagle_panel_enable_tv,
++	.panel_disable = beagle_panel_disable_tv,
++};
++
++static struct omap_dss_board_info beagle_dss_data = {
++	.num_displays = 2,
++	.displays = {
++		&beagle_display_data_dvi,
++		&beagle_display_data_tv,
++	}
++};
++
++static struct platform_device beagle_dss_device = {
++	.name          = "omapdss",
++	.id            = -1,
++	.dev            = {
++		.platform_data = &beagle_dss_data,
++	},
++};
++
++static void __init beagle_display_init(void)
++{
++	int r;
++
++	r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
++	if (r < 0)
++		printk(KERN_ERR "Unable to get DVI reset GPIO\n");
++}
++
+ static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&omap3_beagle_uart_config },
+-	{ OMAP_TAG_LCD,		&omap3_beagle_lcd_config },
+ };
+ 
+ static struct platform_device *omap3_beagle_devices[] __initdata = {
+-	&omap3_beagle_lcd_device,
++	&beagle_dss_device,
+ 	&leds_gpio,
+ 	&keys_gpio,
+ };
+@@ -428,13 +507,11 @@ static void __init omap3_beagle_init(void)
+ 	omap_serial_init();
+ 
+ 	omap_cfg_reg(J25_34XX_GPIO170);
+-	gpio_request(170, "DVI_nPD");
+-	/* REVISIT leave DVI powered down until it's needed ... */
+-	gpio_direction_output(170, true);
+ 
+ 	usb_musb_init();
+ 	usb_ehci_init();
+ 	omap3beagle_flash_init();
++	beagle_display_init();
+ }
+ 
+ static void __init omap3_beagle_map_io(void)
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 024d7c4..6f5a866 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -36,6 +36,7 @@
+ #include <mach/usb.h>
+ #include <mach/common.h>
+ #include <mach/mcspi.h>
++#include <mach/display.h>
+ 
+ #include "sdram-micron-mt46h32m32lf-6.h"
+ #include "twl4030-generic-scripts.h"
+@@ -216,13 +217,215 @@ static int __init omap3_evm_i2c_init(void)
+ 	return 0;
+ }
+ 
+-static struct platform_device omap3_evm_lcd_device = {
+-	.name		= "omap3evm_lcd",
+-	.id		= -1,
++#define LCD_PANEL_LR		2
++#define LCD_PANEL_UD		3
++#define LCD_PANEL_INI		152
++#define LCD_PANEL_ENABLE_GPIO	153
++#define LCD_PANEL_QVGA		154
++#define LCD_PANEL_RESB		155
++
++#define ENABLE_VDAC_DEDICATED	0x03
++#define ENABLE_VDAC_DEV_GRP	0x20
++#define ENABLE_VPLL2_DEDICATED	0x05
++#define ENABLE_VPLL2_DEV_GRP	0xE0
++
++#define TWL4030_GPIODATA_IN3	0x03
++#define TWL4030_GPIODATA_DIR3	0x06
++#define TWL4030_VPLL2_DEV_GRP	0x33
++#define TWL4030_VPLL2_DEDICATED	0x36
++
++static int lcd_enabled;
++static int dvi_enabled;
++
++static void __init omap3_evm_display_init(void)
++{
++	int r;
++	r = gpio_request(LCD_PANEL_LR, "lcd_panel_lr");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_LR\n");
++		return;
++	}
++	r = gpio_request(LCD_PANEL_UD, "lcd_panel_ud");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_UD\n");
++		goto err_1;
++	}
++
++	r = gpio_request(LCD_PANEL_INI, "lcd_panel_ini");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_INI\n");
++		goto err_2;
++	}
++	r = gpio_request(LCD_PANEL_RESB, "lcd_panel_resb");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_RESB\n");
++		goto err_3;
++	}
++	r = gpio_request(LCD_PANEL_QVGA, "lcd_panel_qvga");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_QVGA\n");
++		goto err_4;
++	}
++
++	gpio_direction_output(LCD_PANEL_LR, 0);
++	gpio_direction_output(LCD_PANEL_UD, 0);
++	gpio_direction_output(LCD_PANEL_INI, 0);
++	gpio_direction_output(LCD_PANEL_RESB, 0);
++	gpio_direction_output(LCD_PANEL_QVGA, 0);
++
++#define TWL_LED_LEDEN           0x00
++#define TWL_PWMA_PWMAON         0x00
++#define TWL_PWMA_PWMAOFF        0x01
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
++
++	gpio_direction_output(LCD_PANEL_RESB, 1);
++	gpio_direction_output(LCD_PANEL_INI, 1);
++	gpio_direction_output(LCD_PANEL_QVGA, 0);
++	gpio_direction_output(LCD_PANEL_LR, 1);
++	gpio_direction_output(LCD_PANEL_UD, 1);
++
++	return;
++
++err_4:
++	gpio_free(LCD_PANEL_RESB);
++err_3:
++	gpio_free(LCD_PANEL_INI);
++err_2:
++	gpio_free(LCD_PANEL_UD);
++err_1:
++	gpio_free(LCD_PANEL_LR);
++
++}
++
++static int omap3_evm_panel_enable_lcd(struct omap_display *display)
++{
++	if (dvi_enabled) {
++		printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++		return -EINVAL;
++	}
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
++	}
++	gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
++	lcd_enabled = 1;
++	return 0;
++}
++
++static void omap3_evm_panel_disable_lcd(struct omap_display *display)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEV_GRP);
++	}
++	gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
++	lcd_enabled = 0;
++}
++
++static struct omap_dss_display_config omap3_evm_display_data = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "lcd",
++	.panel_name = "sharp-ls037v7dw01",
++	.u.dpi.data_lines = 18,
++	.panel_enable = omap3_evm_panel_enable_lcd,
++	.panel_disable = omap3_evm_panel_disable_lcd,
+ };
+ 
+-static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
++static int omap3_evm_panel_enable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEDICATED, TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++	return 0;
++}
++
++static void omap3_evm_panel_disable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_dss_display_config omap3_evm_display_data_tv = {
++	.type = OMAP_DISPLAY_TYPE_VENC,
++	.name = "tv",
++	.u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++	.panel_enable = omap3_evm_panel_enable_tv,
++	.panel_disable = omap3_evm_panel_disable_tv,
++};
++
++
++static int omap3_evm_panel_enable_dvi(struct omap_display *display)
++{
++	if (lcd_enabled) {
++		printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++		return -EINVAL;
++	}
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
++	}
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++			TWL4030_GPIODATA_IN3);
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++			TWL4030_GPIODATA_DIR3);
++	dvi_enabled = 1;
++
++	return 0;
++}
++
++static void omap3_evm_panel_disable_dvi(struct omap_display *display)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEV_GRP);
++	}
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++			TWL4030_GPIODATA_IN3);
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++			TWL4030_GPIODATA_DIR3);
++	dvi_enabled = 0;
++}
++
++
++static struct omap_dss_display_config omap3_evm_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-generic",
++	.u.dpi.data_lines = 24,
++	.panel_enable = omap3_evm_panel_enable_dvi,
++	.panel_disable = omap3_evm_panel_disable_dvi,
++};
++
++static struct omap_dss_board_info omap3_evm_dss_data = {
++	.num_displays = 3,
++	.displays = {
++		&omap3_evm_display_data,
++		&omap3_evm_display_data_dvi,
++		&omap3_evm_display_data_tv,
++	}
++};
++static struct platform_device omap3_evm_dss_device = {
++	.name		= "omapdss",
++	.id		= -1,
++	.dev            = {
++		.platform_data = &omap3_evm_dss_data,
++	},
+ };
+ 
+ static void ads7846_dev_init(void)
+@@ -281,11 +484,10 @@ static void __init omap3_evm_init_irq(void)
+ 
+ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&omap3_evm_uart_config },
+-	{ OMAP_TAG_LCD,		&omap3_evm_lcd_config },
+ };
+ 
+ static struct platform_device *omap3_evm_devices[] __initdata = {
+-	&omap3_evm_lcd_device,
++	&omap3_evm_dss_device,
+ 	&omap3evm_smc911x_device,
+ };
+ 
+@@ -305,6 +507,7 @@ static void __init omap3_evm_init(void)
+ 	usb_ehci_init();
+ 	omap3evm_flash_init();
+ 	ads7846_dev_init();
++	omap3_evm_display_init();
+ }
+ 
+ static void __init omap3_evm_map_io(void)
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index 071f4b0..267bb6b 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -41,6 +41,7 @@
+ #include <mach/board-overo.h>
+ #include <mach/board.h>
+ #include <mach/common.h>
++#include <mach/display.h>
+ #include <mach/gpio.h>
+ #include <mach/gpmc.h>
+ #include <mach/hardware.h>
+@@ -176,6 +177,9 @@ static void __init overo_ads7846_init(void)
+ static inline void __init overo_ads7846_init(void) { return; }
+ #endif
+ 
++static int lcd_enabled;
++static int dvi_enabled;
++
+ static struct mtd_partition overo_nand_partitions[] = {
+ 	{
+ 		.name           = "xloader",
+@@ -360,22 +364,101 @@ static void __init overo_init_irq(void)
+ 	omap_gpio_init();
+ }
+ 
+-static struct platform_device overo_lcd_device = {
+-	.name		= "overo_lcd",
+-	.id		= -1,
++/* DSS */
++
++#define OVERO_GPIO_LCD_EN 144
++
++static void __init overo_display_init(void)
++{
++	int r;
++
++	r = gpio_request(OVERO_GPIO_LCD_EN, "display enable");
++	if (r)
++		printk("fail1\n");
++	r = gpio_direction_output(OVERO_GPIO_LCD_EN, 1);
++	if (r)
++		printk("fail2\n");
++	gpio_export(OVERO_GPIO_LCD_EN, 0);
++}
++
++static int overo_panel_enable_dvi(struct omap_display *display)
++{
++	if (lcd_enabled) {
++		printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++		return -EINVAL;
++	}
++	dvi_enabled = 1;
++
++	gpio_set_value(OVERO_GPIO_LCD_EN, 1);
++
++	return 0;
++}
++
++static void overo_panel_disable_dvi(struct omap_display *display)
++{
++	gpio_set_value(OVERO_GPIO_LCD_EN, 0);
++
++	dvi_enabled = 0;
++}
++
++static struct omap_dss_display_config overo_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-generic",
++	.u.dpi.data_lines = 24,
++	.panel_enable = overo_panel_enable_dvi,
++	.panel_disable = overo_panel_disable_dvi,
+ };
+ 
+-static struct omap_lcd_config overo_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
++static int overo_panel_enable_lcd(struct omap_display *display)
++{
++	if (dvi_enabled) {
++		printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++		return -EINVAL;
++	}
++
++	gpio_set_value(OVERO_GPIO_LCD_EN, 1);
++	lcd_enabled = 1;
++	return 0;
++}
++
++static void overo_panel_disable_lcd(struct omap_display *display)
++{
++	gpio_set_value(OVERO_GPIO_LCD_EN, 0);
++	lcd_enabled = 0;
++}
++
++static struct omap_dss_display_config overo_display_data_lcd = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "lcd43",
++	.panel_name = "samsung-lte430wq-f0c",
++	.u.dpi.data_lines = 24,
++	.panel_enable = overo_panel_enable_lcd,
++	.panel_disable = overo_panel_disable_lcd,
++ };
++
++static struct omap_dss_board_info overo_dss_data = {
++	.num_displays = 2,
++	.displays = {
++		&overo_display_data_dvi,
++		&overo_display_data_lcd,
++	}
++};
++
++static struct platform_device overo_dss_device = {
++	.name          = "omapdss",
++	.id            = -1,
++	.dev            = {
++		.platform_data = &overo_dss_data,
++	},
+ };
+ 
+ static struct omap_board_config_kernel overo_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&overo_uart_config },
+-	{ OMAP_TAG_LCD,		&overo_lcd_config },
+ };
+ 
+ static struct platform_device *overo_devices[] __initdata = {
+-	&overo_lcd_device,
++	&overo_dss_device,
+ };
+ 
+ static void __init overo_init(void)
+@@ -390,6 +473,7 @@ static void __init overo_init(void)
+ 	overo_flash_init();
+ 	overo_init_smsc911x();
+ 	overo_ads7846_init();
++	overo_display_init();
+ 
+ 	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
+ 			  "OVERO_GPIO_W2W_NRESET") == 0) &&
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch
new file mode 100644
index 0000000000..f4cd192bdd
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch
@@ -0,0 +1,39 @@
+From 4741076cae4f4284e1fff9a03f35475b8455af54 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Wed, 1 Apr 2009 14:36:39 +0200
+Subject: [PATCH 08/69] DSS2: Add function to display object to get the backlight level
+
+This is needed by an upcoming patch that changes the backlight
+initialization to use the backlight level set by the bootloader.
+
+Also add a field for the maximum backlight level.
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ arch/arm/plat-omap/include/mach/display.h |    3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+index 6288353..6b702c7 100644
+--- a/arch/arm/plat-omap/include/mach/display.h
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -211,6 +211,8 @@ struct omap_dss_display_config {
+ 	int panel_reset_gpio;
+ 	int ctrl_reset_gpio;
+ 
++	int max_backlight_level;
++
+ 	const char *name;		/* for debug */
+ 	const char *ctrl_name;
+ 	const char *panel_name;
+@@ -225,6 +227,7 @@ struct omap_dss_display_config {
+ 	void (*ctrl_disable)(struct omap_display *display);
+ 	int (*set_backlight)(struct omap_display *display,
+ 			int level);
++	int (*get_backlight)(struct omap_display *display);
+ };
+ 
+ struct device;
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0009-DSS2-Add-acx565akm-panel.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0009-DSS2-Add-acx565akm-panel.patch
new file mode 100644
index 0000000000..82a1474056
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0009-DSS2-Add-acx565akm-panel.patch
@@ -0,0 +1,778 @@
+From 66e16f86d3f4c5b34b37e965c65102b7192371de Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Thu, 2 Apr 2009 11:47:13 +0300
+Subject: [PATCH 09/69] DSS2: Add acx565akm panel
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ drivers/video/omap2/displays/Kconfig           |    8 +
+ drivers/video/omap2/displays/Makefile          |    2 +
+ drivers/video/omap2/displays/panel-acx565akm.c |  712 ++++++++++++++++++++++++
+ drivers/video/omap2/displays/panel-acx565akm.h |    9 +
+ 4 files changed, 731 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/displays/panel-acx565akm.c
+ create mode 100644 drivers/video/omap2/displays/panel-acx565akm.h
+
+diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
+index 356ceb1..3feecee 100644
+--- a/drivers/video/omap2/displays/Kconfig
++++ b/drivers/video/omap2/displays/Kconfig
+@@ -28,4 +28,12 @@ config CTRL_BLIZZARD
+         tristate "Blizzard Controller"
+         help
+           Blizzard Controller (hack)
++
++config PANEL_ACX565AKM
++        tristate "ACX565AKM LCD Panel"
++        depends on OMAP2_DSS_SDI
++        select BACKLIGHT_CLASS_DEVICE
++        help
++          LCD Panel used in RX51
++
+ endmenu
+diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
+index 1b74b7e..9bafcb6 100644
+--- a/drivers/video/omap2/displays/Makefile
++++ b/drivers/video/omap2/displays/Makefile
+@@ -4,3 +4,5 @@ obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
+ 
+ obj-$(CONFIG_CTRL_BLIZZARD) += ctrl-blizzard.o
+ obj-$(CONFIG_PANEL_N800) += panel-n800.o
++
++obj-$(CONFIG_PANEL_ACX565AKM) += panel-acx565akm.o
+diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c
+new file mode 100644
+index 0000000..2679d6c
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-acx565akm.c
+@@ -0,0 +1,712 @@
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/spi/spi.h>
++#include <linux/jiffies.h>
++#include <linux/sched.h>
++#include <linux/backlight.h>
++#include <linux/fb.h>
++
++#include <mach/display.h>
++#include <mach/dma.h>
++
++#include "panel-acx565akm.h"
++
++#define MIPID_CMD_READ_DISP_ID         0x04
++#define MIPID_CMD_READ_RED             0x06
++#define MIPID_CMD_READ_GREEN           0x07
++#define MIPID_CMD_READ_BLUE            0x08
++#define MIPID_CMD_READ_DISP_STATUS     0x09
++#define MIPID_CMD_RDDSDR               0x0F
++#define MIPID_CMD_SLEEP_IN             0x10
++#define MIPID_CMD_SLEEP_OUT            0x11
++#define MIPID_CMD_DISP_OFF             0x28
++#define MIPID_CMD_DISP_ON              0x29
++#define MIPID_CMD_WRITE_DISP_BRIGHTNESS        0x51
++#define MIPID_CMD_READ_DISP_BRIGHTNESS 0x52
++#define MIPID_CMD_WRITE_CTRL_DISP      0x53
++
++#define CTRL_DISP_BRIGHTNESS_CTRL_ON   (1 << 5)
++#define CTRL_DISP_AMBIENT_LIGHT_CTRL_ON        (1 << 4)
++#define CTRL_DISP_BACKLIGHT_ON         (1 << 2)
++#define CTRL_DISP_AUTO_BRIGHTNESS_ON   (1 << 1)
++
++#define MIPID_CMD_READ_CTRL_DISP       0x54
++#define MIPID_CMD_WRITE_CABC           0x55
++#define MIPID_CMD_READ_CABC            0x56
++
++#define MIPID_VER_LPH8923              3
++#define MIPID_VER_LS041Y3              4
++#define MIPID_VER_L4F00311             8
++#define MIPID_VER_ACX565AKM            9
++
++struct acx565akm_device {
++       struct backlight_device *bl_dev;
++       int             enabled;
++       int             model;
++       int             revision;
++       u8              display_id[3];
++       int             has_bc:1;
++       int             has_cabc:1;
++       unsigned int    saved_bklight_level;
++       unsigned long   hw_guard_end;           /* next value of jiffies
++                                                  when we can issue the
++                                                  next sleep in/out command */
++       unsigned long   hw_guard_wait;          /* max guard time in jiffies */
++
++       struct spi_device       *spi;
++       struct mutex            mutex;
++       struct omap_panel       panel;
++       struct omap_display     *display;
++};
++
++static int acx565akm_bl_update_status(struct backlight_device *dev);
++
++static void acx565akm_transfer(struct acx565akm_device *md, int cmd,
++                             const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
++{
++       struct spi_message      m;
++       struct spi_transfer     *x, xfer[5];
++       int                     r;
++
++       BUG_ON(md->spi == NULL);
++
++       spi_message_init(&m);
++
++       memset(xfer, 0, sizeof(xfer));
++       x = &xfer[0];
++
++       cmd &=  0xff;
++       x->tx_buf       = &cmd;
++       x->bits_per_word = 9;
++       x->len          = 2;
++
++       if (rlen > 1 && wlen == 0) {
++               /*
++                * Between the command and the response data there is a
++                * dummy clock cycle. Add an extra bit after the command
++                * word to account for this.
++                */
++               x->bits_per_word = 10;
++               cmd <<= 1;
++       }
++       spi_message_add_tail(x, &m);
++
++       if (wlen) {
++               x++;
++               x->tx_buf       = wbuf;
++               x->len          = wlen;
++               x->bits_per_word = 9;
++               spi_message_add_tail(x, &m);
++       }
++
++       if (rlen) {
++               x++;
++               x->rx_buf       = rbuf;
++               x->len          = rlen;
++               spi_message_add_tail(x, &m);
++       }
++
++       r = spi_sync(md->spi, &m);
++       if (r < 0)
++               dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
++}
++
++static inline void acx565akm_cmd(struct acx565akm_device *md, int cmd)
++{
++       acx565akm_transfer(md, cmd, NULL, 0, NULL, 0);
++}
++
++static inline void acx565akm_write(struct acx565akm_device *md,
++                              int reg, const u8 *buf, int len)
++{
++       acx565akm_transfer(md, reg, buf, len, NULL, 0);
++}
++
++static inline void acx565akm_read(struct acx565akm_device *md,
++                             int reg, u8 *buf, int len)
++{
++       acx565akm_transfer(md, reg, NULL, 0, buf, len);
++}
++
++static void hw_guard_start(struct acx565akm_device *md, int guard_msec)
++{
++       md->hw_guard_wait = msecs_to_jiffies(guard_msec);
++       md->hw_guard_end = jiffies + md->hw_guard_wait;
++}
++
++static void hw_guard_wait(struct acx565akm_device *md)
++{
++       unsigned long wait = md->hw_guard_end - jiffies;
++
++       if ((long)wait > 0 && wait <= md->hw_guard_wait) {
++               set_current_state(TASK_UNINTERRUPTIBLE);
++               schedule_timeout(wait);
++       }
++}
++
++static void set_sleep_mode(struct acx565akm_device *md, int on)
++{
++       int cmd, sleep_time = 50;
++
++       if (on)
++               cmd = MIPID_CMD_SLEEP_IN;
++       else
++               cmd = MIPID_CMD_SLEEP_OUT;
++       hw_guard_wait(md);
++       acx565akm_cmd(md, cmd);
++       hw_guard_start(md, 120);
++       /*
++        * When we enable the panel, it seems we _have_ to sleep
++        * 120 ms before sending the init string. When disabling the
++        * panel we'll sleep for the duration of 2 frames, so that the
++        * controller can still provide the PCLK,HS,VS signals. */
++       if (!on)
++               sleep_time = 120;
++       msleep(sleep_time);
++}
++
++static void set_display_state(struct acx565akm_device *md, int enabled)
++{
++       int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
++
++       acx565akm_cmd(md, cmd);
++}
++
++static int panel_enabled(struct acx565akm_device *md)
++{
++       u32 disp_status;
++       int enabled;
++
++       acx565akm_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
++       disp_status = __be32_to_cpu(disp_status);
++       enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
++       dev_dbg(&md->spi->dev,
++               "LCD panel %senabled by bootloader (status 0x%04x)\n",
++               enabled ? "" : "not ", disp_status);
++       return enabled;
++}
++
++static void enable_backlight_ctrl(struct acx565akm_device *md, int enable)
++{
++       u16 ctrl;
++
++       acx565akm_read(md, MIPID_CMD_READ_CTRL_DISP, (u8 *)&ctrl, 1);
++       if (enable) {
++               ctrl |= CTRL_DISP_BRIGHTNESS_CTRL_ON |
++                       CTRL_DISP_BACKLIGHT_ON;
++       } else {
++               ctrl &= ~(CTRL_DISP_BRIGHTNESS_CTRL_ON |
++                         CTRL_DISP_BACKLIGHT_ON);
++       }
++
++       ctrl |= 1 << 8;
++       acx565akm_write(md, MIPID_CMD_WRITE_CTRL_DISP, (u8 *)&ctrl, 2);
++}
++
++static void set_cabc_mode(struct acx565akm_device *md, int mode)
++{
++       u16 cabc_ctrl;
++
++       cabc_ctrl = 0;
++       acx565akm_read(md, MIPID_CMD_READ_CABC, (u8 *)&cabc_ctrl, 1);
++       cabc_ctrl &= ~3;
++       cabc_ctrl |= (1 << 8) | (mode & 3);
++       acx565akm_write(md, MIPID_CMD_WRITE_CABC, (u8 *)&cabc_ctrl, 2);
++}
++
++static int get_cabc_mode(struct acx565akm_device *md)
++{
++       u8 cabc_ctrl;
++
++       acx565akm_read(md, MIPID_CMD_READ_CABC, &cabc_ctrl, 1);
++       return cabc_ctrl & 3;
++}
++
++static int panel_detect(struct acx565akm_device *md)
++{
++       acx565akm_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
++       dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
++               md->display_id[0], md->display_id[1], md->display_id[2]);
++
++       switch (md->display_id[0]) {
++       case 0x10:
++               md->model = MIPID_VER_ACX565AKM;
++               md->panel.name = "acx565akm";
++               md->has_bc = 1;
++               md->has_cabc = 1;
++               break;
++       case 0x29:
++               md->model = MIPID_VER_L4F00311;
++               md->panel.name = "l4f00311";
++               break;
++       case 0x45:
++               md->model = MIPID_VER_LPH8923;
++               md->panel.name = "lph8923";
++               break;
++       case 0x83:
++               md->model = MIPID_VER_LS041Y3;
++               md->panel.name = "ls041y3";
++               break;
++       default:
++               md->panel.name = "unknown";
++               dev_err(&md->spi->dev, "invalid display ID\n");
++               return -ENODEV;
++       }
++
++       md->revision = md->display_id[1];
++
++       pr_info("omapfb: %s rev %02x LCD detected\n",
++                       md->panel.name, md->revision);
++
++       return 0;
++}
++
++static int acx565akm_panel_enable(struct omap_display *display)
++{
++       struct acx565akm_device *md =
++               (struct acx565akm_device *)display->panel->priv;
++
++       dev_dbg(&md->spi->dev, "%s\n", __func__);
++
++       mutex_lock(&md->mutex);
++
++       if (display->hw_config.panel_enable)
++               display->hw_config.panel_enable(display);
++
++       md->enabled = panel_enabled(md);
++
++       if (md->enabled) {
++               dev_dbg(&md->spi->dev, "panel already enabled\n");
++               mutex_unlock(&md->mutex);
++               return 0;
++       }
++
++       set_sleep_mode(md, 0);
++       md->enabled = 1;
++       set_display_state(md, 1);
++
++       mutex_unlock(&md->mutex);
++
++       return acx565akm_bl_update_status(md->bl_dev);
++}
++
++static void acx565akm_panel_disable(struct omap_display *display)
++{
++       struct acx565akm_device *md =
++               (struct acx565akm_device *)display->panel->priv;
++
++       dev_dbg(&md->spi->dev, "%s\n", __func__);
++
++       mutex_lock(&md->mutex);
++
++       if (!md->enabled) {
++               mutex_unlock(&md->mutex);
++               return;
++       }
++       set_display_state(md, 0);
++       set_sleep_mode(md, 1);
++       md->enabled = 0;
++
++       if (display->hw_config.panel_disable)
++               display->hw_config.panel_disable(display);
++
++       mutex_unlock(&md->mutex);
++}
++
++#if 0
++static void acx565akm_set_mode(struct omap_display *display,
++                             int x_res, int y_res, int bpp)
++{
++       struct acx565akm_device *md =
++               (struct acx565akm_device *)display->panel->priv;
++       u16 par;
++
++       switch (bpp) {
++       case 16:
++               par = 0x150;
++               break;
++       case 18:
++               par = 0x160;
++               break;
++       case 24:
++               par = 0x170;
++               break;
++       }
++
++       acx565akm_write(md, 0x3a, (u8 *)&par, 2);
++}
++#endif
++
++static int acx565akm_panel_suspend(struct omap_display *display)
++{
++       acx565akm_panel_disable(display);
++       return 0;
++}
++
++static int acx565akm_panel_resume(struct omap_display *display)
++{
++       return acx565akm_panel_enable(display);
++}
++
++static void acx565akm_set_brightness(struct acx565akm_device *md, int level)
++{
++       int bv;
++
++       bv = level | (1 << 8);
++       acx565akm_write(md, MIPID_CMD_WRITE_DISP_BRIGHTNESS, (u8 *)&bv, 2);
++
++       if (level)
++               enable_backlight_ctrl(md, 1);
++       else
++               enable_backlight_ctrl(md, 0);
++}
++
++static int acx565akm_get_actual_brightness(struct acx565akm_device *md)
++{
++       u8 bv;
++
++       acx565akm_read(md, MIPID_CMD_READ_DISP_BRIGHTNESS, &bv, 1);
++
++       return bv;
++}
++
++static int acx565akm_bl_update_status(struct backlight_device *dev)
++{
++       struct acx565akm_device *md = dev_get_drvdata(&dev->dev);
++       struct omap_display *display = md->display;
++       int r;
++       int level;
++
++       dev_dbg(&md->spi->dev, "%s\n", __func__);
++
++       if (display->hw_config.set_backlight == NULL)
++               return -ENODEV;
++
++       mutex_lock(&md->mutex);
++
++       if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
++                       dev->props.power == FB_BLANK_UNBLANK)
++               level = dev->props.brightness;
++       else
++               level = 0;
++
++       r = 0;
++       if (md->has_bc)
++               acx565akm_set_brightness(md, level);
++       else
++               if (display->hw_config.set_backlight != NULL)
++                       r = display->hw_config.set_backlight(display, level);
++       else
++               r = -ENODEV;
++
++       mutex_unlock(&md->mutex);
++
++       return r;
++}
++
++static int acx565akm_bl_get_intensity(struct backlight_device *dev)
++{
++       struct acx565akm_device *md = dev_get_drvdata(&dev->dev);
++       struct omap_display *display = md->display;
++
++       dev_dbg(&dev->dev, "%s\n", __func__);
++
++       if (md->has_bc && display->hw_config.set_backlight == NULL)
++               return -ENODEV;
++
++       if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
++                       dev->props.power == FB_BLANK_UNBLANK) {
++               if (md->has_bc)
++                       return acx565akm_get_actual_brightness(md);
++               else
++                       return dev->props.brightness;
++       }
++
++       return 0;
++}
++
++static struct backlight_ops acx565akm_bl_ops = {
++       .get_brightness = acx565akm_bl_get_intensity,
++       .update_status  = acx565akm_bl_update_status,
++};
++
++static const char *cabc_modes[] = {
++       "off",          /* used also always when CABC is not supported */
++       "ui",
++       "still-image",
++       "moving-image",
++};
++
++static ssize_t show_cabc_mode(struct device *dev,
++               struct device_attribute *attr,
++               char *buf)
++{
++       struct acx565akm_device *md = dev_get_drvdata(dev);
++       const char *mode_str;
++       int mode;
++       int len;
++
++       if (!md->has_cabc)
++               mode = 0;
++       else
++               mode = get_cabc_mode(md);
++       mode_str = "unknown";
++       if (mode >= 0 && mode < ARRAY_SIZE(cabc_modes))
++               mode_str = cabc_modes[mode];
++       len = snprintf(buf, PAGE_SIZE, "%s\n", mode_str);
++
++       return len < PAGE_SIZE - 1 ? len : PAGE_SIZE - 1;
++}
++
++static ssize_t store_cabc_mode(struct device *dev,
++               struct device_attribute *attr,
++               const char *buf, size_t count)
++{
++       struct acx565akm_device *md = dev_get_drvdata(dev);
++       int i;
++
++       for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) {
++               const char *mode_str = cabc_modes[i];
++               int cmp_len = strlen(mode_str);
++
++               if (count > 0 && buf[count - 1] == '\n')
++                       count--;
++               if (count != cmp_len)
++                       continue;
++
++               if (strncmp(buf, mode_str, cmp_len) == 0)
++                       break;
++       }
++
++       if (i == ARRAY_SIZE(cabc_modes))
++               return -EINVAL;
++
++       if (!md->has_cabc && i != 0)
++               return -EINVAL;
++
++       mutex_lock(&md->mutex);
++       set_cabc_mode(md, i);
++       mutex_unlock(&md->mutex);
++
++       return count;
++}
++
++static ssize_t show_cabc_available_modes(struct device *dev,
++               struct device_attribute *attr,
++               char *buf)
++{
++       struct acx565akm_device *md = dev_get_drvdata(dev);
++       int len;
++       int i;
++
++       if (!md->has_cabc)
++               return snprintf(buf, PAGE_SIZE, "%s\n", cabc_modes[0]);
++
++       for (i = 0, len = 0;
++            len < PAGE_SIZE && i < ARRAY_SIZE(cabc_modes); i++)
++               len += snprintf(&buf[len], PAGE_SIZE - len, "%s%s%s",
++                       i ? " " : "", cabc_modes[i],
++                       i == ARRAY_SIZE(cabc_modes) - 1 ? "\n" : "");
++
++       return len < PAGE_SIZE ? len : PAGE_SIZE - 1;
++}
++
++static DEVICE_ATTR(cabc_mode, S_IRUGO | S_IWUSR,
++               show_cabc_mode, store_cabc_mode);
++static DEVICE_ATTR(cabc_available_modes, S_IRUGO,
++               show_cabc_available_modes, NULL);
++
++static struct attribute *bldev_attrs[] = {
++       &dev_attr_cabc_mode.attr,
++       &dev_attr_cabc_available_modes.attr,
++       NULL,
++};
++
++static struct attribute_group bldev_attr_group = {
++       .attrs = bldev_attrs,
++};
++
++static int acx565akm_panel_init(struct omap_display *display)
++{
++       struct omap_panel *panel = display->panel;
++       struct acx565akm_panel_data *panel_data = display->hw_config.panel_data;
++       struct acx565akm_device *md = (struct acx565akm_device *)panel->priv;
++
++       struct backlight_device *bldev;
++       int brightness;
++       int max_brightness;
++       int r;
++
++       dev_dbg(&md->spi->dev, "%s\n", __func__);
++
++       if (!panel_data) {
++               dev_err(&md->spi->dev, "no panel data\n");
++               return -ENODEV;
++       }
++
++       mutex_init(&md->mutex);
++       md->display = display;
++
++       if (display->hw_config.panel_enable)
++               display->hw_config.panel_enable(display);
++
++       md->enabled = panel_enabled(md);
++
++       r = panel_detect(md);
++       if (r) {
++               if (!md->enabled && display->hw_config.panel_disable)
++                       display->hw_config.panel_disable(display);
++               mutex_unlock(&md->mutex);
++               return r;
++       }
++
++       if (!panel_data->bc_connected) {
++               md->has_bc = 0;
++               md->has_cabc = 0;
++       }
++
++#if 0
++       acx565akm_set_mode(display, panel->timings.x_res, panel->timings.y_res,
++                         panel->bpp);
++#endif
++
++       if (!md->enabled)
++               display->hw_config.panel_disable(display);
++
++       bldev = backlight_device_register("acx565akm", &md->spi->dev,
++                       md, &acx565akm_bl_ops);
++       md->bl_dev = bldev;
++
++       if (md->has_cabc) {
++               r = sysfs_create_group(&bldev->dev.kobj, &bldev_attr_group);
++               if (r) {
++                       dev_err(&bldev->dev, "failed to create sysfs files\n");
++                       backlight_device_unregister(bldev);
++                       return r;
++               }
++       }
++
++       bldev->props.fb_blank = FB_BLANK_UNBLANK;
++       bldev->props.power = FB_BLANK_UNBLANK;
++
++       if (md->has_bc)
++               max_brightness = 255;
++       else
++               max_brightness = display->hw_config.max_backlight_level;
++
++       if (md->has_bc)
++               brightness = acx565akm_get_actual_brightness(md);
++       else {
++               if (display->hw_config.get_backlight != NULL)
++                       brightness = display->hw_config.get_backlight(display);
++               else
++                       brightness = 0;
++       }
++
++       bldev->props.max_brightness = max_brightness;
++       bldev->props.brightness = brightness;
++       acx565akm_bl_update_status(bldev);
++
++       return 0;
++}
++
++static struct omap_panel acx565akm_panel = {
++       .name           = "panel-acx565akm",
++       .init           = acx565akm_panel_init,
++       .suspend        = acx565akm_panel_suspend,
++       .resume         = acx565akm_panel_resume,
++       .enable         = acx565akm_panel_enable,
++       .disable        = acx565akm_panel_disable,
++
++       .timings = {
++               .x_res = 800,
++               .y_res = 480,
++
++               .pixel_clock    = 24000,
++
++               .hsw            = 4,
++               .hfp            = 16,
++               .hbp            = 12,
++
++               .vsw            = 3,
++               .vfp            = 3,
++               .vbp            = 3,
++       },
++
++       .config         = OMAP_DSS_LCD_TFT,
++
++       .recommended_bpp = 16,
++
++       /*
++        * supported modes: 12bpp(444), 16bpp(565), 18bpp(666),  24bpp(888)
++        * resolutions.
++        */
++};
++
++static int acx565akm_spi_probe(struct spi_device *spi)
++{
++       struct acx565akm_device *md;
++
++       dev_dbg(&md->spi->dev, "%s\n", __func__);
++
++       md = kzalloc(sizeof(*md), GFP_KERNEL);
++       if (md == NULL) {
++               dev_err(&spi->dev, "out of memory\n");
++               return -ENOMEM;
++       }
++
++       spi->mode = SPI_MODE_3;
++       md->spi = spi;
++       dev_set_drvdata(&spi->dev, md);
++       md->panel = acx565akm_panel;
++       acx565akm_panel.priv = md;
++
++       omap_dss_register_panel(&acx565akm_panel);
++
++       return 0;
++}
++
++static int acx565akm_spi_remove(struct spi_device *spi)
++{
++       struct acx565akm_device *md = dev_get_drvdata(&spi->dev);
++
++       dev_dbg(&md->spi->dev, "%s\n", __func__);
++
++       sysfs_remove_group(&md->bl_dev->dev.kobj, &bldev_attr_group);
++       backlight_device_unregister(md->bl_dev);
++       omap_dss_unregister_panel(&acx565akm_panel);
++
++       kfree(md);
++
++       return 0;
++}
++
++static struct spi_driver acx565akm_spi_driver = {
++       .driver = {
++               .name   = "acx565akm",
++               .bus    = &spi_bus_type,
++               .owner  = THIS_MODULE,
++       },
++       .probe  = acx565akm_spi_probe,
++       .remove = __devexit_p(acx565akm_spi_remove),
++};
++
++static int __init acx565akm_init(void)
++{
++       return spi_register_driver(&acx565akm_spi_driver);
++}
++
++static void __exit acx565akm_exit(void)
++{
++       spi_unregister_driver(&acx565akm_spi_driver);
++}
++
++module_init(acx565akm_init);
++module_exit(acx565akm_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("acx565akm LCD Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-acx565akm.h b/drivers/video/omap2/displays/panel-acx565akm.h
+new file mode 100644
+index 0000000..6d3727b
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-acx565akm.h
+@@ -0,0 +1,9 @@
++#ifndef __DRIVERS_VIDEO_OMAP2_DISPLAYS_PANEL_ACX565AKM_H
++#define __DRIVERS_VIDEO_OMAP2_DISPLAYS_PANEL_ACX565AKM_H
++
++struct acx565akm_panel_data {
++       unsigned bc_connected:1;
++};
++
++#endif
++
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch
new file mode 100644
index 0000000000..f994327ec1
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch
@@ -0,0 +1,28 @@
+From 370510e24ddbf539392ebb6a1e43280965fcb19b Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Tue, 31 Mar 2009 18:47:32 +0530
+Subject: [PATCH 10/69] DSS2: Small VRFB context allocation bug fixed
+
+This is minor bug while requesting and mapping memory for
+VRFB space.
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+---
+ drivers/video/omap2/omapfb/omapfb-main.c |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index 852abe5..44febef 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -1193,6 +1193,7 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
+ 
+ 		if(!va) {
+ 			printk(KERN_ERR "vrfb: ioremap failed\n");
++			omap_vrfb_release_ctx(&rg->vrfb);
+ 			return -ENOMEM;
+ 		}
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch
new file mode 100644
index 0000000000..2dad1d337f
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch
@@ -0,0 +1,37 @@
+From 370d1f93a32e8fcaeac5c16574417e354af21d08 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Tue, 31 Mar 2009 18:38:31 +0530
+Subject: [PATCH 11/69] DSS2: Allocated memory for Color Look-up-table
+
+We were not allocating memory for CMAP buffer and due to that
+G_CMAP was failing, since it does check for size of CMAP buffer.
+
+Called "fb_alloc_cmap" for llocating memory for CMAP.
+
+We are currently not supporting 1,2,4,8 bpp, so meaning less
+for us as of now. But for completeness this is required.
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+---
+ drivers/video/omap2/omapfb/omapfb-main.c |    5 +++++
+ 1 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index 44febef..afe40a9 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -1525,6 +1525,11 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
+ 		goto err;
+ 
+ 	set_fb_fix(fbi);
++
++	r = fb_alloc_cmap(&fbi->cmap, 256, 0);
++	if (r)
++		dev_err(fbdev->dev, "unable to allocate color map memory\n");
++
+ err:
+ 	return r;
+ }
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0012-DSS2-Fix-DMA-rotation.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0012-DSS2-Fix-DMA-rotation.patch
new file mode 100644
index 0000000000..8e1d139c72
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0012-DSS2-Fix-DMA-rotation.patch
@@ -0,0 +1,65 @@
+From 9c93bcab724b5935d745604773ed43825efefd87 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 13:47:11 +0300
+Subject: [PATCH 12/69] DSS2: Fix DMA rotation
+
+u16 was not a good type for offsets. First, they need to be signed,
+and second, 16 bits is not enough.
+---
+ drivers/video/omap2/dss/dispc.c |   12 ++++++------
+ 1 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index ffb5648..6cea545 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -778,7 +778,7 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
+ 	dispc_write_reg(vsi_reg[plane-1], val);
+ }
+ 
+-static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
++static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
+ {
+ 	const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
+ 				     DISPC_VID_PIXEL_INC(0),
+@@ -787,7 +787,7 @@ static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
+ 	dispc_write_reg(ri_reg[plane], inc);
+ }
+ 
+-static void _dispc_set_row_inc(enum omap_plane plane, u16 inc)
++static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
+ {
+ 	const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
+ 				     DISPC_VID_ROW_INC(0),
+@@ -1123,7 +1123,7 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
+ 	}
+ }
+ 
+-static int pixinc(int pixels, u8 ps)
++static s32 pixinc(int pixels, u8 ps)
+ {
+ 	if (pixels == 1)
+ 		return 1;
+@@ -1140,7 +1140,7 @@ static void calc_rotation_offset(u8 rotation, bool mirror,
+ 		u16 width, u16 height,
+ 		enum omap_color_mode color_mode, bool fieldmode,
+ 		unsigned *offset0, unsigned *offset1,
+-		u16 *row_inc, u16 *pix_inc)
++		s32 *row_inc, s32 *pix_inc)
+ {
+ 	u8 ps;
+ 	u16 fbw, fbh;
+@@ -1298,8 +1298,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 	bool fieldmode = 0;
+ 	int cconv = 0;
+ 	unsigned offset0, offset1;
+-	u16 row_inc;
+-	u16 pix_inc;
++	s32 row_inc;
++	s32 pix_inc;
+ 
+ 	if (plane == OMAP_DSS_GFX) {
+ 		if (width != out_width || height != out_height)
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch
new file mode 100644
index 0000000000..1abc7a8264
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch
@@ -0,0 +1,41 @@
+From 360a55ddd309e3a45b227a4a905ae7120dd16169 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 14:21:12 +0300
+Subject: [PATCH 13/69] DSS2: Verify that overlay paddr != 0
+
+---
+ drivers/video/omap2/dss/dispc.c   |    3 +++
+ drivers/video/omap2/dss/overlay.c |    3 +++
+ 2 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 6cea545..2480a03 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1301,6 +1301,9 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 	s32 row_inc;
+ 	s32 pix_inc;
+ 
++	if (paddr == 0)
++		return -EINVAL;
++
+ 	if (plane == OMAP_DSS_GFX) {
+ 		if (width != out_width || height != out_height)
+ 			return -EINVAL;
+diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
+index 968edbe..9209acf 100644
+--- a/drivers/video/omap2/dss/overlay.c
++++ b/drivers/video/omap2/dss/overlay.c
+@@ -331,6 +331,9 @@ static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
+ 	int r;
+ 	struct omap_overlay_info old_info;
+ 
++	if (info->paddr == 0)
++		return -EINVAL;
++
+ 	old_info = ovl->info;
+ 	ovl->info = *info;
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch
new file mode 100644
index 0000000000..d8aa4eb893
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch
@@ -0,0 +1,51 @@
+From 832b763db235da8e62f7b6ab02bcb8ad6bcb7a01 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 16:48:41 +0300
+Subject: [PATCH 14/69] DSS2: Add function to get DSS logic clock rate
+
+---
+ drivers/video/omap2/dss/dispc.c |   15 +++++++++++++++
+ drivers/video/omap2/dss/dss.h   |    1 +
+ 2 files changed, 16 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 2480a03..1bc23f7 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1850,6 +1850,21 @@ unsigned long dispc_fclk_rate(void)
+ 	return r;
+ }
+ 
++unsigned long dispc_lclk_rate(void)
++{
++	int lcd;
++	unsigned long r;
++	u32 l;
++
++	l = dispc_read_reg(DISPC_DIVISOR);
++
++	lcd = FLD_GET(l, 23, 16);
++
++	r = dispc_fclk_rate();
++
++	return r / lcd;
++}
++
+ unsigned long dispc_pclk_rate(void)
+ {
+ 	int lcd, pcd;
+diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
+index bac5ece..0be42b6 100644
+--- a/drivers/video/omap2/dss/dss.h
++++ b/drivers/video/omap2/dss/dss.h
+@@ -294,6 +294,7 @@ bool dispc_trans_key_enabled(enum omap_channel ch);
+ 
+ void dispc_set_lcd_timings(struct omap_video_timings *timings);
+ unsigned long dispc_fclk_rate(void);
++unsigned long dispc_lclk_rate(void);
+ unsigned long dispc_pclk_rate(void);
+ void dispc_set_pol_freq(struct omap_panel *panel);
+ void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch
new file mode 100644
index 0000000000..a0f2b9f528
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch
@@ -0,0 +1,68 @@
+From a5c235a6f0094494ae1fc1a1ba4728e0d33dfd3b Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 16:49:27 +0300
+Subject: [PATCH 15/69] DSS2: DSI: calculate VP_CLK_RATIO properly
+
+---
+ drivers/video/omap2/dss/dsi.c |   17 +++++++++++------
+ 1 files changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+index 4442931..aecb89d 100644
+--- a/drivers/video/omap2/dss/dsi.c
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -1104,7 +1104,10 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
+ 	enable_clocks(1);
+ 	dsi_enable_pll_clock(1);
+ 
+-	/* configure dispc fck and pixel clock to something sane */
++	/* XXX this should be calculated depending on the screen size,
++	 * required framerate and DSI speed.
++	 * For now 48MHz is enough for 864x480@60 with 360Mbps/lane
++	 * with two lanes */
+ 	r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
+ 	if (r)
+ 		goto err0;
+@@ -1119,7 +1122,7 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
+ 	if (r)
+ 		goto err0;
+ 
+-	/* PLL does not come out of reset without this... */
++	/* XXX PLL does not come out of reset without this... */
+ 	dispc_pck_free_enable(1);
+ 
+ 	if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
+@@ -1128,8 +1131,8 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
+ 		goto err1;
+ 	}
+ 
+-	/* ... but if left on, we get problems when planes do not
+-	 * fill the whole display. No idea about this XXX */
++	/* XXX ... but if left on, we get problems when planes do not
++	 * fill the whole display. No idea about this */
+ 	dispc_pck_free_enable(0);
+ 
+ 	if (enable_hsclk && enable_hsdiv)
+@@ -2214,6 +2217,7 @@ static int dsi_proto_config(struct omap_display *display)
+ {
+ 	u32 r;
+ 	int buswidth = 0;
++	int div;
+ 
+ 	dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
+ 			DSI_FIFO_SIZE_0,
+@@ -2254,8 +2258,9 @@ static int dsi_proto_config(struct omap_display *display)
+ 	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
+ 	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
+ 	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
+-	/* XXX what should the ratio be */
+-	r = FLD_MOD(r, 0, 4, 4);	/* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
++
++	div = dispc_lclk_rate() / dispc_pclk_rate();
++	r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4);	/* VP_CLK_RATIO */
+ 	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
+ 	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
+ 	r = FLD_MOD(r, 2, 13, 12);	/* LINE_BUFFER, 2 lines */
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch
new file mode 100644
index 0000000000..35d65a996d
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch
@@ -0,0 +1,58 @@
+From 6b2c9d84c7accdfe1067fcdc8a00e50674aab4bb Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 2 Apr 2009 17:42:26 +0300
+Subject: [PATCH 16/69] DSS2: DSI: improve packet len calculation
+
+---
+ drivers/video/omap2/dss/dsi.c |   21 ++++++++++++++++-----
+ 1 files changed, 16 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+index aecb89d..66ac6ea 100644
+--- a/drivers/video/omap2/dss/dsi.c
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -2624,17 +2624,28 @@ static void dsi_update_screen_dispc(struct omap_display *display,
+ 		u16 x, u16 y, u16 w, u16 h)
+ {
+ 	int bytespp = 3;
++	int len;
+ 	int total_len;
+-	int line_packet_len;
++	int packet_payload;
++	int packet_len;
+ 	u32 l;
+ 
+ 	if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
+ 		DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
+ 				x, y, w, h);
+ 
+-	/* TODO: one packet could be longer, I think? Max is the line buffer */
+-	line_packet_len = w * bytespp + 1;	/* 1 byte for DCS cmd */
+-	total_len = line_packet_len * h;
++	len = w * h * bytespp;
++
++	/* XXX: one packet could be longer, I think? Line buffer is
++	 * 1024 x 24bits, but we have to put DCS cmd there also.
++	 * 1023 * 3 should work, but causes strange color effects. */
++	packet_payload = min(w, (u16)1020) * bytespp;
++
++	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */
++	total_len = (len / packet_payload) * packet_len;
++
++	if (len % packet_payload)
++		total_len += (len % packet_payload) + 1;
+ 
+ 	display->ctrl->setup_update(display, x, y, w, h);
+ 
+@@ -2646,7 +2657,7 @@ static void dsi_update_screen_dispc(struct omap_display *display,
+ 	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
+ 	dsi_write_reg(DSI_VC_TE(1), l);
+ 
+-	dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
++	dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
+ 
+ 	if (dsi.use_te)
+ 		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch
new file mode 100644
index 0000000000..e9a5dcc67a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch
@@ -0,0 +1,103 @@
+From 85848d329ca3a2d6ee6841cdc11cc5951d187931 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Fri, 3 Apr 2009 19:09:20 +0200
+Subject: [PATCH 17/69] DSS2: Disable video planes on sync lost error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+When encountering the sync lost error disable the display and all video
+planes on the affected manager. Afterwards re-enable the display.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |   50 +++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 50 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 1bc23f7..41734f3 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -2518,29 +2518,79 @@ static void dispc_error_worker(struct work_struct *work)
+ 	}
+ 
+ 	if (errors & DISPC_IRQ_SYNC_LOST) {
++		struct omap_overlay_manager *manager = NULL;
++		bool enable = false;
++
+ 		DSSERR("SYNC_LOST, disabling LCD\n");
++
+ 		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
+ 			struct omap_overlay_manager *mgr;
+ 			mgr = omap_dss_get_overlay_manager(i);
+ 
+ 			if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
++				manager = mgr;
++				enable = mgr->display->state ==
++						OMAP_DSS_DISPLAY_ACTIVE;
+ 				mgr->display->disable(mgr->display);
+ 				break;
+ 			}
+ 		}
++
++		if (manager) {
++			for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++				struct omap_overlay *ovl;
++				ovl = omap_dss_get_overlay(i);
++
++				if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++					continue;
++
++				if (ovl->id != 0 && ovl->manager == manager)
++					dispc_enable_plane(ovl->id, 0);
++			}
++
++			dispc_go(manager->id);
++			mdelay(50);
++			if (enable)
++				manager->display->enable(manager->display);
++		}
+ 	}
+ 
+ 	if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
++		struct omap_overlay_manager *manager = NULL;
++		bool enable = false;
++
+ 		DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
++
+ 		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
+ 			struct omap_overlay_manager *mgr;
+ 			mgr = omap_dss_get_overlay_manager(i);
+ 
+ 			if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
++				manager = mgr;
++				enable = mgr->display->state ==
++						OMAP_DSS_DISPLAY_ACTIVE;
+ 				mgr->display->disable(mgr->display);
+ 				break;
+ 			}
+ 		}
++
++		if (manager) {
++			for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++				struct omap_overlay *ovl;
++				ovl = omap_dss_get_overlay(i);
++
++				if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++					continue;
++
++				if (ovl->id != 0 && ovl->manager == manager)
++					dispc_enable_plane(ovl->id, 0);
++			}
++
++			dispc_go(manager->id);
++			mdelay(50);
++			if (enable)
++				manager->display->enable(manager->display);
++		}
+ 	}
+ 
+ 	if (errors & DISPC_IRQ_OCP_ERR) {
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch
new file mode 100644
index 0000000000..0261db2bd4
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch
@@ -0,0 +1,40 @@
+From 63e15ba8d5f95b13d3abf359da718537d769f112 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Tue, 7 Apr 2009 10:01:58 +0300
+Subject: [PATCH 18/69] DSS2: check for ovl paddr only when enabling
+
+It seems Xvideo uses SETUP_PLANE ioctl even when
+the fb memory has not been allocated. Sigh.
+---
+ drivers/video/omap2/dss/overlay.c |    8 +++++---
+ 1 files changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
+index 9209acf..c047206 100644
+--- a/drivers/video/omap2/dss/overlay.c
++++ b/drivers/video/omap2/dss/overlay.c
+@@ -281,6 +281,11 @@ int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display)
+ 
+ 	info = &ovl->info;
+ 
++	if (info->paddr == 0) {
++		DSSDBG("check_overlay failed: paddr 0\n");
++		return -EINVAL;
++	}
++
+ 	display->get_resolution(display, &dw, &dh);
+ 
+ 	DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n",
+@@ -331,9 +336,6 @@ static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
+ 	int r;
+ 	struct omap_overlay_info old_info;
+ 
+-	if (info->paddr == 0)
+-		return -EINVAL;
+-
+ 	old_info = ovl->info;
+ 	ovl->info = *info;
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch
new file mode 100644
index 0000000000..6569c71471
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch
@@ -0,0 +1,183 @@
+From 67f3fc050ab4e2006d5b7ec6ec341896627181ab Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Mon, 6 Apr 2009 17:32:04 +0200
+Subject: [PATCH 19/69] DSS2: Check fclk limits when configuring video planes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Check that the currect functional clock is fast enough to support
+the requested scaling ratios. Also check if 5-tap filtering can be
+used even though the downscaling ratio is less than 1:2 since the
+functional clock rate required for 5-tap filtering can be less than
+the requirement for 3-tap filtering, and 5-tap filtering should look
+better.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |  104 ++++++++++++++++++++++++++++++++++++---
+ 1 files changed, 97 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 41734f3..61861d8 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1026,11 +1026,11 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
+ static void _dispc_set_scaling(enum omap_plane plane,
+ 		u16 orig_width, u16 orig_height,
+ 		u16 out_width, u16 out_height,
+-		bool ilace)
++		bool ilace, bool five_taps)
+ {
+ 	int fir_hinc;
+ 	int fir_vinc;
+-	int hscaleup, vscaleup, five_taps;
++	int hscaleup, vscaleup;
+ 	int fieldmode = 0;
+ 	int accu0 = 0;
+ 	int accu1 = 0;
+@@ -1040,7 +1040,6 @@ static void _dispc_set_scaling(enum omap_plane plane,
+ 
+ 	hscaleup = orig_width <= out_width;
+ 	vscaleup = orig_height <= out_height;
+-	five_taps = orig_height > out_height * 2;
+ 
+ 	_dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
+ 
+@@ -1283,6 +1282,73 @@ static void calc_rotation_offset(u8 rotation, bool mirror,
+ 	}
+ }
+ 
++static unsigned long calc_fclk_five_taps(u16 width, u16 height,
++		u16 out_width, u16 out_height, enum omap_color_mode color_mode)
++{
++	u32 fclk = 0;
++	/* FIXME venc pclk? */
++	u64 tmp, pclk = dispc_pclk_rate();
++
++	if (height > out_height) {
++		/* FIXME get real display PPL */
++		unsigned int ppl = 800;
++
++		tmp = pclk * height * out_width;
++		do_div(tmp, 2 * out_height * ppl);
++		fclk = tmp;
++
++		if (height > 2 * out_height) {
++			tmp = pclk * (height - 2 * out_height) * out_width;
++			do_div(tmp, 2 * out_height * (ppl - out_width));
++			fclk = max(fclk, (u32) tmp);
++		}
++	}
++
++	if (width > out_width) {
++		tmp = pclk * width;
++		do_div(tmp, out_width);
++		fclk = max(fclk, (u32) tmp);
++
++		if (color_mode == OMAP_DSS_COLOR_RGB24U)
++			fclk <<= 1;
++	}
++
++	return fclk;
++}
++
++static unsigned long calc_fclk(u16 width, u16 height,
++		u16 out_width, u16 out_height,
++		enum omap_color_mode color_mode, bool five_taps)
++{
++	unsigned int hf, vf;
++
++	if (five_taps)
++		return calc_fclk_five_taps(width, height,
++				out_width, out_height, color_mode);
++
++	/*
++	 * FIXME how to determine the 'A' factor
++	 * for the no downscaling case ?
++	 */
++
++	if (width > 3 * out_width)
++		hf = 4;
++	else if (width > 2 * out_width)
++		hf = 3;
++	else if (width > out_width)
++		hf = 2;
++	else
++		hf = 1;
++
++	if (height > out_height)
++		vf = 2;
++	else
++		vf = 1;
++
++	/* FIXME venc pclk? */
++	return dispc_pclk_rate() * vf * hf;
++}
++
+ static int _dispc_setup_plane(enum omap_plane plane,
+ 		enum omap_channel channel_out,
+ 		u32 paddr, u16 screen_width,
+@@ -1294,7 +1360,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 		u8 rotation, int mirror)
+ {
+ 	const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
+-	bool five_taps = height > out_height * 2;
++	bool five_taps = 0;
+ 	bool fieldmode = 0;
+ 	int cconv = 0;
+ 	unsigned offset0, offset1;
+@@ -1323,8 +1389,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 		}
+ 	} else {
+ 		/* video plane */
+-		if (width > (2048 >> five_taps))
+-			return -EINVAL;
++
++		unsigned long fclk;
+ 
+ 		if (out_width < width / maxdownscale ||
+ 		   out_width > width * 8)
+@@ -1356,6 +1422,30 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 		default:
+ 			return -EINVAL;
+ 		}
++
++		/* Must use 5-tap filter? */
++		five_taps = height > out_height * 2;
++
++		/* Try to use 5-tap filter whenever possible. */
++		if (cpu_is_omap34xx() && !five_taps &&
++		    height > out_height && width <= 1024) {
++			fclk = calc_fclk_five_taps(width, height,
++					out_width, out_height, color_mode);
++			if (fclk <= dispc_fclk_rate())
++				five_taps = true;
++		}
++
++		if (width > (2048 >> five_taps))
++			return -EINVAL;
++
++		fclk = calc_fclk(width, height, out_width, out_height,
++				color_mode, five_taps);
++
++		DSSDBG("required fclk rate = %lu Hz\n", fclk);
++		DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
++
++		if (fclk > dispc_fclk_rate())
++			return -EINVAL;
+ 	}
+ 
+ 	if (ilace && height >= out_height)
+@@ -1399,7 +1489,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 	if (plane != OMAP_DSS_GFX) {
+ 		_dispc_set_scaling(plane, width, height,
+ 				   out_width, out_height,
+-				   ilace);
++				   ilace, five_taps);
+ 		_dispc_set_vid_size(plane, out_width, out_height);
+ 		_dispc_set_vid_color_conv(plane, cconv);
+ 	}
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch
new file mode 100644
index 0000000000..c6971ea452
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch
@@ -0,0 +1,79 @@
+From 9f8f1613253656f155b3844c8255a560f86e0acd Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Mon, 6 Apr 2009 17:32:05 +0200
+Subject: [PATCH 20/69] DSS2: Check scaling limits against proper values
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Move the ilace and fieldmode related height adjustments to be performed
+before checking the scaling limits.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |   31 ++++++++++++++++---------------
+ 1 files changed, 16 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 61861d8..ae7be3d 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1366,10 +1366,25 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 	unsigned offset0, offset1;
+ 	s32 row_inc;
+ 	s32 pix_inc;
++	u16 frame_height = height;
+ 
+ 	if (paddr == 0)
+ 		return -EINVAL;
+ 
++	if (ilace && height >= out_height)
++		fieldmode = 1;
++
++	if (ilace) {
++		if (fieldmode)
++			height /= 2;
++		pos_y /= 2;
++		out_height /= 2;
++
++		DSSDBG("adjusting for ilace: height %d, pos_y %d, "
++				"out_height %d\n",
++				height, pos_y, out_height);
++	}
++
+ 	if (plane == OMAP_DSS_GFX) {
+ 		if (width != out_width || height != out_height)
+ 			return -EINVAL;
+@@ -1448,28 +1463,14 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 			return -EINVAL;
+ 	}
+ 
+-	if (ilace && height >= out_height)
+-		fieldmode = 1;
+-
+ 	calc_rotation_offset(rotation, mirror,
+-			screen_width, width, height, color_mode,
++			screen_width, width, frame_height, color_mode,
+ 			fieldmode,
+ 			&offset0, &offset1, &row_inc, &pix_inc);
+ 
+ 	DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
+ 			offset0, offset1, row_inc, pix_inc);
+ 
+-	if (ilace) {
+-		if (fieldmode)
+-			height /= 2;
+-		pos_y /= 2;
+-		out_height /= 2;
+-
+-		DSSDBG("adjusting for ilace: height %d, pos_y %d, "
+-				"out_height %d\n",
+-				height, pos_y, out_height);
+-	}
+-
+ 	_dispc_set_channel_out(plane, channel_out);
+ 	_dispc_set_color_mode(plane, color_mode);
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0021-DSS2-Add-venc-register-dump.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0021-DSS2-Add-venc-register-dump.patch
new file mode 100644
index 0000000000..44f126e7a4
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0021-DSS2-Add-venc-register-dump.patch
@@ -0,0 +1,96 @@
+From c5e71be877e71c7df329205307e830f158c403bf Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Mon, 6 Apr 2009 17:32:06 +0200
+Subject: [PATCH 21/69] DSS2: Add venc register dump
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Add a new file to debugfs to dump the VENC registers. The function
+prototype was already there but the implementation was missing.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/venc.c |   55 ++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 55 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
+index aceed9f..b655df4 100644
+--- a/drivers/video/omap2/dss/venc.c
++++ b/drivers/video/omap2/dss/venc.c
+@@ -30,6 +30,7 @@
+ #include <linux/completion.h>
+ #include <linux/delay.h>
+ #include <linux/string.h>
++#include <linux/seq_file.h>
+ 
+ #include <mach/display.h>
+ #include <mach/cpu.h>
+@@ -81,6 +82,7 @@
+ #define VENC_TVDETGP_INT_START_STOP_Y		0xB4
+ #define VENC_GEN_CTRL				0xB8
+ #define VENC_OUTPUT_CONTROL			0xC4
++#define VENC_OUTPUT_TEST			0xC8
+ #define VENC_DAC_B__DAC_C			0xC8
+ 
+ struct venc_config {
+@@ -598,3 +600,56 @@ void venc_init_display(struct omap_display *display)
+ 	display->set_timings = venc_set_timings;
+ 	display->check_timings = venc_check_timings;
+ }
++
++void venc_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
++
++	venc_enable_clocks(1);
++
++	DUMPREG(VENC_F_CONTROL);
++	DUMPREG(VENC_VIDOUT_CTRL);
++	DUMPREG(VENC_SYNC_CTRL);
++	DUMPREG(VENC_LLEN);
++	DUMPREG(VENC_FLENS);
++	DUMPREG(VENC_HFLTR_CTRL);
++	DUMPREG(VENC_CC_CARR_WSS_CARR);
++	DUMPREG(VENC_C_PHASE);
++	DUMPREG(VENC_GAIN_U);
++	DUMPREG(VENC_GAIN_V);
++	DUMPREG(VENC_GAIN_Y);
++	DUMPREG(VENC_BLACK_LEVEL);
++	DUMPREG(VENC_BLANK_LEVEL);
++	DUMPREG(VENC_X_COLOR);
++	DUMPREG(VENC_M_CONTROL);
++	DUMPREG(VENC_BSTAMP_WSS_DATA);
++	DUMPREG(VENC_S_CARR);
++	DUMPREG(VENC_LINE21);
++	DUMPREG(VENC_LN_SEL);
++	DUMPREG(VENC_L21__WC_CTL);
++	DUMPREG(VENC_HTRIGGER_VTRIGGER);
++	DUMPREG(VENC_SAVID__EAVID);
++	DUMPREG(VENC_FLEN__FAL);
++	DUMPREG(VENC_LAL__PHASE_RESET);
++	DUMPREG(VENC_HS_INT_START_STOP_X);
++	DUMPREG(VENC_HS_EXT_START_STOP_X);
++	DUMPREG(VENC_VS_INT_START_X);
++	DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
++	DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
++	DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
++	DUMPREG(VENC_VS_EXT_STOP_Y);
++	DUMPREG(VENC_AVID_START_STOP_X);
++	DUMPREG(VENC_AVID_START_STOP_Y);
++	DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
++	DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
++	DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
++	DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
++	DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
++	DUMPREG(VENC_GEN_CTRL);
++	DUMPREG(VENC_OUTPUT_CONTROL);
++	DUMPREG(VENC_OUTPUT_TEST);
++
++	venc_enable_clocks(0);
++
++#undef DUMPREG
++}
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0022-DSS2-FB-remove-unused-var-warning.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0022-DSS2-FB-remove-unused-var-warning.patch
new file mode 100644
index 0000000000..207a85f115
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0022-DSS2-FB-remove-unused-var-warning.patch
@@ -0,0 +1,27 @@
+From facfd479bb6efad76eec1e74048cb7a31da7287d Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Mon, 6 Apr 2009 22:26:04 +0200
+Subject: [PATCH 22/69] DSS2: FB: remove unused var warning
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ drivers/video/omap2/omapfb/omapfb-main.c |    2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index afe40a9..12ce0c3 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -1246,7 +1246,9 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
+ 		display->get_resolution(display, &w, &h);
+ 
+ 		if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++#ifdef DEBUG
+ 			int oldw = w, oldh = h;
++#endif
+ 
+ 			omap_vrfb_adjust_size(&w, &h, bytespp);
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch
new file mode 100644
index 0000000000..45045c4b4b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch
@@ -0,0 +1,214 @@
+From c02b843c2732bc7b15a3e35b5dd715d68225bbd1 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Wed, 8 Apr 2009 12:51:46 +0200
+Subject: [PATCH 23/69] DSS2: pass the default FB color format through board info
+
+Add a field to the FB memory region platform data, so that board
+init code can pass a default color format to the driver. Set this
+format as an initial setting for the given FB.
+
+This is needed for an upcoming patch that adds detection of the
+color format set by the bootloader.
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ drivers/video/omap2/omapfb/omapfb-main.c |  121 +++++++++++++++++++++++++++---
+ drivers/video/omap2/omapfb/omapfb.h      |    2 +
+ include/linux/omapfb.h                   |    5 +
+ 3 files changed, 117 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index 12ce0c3..67c67c2 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -370,6 +370,21 @@ static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var)
+ 	return -EINVAL;
+ }
+ 
++static int dss_mode_to_fb_mode(enum omap_color_mode dssmode,
++			       struct fb_var_screeninfo *var)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
++		struct omapfb_colormode *mode = &omapfb_colormodes[i];
++		if (dssmode == mode->dssmode) {
++			assign_colormode_to_var(var, mode);
++			return 0;
++		}
++	}
++	return -ENOENT;
++}
++
+ void set_fb_fix(struct fb_info *fbi)
+ {
+ 	struct fb_fix_screeninfo *fix = &fbi->fix;
+@@ -1267,6 +1282,60 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
+ 	return omapfb_alloc_fbmem(fbi, size, paddr);
+ }
+ 
++static enum omap_color_mode fb_format_to_dss_mode(enum omapfb_color_format format)
++{
++	enum omap_color_mode mode;
++
++	switch (format) {
++	case OMAPFB_COLOR_RGB565:
++		mode = OMAP_DSS_COLOR_RGB16;
++		break;
++	case OMAPFB_COLOR_YUV422:
++		mode = OMAP_DSS_COLOR_YUV2;
++		break;
++	case OMAPFB_COLOR_CLUT_8BPP:
++		mode = OMAP_DSS_COLOR_CLUT8;
++		break;
++	case OMAPFB_COLOR_CLUT_4BPP:
++		mode = OMAP_DSS_COLOR_CLUT4;
++		break;
++	case OMAPFB_COLOR_CLUT_2BPP:
++		mode = OMAP_DSS_COLOR_CLUT2;
++		break;
++	case OMAPFB_COLOR_CLUT_1BPP:
++		mode = OMAP_DSS_COLOR_CLUT1;
++		break;
++	case OMAPFB_COLOR_RGB444:
++		mode = OMAP_DSS_COLOR_RGB12U;
++		break;
++	case OMAPFB_COLOR_YUY422:
++		mode = OMAP_DSS_COLOR_UYVY;
++		break;
++	case OMAPFB_COLOR_ARGB16:
++		mode = OMAP_DSS_COLOR_ARGB16;
++		break;
++	case OMAPFB_COLOR_RGB24U:
++		mode = OMAP_DSS_COLOR_RGB24U;
++		break;
++	case OMAPFB_COLOR_RGB24P:
++		mode = OMAP_DSS_COLOR_RGB24P;
++		break;
++	case OMAPFB_COLOR_ARGB32:
++		mode = OMAP_DSS_COLOR_ARGB32;
++		break;
++	case OMAPFB_COLOR_RGBA32:
++		mode = OMAP_DSS_COLOR_RGBA32;
++		break;
++	case OMAPFB_COLOR_RGBX32:
++		mode = OMAP_DSS_COLOR_RGBX32;
++		break;
++	default:
++		mode = -EINVAL;
++	}
++
++	return mode;
++}
++
+ static int omapfb_parse_vram_param(const char *param, int max_entries,
+ 		unsigned long *sizes, unsigned long *paddrs)
+ {
+@@ -1483,9 +1552,36 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
+ 	}
+ 
+ 	var->nonstd = 0;
++	var->bits_per_pixel = 0;
+ 
+ 	var->rotate = ofbi->rotation;
+ 
++	/*
++	 * Check if there is a default color format set in the board file,
++	 * and use this format instead the default deducted from the
++	 * display bpp.
++	 */
++	if (fbdev->dev->platform_data) {
++		struct omapfb_platform_data *opd;
++		int id = ofbi->id;
++
++		opd = fbdev->dev->platform_data;
++		if (opd->mem_desc.region[id].format_used) {
++			enum omap_color_mode mode;
++			enum omapfb_color_format format;
++
++			format = opd->mem_desc.region[id].format;
++			mode = fb_format_to_dss_mode(format);
++			if (mode < 0) {
++				r = mode;
++				goto err;
++			}
++			r = dss_mode_to_fb_mode(mode, var);
++			if (r < 0)
++				goto err;
++		}
++	}
++
+ 	if (display) {
+ 		u16 w, h;
+ 		display->get_resolution(display, &w, &h);
+@@ -1502,16 +1598,18 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
+ 		var->xres_virtual = var->xres;
+ 		var->yres_virtual = var->yres;
+ 
+-		switch (display->get_recommended_bpp(display)) {
+-		case 16:
+-			var->bits_per_pixel = 16;
+-			break;
+-		case 24:
+-			var->bits_per_pixel = 32;
+-			break;
+-		default:
+-			dev_err(fbdev->dev, "illegal display bpp\n");
+-			return -EINVAL;
++		if (!var->bits_per_pixel) {
++			switch (display->get_recommended_bpp(display)) {
++				case 16:
++					var->bits_per_pixel = 16;
++					break;
++				case 24:
++					var->bits_per_pixel = 32;
++					break;
++				default:
++					dev_err(fbdev->dev, "illegal display bpp\n");
++					return -EINVAL;
++			}
+ 		}
+ 	} else {
+ 		/* if there's no display, let's just guess some basic values */
+@@ -1519,7 +1617,8 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
+ 		var->yres = 240;
+ 		var->xres_virtual = var->xres;
+ 		var->yres_virtual = var->yres;
+-		var->bits_per_pixel = 16;
++		if (!var->bits_per_pixel)
++			var->bits_per_pixel = 16;
+ 	}
+ 
+ 	r = check_fb_var(fbi, var);
+diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
+index 65e9e6e..2607def 100644
+--- a/drivers/video/omap2/omapfb/omapfb.h
++++ b/drivers/video/omap2/omapfb/omapfb.h
+@@ -27,6 +27,8 @@
+ #define DEBUG
+ #endif
+ 
++#include <mach/display.h>
++
+ #ifdef DEBUG
+ extern unsigned int omapfb_debug;
+ #define DBG(format, ...) \
+diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
+index 96190b2..7a34f22 100644
+--- a/include/linux/omapfb.h
++++ b/include/linux/omapfb.h
+@@ -298,6 +298,11 @@ struct omapfb_mem_region {
+ 	void __iomem	*vaddr;
+ 	unsigned long	size;
+ 	u8		type;		/* OMAPFB_PLANE_MEM_* */
++	enum omapfb_color_format format;/* OMAPFB_COLOR_* */
++	unsigned	format_used:1;	/* Must be set when format is set.
++					 * Needed b/c of the badly chosen 0
++					 * base for OMAPFB_COLOR_* values
++					 */
+ 	unsigned	alloc:1;	/* allocated by the driver */
+ 	unsigned	map:1;		/* kernel mapped by the driver */
+ };
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch
new file mode 100644
index 0000000000..1a68d9425a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch
@@ -0,0 +1,48 @@
+From 2710416c43572652cb5355a5eaf68038c95659e8 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 9 Apr 2009 12:10:46 +0300
+Subject: [PATCH 24/69] DSS2: Beagle: Use gpio_set_value
+
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   10 +++++++---
+ 1 files changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index b67e7a5..8c1961d 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -372,7 +372,7 @@ static struct platform_device keys_gpio = {
+ static int beagle_enable_dvi(struct omap_display *display)
+ {
+ 	if (display->hw_config.panel_reset_gpio != -1)
+-		gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
++		gpio_set_value(display->hw_config.panel_reset_gpio, 1);
+ 
+ 	return 0;
+ }
+@@ -380,7 +380,7 @@ static int beagle_enable_dvi(struct omap_display *display)
+ static void beagle_disable_dvi(struct omap_display *display)
+ {
+ 	if (display->hw_config.panel_reset_gpio != -1)
+-		gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
++		gpio_set_value(display->hw_config.panel_reset_gpio, 0);
+ }
+ 
+ static struct omap_dss_display_config beagle_display_data_dvi = {
+@@ -445,8 +445,12 @@ static void __init beagle_display_init(void)
+ 	int r;
+ 
+ 	r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
+-	if (r < 0)
++	if (r < 0) {
+ 		printk(KERN_ERR "Unable to get DVI reset GPIO\n");
++		return;
++	}
++
++	gpio_direction_output(beagle_display_data_dvi.panel_reset_gpio, 0);
+ }
+ 
+ static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch
new file mode 100644
index 0000000000..7f889d95d8
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch
@@ -0,0 +1,28 @@
+From 990f3160d33361c135ee72e91f202e05a8c378fc Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Mon, 13 Apr 2009 18:50:24 +0530
+Subject: [PATCH 25/69] DSS2: VRFB: Macro for calculating base address of the VRFB context was faulty
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ arch/arm/plat-omap/vrfb.c |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+index 7e0f8fc..d68065f 100644
+--- a/arch/arm/plat-omap/vrfb.c
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -16,8 +16,8 @@
+ 
+ #define SMS_ROT_VIRT_BASE(context, rot) \
+ 	(((context >= 4) ? 0xD0000000 : 0x70000000) \
+-	 | 0x4000000 * (context) \
+-	 | 0x1000000 * (rot))
++	 + (0x4000000 * (context)) \
++	 + (0x1000000 * (rot)))
+ 
+ #define OMAP_VRFB_SIZE			(2048 * 2048 * 4)
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch
new file mode 100644
index 0000000000..f5c249e045
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch
@@ -0,0 +1,78 @@
+From a1e8018c0806a1a0579eda4b93b7d6764a2ff643 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 15 Apr 2009 14:06:54 +0300
+Subject: [PATCH 26/69] DSS2: DSI: sidlemode to noidle while sending frame
+
+DISPC interrupts are not wake-up capable. Smart-idle in DISPC_SIDLEMODE
+causes DSS interface to go to idle at the end of the frame, and the
+FRAMEDONE interrupt is then delayed until something wakes up the DSS
+interface.
+
+So we set SIDLEMODE to no-idle when we start sending the frame, and
+set it back to smart-idle after receiving FRAMEDONE.
+---
+ drivers/video/omap2/dss/dispc.c |   10 ++++++++++
+ drivers/video/omap2/dss/dsi.c   |    4 ++++
+ drivers/video/omap2/dss/dss.h   |    3 +++
+ 3 files changed, 17 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index ae7be3d..16c68b8 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -2791,6 +2791,16 @@ static void _omap_dispc_initialize_irq(void)
+ 	omap_dispc_set_irqs();
+ }
+ 
++void dispc_enable_sidle(void)
++{
++	REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);	/* SIDLEMODE: smart idle */
++}
++
++void dispc_disable_sidle(void)
++{
++	REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);	/* SIDLEMODE: no idle */
++}
++
+ static void _omap_dispc_initial_config(void)
+ {
+ 	u32 l;
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+index 66ac6ea..50af925 100644
+--- a/drivers/video/omap2/dss/dsi.c
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -2665,6 +2665,8 @@ static void dsi_update_screen_dispc(struct omap_display *display,
+ 		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
+ 	dsi_write_reg(DSI_VC_TE(1), l);
+ 
++	dispc_disable_sidle();
++
+ 	dispc_enable_lcd_out(1);
+ 
+ 	if (dsi.use_te)
+@@ -2678,6 +2680,8 @@ static void framedone_callback(void *data, u32 mask)
+ 		return;
+ 	}
+ 
++	dispc_enable_sidle();
++
+ 	dsi.framedone_scheduled = 1;
+ 
+ 	/* We get FRAMEDONE when DISPC has finished sending pixels and turns
+diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
+index 0be42b6..d0917a8 100644
+--- a/drivers/video/omap2/dss/dss.h
++++ b/drivers/video/omap2/dss/dss.h
+@@ -244,6 +244,9 @@ void dispc_fake_vsync_irq(void);
+ void dispc_save_context(void);
+ void dispc_restore_context(void);
+ 
++void dispc_enable_sidle(void);
++void dispc_disable_sidle(void);
++
+ void dispc_lcd_enable_signal_polarity(bool act_high);
+ void dispc_lcd_enable_signal(bool enable);
+ void dispc_pck_free_enable(bool enable);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch
new file mode 100644
index 0000000000..5265ae6b0a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch
@@ -0,0 +1,324 @@
+From 77e848eeba461e9b55b09d39fd0d640caea13e19 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Thu, 9 Apr 2009 12:09:44 +0530
+Subject: [PATCH 27/69] DSS2: VRFB rotation and mirroring implemented.
+
+DSS2 modified to accept the rotation_type input
+to get the dma or VRFB rotation.
+
+DSS2: VRFB: Changed to pass DSS mode to vrfb_setup instead of Bpp.
+
+VRFB size registers requires the width to be halved when the
+mode is YUV or UYVY.  So modifed to pass the mode to omap_vrfb_setup
+function.
+
+Code added by Tim Yamin for few bug fixes
+
+Signed-off-by: Tim Yamin <plasm@roo.me.uk>
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ arch/arm/plat-omap/include/mach/display.h |    6 ++
+ arch/arm/plat-omap/include/mach/vrfb.h    |    3 +-
+ arch/arm/plat-omap/vrfb.c                 |   36 +++++++++-
+ drivers/video/omap2/dss/dispc.c           |  109 +++++++++++++++++++++++++++--
+ drivers/video/omap2/dss/dss.h             |    1 +
+ drivers/video/omap2/dss/manager.c         |    1 +
+ 6 files changed, 144 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+index 6b702c7..b0a6272 100644
+--- a/arch/arm/plat-omap/include/mach/display.h
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -341,6 +341,11 @@ enum omap_dss_overlay_managers {
+ 
+ struct omap_overlay_manager;
+ 
++enum omap_dss_rotation_type {
++	OMAP_DSS_ROT_DMA = 0,
++	OMAP_DSS_ROT_VRFB = 1,
++};
++
+ struct omap_overlay_info {
+ 	bool enabled;
+ 
+@@ -351,6 +356,7 @@ struct omap_overlay_info {
+ 	u16 height;
+ 	enum omap_color_mode color_mode;
+ 	u8 rotation;
++	enum omap_dss_rotation_type rotation_type;
+ 	bool mirror;
+ 
+ 	u16 pos_x;
+diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
+index 2047862..12c7fab 100644
+--- a/arch/arm/plat-omap/include/mach/vrfb.h
++++ b/arch/arm/plat-omap/include/mach/vrfb.h
+@@ -24,6 +24,7 @@
+ #ifndef __VRFB_H
+ #define __VRFB_H
+ 
++#include <mach/display.h>
+ #define OMAP_VRFB_LINE_LEN 2048
+ 
+ struct vrfb
+@@ -42,6 +43,6 @@ extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
+ 		u8 bytespp);
+ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ 		u16 width, u16 height,
+-		u8 bytespp);
++		enum omap_color_mode color_mode);
+ 
+ #endif /* __VRFB_H */
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+index d68065f..2f08f6d 100644
+--- a/arch/arm/plat-omap/vrfb.c
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -5,7 +5,6 @@
+ 
+ #include <mach/io.h>
+ #include <mach/vrfb.h>
+-
+ /*#define DEBUG*/
+ 
+ #ifdef DEBUG
+@@ -50,19 +49,48 @@ EXPORT_SYMBOL(omap_vrfb_adjust_size);
+ 
+ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ 		u16 width, u16 height,
+-		u8 bytespp)
++		enum omap_color_mode color_mode)
+ {
+ 	unsigned pixel_size_exp;
+ 	u16 vrfb_width;
+ 	u16 vrfb_height;
+ 	u8 ctx = vrfb->context;
++	u8 bytespp;
+ 
+ 	DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
+ 			width, height, bytespp);
+ 
+-	if (bytespp == 4)
++	switch (color_mode) {
++	case OMAP_DSS_COLOR_RGB16:
++	case OMAP_DSS_COLOR_ARGB16:
++		bytespp = 2;
++		break;
++
++	case OMAP_DSS_COLOR_RGB24P:
++		bytespp = 3;
++		break;
++
++	case OMAP_DSS_COLOR_RGB24U:
++	case OMAP_DSS_COLOR_ARGB32:
++	case OMAP_DSS_COLOR_RGBA32:
++	case OMAP_DSS_COLOR_RGBX32:
++	case OMAP_DSS_COLOR_YUV2:
++	case OMAP_DSS_COLOR_UYVY:
++		bytespp = 4;
++		break;
++
++	default:
++		BUG();
++		return;
++	}
++
++	if (color_mode == OMAP_DSS_COLOR_YUV2 ||
++			color_mode == OMAP_DSS_COLOR_UYVY)
++		width >>= 1;
++
++	if (bytespp == 4) {
+ 		pixel_size_exp = 2;
+-	else if (bytespp == 2)
++	} else if (bytespp == 2)
+ 		pixel_size_exp = 1;
+ 	else
+ 		BUG();
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 16c68b8..23a8155 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1106,7 +1106,7 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
+ 			case 0: vidrot = 0; break;
+ 			case 1: vidrot = 1; break;
+ 			case 2: vidrot = 2; break;
+-			case 3: vidrot = 1; break;
++			case 3: vidrot = 3; break;
+ 			}
+ 		}
+ 
+@@ -1134,7 +1134,92 @@ static s32 pixinc(int pixels, u8 ps)
+ 		BUG();
+ }
+ 
+-static void calc_rotation_offset(u8 rotation, bool mirror,
++static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
++		u16 screen_width,
++		u16 width, u16 height,
++		enum omap_color_mode color_mode, bool fieldmode,
++		unsigned *offset0, unsigned *offset1,
++		s32 *row_inc, s32 *pix_inc)
++{
++	u8 ps;
++
++	switch (color_mode) {
++	case OMAP_DSS_COLOR_RGB16:
++	case OMAP_DSS_COLOR_ARGB16:
++		ps = 2;
++		break;
++
++	case OMAP_DSS_COLOR_RGB24P:
++		ps = 3;
++		break;
++
++	case OMAP_DSS_COLOR_RGB24U:
++	case OMAP_DSS_COLOR_ARGB32:
++	case OMAP_DSS_COLOR_RGBA32:
++	case OMAP_DSS_COLOR_RGBX32:
++	case OMAP_DSS_COLOR_YUV2:
++	case OMAP_DSS_COLOR_UYVY:
++		ps = 4;
++		break;
++
++	default:
++		BUG();
++		return;
++	}
++
++	DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
++			width, height);
++	switch (rotation + mirror * 4) {
++	case 0:
++	case 2:
++		/*
++		 * If the pixel format is YUV or UYVY divide the width
++		 * of the image by 2 for 0 and 180 degree rotation.
++		 */
++		if (color_mode == OMAP_DSS_COLOR_YUV2 ||
++			color_mode == OMAP_DSS_COLOR_UYVY)
++			width = width >> 1;
++	case 1:
++	case 3:
++		*offset0 = 0;
++		if (fieldmode)
++			*offset1 = screen_width * ps;
++		else
++			*offset1 = 0;
++
++		*row_inc = pixinc(1 + (screen_width - width) +
++				(fieldmode ? screen_width : 0),
++				ps);
++		*pix_inc = pixinc(1, ps);
++		break;
++
++	case 4:
++	case 6:
++		/* If the pixel format is YUV or UYVY divide the width
++		 * of the image by 2  for 0 degree and 180 degree
++		 */
++		if (color_mode == OMAP_DSS_COLOR_YUV2 ||
++			color_mode == OMAP_DSS_COLOR_UYVY)
++			width = width >> 1;
++	case 5:
++	case 7:
++		*offset0 = 0;
++		if (fieldmode)
++			*offset1 = screen_width * ps;
++		else
++			*offset1 = 0;
++		*row_inc = pixinc(1 - (screen_width + width) -
++				(fieldmode ? screen_width : 0),
++				ps);
++		*pix_inc = pixinc(1, ps);
++		break;
++
++	default:
++		BUG();
++	}
++}
++
++static void calc_dma_rotation_offset(u8 rotation, bool mirror,
+ 		u16 screen_width,
+ 		u16 width, u16 height,
+ 		enum omap_color_mode color_mode, bool fieldmode,
+@@ -1357,6 +1442,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 		u16 out_width, u16 out_height,
+ 		enum omap_color_mode color_mode,
+ 		bool ilace,
++		enum omap_dss_rotation_type rotation_type,
+ 		u8 rotation, int mirror)
+ {
+ 	const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
+@@ -1463,10 +1549,16 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 			return -EINVAL;
+ 	}
+ 
+-	calc_rotation_offset(rotation, mirror,
+-			screen_width, width, frame_height, color_mode,
+-			fieldmode,
+-			&offset0, &offset1, &row_inc, &pix_inc);
++	if (rotation_type == OMAP_DSS_ROT_DMA)
++		calc_dma_rotation_offset(rotation, mirror,
++				screen_width, width, frame_height, color_mode,
++				fieldmode,
++				&offset0, &offset1, &row_inc, &pix_inc);
++	else
++		calc_vrfb_rotation_offset(rotation, mirror,
++				screen_width, width, frame_height, color_mode,
++				fieldmode,
++				&offset0, &offset1, &row_inc, &pix_inc);
+ 
+ 	DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
+ 			offset0, offset1, row_inc, pix_inc);
+@@ -2889,6 +2981,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
+ 		       u16 out_width, u16 out_height,
+ 		       enum omap_color_mode color_mode,
+ 		       bool ilace,
++		       enum omap_dss_rotation_type rotation_type,
+ 		       u8 rotation, bool mirror)
+ {
+ 	int r = 0;
+@@ -2909,6 +3002,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
+ 			   width, height,
+ 			   out_width, out_height,
+ 			   color_mode, ilace,
++			   rotation_type,
+ 			   rotation, mirror);
+ 
+ 	enable_clocks(0);
+@@ -3122,7 +3216,8 @@ void dispc_setup_partial_planes(struct omap_display *display,
+ 				pw, ph,
+ 				pow, poh,
+ 				pi->color_mode, 0,
+-				pi->rotation, // XXX rotation probably wrong
++				pi->rotation_type,
++				pi->rotation,
+ 				pi->mirror);
+ 
+ 		dispc_enable_plane(ovl->id, 1);
+diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
+index d0917a8..584dce6 100644
+--- a/drivers/video/omap2/dss/dss.h
++++ b/drivers/video/omap2/dss/dss.h
+@@ -272,6 +272,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
+ 		      u16 out_width, u16 out_height,
+ 		      enum omap_color_mode color_mode,
+ 		      bool ilace,
++		      enum omap_dss_rotation_type rotation_type,
+ 		      u8 rotation, bool mirror);
+ 
+ void dispc_go(enum omap_channel channel);
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+index b0fee80..8ca0bbb 100644
+--- a/drivers/video/omap2/dss/manager.c
++++ b/drivers/video/omap2/dss/manager.c
+@@ -395,6 +395,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
+ 				outh,
+ 				ovl->info.color_mode,
+ 				ilace,
++				ovl->info.rotation_type,
+ 				ovl->info.rotation,
+ 				ovl->info.mirror);
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch
new file mode 100644
index 0000000000..178349ed2a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch
@@ -0,0 +1,236 @@
+From c09f1a0642fd58a1b081594ea36dfd1bf71aec52 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Thu, 9 Apr 2009 12:13:07 +0530
+Subject: [PATCH 28/69] DSS2: OMAPFB: Added support for the YUV VRFB rotation and mirroring.
+
+DSS2 now requires roatation_type to be specified by driver.
+Added support for that.
+DSS2 OMAPFB: Modified to pass the dss mode to omap_vrfb_setup function.
+
+VRFB size register requires the width to be halved when the
+mode is YUV or UYVY.  So VRFB is modifed to pass the mode to omap_vrfb_setup
+function.
+
+Few changes done by Tim Yamin
+Signed-off-by: Tim Yamin <plasm@roo.me.uk>
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ arch/arm/plat-omap/vrfb.c                |    4 +-
+ drivers/video/omap2/omapfb/omapfb-main.c |   59 ++++++++++++++----------------
+ drivers/video/omap2/omapfb/omapfb.h      |    7 +---
+ 3 files changed, 30 insertions(+), 40 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+index 2f08f6d..2ae0d68 100644
+--- a/arch/arm/plat-omap/vrfb.c
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -88,9 +88,9 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ 			color_mode == OMAP_DSS_COLOR_UYVY)
+ 		width >>= 1;
+ 
+-	if (bytespp == 4) {
++	if (bytespp == 4)
+ 		pixel_size_exp = 2;
+-	} else if (bytespp == 2)
++	else if (bytespp == 2)
+ 		pixel_size_exp = 1;
+ 	else
+ 		BUG();
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index 67c67c2..57f5900 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -176,15 +176,9 @@ static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot)
+ 
+ static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
+ {
+-	if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
+-		unsigned offset;
+-		int rot;
+-
+-		rot = ofbi->rotation;
+-
+-		offset = omapfb_get_vrfb_offset(ofbi, rot);
+-
+-		return ofbi->region.vrfb.paddr[rot] + offset;
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++		return ofbi->region.vrfb.paddr[ofbi->rotation]
++			+ omapfb_get_vrfb_offset(ofbi, ofbi->rotation);
+ 	} else {
+ 		return ofbi->region.paddr;
+ 	}
+@@ -192,7 +186,7 @@ static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
+ 
+ u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
+ {
+-	if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+ 		return ofbi->region.vrfb.paddr[0];
+ 	else
+ 		return ofbi->region.paddr;
+@@ -200,7 +194,7 @@ u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
+ 
+ void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi)
+ {
+-	if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+ 		return ofbi->region.vrfb.vaddr[0];
+ 	else
+ 		return ofbi->region.vaddr;
+@@ -398,7 +392,7 @@ void set_fb_fix(struct fb_info *fbi)
+ 	fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
+ 
+ 	/* used by mmap in fbmem.c */
+-	if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+ 		fix->line_length =
+ 			(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
+ 	else
+@@ -434,11 +428,14 @@ void set_fb_fix(struct fb_info *fbi)
+ 	fix->xpanstep = 1;
+ 	fix->ypanstep = 1;
+ 
+-	if (rg->size) {
+-		if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
+-			omap_vrfb_setup(&rg->vrfb, rg->paddr,
+-					var->xres_virtual, var->yres_virtual,
+-					var->bits_per_pixel >> 3);
++	if (rg->size && ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++		enum omap_color_mode mode = 0;
++		mode = fb_mode_to_dss_mode(var);
++
++		omap_vrfb_setup(&rg->vrfb, rg->paddr,
++				var->xres_virtual,
++				var->yres_virtual,
++				mode);
+ 	}
+ }
+ 
+@@ -527,7 +524,7 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
+ 	if (var->yres > var->yres_virtual)
+ 		var->yres = var->yres_virtual;
+ 
+-	if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+ 		line_size = OMAP_VRFB_LINE_LEN * bytespp;
+ 	else
+ 		line_size = var->xres_virtual * bytespp;
+@@ -549,7 +546,7 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
+ 
+ 	if (line_size * var->yres_virtual > max_frame_size) {
+ 		DBG("can't fit FB into memory, reducing x\n");
+-		if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
++		if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+ 			return -EINVAL;
+ 
+ 		var->xres_virtual = max_frame_size / var->yres_virtual /
+@@ -672,7 +669,7 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
+ 	struct omap_overlay_info info;
+ 	int xres, yres;
+ 	int screen_width;
+-	int rot, mirror;
++	int mirror;
+ 
+ 	DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
+ 			posx, posy, outw, outh);
+@@ -688,7 +685,7 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
+ 	offset = ((var->yoffset * var->xres_virtual +
+ 				var->xoffset) * var->bits_per_pixel) >> 3;
+ 
+-	if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
+ 		data_start_p = omapfb_get_region_rot_paddr(ofbi);
+ 		data_start_v = NULL;
+ 	} else {
+@@ -711,13 +708,10 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
+ 
+ 	ovl->get_overlay_info(ovl, &info);
+ 
+-	if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
+-		rot = 0;
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+ 		mirror = 0;
+-	} else {
+-		rot = ofbi->rotation;
++	else
+ 		mirror = ofbi->mirror;
+-	}
+ 
+ 	info.paddr = data_start_p;
+ 	info.vaddr = data_start_v;
+@@ -725,7 +719,8 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
+ 	info.width = xres;
+ 	info.height = yres;
+ 	info.color_mode = mode;
+-	info.rotation = rot;
++	info.rotation_type = ofbi->rotation_type;
++	info.rotation = ofbi->rotation;
+ 	info.mirror = mirror;
+ 
+ 	info.pos_x = posx;
+@@ -1121,7 +1116,7 @@ static void omapfb_free_fbmem(struct fb_info *fbi)
+ 	if (rg->vaddr)
+ 		iounmap(rg->vaddr);
+ 
+-	if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
+ 		/* unmap the 0 angle rotation */
+ 		if (rg->vrfb.vaddr[0]) {
+ 			iounmap(rg->vrfb.vaddr[0]);
+@@ -1181,7 +1176,7 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
+ 		return -ENOMEM;
+ 	}
+ 
+-	if (ofbi->rotation_type != OMAPFB_ROT_VRFB) {
++	if (ofbi->rotation_type != OMAP_DSS_ROT_VRFB) {
+ 		vaddr = ioremap_wc(paddr, size);
+ 
+ 		if (!vaddr) {
+@@ -1260,7 +1255,7 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
+ 
+ 		display->get_resolution(display, &w, &h);
+ 
+-		if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
++		if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
+ #ifdef DEBUG
+ 			int oldw = w, oldh = h;
+ #endif
+@@ -1701,8 +1696,8 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
+ 		ofbi->id = i;
+ 
+ 		/* assign these early, so that fb alloc can use them */
+-		ofbi->rotation_type = def_vrfb ? OMAPFB_ROT_VRFB :
+-			OMAPFB_ROT_DMA;
++		ofbi->rotation_type = def_vrfb ? OMAP_DSS_ROT_VRFB :
++			OMAP_DSS_ROT_DMA;
+ 		ofbi->rotation = def_rotate;
+ 		ofbi->mirror = def_mirror;
+ 
+diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
+index 2607def..43f6922 100644
+--- a/drivers/video/omap2/omapfb/omapfb.h
++++ b/drivers/video/omap2/omapfb/omapfb.h
+@@ -53,11 +53,6 @@ struct omapfb2_mem_region {
+ 	bool		map;		/* kernel mapped by the driver */
+ };
+ 
+-enum omapfb_rotation_type {
+-	OMAPFB_ROT_DMA = 0,
+-	OMAPFB_ROT_VRFB = 1,
+-};
+-
+ /* appended to fb_info */
+ struct omapfb_info {
+ 	int id;
+@@ -66,7 +61,7 @@ struct omapfb_info {
+ 	int num_overlays;
+ 	struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB];
+ 	struct omapfb2_device *fbdev;
+-	enum omapfb_rotation_type rotation_type;
++	enum omap_dss_rotation_type rotation_type;
+ 	u8 rotation;
+ 	bool mirror;
+ };
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch
new file mode 100644
index 0000000000..e9f25dfef1
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch
@@ -0,0 +1,61 @@
+From a8a37babe4856170f4cba86c425a8f21975d9e9e Mon Sep 17 00:00:00 2001
+From: Tim Yamin <plasm@roo.me.uk>
+Date: Mon, 13 Apr 2009 13:57:42 -0700
+Subject: [PATCH 29/69] DSS2: OMAPFB: Set line_length correctly for YUV with VRFB.
+
+Signed-off-by: Tim Yamin <plasm@roo.me.uk>
+---
+ drivers/video/omap2/omapfb/omapfb-main.c |   30 +++++++++++++++++++++++++-----
+ 1 files changed, 25 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index 57f5900..cd63740 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -392,10 +392,19 @@ void set_fb_fix(struct fb_info *fbi)
+ 	fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
+ 
+ 	/* used by mmap in fbmem.c */
+-	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+-		fix->line_length =
+-			(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
+-	else
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++		switch (var->nonstd) {
++		case OMAPFB_COLOR_YUV422:
++		case OMAPFB_COLOR_YUY422:
++			fix->line_length =
++				(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 2;
++			break;
++		default:
++			fix->line_length =
++				(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
++			break;
++		}
++	} else
+ 		fix->line_length =
+ 			(var->xres_virtual * var->bits_per_pixel) >> 3;
+ 	fix->smem_start = omapfb_get_region_paddr(ofbi);
+@@ -704,7 +713,18 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
+ 		goto err;
+ 	}
+ 
+-	screen_width = fix->line_length / (var->bits_per_pixel >> 3);
++	switch (var->nonstd) {
++	case OMAPFB_COLOR_YUV422:
++	case OMAPFB_COLOR_YUY422:
++		if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++			screen_width = fix->line_length
++				/ (var->bits_per_pixel >> 2);
++			break;
++		}
++	default:
++		screen_width = fix->line_length / (var->bits_per_pixel >> 3);
++		break;
++	}
+ 
+ 	ovl->get_overlay_info(ovl, &info);
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch
new file mode 100644
index 0000000000..63b3594ef5
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch
@@ -0,0 +1,29 @@
+From bda19b9359d9dc60f8b0beb5685e173e236ee30f Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Wed, 15 Apr 2009 17:05:18 +0530
+Subject: [PATCH 30/69] DSS2: dispc_get_trans_key was returning wrong key type
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ drivers/video/omap2/dss/dispc.c |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 23a8155..076d3d4 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1826,9 +1826,9 @@ void dispc_get_trans_key(enum omap_channel ch,
+ 	enable_clocks(1);
+ 	if (type) {
+ 		if (ch == OMAP_DSS_CHANNEL_LCD)
+-			*type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
++			*type = REG_GET(DISPC_CONFIG, 11, 11);
+ 		else if (ch == OMAP_DSS_CHANNEL_DIGIT)
+-			*type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
++			*type = REG_GET(DISPC_CONFIG, 13, 13);
+ 		else
+ 			BUG();
+ 	}
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch
new file mode 100644
index 0000000000..684857c15f
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch
@@ -0,0 +1,33 @@
+From 30c40f5e6b1794430f678bf23d3319354321cab7 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Tue, 14 Apr 2009 14:50:11 +0200
+Subject: [PATCH 31/69] DSS2: do bootmem reserve for exclusive access
+
+BOOTMEM_DEFAULT would allow multiple reservations for the same location,
+we need to reserve the region for our exclusive use. Also check if the
+reserve succeeded.
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ arch/arm/plat-omap/vram.c |    5 ++++-
+ 1 files changed, 4 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
+index f24a110..520f260 100644
+--- a/arch/arm/plat-omap/vram.c
++++ b/arch/arm/plat-omap/vram.c
+@@ -524,7 +524,10 @@ void __init omapfb_reserve_sdram(void)
+ 			return;
+ 		}
+ 
+-		reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
++		if (reserve_bootmem(paddr, size, BOOTMEM_EXCLUSIVE) < 0) {
++			pr_err("FB: failed to reserve VRAM\n");
++			return;
++		}
+ 	} else {
+ 		if (size > sdram_size) {
+ 			printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch
new file mode 100644
index 0000000000..df3a7a9dd9
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch
@@ -0,0 +1,35 @@
+From ed7a9223f6785be03951c55f3b0695b0d5635c80 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Thu, 9 Apr 2009 15:04:44 +0200
+Subject: [PATCH 32/69] DSS2: Fix DISPC_VID_FIR value for omap34xx
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+The msbs of the DISPC_VID_FIR fields were incorrectly masked out on
+omap34xx and thus 4:1 downscale did not work correctly.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |    5 ++++-
+ 1 files changed, 4 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 076d3d4..b8a3329 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -994,7 +994,10 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
+ 
+ 	BUG_ON(plane == OMAP_DSS_GFX);
+ 
+-	val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
++	if (cpu_is_omap24xx())
++		val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
++	else
++		val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
+ 	dispc_write_reg(fir_reg[plane-1], val);
+ }
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0033-DSS2-Prefer-3-tap-filter.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0033-DSS2-Prefer-3-tap-filter.patch
new file mode 100644
index 0000000000..6457a5b94a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0033-DSS2-Prefer-3-tap-filter.patch
@@ -0,0 +1,82 @@
+From 5390230ed12585a79683733209db34e9130b8e3b Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Thu, 9 Apr 2009 15:04:43 +0200
+Subject: [PATCH 33/69] DSS2: Prefer 3-tap filter
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+The 5-tap filter seems rather unstable. With some scaling settings it
+works and with some it doesn't even though the functional clock remains
+within the TRM limits. So prefer the 3-tap filter unless the functional
+clock required for it is too high.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |   27 ++++++++++++---------------
+ 1 files changed, 12 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index b8a3329..b631dd8 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1405,15 +1405,10 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
+ }
+ 
+ static unsigned long calc_fclk(u16 width, u16 height,
+-		u16 out_width, u16 out_height,
+-		enum omap_color_mode color_mode, bool five_taps)
++		u16 out_width, u16 out_height)
+ {
+ 	unsigned int hf, vf;
+ 
+-	if (five_taps)
+-		return calc_fclk_five_taps(width, height,
+-				out_width, out_height, color_mode);
+-
+ 	/*
+ 	 * FIXME how to determine the 'A' factor
+ 	 * for the no downscaling case ?
+@@ -1494,7 +1489,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 	} else {
+ 		/* video plane */
+ 
+-		unsigned long fclk;
++		unsigned long fclk = 0;
+ 
+ 		if (out_width < width / maxdownscale ||
+ 		   out_width > width * 8)
+@@ -1530,20 +1525,22 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 		/* Must use 5-tap filter? */
+ 		five_taps = height > out_height * 2;
+ 
+-		/* Try to use 5-tap filter whenever possible. */
+-		if (cpu_is_omap34xx() && !five_taps &&
+-		    height > out_height && width <= 1024) {
+-			fclk = calc_fclk_five_taps(width, height,
+-					out_width, out_height, color_mode);
+-			if (fclk <= dispc_fclk_rate())
++		if (!five_taps) {
++			fclk = calc_fclk(width, height,
++					out_width, out_height);
++
++			/* Try 5-tap filter if 3-tap fclk is too high */
++			if (cpu_is_omap34xx() && height > out_height &&
++					fclk > dispc_fclk_rate())
+ 				five_taps = true;
+ 		}
+ 
+ 		if (width > (2048 >> five_taps))
+ 			return -EINVAL;
+ 
+-		fclk = calc_fclk(width, height, out_width, out_height,
+-				color_mode, five_taps);
++		if (five_taps)
++			fclk = calc_fclk_five_taps(width, height,
++					out_width, out_height, color_mode);
+ 
+ 		DSSDBG("required fclk rate = %lu Hz\n", fclk);
+ 		DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch
new file mode 100644
index 0000000000..dd01886406
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch
@@ -0,0 +1,135 @@
+From 946eb774e95cdc2f2fa5cdc24aa69229f82814b8 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 16 Apr 2009 17:56:00 +0300
+Subject: [PATCH 34/69] DSS2: VRAM: improve omap_vram_add_region()
+
+Combine postponed and non-posponed versions of omap_vram_add_region.
+Make the func non-static, so it can be called from board files.
+---
+ arch/arm/plat-omap/include/mach/vram.h |    1 +
+ arch/arm/plat-omap/vram.c              |   54 +++++++++++++------------------
+ 2 files changed, 24 insertions(+), 31 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
+index f176562..8639e08 100644
+--- a/arch/arm/plat-omap/include/mach/vram.h
++++ b/arch/arm/plat-omap/include/mach/vram.h
+@@ -24,6 +24,7 @@
+ 
+ #include <asm/types.h>
+ 
++extern int omap_vram_add_region(unsigned long paddr, size_t size);
+ extern int omap_vram_free(unsigned long paddr, size_t size);
+ extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
+ extern int omap_vram_reserve(unsigned long paddr, size_t size);
+diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
+index 520f260..8e9fe77 100644
+--- a/arch/arm/plat-omap/vram.c
++++ b/arch/arm/plat-omap/vram.c
+@@ -60,6 +60,7 @@
+  * time when we cannot yet allocate the region list */
+ #define MAX_POSTPONED_REGIONS 10
+ 
++static bool vram_initialized;
+ static int postponed_cnt __initdata;
+ static struct {
+ 	unsigned long paddr;
+@@ -145,39 +146,32 @@ static void omap_vram_free_allocation(struct vram_alloc *va)
+ 	kfree(va);
+ }
+ 
+-static __init int omap_vram_add_region_postponed(unsigned long paddr,
+-		size_t size)
+-{
+-	if (postponed_cnt == MAX_POSTPONED_REGIONS)
+-		return -ENOMEM;
+-
+-	postponed_regions[postponed_cnt].paddr = paddr;
+-	postponed_regions[postponed_cnt].size = size;
+-
+-	++postponed_cnt;
+-
+-	return 0;
+-}
+-
+-/* add/remove_region can be exported if there's need to add/remove regions
+- * runtime */
+-static int omap_vram_add_region(unsigned long paddr, size_t size)
++int omap_vram_add_region(unsigned long paddr, size_t size)
+ {
+ 	struct vram_region *rm;
+ 	unsigned pages;
+ 
+-	DBG("adding region paddr %08lx size %d\n",
+-			paddr, size);
++	if (vram_initialized) {
++		DBG("adding region paddr %08lx size %d\n",
++				paddr, size);
+ 
+-	size &= PAGE_MASK;
+-	pages = size >> PAGE_SHIFT;
++		size &= PAGE_MASK;
++		pages = size >> PAGE_SHIFT;
+ 
+-	rm = omap_vram_create_region(paddr, pages);
+-	if (rm == NULL)
+-		return -ENOMEM;
++		rm = omap_vram_create_region(paddr, pages);
++		if (rm == NULL)
++			return -ENOMEM;
++
++		list_add(&rm->list, &region_list);
++	} else {
++		if (postponed_cnt == MAX_POSTPONED_REGIONS)
++			return -ENOMEM;
+ 
+-	list_add(&rm->list, &region_list);
++		postponed_regions[postponed_cnt].paddr = paddr;
++		postponed_regions[postponed_cnt].size = size;
+ 
++		++postponed_cnt;
++	}
+ 	return 0;
+ }
+ 
+@@ -438,6 +432,8 @@ static __init int omap_vram_init(void)
+ {
+ 	int i, r;
+ 
++	vram_initialized = 1;
++
+ 	for (i = 0; i < postponed_cnt; i++)
+ 		omap_vram_add_region(postponed_regions[i].paddr,
+ 				postponed_regions[i].size);
+@@ -472,10 +468,6 @@ static void __init omapfb_early_vram(char **p)
+ 	omapfb_def_sdram_vram_size = memparse(*p, p);
+ 	if (**p == ',')
+ 		omapfb_def_sdram_vram_start = simple_strtoul((*p) + 1, p, 16);
+-
+-	printk("omapfb_early_vram, %d, 0x%x\n",
+-			omapfb_def_sdram_vram_size,
+-			omapfb_def_sdram_vram_start);
+ }
+ __early_param("vram=", omapfb_early_vram);
+ 
+@@ -538,7 +530,7 @@ void __init omapfb_reserve_sdram(void)
+ 		BUG_ON(paddr & ~PAGE_MASK);
+ 	}
+ 
+-	omap_vram_add_region_postponed(paddr, size);
++	omap_vram_add_region(paddr, size);
+ 
+ 	pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
+ }
+@@ -594,7 +586,7 @@ unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
+ 		reserved = pend_avail - paddr;
+ 	size_avail = pend_avail - reserved - pstart_avail;
+ 
+-	omap_vram_add_region_postponed(paddr, size);
++	omap_vram_add_region(paddr, size);
+ 
+ 	if (reserved)
+ 		pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch
new file mode 100644
index 0000000000..6b29d50dc0
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch
@@ -0,0 +1,66 @@
+From f825cafd5ee5c600218740507f85594c825b0c00 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Thu, 16 Apr 2009 18:47:49 +0530
+Subject: [PATCH 35/69] DSS2: Added the function pointer for getting default color.
+
+V4L2 Framework has a CID for getting/setting default color.
+So added the function pointer for doing same.
+SYSFS based getting the default color will remain same
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ arch/arm/plat-omap/include/mach/display.h |    1 +
+ drivers/video/omap2/dss/manager.c         |   11 +++++++----
+ 2 files changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+index b0a6272..073cdda 100644
+--- a/arch/arm/plat-omap/include/mach/display.h
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -414,6 +414,7 @@ struct omap_overlay_manager {
+ 	int (*apply)(struct omap_overlay_manager *mgr);
+ 
+ 	void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
++	u32 (*get_default_color)(struct omap_overlay_manager *mgr);
+ 	void (*set_trans_key)(struct omap_overlay_manager *mgr,
+ 		enum omap_dss_color_key_type type,
+ 		u32 trans_key);
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+index 8ca0bbb..12cf7b0 100644
+--- a/drivers/video/omap2/dss/manager.c
++++ b/drivers/video/omap2/dss/manager.c
+@@ -98,10 +98,8 @@ static ssize_t manager_display_store(struct omap_overlay_manager *mgr, const cha
+ static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
+ 					  char *buf)
+ {
+-	u32 default_color;
+-
+-	default_color = dispc_get_default_color(mgr->id);
+-	return snprintf(buf, PAGE_SIZE, "%d", default_color);
++	return snprintf(buf, PAGE_SIZE, "%d",
++			mgr->get_default_color(mgr));
+ }
+ 
+ static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
+@@ -470,6 +468,10 @@ static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
+ {
+ 	dispc_enable_trans_key(mgr->id, enable);
+ }
++static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
++{
++	return dispc_get_default_color(mgr->id);
++}
+ 
+ static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
+ {
+@@ -512,6 +514,7 @@ int dss_init_overlay_managers(struct platform_device *pdev)
+ 		mgr->set_default_color = &omap_dss_mgr_set_def_color,
+ 		mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
+ 		mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
++		mgr->get_default_color = &omap_dss_mgr_get_default_color;
+ 		mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
+ 
+ 		dss_overlay_setup_dispc_manager(mgr);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch
new file mode 100644
index 0000000000..ace5079234
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch
@@ -0,0 +1,118 @@
+From 6c56dc10226c84f41917ac2117b0e654fa080d40 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Thu, 16 Apr 2009 19:00:11 +0530
+Subject: [PATCH 36/69] DSS2: Added support for setting and querying alpha blending.
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ arch/arm/plat-omap/include/mach/display.h |    3 +++
+ drivers/video/omap2/dss/dispc.c           |   26 ++++++++++++++++++++++++++
+ drivers/video/omap2/dss/dss.h             |    2 ++
+ drivers/video/omap2/dss/manager.c         |   14 ++++++++++++++
+ 4 files changed, 45 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+index 073cdda..e1f615a 100644
+--- a/arch/arm/plat-omap/include/mach/display.h
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -415,11 +415,14 @@ struct omap_overlay_manager {
+ 
+ 	void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
+ 	u32 (*get_default_color)(struct omap_overlay_manager *mgr);
++	bool (*get_alpha_blending_status)(struct omap_overlay_manager *mgr);
+ 	void (*set_trans_key)(struct omap_overlay_manager *mgr,
+ 		enum omap_dss_color_key_type type,
+ 		u32 trans_key);
+ 	void (*enable_trans_key)(struct omap_overlay_manager *mgr,
+ 		bool enable);
++	void (*enable_alpha_blending)(struct omap_overlay_manager *mgr,
++			bool enable);
+ };
+ 
+ enum omap_display_caps {
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index b631dd8..7e551c2 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1847,6 +1847,32 @@ void dispc_enable_trans_key(enum omap_channel ch, bool enable)
+ 		REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
+ 	enable_clocks(0);
+ }
++void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
++{
++	enable_clocks(1);
++	if (ch == OMAP_DSS_CHANNEL_LCD)
++		REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
++	else /* OMAP_DSS_CHANNEL_DIGIT */
++		REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
++	enable_clocks(0);
++}
++bool dispc_alpha_blending_enabled(enum omap_channel ch)
++{
++	bool enabled;
++
++	enable_clocks(1);
++	if (ch == OMAP_DSS_CHANNEL_LCD)
++		enabled = REG_GET(DISPC_CONFIG, 18, 18);
++	else if (ch == OMAP_DSS_CHANNEL_DIGIT)
++		enabled = REG_GET(DISPC_CONFIG, 18, 18);
++	else
++		BUG();
++	enable_clocks(0);
++
++	return enabled;
++
++}
++
+ 
+ bool dispc_trans_key_enabled(enum omap_channel ch)
+ {
+diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
+index 584dce6..1d01ff6 100644
+--- a/drivers/video/omap2/dss/dss.h
++++ b/drivers/video/omap2/dss/dss.h
+@@ -294,7 +294,9 @@ void dispc_get_trans_key(enum omap_channel ch,
+ 		enum omap_dss_color_key_type *type,
+ 		u32 *trans_key);
+ void dispc_enable_trans_key(enum omap_channel ch, bool enable);
++void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
+ bool dispc_trans_key_enabled(enum omap_channel ch);
++bool dispc_alpha_blending_enabled(enum omap_channel ch);
+ 
+ void dispc_set_lcd_timings(struct omap_video_timings *timings);
+ unsigned long dispc_fclk_rate(void);
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+index 12cf7b0..90acd28 100644
+--- a/drivers/video/omap2/dss/manager.c
++++ b/drivers/video/omap2/dss/manager.c
+@@ -468,6 +468,16 @@ static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
+ {
+ 	dispc_enable_trans_key(mgr->id, enable);
+ }
++static void omap_dss_mgr_enable_alpha_blending(struct omap_overlay_manager *mgr,
++		bool enable)
++{
++	dispc_enable_alpha_blending(mgr->id, enable);
++}
++static bool omap_dss_mgr_get_alpha_blending_status(
++		struct omap_overlay_manager *mgr)
++{
++	return dispc_alpha_blending_enabled(mgr->id);
++}
+ static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
+ {
+ 	return dispc_get_default_color(mgr->id);
+@@ -514,6 +524,10 @@ int dss_init_overlay_managers(struct platform_device *pdev)
+ 		mgr->set_default_color = &omap_dss_mgr_set_def_color,
+ 		mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
+ 		mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
++		mgr->enable_alpha_blending =
++			&omap_dss_mgr_enable_alpha_blending;
++		mgr->get_alpha_blending_status =
++			omap_dss_mgr_get_alpha_blending_status;
+ 		mgr->get_default_color = &omap_dss_mgr_get_default_color;
+ 		mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0037-DSS2-Added-support-for-querying-color-keying.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0037-DSS2-Added-support-for-querying-color-keying.patch
new file mode 100644
index 0000000000..e7f43ad83d
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0037-DSS2-Added-support-for-querying-color-keying.patch
@@ -0,0 +1,150 @@
+From 2c9edd6af31a812a9487dd8bc12322e105a29f44 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Fri, 17 Apr 2009 09:42:36 +0530
+Subject: [PATCH 37/69] DSS2: Added support for querying color keying.
+
+V4L2 Framework has a ioctl for getting/setting color keying.
+So added the function manager pointers for doing same.
+
+Modifed the color keying sysfs entries to use manager
+function pointer. Earlier they were calling direcly
+dispc function to set/enable color keying.
+
+Some of color-keying function pointers in the overlay_manager
+structure re-named to be more specific.
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ arch/arm/plat-omap/include/mach/display.h |    6 ++++-
+ drivers/video/omap2/dss/manager.c         |   36 +++++++++++++++++++++--------
+ 2 files changed, 31 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+index e1f615a..d0b4c83 100644
+--- a/arch/arm/plat-omap/include/mach/display.h
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -416,7 +416,11 @@ struct omap_overlay_manager {
+ 	void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
+ 	u32 (*get_default_color)(struct omap_overlay_manager *mgr);
+ 	bool (*get_alpha_blending_status)(struct omap_overlay_manager *mgr);
+-	void (*set_trans_key)(struct omap_overlay_manager *mgr,
++	bool (*get_trans_key_status)(struct omap_overlay_manager *mgr);
++	void (*get_trans_key_type_and_value)(struct omap_overlay_manager *mgr,
++		enum omap_dss_color_key_type *type,
++		u32 *trans_key);
++	void (*set_trans_key_type_and_value)(struct omap_overlay_manager *mgr,
+ 		enum omap_dss_color_key_type type,
+ 		u32 trans_key);
+ 	void (*enable_trans_key)(struct omap_overlay_manager *mgr,
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+index 90acd28..e0501c4 100644
+--- a/drivers/video/omap2/dss/manager.c
++++ b/drivers/video/omap2/dss/manager.c
+@@ -124,7 +124,7 @@ static ssize_t manager_color_key_type_show(struct omap_overlay_manager *mgr,
+ {
+ 	enum omap_dss_color_key_type key_type;
+ 
+-	dispc_get_trans_key(mgr->id, &key_type, NULL);
++	mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
+ 	BUG_ON(key_type >= ARRAY_SIZE(color_key_type_str));
+ 
+ 	return snprintf(buf, PAGE_SIZE, "%s\n", color_key_type_str[key_type]);
+@@ -143,8 +143,8 @@ static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
+ 	}
+ 	if (key_type == ARRAY_SIZE(color_key_type_str))
+ 		return -EINVAL;
+-	dispc_get_trans_key(mgr->id, NULL, &key_value);
+-	dispc_set_trans_key(mgr->id, key_type, key_value);
++	mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
++	mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
+ 
+ 	return size;
+ }
+@@ -154,7 +154,7 @@ static ssize_t manager_color_key_value_show(struct omap_overlay_manager *mgr,
+ {
+ 	u32 key_value;
+ 
+-	dispc_get_trans_key(mgr->id, NULL, &key_value);
++	 mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
+ 
+ 	return snprintf(buf, PAGE_SIZE, "%d\n", key_value);
+ }
+@@ -167,8 +167,8 @@ static ssize_t manager_color_key_value_store(struct omap_overlay_manager *mgr,
+ 
+ 	if (sscanf(buf, "%d", &key_value) != 1)
+ 		return -EINVAL;
+-	dispc_get_trans_key(mgr->id, &key_type, NULL);
+-	dispc_set_trans_key(mgr->id, key_type, key_value);
++	mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
++	mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
+ 
+ 	return size;
+ }
+@@ -177,7 +177,7 @@ static ssize_t manager_color_key_enabled_show(struct omap_overlay_manager *mgr,
+ 					      char *buf)
+ {
+ 	return snprintf(buf, PAGE_SIZE, "%d\n",
+-			dispc_trans_key_enabled(mgr->id));
++	mgr->get_trans_key_status(mgr));
+ }
+ 
+ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
+@@ -188,7 +188,7 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
+ 	if (sscanf(buf, "%d", &enable) != 1)
+ 		return -EINVAL;
+ 
+-	dispc_enable_trans_key(mgr->id, enable);
++	mgr->enable_trans_key(mgr, enable);
+ 
+ 	return size;
+ }
+@@ -456,12 +456,20 @@ static void omap_dss_mgr_set_def_color(struct omap_overlay_manager *mgr,
+ 	dispc_set_default_color(mgr->id, color);
+ }
+ 
+-static void omap_dss_mgr_set_trans_key(struct omap_overlay_manager *mgr,
++static void omap_dss_mgr_set_trans_key_type_and_value(
++		struct omap_overlay_manager *mgr,
+ 		enum omap_dss_color_key_type type,
+ 		u32 trans_key)
+ {
+ 	dispc_set_trans_key(mgr->id, type, trans_key);
+ }
++static void omap_dss_mgr_get_trans_key_type_and_value(
++		struct omap_overlay_manager *mgr,
++		enum omap_dss_color_key_type *type,
++		u32 *trans_key)
++{
++	dispc_get_trans_key(mgr->id, type, trans_key);
++}
+ 
+ static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
+ 		bool enable)
+@@ -482,6 +490,10 @@ static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
+ {
+ 	return dispc_get_default_color(mgr->id);
+ }
++static bool omap_dss_mgr_get_trans_key_status(struct omap_overlay_manager *mgr)
++{
++	return dispc_trans_key_enabled(mgr->id);
++}
+ 
+ static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
+ {
+@@ -522,8 +534,12 @@ int dss_init_overlay_managers(struct platform_device *pdev)
+ 		mgr->unset_display = &omap_dss_unset_display,
+ 		mgr->apply = &omap_dss_mgr_apply,
+ 		mgr->set_default_color = &omap_dss_mgr_set_def_color,
+-		mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
++		mgr->set_trans_key_type_and_value =
++			&omap_dss_mgr_set_trans_key_type_and_value,
++		mgr->get_trans_key_type_and_value =
++			&omap_dss_mgr_get_trans_key_type_and_value,
+ 		mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
++		mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status,
+ 		mgr->enable_alpha_blending =
+ 			&omap_dss_mgr_enable_alpha_blending;
+ 		mgr->get_alpha_blending_status =
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch
new file mode 100644
index 0000000000..096c976a70
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch
@@ -0,0 +1,56 @@
+From 9e8877f0e5b17d3ddd101d6a63aa86fdb14d35d5 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Fri, 17 Apr 2009 09:51:25 +0530
+Subject: [PATCH 38/69] DSS2:OMAPFB: Some color keying pointerd renamed in DSS2. Replicated in FB
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ drivers/video/omap2/omapfb/omapfb-ioctl.c |   11 +++++++----
+ 1 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
+index 7f18d2a..79d8916 100644
+--- a/drivers/video/omap2/omapfb/omapfb-ioctl.c
++++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
+@@ -288,7 +288,8 @@ static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
+ {
+ 	enum omap_dss_color_key_type kt;
+ 
+-	if(!mgr->set_default_color || !mgr->set_trans_key ||
++	if (!mgr->set_default_color ||
++			!mgr->set_trans_key_type_and_value ||
+ 			!mgr->enable_trans_key)
+ 		return 0;
+ 
+@@ -310,7 +311,7 @@ static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
+ 	}
+ 
+ 	mgr->set_default_color(mgr, ck->background);
+-	mgr->set_trans_key(mgr, kt, ck->trans_key);
++	mgr->set_trans_key_type_and_value(mgr, kt, ck->trans_key);
+ 	mgr->enable_trans_key(mgr, 1);
+ 
+ 	omapfb_color_keys[mgr->id] = *ck;
+@@ -341,7 +342,8 @@ static int omapfb_set_color_key(struct fb_info *fbi,
+ 		goto err;
+ 	}
+ 
+-	if(!mgr->set_default_color || !mgr->set_trans_key ||
++	if (!mgr->set_default_color ||
++			!mgr->set_trans_key_type_and_value ||
+ 			!mgr->enable_trans_key) {
+ 		r = -ENODEV;
+ 		goto err;
+@@ -377,7 +379,8 @@ static int omapfb_get_color_key(struct fb_info *fbi,
+ 		goto err;
+ 	}
+ 
+-	if(!mgr->set_default_color || !mgr->set_trans_key ||
++	if (!mgr->set_default_color ||
++			!mgr->set_trans_key_type_and_value ||
+ 			!mgr->enable_trans_key) {
+ 		r = -ENODEV;
+ 		goto err;
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch
new file mode 100644
index 0000000000..d731b78008
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch
@@ -0,0 +1,59 @@
+From 6f1f0c7b19ecb468824b79f9d181ef0da41b7d7d Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Fri, 17 Apr 2009 13:58:21 +0530
+Subject: [PATCH 39/69] DSS2: Add sysfs entry to for the alpha blending support.
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ drivers/video/omap2/dss/manager.c |   21 +++++++++++++++++++++
+ 1 files changed, 21 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+index e0501c4..7965a84 100644
+--- a/drivers/video/omap2/dss/manager.c
++++ b/drivers/video/omap2/dss/manager.c
+@@ -192,6 +192,22 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
+ 
+ 	return size;
+ }
++static ssize_t manager_alpha_blending_enabled_show(
++		struct omap_overlay_manager *mgr, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d\n",
++			mgr->get_alpha_blending_status(mgr));
++}
++static ssize_t manager_alpha_blending_enabled_store(
++		struct omap_overlay_manager *mgr,
++		const char *buf, size_t size)
++{
++	int enable;
++	if (sscanf(buf, "%d", &enable) != 1)
++		return -EINVAL;
++	mgr->enable_alpha_blending(mgr, enable);
++	return size;
++}
+ 
+ 
+ struct manager_attribute {
+@@ -215,6 +231,10 @@ static MANAGER_ATTR(color_key_value, S_IRUGO|S_IWUSR,
+ 		manager_color_key_value_show, manager_color_key_value_store);
+ static MANAGER_ATTR(color_key_enabled, S_IRUGO|S_IWUSR,
+ 		manager_color_key_enabled_show, manager_color_key_enabled_store);
++static MANAGER_ATTR(alpha_blending_enabled, S_IRUGO|S_IWUSR,
++		manager_alpha_blending_enabled_show,
++		manager_alpha_blending_enabled_store);
++
+ 
+ static struct attribute *manager_sysfs_attrs[] = {
+ 	&manager_attr_name.attr,
+@@ -223,6 +243,7 @@ static struct attribute *manager_sysfs_attrs[] = {
+ 	&manager_attr_color_key_type.attr,
+ 	&manager_attr_color_key_value.attr,
+ 	&manager_attr_color_key_enabled.attr,
++	&manager_attr_alpha_blending_enabled.attr,
+ 	NULL
+ };
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch
new file mode 100644
index 0000000000..471a2a7f6c
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch
@@ -0,0 +1,97 @@
+From a5129f272a48aa22629137c9c31e60eddb8c3f5d Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Fri, 17 Apr 2009 14:24:46 +0530
+Subject: [PATCH 40/69] DSS2: Provided proper exclusion for destination color keying and alpha blending.
+
+OMAP does not support destination color key and alpha blending
+simultaneously.  So this patch does not allow the user
+so set both at a time.
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ drivers/video/omap2/dss/manager.c |   50 ++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 49 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+index 7965a84..108489c 100644
+--- a/drivers/video/omap2/dss/manager.c
++++ b/drivers/video/omap2/dss/manager.c
+@@ -137,12 +137,26 @@ static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
+ 	u32 key_value;
+ 
+ 	for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
+-	     key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
++			key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
+ 		if (sysfs_streq(buf, color_key_type_str[key_type]))
+ 			break;
+ 	}
+ 	if (key_type == ARRAY_SIZE(color_key_type_str))
+ 		return -EINVAL;
++	/* OMAP does not support destination color key and alpha blending
++	 * simultaneously.  So if alpha blending and color keying both are
++	 * enabled then refrain from setting the color key type to
++	 * gfx-destination
++	 */
++	if (!key_type) {
++		bool color_key_enabled;
++		bool alpha_blending_enabled;
++		color_key_enabled = mgr->get_trans_key_status(mgr);
++		alpha_blending_enabled = mgr->get_alpha_blending_status(mgr);
++		if (color_key_enabled && alpha_blending_enabled)
++			return -EINVAL;
++	}
++
+ 	mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
+ 	mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
+ 
+@@ -188,6 +202,23 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
+ 	if (sscanf(buf, "%d", &enable) != 1)
+ 		return -EINVAL;
+ 
++	/* OMAP does not support destination color keying and
++	 * alpha blending simultaneously.  so if alpha blending
++	 * is enabled refrain from enabling destination color
++	 * keying.
++	 */
++	if (enable) {
++		bool enabled;
++		enabled = mgr->get_alpha_blending_status(mgr);
++		if (enabled) {
++			enum omap_dss_color_key_type key_type;
++			mgr->get_trans_key_type_and_value(mgr,
++					&key_type, NULL);
++			if (!key_type)
++				return -EINVAL;
++		}
++
++	}
+ 	mgr->enable_trans_key(mgr, enable);
+ 
+ 	return size;
+@@ -205,6 +236,23 @@ static ssize_t manager_alpha_blending_enabled_store(
+ 	int enable;
+ 	if (sscanf(buf, "%d", &enable) != 1)
+ 		return -EINVAL;
++	/* OMAP does not support destination color keying and
++	 * alpha blending simultaneously.  so if destination
++	 * color keying is enabled refrain from enabling
++	 * alpha blending
++	 */
++	if (enable) {
++		bool enabled;
++		enabled = mgr->get_trans_key_status(mgr);
++		if (enabled) {
++			enum omap_dss_color_key_type key_type;
++			mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
++			if (!key_type)
++				return -EINVAL;
++
++		}
++
++	}
+ 	mgr->enable_alpha_blending(mgr, enable);
+ 	return size;
+ }
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch
new file mode 100644
index 0000000000..2c90c0cc06
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch
@@ -0,0 +1,71 @@
+From 9bcac9b9e678f476c83b5679b1215b6bc946130a Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Mon, 20 Apr 2009 16:26:18 +0200
+Subject: [PATCH 41/69] DSS2: Disable vertical offset with fieldmode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+When using fieldmode each field is basically a separate picture so the
+vertical filter should start at phase 0 for both fields.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |   23 +++++++++--------------
+ 1 files changed, 9 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 7e551c2..f15614b 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1029,12 +1029,12 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
+ static void _dispc_set_scaling(enum omap_plane plane,
+ 		u16 orig_width, u16 orig_height,
+ 		u16 out_width, u16 out_height,
+-		bool ilace, bool five_taps)
++		bool ilace, bool five_taps,
++		bool fieldmode)
+ {
+ 	int fir_hinc;
+ 	int fir_vinc;
+ 	int hscaleup, vscaleup;
+-	int fieldmode = 0;
+ 	int accu0 = 0;
+ 	int accu1 = 0;
+ 	u32 l;
+@@ -1072,17 +1072,12 @@ static void _dispc_set_scaling(enum omap_plane plane,
+ 
+ 	dispc_write_reg(dispc_reg_att[plane], l);
+ 
+-	if (ilace) {
+-		if (fieldmode) {
+-			accu0 = fir_vinc / 2;
+-			accu1 = 0;
+-		} else {
+-			accu0 = 0;
+-			accu1 = fir_vinc / 2;
+-			if (accu1 >= 1024/2) {
+-				accu0 = 1024/2;
+-				accu1 -= accu0;
+-			}
++	if (ilace && !fieldmode) {
++		accu0 = 0;
++		accu1 = fir_vinc / 2;
++		if (accu1 >= 1024/2) {
++			accu0 = 1024/2;
++			accu1 -= accu0;
+ 		}
+ 	}
+ 
+@@ -1582,7 +1577,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 	if (plane != OMAP_DSS_GFX) {
+ 		_dispc_set_scaling(plane, width, height,
+ 				   out_width, out_height,
+-				   ilace, five_taps);
++				   ilace, five_taps, fieldmode);
+ 		_dispc_set_vid_size(plane, out_width, out_height);
+ 		_dispc_set_vid_color_conv(plane, cconv);
+ 	}
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch
new file mode 100644
index 0000000000..7e2e44d809
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch
@@ -0,0 +1,34 @@
+From 9c6de0fed6e8a598d026d348533fdf731b737d55 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Mon, 20 Apr 2009 16:26:19 +0200
+Subject: [PATCH 42/69] DSS2: Don't enable fieldmode automatically
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+The only case where enabling fieldmode automatically seems reasonable
+is when source and destination heights are equal. Some kind of user
+controllable knob should be added so the user could enable field mode
+when the source is interlaced.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index f15614b..1c036c1 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1450,7 +1450,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 	if (paddr == 0)
+ 		return -EINVAL;
+ 
+-	if (ilace && height >= out_height)
++	if (ilace && height == out_height)
+ 		fieldmode = 1;
+ 
+ 	if (ilace) {
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch
new file mode 100644
index 0000000000..2e09335611
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch
@@ -0,0 +1,170 @@
+From 35e88797e93b107ba602dee1e2ac8ea761dccd4b Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Mon, 20 Apr 2009 16:26:20 +0200
+Subject: [PATCH 43/69] DSS2: Swap field 0 and field 1 registers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+The values for the registers which have alternate values for each field
+were reveresed to what the hardware expects. For the hardware field 0
+is the even field or the bottom field, field 1 is the odd field or the
+top field. So simply swap the register values.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |   66 ++++++++++++++++++++++-----------------
+ 1 files changed, 37 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 1c036c1..9bab6cf 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1072,12 +1072,16 @@ static void _dispc_set_scaling(enum omap_plane plane,
+ 
+ 	dispc_write_reg(dispc_reg_att[plane], l);
+ 
++	/*
++	 * field 0 = even field = bottom field
++	 * field 1 = odd field = top field
++	 */
+ 	if (ilace && !fieldmode) {
+-		accu0 = 0;
+-		accu1 = fir_vinc / 2;
+-		if (accu1 >= 1024/2) {
+-			accu0 = 1024/2;
+-			accu1 -= accu0;
++		accu1 = 0;
++		accu0 = fir_vinc / 2;
++		if (accu0 >= 1024/2) {
++			accu1 = 1024/2;
++			accu0 -= accu1;
+ 		}
+ 	}
+ 
+@@ -1266,34 +1270,38 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
+ 		fbh = width;
+ 	}
+ 
++	/*
++	 * field 0 = even field = bottom field
++	 * field 1 = odd field = top field
++	 */
+ 	switch (rotation + mirror * 4) {
+ 	case 0:
+-		*offset0 = 0;
++		*offset1 = 0;
+ 		if (fieldmode)
+-			*offset1 = screen_width * ps;
++			*offset0 = screen_width * ps;
+ 		else
+-			*offset1 = 0;
++			*offset0 = 0;
+ 		*row_inc = pixinc(1 + (screen_width - fbw) +
+ 				(fieldmode ? screen_width : 0),
+ 				ps);
+ 		*pix_inc = pixinc(1, ps);
+ 		break;
+ 	case 1:
+-		*offset0 = screen_width * (fbh - 1) * ps;
++		*offset1 = screen_width * (fbh - 1) * ps;
+ 		if (fieldmode)
+-			*offset1 = *offset0 + ps;
++			*offset0 = *offset1 + ps;
+ 		else
+-			*offset1 = *offset0;
++			*offset0 = *offset1;
+ 		*row_inc = pixinc(screen_width * (fbh - 1) + 1 +
+ 				(fieldmode ? 1 : 0), ps);
+ 		*pix_inc = pixinc(-screen_width, ps);
+ 		break;
+ 	case 2:
+-		*offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
++		*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
+ 		if (fieldmode)
+-			*offset1 = *offset0 - screen_width * ps;
++			*offset0 = *offset1 - screen_width * ps;
+ 		else
+-			*offset1 = *offset0;
++			*offset0 = *offset1;
+ 		*row_inc = pixinc(-1 -
+ 				(screen_width - fbw) -
+ 				(fieldmode ? screen_width : 0),
+@@ -1301,11 +1309,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
+ 		*pix_inc = pixinc(-1, ps);
+ 		break;
+ 	case 3:
+-		*offset0 = (fbw - 1) * ps;
++		*offset1 = (fbw - 1) * ps;
+ 		if (fieldmode)
+-			*offset1 = *offset0 - ps;
++			*offset0 = *offset1 - ps;
+ 		else
+-			*offset1 = *offset0;
++			*offset0 = *offset1;
+ 		*row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
+ 				(fieldmode ? 1 : 0), ps);
+ 		*pix_inc = pixinc(screen_width, ps);
+@@ -1313,11 +1321,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
+ 
+ 	/* mirroring */
+ 	case 0 + 4:
+-		*offset0 = (fbw - 1) * ps;
++		*offset1 = (fbw - 1) * ps;
+ 		if (fieldmode)
+-			*offset1 = *offset0 + screen_width * ps;
++			*offset0 = *offset1 + screen_width * ps;
+ 		else
+-			*offset1 = *offset0;
++			*offset0 = *offset1;
+ 		*row_inc = pixinc(screen_width * 2 - 1 +
+ 				(fieldmode ? screen_width : 0),
+ 				ps);
+@@ -1325,11 +1333,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
+ 		break;
+ 
+ 	case 1 + 4:
+-		*offset0 = 0;
++		*offset1 = 0;
+ 		if (fieldmode)
+-			*offset1 = *offset0 + screen_width * ps;
++			*offset0 = *offset1 + screen_width * ps;
+ 		else
+-			*offset1 = *offset0;
++			*offset0 = *offset1;
+ 		*row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
+ 				(fieldmode ? 1 : 0),
+ 				ps);
+@@ -1337,11 +1345,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
+ 		break;
+ 
+ 	case 2 + 4:
+-		*offset0 = screen_width * (fbh - 1) * ps;
++		*offset1 = screen_width * (fbh - 1) * ps;
+ 		if (fieldmode)
+-			*offset1 = *offset0 + screen_width * ps;
++			*offset0 = *offset1 + screen_width * ps;
+ 		else
+-			*offset1 = *offset0;
++			*offset0 = *offset1;
+ 		*row_inc = pixinc(1 - screen_width * 2 -
+ 				(fieldmode ? screen_width : 0),
+ 				ps);
+@@ -1349,11 +1357,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
+ 		break;
+ 
+ 	case 3 + 4:
+-		*offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
++		*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
+ 		if (fieldmode)
+-			*offset1 = *offset0 + screen_width * ps;
++			*offset0 = *offset1 + screen_width * ps;
+ 		else
+-			*offset1 = *offset0;
++			*offset0 = *offset1;
+ 		*row_inc = pixinc(screen_width * (fbh - 1) - 1 -
+ 				(fieldmode ? 1 : 0),
+ 				ps);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch
new file mode 100644
index 0000000000..19d24c3a07
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch
@@ -0,0 +1,76 @@
+From a9b3500bd14609750a2337e866e1df62627c1bac Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Mon, 20 Apr 2009 14:55:33 +0200
+Subject: [PATCH 44/69] DSS2: add sysfs entry for seting the rotate type
+
+This can help in utilizing VRAM memory better. Since with VRFB rotation
+we waste a lot of physical memory due to the VRFB HW design, provide the
+possibility to turn it off and free the extra memory for the use by other
+planes for example.
+---
+ drivers/video/omap2/omapfb/omapfb-sysfs.c |   42 ++++++++++++++++++++++++++++-
+ 1 files changed, 41 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+index 2c88718..4e3da42 100644
+--- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
++++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+@@ -43,6 +43,46 @@ static ssize_t show_rotate_type(struct device *dev,
+ 	return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->rotation_type);
+ }
+ 
++static ssize_t store_rotate_type(struct device *dev,
++		struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct fb_info *fbi = dev_get_drvdata(dev);
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	enum omap_dss_rotation_type rot_type;
++	int r;
++
++	rot_type = simple_strtoul(buf, NULL, 0);
++
++	if (rot_type != OMAP_DSS_ROT_DMA && rot_type != OMAP_DSS_ROT_VRFB)
++		return -EINVAL;
++
++	omapfb_lock(fbdev);
++
++	r = 0;
++	if (rot_type == ofbi->rotation_type)
++		goto out;
++
++	r = -EBUSY;
++	if (ofbi->region.size)
++		goto out;
++
++	ofbi->rotation_type = rot_type;
++
++	/*
++	 * Since the VRAM for this FB is not allocated at the moment we don't need to
++	 * do any further parameter checking at this point.
++	 */
++
++	r = count;
++out:
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++
+ static ssize_t show_mirror(struct device *dev,
+ 		struct device_attribute *attr, char *buf)
+ {
+@@ -327,7 +367,7 @@ static ssize_t show_virt(struct device *dev,
+ }
+ 
+ static struct device_attribute omapfb_attrs[] = {
+-	__ATTR(rotate_type, S_IRUGO, show_rotate_type, NULL),
++	__ATTR(rotate_type, S_IRUGO | S_IWUSR, show_rotate_type, store_rotate_type),
+ 	__ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror),
+ 	__ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size),
+ 	__ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays),
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0045-DSS2-Fixed-line-endings-from-to.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0045-DSS2-Fixed-line-endings-from-to.patch
new file mode 100644
index 0000000000..3206306cc7
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0045-DSS2-Fixed-line-endings-from-to.patch
@@ -0,0 +1,48 @@
+From b0e081456a9b094109c04467d041ff693843ca47 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Tue, 21 Apr 2009 09:25:16 +0300
+Subject: [PATCH 45/69] DSS2: Fixed line endings from , to ;
+
+---
+ drivers/video/omap2/dss/manager.c |   18 +++++++++---------
+ 1 files changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+index 108489c..bf059e0 100644
+--- a/drivers/video/omap2/dss/manager.c
++++ b/drivers/video/omap2/dss/manager.c
+@@ -599,22 +599,22 @@ int dss_init_overlay_managers(struct platform_device *pdev)
+ 			break;
+ 		}
+ 
+-		mgr->set_display = &omap_dss_set_display,
+-		mgr->unset_display = &omap_dss_unset_display,
+-		mgr->apply = &omap_dss_mgr_apply,
+-		mgr->set_default_color = &omap_dss_mgr_set_def_color,
++		mgr->set_display = &omap_dss_set_display;
++		mgr->unset_display = &omap_dss_unset_display;
++		mgr->apply = &omap_dss_mgr_apply;
++		mgr->set_default_color = &omap_dss_mgr_set_def_color;
+ 		mgr->set_trans_key_type_and_value =
+-			&omap_dss_mgr_set_trans_key_type_and_value,
++			&omap_dss_mgr_set_trans_key_type_and_value;
+ 		mgr->get_trans_key_type_and_value =
+-			&omap_dss_mgr_get_trans_key_type_and_value,
+-		mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
+-		mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status,
++			&omap_dss_mgr_get_trans_key_type_and_value;
++		mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key;
++		mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status;
+ 		mgr->enable_alpha_blending =
+ 			&omap_dss_mgr_enable_alpha_blending;
+ 		mgr->get_alpha_blending_status =
+ 			omap_dss_mgr_get_alpha_blending_status;
+ 		mgr->get_default_color = &omap_dss_mgr_get_default_color;
+-		mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
++		mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC;
+ 
+ 		dss_overlay_setup_dispc_manager(mgr);
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch
new file mode 100644
index 0000000000..301db79267
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch
@@ -0,0 +1,26 @@
+From 0f88992b2681aed4f31dc7dd3926b357bbc95154 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Tue, 21 Apr 2009 10:11:55 +0300
+Subject: [PATCH 46/69] DSS2: DSI: decrease sync timeout from 60s to 2s
+
+The framedone-problem should be ok now, so we shouldn't get long waits.
+---
+ drivers/video/omap2/dss/dsi.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+index 50af925..d59ad38 100644
+--- a/drivers/video/omap2/dss/dsi.c
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -3216,7 +3216,7 @@ static void dsi_push_set_mirror(struct omap_display *display, int mirror)
+ 
+ static int dsi_wait_sync(struct omap_display *display)
+ {
+-	long wait = msecs_to_jiffies(60000);
++	long wait = msecs_to_jiffies(2000);
+ 	struct completion compl;
+ 
+ 	DSSDBGF("");
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch
new file mode 100644
index 0000000000..fbc30b8858
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch
@@ -0,0 +1,44 @@
+From 7ddd5eaa7bc345c3719d613a46a95b7e8052ad2c Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Tue, 21 Apr 2009 15:18:36 +0200
+Subject: [PATCH 47/69] DSS2: fix return value for rotate_type sysfs function
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ drivers/video/omap2/omapfb/omapfb-sysfs.c |    9 ++++-----
+ 1 files changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+index 4e3da42..13028ae 100644
+--- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
++++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+@@ -64,9 +64,10 @@ static ssize_t store_rotate_type(struct device *dev,
+ 	if (rot_type == ofbi->rotation_type)
+ 		goto out;
+ 
+-	r = -EBUSY;
+-	if (ofbi->region.size)
++	if (ofbi->region.size) {
++		r = -EBUSY;
+ 		goto out;
++	}
+ 
+ 	ofbi->rotation_type = rot_type;
+ 
+@@ -74,12 +75,10 @@ static ssize_t store_rotate_type(struct device *dev,
+ 	 * Since the VRAM for this FB is not allocated at the moment we don't need to
+ 	 * do any further parameter checking at this point.
+ 	 */
+-
+-	r = count;
+ out:
+ 	omapfb_unlock(fbdev);
+ 
+-	return r;
++	return r ? r : count;
+ }
+ 
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch
new file mode 100644
index 0000000000..1097fedabf
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch
@@ -0,0 +1,123 @@
+From e34564db95627ad20e918b240c45e2bd5555f7e8 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 22 Apr 2009 10:06:08 +0300
+Subject: [PATCH 48/69] OMAP2/3: DMA: implement trans copy and const fill
+
+Implement transparent copy and constant fill features for OMAP2/3.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/plat-omap/dma.c              |   81 +++++++++++++++++++++------------
+ arch/arm/plat-omap/include/mach/dma.h |    1 +
+ 2 files changed, 52 insertions(+), 30 deletions(-)
+
+diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
+index 3fd0e77..060ac71 100755
+--- a/arch/arm/plat-omap/dma.c
++++ b/arch/arm/plat-omap/dma.c
+@@ -310,41 +310,62 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params);
+ 
+ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
+ {
+-	u16 w;
+-
+ 	BUG_ON(omap_dma_in_1510_mode());
+ 
+-	if (cpu_class_is_omap2()) {
+-		REVISIT_24XX();
+-		return;
+-	}
++	if (cpu_class_is_omap1()) {
++		u16 w;
+ 
+-	w = dma_read(CCR2(lch));
+-	w &= ~0x03;
++		w = dma_read(CCR2(lch));
++		w &= ~0x03;
+ 
+-	switch (mode) {
+-	case OMAP_DMA_CONSTANT_FILL:
+-		w |= 0x01;
+-		break;
+-	case OMAP_DMA_TRANSPARENT_COPY:
+-		w |= 0x02;
+-		break;
+-	case OMAP_DMA_COLOR_DIS:
+-		break;
+-	default:
+-		BUG();
++		switch (mode) {
++		case OMAP_DMA_CONSTANT_FILL:
++			w |= 0x01;
++			break;
++		case OMAP_DMA_TRANSPARENT_COPY:
++			w |= 0x02;
++			break;
++		case OMAP_DMA_COLOR_DIS:
++			break;
++		default:
++			BUG();
++		}
++		dma_write(w, CCR2(lch));
++
++		w = dma_read(LCH_CTRL(lch));
++		w &= ~0x0f;
++		/* Default is channel type 2D */
++		if (mode) {
++			dma_write((u16)color, COLOR_L(lch));
++			dma_write((u16)(color >> 16), COLOR_U(lch));
++			w |= 1;		/* Channel type G */
++		}
++		dma_write(w, LCH_CTRL(lch));
+ 	}
+-	dma_write(w, CCR2(lch));
+ 
+-	w = dma_read(LCH_CTRL(lch));
+-	w &= ~0x0f;
+-	/* Default is channel type 2D */
+-	if (mode) {
+-		dma_write((u16)color, COLOR_L(lch));
+-		dma_write((u16)(color >> 16), COLOR_U(lch));
+-		w |= 1;		/* Channel type G */
++	if (cpu_class_is_omap2()) {
++		u32 val;
++
++		val = dma_read(CCR(lch));
++		val &= ~((1 << 17) | (1 << 16));
++
++		switch (mode) {
++		case OMAP_DMA_CONSTANT_FILL:
++			val |= 1 << 16;
++			break;
++		case OMAP_DMA_TRANSPARENT_COPY:
++			val |= 1 << 17;
++			break;
++		case OMAP_DMA_COLOR_DIS:
++			break;
++		default:
++			BUG();
++		}
++		dma_write(val, CCR(lch));
++
++		color &= 0xffffff;
++		dma_write(color, COLOR(lch));
+ 	}
+-	dma_write(w, LCH_CTRL(lch));
+ }
+ EXPORT_SYMBOL(omap_set_dma_color_mode);
+ 
+diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
+index 224b077..4e34f47 100644
+--- a/arch/arm/plat-omap/include/mach/dma.h
++++ b/arch/arm/plat-omap/include/mach/dma.h
+@@ -144,6 +144,7 @@
+ #define OMAP_DMA4_CSSA_U(n)		0
+ #define OMAP_DMA4_CDSA_L(n)		0
+ #define OMAP_DMA4_CDSA_U(n)		0
++#define OMAP1_DMA_COLOR(n)		0
+ 
+ /*----------------------------------------------------------------------------*/
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch
new file mode 100644
index 0000000000..d9901f95d9
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch
@@ -0,0 +1,101 @@
+From 02034cc79f69512a6037f03ad1243c28f59fdd8a Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 22 Apr 2009 10:25:20 +0300
+Subject: [PATCH 49/69] DSS2: VRAM: clear allocated area with DMA
+
+Use DMA constant fill feature to clear VRAM area when
+someone allocates it.
+---
+ arch/arm/plat-omap/vram.c |   57 +++++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 57 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
+index 8e9fe77..90276ac 100644
+--- a/arch/arm/plat-omap/vram.c
++++ b/arch/arm/plat-omap/vram.c
+@@ -31,11 +31,13 @@
+ #include <linux/seq_file.h>
+ #include <linux/bootmem.h>
+ #include <linux/omapfb.h>
++#include <linux/completion.h>
+ 
+ #include <asm/setup.h>
+ 
+ #include <mach/sram.h>
+ #include <mach/vram.h>
++#include <mach/dma.h>
+ 
+ #ifdef DEBUG
+ #define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
+@@ -276,6 +278,59 @@ int omap_vram_reserve(unsigned long paddr, size_t size)
+ }
+ EXPORT_SYMBOL(omap_vram_reserve);
+ 
++static void _omap_vram_dma_cb(int lch, u16 ch_status, void *data)
++{
++	struct completion *compl = data;
++	complete(compl);
++}
++
++static int _omap_vram_clear(u32 paddr, unsigned pages)
++{
++	struct completion compl;
++        unsigned elem_count;
++        unsigned frame_count;
++	int r;
++	int lch;
++
++	init_completion(&compl);
++
++        r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
++			_omap_vram_dma_cb,
++                        &compl, &lch);
++        if (r) {
++		pr_err("VRAM: request_dma failed for memory clear\n");
++		return -EBUSY;
++	}
++
++        elem_count = pages * PAGE_SIZE / 4;
++        frame_count = 1;
++
++        omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
++                        elem_count, frame_count,
++                        OMAP_DMA_SYNC_ELEMENT,
++                        0, 0);
++
++        omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
++			paddr, 0, 0);
++
++	omap_set_dma_color_mode(lch, OMAP_DMA_CONSTANT_FILL, 0x000000);
++
++        omap_start_dma(lch);
++
++	if (wait_for_completion_timeout(&compl, msecs_to_jiffies(1000)) == 0) {
++		omap_stop_dma(lch);
++		pr_err("VRAM: dma timeout while clearing memory\n");
++		r = -EIO;
++		goto err;
++	}
++
++	r = 0;
++err:
++	omap_free_dma(lch);
++
++	return r;
++}
++
+ static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
+ {
+ 	struct vram_region *rm;
+@@ -313,6 +368,8 @@ found:
+ 
+ 		*paddr = start;
+ 
++		_omap_vram_clear(start, pages);
++
+ 		return 0;
+ 	}
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch
new file mode 100644
index 0000000000..4a0a078bc7
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch
@@ -0,0 +1,53 @@
+From 07482193cccdfe9ede1f47d72790dfbe54343505 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 22 Apr 2009 10:26:06 +0300
+Subject: [PATCH 50/69] DSS2: OMAPFB: remove fb clearing code
+
+VRAM manager does the clearing now when the area is allocated.
+---
+ drivers/video/omap2/omapfb/omapfb-main.c |    8 --------
+ 1 files changed, 0 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index cd63740..76e7c6c 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -1174,7 +1174,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
+ 	struct omapfb2_mem_region *rg;
+ 	void __iomem *vaddr;
+ 	int r;
+-	int clear = 0;
+ 
+ 	rg = &ofbi->region;
+ 	memset(rg, 0, sizeof(*rg));
+@@ -1184,7 +1183,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
+ 	if (!paddr) {
+ 		DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
+ 		r = omap_vram_alloc(OMAPFB_MEMTYPE_SDRAM, size, &paddr);
+-		clear = 1;
+ 	} else {
+ 		DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
+ 				ofbi->id);
+@@ -1206,9 +1204,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
+ 		}
+ 
+ 		DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
+-
+-		if (clear)
+-			memset_io(vaddr, 0, size);
+ 	} else {
+ 		void __iomem *va;
+ 
+@@ -1232,9 +1227,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
+ 		rg->vrfb.vaddr[0] = va;
+ 
+ 		vaddr = NULL;
+-
+-		if (clear)
+-			memset_io(va, 0, size);
+ 	}
+ 
+ 	rg->paddr = paddr;
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch
new file mode 100644
index 0000000000..739d3cd1a6
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch
@@ -0,0 +1,170 @@
+From b47aef28536f3c276d232c41cd3084c69389dca4 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 22 Apr 2009 14:11:52 +0300
+Subject: [PATCH 51/69] DSS2: VRAM: use debugfs, not procfs
+
+---
+ arch/arm/plat-omap/vram.c |  103 +++++++++++++++------------------------------
+ 1 files changed, 34 insertions(+), 69 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
+index 90276ac..e847579 100644
+--- a/arch/arm/plat-omap/vram.c
++++ b/arch/arm/plat-omap/vram.c
+@@ -27,11 +27,11 @@
+ #include <linux/mm.h>
+ #include <linux/list.h>
+ #include <linux/dma-mapping.h>
+-#include <linux/proc_fs.h>
+ #include <linux/seq_file.h>
+ #include <linux/bootmem.h>
+ #include <linux/omapfb.h>
+ #include <linux/completion.h>
++#include <linux/debugfs.h>
+ 
+ #include <asm/setup.h>
+ 
+@@ -398,88 +398,54 @@ int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
+ }
+ EXPORT_SYMBOL(omap_vram_alloc);
+ 
+-#ifdef CONFIG_PROC_FS
+-static void *r_next(struct seq_file *m, void *v, loff_t *pos)
+-{
+-	struct list_head *l = v;
+-
+-	(*pos)++;
+-
+-	if (list_is_last(l, &region_list))
+-		return NULL;
+-
+-	return l->next;
+-}
+-
+-static void *r_start(struct seq_file *m, loff_t *pos)
+-{
+-	loff_t p = *pos;
+-	struct list_head *l = &region_list;
+-
+-	mutex_lock(&region_mutex);
+-
+-	do {
+-		l = l->next;
+-		if (l == &region_list)
+-			return NULL;
+-	} while (p--);
+-
+-	return l;
+-}
+-
+-static void r_stop(struct seq_file *m, void *v)
+-{
+-	mutex_unlock(&region_mutex);
+-}
+-
+-static int r_show(struct seq_file *m, void *v)
++#if defined(CONFIG_DEBUG_FS)
++static int vram_debug_show(struct seq_file *s, void *unused)
+ {
+ 	struct vram_region *vr;
+ 	struct vram_alloc *va;
+ 	unsigned size;
+ 
+-	vr = list_entry(v, struct vram_region, list);
+-
+-	size = vr->pages << PAGE_SHIFT;
+-
+-	seq_printf(m, "%08lx-%08lx (%d bytes)\n",
+-			vr->paddr, vr->paddr + size - 1,
+-			size);
++	mutex_lock(&region_mutex);
+ 
+-	list_for_each_entry(va, &vr->alloc_list, list) {
+-		size = va->pages << PAGE_SHIFT;
+-		seq_printf(m, "    %08lx-%08lx (%d bytes)\n",
+-				va->paddr, va->paddr + size - 1,
++	list_for_each_entry(vr, &region_list, list) {
++		size = vr->pages << PAGE_SHIFT;
++		seq_printf(s, "%08lx-%08lx (%d bytes)\n",
++				vr->paddr, vr->paddr + size - 1,
+ 				size);
+-	}
+ 
++		list_for_each_entry(va, &vr->alloc_list, list) {
++			size = va->pages << PAGE_SHIFT;
++			seq_printf(s, "    %08lx-%08lx (%d bytes)\n",
++					va->paddr, va->paddr + size - 1,
++					size);
++		}
++	}
+ 
++	mutex_unlock(&region_mutex);
+ 
+ 	return 0;
+ }
+ 
+-static const struct seq_operations resource_op = {
+-	.start	= r_start,
+-	.next	= r_next,
+-	.stop	= r_stop,
+-	.show	= r_show,
+-};
+-
+-static int vram_open(struct inode *inode, struct file *file)
++static int vram_debug_open(struct inode *inode, struct file *file)
+ {
+-	return seq_open(file, &resource_op);
++	return single_open(file, vram_debug_show, inode->i_private);
+ }
+ 
+-static const struct file_operations proc_vram_operations = {
+-	.open		= vram_open,
+-	.read		= seq_read,
+-	.llseek		= seq_lseek,
+-	.release	= seq_release,
++static const struct file_operations vram_debug_fops = {
++	.open           = vram_debug_open,
++	.read           = seq_read,
++	.llseek         = seq_lseek,
++	.release        = single_release,
+ };
+ 
+-static int __init omap_vram_create_proc(void)
++static int __init omap_vram_create_debugfs(void)
+ {
+-	proc_create("omap-vram", 0, NULL, &proc_vram_operations);
++	struct dentry *d;
++
++	d = debugfs_create_file("vram", S_IRUGO, NULL,
++			NULL, &vram_debug_fops);
++	if (IS_ERR(d))
++		return PTR_ERR(d);
+ 
+ 	return 0;
+ }
+@@ -487,7 +453,7 @@ static int __init omap_vram_create_proc(void)
+ 
+ static __init int omap_vram_init(void)
+ {
+-	int i, r;
++	int i;
+ 
+ 	vram_initialized = 1;
+ 
+@@ -495,10 +461,9 @@ static __init int omap_vram_init(void)
+ 		omap_vram_add_region(postponed_regions[i].paddr,
+ 				postponed_regions[i].size);
+ 
+-#ifdef CONFIG_PROC_FS
+-	r = omap_vram_create_proc();
+-	if (r)
+-		return -ENOMEM;
++#ifdef CONFIG_DEBUG_FS
++	if (omap_vram_create_debugfs())
++		pr_err("VRAM: Failed to create debugfs file\n");
+ #endif
+ 
+ 	return 0;
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch
new file mode 100644
index 0000000000..a28a96b23b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch
@@ -0,0 +1,34 @@
+From 635fa66abe6e502c9b78b1dc66757bf67fd163e1 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Wed, 22 Apr 2009 14:40:48 +0200
+Subject: [PATCH 52/69] DSS2: VRAM: fix section mismatch warning
+
+postponed_regions are accessed from the non __init
+omap_vram_add_region().
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ arch/arm/plat-omap/vram.c |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
+index e847579..b126a64 100644
+--- a/arch/arm/plat-omap/vram.c
++++ b/arch/arm/plat-omap/vram.c
+@@ -63,11 +63,11 @@
+ #define MAX_POSTPONED_REGIONS 10
+ 
+ static bool vram_initialized;
+-static int postponed_cnt __initdata;
++static int postponed_cnt;
+ static struct {
+ 	unsigned long paddr;
+ 	size_t size;
+-} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
++} postponed_regions[MAX_POSTPONED_REGIONS];
+ 
+ struct vram_alloc {
+ 	struct list_head list;
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch
new file mode 100644
index 0000000000..38d162d024
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch
@@ -0,0 +1,41 @@
+From c7ce3c5e9f7e28900b8ea9c3e1afe41dcdc0863d Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 23 Apr 2009 10:46:53 +0300
+Subject: [PATCH 53/69] DSS2: disable LCD & DIGIT before resetting DSS
+
+This seems to fix the synclost problem that we get, if the bootloader
+starts the DSS and the kernel resets it.
+---
+ drivers/video/omap2/dss/dss.c |    8 +++++---
+ 1 files changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
+index adc1f34..aab9758 100644
+--- a/drivers/video/omap2/dss/dss.c
++++ b/drivers/video/omap2/dss/dss.c
+@@ -285,6 +285,11 @@ int dss_init(bool skip_init)
+ 	}
+ 
+ 	if (!skip_init) {
++		/* disable LCD and DIGIT output. This seems to fix the synclost
++		 * problem that we get, if the bootloader starts the DSS and
++		 * the kernel resets it */
++		omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
++
+ 		/* We need to wait here a bit, otherwise we sometimes start to
+ 		 * get synclost errors, and after that only power cycle will
+ 		 * restore DSS functionality. I have no idea why this happens.
+@@ -294,10 +299,7 @@ int dss_init(bool skip_init)
+ 		msleep(50);
+ 
+ 		_omap_dss_reset();
+-
+ 	}
+-	else
+-		printk("DSS SKIP RESET\n");
+ 
+ 	/* autoidle */
+ 	REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0054-DSS2-DSI-more-error-handling.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0054-DSS2-DSI-more-error-handling.patch
new file mode 100644
index 0000000000..5f4f155452
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0054-DSS2-DSI-more-error-handling.patch
@@ -0,0 +1,85 @@
+From 3b27a3c4f6b84e46c84509f610dfe1456c0d72d3 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Mon, 27 Apr 2009 11:06:16 +0300
+Subject: [PATCH 54/69] DSS2: DSI: more error handling
+
+---
+ drivers/video/omap2/dss/dsi.c |   27 +++++++++++++++++++++++++++
+ 1 files changed, 27 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+index d59ad38..d8df353 100644
+--- a/drivers/video/omap2/dss/dsi.c
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -289,6 +289,8 @@ static struct
+ 
+ 	bool autoupdate_setup;
+ 
++	u32		errors;
++	spinlock_t	errors_lock;
+ #ifdef DEBUG
+ 	ktime_t perf_setup_time;
+ 	ktime_t perf_start_time;
+@@ -541,6 +543,9 @@ void dsi_irq_handler(void)
+ 	if (irqstatus & DSI_IRQ_ERROR_MASK) {
+ 		DSSERR("DSI error, irqstatus %x\n", irqstatus);
+ 		print_irq_status(irqstatus);
++		spin_lock(&dsi.errors_lock);
++		dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
++		spin_unlock(&dsi.errors_lock);
+ 	} else if (debug_irq) {
+ 		print_irq_status(irqstatus);
+ 	}
+@@ -616,6 +621,17 @@ static void _dsi_initialize_irq(void)
+ 			-1 & (~DSI_CIO_IRQ_ERRCONTROL2));
+ }
+ 
++static u32 dsi_get_errors(void)
++{
++	unsigned long flags;
++	u32 e;
++	spin_lock_irqsave(&dsi.errors_lock, flags);
++	e = dsi.errors;
++	dsi.errors = 0;
++	spin_unlock_irqrestore(&dsi.errors_lock, flags);
++	return e;
++}
++
+ static void dsi_vc_enable_bta_irq(int channel)
+ {
+ 	u32 l;
+@@ -1807,6 +1823,7 @@ static int dsi_vc_send_bta(int channel)
+ static int dsi_vc_send_bta_sync(int channel)
+ {
+ 	int r = 0;
++	u32 err;
+ 
+ 	init_completion(&dsi.bta_completion);
+ 
+@@ -1822,6 +1839,13 @@ static int dsi_vc_send_bta_sync(int channel)
+ 		r = -EIO;
+ 		goto err;
+ 	}
++
++	err = dsi_get_errors();
++	if (err) {
++		DSSERR("Error while sending BTA: %x\n", err);
++		r = -EIO;
++		goto err;
++	}
+ err:
+ 	dsi_vc_disable_bta_irq(channel);
+ 
+@@ -3720,6 +3744,9 @@ int dsi_init(void)
+ {
+ 	u32 rev;
+ 
++	spin_lock_init(&dsi.errors_lock);
++	dsi.errors = 0;
++
+ 	spin_lock_init(&dsi.cmd_lock);
+ 	dsi.cmd_fifo = kfifo_alloc(
+ 			DSI_CMD_FIFO_LEN * sizeof(struct dsi_cmd_item),
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0055-DSS2-Added-global-alpha-support.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0055-DSS2-Added-global-alpha-support.patch
new file mode 100644
index 0000000000..c545b648cc
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0055-DSS2-Added-global-alpha-support.patch
@@ -0,0 +1,230 @@
+From c8588370442424ac31e2392b07891615629eb999 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Fri, 24 Apr 2009 15:29:06 +0530
+Subject: [PATCH 55/69] DSS2: Added global alpha support.
+
+global_alpha sysfs entry for video1 plane will always show 255 as
+it does not support global_alpha.
+Initliazied the global alpha field for all the overlays
+to 255 (fully opaque).
+Documentation also updated.
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ Documentation/arm/OMAP/DSS                |    1 +
+ arch/arm/plat-omap/include/mach/display.h |    1 +
+ drivers/video/omap2/dss/dispc.c           |   25 ++++++++++++++++---
+ drivers/video/omap2/dss/dss.h             |    3 +-
+ drivers/video/omap2/dss/manager.c         |    3 +-
+ drivers/video/omap2/dss/overlay.c         |   37 +++++++++++++++++++++++++++++
+ 6 files changed, 64 insertions(+), 6 deletions(-)
+
+diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
+index 9e902a2..249e1a3 100644
+--- a/Documentation/arm/OMAP/DSS
++++ b/Documentation/arm/OMAP/DSS
+@@ -133,6 +133,7 @@ name
+ output_size	width,height
+ position	x,y
+ screen_width	width
++global_alpha   	global alpha 0-255 0=transparent 255=opaque
+ 
+ /sys/devices/platform/omapdss/manager? directory:
+ display		Destination display
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+index d0b4c83..45b16ca 100644
+--- a/arch/arm/plat-omap/include/mach/display.h
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -363,6 +363,7 @@ struct omap_overlay_info {
+ 	u16 pos_y;
+ 	u16 out_width;	/* if 0, out_width == width */
+ 	u16 out_height;	/* if 0, out_height == height */
++	u8 global_alpha;
+ };
+ 
+ enum omap_overlay_caps {
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 9bab6cf..b6a39f5 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -778,6 +778,17 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
+ 	dispc_write_reg(vsi_reg[plane-1], val);
+ }
+ 
++static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
++{
++
++	BUG_ON(plane == OMAP_DSS_VIDEO1);
++
++	if (plane == OMAP_DSS_GFX)
++		REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
++	else if (plane == OMAP_DSS_VIDEO2)
++		REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
++}
++
+ static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
+ {
+ 	const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
+@@ -1444,7 +1455,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 		enum omap_color_mode color_mode,
+ 		bool ilace,
+ 		enum omap_dss_rotation_type rotation_type,
+-		u8 rotation, int mirror)
++		u8 rotation, int mirror,
++		u8 global_alpha)
+ {
+ 	const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
+ 	bool five_taps = 0;
+@@ -1592,6 +1604,9 @@ static int _dispc_setup_plane(enum omap_plane plane,
+ 
+ 	_dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
+ 
++	if (plane != OMAP_DSS_VIDEO1)
++		_dispc_setup_global_alpha(plane, global_alpha);
++
+ 	return 0;
+ }
+ 
+@@ -3011,7 +3026,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
+ 		       enum omap_color_mode color_mode,
+ 		       bool ilace,
+ 		       enum omap_dss_rotation_type rotation_type,
+-		       u8 rotation, bool mirror)
++		       u8 rotation, bool mirror, u8 global_alpha)
+ {
+ 	int r = 0;
+ 
+@@ -3032,7 +3047,8 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
+ 			   out_width, out_height,
+ 			   color_mode, ilace,
+ 			   rotation_type,
+-			   rotation, mirror);
++			   rotation, mirror,
++			   global_alpha);
+ 
+ 	enable_clocks(0);
+ 
+@@ -3247,7 +3263,8 @@ void dispc_setup_partial_planes(struct omap_display *display,
+ 				pi->color_mode, 0,
+ 				pi->rotation_type,
+ 				pi->rotation,
+-				pi->mirror);
++				pi->mirror,
++				pi->global_alpha);
+ 
+ 		dispc_enable_plane(ovl->id, 1);
+ 	}
+diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
+index 1d01ff6..20cef0a 100644
+--- a/drivers/video/omap2/dss/dss.h
++++ b/drivers/video/omap2/dss/dss.h
+@@ -273,7 +273,8 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
+ 		      enum omap_color_mode color_mode,
+ 		      bool ilace,
+ 		      enum omap_dss_rotation_type rotation_type,
+-		      u8 rotation, bool mirror);
++		      u8 rotation, bool mirror,
++		      u8 global_alpha);
+ 
+ void dispc_go(enum omap_channel channel);
+ void dispc_enable_lcd_out(bool enable);
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+index bf059e0..1e6cd8d 100644
+--- a/drivers/video/omap2/dss/manager.c
++++ b/drivers/video/omap2/dss/manager.c
+@@ -464,7 +464,8 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
+ 				ilace,
+ 				ovl->info.rotation_type,
+ 				ovl->info.rotation,
+-				ovl->info.mirror);
++				ovl->info.mirror,
++				ovl->info.global_alpha);
+ 
+ 		if (r) {
+ 			DSSERR("dispc_setup_plane failed for ovl %d\n",
+diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
+index c047206..035a57a 100644
+--- a/drivers/video/omap2/dss/overlay.c
++++ b/drivers/video/omap2/dss/overlay.c
+@@ -194,6 +194,37 @@ static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf,
+ 	return size;
+ }
+ 
++static ssize_t overlay_global_alpha_show(struct omap_overlay *ovl, char *buf)
++{
++	return snprintf(buf, PAGE_SIZE, "%d\n",
++			ovl->info.global_alpha);
++}
++
++static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
++		const char *buf, size_t size)
++{
++	int r;
++	struct omap_overlay_info info;
++
++	ovl->get_overlay_info(ovl, &info);
++
++	/* Video1 plane does not support global alpha
++	 * to always make it 255 completely opaque
++	 */
++	if (ovl->id == OMAP_DSS_VIDEO1)
++		info.global_alpha = 255;
++	else
++		info.global_alpha = simple_strtoul(buf, NULL, 10);
++
++	if ((r = ovl->set_overlay_info(ovl, &info)))
++		return r;
++
++	if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
++		return r;
++
++	return size;
++}
++
+ struct overlay_attribute {
+ 	struct attribute attr;
+ 	ssize_t (*show)(struct omap_overlay *, char *);
+@@ -215,6 +246,8 @@ static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
+ 		overlay_output_size_show, overlay_output_size_store);
+ static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
+ 		overlay_enabled_show, overlay_enabled_store);
++static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR,
++		overlay_global_alpha_show, overlay_global_alpha_store);
+ 
+ static struct attribute *overlay_sysfs_attrs[] = {
+ 	&overlay_attr_name.attr,
+@@ -224,6 +257,7 @@ static struct attribute *overlay_sysfs_attrs[] = {
+ 	&overlay_attr_position.attr,
+ 	&overlay_attr_output_size.attr,
+ 	&overlay_attr_enabled.attr,
++	&overlay_attr_global_alpha.attr,
+ 	NULL
+ };
+ 
+@@ -444,6 +478,7 @@ void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
+ 			ovl->id = OMAP_DSS_GFX;
+ 			ovl->supported_modes = OMAP_DSS_COLOR_GFX_OMAP3;
+ 			ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
++			ovl->info.global_alpha = 255;
+ 			break;
+ 		case 1:
+ 			ovl->name = "vid1";
+@@ -451,6 +486,7 @@ void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
+ 			ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
+ 			ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
+ 				OMAP_DSS_OVL_CAP_DISPC;
++			ovl->info.global_alpha = 255;
+ 			break;
+ 		case 2:
+ 			ovl->name = "vid2";
+@@ -458,6 +494,7 @@ void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
+ 			ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
+ 			ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
+ 				OMAP_DSS_OVL_CAP_DISPC;
++			ovl->info.global_alpha = 255;
+ 			break;
+ 		}
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0056-DSS2-Rotation-attrs-for-YUV-need-not-to-be-reversed.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0056-DSS2-Rotation-attrs-for-YUV-need-not-to-be-reversed.patch
new file mode 100644
index 0000000000..c46fda0d52
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0056-DSS2-Rotation-attrs-for-YUV-need-not-to-be-reversed.patch
@@ -0,0 +1,35 @@
+From 32cf39c92dfd28e18936c31eea90b4d43a3c0968 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Fri, 24 Apr 2009 14:33:48 +0530
+Subject: [PATCH 56/69] DSS2: Rotation attrs for YUV need not to be reversed for 90 and 270
+
+DSS2 supports horizontal mirroing. so only 180 and 0 degree attributes needs
+to be reversed for mirroring.
+Slight corrupt image is seen with 90 ad 270 degree rotation with mirroring
+when the image height and widht is not 32-pixels aligned. To be specific
+resolution is 168X192.
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ drivers/video/omap2/dss/dispc.c |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index b6a39f5..f79decb 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1110,9 +1110,9 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
+ 		if (mirroring) {
+ 			switch (rotation) {
+ 			case 0: vidrot = 2; break;
+-			case 1: vidrot = 3; break;
++			case 1: vidrot = 1; break;
+ 			case 2: vidrot = 0; break;
+-			case 3: vidrot = 1; break;
++			case 3: vidrot = 3; break;
+ 			}
+ 		} else {
+ 			switch (rotation) {
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0057-DSS2-Documentation-update-for-new-sysfs-entries-in.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0057-DSS2-Documentation-update-for-new-sysfs-entries-in.patch
new file mode 100644
index 0000000000..929f41b590
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0057-DSS2-Documentation-update-for-new-sysfs-entries-in.patch
@@ -0,0 +1,32 @@
+From bc67f1fce4472087014fdacd3f44ea732200533e Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Mon, 27 Apr 2009 13:15:07 +0530
+Subject: [PATCH 57/69] DSS2: Documentation update for new sysfs entries in omapdss/manager
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ Documentation/arm/OMAP/DSS |    7 ++++++-
+ 1 files changed, 6 insertions(+), 1 deletions(-)
+
+diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
+index 249e1a3..751000b 100644
+--- a/Documentation/arm/OMAP/DSS
++++ b/Documentation/arm/OMAP/DSS
+@@ -136,8 +136,13 @@ screen_width	width
+ global_alpha   	global alpha 0-255 0=transparent 255=opaque
+ 
+ /sys/devices/platform/omapdss/manager? directory:
+-display		Destination display
++display				Destination display
+ name
++alpha_blending_enabled		0=off 1=on
++color_key_enabled		0=off 1=on
++color_key_type			gfx-destination video-source
++color_key_value			0 to 2^24
++default_color			default background color RGB24 0 to 2^24
+ 
+ /sys/devices/platform/omapdss/display? directory:
+ ctrl_name	Controller name
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0058-DSS2-Don-t-touch-plane-coordinates-when-changing-fb.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0058-DSS2-Don-t-touch-plane-coordinates-when-changing-fb.patch
new file mode 100644
index 0000000000..7a6f23b349
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0058-DSS2-Don-t-touch-plane-coordinates-when-changing-fb.patch
@@ -0,0 +1,56 @@
+From 9500c899f05048d17ced4340ecfd377656a23934 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Fri, 17 Apr 2009 18:34:33 +0200
+Subject: [PATCH 58/69] DSS2: Don't touch plane coordinates when changing fb->ovl mapping
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+When attaching overlays to a framebuffer via the 'overlays' sysfs file
+do not touch the planes' coordinates. Without this change attaching
+VID2 to a framebuffer which already has VID1 attached would cause VID1
+to be reset to position 0,0 and scaled to 1:1 size. Also call
+omapfb_apply_changes() only once after all the overlays have been
+attached to avoid fiddling with all the overlays several times.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/omapfb/omapfb-sysfs.c |   13 ++++++-------
+ 1 files changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+index 13028ae..702199d 100644
+--- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
++++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+@@ -183,6 +183,7 @@ static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
+ 	struct omap_overlay *ovl;
+ 	int num_ovls, r, i;
+ 	int len;
++	bool added = false;
+ 
+ 	num_ovls = 0;
+ 
+@@ -284,15 +285,13 @@ static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
+ 
+ 		ofbi->overlays[ofbi->num_overlays++] = ovl;
+ 
+-		r = omapfb_apply_changes(fbi, 1);
++		added = true;
++	}
++
++	if (added) {
++		r = omapfb_apply_changes(fbi, 0);
+ 		if (r)
+ 			goto out;
+-
+-		if (ovl->manager) {
+-			r = ovl->manager->apply(ovl->manager);
+-			if (r)
+-				goto out;
+-		}
+ 	}
+ 
+ 	r = count;
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0059-DSS2-DSI-configure-ENTER-EXIT_HS_MODE_LATENCY.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0059-DSS2-DSI-configure-ENTER-EXIT_HS_MODE_LATENCY.patch
new file mode 100644
index 0000000000..9ca0f2eab1
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0059-DSS2-DSI-configure-ENTER-EXIT_HS_MODE_LATENCY.patch
@@ -0,0 +1,97 @@
+From 750f7ddc0881834f3400c40e9a59d11f9427cf99 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 29 Apr 2009 17:26:30 +0300
+Subject: [PATCH 59/69] DSS2: DSI: configure ENTER/EXIT_HS_MODE_LATENCY
+
+---
+ drivers/video/omap2/dss/dsi.c |   49 ++++++++++++++++++++++++++++++++--------
+ 1 files changed, 39 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+index d8df353..5225ed6 100644
+--- a/drivers/video/omap2/dss/dsi.c
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -2309,15 +2309,26 @@ static int dsi_proto_config(struct omap_display *display)
+ 	return 0;
+ }
+ 
+-static void dsi_proto_timings(void)
+-{
+-	int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
+-	int tclk_pre, tclk_post;
+-	int ddr_clk_pre, ddr_clk_post;
++static void dsi_proto_timings(struct omap_display *display)
++{
++	unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
++	unsigned tclk_pre, tclk_post;
++	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
++	unsigned ths_trail, ths_exit;
++	unsigned ddr_clk_pre, ddr_clk_post;
++	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
++	unsigned ths_eot;
+ 	u32 r;
+ 
++	r = dsi_read_reg(DSI_DSIPHY_CFG0);
++	ths_prepare = FLD_GET(r, 31, 24);
++	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
++	ths_zero = ths_prepare_ths_zero - ths_prepare;
++	ths_trail = FLD_GET(r, 15, 8);
++	ths_exit = FLD_GET(r, 7, 0);
++
+ 	r = dsi_read_reg(DSI_DSIPHY_CFG1);
+-	tlpx_half = FLD_GET(r, 22, 16);
++	tlpx = FLD_GET(r, 22, 16) * 2;
+ 	tclk_trail = FLD_GET(r, 15, 8);
+ 	tclk_zero = FLD_GET(r, 7, 0);
+ 
+@@ -2329,17 +2340,35 @@ static void dsi_proto_timings(void)
+ 	/* min 60ns + 52*UI */
+ 	tclk_post = ns2ddr(60) + 26;
+ 
+-	ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
+-	ddr_clk_post = (tclk_post + tclk_trail) / 4;
++	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
++			4);
++	ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4);
+ 
+ 	r = dsi_read_reg(DSI_CLK_TIMING);
+ 	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
+ 	r = FLD_MOD(r, ddr_clk_post, 7, 0);
+ 	dsi_write_reg(DSI_CLK_TIMING, r);
+ 
+-	DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
++	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
+ 			ddr_clk_pre,
+ 			ddr_clk_post);
++
++	/* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
++	if (display->hw_config.u.dsi.data1_lane != 0 &&
++			display->hw_config.u.dsi.data2_lane != 0)
++		ths_eot = 2;
++	else
++		ths_eot = 4;
++
++	enter_hs_mode_lat = DIV_ROUND_UP(tlpx + ths_prepare + ths_zero, 4) + 4;
++	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
++
++	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
++		FLD_VAL(exit_hs_mode_lat, 15, 0);
++	dsi_write_reg(DSI_VM_TIMING7, r);
++
++	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
++			enter_hs_mode_lat, exit_hs_mode_lat);
+ }
+ 
+ 
+@@ -3340,7 +3369,7 @@ static int dsi_display_init_dsi(struct omap_display *display)
+ 
+ 	_dsi_print_reset_status();
+ 
+-	dsi_proto_timings();
++	dsi_proto_timings(display);
+ 	dsi_set_lp_clk_divisor();
+ 
+ 	if (1)
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0060-DSS2-Avoid-div-by-zero-when-calculating-required-fc.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0060-DSS2-Avoid-div-by-zero-when-calculating-required-fc.patch
new file mode 100644
index 0000000000..0ff2c7b1a6
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0060-DSS2-Avoid-div-by-zero-when-calculating-required-fc.patch
@@ -0,0 +1,34 @@
+From 233a6e4f4ccaf5827f04ab38c590397755e61ecb Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Mon, 4 May 2009 16:18:30 +0200
+Subject: [PATCH 60/69] DSS2: Avoid div by zero when calculating required fclk
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+When calculating the required fclk rate for five tap filtering if the
+display width and output width are equal div by zero could occur. The
+TRM doesn't actually specify how this case should be handled but for
+now just skip the calculation which would trigger the div by zero.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index f79decb..5fc9457 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1399,7 +1399,7 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
+ 		do_div(tmp, 2 * out_height * ppl);
+ 		fclk = tmp;
+ 
+-		if (height > 2 * out_height) {
++		if (height > 2 * out_height && ppl != out_width) {
+ 			tmp = pclk * (height - 2 * out_height) * out_width;
+ 			do_div(tmp, 2 * out_height * (ppl - out_width));
+ 			fclk = max(fclk, (u32) tmp);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0061-DSS2-VRFB-save-restore-context.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0061-DSS2-VRFB-save-restore-context.patch
new file mode 100644
index 0000000000..a0b694736b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0061-DSS2-VRFB-save-restore-context.patch
@@ -0,0 +1,106 @@
+From e58576ceca922bfe4c793e6f77a873c4ea14f768 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Tue, 5 May 2009 09:05:12 +0300
+Subject: [PATCH 61/69] DSS2: VRFB: save / restore context
+
+The VRFB is part of the SMS and supplied by the core power domain; do
+the context saving while VRFB is configured and restore it along with
+the rest of the domain context.
+
+This patch only implements the restore functionality, but not the
+actual call to the restore. That belongs to PM functionality.
+---
+ arch/arm/plat-omap/include/mach/vrfb.h |    1 +
+ arch/arm/plat-omap/vrfb.c              |   50 ++++++++++++++++++++++++++-----
+ 2 files changed, 43 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
+index 12c7fab..ee6c062 100644
+--- a/arch/arm/plat-omap/include/mach/vrfb.h
++++ b/arch/arm/plat-omap/include/mach/vrfb.h
+@@ -44,5 +44,6 @@ extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
+ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ 		u16 width, u16 height,
+ 		enum omap_color_mode color_mode);
++extern void omap_vrfb_restore_context(void);
+ 
+ #endif /* __VRFB_H */
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+index 2ae0d68..649803e 100644
+--- a/arch/arm/plat-omap/vrfb.c
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -39,6 +39,33 @@
+ /* bitmap of reserved contexts */
+ static unsigned ctx_map;
+ 
++/*
++ * Access to this happens from client drivers or the PM core after wake-up.
++ * For the first case we require locking at the driver level, for the second
++ * we don't need locking, since no drivers will run until after the wake-up
++ * has finished.
++ */
++struct {
++	u32 physical_ba;
++	u32 control;
++	u32 size;
++} vrfb_hw_context[VRFB_NUM_CTXS];
++
++void omap_vrfb_restore_context(void)
++{
++	int i;
++
++	for (i = 0; i < VRFB_NUM_CTXS; i++) {
++		/* Restore only the active contexts */
++		if (!(ctx_map & (1 << i)))
++			continue;
++		omap_writel(vrfb_hw_context[i].control, SMS_ROT_CONTROL(i));
++		omap_writel(vrfb_hw_context[i].size, SMS_ROT_SIZE(i));
++		omap_writel(vrfb_hw_context[i].physical_ba,
++			    SMS_ROT_PHYSICAL_BA(i));
++	}
++}
++
+ void omap_vrfb_adjust_size(u16 *width, u16 *height,
+ 		u8 bytespp)
+ {
+@@ -56,6 +83,8 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ 	u16 vrfb_height;
+ 	u8 ctx = vrfb->context;
+ 	u8 bytespp;
++	u32 size;
++	u32 control;
+ 
+ 	DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
+ 			width, height, bytespp);
+@@ -100,15 +129,20 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ 
+ 	DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
+ 
++	size  = vrfb_width << SMS_IMAGEWIDTH_OFFSET;
++	size |= vrfb_height << SMS_IMAGEHEIGHT_OFFSET;
++
++	control  = pixel_size_exp << SMS_PS_OFFSET;
++	control |= VRFB_PAGE_WIDTH_EXP  << SMS_PW_OFFSET;
++	control |= VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET;
++
++	vrfb_hw_context[ctx].physical_ba = paddr;
++	vrfb_hw_context[ctx].size = size;
++	vrfb_hw_context[ctx].control = control;
++
+ 	omap_writel(paddr, SMS_ROT_PHYSICAL_BA(ctx));
+-	omap_writel((vrfb_width << SMS_IMAGEWIDTH_OFFSET) |
+-			(vrfb_height << SMS_IMAGEHEIGHT_OFFSET),
+-			SMS_ROT_SIZE(ctx));
+-
+-	omap_writel(pixel_size_exp << SMS_PS_OFFSET |
+-			VRFB_PAGE_WIDTH_EXP  << SMS_PW_OFFSET |
+-			VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET,
+-			SMS_ROT_CONTROL(ctx));
++	omap_writel(size, SMS_ROT_SIZE(ctx));
++	omap_writel(control, SMS_ROT_CONTROL(ctx));
+ 
+ 	DBG("vrfb offset pixels %d, %d\n",
+ 			vrfb_width - width, vrfb_height - height);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0062-DSS2-VRAM-Fix-indentation.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0062-DSS2-VRAM-Fix-indentation.patch
new file mode 100644
index 0000000000..8d5f57866d
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0062-DSS2-VRAM-Fix-indentation.patch
@@ -0,0 +1,65 @@
+From 0fb6754f996b5022e1d856fda3d3258382383596 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 6 May 2009 09:03:43 +0300
+Subject: [PATCH 62/69] DSS2: VRAM: Fix indentation
+
+---
+ arch/arm/plat-omap/vram.c |   26 +++++++++++++-------------
+ 1 files changed, 13 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
+index b126a64..f3ce849 100644
+--- a/arch/arm/plat-omap/vram.c
++++ b/arch/arm/plat-omap/vram.c
+@@ -287,35 +287,35 @@ static void _omap_vram_dma_cb(int lch, u16 ch_status, void *data)
+ static int _omap_vram_clear(u32 paddr, unsigned pages)
+ {
+ 	struct completion compl;
+-        unsigned elem_count;
+-        unsigned frame_count;
++	unsigned elem_count;
++	unsigned frame_count;
+ 	int r;
+ 	int lch;
+ 
+ 	init_completion(&compl);
+ 
+-        r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
++	r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
+ 			_omap_vram_dma_cb,
+-                        &compl, &lch);
+-        if (r) {
++			&compl, &lch);
++	if (r) {
+ 		pr_err("VRAM: request_dma failed for memory clear\n");
+ 		return -EBUSY;
+ 	}
+ 
+-        elem_count = pages * PAGE_SIZE / 4;
+-        frame_count = 1;
++	elem_count = pages * PAGE_SIZE / 4;
++	frame_count = 1;
+ 
+-        omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
+-                        elem_count, frame_count,
+-                        OMAP_DMA_SYNC_ELEMENT,
+-                        0, 0);
++	omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
++			elem_count, frame_count,
++			OMAP_DMA_SYNC_ELEMENT,
++			0, 0);
+ 
+-        omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
++	omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
+ 			paddr, 0, 0);
+ 
+ 	omap_set_dma_color_mode(lch, OMAP_DMA_CONSTANT_FILL, 0x000000);
+ 
+-        omap_start_dma(lch);
++	omap_start_dma(lch);
+ 
+ 	if (wait_for_completion_timeout(&compl, msecs_to_jiffies(1000)) == 0) {
+ 		omap_stop_dma(lch);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0063-DSS2-fix-the-usage-of-get_last_off_on_transaction_i.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0063-DSS2-fix-the-usage-of-get_last_off_on_transaction_i.patch
new file mode 100644
index 0000000000..8633921979
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0063-DSS2-fix-the-usage-of-get_last_off_on_transaction_i.patch
@@ -0,0 +1,82 @@
+From 5d3426ae63c27b9405be8179beabe1e095b44a35 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Tue, 5 May 2009 19:00:19 +0200
+Subject: [PATCH 63/69] DSS2: fix the usage of get_last_off_on_transaction_id
+
+The function returns int not unsigned since it can fail. Handle the
+failing case as if the context had been lost. So now:
+
+1. No get_last_off_on_transaction_id func in platform data->
+   never restore the context
+2. Return val < 0 -> force the restore
+3. Return val >= 0 do the restore only if the counter has changed.
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ arch/arm/plat-omap/include/mach/display.h |    2 +-
+ drivers/video/omap2/dss/core.c            |   18 ++++++++++++------
+ 2 files changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+index 45b16ca..31ebb96 100644
+--- a/arch/arm/plat-omap/include/mach/display.h
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -234,7 +234,7 @@ struct device;
+ 
+ /* Board specific data */
+ struct  omap_dss_board_info {
+-	unsigned (*get_last_off_on_transaction_id)(struct device *dev);
++	int (*get_last_off_on_transaction_id)(struct device *dev);
+ 	int (*dsi_power_up)(void);
+ 	void (*dsi_power_down)(void);
+ 	int num_displays;
+diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
+index ae7cd06..6d11b04 100644
+--- a/drivers/video/omap2/dss/core.c
++++ b/drivers/video/omap2/dss/core.c
+@@ -38,7 +38,7 @@
+ 
+ static struct {
+ 	struct platform_device *pdev;
+-	unsigned	ctx_id;
++	int		ctx_id;
+ 
+ 	struct clk      *dss_ick;
+ 	struct clk	*dss1_fck;
+@@ -63,22 +63,28 @@ module_param_named(debug, dss_debug, bool, 0644);
+ #endif
+ 
+ /* CONTEXT */
+-static unsigned dss_get_ctx_id(void)
++static int dss_get_ctx_id(void)
+ {
+ 	struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++	int r;
+ 
+ 	if (!pdata->get_last_off_on_transaction_id)
+ 		return 0;
+-
+-	return pdata->get_last_off_on_transaction_id(&core.pdev->dev);
++	r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
++	if (r < 0) {
++		dev_err(&core.pdev->dev,
++			"getting transaction ID failed, will force context restore\n");
++		r = -1;
++	}
++	return r;
+ }
+ 
+ int dss_need_ctx_restore(void)
+ {
+ 	int id = dss_get_ctx_id();
+ 
+-	if (id != core.ctx_id) {
+-		DSSDBG("ctx id %u -> id %u\n",
++	if (id < 0 || id != core.ctx_id) {
++		DSSDBG("ctx id %d -> id %d\n",
+ 				core.ctx_id, id);
+ 		core.ctx_id = id;
+ 		return 1;
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0064-VRFB-fix-debug-messages.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0064-VRFB-fix-debug-messages.patch
new file mode 100644
index 0000000000..2ba9b1b1a2
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0064-VRFB-fix-debug-messages.patch
@@ -0,0 +1,35 @@
+From 784271e9546844c5e69ec6d8f2fd3713847b6ab2 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Tue, 5 May 2009 11:16:14 +0200
+Subject: [PATCH 64/69] VRFB: fix debug messages
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ arch/arm/plat-omap/vrfb.c |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+index 649803e..289fc8a 100644
+--- a/arch/arm/plat-omap/vrfb.c
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -87,7 +87,7 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ 	u32 control;
+ 
+ 	DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
+-			width, height, bytespp);
++			width, height, color_mode);
+ 
+ 	switch (color_mode) {
+ 	case OMAP_DSS_COLOR_RGB16:
+@@ -127,7 +127,7 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ 	vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
+ 	vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
+ 
+-	DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
++	DBG("vrfb w %u, h %u bytespp %d\n", vrfb_width, vrfb_height, bytespp);
+ 
+ 	size  = vrfb_width << SMS_IMAGEWIDTH_OFFSET;
+ 	size |= vrfb_height << SMS_IMAGEHEIGHT_OFFSET;
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0065-VRFB-add-suspend-resume-functionality.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0065-VRFB-add-suspend-resume-functionality.patch
new file mode 100644
index 0000000000..17f959cb27
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0065-VRFB-add-suspend-resume-functionality.patch
@@ -0,0 +1,216 @@
+From 1269429fe6ddd6e5f15e3b4edb4fc2bcd6fc0410 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Tue, 5 May 2009 11:16:13 +0200
+Subject: [PATCH 65/69] VRFB: add suspend/resume functionality
+
+At the moment the VRFB context is restored at each core power domain
+OFF->ON transition. This is not optimal since the VRFB might be unused
+temporarily for example when the screen is blanked. Add a suspend /
+resume function to mark these unused periods during which we'll avoid
+thea the context restore.
+
+Use atomic bitops for ctx_map for consistency.
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ arch/arm/plat-omap/include/mach/vrfb.h   |    2 +
+ arch/arm/plat-omap/vrfb.c                |   75 ++++++++++++++++++++++++-----
+ drivers/video/omap2/omapfb/omapfb-main.c |   28 +++++++++++
+ 3 files changed, 92 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
+index ee6c062..9647d82 100644
+--- a/arch/arm/plat-omap/include/mach/vrfb.h
++++ b/arch/arm/plat-omap/include/mach/vrfb.h
+@@ -39,6 +39,8 @@ struct vrfb
+ 
+ extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
+ extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_suspend_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_resume_ctx(struct vrfb *vrfb);
+ extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
+ 		u8 bytespp);
+ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+index 289fc8a..29f04e2 100644
+--- a/arch/arm/plat-omap/vrfb.c
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -1,7 +1,9 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/ioport.h>
++
+ #include <asm/io.h>
++#include <asm/bitops.h>
+ 
+ #include <mach/io.h>
+ #include <mach/vrfb.h>
+@@ -37,7 +39,9 @@
+ 
+ #define VRFB_NUM_CTXS 12
+ /* bitmap of reserved contexts */
+-static unsigned ctx_map;
++static unsigned long ctx_map;
++/* bitmap of contexts for which we have to keep the HW context valid */
++static unsigned long ctx_map_active;
+ 
+ /*
+  * Access to this happens from client drivers or the PM core after wake-up.
+@@ -51,18 +55,23 @@ struct {
+ 	u32 size;
+ } vrfb_hw_context[VRFB_NUM_CTXS];
+ 
++static void inline restore_hw_context(int ctx)
++{
++	omap_writel(vrfb_hw_context[ctx].control, SMS_ROT_CONTROL(ctx));
++	omap_writel(vrfb_hw_context[ctx].size, SMS_ROT_SIZE(ctx));
++	omap_writel(vrfb_hw_context[ctx].physical_ba, SMS_ROT_PHYSICAL_BA(ctx));
++}
++
+ void omap_vrfb_restore_context(void)
+ {
+ 	int i;
++	unsigned long map = ctx_map_active;
+ 
+-	for (i = 0; i < VRFB_NUM_CTXS; i++) {
+-		/* Restore only the active contexts */
+-		if (!(ctx_map & (1 << i)))
+-			continue;
+-		omap_writel(vrfb_hw_context[i].control, SMS_ROT_CONTROL(i));
+-		omap_writel(vrfb_hw_context[i].size, SMS_ROT_SIZE(i));
+-		omap_writel(vrfb_hw_context[i].physical_ba,
+-			    SMS_ROT_PHYSICAL_BA(i));
++	for (i = ffs(map); i; i = ffs(map)) {
++		/* i=1..32 */
++		i--;
++		map &= ~(1 << i);
++		restore_hw_context(i);
+ 	}
+ }
+ 
+@@ -156,13 +165,20 @@ EXPORT_SYMBOL(omap_vrfb_setup);
+ void omap_vrfb_release_ctx(struct vrfb *vrfb)
+ {
+ 	int rot;
++	int ctx = vrfb->context;
+ 
+-	if (vrfb->context == 0xff)
++	if (ctx == 0xff)
+ 		return;
+ 
+-	DBG("release ctx %d\n", vrfb->context);
++	DBG("release ctx %d\n", ctx);
+ 
+-	ctx_map &= ~(1 << vrfb->context);
++	if (!(ctx_map & (1 << ctx))) {
++		BUG();
++		return;
++	}
++	WARN_ON(!(ctx_map_active & (1 << ctx)));
++	clear_bit(ctx, &ctx_map_active);
++	clear_bit(ctx, &ctx_map);
+ 
+ 	for (rot = 0; rot < 4; ++rot) {
+ 		if(vrfb->paddr[rot]) {
+@@ -194,7 +210,9 @@ int omap_vrfb_request_ctx(struct vrfb *vrfb)
+ 
+ 	DBG("found free ctx %d\n", ctx);
+ 
+-	ctx_map |= 1 << ctx;
++	set_bit(ctx, &ctx_map);
++	WARN_ON(ctx_map_active & (1 << ctx));
++	set_bit(ctx, &ctx_map_active);
+ 
+ 	memset(vrfb, 0, sizeof(*vrfb));
+ 
+@@ -219,3 +237,34 @@ int omap_vrfb_request_ctx(struct vrfb *vrfb)
+ }
+ EXPORT_SYMBOL(omap_vrfb_request_ctx);
+ 
++void omap_vrfb_suspend_ctx(struct vrfb *vrfb)
++{
++	DBG("suspend ctx %d\n", vrfb->context);
++	if (vrfb->context >= VRFB_NUM_CTXS ||
++	    (!(1 << vrfb->context) & ctx_map_active)) {
++		BUG();
++		return;
++	}
++	clear_bit(vrfb->context, &ctx_map_active);
++}
++EXPORT_SYMBOL(omap_vrfb_suspend_ctx);
++
++void omap_vrfb_resume_ctx(struct vrfb *vrfb)
++{
++	DBG("resume ctx %d\n", vrfb->context);
++	if (vrfb->context >= VRFB_NUM_CTXS ||
++	    ((1 << vrfb->context) & ctx_map_active)) {
++		BUG();
++		return;
++	}
++	/*
++	 * omap_vrfb_restore_context is normally called by the core domain
++	 * save / restore logic, but since this VRFB context was suspended
++	 * those calls didn't actually restore the context and now we might
++	 * have an invalid context. Do an explicit restore here.
++	 */
++	restore_hw_context(vrfb->context);
++	set_bit(vrfb->context, &ctx_map_active);
++}
++EXPORT_SYMBOL(omap_vrfb_resume_ctx);
++
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index 76e7c6c..4bb74b7 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -1036,6 +1036,30 @@ static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
+ 	return 0;
+ }
+ 
++static void omapfb_vrfb_suspend_all(struct omapfb2_device *fbdev)
++{
++	int i;
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++		if (ofbi->region.vrfb.vaddr[0])
++			omap_vrfb_suspend_ctx(&ofbi->region.vrfb);
++	}
++}
++
++static void omapfb_vrfb_resume_all(struct omapfb2_device *fbdev)
++{
++	int i;
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++		if (ofbi->region.vrfb.vaddr[0])
++			omap_vrfb_resume_ctx(&ofbi->region.vrfb);
++	}
++}
++
+ static int omapfb_blank(int blank, struct fb_info *fbi)
+ {
+ 	struct omapfb_info *ofbi = FB2OFB(fbi);
+@@ -1051,6 +1075,8 @@ static int omapfb_blank(int blank, struct fb_info *fbi)
+ 		if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
+ 			goto exit;
+ 
++		omapfb_vrfb_resume_all(fbdev);
++
+ 		if (display->resume)
+ 			r = display->resume(display);
+ 
+@@ -1073,6 +1099,8 @@ static int omapfb_blank(int blank, struct fb_info *fbi)
+ 		if (display->suspend)
+ 			r = display->suspend(display);
+ 
++		omapfb_vrfb_suspend_all(fbdev);
++
+ 		break;
+ 
+ 	default:
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0066-DSS2-DSI-tune-the-timings-to-be-more-relaxed.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0066-DSS2-DSI-tune-the-timings-to-be-more-relaxed.patch
new file mode 100644
index 0000000000..a3af90d959
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0066-DSS2-DSI-tune-the-timings-to-be-more-relaxed.patch
@@ -0,0 +1,92 @@
+From 0201b40018d9e264f8c4ea7871223c94e0de61b1 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 7 May 2009 14:32:55 +0300
+Subject: [PATCH 66/69] DSS2: DSI: tune the timings to be more relaxed
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/dss/dsi.c |   37 +++++++++++++++++++++----------------
+ 1 files changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+index 5225ed6..67ecfcf 100644
+--- a/drivers/video/omap2/dss/dsi.c
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -1396,28 +1396,28 @@ static void dsi_complexio_timings(void)
+ 	/* 1 * DDR_CLK = 2 * UI */
+ 
+ 	/* min 40ns + 4*UI	max 85ns + 6*UI */
+-	ths_prepare = ns2ddr(59) + 2;
++	ths_prepare = ns2ddr(70) + 2;
+ 
+ 	/* min 145ns + 10*UI */
+-	ths_prepare_ths_zero = ns2ddr(145) + 5;
++	ths_prepare_ths_zero = ns2ddr(175) + 2;
+ 
+ 	/* min max(8*UI, 60ns+4*UI) */
+-	ths_trail = max((unsigned)4, ns2ddr(60) + 2);
++	ths_trail = ns2ddr(60) + 5;
+ 
+ 	/* min 100ns */
+-	ths_exit = ns2ddr(100);
++	ths_exit = ns2ddr(145);
+ 
+ 	/* tlpx min 50n */
+ 	tlpx_half = ns2ddr(25);
+ 
+ 	/* min 60ns */
+-	tclk_trail = ns2ddr(60);
++	tclk_trail = ns2ddr(60) + 2;
+ 
+ 	/* min 38ns, max 95ns */
+-	tclk_prepare = ns2ddr(38);
++	tclk_prepare = ns2ddr(65);
+ 
+ 	/* min tclk-prepare + tclk-zero = 300ns */
+-	tclk_zero = ns2ddr(300 - 38);
++	tclk_zero = ns2ddr(260);
+ 
+ 	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
+ 		ths_prepare, ddr2ns(ths_prepare),
+@@ -2340,9 +2340,19 @@ static void dsi_proto_timings(struct omap_display *display)
+ 	/* min 60ns + 52*UI */
+ 	tclk_post = ns2ddr(60) + 26;
+ 
++	/* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
++	if (display->hw_config.u.dsi.data1_lane != 0 &&
++			display->hw_config.u.dsi.data2_lane != 0)
++		ths_eot = 2;
++	else
++		ths_eot = 4;
++
+ 	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
+ 			4);
+-	ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4);
++	ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4) + ths_eot;
++
++	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
++	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
+ 
+ 	r = dsi_read_reg(DSI_CLK_TIMING);
+ 	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
+@@ -2353,14 +2363,9 @@ static void dsi_proto_timings(struct omap_display *display)
+ 			ddr_clk_pre,
+ 			ddr_clk_post);
+ 
+-	/* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
+-	if (display->hw_config.u.dsi.data1_lane != 0 &&
+-			display->hw_config.u.dsi.data2_lane != 0)
+-		ths_eot = 2;
+-	else
+-		ths_eot = 4;
+-
+-	enter_hs_mode_lat = DIV_ROUND_UP(tlpx + ths_prepare + ths_zero, 4) + 4;
++	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
++		DIV_ROUND_UP(ths_prepare, 4) +
++		DIV_ROUND_UP(ths_zero + 3, 4);
+ 	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
+ 
+ 	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0067-DSS2-VRFB-don-t-WARN-when-releasing-inactive-ctx.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0067-DSS2-VRFB-don-t-WARN-when-releasing-inactive-ctx.patch
new file mode 100644
index 0000000000..911fe79bfa
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0067-DSS2-VRFB-don-t-WARN-when-releasing-inactive-ctx.patch
@@ -0,0 +1,29 @@
+From c474849d7aff57d578c639f63a9c3cbdec0501dd Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@nokia.com>
+Date: Mon, 11 May 2009 15:15:52 +0200
+Subject: [PATCH 67/69] DSS2: VRFB: don't WARN when releasing inactive ctx
+
+Releasing an inactive context is valid, it can happen when
+the application first blanks the screen then frees the
+framebuffer.
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+ arch/arm/plat-omap/vrfb.c |    1 -
+ 1 files changed, 0 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+index 29f04e2..34395c2 100644
+--- a/arch/arm/plat-omap/vrfb.c
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -176,7 +176,6 @@ void omap_vrfb_release_ctx(struct vrfb *vrfb)
+ 		BUG();
+ 		return;
+ 	}
+-	WARN_ON(!(ctx_map_active & (1 << ctx)));
+ 	clear_bit(ctx, &ctx_map_active);
+ 	clear_bit(ctx, &ctx_map);
+ 
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0068-DSS2-Swap-field-offset-values-w-VRFB-rotation.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0068-DSS2-Swap-field-offset-values-w-VRFB-rotation.patch
new file mode 100644
index 0000000000..fba2ebd5db
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0068-DSS2-Swap-field-offset-values-w-VRFB-rotation.patch
@@ -0,0 +1,65 @@
+From 0db37fa025f0eac64f9fdad49e310d7660f48944 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
+Date: Tue, 12 May 2009 14:38:05 +0200
+Subject: [PATCH 68/69] DSS2: Swap field offset values w/ VRFB rotation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+The field 0 and field 1 offset values were still incorrect when VRFB
+rotation is used. Swap them to put the fields into proper order.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c |   17 +++++++++++------
+ 1 files changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index 5fc9457..b0e4960 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -1182,6 +1182,11 @@ static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
+ 
+ 	DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
+ 			width, height);
++
++	/*
++	 * field 0 = even field = bottom field
++	 * field 1 = odd field = top field
++	 */
+ 	switch (rotation + mirror * 4) {
+ 	case 0:
+ 	case 2:
+@@ -1194,11 +1199,11 @@ static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
+ 			width = width >> 1;
+ 	case 1:
+ 	case 3:
+-		*offset0 = 0;
++		*offset1 = 0;
+ 		if (fieldmode)
+-			*offset1 = screen_width * ps;
++			*offset0 = screen_width * ps;
+ 		else
+-			*offset1 = 0;
++			*offset0 = 0;
+ 
+ 		*row_inc = pixinc(1 + (screen_width - width) +
+ 				(fieldmode ? screen_width : 0),
+@@ -1216,11 +1221,11 @@ static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
+ 			width = width >> 1;
+ 	case 5:
+ 	case 7:
+-		*offset0 = 0;
++		*offset1 = 0;
+ 		if (fieldmode)
+-			*offset1 = screen_width * ps;
++			*offset0 = screen_width * ps;
+ 		else
+-			*offset1 = 0;
++			*offset0 = 0;
+ 		*row_inc = pixinc(1 - (screen_width + width) -
+ 				(fieldmode ? screen_width : 0),
+ 				ps);
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0069-DSS2-OMAP3EVM-Added-DSI-powerup-and-powerdown-func.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0069-DSS2-OMAP3EVM-Added-DSI-powerup-and-powerdown-func.patch
new file mode 100644
index 0000000000..c637c48602
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0069-DSS2-OMAP3EVM-Added-DSI-powerup-and-powerdown-func.patch
@@ -0,0 +1,125 @@
+From b06406f3e5c3958f69185314c969f7c1a3265f71 Mon Sep 17 00:00:00 2001
+From: Hardik Shah <hardik.shah@ti.com>
+Date: Thu, 14 May 2009 15:04:17 +0530
+Subject: [PATCH 69/69] DSS2: OMAP3EVM: Added DSI powerup and powerdown functions
+
+Copied fom 3430sdp implementation.
+
+Signed-off-by: Hardik Shah <hardik.shah@ti.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c |   62 +++++++++++++++++++++-------------
+ 1 files changed, 38 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 6f5a866..57c4fc7 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -237,6 +237,38 @@ static int __init omap3_evm_i2c_init(void)
+ static int lcd_enabled;
+ static int dvi_enabled;
+ 
++static void enable_vpll2(int enable)
++{
++	u8 ded_val, grp_val;
++
++	if (enable) {
++		ded_val = ENABLE_VPLL2_DEDICATED;
++		grp_val = ENABLE_VPLL2_DEV_GRP;
++	} else {
++		ded_val = 0;
++		grp_val = 0;
++	}
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ded_val, TWL4030_VPLL2_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			grp_val, TWL4030_VPLL2_DEV_GRP);
++}
++
++static int omap3evm_dsi_power_up(void)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0)
++		enable_vpll2(1);
++	return 0;
++}
++
++static void omap3evm_dsi_power_down(void)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0)
++		enable_vpll2(0);
++}
++
++
+ static void __init omap3_evm_display_init(void)
+ {
+ 	int r;
+@@ -306,12 +338,7 @@ static int omap3_evm_panel_enable_lcd(struct omap_display *display)
+ 		printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
+ 		return -EINVAL;
+ 	}
+-	if (omap_rev() > OMAP3430_REV_ES1_0) {
+-		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+-			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
+-		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+-			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
+-	}
++	omap3evm_dsi_power_up();
+ 	gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
+ 	lcd_enabled = 1;
+ 	return 0;
+@@ -319,12 +346,7 @@ static int omap3_evm_panel_enable_lcd(struct omap_display *display)
+ 
+ static void omap3_evm_panel_disable_lcd(struct omap_display *display)
+ {
+-	if (omap_rev() > OMAP3430_REV_ES1_0) {
+-		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
+-				TWL4030_VPLL2_DEDICATED);
+-		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
+-				TWL4030_VPLL2_DEV_GRP);
+-	}
++	omap3evm_dsi_power_down();
+ 	gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
+ 	lcd_enabled = 0;
+ }
+@@ -370,13 +392,8 @@ static int omap3_evm_panel_enable_dvi(struct omap_display *display)
+ 		printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
+ 		return -EINVAL;
+ 	}
+-	if (omap_rev() > OMAP3430_REV_ES1_0) {
+-		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+-			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
+-		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+-			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
+-	}
+ 
++	omap3evm_dsi_power_up();
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
+ 			TWL4030_GPIODATA_IN3);
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
+@@ -388,13 +405,8 @@ static int omap3_evm_panel_enable_dvi(struct omap_display *display)
+ 
+ static void omap3_evm_panel_disable_dvi(struct omap_display *display)
+ {
+-	if (omap_rev() > OMAP3430_REV_ES1_0) {
+-		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
+-				TWL4030_VPLL2_DEDICATED);
+-		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
+-				TWL4030_VPLL2_DEV_GRP);
+-	}
+ 
++	omap3evm_dsi_power_down();
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
+ 			TWL4030_GPIODATA_IN3);
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
+@@ -413,6 +425,8 @@ static struct omap_dss_display_config omap3_evm_display_data_dvi = {
+ };
+ 
+ static struct omap_dss_board_info omap3_evm_dss_data = {
++	.dsi_power_up = omap3evm_dsi_power_up,
++	.dsi_power_down = omap3evm_dsi_power_down,
+ 	.num_displays = 3,
+ 	.displays = {
+ 		&omap3_evm_display_data,
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0070-DSS2-fix-irq1.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0070-DSS2-fix-irq1.diff
new file mode 100644
index 0000000000..8f384dfe2d
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0070-DSS2-fix-irq1.diff
@@ -0,0 +1,221 @@
+From 093988f36ffcb0201927f8b452e546e1141aa0fa Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Sat, 23 May 2009 15:00:21 +0000
+Subject: DSS2: DISPC: fix irq handling locking
+
+---
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index b0e4960..b3685b2 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -154,23 +154,20 @@ static struct {
+ 
+ 	struct clk	*dpll4_m4_ck;
+ 
+-	spinlock_t	irq_lock;
+-
+ 	unsigned long	cache_req_pck;
+ 	unsigned long	cache_prate;
+ 	struct dispc_clock_info cache_cinfo;
+ 
+-	u32		irq_error_mask;
++	spinlock_t irq_lock;
++	u32 irq_error_mask;
+ 	struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
+-
+-	spinlock_t error_lock;
+ 	u32 error_irqs;
+ 	struct work_struct error_work;
+ 
+ 	u32		ctx[DISPC_SZ_REGS / sizeof(u32)];
+ } dispc;
+ 
+-static void omap_dispc_set_irqs(void);
++static void _omap_dispc_set_irqs(void);
+ 
+ static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
+ {
+@@ -1691,10 +1688,13 @@ void dispc_enable_digit_out(bool enable)
+ 	}
+ 
+ 	if (enable) {
++		unsigned long flags;
+ 		/* When we enable digit output, we'll get an extra digit
+ 		 * sync lost interrupt, that we need to ignore */
++		spin_lock_irqsave(&dispc.irq_lock, flags);
+ 		dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
+-		omap_dispc_set_irqs();
++		_omap_dispc_set_irqs();
++		spin_unlock_irqrestore(&dispc.irq_lock, flags);
+ 	}
+ 
+ 	/* When we disable digit output, we need to wait until fields are done.
+@@ -1728,9 +1728,12 @@ void dispc_enable_digit_out(bool enable)
+ 		DSSERR("failed to unregister EVSYNC isr\n");
+ 
+ 	if (enable) {
++		unsigned long flags;
++		spin_lock_irqsave(&dispc.irq_lock, flags);
+ 		dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
+ 		dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
+-		omap_dispc_set_irqs();
++		_omap_dispc_set_irqs();
++		spin_unlock_irqrestore(&dispc.irq_lock, flags);
+ 	}
+ 
+ 	enable_clocks(0);
+@@ -2508,14 +2511,14 @@ int dispc_get_clock_div(struct dispc_clock_info *cinfo)
+ 	return 0;
+ }
+ 
+-static void omap_dispc_set_irqs(void)
++/* dispc.irq_lock has to be locked by the caller */
++static void _omap_dispc_set_irqs(void)
+ {
+-	unsigned long flags;
+-	u32 mask = dispc.irq_error_mask;
++	u32 mask;
+ 	int i;
+ 	struct omap_dispc_isr_data *isr_data;
+ 
+-	spin_lock_irqsave(&dispc.irq_lock, flags);
++	mask = dispc.irq_error_mask;
+ 
+ 	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
+ 		isr_data = &dispc.registered_isr[i];
+@@ -2528,9 +2531,8 @@ static void omap_dispc_set_irqs(void)
+ 
+ 	enable_clocks(1);
+ 	dispc_write_reg(DISPC_IRQENABLE, mask);
+-	enable_clocks(0);
+ 
+-	spin_unlock_irqrestore(&dispc.irq_lock, flags);
++	enable_clocks(0);
+ }
+ 
+ int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
+@@ -2571,11 +2573,14 @@ int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
+ 
+ 		break;
+ 	}
+-err:
++
++	_omap_dispc_set_irqs();
++
+ 	spin_unlock_irqrestore(&dispc.irq_lock, flags);
+ 
+-	if (ret == 0)
+-		omap_dispc_set_irqs();
++	return 0;
++err:
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
+ 
+ 	return ret;
+ }
+@@ -2606,10 +2611,10 @@ int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
+ 		break;
+ 	}
+ 
+-	spin_unlock_irqrestore(&dispc.irq_lock, flags);
+-
+ 	if (ret == 0)
+-		omap_dispc_set_irqs();
++		_omap_dispc_set_irqs();
++
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
+ 
+ 	return ret;
+ }
+@@ -2645,11 +2650,15 @@ static void print_irq_status(u32 status)
+ void dispc_irq_handler(void)
+ {
+ 	int i;
+-	u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
++	u32 irqstatus;
+ 	u32 handledirqs = 0;
+ 	u32 unhandled_errors;
+ 	struct omap_dispc_isr_data *isr_data;
+ 
++	spin_lock(&dispc.irq_lock);
++
++	irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
++
+ #ifdef DEBUG
+ 	if (dss_debug)
+ 		print_irq_status(irqstatus);
+@@ -2673,15 +2682,15 @@ void dispc_irq_handler(void)
+ 	unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
+ 
+ 	if (unhandled_errors) {
+-		spin_lock(&dispc.error_lock);
+ 		dispc.error_irqs |= unhandled_errors;
+-		spin_unlock(&dispc.error_lock);
+ 
+ 		dispc.irq_error_mask &= ~unhandled_errors;
+-		omap_dispc_set_irqs();
++		_omap_dispc_set_irqs();
+ 
+ 		schedule_work(&dispc.error_work);
+ 	}
++
++	spin_unlock(&dispc.irq_lock);
+ }
+ 
+ static void dispc_error_worker(struct work_struct *work)
+@@ -2690,10 +2699,10 @@ static void dispc_error_worker(struct work_struct *work)
+ 	u32 errors;
+ 	unsigned long flags;
+ 
+-	spin_lock_irqsave(&dispc.error_lock, flags);
++	spin_lock_irqsave(&dispc.irq_lock, flags);
+ 	errors = dispc.error_irqs;
+ 	dispc.error_irqs = 0;
+-	spin_unlock_irqrestore(&dispc.error_lock, flags);
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
+ 
+ 	if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
+ 		DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
+@@ -2836,8 +2845,10 @@ static void dispc_error_worker(struct work_struct *work)
+ 		}
+ 	}
+ 
++	spin_lock_irqsave(&dispc.irq_lock, flags);
+ 	dispc.irq_error_mask |= errors;
+-	omap_dispc_set_irqs();
++	_omap_dispc_set_irqs();
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
+ }
+ 
+ int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
+@@ -2921,6 +2932,10 @@ void dispc_fake_vsync_irq(void)
+ 
+ static void _omap_dispc_initialize_irq(void)
+ {
++	unsigned long flags;
++
++	spin_lock_irqsave(&dispc.irq_lock, flags);
++
+ 	memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
+ 
+ 	dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
+@@ -2929,7 +2944,9 @@ static void _omap_dispc_initialize_irq(void)
+ 	 * so clear it */
+ 	dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
+ 
+-	omap_dispc_set_irqs();
++	_omap_dispc_set_irqs();
++
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
+ }
+ 
+ void dispc_enable_sidle(void)
+@@ -2970,7 +2987,6 @@ int dispc_init(void)
+ 	u32 rev;
+ 
+ 	spin_lock_init(&dispc.irq_lock);
+-	spin_lock_init(&dispc.error_lock);
+ 
+ 	INIT_WORK(&dispc.error_work, dispc_error_worker);
+ 
+--
+cgit v0.8.2.1-10-g45e7
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0071-DSS2-fix-irq2.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0071-DSS2-fix-irq2.diff
new file mode 100644
index 0000000000..cb8aaf1a28
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/dss2/0071-DSS2-fix-irq2.diff
@@ -0,0 +1,35 @@
+From 8af2f6550d6971875e4c5d3f93982f86f4bcf216 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Sat, 23 May 2009 15:00:00 +0000
+Subject: DSS2: DISPC: clear irqstatus for newly enabled irqs
+
+This fixes the problem that when requesting a new irq
+we could get the isr called too early in case irqstatus
+already had that irq flag on.
+---
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+index b3685b2..2471cfe 100644
+--- a/drivers/video/omap2/dss/dispc.c
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -2515,6 +2515,7 @@ int dispc_get_clock_div(struct dispc_clock_info *cinfo)
+ static void _omap_dispc_set_irqs(void)
+ {
+ 	u32 mask;
++	u32 old_mask;
+ 	int i;
+ 	struct omap_dispc_isr_data *isr_data;
+ 
+@@ -2530,6 +2531,11 @@ static void _omap_dispc_set_irqs(void)
+ 	}
+ 
+ 	enable_clocks(1);
++
++	old_mask = dispc_read_reg(DISPC_IRQENABLE);
++	/* clear the irqstatus for newly enabled irqs */
++	dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
++
+ 	dispc_write_reg(DISPC_IRQENABLE, mask);
+ 
+ 	enable_clocks(0);
+--
+cgit v0.8.2.1-10-g45e7
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/ehci.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/ehci.patch
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/ehci.patch
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/evm-mcspi-ts.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/evm-mcspi-ts.diff
new file mode 100644
index 0000000000..64d797cf96
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/evm-mcspi-ts.diff
@@ -0,0 +1,132 @@
+From linux-omap-owner@vger.kernel.org Sun Nov 02 21:08:25 2008
+Received: from localhost
+	([127.0.0.1] helo=dominion ident=koen)
+	by dominion.dominion.void with esmtp (Exim 4.69)
+	(envelope-from <linux-omap-owner@vger.kernel.org>)
+	id 1KwjFJ-0008Hg-0T
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+        (version=TLSv1/SSLv3 cipher=RC4-MD5);
+        Sun, 02 Nov 2008 11:56:31 -0800 (PST)
+From: Grazvydas Ignotas <notasas@gmail.com>
+To: linux-omap@vger.kernel.org
+Cc: Grazvydas Ignotas <notasas@gmail.com>
+Subject: Re: omap3evm LCD red-tint workaround
+Date: 	Sun,  2 Nov 2008 21:56:19 +0200
+Message-Id: <1225655779-18934-1-git-send-email-notasas@gmail.com>
+X-Mailer: git-send-email 1.5.4.3
+In-Reply-To: <57322719-1A5A-45DC-9846-5C0A3B6EF346@student.utwente.nl>
+References: <57322719-1A5A-45DC-9846-5C0A3B6EF346@student.utwente.nl>
+Sender: linux-omap-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-omap.vger.kernel.org>
+X-Mailing-List: 	linux-omap@vger.kernel.org
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+X-UTwente-MailScanner: Found to be clean
+X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org
+X-Spam-Status: No
+X-OriginalArrivalTime: 02 Nov 2008 19:57:16.0876 (UTC) FILETIME=[34FBA0C0:01C93D25]
+
+> PS: TS is still unusable with the 16x16 pixel resolution
+This is also the case for Pandora. The patch below fixes the problem,
+but as I have no other boards to test this on, I haven't sent it.
+See if it helps you.
+
+
+From 91f3af26bbf751b846e6265d86387e81be7c1364 Mon Sep 17 00:00:00 2001
+From: Grazvydas Ignotas <notasas@gmail.com>
+Date: Tue, 28 Oct 2008 22:01:42 +0200
+Subject: [PATCH] OMAP3: fix McSPI transfers
+
+Currently on OMAP3 if both write and read is set up for a transfer,
+the first byte returned on read is corrupted. Work around this by
+disabling channel between reads and writes, instead of transfers.
+---
+ drivers/spi/omap2_mcspi.c |    7 ++++---
+ 1 files changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
+index 454a271..4890b6c 100644
+--- a/drivers/spi/omap2_mcspi.c
++++ b/drivers/spi/omap2_mcspi.c
+@@ -710,7 +710,6 @@ static void omap2_mcspi_work(struct work_struct *work)
+ 		spi = m->spi;
+ 		cs = spi->controller_state;
+ 
+-		omap2_mcspi_set_enable(spi, 1);
+ 		list_for_each_entry(t, &m->transfers, transfer_list) {
+ 			if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
+ 				status = -EINVAL;
+@@ -741,6 +740,8 @@ static void omap2_mcspi_work(struct work_struct *work)
+ 			if (t->len) {
+ 				unsigned	count;
+ 
++				omap2_mcspi_set_enable(spi, 1);
++
+ 				/* RX_ONLY mode needs dummy data in TX reg */
+ 				if (t->tx_buf == NULL)
+ 					__raw_writel(0, cs->base
+@@ -752,6 +753,8 @@ static void omap2_mcspi_work(struct work_struct *work)
+ 					count = omap2_mcspi_txrx_pio(spi, t);
+ 				m->actual_length += count;
+ 
++				omap2_mcspi_set_enable(spi, 0);
++
+ 				if (count != t->len) {
+ 					status = -EIO;
+ 					break;
+@@ -777,8 +780,6 @@ static void omap2_mcspi_work(struct work_struct *work)
+ 		if (cs_active)
+ 			omap2_mcspi_force_cs(spi, 0);
+ 
+-		omap2_mcspi_set_enable(spi, 0);
+-
+ 		m->status = status;
+ 		m->complete(m->context);
+ 
+-- 
+1.5.4.3
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/fix-audio-capture.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/fix-audio-capture.patch
new file mode 100644
index 0000000000..c5ff914757
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/fix-audio-capture.patch
@@ -0,0 +1,16 @@
+diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
+index ee2f0d3..8b4aafb 100644
+--- a/sound/soc/codecs/twl4030.c
++++ b/sound/soc/codecs/twl4030.c
+@@ -45,8 +45,8 @@ static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
+ 	0xc3, /* REG_OPTION		(0x2)	*/
+ 	0x00, /* REG_UNKNOWN		(0x3)	*/
+ 	0x00, /* REG_MICBIAS_CTL	(0x4)	*/
+-	0x20, /* REG_ANAMICL		(0x5)	*/
+-	0x00, /* REG_ANAMICR		(0x6)	*/
++	0x34, /* REG_ANAMICL		(0x5)	*/
++	0x14, /* REG_ANAMICR		(0x6)	*/
+ 	0x00, /* REG_AVADC_CTL		(0x7)	*/
+ 	0x00, /* REG_ADCMICSEL		(0x8)	*/
+ 	0x00, /* REG_DIGMIXING		(0x9)	*/
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/fix-install.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/fix-install.patch
new file mode 100644
index 0000000000..46bc25a50b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/fix-install.patch
@@ -0,0 +1,23 @@
+From: Steve Sakoman <steve@sakoman.com>
+Date: Mon, 18 Aug 2008 16:07:31 +0000 (-0700)
+Subject: scripts/Makefile.fwinst: add missing space when setting mode in cmd_install
+X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=f039944bdd491cde7327133e9976881d3133ae70
+
+scripts/Makefile.fwinst: add missing space when setting mode in cmd_install
+
+This was causing build failures on some machines
+---
+
+diff --git a/scripts/Makefile.fwinst b/scripts/Makefile.fwinst
+index 6bf8e87..fb20532 100644
+--- a/scripts/Makefile.fwinst
++++ b/scripts/Makefile.fwinst
+@@ -37,7 +37,7 @@ install-all-dirs: $(installed-fw-dirs)
+ 	@true
+ 
+ quiet_cmd_install = INSTALL $(subst $(srctree)/,,$@)
+-      cmd_install = $(INSTALL) -m0644 $< $@
++      cmd_install = $(INSTALL) -m 0644 $< $@
+ 
+ $(installed-fw-dirs):
+ 	$(call cmd,mkdir)
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/fix-unaligned-access.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/fix-unaligned-access.diff
new file mode 100644
index 0000000000..c82090f54a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/fix-unaligned-access.diff
@@ -0,0 +1,41 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Sat, 28 Mar 2009 12:54:25 +0000 (+0000)
+Subject: NSM: Fix unaligned accesses in nsm_init_private()
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=8f2bd6fdde1ebfef57f65b6cf29b29008c23d297
+
+NSM: Fix unaligned accesses in nsm_init_private()
+
+This fixes unaligned accesses in nsm_init_private() when
+creating nlm_reboot keys.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/fs/lockd/mon.c b/fs/lockd/mon.c
+index 5e2c4d5..6d5d4a4 100644
+--- a/fs/lockd/mon.c
++++ b/fs/lockd/mon.c
+@@ -16,6 +16,8 @@
+ #include <linux/sunrpc/svc.h>
+ #include <linux/lockd/lockd.h>
+ 
++#include <asm/unaligned.h>
++
+ #define NLMDBG_FACILITY		NLMDBG_MONITOR
+ #define NSM_PROGRAM		100024
+ #define NSM_VERSION		1
+@@ -274,10 +276,12 @@ static void nsm_init_private(struct nsm_handle *nsm)
+ {
+ 	u64 *p = (u64 *)&nsm->sm_priv.data;
+ 	struct timespec ts;
++	s64 ns;
+ 
+ 	ktime_get_ts(&ts);
+-	*p++ = timespec_to_ns(&ts);
+-	*p = (unsigned long)nsm;
++	ns = timespec_to_ns(&ts);
++	put_unaligned(ns, p);
++	put_unaligned((unsigned long)nsm, p + 1);
+ }
+ 
+ static struct nsm_handle *nsm_create_handle(const struct sockaddr *sap,
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0001-omap-iommu-tlb-and-pagetable-primitives.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0001-omap-iommu-tlb-and-pagetable-primitives.patch
new file mode 100644
index 0000000000..c2c9bc2b62
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0001-omap-iommu-tlb-and-pagetable-primitives.patch
@@ -0,0 +1,1226 @@
+From a62a047ed02162573e4bece18ecf8bdd66ccd06b Mon Sep 17 00:00:00 2001
+From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+Date: Mon, 26 Jan 2009 15:13:40 +0200
+Subject: [PATCH] omap iommu: tlb and pagetable primitives
+
+This patch provides:
+
+- iotlb_*()     : iommu tlb operations
+- iopgtable_*() : iommu pagetable(twl) operations
+- iommu_*()     : the other generic operations
+
+and the entry points to register and acquire iommu object.
+
+Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+---
+ arch/arm/plat-omap/include/mach/iommu.h |  157 +++++
+ arch/arm/plat-omap/iommu.c              |  953 +++++++++++++++++++++++++++++++
+ arch/arm/plat-omap/iopgtable.h          |   72 +++
+ 3 files changed, 1182 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/plat-omap/include/mach/iommu.h
+ create mode 100644 arch/arm/plat-omap/iommu.c
+ create mode 100644 arch/arm/plat-omap/iopgtable.h
+
+diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h
+new file mode 100644
+index 0000000..ef04d7a
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/iommu.h
+@@ -0,0 +1,157 @@
++/*
++ * omap iommu: main structures
++ *
++ * Copyright (C) 2008-2009 Nokia Corporation
++ *
++ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __MACH_IOMMU_H
++#define __MACH_IOMMU_H
++
++struct iotlb_entry {
++	u32 da;
++	u32 pa;
++	u32 pgsz, prsvd, valid;
++	union {
++		u16 ap;
++		struct {
++			u32 endian, elsz, mixed;
++		};
++	};
++};
++
++struct iommu {
++	const char	*name;
++	struct module	*owner;
++	struct clk	*clk;
++	void __iomem	*regbase;
++	struct device	*dev;
++
++	unsigned int	refcount;
++	struct mutex	iommu_lock;	/* global for this whole object */
++
++	/*
++	 * We don't change iopgd for a situation like pgd for a task,
++	 * but share it globally for each iommu.
++	 */
++	u32		*iopgd;
++	spinlock_t	page_table_lock; /* protect iopgd */
++
++	int		nr_tlb_entries;
++
++	struct list_head	mmap;
++	struct mutex		mmap_lock; /* protect mmap */
++
++	int (*isr)(struct iommu *obj);
++
++	void *ctx; /* iommu context: registres saved area */
++};
++
++struct cr_regs {
++	union {
++		struct {
++			u16 cam_l;
++			u16 cam_h;
++		};
++		u32 cam;
++	};
++	union {
++		struct {
++			u16 ram_l;
++			u16 ram_h;
++		};
++		u32 ram;
++	};
++};
++
++struct iotlb_lock {
++	short base;
++	short vict;
++};
++
++/* architecture specific functions */
++struct iommu_functions {
++	unsigned long	version;
++
++	int (*enable)(struct iommu *obj);
++	void (*disable)(struct iommu *obj);
++	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
++
++	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
++	void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
++
++	struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
++	int (*cr_valid)(struct cr_regs *cr);
++	u32 (*cr_to_virt)(struct cr_regs *cr);
++	void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
++	ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
++
++	u32 (*get_pte_attr)(struct iotlb_entry *e);
++
++	void (*save_ctx)(struct iommu *obj);
++	void (*restore_ctx)(struct iommu *obj);
++	ssize_t (*dump_ctx)(struct iommu *obj, char *buf);
++};
++
++struct iommu_platform_data {
++	const char *name;
++	const char *clk_name;
++	const int nr_tlb_entries;
++};
++
++#include <mach/iommu2.h>
++
++/*
++ * utilities for super page(16MB, 1MB, 64KB and 4KB)
++ */
++
++#define iopgsz_max(bytes)			\
++	(((bytes) >= SZ_16M) ? SZ_16M :		\
++	 ((bytes) >= SZ_1M)  ? SZ_1M  :		\
++	 ((bytes) >= SZ_64K) ? SZ_64K :		\
++	 ((bytes) >= SZ_4K)  ? SZ_4K  :	0)
++
++#define bytes_to_iopgsz(bytes)				\
++	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :	\
++	 ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :	\
++	 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :	\
++	 ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
++
++#define iopgsz_to_bytes(iopgsz)				\
++	(((iopgsz) == MMU_CAM_PGSZ_16M)	? SZ_16M :	\
++	 ((iopgsz) == MMU_CAM_PGSZ_1M)	? SZ_1M  :	\
++	 ((iopgsz) == MMU_CAM_PGSZ_64K)	? SZ_64K :	\
++	 ((iopgsz) == MMU_CAM_PGSZ_4K)	? SZ_4K  : 0)
++
++#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
++
++/*
++ * global functions
++ */
++extern u32 iommu_arch_version(void);
++
++extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
++extern void flush_iotlb_page(struct iommu *obj, u32 da);
++extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
++extern void flush_iotlb_all(struct iommu *obj);
++
++ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf);
++
++extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
++extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
++
++extern struct iommu *iommu_get(const char *name);
++extern void iommu_put(struct iommu *obj);
++
++extern void iommu_save_ctx(struct iommu *obj);
++extern void iommu_restore_ctx(struct iommu *obj);
++
++extern int install_iommu_arch(const struct iommu_functions *ops);
++extern void uninstall_iommu_arch(const struct iommu_functions *ops);
++
++#endif /* __MACH_IOMMU_H */
+diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
+new file mode 100644
+index 0000000..e638883
+--- /dev/null
++++ b/arch/arm/plat-omap/iommu.c
+@@ -0,0 +1,953 @@
++/*
++ * omap iommu: tlb and pagetable primitives
++ *
++ * Copyright (C) 2008-2009 Nokia Corporation
++ *
++ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
++ *		Paul Mundt and Toshihiro Kobayashi
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/err.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++#include <asm/cacheflush.h>
++
++#include <mach/clock.h>
++#include <mach/iommu.h>
++
++#include "iopgtable.h"
++
++/* accommodate the difference between omap1 and omap2/3 */
++static const struct iommu_functions *arch_iommu;
++
++static struct platform_driver omap_iommu_driver;
++static struct kmem_cache *iopte_cachep;
++
++/**
++ * install_iommu_arch() - Install archtecure specific iommu functions
++ * @ops:	a pointer to architecture specific iommu functions
++ *
++ * There are several kind of iommu algorithm(tlb, pagetable) among
++ * omap series. This interface installs such an iommu algorighm.
++ **/
++int install_iommu_arch(const struct iommu_functions *ops)
++{
++	if (arch_iommu)
++		return -EBUSY;
++
++	arch_iommu = ops;
++	return 0;
++}
++EXPORT_SYMBOL_GPL(install_iommu_arch);
++
++/**
++ * uninstall_iommu_arch() - Uninstall archtecure specific iommu functions
++ * @ops:	a pointer to architecture specific iommu functions
++ *
++ * This interface uninstalls the iommu algorighm installed previously.
++ **/
++void uninstall_iommu_arch(const struct iommu_functions *ops)
++{
++	if (arch_iommu != ops)
++		pr_err("%s: not your arch\n", __func__);
++
++	arch_iommu = NULL;
++}
++EXPORT_SYMBOL_GPL(uninstall_iommu_arch);
++
++/**
++ * iommu_save_ctx() - Save registers for pm off-mode support
++ * @obj:	target iommu
++ **/
++void iommu_save_ctx(struct iommu *obj)
++{
++	arch_iommu->save_ctx(obj);
++}
++EXPORT_SYMBOL_GPL(iommu_save_ctx);
++
++/**
++ * iommu_restore_ctx() - Restore registers for pm off-mode support
++ * @obj:	target iommu
++ **/
++void iommu_restore_ctx(struct iommu *obj)
++{
++	arch_iommu->restore_ctx(obj);
++}
++EXPORT_SYMBOL_GPL(iommu_restore_ctx);
++
++/**
++ * iommu_arch_version() - Return running iommu arch version
++ **/
++u32 iommu_arch_version(void)
++{
++	return arch_iommu->version;
++}
++EXPORT_SYMBOL_GPL(iommu_arch_version);
++
++static int iommu_enable(struct iommu *obj)
++{
++	int err;
++
++	if (!obj)
++		return -EINVAL;
++
++	clk_enable(obj->clk);
++
++	err = arch_iommu->enable(obj);
++
++	clk_disable(obj->clk);
++	return err;
++}
++
++static void iommu_disable(struct iommu *obj)
++{
++	if (!obj)
++		return;
++
++	clk_enable(obj->clk);
++
++	arch_iommu->disable(obj);
++
++	clk_disable(obj->clk);
++}
++
++#ifdef DEBUG
++static ssize_t iommu_dump_ctx(struct iommu *obj, char *buf)
++{
++	if (!obj || !buf)
++		return -EINVAL;
++
++	return arch_iommu->dump_ctx(obj, buf);
++}
++#endif
++
++/*
++ *	TLB operations
++ */
++static inline void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
++{
++	BUG_ON(!cr || !e);
++
++	arch_iommu->cr_to_e(cr, e);
++}
++
++static inline int iotlb_cr_valid(struct cr_regs *cr)
++{
++	if (!cr)
++		return -EINVAL;
++
++	return arch_iommu->cr_valid(cr);
++}
++
++static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj,
++					     struct iotlb_entry *e)
++{
++	if (!e)
++		return NULL;
++
++	return arch_iommu->alloc_cr(obj, e);
++}
++
++static inline u32 iotlb_cr_to_virt(struct cr_regs *cr)
++{
++	return arch_iommu->cr_to_virt(cr);
++}
++
++static u32 get_iopte_attr(struct iotlb_entry *e)
++{
++	return arch_iommu->get_pte_attr(e);
++}
++
++static u32 iommu_report_fault(struct iommu *obj, u32 *da)
++{
++	return arch_iommu->fault_isr(obj, da);
++}
++
++static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
++{
++	u32 val;
++
++	val = iommu_read_reg(obj, MMU_LOCK);
++
++	l->base = MMU_LOCK_BASE(val);
++	l->vict = MMU_LOCK_VICT(val);
++
++	BUG_ON(l->base != 0); /* Currently no preservation is used */
++}
++
++static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l)
++{
++	u32 val;
++
++	BUG_ON(l->base != 0); /* Currently no preservation is used */
++
++	val = (l->base << MMU_LOCK_BASE_SHIFT);
++	val |= (l->vict << MMU_LOCK_VICT_SHIFT);
++
++	iommu_write_reg(obj, val, MMU_LOCK);
++}
++
++static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr)
++{
++	arch_iommu->tlb_read_cr(obj, cr);
++}
++
++static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr)
++{
++	arch_iommu->tlb_load_cr(obj, cr);
++
++	iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
++	iommu_write_reg(obj, 1, MMU_LD_TLB);
++}
++
++/**
++ * iotlb_dump_cr() - Dump an iommu tlb entry into buf
++ * @obj:	target iommu
++ * @cr:		contents of cam and ram register
++ * @buf:	output buffer
++ **/
++ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
++{
++	BUG_ON(!cr || !buf);
++
++	return arch_iommu->dump_cr(obj, cr, buf);
++}
++EXPORT_SYMBOL_GPL(iotlb_dump_cr);
++
++/**
++ * load_iotlb_entry() - Set an iommu tlb entry
++ * @obj:	target iommu
++ * @e:		an iommu tlb entry info
++ **/
++int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
++{
++	int i;
++	int err = 0;
++	struct iotlb_lock l;
++	struct cr_regs *cr;
++
++	if (!obj || !obj->nr_tlb_entries || !e)
++		return -EINVAL;
++
++	clk_enable(obj->clk);
++
++	for (i = 0; i < obj->nr_tlb_entries; i++) {
++		struct cr_regs tmp;
++
++		iotlb_lock_get(obj, &l);
++		l.vict = i;
++		iotlb_lock_set(obj, &l);
++		iotlb_read_cr(obj, &tmp);
++		if (!iotlb_cr_valid(&tmp))
++			break;
++	}
++
++	if (i == obj->nr_tlb_entries) {
++		dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
++		err = -EBUSY;
++		goto out;
++	}
++
++	cr = iotlb_alloc_cr(obj, e);
++	if (IS_ERR(cr)) {
++		clk_disable(obj->clk);
++		return PTR_ERR(cr);
++	}
++
++	iotlb_load_cr(obj, cr);
++	kfree(cr);
++
++	/* increment victim for next tlb load */
++	if (++l.vict == obj->nr_tlb_entries)
++		l.vict = 0;
++	iotlb_lock_set(obj, &l);
++out:
++	clk_disable(obj->clk);
++	return err;
++}
++EXPORT_SYMBOL_GPL(load_iotlb_entry);
++
++/**
++ * flush_iotlb_page() - Clear an iommu tlb entry
++ * @obj:	target iommu
++ * @da:		iommu device virtual address
++ *
++ * Clear an iommu tlb entry which includes 'da' address.
++ **/
++void flush_iotlb_page(struct iommu *obj, u32 da)
++{
++	struct iotlb_lock l;
++	int i;
++
++	clk_enable(obj->clk);
++
++	for (i = 0; i < obj->nr_tlb_entries; i++) {
++		struct cr_regs cr;
++		u32 start;
++		size_t bytes;
++
++		iotlb_lock_get(obj, &l);
++		l.vict = i;
++		iotlb_lock_set(obj, &l);
++		iotlb_read_cr(obj, &cr);
++		if (!iotlb_cr_valid(&cr))
++			continue;
++
++		start = iotlb_cr_to_virt(&cr);
++		bytes = iopgsz_to_bytes(cr.cam & 3);
++
++		if ((start <= da) && (da < start + bytes)) {
++			dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
++				__func__, start, da, bytes);
++
++			iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
++		}
++	}
++	clk_disable(obj->clk);
++
++	if (i == obj->nr_tlb_entries)
++		dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
++}
++EXPORT_SYMBOL_GPL(flush_iotlb_page);
++
++/**
++ * flush_iotlb_range() - Clear an iommu tlb entries
++ * @obj:	target iommu
++ * @start:	iommu device virtual address(start)
++ * @end:	iommu device virtual address(end)
++ *
++ * Clear an iommu tlb entry which includes 'da' address.
++ **/
++void flush_iotlb_range(struct iommu *obj, u32 start, u32 end)
++{
++	u32 da = start;
++
++	while (da < end) {
++		flush_iotlb_page(obj, da);
++		/* FIXME: Optimize for multiple page size */
++		da += IOPTE_SIZE;
++	}
++}
++EXPORT_SYMBOL_GPL(flush_iotlb_range);
++
++/**
++ * flush_iotlb_all() - Clear all iommu tlb entries
++ * @obj:	target iommu
++ **/
++void flush_iotlb_all(struct iommu *obj)
++{
++	struct iotlb_lock l;
++
++	clk_enable(obj->clk);
++
++	l.base = 0;
++	l.vict = 0;
++	iotlb_lock_set(obj, &l);
++
++	iommu_write_reg(obj, 1, MMU_GFLUSH);
++
++	clk_disable(obj->clk);
++}
++EXPORT_SYMBOL_GPL(flush_iotlb_all);
++
++/*
++ *	H/W pagetable operations
++ */
++static void flush_iopgd_range(u32 *first, u32 *last)
++{
++	/* FIXME: L2 cache should be taken care of if it exists */
++	do {
++		asm("mcr	p15, 0, %0, c7, c10, 1 @ flush_pgd"
++		    : : "r" (first));
++		first += L1_CACHE_BYTES / sizeof(*first);
++	} while (first <= last);
++}
++
++static void flush_iopte_range(u32 *first, u32 *last)
++{
++	/* FIXME: L2 cache should be taken care of if it exists */
++	do {
++		asm("mcr	p15, 0, %0, c7, c10, 1 @ flush_pte"
++		    : : "r" (first));
++		first += L1_CACHE_BYTES / sizeof(*first);
++	} while (first <= last);
++}
++
++static void iopte_free(u32 *iopte)
++{
++	/* Note: freed iopte's must be clean ready for re-use */
++	kmem_cache_free(iopte_cachep, iopte);
++}
++
++static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da)
++{
++	u32 *iopte;
++
++	/* a table has already existed */
++	if (*iopgd)
++		goto pte_ready;
++
++	/*
++	 * do the allocation outside the page table lock
++	 */
++	spin_unlock(&obj->page_table_lock);
++	iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
++	spin_lock(&obj->page_table_lock);
++
++	if (!*iopgd) {
++		if (!iopte)
++			return ERR_PTR(-ENOMEM);
++
++		*iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
++		flush_iopgd_range(iopgd, iopgd);
++
++		dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
++	} else {
++		/* We raced, free the reduniovant table */
++		iopte_free(iopte);
++	}
++
++pte_ready:
++	iopte = iopte_offset(iopgd, da);
++
++	dev_vdbg(obj->dev,
++		 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
++		 __func__, da, iopgd, *iopgd, iopte, *iopte);
++
++	return iopte;
++}
++
++static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot)
++{
++	u32 *iopgd = iopgd_offset(obj, da);
++
++	*iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
++	flush_iopgd_range(iopgd, iopgd);
++	return 0;
++}
++
++static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot)
++{
++	u32 *iopgd = iopgd_offset(obj, da);
++	int i;
++
++	for (i = 0; i < 16; i++)
++		*(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
++	flush_iopgd_range(iopgd, iopgd + 15);
++	return 0;
++}
++
++static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot)
++{
++	u32 *iopgd = iopgd_offset(obj, da);
++	u32 *iopte = iopte_alloc(obj, iopgd, da);
++
++	if (IS_ERR(iopte))
++		return PTR_ERR(iopte);
++
++	*iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
++	flush_iopte_range(iopte, iopte);
++
++	dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
++		 __func__, da, pa, iopte, *iopte);
++
++	return 0;
++}
++
++static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot)
++{
++	u32 *iopgd = iopgd_offset(obj, da);
++	u32 *iopte = iopte_alloc(obj, iopgd, da);
++	int i;
++
++	if (IS_ERR(iopte))
++		return PTR_ERR(iopte);
++
++	for (i = 0; i < 16; i++)
++		*(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
++	flush_iopte_range(iopte, iopte + 15);
++	return 0;
++}
++
++static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e)
++{
++	int (*fn)(struct iommu *, u32, u32, u32);
++	u32 prot;
++	int err;
++
++	if (!obj || !e)
++		return -EINVAL;
++
++	switch (e->pgsz) {
++	case MMU_CAM_PGSZ_16M:
++		fn = iopgd_alloc_super;
++		break;
++	case MMU_CAM_PGSZ_1M:
++		fn = iopgd_alloc_section;
++		break;
++	case MMU_CAM_PGSZ_64K:
++		fn = iopte_alloc_large;
++		break;
++	case MMU_CAM_PGSZ_4K:
++		fn = iopte_alloc_page;
++		break;
++	default:
++		fn = NULL;
++		BUG();
++		break;
++	}
++
++	prot = get_iopte_attr(e);
++
++	spin_lock(&obj->page_table_lock);
++	err = fn(obj, e->da, e->pa, prot);
++	spin_unlock(&obj->page_table_lock);
++
++	return err;
++}
++
++#ifdef DEBUG
++static void dump_tlb_entries(struct iommu *obj)
++{
++	int i;
++	struct iotlb_lock l;
++
++	clk_enable(obj->clk);
++
++	pr_info("%8s %8s\n", "cam:", "ram:");
++	pr_info("-----------------------------------------\n");
++
++	for (i = 0; i < obj->nr_tlb_entries; i++) {
++		struct cr_regs cr;
++		static char buf[4096];
++
++		iotlb_lock_get(obj, &l);
++		l.vict = i;
++		iotlb_lock_set(obj, &l);
++		iotlb_read_cr(obj, &cr);
++		if (!iotlb_cr_valid(&cr))
++			continue;
++
++		memset(buf, 0, 4096);
++		iotlb_dump_cr(obj, &cr, buf);
++		pr_err("%s", buf);
++	}
++
++	clk_disable(obj->clk);
++}
++#else
++static inline void dump_tlb_entries(struct iommu *obj) {}
++#endif
++
++/**
++ * iopgtable_store_entry() - Make an iommu pte entry
++ * @obj:	target iommu
++ * @e:		an iommu tlb entry info
++ **/
++int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e)
++{
++	int err;
++
++	flush_iotlb_page(obj, e->da);
++	err = iopgtable_store_entry_core(obj, e);
++#ifdef USE_IOTLB
++	if (!err)
++		load_iotlb_entry(obj, e);
++#endif
++	return err;
++}
++EXPORT_SYMBOL_GPL(iopgtable_store_entry);
++
++/**
++ * iopgtable_lookup_entry() - Lookup an iommu pte entry
++ * @obj:	target iommu
++ * @da:		iommu device virtual address
++ * @ppgd:	iommu pgd entry pointer to be returned
++ * @ppte:	iommu pte entry pointer to be returned
++ **/
++void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
++{
++	u32 *iopgd, *iopte = NULL;
++
++	iopgd = iopgd_offset(obj, da);
++	if (!*iopgd)
++		goto out;
++
++	if (*iopgd & IOPGD_TABLE)
++		iopte = iopte_offset(iopgd, da);
++out:
++	*ppgd = iopgd;
++	*ppte = iopte;
++}
++EXPORT_SYMBOL_GPL(iopgtable_lookup_entry);
++
++static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
++{
++	size_t bytes;
++	u32 *iopgd = iopgd_offset(obj, da);
++	int nent = 1;
++
++	if (!*iopgd)
++		return 0;
++
++	if (*iopgd & IOPGD_TABLE) {
++		int i;
++		u32 *iopte = iopte_offset(iopgd, da);
++
++		bytes = IOPTE_SIZE;
++		if (*iopte & IOPTE_LARGE) {
++			nent *= 16;
++			/* rewind to the 1st entry */
++			iopte = (u32 *)((u32)iopte & IOLARGE_MASK);
++		}
++		bytes *= nent;
++		memset(iopte, 0, nent * sizeof(*iopte));
++		flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
++
++		/*
++		 * do table walk to check if this table is necessary or not
++		 */
++		iopte = iopte_offset(iopgd, 0);
++		for (i = 0; i < PTRS_PER_IOPTE; i++)
++			if (iopte[i])
++				goto out;
++
++		iopte_free(iopte);
++		nent = 1; /* for the next L1 entry */
++	} else {
++		bytes = IOPGD_SIZE;
++		if (*iopgd & IOPGD_SUPER) {
++			nent *= 16;
++			/* rewind to the 1st entry */
++			iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK);
++		}
++		bytes *= nent;
++	}
++	memset(iopgd, 0, nent * sizeof(*iopgd));
++	flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
++out:
++	return bytes;
++}
++
++/**
++ * iopgtable_clear_entry() - Remove an iommu pte entry
++ * @obj:	target iommu
++ * @da:		iommu device virtual address
++ **/
++size_t iopgtable_clear_entry(struct iommu *obj, u32 da)
++{
++	size_t bytes;
++
++	spin_lock(&obj->page_table_lock);
++
++	bytes = iopgtable_clear_entry_core(obj, da);
++	flush_iotlb_page(obj, da);
++
++	spin_unlock(&obj->page_table_lock);
++
++	return bytes;
++}
++EXPORT_SYMBOL_GPL(iopgtable_clear_entry);
++
++static void iopgtable_clear_entry_all(struct iommu *obj)
++{
++	int i;
++
++	spin_lock(&obj->page_table_lock);
++
++	for (i = 0; i < PTRS_PER_IOPGD; i++) {
++		u32 da;
++		u32 *iopgd;
++
++		da = i << IOPGD_SHIFT;
++		iopgd = iopgd_offset(obj, da);
++
++		if (!*iopgd)
++			continue;
++
++		if (*iopgd & IOPGD_TABLE)
++			iopte_free(iopte_offset(iopgd, 0));
++
++		*iopgd = 0;
++		flush_iopgd_range(iopgd, iopgd);
++	}
++
++	flush_iotlb_all(obj);
++
++	spin_unlock(&obj->page_table_lock);
++}
++
++/*
++ *	Device IOMMU generic operations
++ */
++static irqreturn_t iommu_fault_handler(int irq, void *data)
++{
++	u32 stat, da;
++	u32 *iopgd, *iopte;
++	int err = -EIO;
++	struct iommu *obj = data;
++
++	/* Dynamic loading TLB or PTE */
++	if (obj->isr)
++		err = obj->isr(obj);
++
++	if (!err)
++		return IRQ_HANDLED;
++
++	stat = iommu_report_fault(obj, &da);
++	if (!stat)
++		return IRQ_HANDLED;
++
++	iopgd = iopgd_offset(obj, da);
++
++	if (!(*iopgd & IOPGD_TABLE)) {
++		dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
++			da, iopgd, *iopgd);
++		return IRQ_NONE;
++	}
++
++	iopte = iopte_offset(iopgd, da);
++
++	dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
++		__func__, da, iopgd, *iopgd, iopte, *iopte);
++
++	dump_tlb_entries(obj);
++
++	return IRQ_NONE;
++}
++
++static int device_match_by_alias(struct device *dev, void *data)
++{
++	struct iommu *obj = to_iommu(dev);
++	const char *name = data;
++
++	pr_debug("%s: %s %s\n", __func__, obj->name, name);
++
++	return strcmp(obj->name, name) == 0;
++}
++
++/**
++ * iommu_put() - Get iommu handler
++ * @name:	target iommu name
++ **/
++struct iommu *iommu_get(const char *name)
++{
++	int err = -ENOMEM;
++	struct device *dev;
++	struct iommu *obj;
++
++	dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
++				 device_match_by_alias);
++	if (!dev)
++		return ERR_PTR(-ENODEV);
++
++	obj = to_iommu(dev);
++
++	mutex_lock(&obj->iommu_lock);
++
++	if (obj->refcount++ == 0) {
++		err = iommu_enable(obj);
++		if (err)
++			goto err_enable;
++		flush_iotlb_all(obj);
++	}
++
++	if (!try_module_get(obj->owner))
++		goto err_module;
++
++	mutex_unlock(&obj->iommu_lock);
++
++	dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
++	return obj;
++
++err_module:
++	if (obj->refcount == 1)
++		iommu_disable(obj);
++err_enable:
++	mutex_unlock(&obj->iommu_lock);
++	return ERR_PTR(err);
++}
++EXPORT_SYMBOL_GPL(iommu_get);
++
++/**
++ * iommu_put() - Put back iommu handler
++ * @obj:	target iommu
++ **/
++void iommu_put(struct iommu *obj)
++{
++	if (!obj && IS_ERR(obj))
++		return;
++
++	mutex_lock(&obj->iommu_lock);
++
++	if (--obj->refcount == 0)
++		iommu_disable(obj);
++
++	module_put(obj->owner);
++
++	mutex_unlock(&obj->iommu_lock);
++
++	dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
++}
++EXPORT_SYMBOL_GPL(iommu_put);
++
++/*
++ *	OMAP Device MMU(IOMMU) detection
++ */
++static int __devinit omap_iommu_probe(struct platform_device *pdev)
++{
++	int err = -ENODEV;
++	void *p;
++	int irq;
++	struct iommu *obj;
++	struct resource *res;
++	struct iommu_platform_data *pdata = pdev->dev.platform_data;
++
++	if (pdev->num_resources != 2)
++		return -EINVAL;
++
++	obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
++	if (!obj)
++		return -ENOMEM;
++
++	obj->clk = clk_get(&pdev->dev, pdata->clk_name);
++	if (IS_ERR(obj->clk))
++		goto err_clk;
++
++	obj->nr_tlb_entries = pdata->nr_tlb_entries;
++	obj->name = pdata->name;
++	obj->dev = &pdev->dev;
++	obj->ctx = (void *)obj + sizeof(*obj);
++
++	mutex_init(&obj->iommu_lock);
++	mutex_init(&obj->mmap_lock);
++	spin_lock_init(&obj->page_table_lock);
++	INIT_LIST_HEAD(&obj->mmap);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		err = -ENODEV;
++		goto err_mem;
++	}
++	obj->regbase = ioremap(res->start, resource_size(res));
++	if (!obj->regbase) {
++		err = -ENOMEM;
++		goto err_mem;
++	}
++
++	res = request_mem_region(res->start, resource_size(res),
++				 dev_name(&pdev->dev));
++	if (!res) {
++		err = -EIO;
++		goto err_mem;
++	}
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0) {
++		err = -ENODEV;
++		goto err_irq;
++	}
++	err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
++			  dev_name(&pdev->dev), obj);
++	if (err < 0)
++		goto err_irq;
++	platform_set_drvdata(pdev, obj);
++
++	p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE));
++	if (!p) {
++		err = -ENOMEM;
++		goto err_pgd;
++	}
++	memset(p, 0, IOPGD_TABLE_SIZE);
++	clean_dcache_area(p, IOPGD_TABLE_SIZE);
++	obj->iopgd = p;
++
++	BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE));
++
++	dev_info(&pdev->dev, "%s registered\n", obj->name);
++	return 0;
++
++err_pgd:
++	free_irq(irq, obj);
++err_irq:
++	release_mem_region(res->start, resource_size(res));
++	iounmap(obj->regbase);
++err_mem:
++	clk_put(obj->clk);
++err_clk:
++	kfree(obj);
++	return err;
++}
++
++static int __devexit omap_iommu_remove(struct platform_device *pdev)
++{
++	int irq;
++	struct resource *res;
++	struct iommu *obj = platform_get_drvdata(pdev);
++
++	platform_set_drvdata(pdev, NULL);
++
++	iopgtable_clear_entry_all(obj);
++	free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE));
++
++	irq = platform_get_irq(pdev, 0);
++	free_irq(irq, obj);
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	release_mem_region(res->start, resource_size(res));
++	iounmap(obj->regbase);
++
++	clk_put(obj->clk);
++	dev_info(&pdev->dev, "%s removed\n", obj->name);
++	kfree(obj);
++	return 0;
++}
++
++static struct platform_driver omap_iommu_driver = {
++	.probe	= omap_iommu_probe,
++	.remove	= __devexit_p(omap_iommu_remove),
++	.driver	= {
++		.name	= "omap-iommu",
++	},
++};
++
++static void iopte_cachep_ctor(void *iopte)
++{
++	clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
++}
++
++static int __init omap_iommu_init(void)
++{
++	struct kmem_cache *p;
++	const unsigned long flags = SLAB_HWCACHE_ALIGN;
++
++	p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, 0, flags,
++			      iopte_cachep_ctor);
++	if (!p)
++		return -ENOMEM;
++	iopte_cachep = p;
++
++	return platform_driver_register(&omap_iommu_driver);
++}
++module_init(omap_iommu_init);
++
++static void __exit omap_iommu_exit(void)
++{
++	kmem_cache_destroy(iopte_cachep);
++
++	platform_driver_unregister(&omap_iommu_driver);
++}
++module_exit(omap_iommu_exit);
++
++MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
++MODULE_ALIAS("platform:omap-iommu");
++MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
++MODULE_LICENSE("GPL v2");
+diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
+new file mode 100644
+index 0000000..37dac43
+--- /dev/null
++++ b/arch/arm/plat-omap/iopgtable.h
+@@ -0,0 +1,72 @@
++/*
++ * omap iommu: pagetable definitions
++ *
++ * Copyright (C) 2008-2009 Nokia Corporation
++ *
++ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __PLAT_OMAP_IOMMU_H
++#define __PLAT_OMAP_IOMMU_H
++
++#define IOPGD_SHIFT		20
++#define IOPGD_SIZE		(1 << IOPGD_SHIFT)
++#define IOPGD_MASK		(~(IOPGD_SIZE - 1))
++#define IOSECTION_MASK		IOPGD_MASK
++#define PTRS_PER_IOPGD		(1 << (32 - IOPGD_SHIFT))
++#define IOPGD_TABLE_SIZE	(PTRS_PER_IOPGD * sizeof(u32))
++
++#define IOSUPER_SIZE		(IOPGD_SIZE << 4)
++#define IOSUPER_MASK		(~(IOSUPER_SIZE - 1))
++
++#define IOPTE_SHIFT		12
++#define IOPTE_SIZE		(1 << IOPTE_SHIFT)
++#define IOPTE_MASK		(~(IOPTE_SIZE - 1))
++#define IOPAGE_MASK		IOPTE_MASK
++#define PTRS_PER_IOPTE		(1 << (IOPGD_SHIFT - IOPTE_SHIFT))
++#define IOPTE_TABLE_SIZE	(PTRS_PER_IOPTE * sizeof(u32))
++
++#define IOLARGE_SIZE		(IOPTE_SIZE << 4)
++#define IOLARGE_MASK		(~(IOLARGE_SIZE - 1))
++
++#define IOPGD_TABLE		(1 << 0)
++#define IOPGD_SECTION		(2 << 0)
++#define IOPGD_SUPER		(1 << 18 | 2 << 0)
++
++#define IOPTE_SMALL		(2 << 0)
++#define IOPTE_LARGE		(1 << 0)
++
++#define iopgd_index(da)		(((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
++#define iopgd_offset(obj, da)	((obj)->iopgd + iopgd_index(da))
++
++#define iopte_paddr(iopgd)	(*iopgd & ~((1 << 10) - 1))
++#define iopte_vaddr(iopgd)	((u32 *)phys_to_virt(iopte_paddr(iopgd)))
++
++#define iopte_index(da)		(((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
++#define iopte_offset(iopgd, da)	(iopte_vaddr(iopgd) + iopte_index(da))
++
++static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
++				   u32 flags)
++{
++	memset(e, 0, sizeof(*e));
++
++	e->da		= da;
++	e->pa		= pa;
++	e->valid	= 1;
++	/* FIXME: add OMAP1 support */
++	e->pgsz		= flags & MMU_CAM_PGSZ_MASK;
++	e->endian	= flags & MMU_RAM_ENDIAN_MASK;
++	e->elsz		= flags & MMU_RAM_ELSZ_MASK;
++	e->mixed	= flags & MMU_RAM_MIXED_MASK;
++
++	return iopgsz_to_bytes(e->pgsz);
++}
++
++#define to_iommu(dev)							\
++	(struct iommu *)platform_get_drvdata(to_platform_device(dev))
++
++#endif /* __PLAT_OMAP_IOMMU_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0002-omap-iommu-omap2-architecture-specific-functions.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0002-omap-iommu-omap2-architecture-specific-functions.patch
new file mode 100644
index 0000000000..d5f78dd14e
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0002-omap-iommu-omap2-architecture-specific-functions.patch
@@ -0,0 +1,453 @@
+From c79d7959c45f40e47520aa6acd54c19094754787 Mon Sep 17 00:00:00 2001
+From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+Date: Mon, 26 Jan 2009 15:13:45 +0200
+Subject: [PATCH] omap iommu: omap2 architecture specific functions
+
+The structure 'arch_mmu' accommodates the difference between omap1 and
+omap2/3.
+
+This patch provides omap2/3 specific functions
+
+Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+---
+ arch/arm/mach-omap2/iommu2.c             |  326 ++++++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/mach/iommu2.h |   94 +++++++++
+ 2 files changed, 420 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/iommu2.c
+ create mode 100644 arch/arm/plat-omap/include/mach/iommu2.h
+
+diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
+new file mode 100644
+index 0000000..88a44f1
+--- /dev/null
++++ b/arch/arm/mach-omap2/iommu2.c
+@@ -0,0 +1,326 @@
++/*
++ * omap iommu: omap2/3 architecture specific functions
++ *
++ * Copyright (C) 2008-2009 Nokia Corporation
++ *
++ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
++ *		Paul Mundt and Toshihiro Kobayashi
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/err.h>
++#include <linux/device.h>
++#include <linux/jiffies.h>
++#include <linux/module.h>
++#include <linux/stringify.h>
++
++#include <asm/io.h>
++
++#include <mach/iommu.h>
++#include <mach/iommu2.h>
++
++/*
++ * omap2 architecture specific register bit definitions
++ */
++#define IOMMU_ARCH_VERSION	0x00000011
++
++/* SYSCONF */
++#define MMU_SYS_IDLE_SHIFT	3
++#define MMU_SYS_IDLE_FORCE	(0 << MMU_SYS_IDLE_SHIFT)
++#define MMU_SYS_IDLE_NONE	(1 << MMU_SYS_IDLE_SHIFT)
++#define MMU_SYS_IDLE_SMART	(2 << MMU_SYS_IDLE_SHIFT)
++#define MMU_SYS_IDLE_MASK	(3 << MMU_SYS_IDLE_SHIFT)
++
++#define MMU_SYS_SOFTRESET	(1 << 1)
++#define MMU_SYS_AUTOIDLE	1
++
++/* SYSSTATUS */
++#define MMU_SYS_RESETDONE	1
++
++/* IRQSTATUS & IRQENABLE */
++#define MMU_IRQ_MULTIHITFAULT	(1 << 4)
++#define MMU_IRQ_TABLEWALKFAULT	(1 << 3)
++#define MMU_IRQ_EMUMISS		(1 << 2)
++#define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
++#define MMU_IRQ_TLBMISS		(1 << 0)
++#define MMU_IRQ_MASK	\
++	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
++	 MMU_IRQ_TRANSLATIONFAULT)
++
++/* MMU_CNTL */
++#define MMU_CNTL_SHIFT		1
++#define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
++#define MMU_CNTL_EML_TLB	(1 << 3)
++#define MMU_CNTL_TWL_EN		(1 << 2)
++#define MMU_CNTL_MMU_EN		(1 << 1)
++
++#define get_cam_va_mask(pgsz)				\
++	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
++	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
++	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
++	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
++
++static int omap2_iommu_enable(struct iommu *obj)
++{
++	u32 l, pa;
++	unsigned long timeout;
++
++	if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
++		return -EINVAL;
++
++	pa = virt_to_phys(obj->iopgd);
++	if (!IS_ALIGNED(pa, SZ_16K))
++		return -EINVAL;
++
++	iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
++
++	timeout = jiffies + msecs_to_jiffies(20);
++	do {
++		l = iommu_read_reg(obj, MMU_SYSSTATUS);
++		if (l & MMU_SYS_RESETDONE)
++			break;
++	} while (time_after(jiffies, timeout));
++
++	if (!(l & MMU_SYS_RESETDONE)) {
++		dev_err(obj->dev, "can't take mmu out of reset\n");
++		return -ENODEV;
++	}
++
++	l = iommu_read_reg(obj, MMU_REVISION);
++	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
++		 (l >> 4) & 0xf, l & 0xf);
++
++	l = iommu_read_reg(obj, MMU_SYSCONFIG);
++	l &= ~MMU_SYS_IDLE_MASK;
++	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
++	iommu_write_reg(obj, l, MMU_SYSCONFIG);
++
++	iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
++	iommu_write_reg(obj, pa, MMU_TTB);
++
++	l = iommu_read_reg(obj, MMU_CNTL);
++	l &= ~MMU_CNTL_MASK;
++	l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
++	iommu_write_reg(obj, l, MMU_CNTL);
++
++	return 0;
++}
++
++static void omap2_iommu_disable(struct iommu *obj)
++{
++	u32 l = iommu_read_reg(obj, MMU_CNTL);
++
++	l &= ~MMU_CNTL_MASK;
++	iommu_write_reg(obj, l, MMU_CNTL);
++	iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
++
++	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
++}
++
++static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
++{
++	int i;
++	u32 stat, da;
++	const char *err_msg[] =	{
++		"tlb miss",
++		"translation fault",
++		"emulation miss",
++		"table walk fault",
++		"multi hit fault",
++	};
++
++	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
++	stat &= MMU_IRQ_MASK;
++	if (!stat)
++		return 0;
++
++	da = iommu_read_reg(obj, MMU_FAULT_AD);
++	*ra = da;
++
++	dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
++
++	for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
++		if (stat & (1 << i))
++			printk("%s ", err_msg[i]);
++	}
++	printk("\n");
++
++	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
++	return stat;
++}
++
++static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
++{
++	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
++	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
++}
++
++static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr)
++{
++	iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
++	iommu_write_reg(obj, cr->ram, MMU_RAM);
++}
++
++static u32 omap2_cr_to_virt(struct cr_regs *cr)
++{
++	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
++	u32 mask = get_cam_va_mask(cr->cam & page_size);
++
++	return cr->cam & mask;
++}
++
++static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
++{
++	struct cr_regs *cr;
++
++	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
++		dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
++			e->da);
++		return ERR_PTR(-EINVAL);
++	}
++
++	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
++	if (!cr)
++		return ERR_PTR(-ENOMEM);
++
++	cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz;
++	cr->ram = e->pa | e->endian | e->elsz | e->mixed;
++
++	return cr;
++}
++
++static inline int omap2_cr_valid(struct cr_regs *cr)
++{
++	return cr->cam & MMU_CAM_V;
++}
++
++static u32 omap2_get_pte_attr(struct iotlb_entry *e)
++{
++	u32 attr;
++
++	attr = e->mixed << 5;
++	attr |= e->endian;
++	attr |= e->elsz >> 3;
++	attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
++
++	return attr;
++}
++
++static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
++{
++	char *p = buf;
++
++	/* FIXME: Need more detail analysis of cam/ram */
++	p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);
++
++	return p - buf;
++}
++
++#define pr_reg(name)							\
++	p += sprintf(p, "%20s: %08x\n",					\
++		     __stringify(name), iommu_read_reg(obj, MMU_##name));
++
++static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
++{
++	char *p = buf;
++
++	pr_reg(REVISION);
++	pr_reg(SYSCONFIG);
++	pr_reg(SYSSTATUS);
++	pr_reg(IRQSTATUS);
++	pr_reg(IRQENABLE);
++	pr_reg(WALKING_ST);
++	pr_reg(CNTL);
++	pr_reg(FAULT_AD);
++	pr_reg(TTB);
++	pr_reg(LOCK);
++	pr_reg(LD_TLB);
++	pr_reg(CAM);
++	pr_reg(RAM);
++	pr_reg(GFLUSH);
++	pr_reg(FLUSH_ENTRY);
++	pr_reg(READ_CAM);
++	pr_reg(READ_RAM);
++	pr_reg(EMU_FAULT_AD);
++
++	return p - buf;
++}
++
++static void omap2_iommu_save_ctx(struct iommu *obj)
++{
++	int i;
++	u32 *p = obj->ctx;
++
++	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
++		p[i] = iommu_read_reg(obj, i * sizeof(u32));
++		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
++	}
++
++	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
++}
++
++static void omap2_iommu_restore_ctx(struct iommu *obj)
++{
++	int i;
++	u32 *p = obj->ctx;
++
++	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
++		iommu_write_reg(obj, p[i], i * sizeof(u32));
++		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
++	}
++
++	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
++}
++
++static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
++{
++	e->da		= cr->cam & MMU_CAM_VATAG_MASK;
++	e->pa		= cr->ram & MMU_RAM_PADDR_MASK;
++	e->valid	= cr->cam & MMU_CAM_V;
++	e->pgsz		= cr->cam & MMU_CAM_PGSZ_MASK;
++	e->endian	= cr->ram & MMU_RAM_ENDIAN_MASK;
++	e->elsz		= cr->ram & MMU_RAM_ELSZ_MASK;
++	e->mixed	= cr->ram & MMU_RAM_MIXED;
++}
++
++static const struct iommu_functions omap2_iommu_ops = {
++	.version	= IOMMU_ARCH_VERSION,
++
++	.enable		= omap2_iommu_enable,
++	.disable	= omap2_iommu_disable,
++	.fault_isr	= omap2_iommu_fault_isr,
++
++	.tlb_read_cr	= omap2_tlb_read_cr,
++	.tlb_load_cr	= omap2_tlb_load_cr,
++
++	.cr_to_e	= omap2_cr_to_e,
++	.cr_to_virt	= omap2_cr_to_virt,
++	.alloc_cr	= omap2_alloc_cr,
++	.cr_valid	= omap2_cr_valid,
++	.dump_cr	= omap2_dump_cr,
++
++	.get_pte_attr	= omap2_get_pte_attr,
++
++	.save_ctx	= omap2_iommu_save_ctx,
++	.restore_ctx	= omap2_iommu_restore_ctx,
++	.dump_ctx	= omap2_iommu_dump_ctx,
++};
++
++static int __init omap2_iommu_init(void)
++{
++	return install_iommu_arch(&omap2_iommu_ops);
++}
++module_init(omap2_iommu_init);
++
++static void __exit omap2_iommu_exit(void)
++{
++	uninstall_iommu_arch(&omap2_iommu_ops);
++}
++module_exit(omap2_iommu_exit);
++
++MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
++MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
++MODULE_LICENSE("GPL v2");
+diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h
+new file mode 100644
+index 0000000..d746047
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/iommu2.h
+@@ -0,0 +1,94 @@
++/*
++ * omap iommu: omap2 architecture specific definitions
++ *
++ * Copyright (C) 2008-2009 Nokia Corporation
++ *
++ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __MACH_IOMMU2_H
++#define __MACH_IOMMU2_H
++
++/*
++ * MMU Register offsets
++ */
++#define MMU_REVISION		0x00
++#define MMU_SYSCONFIG		0x10
++#define MMU_SYSSTATUS		0x14
++#define MMU_IRQSTATUS		0x18
++#define MMU_IRQENABLE		0x1c
++#define MMU_WALKING_ST		0x40
++#define MMU_CNTL		0x44
++#define MMU_FAULT_AD		0x48
++#define MMU_TTB			0x4c
++#define MMU_LOCK		0x50
++#define MMU_LD_TLB		0x54
++#define MMU_CAM			0x58
++#define MMU_RAM			0x5c
++#define MMU_GFLUSH		0x60
++#define MMU_FLUSH_ENTRY		0x64
++#define MMU_READ_CAM		0x68
++#define MMU_READ_RAM		0x6c
++#define MMU_EMU_FAULT_AD	0x70
++
++#define MMU_REG_SIZE		256
++
++/*
++ * MMU Register bit definitions
++ */
++#define MMU_LOCK_BASE_SHIFT	10
++#define MMU_LOCK_BASE_MASK	(0x1f << MMU_LOCK_BASE_SHIFT)
++#define MMU_LOCK_BASE(x)	\
++	((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
++
++#define MMU_LOCK_VICT_SHIFT	4
++#define MMU_LOCK_VICT_MASK	(0x1f << MMU_LOCK_VICT_SHIFT)
++#define MMU_LOCK_VICT(x)	\
++	((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
++
++#define MMU_CAM_VATAG_SHIFT	12
++#define MMU_CAM_VATAG_MASK \
++	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
++#define MMU_CAM_P		(1 << 3)
++#define MMU_CAM_V		(1 << 2)
++#define MMU_CAM_PGSZ_MASK	3
++#define MMU_CAM_PGSZ_1M		(0 << 0)
++#define MMU_CAM_PGSZ_64K	(1 << 0)
++#define MMU_CAM_PGSZ_4K		(2 << 0)
++#define MMU_CAM_PGSZ_16M	(3 << 0)
++
++#define MMU_RAM_PADDR_SHIFT	12
++#define MMU_RAM_PADDR_MASK \
++	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
++#define MMU_RAM_ENDIAN_SHIFT	9
++#define MMU_RAM_ENDIAN_MASK	(1 << MMU_RAM_ENDIAN_SHIFT)
++#define MMU_RAM_ENDIAN_BIG	(1 << MMU_RAM_ENDIAN_SHIFT)
++#define MMU_RAM_ENDIAN_LITTLE	(0 << MMU_RAM_ENDIAN_SHIFT)
++#define MMU_RAM_ELSZ_SHIFT	7
++#define MMU_RAM_ELSZ_MASK	(3 << MMU_RAM_ELSZ_SHIFT)
++#define MMU_RAM_ELSZ_8		(0 << MMU_RAM_ELSZ_SHIFT)
++#define MMU_RAM_ELSZ_16		(1 << MMU_RAM_ELSZ_SHIFT)
++#define MMU_RAM_ELSZ_32		(2 << MMU_RAM_ELSZ_SHIFT)
++#define MMU_RAM_ELSZ_NONE	(3 << MMU_RAM_ELSZ_SHIFT)
++#define MMU_RAM_MIXED_SHIFT	6
++#define MMU_RAM_MIXED_MASK	(1 << MMU_RAM_MIXED_SHIFT)
++#define MMU_RAM_MIXED		MMU_RAM_MIXED_MASK
++
++/*
++ * register accessors
++ */
++static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
++{
++	return __raw_readl(obj->regbase + offs);
++}
++
++static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
++{
++	__raw_writel(val, obj->regbase + offs);
++}
++
++#endif /* __MACH_IOMMU2_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0003-omap-iommu-omap3-iommu-device-registration.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0003-omap-iommu-omap3-iommu-device-registration.patch
new file mode 100644
index 0000000000..2954c47872
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0003-omap-iommu-omap3-iommu-device-registration.patch
@@ -0,0 +1,124 @@
+From 6a84082597dd322713c5d5951530e3eecb878ad4 Mon Sep 17 00:00:00 2001
+From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+Date: Wed, 28 Jan 2009 21:32:04 +0200
+Subject: [PATCH] omap iommu: omap3 iommu device registration
+
+Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+---
+ arch/arm/mach-omap2/omap3-iommu.c |  104 +++++++++++++++++++++++++++++++++++++
+ 1 files changed, 104 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/omap3-iommu.c
+
+diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c
+new file mode 100644
+index 0000000..97481cc
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap3-iommu.c
+@@ -0,0 +1,104 @@
++/*
++ * omap iommu: omap3 device registration
++ *
++ * Copyright (C) 2008-2009 Nokia Corporation
++ *
++ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/io.h>
++
++#include <mach/iommu.h>
++
++#define OMAP3_MMU1_BASE	0x480bd400
++#define OMAP3_MMU2_BASE	0x5d000000
++#define OMAP3_MMU1_IRQ	24
++#define OMAP3_MMU2_IRQ	28
++
++static struct resource omap3_iommu_res[] = {
++	{ /* Camera ISP MMU */
++		.start		= OMAP3_MMU1_BASE,
++		.end		= OMAP3_MMU1_BASE + MMU_REG_SIZE - 1,
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= OMAP3_MMU1_IRQ,
++		.flags		= IORESOURCE_IRQ,
++	},
++	{ /* IVA2.2 MMU */
++		.start		= OMAP3_MMU2_BASE,
++		.end		= OMAP3_MMU2_BASE + MMU_REG_SIZE - 1,
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= OMAP3_MMU2_IRQ,
++		.flags		= IORESOURCE_IRQ,
++	},
++};
++#define NR_IOMMU_RES (ARRAY_SIZE(omap3_iommu_res) / 2)
++
++static const struct iommu_platform_data omap3_iommu_pdata[] __initconst = {
++	{
++		.name = "isp",
++		.nr_tlb_entries = 8,
++		.clk_name = "cam_ick",
++	},
++	{
++		.name = "iva2",
++		.nr_tlb_entries = 32,
++		.clk_name = "iva2_ck",
++	},
++};
++#define NR_IOMMU_DEVICES ARRAY_SIZE(omap3_iommu_pdata)
++
++static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES];
++
++static int __init omap3_iommu_init(void)
++{
++	int i, err;
++
++	for (i = 0; i < NR_IOMMU_DEVICES; i++) {
++		struct platform_device *pdev;
++
++		pdev = platform_device_alloc("omap-iommu", i + 1);
++		if (!pdev)
++			goto err_out;
++		err = platform_device_add_resources(pdev,
++				    &omap3_iommu_res[2 * i], NR_IOMMU_RES);
++		if (err)
++			goto err_out;
++		err = platform_device_add_data(pdev, &omap3_iommu_pdata[i],
++					       sizeof(omap3_iommu_pdata[0]));
++		if (err)
++			goto err_out;
++		err = platform_device_add(pdev);
++		if (err)
++			goto err_out;
++		omap3_iommu_pdev[i] = pdev;
++	}
++	return 0;
++
++err_out:
++	while (i--)
++		platform_device_put(omap3_iommu_pdev[i]);
++	return err;
++}
++module_init(omap3_iommu_init);
++
++static void __exit omap3_iommu_exit(void)
++{
++	int i;
++
++	for (i = 0; i < NR_IOMMU_DEVICES; i++)
++		platform_device_unregister(omap3_iommu_pdev[i]);
++}
++module_exit(omap3_iommu_exit);
++
++MODULE_AUTHOR("Hiroshi DOYU");
++MODULE_DESCRIPTION("omap iommu: omap3 device registration");
++MODULE_LICENSE("GPL v2");
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0004-omap-iommu-simple-virtual-address-space-management.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0004-omap-iommu-simple-virtual-address-space-management.patch
new file mode 100644
index 0000000000..945778b943
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0004-omap-iommu-simple-virtual-address-space-management.patch
@@ -0,0 +1,1083 @@
+From 07365182b998af3dc2b79e822b8e21a3f50262c4 Mon Sep 17 00:00:00 2001
+From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+Date: Wed, 28 Jan 2009 21:32:08 +0200
+Subject: [PATCH] omap iommu: simple virtual address space management
+
+This patch provides a device drivers, which has a omap iommu, with
+address mapping APIs between device virtual address(iommu), physical
+address and MPU virtual address.
+
+There are 4 possible patterns for iommu virtual address(iova/da) mapping.
+
+    |iova/			  mapping		iommu_		page
+    | da	pa	va	(d)-(p)-(v)		function	type
+  ---------------------------------------------------------------------------
+  1 | c		c	c	 1 - 1 - 1	  _kmap() / _kunmap()	s
+  2 | c		c,a	c	 1 - 1 - 1	_kmalloc()/ _kfree()	s
+  3 | c		d	c	 1 - n - 1	  _vmap() / _vunmap()	s
+  4 | c		d,a	c	 1 - n - 1	_vmalloc()/ _vfree()	n*
+
+    'iova':	device iommu virtual address
+    'da':	alias of 'iova'
+    'pa':	physical address
+    'va':	mpu virtual address
+
+    'c':	contiguous memory area
+    'd':	dicontiguous memory area
+    'a':	anonymous memory allocation
+    '()':	optional feature
+
+    'n':	a normal page(4KB) size is used.
+    's':	multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used.
+
+    '*':	not yet, but feasible.
+
+Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+---
+ arch/arm/include/asm/io.h               |    6 +
+ arch/arm/mm/ioremap.c                   |   11 +
+ arch/arm/plat-omap/include/mach/iovmm.h |   94 ++++
+ arch/arm/plat-omap/iovmm.c              |  891 +++++++++++++++++++++++++++++++
+ 4 files changed, 1002 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/plat-omap/include/mach/iovmm.h
+ create mode 100644 arch/arm/plat-omap/iovmm.c
+
+diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
+index d2a59cf..cbdadfe 100644
+--- a/arch/arm/include/asm/io.h
++++ b/arch/arm/include/asm/io.h
+@@ -75,6 +75,12 @@ extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int);
+ extern void __iounmap(volatile void __iomem *addr);
+ 
+ /*
++ * external interface to remap single page with appropriate type
++ */
++extern int ioremap_page(unsigned long virt, unsigned long phys,
++			unsigned int mtype);
++
++/*
+  * Bad read/write accesses...
+  */
+ extern void __readwrite_bug(const char *fn);
+diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
+index 9f88dd3..8441351 100644
+--- a/arch/arm/mm/ioremap.c
++++ b/arch/arm/mm/ioremap.c
+@@ -110,6 +110,17 @@ static int remap_area_pages(unsigned long start, unsigned long pfn,
+ 	return err;
+ }
+ 
++int ioremap_page(unsigned long virt, unsigned long phys, unsigned int mtype)
++{
++	const struct mem_type *type;
++
++	type = get_mem_type(mtype);
++	if (!type)
++		return -EINVAL;
++
++	return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, type);
++}
++EXPORT_SYMBOL(ioremap_page);
+ 
+ void __check_kvm_seq(struct mm_struct *mm)
+ {
+diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h
+new file mode 100644
+index 0000000..bdc7ce5
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/iovmm.h
+@@ -0,0 +1,94 @@
++/*
++ * omap iommu: simple virtual address space management
++ *
++ * Copyright (C) 2008-2009 Nokia Corporation
++ *
++ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __IOMMU_MMAP_H
++#define __IOMMU_MMAP_H
++
++struct iovm_struct {
++	struct iommu		*iommu;	/* iommu object which this belongs to */
++	u32			da_start; /* area definition */
++	u32			da_end;
++	u32			flags; /* IOVMF_: see below */
++	struct list_head	list; /* linked in ascending order */
++	const struct sg_table	*sgt; /* keep 'page' <-> 'da' mapping */
++	void			*va; /* mpu side mapped address */
++};
++
++/*
++ * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
++ *
++ * lower 16 bit is used for h/w and upper 16 bit is for s/w.
++ */
++#define IOVMF_SW_SHIFT		16
++#define IOVMF_HW_SIZE		(1 << IOVMF_SW_SHIFT)
++#define IOVMF_HW_MASK		(IOVMF_HW_SIZE - 1)
++#define IOVMF_SW_MASK		(~IOVMF_HW_MASK)UL
++
++/*
++ * iovma: h/w flags derived from cam and ram attribute
++ */
++#define IOVMF_CAM_MASK		(~((1 << 10) - 1))
++#define IOVMF_RAM_MASK		(~IOVMF_CAM_MASK)
++
++#define IOVMF_PGSZ_MASK		(3 << 0)
++#define IOVMF_PGSZ_1M		MMU_CAM_PGSZ_1M
++#define IOVMF_PGSZ_64K		MMU_CAM_PGSZ_64K
++#define IOVMF_PGSZ_4K		MMU_CAM_PGSZ_4K
++#define IOVMF_PGSZ_16M		MMU_CAM_PGSZ_16M
++
++#define IOVMF_ENDIAN_MASK	(1 << 9)
++#define IOVMF_ENDIAN_BIG	MMU_RAM_ENDIAN_BIG
++#define IOVMF_ENDIAN_LITTLE	MMU_RAM_ENDIAN_LITTLE
++
++#define IOVMF_ELSZ_MASK		(3 << 7)
++#define IOVMF_ELSZ_8		MMU_RAM_ELSZ_8
++#define IOVMF_ELSZ_16		MMU_RAM_ELSZ_16
++#define IOVMF_ELSZ_32		MMU_RAM_ELSZ_32
++#define IOVMF_ELSZ_NONE		MMU_RAM_ELSZ_NONE
++
++#define IOVMF_MIXED_MASK	(1 << 6)
++#define IOVMF_MIXED		MMU_RAM_MIXED
++
++/*
++ * iovma: s/w flags, used for mapping and umapping internally.
++ */
++#define IOVMF_MMIO		(1 << IOVMF_SW_SHIFT)
++#define IOVMF_ALLOC		(2 << IOVMF_SW_SHIFT)
++#define IOVMF_ALLOC_MASK	(3 << IOVMF_SW_SHIFT)
++
++/* "superpages" is supported just with physically linear pages */
++#define IOVMF_DISCONT		(1 << (2 + IOVMF_SW_SHIFT))
++#define IOVMF_LINEAR		(2 << (2 + IOVMF_SW_SHIFT))
++#define IOVMF_LINEAR_MASK	(3 << (2 + IOVMF_SW_SHIFT))
++
++#define IOVMF_DA_FIXED		(1 << (4 + IOVMF_SW_SHIFT))
++#define IOVMF_DA_ANON		(2 << (4 + IOVMF_SW_SHIFT))
++#define IOVMF_DA_MASK		(3 << (4 + IOVMF_SW_SHIFT))
++
++
++extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
++extern u32 iommu_vmap(struct iommu *obj, u32 da,
++			const struct sg_table *sgt, u32 flags);
++extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
++extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
++			   u32 flags);
++extern void iommu_vfree(struct iommu *obj, const u32 da);
++extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
++			u32 flags);
++extern void iommu_kunmap(struct iommu *obj, u32 da);
++extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
++			   u32 flags);
++extern void iommu_kfree(struct iommu *obj, u32 da);
++
++extern void *da_to_va(struct iommu *obj, u32 da);
++
++#endif /* __IOMMU_MMAP_H */
+diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
+new file mode 100644
+index 0000000..6726d10
+--- /dev/null
++++ b/arch/arm/plat-omap/iovmm.c
+@@ -0,0 +1,891 @@
++/*
++ * omap iommu: simple virtual address space management
++ *
++ * Copyright (C) 2008-2009 Nokia Corporation
++ *
++ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/err.h>
++#include <linux/vmalloc.h>
++#include <linux/device.h>
++#include <linux/scatterlist.h>
++
++#include <asm/io.h>
++#include <asm/cacheflush.h>
++
++#include <mach/iommu.h>
++#include <mach/iovmm.h>
++
++#include "iopgtable.h"
++
++/*
++ * A device driver needs to create address mappings between:
++ *
++ * - iommu/device address
++ * - physical address
++ * - mpu virtual address
++ *
++ * There are 4 possible patterns for them:
++ *
++ *    |iova/			  mapping		iommu_		page
++ *    | da	pa	va	(d)-(p)-(v)		function	type
++ *  ---------------------------------------------------------------------------
++ *  1 | c	c	c	 1 - 1 - 1	  _kmap() / _kunmap()	s
++ *  2 | c	c,a	c	 1 - 1 - 1	_kmalloc()/ _kfree()	s
++ *  3 | c	d	c	 1 - n - 1	  _vmap() / _vunmap()	s
++ *  4 | c	d,a	c	 1 - n - 1	_vmalloc()/ _vfree()	n*
++ *
++ *
++ *	'iova':	device iommu virtual address
++ *	'da':	alias of 'iova'
++ *	'pa':	physical address
++ *	'va':	mpu virtual address
++ *
++ *	'c':	contiguous memory area
++ *	'd':	dicontiguous memory area
++ *	'a':	anonymous memory allocation
++ *	'()':	optional feature
++ *
++ *	'n':	a normal page(4KB) size is used.
++ *	's':	multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used.
++ *
++ *	'*':	not yet, but feasible.
++ */
++
++static struct kmem_cache *iovm_area_cachep;
++
++/* return total bytes of sg buffers */
++static size_t sgtable_len(const struct sg_table *sgt)
++{
++	unsigned int i, total = 0;
++	struct scatterlist *sg;
++
++	if (!sgt)
++		return 0;
++
++	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
++		size_t bytes;
++
++		bytes = sg_dma_len(sg);
++
++		if (!iopgsz_ok(bytes)) {
++			pr_err("%s: sg[%d] not iommu pagesize(%x)\n",
++			       __func__, i, bytes);
++			return 0;
++		}
++
++		total += bytes;
++	}
++
++	return total;
++}
++#define sgtable_ok(x)	(!!sgtable_len(x))
++
++/*
++ * calculate the optimal number sg elements from total bytes based on
++ * iommu superpages
++ */
++static unsigned int sgtable_nents(size_t bytes)
++{
++	int i;
++	unsigned int nr_entries;
++	const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
++
++	if (!IS_ALIGNED(bytes, PAGE_SIZE)) {
++		pr_err("%s: wrong size %08x\n", __func__, bytes);
++		return 0;
++	}
++
++	nr_entries = 0;
++	for (i = 0; i < ARRAY_SIZE(pagesize); i++) {
++		if (bytes >= pagesize[i]) {
++			nr_entries += (bytes / pagesize[i]);
++			bytes %= pagesize[i];
++		}
++	}
++	BUG_ON(bytes);
++
++	return nr_entries;
++}
++
++/* allocate and initialize sg_table header(a kind of 'superblock') */
++static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
++{
++	unsigned int nr_entries;
++	int err;
++	struct sg_table *sgt;
++
++	if (!bytes)
++		return ERR_PTR(-EINVAL);
++
++	if (!IS_ALIGNED(bytes, PAGE_SIZE))
++		return ERR_PTR(-EINVAL);
++
++	/* FIXME: IOVMF_DA_FIXED should support 'superpages' */
++	if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) {
++		nr_entries = sgtable_nents(bytes);
++		if (!nr_entries)
++			return ERR_PTR(-EINVAL);
++	} else
++		nr_entries =  bytes / PAGE_SIZE;
++
++	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
++	if (!sgt)
++		return ERR_PTR(-ENOMEM);
++
++	err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL);
++	if (err)
++		return ERR_PTR(err);
++
++	pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries);
++
++	return sgt;
++}
++
++/* free sg_table header(a kind of superblock) */
++static void sgtable_free(struct sg_table *sgt)
++{
++	if (!sgt)
++		return;
++
++	sg_free_table(sgt);
++	kfree(sgt);
++
++	pr_debug("%s: sgt:%p\n", __func__, sgt);
++}
++
++/* map 'sglist' to a contiguous mpu virtual area and return 'va' */
++static void *vmap_sg(const struct sg_table *sgt)
++{
++	u32 va;
++	size_t total;
++	unsigned int i;
++	struct scatterlist *sg;
++	struct vm_struct *new;
++
++	total = sgtable_len(sgt);
++	if (!total)
++		return ERR_PTR(-EINVAL);
++
++	new = __get_vm_area(total, VM_IOREMAP, VMALLOC_START, VMALLOC_END);
++	if (!new)
++		return ERR_PTR(-ENOMEM);
++	va = (u32)new->addr;
++
++	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
++		size_t bytes;
++		u32 pa;
++		int err;
++
++		pa = sg_phys(sg);
++		bytes = sg_dma_len(sg);
++
++		BUG_ON(bytes != PAGE_SIZE);
++
++		err = ioremap_page(va,  pa, MT_DEVICE);
++		if (err)
++			goto err_out;
++
++		va += bytes;
++	}
++
++	flush_cache_vmap(new->addr, total);
++	return new->addr;
++
++err_out:
++	WARN_ON(1); /* FIXME: cleanup some mpu mappings */
++	vunmap(new->addr);
++	return ERR_PTR(-EAGAIN);
++}
++
++static inline void vunmap_sg(const void *va)
++{
++	vunmap(va);
++}
++
++static struct iovm_struct *__find_iovm_area(struct iommu *obj, const u32 da)
++{
++	struct iovm_struct *tmp;
++
++	list_for_each_entry(tmp, &obj->mmap, list) {
++		if ((da >= tmp->da_start) && (da < tmp->da_end)) {
++			size_t len;
++
++			len = tmp->da_end - tmp->da_start;
++
++			dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n",
++				__func__, tmp->da_start, da, tmp->da_end, len,
++				tmp->flags);
++
++			return tmp;
++		}
++	}
++
++	return NULL;
++}
++
++/**
++ * find_iovm_area  -  find iovma which includes @da
++ * @da:		iommu device virtual address
++ *
++ * Find the existing iovma starting at @da
++ */
++struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da)
++{
++	struct iovm_struct *area;
++
++	mutex_lock(&obj->mmap_lock);
++	area = __find_iovm_area(obj, da);
++	mutex_unlock(&obj->mmap_lock);
++
++	return area;
++}
++EXPORT_SYMBOL_GPL(find_iovm_area);
++
++/*
++ * This finds the hole(area) which fits the requested address and len
++ * in iovmas mmap, and returns the new allocated iovma.
++ */
++static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
++					   size_t bytes, u32 flags)
++{
++	struct iovm_struct *new, *tmp;
++	u32 start, prev_end, alignement;
++
++	if (!obj || !bytes)
++		return ERR_PTR(-EINVAL);
++
++	start = da;
++	alignement = PAGE_SIZE;
++
++	if (flags & IOVMF_DA_ANON) {
++		/*
++		 * Reserve the first page for NULL
++		 */
++		start = PAGE_SIZE;
++		if (flags & IOVMF_LINEAR)
++			alignement = iopgsz_max(bytes);
++		start = roundup(start, alignement);
++	}
++
++	tmp = NULL;
++	if (list_empty(&obj->mmap))
++		goto found;
++
++	prev_end = 0;
++	list_for_each_entry(tmp, &obj->mmap, list) {
++
++		if ((prev_end <= start) && (start + bytes < tmp->da_start))
++			goto found;
++
++		if (flags & IOVMF_DA_ANON)
++			start = roundup(tmp->da_end, alignement);
++
++		prev_end = tmp->da_end;
++	}
++
++	if ((start >= prev_end) && (ULONG_MAX - start >= bytes))
++		goto found;
++
++	dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n",
++		__func__, da, bytes, flags);
++
++	return ERR_PTR(-EINVAL);
++
++found:
++	new = kmem_cache_zalloc(iovm_area_cachep, GFP_KERNEL);
++	if (!new)
++		return ERR_PTR(-ENOMEM);
++
++	new->iommu = obj;
++	new->da_start = start;
++	new->da_end = start + bytes;
++	new->flags = flags;
++
++	/*
++	 * keep ascending order of iovmas
++	 */
++	if (tmp)
++		list_add_tail(&new->list, &tmp->list);
++	else
++		list_add(&new->list, &obj->mmap);
++
++	dev_dbg(obj->dev, "%s: found %08x-%08x-%08x(%x) %08x\n",
++		__func__, new->da_start, start, new->da_end, bytes, flags);
++
++	return new;
++}
++
++static void free_iovm_area(struct iommu *obj, struct iovm_struct *area)
++{
++	size_t bytes;
++
++	BUG_ON(!obj || !area);
++
++	bytes = area->da_end - area->da_start;
++
++	dev_dbg(obj->dev, "%s: %08x-%08x(%x) %08x\n",
++		__func__, area->da_start, area->da_end, bytes, area->flags);
++
++	list_del(&area->list);
++	kmem_cache_free(iovm_area_cachep, area);
++}
++
++/**
++ * da_to_va - convert (d) to (v)
++ * @obj:	objective iommu
++ * @da:		iommu device virtual address
++ * @va:		mpu virtual address
++ *
++ * Returns mpu virtual addr which corresponds to a given device virtual addr
++ */
++void *da_to_va(struct iommu *obj, u32 da)
++{
++	void *va = NULL;
++	struct iovm_struct *area;
++
++	mutex_lock(&obj->mmap_lock);
++
++	area = __find_iovm_area(obj, da);
++	if (!area) {
++		dev_warn(obj->dev, "%s: no da area(%08x)\n", __func__, da);
++		goto out;
++	}
++	va = area->va;
++	mutex_unlock(&obj->mmap_lock);
++out:
++	return va;
++}
++EXPORT_SYMBOL_GPL(da_to_va);
++
++static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va)
++{
++	unsigned int i;
++	struct scatterlist *sg;
++	void *va = _va;
++	void *va_end;
++
++	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
++		struct page *pg;
++		const size_t bytes = PAGE_SIZE;
++
++		/*
++		 * iommu 'superpage' isn't supported with 'iommu_vmalloc()'
++		 */
++		pg = vmalloc_to_page(va);
++		BUG_ON(!pg);
++		sg_set_page(sg, pg, bytes, 0);
++
++		va += bytes;
++	}
++
++	va_end = _va + PAGE_SIZE * i;
++	flush_cache_vmap(_va, va_end);
++}
++
++static inline void sgtable_drain_vmalloc(struct sg_table *sgt)
++{
++	/*
++	 * Actually this is not necessary at all, just exists for
++	 * consistency of the code readibility.
++	 */
++	BUG_ON(!sgt);
++}
++
++static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
++{
++	unsigned int i;
++	struct scatterlist *sg;
++	void *va;
++
++	va = phys_to_virt(pa);
++
++	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
++		size_t bytes;
++
++		bytes = iopgsz_max(len);
++
++		BUG_ON(!iopgsz_ok(bytes));
++
++		sg_set_buf(sg, phys_to_virt(pa), bytes);
++		/*
++		 * 'pa' is cotinuous(linear).
++		 */
++		pa += bytes;
++		len -= bytes;
++	}
++	BUG_ON(len);
++
++	clean_dcache_area(va, len);
++}
++
++static inline void sgtable_drain_kmalloc(struct sg_table *sgt)
++{
++	/*
++	 * Actually this is not necessary at all, just exists for
++	 * consistency of the code readibility
++	 */
++	BUG_ON(!sgt);
++}
++
++/* create 'da' <-> 'pa' mapping from 'sgt' */
++static int map_iovm_area(struct iommu *obj, struct iovm_struct *new,
++			 const struct sg_table *sgt, u32 flags)
++{
++	int err;
++	unsigned int i, j;
++	struct scatterlist *sg;
++	u32 da = new->da_start;
++
++	if (!obj || !new || !sgt)
++		return -EINVAL;
++
++	BUG_ON(!sgtable_ok(sgt));
++
++	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
++		u32 pa;
++		int pgsz;
++		size_t bytes;
++		struct iotlb_entry e;
++
++		pa = sg_phys(sg);
++		bytes = sg_dma_len(sg);
++
++		flags &= ~IOVMF_PGSZ_MASK;
++		pgsz = bytes_to_iopgsz(bytes);
++		if (pgsz < 0)
++			goto err_out;
++		flags |= pgsz;
++
++		pr_debug("%s: [%d] %08x %08x(%x)\n", __func__,
++			 i, da, pa, bytes);
++
++		iotlb_init_entry(&e, da, pa, flags);
++		err = iopgtable_store_entry(obj, &e);
++		if (err)
++			goto err_out;
++
++		da += bytes;
++	}
++	return 0;
++
++err_out:
++	da = new->da_start;
++
++	for_each_sg(sgt->sgl, sg, i, j) {
++		size_t bytes;
++
++		bytes = iopgtable_clear_entry(obj, da);
++
++		BUG_ON(!iopgsz_ok(bytes));
++
++		da += bytes;
++	}
++	return err;
++}
++
++/* release 'da' <-> 'pa' mapping */
++static void unmap_iovm_area(struct iommu *obj, struct iovm_struct *area)
++{
++	u32 start;
++	size_t total = area->da_end - area->da_start;
++
++	BUG_ON((!total) || !IS_ALIGNED(total, PAGE_SIZE));
++
++	start = area->da_start;
++	while (total > 0) {
++		size_t bytes;
++
++		bytes = iopgtable_clear_entry(obj, start);
++		if (bytes == 0)
++			bytes = PAGE_SIZE;
++		else
++			dev_dbg(obj->dev, "%s: unmap %08x(%x) %08x\n",
++				__func__, start, bytes, area->flags);
++
++		BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE));
++
++		total -= bytes;
++		start += bytes;
++	}
++	BUG_ON(total);
++}
++
++/* template function for all unmapping */
++static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da,
++				      void (*fn)(const void *), u32 flags)
++{
++	struct sg_table *sgt = NULL;
++	struct iovm_struct *area;
++
++	BUG_ON(in_interrupt());
++
++	if (!IS_ALIGNED(da, PAGE_SIZE)) {
++		dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da);
++		return NULL;
++	}
++
++	mutex_lock(&obj->mmap_lock);
++
++	area = __find_iovm_area(obj, da);
++	if (!area) {
++		dev_err(obj->dev, "%s: no da area(%08x)\n", __func__, da);
++		goto out;
++	}
++
++	if ((area->flags & flags) != flags) {
++		dev_err(obj->dev, "%s: wrong flags(%08x)\n", __func__,
++			area->flags);
++		goto out;
++	}
++	sgt = (struct sg_table *)area->sgt;
++
++	unmap_iovm_area(obj, area);
++
++	fn(area->va);
++
++	dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", __func__,
++		area->da_start, da, area->da_end,
++		area->da_end - area->da_start, area->flags);
++
++	free_iovm_area(obj, area);
++out:
++	mutex_unlock(&obj->mmap_lock);
++
++	return sgt;
++}
++
++static u32 map_iommu_region(struct iommu *obj, u32 da,
++	      const struct sg_table *sgt, void *va, size_t bytes, u32 flags)
++{
++	int err = -ENOMEM;
++	struct iovm_struct *new;
++
++	mutex_lock(&obj->mmap_lock);
++
++	new = alloc_iovm_area(obj, da, bytes, flags);
++	if (IS_ERR(new)) {
++		err = PTR_ERR(new);
++		goto err_alloc_iovma;
++	}
++	new->va = va;
++	new->sgt = sgt;
++
++	if (map_iovm_area(obj, new, sgt, new->flags))
++		goto err_map;
++
++	mutex_unlock(&obj->mmap_lock);
++
++	dev_dbg(obj->dev, "%s: da:%08x(%x) flags:%08x va:%p\n",
++		__func__, new->da_start, bytes, new->flags, va);
++
++	return new->da_start;
++
++err_map:
++	free_iovm_area(obj, new);
++err_alloc_iovma:
++	mutex_unlock(&obj->mmap_lock);
++	return err;
++}
++
++static inline u32 __iommu_vmap(struct iommu *obj, u32 da,
++		 const struct sg_table *sgt, void *va, size_t bytes, u32 flags)
++{
++	return map_iommu_region(obj, da, sgt, va, bytes, flags);
++}
++
++/**
++ * iommu_vmap  -  (d)-(p)-(v) address mapper
++ * @obj:	objective iommu
++ * @sgt:	address of scatter gather table
++ * @flags:	iovma and page property
++ *
++ * Creates 1-n-1 mapping with given @sgt and returns @da.
++ * All @sgt element must be io page size aligned.
++ */
++u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
++		 u32 flags)
++{
++	size_t bytes;
++	void *va;
++
++	if (!obj || !obj->dev || !sgt)
++		return -EINVAL;
++
++	bytes = sgtable_len(sgt);
++	if (!bytes)
++		return -EINVAL;
++	bytes = PAGE_ALIGN(bytes);
++
++	va = vmap_sg(sgt);
++	if (IS_ERR(va))
++		return PTR_ERR(va);
++
++	flags &= IOVMF_HW_MASK;
++	flags |= IOVMF_DISCONT;
++	flags |= IOVMF_MMIO;
++	flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
++
++	da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
++	if (IS_ERR_VALUE(da))
++		vunmap_sg(va);
++
++	return da;
++}
++EXPORT_SYMBOL_GPL(iommu_vmap);
++
++/**
++ * iommu_vunmap  -  release virtual mapping obtained by 'iommu_vmap()'
++ * @obj:	objective iommu
++ * @da:		iommu device virtual address
++ *
++ * Free the iommu virtually contiguous memory area starting at
++ * @da, which was returned by 'iommu_vmap()'.
++ */
++struct sg_table *iommu_vunmap(struct iommu *obj, u32 da)
++{
++	struct sg_table *sgt;
++	/*
++	 * 'sgt' is allocated before 'iommu_vmalloc()' is called.
++	 * Just returns 'sgt' to the caller to free
++	 */
++	sgt = unmap_vm_area(obj, da, vunmap_sg, IOVMF_DISCONT | IOVMF_MMIO);
++	if (!sgt)
++		dev_err(obj->dev, "%s: No sgt\n", __func__);
++	return sgt;
++}
++EXPORT_SYMBOL_GPL(iommu_vunmap);
++
++/**
++ * iommu_vmalloc  -  (d)-(p)-(v) address allocator and mapper
++ * @obj:	objective iommu
++ * @da:		contiguous iommu virtual memory
++ * @bytes:	allocation size
++ * @flags:	iovma and page property
++ *
++ * Allocate @bytes linearly and creates 1-n-1 mapping and returns
++ * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
++ */
++u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
++{
++	void *va;
++	struct sg_table *sgt;
++
++	if (!obj || !obj->dev || !bytes)
++		return -EINVAL;
++
++	bytes = PAGE_ALIGN(bytes);
++
++	va = vmalloc(bytes);
++	if (!va)
++		return -ENOMEM;
++
++	sgt = sgtable_alloc(bytes, flags);
++	if (IS_ERR(sgt)) {
++		da = PTR_ERR(sgt);
++		goto err_sgt_alloc;
++	}
++	sgtable_fill_vmalloc(sgt, va);
++
++	flags &= IOVMF_HW_MASK;
++	flags |= IOVMF_DISCONT;
++	flags |= IOVMF_ALLOC;
++	flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
++
++	da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
++	if (IS_ERR_VALUE(da))
++		goto err_iommu_vmap;
++
++	return da;
++
++err_iommu_vmap:
++	sgtable_drain_vmalloc(sgt);
++	sgtable_free(sgt);
++err_sgt_alloc:
++	vfree(va);
++	return da;
++}
++EXPORT_SYMBOL_GPL(iommu_vmalloc);
++
++/**
++ * iommu_vfree  -  release memory allocated by 'iommu_vmalloc()'
++ * @obj:	objective iommu
++ * @da:		iommu device virtual address
++ *
++ * Frees the iommu virtually continuous memory area starting at
++ * @da, as obtained from 'iommu_vmalloc()'.
++ */
++void iommu_vfree(struct iommu *obj, const u32 da)
++{
++	struct sg_table *sgt;
++
++	sgt = unmap_vm_area(obj, da, vfree, IOVMF_DISCONT | IOVMF_ALLOC);
++	if (!sgt)
++		dev_err(obj->dev, "%s: No sgt\n", __func__);
++	sgtable_free(sgt);
++}
++EXPORT_SYMBOL_GPL(iommu_vfree);
++
++static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va,
++			  size_t bytes, u32 flags)
++{
++	struct sg_table *sgt;
++
++	sgt = sgtable_alloc(bytes, flags);
++	if (IS_ERR(sgt))
++		return PTR_ERR(sgt);
++
++	sgtable_fill_kmalloc(sgt, pa, bytes);
++
++	da = map_iommu_region(obj, da, sgt, va, bytes, flags);
++	if (IS_ERR_VALUE(da)) {
++		sgtable_drain_kmalloc(sgt);
++		sgtable_free(sgt);
++	}
++
++	return da;
++}
++
++/**
++ * iommu_kmap  -  (d)-(p)-(v) address mapper
++ * @obj:	objective iommu
++ * @da:		contiguous iommu virtual memory
++ * @pa:		contiguous physical memory
++ * @flags:	iovma and page property
++ *
++ * Creates 1-1-1 mapping and returns @da again, which can be
++ * adjusted if 'IOVMF_DA_ANON' is set.
++ */
++u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
++		 u32 flags)
++{
++	void *va;
++
++	if (!obj || !obj->dev || !bytes)
++		return -EINVAL;
++
++	bytes = PAGE_ALIGN(bytes);
++
++	va = ioremap(pa, bytes);
++	if (!va)
++		return -ENOMEM;
++
++	flags &= IOVMF_HW_MASK;
++	flags |= IOVMF_LINEAR;
++	flags |= IOVMF_MMIO;
++	flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
++
++	da = __iommu_kmap(obj, da, pa, va, bytes, flags);
++	if (IS_ERR_VALUE(da))
++		iounmap(va);
++
++	return da;
++}
++EXPORT_SYMBOL_GPL(iommu_kmap);
++
++/**
++ * iommu_kunmap  -  release virtual mapping obtained by 'iommu_kmap()'
++ * @obj:	objective iommu
++ * @da:		iommu device virtual address
++ *
++ * Frees the iommu virtually contiguous memory area starting at
++ * @da, which was passed to and was returned by'iommu_kmap()'.
++ */
++void iommu_kunmap(struct iommu *obj, u32 da)
++{
++	struct sg_table *sgt;
++
++	sgt = unmap_vm_area(obj, da, __iounmap, IOVMF_LINEAR | IOVMF_MMIO);
++	if (!sgt)
++		dev_err(obj->dev, "%s: No sgt\n", __func__);
++	sgtable_free(sgt);
++}
++EXPORT_SYMBOL_GPL(iommu_kunmap);
++
++/**
++ * iommu_kmalloc  -  (d)-(p)-(v) address allocator and mapper
++ * @obj:	objective iommu
++ * @da:		contiguous iommu virtual memory
++ * @bytes:	bytes for allocation
++ * @flags:	iovma and page property
++ *
++ * Allocate @bytes linearly and creates 1-1-1 mapping and returns
++ * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
++ */
++u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
++{
++	void *va;
++	u32 pa;
++
++	if (!obj || !obj->dev || !bytes)
++		return -EINVAL;
++
++	bytes = PAGE_ALIGN(bytes);
++
++	va = kmalloc(bytes, GFP_KERNEL | GFP_DMA);
++	if (!va)
++		return -ENOMEM;
++	pa = virt_to_phys(va);
++
++	flags &= IOVMF_HW_MASK;
++	flags |= IOVMF_LINEAR;
++	flags |= IOVMF_ALLOC;
++	flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
++
++	da = __iommu_kmap(obj, da, pa, va, bytes, flags);
++	if (IS_ERR_VALUE(da))
++		kfree(va);
++
++	return da;
++}
++EXPORT_SYMBOL_GPL(iommu_kmalloc);
++
++/**
++ * iommu_kfree  -  release virtual mapping obtained by 'iommu_kmalloc()'
++ * @obj:	objective iommu
++ * @da:		iommu device virtual address
++ *
++ * Frees the iommu virtually contiguous memory area starting at
++ * @da, which was passed to and was returned by'iommu_kmalloc()'.
++ */
++void iommu_kfree(struct iommu *obj, u32 da)
++{
++	struct sg_table *sgt;
++
++	sgt = unmap_vm_area(obj, da, kfree, IOVMF_LINEAR | IOVMF_ALLOC);
++	if (!sgt)
++		dev_err(obj->dev, "%s: No sgt\n", __func__);
++	sgtable_free(sgt);
++}
++EXPORT_SYMBOL_GPL(iommu_kfree);
++
++
++static int __init iovmm_init(void)
++{
++	const unsigned long flags = SLAB_HWCACHE_ALIGN;
++	struct kmem_cache *p;
++
++	p = kmem_cache_create("iovm_area_cache", sizeof(struct iovm_struct), 0,
++			      flags, NULL);
++	if (!p)
++		return -ENOMEM;
++	iovm_area_cachep = p;
++
++	return 0;
++}
++module_init(iovmm_init);
++
++static void __exit iovmm_exit(void)
++{
++	kmem_cache_destroy(iovm_area_cachep);
++}
++module_exit(iovmm_exit);
++
++MODULE_DESCRIPTION("omap iommu: simple virtual address space management");
++MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0005-omap-iommu-entries-for-Kconfig-and-Makefile.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0005-omap-iommu-entries-for-Kconfig-and-Makefile.patch
new file mode 100644
index 0000000000..c0f9e4d9ac
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0005-omap-iommu-entries-for-Kconfig-and-Makefile.patch
@@ -0,0 +1,45 @@
+From 7de046a6a8446358001c38ad1d0b2b829ca0c98c Mon Sep 17 00:00:00 2001
+From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+Date: Wed, 28 Jan 2009 21:32:08 +0200
+Subject: [PATCH] omap iommu: entries for Kconfig and Makefile
+
+Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+---
+ arch/arm/plat-omap/Kconfig  |    8 ++++++++
+ arch/arm/plat-omap/Makefile |    1 +
+ 2 files changed, 9 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
+index b16ae76..2090bb5 100644
+--- a/arch/arm/plat-omap/Kconfig
++++ b/arch/arm/plat-omap/Kconfig
+@@ -176,6 +176,14 @@ config OMAP_MBOX_FWK
+ 	  Say Y here if you want to use OMAP Mailbox framework support for
+ 	  DSP, IVA1.0 and IVA2 in OMAP1/2/3.
+ 
++config OMAP_IOMMU
++	tristate "IOMMU support"
++	depends on ARCH_OMAP
++	default n
++	help
++	  Say Y here if you want to use OMAP IOMMU support for IVA2 and
++	  Camera in OMAP3.
++
+ choice
+         prompt "System timer"
+ 	default OMAP_MPU_TIMER
+diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
+index 3ebc09e..aa8f6df 100644
+--- a/arch/arm/plat-omap/Makefile
++++ b/arch/arm/plat-omap/Makefile
+@@ -13,6 +13,7 @@ obj-  :=
+ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
+ 
+ obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
++obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o
+ 
+ obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
+ obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0006-omap-iommu-Don-t-try-BUG_ON-in_interrupt.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0006-omap-iommu-Don-t-try-BUG_ON-in_interrupt.patch
new file mode 100644
index 0000000000..54a7abfe85
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0006-omap-iommu-Don-t-try-BUG_ON-in_interrupt.patch
@@ -0,0 +1,26 @@
+From b03f695e25bbdaa95a2cc87e15ee8592e7ca128d Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Feb 2009 18:01:29 +0200
+Subject: [PATCH] omap iommu: Don't try BUG_ON(in_interrupt())
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ arch/arm/plat-omap/iovmm.c |    2 --
+ 1 files changed, 0 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
+index 6726d10..bdfbb09 100644
+--- a/arch/arm/plat-omap/iovmm.c
++++ b/arch/arm/plat-omap/iovmm.c
+@@ -523,8 +523,6 @@ static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da,
+ 	struct sg_table *sgt = NULL;
+ 	struct iovm_struct *area;
+ 
+-	BUG_ON(in_interrupt());
+-
+ 	if (!IS_ALIGNED(da, PAGE_SIZE)) {
+ 		dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da);
+ 		return NULL;
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0007-omap-iommu-We-support-chained-scatterlists-probabl.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0007-omap-iommu-We-support-chained-scatterlists-probabl.patch
new file mode 100644
index 0000000000..d8ad0eb0b7
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0007-omap-iommu-We-support-chained-scatterlists-probabl.patch
@@ -0,0 +1,24 @@
+From 24f984f784cae1a4515fe1be8db1ac24cdf51e84 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Feb 2009 18:37:41 +0200
+Subject: [PATCH] omap iommu: We support chained scatterlists, probably. :)
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ arch/arm/include/asm/scatterlist.h |    2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/include/asm/scatterlist.h b/arch/arm/include/asm/scatterlist.h
+index ca0a37d..393f8b8 100644
+--- a/arch/arm/include/asm/scatterlist.h
++++ b/arch/arm/include/asm/scatterlist.h
+@@ -24,4 +24,6 @@ struct scatterlist {
+ #define sg_dma_address(sg)      ((sg)->dma_address)
+ #define sg_dma_len(sg)          ((sg)->length)
+ 
++#define ARCH_HAS_SG_CHAIN
++
+ #endif /* _ASMARM_SCATTERLIST_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0008-omap2-iommu-entries-for-Kconfig-and-Makefile.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0008-omap2-iommu-entries-for-Kconfig-and-Makefile.patch
new file mode 100644
index 0000000000..298e797c37
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/iommu/0008-omap2-iommu-entries-for-Kconfig-and-Makefile.patch
@@ -0,0 +1,29 @@
+From 3c65ff4a684d3e0f4d9c59e731975408452c3743 Mon Sep 17 00:00:00 2001
+From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+Date: Wed, 28 Jan 2009 21:32:09 +0200
+Subject: [PATCH] omap2 iommu: entries for Kconfig and Makefile
+
+Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+---
+ arch/arm/mach-omap2/Makefile |    5 +++++
+ 1 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index b44bb78..33b5aa8 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -38,6 +38,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o
+ obj-$(CONFIG_OMAP_MBOX_FWK)	+= mailbox_mach.o
+ mailbox_mach-objs		:= mailbox.o
+ 
++iommu-y					+= iommu2.o
++iommu-$(CONFIG_ARCH_OMAP3)		+= omap3-iommu.o
++
++obj-$(CONFIG_OMAP_IOMMU)		+= $(iommu-y)
++
+ # Specific board support
+ obj-$(CONFIG_MACH_OMAP_GENERIC)		+= board-generic.o
+ obj-$(CONFIG_MACH_OMAP_H4)		+= board-h4.o board-h4-mmc.o
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0001-omap3isp-Add-ISP-main-driver-and-register-definitio.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0001-omap3isp-Add-ISP-main-driver-and-register-definitio.patch
new file mode 100644
index 0000000000..e6e07d8afc
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0001-omap3isp-Add-ISP-main-driver-and-register-definitio.patch
@@ -0,0 +1,4625 @@
+From 77c99cd863b906c803c3dec08753c19bf9b67882 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:02 +0200
+Subject: [PATCH] omap3isp: Add ISP main driver and register definitions
+
+TODO:
+
+- Release resoures in isp_probe() if something fails.
+
+- Implement a sensible generic interface so that the ISP can offer a
+  v4l2_subdev (like the v4l2-int-device slaves) interface towards the
+  camera driver.
+
+- Handle CSI1 and CSI2 error cases (currently unhandled?).
+
+- Fix H3A / HIST interrupt enabling / disabling.
+
+- Clean up the private ioctls.
+
+- Handle SBL overflows somehow.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ drivers/media/video/Makefile     |    2 +
+ drivers/media/video/isp/Makefile |   12 +
+ drivers/media/video/isp/isp.c    | 2547 ++++++++++++++++++++++++++++++++++++++
+ drivers/media/video/isp/isp.h    |  318 +++++
+ drivers/media/video/isp/ispreg.h | 1674 +++++++++++++++++++++++++
+ 5 files changed, 4553 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/isp/Makefile
+ create mode 100644 drivers/media/video/isp/isp.c
+ create mode 100644 drivers/media/video/isp/isp.h
+ create mode 100644 drivers/media/video/isp/ispreg.h
+
+diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
+index 72f6d03..e654270 100644
+--- a/drivers/media/video/Makefile
++++ b/drivers/media/video/Makefile
+@@ -106,6 +106,8 @@ obj-$(CONFIG_VIDEO_CX2341X) += cx2341x.o
+ obj-$(CONFIG_VIDEO_CAFE_CCIC) += cafe_ccic.o
+ obj-$(CONFIG_VIDEO_OV7670) 	+= ov7670.o
+ 
++obj-y				+= isp/
++
+ obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
+ 
+ obj-$(CONFIG_USB_DABUSB)        += dabusb.o
+diff --git a/drivers/media/video/isp/Makefile b/drivers/media/video/isp/Makefile
+new file mode 100644
+index 0000000..f14d617
+--- /dev/null
++++ b/drivers/media/video/isp/Makefile
+@@ -0,0 +1,12 @@
++# Makefile for OMAP3 ISP driver
++
++ifdef CONFIG_ARCH_OMAP3410
++isp-mod-objs += \
++	isp.o ispccdc.o
++else
++isp-mod-objs += \
++	isp.o ispccdc.o ispmmu.o \
++	isppreview.o ispresizer.o isph3a.o isphist.o isp_af.o ispcsi2.o
++endif
++
++obj-$(CONFIG_VIDEO_OMAP3) += isp-mod.o
+diff --git a/drivers/media/video/isp/isp.c b/drivers/media/video/isp/isp.c
+new file mode 100644
+index 0000000..54c839b
+--- /dev/null
++++ b/drivers/media/video/isp/isp.c
+@@ -0,0 +1,2547 @@
++/*
++ * isp.c
++ *
++ * Driver Library for ISP Control module in TI's OMAP3 Camera ISP
++ * ISP interface and IRQ related APIs are defined here.
++ *
++ * Copyright (C) 2009 Texas Instruments.
++ * Copyright (C) 2009 Nokia.
++ *
++ * Contributors:
++ * 	Sameer Venkatraman <sameerv@ti.com>
++ * 	Mohit Jalori <mjalori@ti.com>
++ * 	Sergio Aguirre <saaguirre@ti.com>
++ * 	Sakari Ailus <sakari.ailus@nokia.com>
++ * 	Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
++ *	Toni Leinonen <toni.leinonen@nokia.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <asm/cacheflush.h>
++
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/platform_device.h>
++
++#include "isp.h"
++#include "ispmmu.h"
++#include "ispreg.h"
++#include "ispccdc.h"
++#include "isph3a.h"
++#include "isphist.h"
++#include "isp_af.h"
++#include "isppreview.h"
++#include "ispresizer.h"
++#include "ispcsi2.h"
++
++static struct isp_device *omap3isp;
++
++static int isp_try_size(struct v4l2_pix_format *pix_input,
++			struct v4l2_pix_format *pix_output);
++
++static void isp_save_ctx(void);
++
++static void isp_restore_ctx(void);
++
++static void isp_buf_init(void);
++
++/* List of image formats supported via OMAP ISP */
++const static struct v4l2_fmtdesc isp_formats[] = {
++	{
++		.description = "UYVY, packed",
++		.pixelformat = V4L2_PIX_FMT_UYVY,
++	},
++	{
++		.description = "YUYV (YUV 4:2:2), packed",
++		.pixelformat = V4L2_PIX_FMT_YUYV,
++	},
++	{
++		.description = "Bayer10 (GrR/BGb)",
++		.pixelformat = V4L2_PIX_FMT_SGRBG10,
++	},
++};
++
++/* ISP Crop capabilities */
++static struct v4l2_rect ispcroprect;
++static struct v4l2_rect cur_rect;
++
++/**
++ * struct vcontrol - Video control structure.
++ * @qc: V4L2 Query control structure.
++ * @current_value: Current value of the control.
++ */
++static struct vcontrol {
++	struct v4l2_queryctrl qc;
++	int current_value;
++} video_control[] = {
++	{
++		{
++			.id = V4L2_CID_BRIGHTNESS,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Brightness",
++			.minimum = ISPPRV_BRIGHT_LOW,
++			.maximum = ISPPRV_BRIGHT_HIGH,
++			.step = ISPPRV_BRIGHT_STEP,
++			.default_value = ISPPRV_BRIGHT_DEF,
++		},
++		.current_value = ISPPRV_BRIGHT_DEF,
++	},
++	{
++		{
++			.id = V4L2_CID_CONTRAST,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Contrast",
++			.minimum = ISPPRV_CONTRAST_LOW,
++			.maximum = ISPPRV_CONTRAST_HIGH,
++			.step = ISPPRV_CONTRAST_STEP,
++			.default_value = ISPPRV_CONTRAST_DEF,
++		},
++		.current_value = ISPPRV_CONTRAST_DEF,
++	},
++	{
++		{
++			.id = V4L2_CID_COLORFX,
++			.type = V4L2_CTRL_TYPE_MENU,
++			.name = "Color Effects",
++			.minimum = V4L2_COLORFX_NONE,
++			.maximum = V4L2_COLORFX_SEPIA,
++			.step = 1,
++			.default_value = V4L2_COLORFX_NONE,
++		},
++		.current_value = V4L2_COLORFX_NONE,
++	}
++};
++
++static struct v4l2_querymenu video_menu[] = {
++	{
++		.id = V4L2_CID_COLORFX,
++		.index = 0,
++		.name = "None",
++	},
++	{
++		.id = V4L2_CID_COLORFX,
++		.index = 1,
++		.name = "B&W",
++	},
++	{
++		.id = V4L2_CID_COLORFX,
++		.index = 2,
++		.name = "Sepia",
++	},
++};
++
++struct isp_buf {
++	dma_addr_t isp_addr;
++	void (*complete)(struct videobuf_buffer *vb, void *priv);
++	struct videobuf_buffer *vb;
++	void *priv;
++	u32 vb_state;
++};
++
++#define ISP_BUFS_IS_FULL(bufs)					\
++	(((bufs)->queue + 1) % NUM_BUFS == (bufs)->done)
++#define ISP_BUFS_IS_EMPTY(bufs)		((bufs)->queue == (bufs)->done)
++#define ISP_BUFS_IS_LAST(bufs)					\
++	((bufs)->queue == ((bufs)->done + 1) % NUM_BUFS)
++#define ISP_BUFS_QUEUED(bufs)						\
++	((((bufs)->done - (bufs)->queue + NUM_BUFS)) % NUM_BUFS)
++#define ISP_BUF_DONE(bufs)		((bufs)->buf + (bufs)->done)
++#define ISP_BUF_NEXT_DONE(bufs)				\
++	((bufs)->buf + ((bufs)->done + 1) % NUM_BUFS)
++#define ISP_BUF_QUEUE(bufs)		((bufs)->buf + (bufs)->queue)
++#define ISP_BUF_MARK_DONE(bufs)				\
++	(bufs)->done = ((bufs)->done + 1) % NUM_BUFS;
++#define ISP_BUF_MARK_QUEUED(bufs)			\
++	(bufs)->queue = ((bufs)->queue + 1) % NUM_BUFS;
++
++struct isp_bufs {
++	dma_addr_t isp_addr_capture[VIDEO_MAX_FRAME];
++	spinlock_t lock;	/* For handling current buffer */
++	/* queue full: (ispsg.queue + 1) % NUM_BUFS == ispsg.done
++	   queue empty: ispsg.queue == ispsg.done */
++	struct isp_buf buf[NUM_BUFS];
++	/* Next slot to queue a buffer. */
++	int queue;
++	/* Buffer that is being processed. */
++	int done;
++	/* Wait for this many hs_vs before anything else. */
++	int wait_hs_vs;
++};
++
++/**
++ * struct ispirq - Structure for containing callbacks to be called in ISP ISR.
++ * @isp_callbk: Array which stores callback functions, indexed by the type of
++ *              callback (8 possible types).
++ * @isp_callbk_arg1: Pointer to array containing pointers to the first argument
++ *                   to be passed to the requested callback function.
++ * @isp_callbk_arg2: Pointer to array containing pointers to the second
++ *                   argument to be passed to the requested callback function.
++ *
++ * This structure is used to contain all the callback functions related for
++ * each callback type (CBK_CCDC_VD0, CBK_CCDC_VD1, CBK_PREV_DONE,
++ * CBK_RESZ_DONE, CBK_MMU_ERR, CBK_H3A_AWB_DONE, CBK_HIST_DONE, CBK_HS_VS,
++ * CBK_LSC_ISR).
++ */
++struct isp_irq {
++	isp_callback_t isp_callbk[CBK_END];
++	isp_vbq_callback_ptr isp_callbk_arg1[CBK_END];
++	void *isp_callbk_arg2[CBK_END];
++};
++
++/**
++ * struct ispmodule - Structure for storing ISP sub-module information.
++ * @isp_pipeline: Bit mask for submodules enabled within the ISP.
++ * @applyCrop: Flag to do a crop operation when video buffer queue ISR is done
++ * @pix: Structure containing the format and layout of the output image.
++ * @ccdc_input_width: ISP CCDC module input image width.
++ * @ccdc_input_height: ISP CCDC module input image height.
++ * @ccdc_output_width: ISP CCDC module output image width.
++ * @ccdc_output_height: ISP CCDC module output image height.
++ * @preview_input_width: ISP Preview module input image width.
++ * @preview_input_height: ISP Preview module input image height.
++ * @preview_output_width: ISP Preview module output image width.
++ * @preview_output_height: ISP Preview module output image height.
++ * @resizer_input_width: ISP Resizer module input image width.
++ * @resizer_input_height: ISP Resizer module input image height.
++ * @resizer_output_width: ISP Resizer module output image width.
++ * @resizer_output_height: ISP Resizer module output image height.
++ */
++struct isp_module {
++	unsigned int isp_pipeline;
++	int applyCrop;
++	struct v4l2_pix_format pix;
++	unsigned int ccdc_input_width;
++	unsigned int ccdc_input_height;
++	unsigned int ccdc_output_width;
++	unsigned int ccdc_output_height;
++	unsigned int preview_input_width;
++	unsigned int preview_input_height;
++	unsigned int preview_output_width;
++	unsigned int preview_output_height;
++	unsigned int resizer_input_width;
++	unsigned int resizer_input_height;
++	unsigned int resizer_output_width;
++	unsigned int resizer_output_height;
++};
++
++#define RAW_CAPTURE(isp)					\
++	(!((isp)->module.isp_pipeline & OMAP_ISP_PREVIEW))
++
++/**
++ * struct isp - Structure for storing ISP Control module information
++ * @lock: Spinlock to sync between isr and processes.
++ * @isp_mutex: Semaphore used to get access to the ISP.
++ * @ref_count: Reference counter.
++ * @cam_ick: Pointer to ISP Interface clock.
++ * @cam_fck: Pointer to ISP Functional clock.
++ *
++ * This structure is used to store the OMAP ISP Control Information.
++ */
++static struct isp {
++	spinlock_t lock;	/* For handling registered ISP callbacks */
++	struct mutex isp_mutex;	/* For handling ref_count field */
++	int ref_count;
++	struct clk *cam_ick;
++	struct clk *cam_mclk;
++	struct clk *csi2_fck;
++	struct isp_interface_config *config;
++	dma_addr_t tmp_buf;
++	size_t tmp_buf_size;
++	unsigned long tmp_buf_offset;
++	struct isp_bufs bufs;
++	struct isp_irq irq;
++	struct isp_module module;
++} isp_obj;
++
++/* Structure for saving/restoring ISP module registers */
++static struct isp_reg isp_reg_list[] = {
++	{OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_GRESET_LENGTH, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_PSTRB_REPLAY, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_FRAME, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_PSTRB_DELAY, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_STRB_DELAY, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_SHUT_DELAY, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_PSTRB_LENGTH, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_STRB_LENGTH, 0},
++	{OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_SHUT_LENGTH, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF_SYSCONFIG, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF_IRQENABLE, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_CTRL, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_CTRL, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_START, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_START, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_END, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_END, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_WINDOWSIZE, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_WINDOWSIZE, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_THRESHOLD, 0},
++	{OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_THRESHOLD, 0},
++	{0, ISP_TOK_TERM, 0}
++};
++
++u32 isp_reg_readl(enum isp_mem_resources isp_mmio_range, u32 reg_offset)
++{
++	return __raw_readl(omap3isp->mmio_base[isp_mmio_range] + reg_offset);
++}
++EXPORT_SYMBOL(isp_reg_readl);
++
++void isp_reg_writel(u32 reg_value, enum isp_mem_resources isp_mmio_range,
++		    u32 reg_offset)
++{
++	__raw_writel(reg_value,
++		     omap3isp->mmio_base[isp_mmio_range] + reg_offset);
++}
++EXPORT_SYMBOL(isp_reg_writel);
++
++/*
++ *
++ * V4L2 Handling
++ *
++ */
++
++/**
++ * find_vctrl - Returns the index of the ctrl array of the requested ctrl ID.
++ * @id: Requested control ID.
++ *
++ * Returns 0 if successful, -EINVAL if not found, or -EDOM if its out of
++ * domain.
++ **/
++static int find_vctrl(int id)
++{
++	int i;
++
++	if (id < V4L2_CID_BASE)
++		return -EDOM;
++
++	for (i = (ARRAY_SIZE(video_control) - 1); i >= 0; i--)
++		if (video_control[i].qc.id == id)
++			break;
++
++	if (i < 0)
++		i = -EINVAL;
++
++	return i;
++}
++
++static int find_next_vctrl(int id)
++{
++	int i;
++	u32 best = (u32)-1;
++
++	for (i = 0; i < ARRAY_SIZE(video_control); i++) {
++		if (video_control[i].qc.id > id &&
++		    (best == (u32)-1 ||
++		     video_control[i].qc.id <
++		     video_control[best].qc.id)) {
++			best = i;
++		}
++	}
++
++	if (best == (u32)-1)
++		return -EINVAL;
++
++	return best;
++}
++
++/**
++ * find_vmenu - Returns index of the menu array of the requested ctrl option.
++ * @id: Requested control ID.
++ * @index: Requested menu option index.
++ *
++ * Returns 0 if successful, -EINVAL if not found, or -EDOM if its out of
++ * domain.
++ **/
++static int find_vmenu(int id, int index)
++{
++	int i;
++
++	if (id < V4L2_CID_BASE)
++		return -EDOM;
++
++	for (i = (ARRAY_SIZE(video_menu) - 1); i >= 0; i--) {
++		if (video_menu[i].id != id || video_menu[i].index != index)
++			continue;
++		return i;
++	}
++
++	return -EINVAL;
++}
++
++/**
++ * isp_release_resources - Free ISP submodules
++ **/
++static void isp_release_resources(void)
++{
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_CCDC)
++		ispccdc_free();
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW)
++		isppreview_free();
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER)
++		ispresizer_free();
++	return;
++}
++
++static int isp_wait(int (*busy)(void), int wait_for_busy, int max_wait)
++{
++	int wait = 0;
++
++	if (max_wait == 0)
++		max_wait = 10000; /* 10 ms */
++
++	while ((wait_for_busy && !busy())
++	       || (!wait_for_busy && busy())) {
++		rmb();
++		udelay(1);
++		wait++;
++		if (wait > max_wait) {
++			printk(KERN_ALERT "%s: wait is too much\n", __func__);
++			return -EBUSY;
++		}
++	}
++	DPRINTK_ISPCTRL(KERN_ALERT "%s: wait %d\n", __func__, wait);
++
++	return 0;
++}
++
++static int ispccdc_sbl_wait_idle(int max_wait)
++{
++	return isp_wait(ispccdc_sbl_busy, 0, max_wait);
++}
++
++static void isp_enable_interrupts(int is_raw)
++{
++	isp_reg_writel(-1, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
++	isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++		   IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ |
++		   IRQ0ENABLE_HS_VS_IRQ |
++		   IRQ0ENABLE_CCDC_VD0_IRQ |
++		   IRQ0ENABLE_CCDC_VD1_IRQ);
++
++	if (is_raw)
++		return;
++
++	isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++		   IRQ0ENABLE_PRV_DONE_IRQ |
++		   IRQ0ENABLE_RSZ_DONE_IRQ);
++
++	return;
++}
++
++static void isp_disable_interrupts(void)
++{
++	isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++		    ~(IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ |
++		      IRQ0ENABLE_HS_VS_IRQ |
++		      IRQ0ENABLE_CCDC_VD0_IRQ |
++		      IRQ0ENABLE_CCDC_VD1_IRQ |
++		      IRQ0ENABLE_PRV_DONE_IRQ |
++		      IRQ0ENABLE_RSZ_DONE_IRQ));
++}
++
++/**
++ * isp_set_callback - Sets the callback for the ISP module done events.
++ * @type: Type of the event for which callback is requested.
++ * @callback: Method to be called as callback in the ISR context.
++ * @arg1: First argument to be passed when callback is called in ISR.
++ * @arg2: Second argument to be passed when callback is called in ISR.
++ *
++ * This function sets a callback function for a done event in the ISP
++ * module, and enables the corresponding interrupt.
++ **/
++int isp_set_callback(enum isp_callback_type type, isp_callback_t callback,
++		     isp_vbq_callback_ptr arg1,
++		     void *arg2)
++{
++	unsigned long irqflags = 0;
++
++	if (callback == NULL) {
++		DPRINTK_ISPCTRL("ISP_ERR : Null Callback\n");
++		return -EINVAL;
++	}
++
++	spin_lock_irqsave(&isp_obj.lock, irqflags);
++	isp_obj.irq.isp_callbk[type] = callback;
++	isp_obj.irq.isp_callbk_arg1[type] = arg1;
++	isp_obj.irq.isp_callbk_arg2[type] = arg2;
++	spin_unlock_irqrestore(&isp_obj.lock, irqflags);
++
++	switch (type) {
++	case CBK_H3A_AWB_DONE:
++		isp_reg_writel(IRQ0ENABLE_H3A_AWB_DONE_IRQ,
++			       OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
++		isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			   IRQ0ENABLE_H3A_AWB_DONE_IRQ);
++		break;
++	case CBK_H3A_AF_DONE:
++		isp_reg_writel(IRQ0ENABLE_H3A_AF_DONE_IRQ,
++			       OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
++		isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			   IRQ0ENABLE_H3A_AF_DONE_IRQ);
++		break;
++	case CBK_HIST_DONE:
++		isp_reg_writel(IRQ0ENABLE_HIST_DONE_IRQ,
++			       OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
++		isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			   IRQ0ENABLE_HIST_DONE_IRQ);
++		break;
++	case CBK_PREV_DONE:
++		isp_reg_writel(IRQ0ENABLE_PRV_DONE_IRQ,
++			       OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
++		isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			   IRQ0ENABLE_PRV_DONE_IRQ);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_set_callback);
++
++/**
++ * isp_unset_callback - Clears the callback for the ISP module done events.
++ * @type: Type of the event for which callback to be cleared.
++ *
++ * This function clears a callback function for a done event in the ISP
++ * module, and disables the corresponding interrupt.
++ **/
++int isp_unset_callback(enum isp_callback_type type)
++{
++	unsigned long irqflags = 0;
++
++	spin_lock_irqsave(&isp_obj.lock, irqflags);
++	isp_obj.irq.isp_callbk[type] = NULL;
++	isp_obj.irq.isp_callbk_arg1[type] = NULL;
++	isp_obj.irq.isp_callbk_arg2[type] = NULL;
++	spin_unlock_irqrestore(&isp_obj.lock, irqflags);
++
++	switch (type) {
++	case CBK_H3A_AWB_DONE:
++		isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			    ~IRQ0ENABLE_H3A_AWB_DONE_IRQ);
++		break;
++	case CBK_H3A_AF_DONE:
++		isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			    ~IRQ0ENABLE_H3A_AF_DONE_IRQ);
++		break;
++	case CBK_HIST_DONE:
++		isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			    ~IRQ0ENABLE_HIST_DONE_IRQ);
++		break;
++	case CBK_CSIA:
++		isp_csi2_irq_set(0);
++		break;
++	case CBK_CSIB:
++		isp_reg_writel(IRQ0ENABLE_CSIB_IRQ, OMAP3_ISP_IOMEM_MAIN,
++			       ISP_IRQ0STATUS);
++		isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			   IRQ0ENABLE_CSIB_IRQ);
++		break;
++	case CBK_PREV_DONE:
++		isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++			    ~IRQ0ENABLE_PRV_DONE_IRQ);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_unset_callback);
++
++/**
++ * isp_set_xclk - Configures the specified cam_xclk to the desired frequency.
++ * @xclk: Desired frequency of the clock in Hz.
++ * @xclksel: XCLK to configure (0 = A, 1 = B).
++ *
++ * Configures the specified MCLK divisor in the ISP timing control register
++ * (TCTRL_CTRL) to generate the desired xclk clock value.
++ *
++ * Divisor = CM_CAM_MCLK_HZ / xclk
++ *
++ * Returns the final frequency that is actually being generated
++ **/
++u32 isp_set_xclk(u32 xclk, u8 xclksel)
++{
++	u32 divisor;
++	u32 currentxclk;
++
++	if (xclk >= CM_CAM_MCLK_HZ) {
++		divisor = ISPTCTRL_CTRL_DIV_BYPASS;
++		currentxclk = CM_CAM_MCLK_HZ;
++	} else if (xclk >= 2) {
++		divisor = CM_CAM_MCLK_HZ / xclk;
++		if (divisor >= ISPTCTRL_CTRL_DIV_BYPASS)
++			divisor = ISPTCTRL_CTRL_DIV_BYPASS - 1;
++		currentxclk = CM_CAM_MCLK_HZ / divisor;
++	} else {
++		divisor = xclk;
++		currentxclk = 0;
++	}
++
++	switch (xclksel) {
++	case 0:
++		isp_reg_and_or(OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
++			       ~ISPTCTRL_CTRL_DIVA_MASK,
++			       divisor << ISPTCTRL_CTRL_DIVA_SHIFT);
++		DPRINTK_ISPCTRL("isp_set_xclk(): cam_xclka set to %d Hz\n",
++				currentxclk);
++		break;
++	case 1:
++		isp_reg_and_or(OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
++			       ~ISPTCTRL_CTRL_DIVB_MASK,
++			       divisor << ISPTCTRL_CTRL_DIVB_SHIFT);
++		DPRINTK_ISPCTRL("isp_set_xclk(): cam_xclkb set to %d Hz\n",
++				currentxclk);
++		break;
++	default:
++		DPRINTK_ISPCTRL("ISP_ERR: isp_set_xclk(): Invalid requested "
++				"xclk. Must be 0 (A) or 1 (B)."
++				"\n");
++		return -EINVAL;
++	}
++
++	return currentxclk;
++}
++EXPORT_SYMBOL(isp_set_xclk);
++
++/**
++ * isp_power_settings - Sysconfig settings, for Power Management.
++ * @isp_sysconfig: Structure containing the power settings for ISP to configure
++ *
++ * Sets the power settings for the ISP, and SBL bus.
++ **/
++static void isp_power_settings(int idle)
++{
++	if (idle) {
++		isp_reg_writel(ISP_SYSCONFIG_AUTOIDLE |
++			       (ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY <<
++				ISP_SYSCONFIG_MIDLEMODE_SHIFT),
++			       OMAP3_ISP_IOMEM_MAIN,
++			       ISP_SYSCONFIG);
++		if (omap_rev() == OMAP3430_REV_ES1_0) {
++			isp_reg_writel(ISPCSI1_AUTOIDLE |
++				       (ISPCSI1_MIDLEMODE_SMARTSTANDBY <<
++					ISPCSI1_MIDLEMODE_SHIFT),
++				       OMAP3_ISP_IOMEM_CSI2A,
++				       ISP_CSIA_SYSCONFIG);
++			isp_reg_writel(ISPCSI1_AUTOIDLE |
++				       (ISPCSI1_MIDLEMODE_SMARTSTANDBY <<
++					ISPCSI1_MIDLEMODE_SHIFT),
++				       OMAP3_ISP_IOMEM_CCP2,
++				       ISP_CSIB_SYSCONFIG);
++		}
++		isp_reg_writel(ISPCTRL_SBL_AUTOIDLE, OMAP3_ISP_IOMEM_MAIN,
++			       ISP_CTRL);
++
++	} else {
++		isp_reg_writel(ISP_SYSCONFIG_AUTOIDLE |
++			       (ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY <<
++				ISP_SYSCONFIG_MIDLEMODE_SHIFT),
++			       OMAP3_ISP_IOMEM_MAIN,
++			       ISP_SYSCONFIG);
++		if (omap_rev() == OMAP3430_REV_ES1_0) {
++			isp_reg_writel(ISPCSI1_AUTOIDLE |
++				       (ISPCSI1_MIDLEMODE_FORCESTANDBY <<
++					ISPCSI1_MIDLEMODE_SHIFT),
++				       OMAP3_ISP_IOMEM_CSI2A,
++				       ISP_CSIA_SYSCONFIG);
++
++			isp_reg_writel(ISPCSI1_AUTOIDLE |
++				       (ISPCSI1_MIDLEMODE_FORCESTANDBY <<
++					ISPCSI1_MIDLEMODE_SHIFT),
++				       OMAP3_ISP_IOMEM_CCP2,
++				       ISP_CSIB_SYSCONFIG);
++		}
++
++		isp_reg_writel(ISPCTRL_SBL_AUTOIDLE, OMAP3_ISP_IOMEM_MAIN,
++			       ISP_CTRL);
++	}
++}
++
++#define BIT_SET(var, shift, mask, val)		\
++	do {					\
++		var = (var & ~(mask << shift))	\
++			| (val << shift);	\
++	} while (0)
++
++static int isp_init_csi(struct isp_interface_config *config)
++{
++	u32 i = 0, val, reg;
++	int format;
++
++	switch (config->u.csi.format) {
++	case V4L2_PIX_FMT_SGRBG10:
++		format = 0x16;		/* RAW10+VP */
++		break;
++	case V4L2_PIX_FMT_SGRBG10DPCM8:
++		format = 0x12;		/* RAW8+DPCM10+VP */
++		break;
++	default:
++		printk(KERN_ERR "isp_init_csi: bad csi format\n");
++		return -EINVAL;
++	}
++
++	/* Reset the CSI and wait for reset to complete */
++	isp_reg_writel(isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_SYSCONFIG) |
++		       BIT(1),
++		       OMAP3_ISP_IOMEM_CCP2,
++		       ISPCSI1_SYSCONFIG);
++	while (!(isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_SYSSTATUS) &
++		 BIT(0))) {
++		udelay(10);
++		if (i++ > 10)
++			break;
++	}
++	if (!(isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_SYSSTATUS) &
++	      BIT(0))) {
++		printk(KERN_WARNING
++		       "omap3_isp: timeout waiting for csi reset\n");
++	}
++
++	/* ISPCSI1_CTRL */
++	val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL);
++	val &= ~BIT(11);	/* Enable VP only off ->
++				   extract embedded data to interconnect */
++	BIT_SET(val, 8, 0x3, config->u.csi.vpclk);	/* Video port clock */
++/*	val |= BIT(3);	*/	/* Wait for FEC before disabling interface */
++	val |= BIT(2);		/* I/O cell output is parallel
++				   (no effect, but errata says should be enabled
++				   for class 1/2) */
++	val |= BIT(12);		/* VP clock polarity to falling edge
++				   (needed or bad picture!) */
++
++	/* Data/strobe physical layer */
++	BIT_SET(val, 1, 1, config->u.csi.signalling);
++	BIT_SET(val, 10, 1, config->u.csi.strobe_clock_inv);
++	val |= BIT(4);		/* Magic bit to enable CSI1 and strobe mode */
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL);
++
++	/* ISPCSI1_LCx_CTRL logical channel #0 */
++	reg = ISPCSI1_LCx_CTRL(0);	/* reg = ISPCSI1_CTRL1; */
++	val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, reg);
++	/* Format = RAW10+VP or RAW8+DPCM10+VP*/
++	BIT_SET(val, 3, 0x1f, format);
++	/* Enable setting of frame regions of interest */
++	BIT_SET(val, 1, 1, 1);
++	BIT_SET(val, 2, 1, config->u.csi.crc);
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, reg);
++
++	/* ISPCSI1_DAT_START for logical channel #0 */
++	reg = ISPCSI1_LCx_DAT_START(0);		/* reg = ISPCSI1_DAT_START; */
++	val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, reg);
++	BIT_SET(val, 16, 0xfff, config->u.csi.data_start);
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, reg);
++
++	/* ISPCSI1_DAT_SIZE for logical channel #0 */
++	reg = ISPCSI1_LCx_DAT_SIZE(0);		/* reg = ISPCSI1_DAT_SIZE; */
++	val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, reg);
++	BIT_SET(val, 16, 0xfff, config->u.csi.data_size);
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, reg);
++
++	/* Clear status bits for logical channel #0 */
++	isp_reg_writel(0xFFF & ~BIT(6), OMAP3_ISP_IOMEM_CCP2,
++		       ISPCSI1_LC01_IRQSTATUS);
++
++	/* Enable CSI1 */
++	val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL);
++	val |=  BIT(0) | BIT(4);
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL);
++
++	if (!(isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL) & BIT(4))) {
++		printk(KERN_WARNING "OMAP3 CSI1 bus not available\n");
++		if (config->u.csi.signalling)	/* Strobe mode requires CSI1 */
++			return -EIO;
++	}
++
++	return 0;
++}
++
++/**
++ * isp_configure_interface - Configures ISP Control I/F related parameters.
++ * @config: Pointer to structure containing the desired configuration for the
++ * 	ISP.
++ *
++ * Configures ISP control register (ISP_CTRL) with the values specified inside
++ * the config structure. Controls:
++ * - Selection of parallel or serial input to the preview hardware.
++ * - Data lane shifter.
++ * - Pixel clock polarity.
++ * - 8 to 16-bit bridge at the input of CCDC module.
++ * - HS or VS synchronization signal detection
++ **/
++int isp_configure_interface(struct isp_interface_config *config)
++{
++	u32 ispctrl_val = isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
++	int r;
++
++	isp_obj.config = config;
++
++	ispctrl_val &= ISPCTRL_SHIFT_MASK;
++	ispctrl_val |= config->dataline_shift << ISPCTRL_SHIFT_SHIFT;
++	ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
++
++	ispctrl_val &= ISPCTRL_PAR_SER_CLK_SEL_MASK;
++
++	isp_buf_init();
++
++	switch (config->ccdc_par_ser) {
++	case ISP_PARLL:
++		ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
++		ispctrl_val |= config->u.par.par_clk_pol
++			<< ISPCTRL_PAR_CLK_POL_SHIFT;
++		ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_BENDIAN;
++		ispctrl_val |= config->u.par.par_bridge
++			<< ISPCTRL_PAR_BRIDGE_SHIFT;
++		break;
++	case ISP_CSIA:
++		ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
++		ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_BENDIAN;
++
++		isp_csi2_ctx_config_format(0, config->u.csi.format);
++		isp_csi2_ctx_update(0, false);
++
++		if (config->u.csi.crc)
++			isp_csi2_ctrl_config_ecc_enable(true);
++
++		isp_csi2_ctrl_config_vp_out_ctrl(config->u.csi.vpclk);
++		isp_csi2_ctrl_config_vp_only_enable(true);
++		isp_csi2_ctrl_config_vp_clk_enable(true);
++		isp_csi2_ctrl_update(false);
++
++		isp_csi2_irq_complexio1_set(1);
++		isp_csi2_irq_status_set(1);
++		isp_csi2_irq_set(1);
++
++		isp_csi2_enable(1);
++		mdelay(3);
++		break;
++	case ISP_CSIB:
++		ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
++		r = isp_init_csi(config);
++		if (r)
++			return r;
++		break;
++	case ISP_NONE:
++		return 0;
++	default:
++		return -EINVAL;
++	}
++
++	ispctrl_val &= ~ISPCTRL_SYNC_DETECT_VSRISE;
++	ispctrl_val |= config->hsvs_syncdetect;
++
++	isp_reg_writel(ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
++
++	/* Set sensor specific fields in CCDC and Previewer module.*/
++	isppreview_set_skip(config->prev_sph, config->prev_slv);
++	ispccdc_set_wenlog(config->wenlog);
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_configure_interface);
++
++static int isp_buf_process(struct isp_bufs *bufs);
++
++/**
++ * omap34xx_isp_isr - Interrupt Service Routine for Camera ISP module.
++ * @irq: Not used currently.
++ * @ispirq_disp: Pointer to the object that is passed while request_irq is
++ *               called. This is the isp_obj.irq object containing info on the
++ *               callback.
++ *
++ * Handles the corresponding callback if plugged in.
++ *
++ * Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the
++ * IRQ wasn't handled.
++ **/
++static irqreturn_t omap34xx_isp_isr(int irq, void *_isp)
++{
++	struct isp *isp = _isp;
++	struct isp_irq *irqdis = &isp->irq;
++	struct isp_bufs *bufs = &isp->bufs;
++	unsigned long flags;
++	u32 irqstatus = 0;
++	unsigned long irqflags = 0;
++	int wait_hs_vs = 0;
++
++	irqstatus = isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
++	isp_reg_writel(irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
++
++	spin_lock_irqsave(&bufs->lock, flags);
++	wait_hs_vs = bufs->wait_hs_vs;
++	if (irqstatus & HS_VS && bufs->wait_hs_vs)
++		bufs->wait_hs_vs--;
++	spin_unlock_irqrestore(&bufs->lock, flags);
++
++	spin_lock_irqsave(&isp_obj.lock, irqflags);
++	/*
++	 * We need to wait for the first HS_VS interrupt from CCDC.
++	 * Otherwise our frame (and everything else) might be bad.
++	 */
++	if (wait_hs_vs)
++		goto out_ignore_buff;
++
++	if (irqstatus & CCDC_VD0) {
++		if (RAW_CAPTURE(&isp_obj))
++			isp_buf_process(bufs);
++		if (!ispccdc_busy())
++			ispccdc_config_shadow_registers();
++	}
++
++	if (irqstatus & PREV_DONE) {
++		if (irqdis->isp_callbk[CBK_PREV_DONE])
++			irqdis->isp_callbk[CBK_PREV_DONE](
++				PREV_DONE,
++				irqdis->isp_callbk_arg1[CBK_PREV_DONE],
++				irqdis->isp_callbk_arg2[CBK_PREV_DONE]);
++		else if (!RAW_CAPTURE(&isp_obj) && !ispresizer_busy()) {
++			if (isp_obj.module.applyCrop) {
++				ispresizer_applycrop();
++				if (!ispresizer_busy())
++					isp_obj.module.applyCrop = 0;
++			}
++			if (!isppreview_busy()) {
++				ispresizer_enable(1);
++				if (isppreview_busy()) {
++					/* FIXME: locking! */
++					ISP_BUF_DONE(bufs)->vb_state =
++						VIDEOBUF_ERROR;
++					printk(KERN_ERR "%s: can't stop"
++					       " preview\n", __func__);
++				}
++			}
++			if (!isppreview_busy())
++				isppreview_config_shadow_registers();
++			if (!isppreview_busy())
++				isph3a_update_wb();
++		}
++	}
++
++	if (irqstatus & RESZ_DONE) {
++		if (!RAW_CAPTURE(&isp_obj)) {
++			if (!ispresizer_busy())
++				ispresizer_config_shadow_registers();
++			isp_buf_process(bufs);
++		}
++	}
++
++	if (irqstatus & H3A_AWB_DONE) {
++		if (irqdis->isp_callbk[CBK_H3A_AWB_DONE])
++			irqdis->isp_callbk[CBK_H3A_AWB_DONE](
++				H3A_AWB_DONE,
++				irqdis->isp_callbk_arg1[CBK_H3A_AWB_DONE],
++				irqdis->isp_callbk_arg2[CBK_H3A_AWB_DONE]);
++	}
++
++	if (irqstatus & HIST_DONE) {
++		if (irqdis->isp_callbk[CBK_HIST_DONE])
++			irqdis->isp_callbk[CBK_HIST_DONE](
++				HIST_DONE,
++				irqdis->isp_callbk_arg1[CBK_HIST_DONE],
++				irqdis->isp_callbk_arg2[CBK_HIST_DONE]);
++	}
++
++	if (irqstatus & H3A_AF_DONE) {
++		if (irqdis->isp_callbk[CBK_H3A_AF_DONE])
++			irqdis->isp_callbk[CBK_H3A_AF_DONE](
++				H3A_AF_DONE,
++				irqdis->isp_callbk_arg1[CBK_H3A_AF_DONE],
++				irqdis->isp_callbk_arg2[CBK_H3A_AF_DONE]);
++	}
++
++
++out_ignore_buff:
++	if (irqstatus & LSC_PRE_ERR) {
++		struct isp_buf *buf = ISP_BUF_DONE(bufs);
++		/* Mark buffer faulty. */
++		buf->vb_state = VIDEOBUF_ERROR;
++		ispccdc_lsc_error_handler();
++		printk(KERN_ERR "%s: lsc prefetch error\n", __func__);
++	}
++
++	if (irqstatus & CSIA) {
++		struct isp_buf *buf = ISP_BUF_DONE(bufs);
++		isp_csi2_isr();
++		buf->vb_state = VIDEOBUF_ERROR;
++	}
++
++	if (irqstatus & IRQ0STATUS_CSIB_IRQ) {
++		u32 ispcsi1_irqstatus;
++
++		ispcsi1_irqstatus = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2,
++						  ISPCSI1_LC01_IRQSTATUS);
++		DPRINTK_ISPCTRL("%x\n", ispcsi1_irqstatus);
++	}
++
++	if (irqdis->isp_callbk[CBK_CATCHALL]) {
++		irqdis->isp_callbk[CBK_CATCHALL](
++			irqstatus,
++			irqdis->isp_callbk_arg1[CBK_CATCHALL],
++			irqdis->isp_callbk_arg2[CBK_CATCHALL]);
++	}
++
++	spin_unlock_irqrestore(&isp_obj.lock, irqflags);
++
++#if 1
++	{
++		static const struct {
++			int num;
++			char *name;
++		} bits[] = {
++			{ 31, "HS_VS_IRQ" },
++			{ 30, "SEC_ERR_IRQ" },
++			{ 29, "OCP_ERR_IRQ" },
++			{ 28, "MMU_ERR_IRQ" },
++			{ 27, "res27" },
++			{ 26, "res26" },
++			{ 25, "OVF_IRQ" },
++			{ 24, "RSZ_DONE_IRQ" },
++			{ 23, "res23" },
++			{ 22, "res22" },
++			{ 21, "CBUFF_IRQ" },
++			{ 20, "PRV_DONE_IRQ" },
++			{ 19, "CCDC_LSC_PREFETCH_ERROR" },
++			{ 18, "CCDC_LSC_PREFETCH_COMPLETED" },
++			{ 17, "CCDC_LSC_DONE" },
++			{ 16, "HIST_DONE_IRQ" },
++			{ 15, "res15" },
++			{ 14, "res14" },
++			{ 13, "H3A_AWB_DONE_IRQ" },
++			{ 12, "H3A_AF_DONE_IRQ" },
++			{ 11, "CCDC_ERR_IRQ" },
++			{ 10, "CCDC_VD2_IRQ" },
++			{  9, "CCDC_VD1_IRQ" },
++			{  8, "CCDC_VD0_IRQ" },
++			{  7, "res7" },
++			{  6, "res6" },
++			{  5, "res5" },
++			{  4, "CSIB_IRQ" },
++			{  3, "CSIB_LCM_IRQ" },
++			{  2, "res2" },
++			{  1, "res1" },
++			{  0, "CSIA_IRQ" },
++		};
++		int i;
++		for (i = 0; i < ARRAY_SIZE(bits); i++) {
++			if ((1 << bits[i].num) & irqstatus)
++				DPRINTK_ISPCTRL("%s ", bits[i].name);
++		}
++		DPRINTK_ISPCTRL("\n");
++	}
++#endif
++
++	return IRQ_HANDLED;
++}
++
++/* Device name, needed for resource tracking layer */
++struct device_driver camera_drv = {
++	.name = "camera"
++};
++
++struct device camera_dev = {
++	.driver = &camera_drv,
++};
++
++/**
++ *  isp_tmp_buf_free - To free allocated 10MB memory
++ *
++ **/
++static void isp_tmp_buf_free(void)
++{
++	if (isp_obj.tmp_buf) {
++		ispmmu_vfree(isp_obj.tmp_buf);
++		isp_obj.tmp_buf = 0;
++		isp_obj.tmp_buf_size = 0;
++	}
++}
++
++/**
++ *  isp_tmp_buf_alloc - To allocate a 10MB memory
++ *
++ **/
++static u32 isp_tmp_buf_alloc(size_t size)
++{
++	isp_tmp_buf_free();
++
++	printk(KERN_INFO "%s: allocating %d bytes\n", __func__, size);
++
++	isp_obj.tmp_buf = ispmmu_vmalloc(size);
++	if (IS_ERR((void *)isp_obj.tmp_buf)) {
++		printk(KERN_ERR "ispmmu_vmap mapping failed ");
++		return -ENOMEM;
++	}
++	isp_obj.tmp_buf_size = size;
++
++	isppreview_set_outaddr(isp_obj.tmp_buf);
++	ispresizer_set_inaddr(isp_obj.tmp_buf);
++
++	return 0;
++}
++
++/**
++ * isp_start - Starts ISP submodule
++ *
++ * Start the needed isp components assuming these components
++ * are configured correctly.
++ **/
++void isp_start(void)
++{
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW
++	    && is_isppreview_enabled())
++		isppreview_enable(1);
++
++	return;
++}
++EXPORT_SYMBOL(isp_start);
++
++#define ISP_STATISTICS_BUSY			\
++	()
++#define ISP_STOP_TIMEOUT	msecs_to_jiffies(1000)
++static int __isp_disable_modules(int suspend)
++{
++	unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
++	int reset = 0;
++
++	/*
++	 * We need to stop all the modules after CCDC first or they'll
++	 * never stop since they may not get a full frame from CCDC.
++	 */
++	if (suspend) {
++		isp_af_suspend();
++		isph3a_aewb_suspend();
++		isp_hist_suspend();
++		isppreview_suspend();
++		ispresizer_suspend();
++	} else {
++		isp_af_enable(0);
++		isph3a_aewb_enable(0);
++		isp_hist_enable(0);
++		isppreview_enable(0);
++		ispresizer_enable(0);
++	}
++
++	timeout = jiffies + ISP_STOP_TIMEOUT;
++	while (isp_af_busy()
++	       || isph3a_aewb_busy()
++	       || isp_hist_busy()
++	       || isppreview_busy()
++	       || ispresizer_busy()) {
++		if (time_after(jiffies, timeout)) {
++			printk(KERN_ERR "%s: can't stop non-ccdc modules\n",
++			       __func__);
++			reset = 1;
++			break;
++		}
++		msleep(1);
++	}
++
++	/* Let's stop CCDC now. */
++	if (suspend)
++		/* This function supends lsc too */
++		ispccdc_suspend();
++	else {
++		ispccdc_enable_lsc(0);
++		ispccdc_enable(0);
++	}
++
++	timeout = jiffies + ISP_STOP_TIMEOUT;
++	while (ispccdc_busy()) {
++		if (time_after(jiffies, timeout)) {
++			printk(KERN_ERR "%s: can't stop ccdc\n", __func__);
++			reset = 1;
++			break;
++		}
++		msleep(1);
++	}
++
++	return reset;
++}
++
++static int isp_stop_modules(void)
++{
++	return __isp_disable_modules(0);
++}
++
++static int isp_suspend_modules(void)
++{
++	return __isp_disable_modules(1);
++}
++
++static void isp_resume_modules(void)
++{
++	ispresizer_resume();
++	isppreview_resume();
++	isp_hist_resume();
++	isph3a_aewb_resume();
++	isp_af_resume();
++	ispccdc_resume();
++}
++
++static void isp_reset(void)
++{
++	unsigned long timeout = 0;
++
++	isp_reg_writel(isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
++		       | ISP_SYSCONFIG_SOFTRESET,
++		       OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
++	while (!(isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_SYSSTATUS) & 0x1)) {
++		if (timeout++ > 10000) {
++			printk(KERN_ALERT "%s: cannot reset ISP\n", __func__);
++			break;
++		}
++		udelay(1);
++	}
++}
++
++/**
++ * isp_stop - Stops isp submodules
++ **/
++void isp_stop()
++{
++	int reset;
++
++	isp_disable_interrupts();
++	reset = isp_stop_modules();
++	isp_buf_init();
++	if (!reset)
++		return;
++
++	isp_save_ctx();
++	isp_reset();
++	isp_restore_ctx();
++}
++EXPORT_SYMBOL(isp_stop);
++
++static void isp_set_buf(struct isp_buf *buf)
++{
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER
++	    && is_ispresizer_enabled())
++		ispresizer_set_outaddr(buf->isp_addr);
++	else if (isp_obj.module.isp_pipeline & OMAP_ISP_CCDC)
++		ispccdc_set_outaddr(buf->isp_addr);
++
++}
++
++/**
++ * isp_calc_pipeline - Sets pipeline depending of input and output pixel format
++ * @pix_input: Pointer to V4L2 pixel format structure for input image.
++ * @pix_output: Pointer to V4L2 pixel format structure for output image.
++ **/
++static u32 isp_calc_pipeline(struct v4l2_pix_format *pix_input,
++			     struct v4l2_pix_format *pix_output)
++{
++	isp_release_resources();
++	if ((pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10
++	     || pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10DPCM8)
++	    && pix_output->pixelformat != V4L2_PIX_FMT_SGRBG10) {
++		isp_obj.module.isp_pipeline =
++			OMAP_ISP_CCDC | OMAP_ISP_PREVIEW | OMAP_ISP_RESIZER;
++		ispccdc_request();
++		isppreview_request();
++		ispresizer_request();
++		ispccdc_config_datapath(CCDC_RAW, CCDC_OTHERS_VP);
++		isppreview_config_datapath(PRV_RAW_CCDC, PREVIEW_MEM);
++		ispresizer_config_datapath(RSZ_MEM_YUV);
++	} else {
++		isp_obj.module.isp_pipeline = OMAP_ISP_CCDC;
++		ispccdc_request();
++		if (pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10
++		    || pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10DPCM8)
++			ispccdc_config_datapath(CCDC_RAW, CCDC_OTHERS_VP_MEM);
++		else
++			ispccdc_config_datapath(CCDC_YUV_SYNC,
++						CCDC_OTHERS_MEM);
++	}
++	return 0;
++}
++
++/**
++ * isp_config_pipeline - Configures the image size and ycpos for ISP submodules
++ * @pix_input: Pointer to V4L2 pixel format structure for input image.
++ * @pix_output: Pointer to V4L2 pixel format structure for output image.
++ *
++ * The configuration of ycpos depends on the output pixel format for both the
++ * Preview and Resizer submodules.
++ **/
++static void isp_config_pipeline(struct v4l2_pix_format *pix_input,
++				struct v4l2_pix_format *pix_output)
++{
++	ispccdc_config_size(isp_obj.module.ccdc_input_width,
++			    isp_obj.module.ccdc_input_height,
++			    isp_obj.module.ccdc_output_width,
++			    isp_obj.module.ccdc_output_height);
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW) {
++		isppreview_config_size(isp_obj.module.preview_input_width,
++				       isp_obj.module.preview_input_height,
++				       isp_obj.module.preview_output_width,
++				       isp_obj.module.preview_output_height);
++	}
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER) {
++		ispresizer_config_size(isp_obj.module.resizer_input_width,
++				       isp_obj.module.resizer_input_height,
++				       isp_obj.module.resizer_output_width,
++				       isp_obj.module.resizer_output_height);
++	}
++
++	if (pix_output->pixelformat == V4L2_PIX_FMT_UYVY) {
++		isppreview_config_ycpos(YCPOS_YCrYCb);
++		if (is_ispresizer_enabled())
++			ispresizer_config_ycpos(0);
++	} else {
++		isppreview_config_ycpos(YCPOS_CrYCbY);
++		if (is_ispresizer_enabled())
++			ispresizer_config_ycpos(1);
++	}
++
++	return;
++}
++
++static void isp_buf_init(void)
++{
++	struct isp_bufs *bufs = &isp_obj.bufs;
++	int sg;
++
++	bufs->queue = 0;
++	bufs->done = 0;
++	bufs->wait_hs_vs = isp_obj.config->wait_hs_vs;
++	for (sg = 0; sg < NUM_BUFS; sg++) {
++		bufs->buf[sg].complete = NULL;
++		bufs->buf[sg].vb = NULL;
++		bufs->buf[sg].priv = NULL;
++	}
++}
++
++/**
++ * isp_vbq_sync - Walks the pages table and flushes the cache for
++ *                each page.
++ **/
++static int isp_vbq_sync(struct videobuf_buffer *vb, int when)
++{
++	flush_cache_all();
++
++	return 0;
++}
++
++static int isp_buf_process(struct isp_bufs *bufs)
++{
++	struct isp_buf *buf = NULL;
++	unsigned long flags;
++	int last;
++
++	spin_lock_irqsave(&bufs->lock, flags);
++
++	if (ISP_BUFS_IS_EMPTY(bufs))
++		goto out;
++
++	if (RAW_CAPTURE(&isp_obj) && ispccdc_sbl_wait_idle(1000)) {
++		printk(KERN_ERR "ccdc %d won't become idle!\n",
++		       RAW_CAPTURE(&isp_obj));
++		goto out;
++	}
++
++	/* We had at least one buffer in queue. */
++	buf = ISP_BUF_DONE(bufs);
++	last = ISP_BUFS_IS_LAST(bufs);
++
++	if (!last) {
++		/* Set new buffer address. */
++		isp_set_buf(ISP_BUF_NEXT_DONE(bufs));
++	} else {
++		/* Tell ISP not to write any of our buffers. */
++		isp_disable_interrupts();
++		if (RAW_CAPTURE(&isp_obj))
++			ispccdc_enable(0);
++		else
++			ispresizer_enable(0);
++		/*
++		 * We must wait for the HS_VS since before that the
++		 * CCDC may trigger interrupts even if it's not
++		 * receiving a frame.
++		 */
++		bufs->wait_hs_vs = isp_obj.config->wait_hs_vs;
++	}
++	if ((RAW_CAPTURE(&isp_obj) && ispccdc_busy())
++	    || (!RAW_CAPTURE(&isp_obj) && ispresizer_busy())) {
++		/*
++		 * Next buffer available: for the transfer to succeed, the
++		 * CCDC (RAW capture) or resizer (YUV capture) must be idle
++		 * for the duration of transfer setup. Bad things happen
++		 * otherwise!
++		 *
++		 * Next buffer not available: if we fail to stop the
++		 * ISP the buffer is probably going to be bad.
++		 */
++		/* Mark this buffer faulty. */
++		buf->vb_state = VIDEOBUF_ERROR;
++		/* Mark next faulty, too, in case we have one. */
++		if (!last) {
++			ISP_BUF_NEXT_DONE(bufs)->vb_state =
++				VIDEOBUF_ERROR;
++			printk(KERN_ALERT "OUCH!!!\n");
++		} else {
++			printk(KERN_ALERT "Ouch!\n");
++		}
++	}
++
++	/* Mark the current buffer as done. */
++	ISP_BUF_MARK_DONE(bufs);
++
++	DPRINTK_ISPCTRL(KERN_ALERT "%s: finish %d mmu %p\n", __func__,
++			(bufs->done - 1 + NUM_BUFS) % NUM_BUFS,
++			(bufs->buf+((bufs->done - 1 + NUM_BUFS)
++				    % NUM_BUFS))->isp_addr);
++
++out:
++	spin_unlock_irqrestore(&bufs->lock, flags);
++
++	if (buf != NULL) {
++		/*
++		 * We want to dequeue a buffer from the video buffer
++		 * queue. Let's do it!
++		 */
++		isp_vbq_sync(buf->vb, DMA_FROM_DEVICE);
++		buf->vb->state = buf->vb_state;
++		buf->complete(buf->vb, buf->priv);
++	}
++
++	return 0;
++}
++
++int isp_buf_queue(struct videobuf_buffer *vb,
++		  void (*complete)(struct videobuf_buffer *vb, void *priv),
++		  void *priv)
++{
++	unsigned long flags;
++	struct isp_buf *buf;
++	struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
++	const struct scatterlist *sglist = dma->sglist;
++	struct isp_bufs *bufs = &isp_obj.bufs;
++	int sglen = dma->sglen;
++
++	BUG_ON(sglen < 0 || !sglist);
++
++	isp_vbq_sync(vb, DMA_TO_DEVICE);
++
++	spin_lock_irqsave(&bufs->lock, flags);
++
++	BUG_ON(ISP_BUFS_IS_FULL(bufs));
++
++	buf = ISP_BUF_QUEUE(bufs);
++
++	buf->isp_addr = bufs->isp_addr_capture[vb->i];
++	buf->complete = complete;
++	buf->vb = vb;
++	buf->priv = priv;
++	buf->vb_state = VIDEOBUF_DONE;
++
++	if (ISP_BUFS_IS_EMPTY(bufs)) {
++		isp_enable_interrupts(RAW_CAPTURE(&isp_obj));
++		isp_set_buf(buf);
++		ispccdc_enable(1);
++		isp_start();
++	}
++
++	ISP_BUF_MARK_QUEUED(bufs);
++
++	spin_unlock_irqrestore(&bufs->lock, flags);
++
++	DPRINTK_ISPCTRL(KERN_ALERT "%s: queue %d vb %d, mmu %p\n", __func__,
++			(bufs->queue - 1 + NUM_BUFS) % NUM_BUFS, vb->i,
++			buf->isp_addr);
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_buf_queue);
++
++int isp_vbq_setup(struct videobuf_queue *vbq, unsigned int *cnt,
++		  unsigned int *size)
++{
++	int rval = 0;
++	size_t tmp_size = PAGE_ALIGN(isp_obj.module.preview_output_width
++				     * isp_obj.module.preview_output_height
++				     * ISP_BYTES_PER_PIXEL);
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW
++	    && isp_obj.tmp_buf_size < tmp_size)
++		rval = isp_tmp_buf_alloc(tmp_size);
++
++	return rval;
++}
++EXPORT_SYMBOL(isp_vbq_setup);
++
++/**
++ * isp_vbq_prepare - Videobuffer queue prepare.
++ * @vbq: Pointer to videobuf_queue structure.
++ * @vb: Pointer to videobuf_buffer structure.
++ * @field: Requested Field order for the videobuffer.
++ *
++ * Returns 0 if successful, or -EIO if the ispmmu was unable to map a
++ * scatter-gather linked list data space.
++ **/
++int isp_vbq_prepare(struct videobuf_queue *vbq, struct videobuf_buffer *vb,
++		    enum v4l2_field field)
++{
++	unsigned int isp_addr;
++	struct videobuf_dmabuf *vdma;
++	struct isp_bufs *bufs = &isp_obj.bufs;
++
++	int err = 0;
++
++	vdma = videobuf_to_dma(vb);
++
++	isp_addr = ispmmu_vmap(vdma->sglist, vdma->sglen);
++
++	if (IS_ERR_VALUE(isp_addr))
++		err = -EIO;
++	else
++		bufs->isp_addr_capture[vb->i] = isp_addr;
++
++	return err;
++}
++EXPORT_SYMBOL(isp_vbq_prepare);
++
++/**
++ * isp_vbq_release - Videobuffer queue release.
++ * @vbq: Pointer to videobuf_queue structure.
++ * @vb: Pointer to videobuf_buffer structure.
++ **/
++void isp_vbq_release(struct videobuf_queue *vbq, struct videobuf_buffer *vb)
++{
++	struct isp_bufs *bufs = &isp_obj.bufs;
++
++	ispmmu_vunmap(bufs->isp_addr_capture[vb->i]);
++	bufs->isp_addr_capture[vb->i] = (dma_addr_t)NULL;
++	return;
++}
++EXPORT_SYMBOL(isp_vbq_release);
++
++/**
++ * isp_queryctrl - Query V4L2 control from existing controls in ISP.
++ * @a: Pointer to v4l2_queryctrl structure. It only needs the id field filled.
++ *
++ * Returns 0 if successful, or -EINVAL if not found in ISP.
++ **/
++int isp_queryctrl(struct v4l2_queryctrl *a)
++{
++	int i;
++
++	if (a->id & V4L2_CTRL_FLAG_NEXT_CTRL) {
++		a->id &= ~V4L2_CTRL_FLAG_NEXT_CTRL;
++		i = find_next_vctrl(a->id);
++	} else {
++		i = find_vctrl(a->id);
++	}
++
++	if (i < 0)
++		return -EINVAL;
++
++	*a = video_control[i].qc;
++	return 0;
++}
++EXPORT_SYMBOL(isp_queryctrl);
++
++/**
++ * isp_queryctrl - Query V4L2 control from existing controls in ISP.
++ * @a: Pointer to v4l2_queryctrl structure. It only needs the id field filled.
++ *
++ * Returns 0 if successful, or -EINVAL if not found in ISP.
++ **/
++int isp_querymenu(struct v4l2_querymenu *a)
++{
++	int i;
++
++	i = find_vmenu(a->id, a->index);
++
++	if (i < 0)
++		return -EINVAL;
++
++	*a = video_menu[i];
++	return 0;
++}
++EXPORT_SYMBOL(isp_querymenu);
++
++/**
++ * isp_g_ctrl - Gets value of the desired V4L2 control.
++ * @a: V4L2 control to read actual value from.
++ *
++ * Return 0 if successful, or -EINVAL if chosen control is not found.
++ **/
++int isp_g_ctrl(struct v4l2_control *a)
++{
++	u8 current_value;
++	int rval = 0;
++
++	if (!isp_obj.ref_count)
++		return -EINVAL;
++
++	switch (a->id) {
++	case V4L2_CID_BRIGHTNESS:
++		isppreview_query_brightness(&current_value);
++		a->value = current_value / ISPPRV_BRIGHT_UNITS;
++		break;
++	case V4L2_CID_CONTRAST:
++		isppreview_query_contrast(&current_value);
++		a->value = current_value / ISPPRV_CONTRAST_UNITS;
++		break;
++	case V4L2_CID_COLORFX:
++		isppreview_get_color(&current_value);
++		a->value = current_value;
++		break;
++	default:
++		rval = -EINVAL;
++		break;
++	}
++
++	return rval;
++}
++EXPORT_SYMBOL(isp_g_ctrl);
++
++/**
++ * isp_s_ctrl - Sets value of the desired V4L2 control.
++ * @a: V4L2 control to read actual value from.
++ *
++ * Return 0 if successful, -EINVAL if chosen control is not found or value
++ * is out of bounds, -EFAULT if copy_from_user or copy_to_user operation fails
++ * from camera abstraction layer related controls or the transfered user space
++ * pointer via the value field is not set properly.
++ **/
++int isp_s_ctrl(struct v4l2_control *a)
++{
++	int rval = 0;
++	u8 new_value = a->value;
++
++	if (!isp_obj.ref_count)
++		return -EINVAL;
++
++	switch (a->id) {
++	case V4L2_CID_BRIGHTNESS:
++		if (new_value > ISPPRV_BRIGHT_HIGH)
++			rval = -EINVAL;
++		else
++			isppreview_update_brightness(&new_value);
++		break;
++	case V4L2_CID_CONTRAST:
++		if (new_value > ISPPRV_CONTRAST_HIGH)
++			rval = -EINVAL;
++		else
++			isppreview_update_contrast(&new_value);
++		break;
++	case V4L2_CID_COLORFX:
++		if (new_value > V4L2_COLORFX_SEPIA)
++			rval = -EINVAL;
++		else
++			isppreview_set_color(&new_value);
++		break;
++	default:
++		rval = -EINVAL;
++		break;
++	}
++
++	return rval;
++}
++EXPORT_SYMBOL(isp_s_ctrl);
++
++/**
++ * isp_handle_private - Handle all private ioctls for isp module.
++ * @cmd: ioctl cmd value
++ * @arg: ioctl arg value
++ *
++ * Return 0 if successful, -EINVAL if chosen cmd value is not handled or value
++ * is out of bounds, -EFAULT if ioctl arg value is not valid.
++ * Function simply routes the input ioctl cmd id to the appropriate handler in
++ * the isp module.
++ **/
++int isp_handle_private(int cmd, void *arg)
++{
++	int rval = 0;
++
++	if (!isp_obj.ref_count)
++		return -EINVAL;
++
++	switch (cmd) {
++	case VIDIOC_PRIVATE_ISP_CCDC_CFG:
++		rval = omap34xx_isp_ccdc_config(arg);
++		break;
++	case VIDIOC_PRIVATE_ISP_PRV_CFG:
++		rval = omap34xx_isp_preview_config(arg);
++		break;
++	case VIDIOC_PRIVATE_ISP_AEWB_CFG: {
++		struct isph3a_aewb_config *params;
++		params = (struct isph3a_aewb_config *)arg;
++		rval = isph3a_aewb_configure(params);
++	}
++		break;
++	case VIDIOC_PRIVATE_ISP_AEWB_REQ: {
++		struct isph3a_aewb_data *data;
++		data = (struct isph3a_aewb_data *)arg;
++		rval = isph3a_aewb_request_statistics(data);
++	}
++		break;
++	case VIDIOC_PRIVATE_ISP_HIST_CFG: {
++		struct isp_hist_config *params;
++		params = (struct isp_hist_config *)arg;
++		rval = isp_hist_configure(params);
++	}
++		break;
++	case VIDIOC_PRIVATE_ISP_HIST_REQ: {
++		struct isp_hist_data *data;
++		data = (struct isp_hist_data *)arg;
++		rval = isp_hist_request_statistics(data);
++	}
++		break;
++	case VIDIOC_PRIVATE_ISP_AF_CFG: {
++		struct af_configuration *params;
++		params = (struct af_configuration *)arg;
++		rval = isp_af_configure(params);
++	}
++		break;
++	case VIDIOC_PRIVATE_ISP_AF_REQ: {
++		struct isp_af_data *data;
++		data = (struct isp_af_data *)arg;
++		rval = isp_af_request_statistics(data);
++	}
++		break;
++	default:
++		rval = -EINVAL;
++		break;
++	}
++	return rval;
++}
++EXPORT_SYMBOL(isp_handle_private);
++
++/**
++ * isp_enum_fmt_cap - Gets more information of chosen format index and type
++ * @f: Pointer to structure containing index and type of format to read from.
++ *
++ * Returns 0 if successful, or -EINVAL if format index or format type is
++ * invalid.
++ **/
++int isp_enum_fmt_cap(struct v4l2_fmtdesc *f)
++{
++	int index = f->index;
++	enum v4l2_buf_type type = f->type;
++	int rval = -EINVAL;
++
++	if (index >= NUM_ISP_CAPTURE_FORMATS)
++		goto err;
++
++	memset(f, 0, sizeof(*f));
++	f->index = index;
++	f->type = type;
++
++	switch (f->type) {
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++		rval = 0;
++		break;
++	default:
++		goto err;
++	}
++
++	f->flags = isp_formats[index].flags;
++	strncpy(f->description, isp_formats[index].description,
++		sizeof(f->description));
++	f->pixelformat = isp_formats[index].pixelformat;
++err:
++	return rval;
++}
++EXPORT_SYMBOL(isp_enum_fmt_cap);
++
++/**
++ * isp_g_fmt_cap - Gets current output image format.
++ * @f: Pointer to V4L2 format structure to be filled with current output format
++ **/
++void isp_g_fmt_cap(struct v4l2_pix_format *pix)
++{
++	*pix = isp_obj.module.pix;
++	return;
++}
++EXPORT_SYMBOL(isp_g_fmt_cap);
++
++/**
++ * isp_s_fmt_cap - Sets I/O formats and crop and configures pipeline in ISP
++ * @f: Pointer to V4L2 format structure to be filled with current output format
++ *
++ * Returns 0 if successful, or return value of either isp_try_size or
++ * isp_try_fmt if there is an error.
++ **/
++int isp_s_fmt_cap(struct v4l2_pix_format *pix_input,
++		  struct v4l2_pix_format *pix_output)
++{
++	int crop_scaling_w = 0, crop_scaling_h = 0;
++	int rval = 0;
++
++	if (!isp_obj.ref_count)
++		return -EINVAL;
++
++	rval = isp_calc_pipeline(pix_input, pix_output);
++	if (rval)
++		goto out;
++
++	rval = isp_try_size(pix_input, pix_output);
++	if (rval)
++		goto out;
++
++	rval = isp_try_fmt(pix_input, pix_output);
++	if (rval)
++		goto out;
++
++	if (ispcroprect.width != pix_output->width) {
++		crop_scaling_w = 1;
++		ispcroprect.left = 0;
++		ispcroprect.width = pix_output->width;
++	}
++
++	if (ispcroprect.height != pix_output->height) {
++		crop_scaling_h = 1;
++		ispcroprect.top = 0;
++		ispcroprect.height = pix_output->height;
++	}
++
++	isp_config_pipeline(pix_input, pix_output);
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER
++	    && (crop_scaling_h || crop_scaling_w))
++		isp_config_crop(pix_output);
++
++out:
++	return rval;
++}
++EXPORT_SYMBOL(isp_s_fmt_cap);
++
++/**
++ * isp_config_crop - Configures crop parameters in isp resizer.
++ * @croppix: Pointer to V4L2 pixel format structure containing crop parameters
++ **/
++void isp_config_crop(struct v4l2_pix_format *croppix)
++{
++	u8 crop_scaling_w;
++	u8 crop_scaling_h;
++	unsigned long org_left, num_pix, new_top;
++
++	struct v4l2_pix_format *pix = croppix;
++
++	crop_scaling_w = (isp_obj.module.preview_output_width * 10) /
++		pix->width;
++	crop_scaling_h = (isp_obj.module.preview_output_height * 10) /
++		pix->height;
++
++	cur_rect.left = (ispcroprect.left * crop_scaling_w) / 10;
++	cur_rect.top = (ispcroprect.top * crop_scaling_h) / 10;
++	cur_rect.width = (ispcroprect.width * crop_scaling_w) / 10;
++	cur_rect.height = (ispcroprect.height * crop_scaling_h) / 10;
++
++	org_left = cur_rect.left;
++	while (((int)cur_rect.left & 0xFFFFFFF0) != (int)cur_rect.left)
++		(int)cur_rect.left--;
++
++	num_pix = org_left - cur_rect.left;
++	new_top = (int)(num_pix * 3) / 4;
++	cur_rect.top = cur_rect.top - new_top;
++	cur_rect.height = (2 * new_top) + cur_rect.height;
++
++	cur_rect.width = cur_rect.width + (2 * num_pix);
++	while (((int)cur_rect.width & 0xFFFFFFF0) != (int)cur_rect.width)
++		(int)cur_rect.width--;
++
++	isp_obj.tmp_buf_offset =
++		cur_rect.left * 2 +
++		isp_obj.module.preview_output_width * 2 * cur_rect.top;
++
++	ispresizer_trycrop(cur_rect.left, cur_rect.top, cur_rect.width,
++			   cur_rect.height,
++			   isp_obj.module.resizer_output_width,
++			   isp_obj.module.resizer_output_height);
++
++	return;
++}
++EXPORT_SYMBOL(isp_config_crop);
++
++/**
++ * isp_g_crop - Gets crop rectangle size and position.
++ * @a: Pointer to V4L2 crop structure to be filled.
++ *
++ * Always returns 0.
++ **/
++int isp_g_crop(struct v4l2_crop *a)
++{
++	struct v4l2_crop *crop = a;
++
++	crop->c = ispcroprect;
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_g_crop);
++
++/**
++ * isp_s_crop - Sets crop rectangle size and position and queues crop operation
++ * @a: Pointer to V4L2 crop structure with desired parameters.
++ * @pix: Pointer to V4L2 pixel format structure with desired parameters.
++ *
++ * Returns 0 if successful, or -EINVAL if crop parameters are out of bounds.
++ **/
++int isp_s_crop(struct v4l2_crop *a, struct v4l2_pix_format *pix)
++{
++	struct v4l2_crop *crop = a;
++	int rval = 0;
++
++	if (!isp_obj.ref_count)
++		return -EINVAL;
++
++	if (crop->c.left < 0)
++		crop->c.left = 0;
++	if (crop->c.width < 0)
++		crop->c.width = 0;
++	if (crop->c.top < 0)
++		crop->c.top = 0;
++	if (crop->c.height < 0)
++		crop->c.height = 0;
++
++	if (crop->c.left >= pix->width)
++		crop->c.left = pix->width - 1;
++	if (crop->c.top >= pix->height)
++		crop->c.top = pix->height - 1;
++
++	if (crop->c.left + crop->c.width > pix->width)
++		crop->c.width = pix->width - crop->c.left;
++	if (crop->c.top + crop->c.height > pix->height)
++		crop->c.height = pix->height - crop->c.top;
++
++	ispcroprect.left = crop->c.left;
++	ispcroprect.top = crop->c.top;
++	ispcroprect.width = crop->c.width;
++	ispcroprect.height = crop->c.height;
++
++	isp_config_crop(pix);
++
++	isp_obj.module.applyCrop = 1;
++
++	return rval;
++}
++EXPORT_SYMBOL(isp_s_crop);
++
++/**
++ * isp_try_fmt_cap - Tries desired input/output image formats
++ * @pix_input: Pointer to V4L2 pixel format structure for input image.
++ * @pix_output: Pointer to V4L2 pixel format structure for output image.
++ *
++ * Returns 0 if successful, or return value of either isp_try_size or
++ * isp_try_fmt if there is an error.
++ **/
++int isp_try_fmt_cap(struct v4l2_pix_format *pix_input,
++		    struct v4l2_pix_format *pix_output)
++{
++	int rval = 0;
++
++	rval = isp_calc_pipeline(pix_input, pix_output);
++	if (rval)
++		goto out;
++
++	rval = isp_try_size(pix_input, pix_output);
++	if (rval)
++		goto out;
++
++	rval = isp_try_fmt(pix_input, pix_output);
++	if (rval)
++		goto out;
++
++out:
++	return rval;
++}
++EXPORT_SYMBOL(isp_try_fmt_cap);
++
++/**
++ * isp_try_size - Tries size configuration for I/O images of each ISP submodule
++ * @pix_input: Pointer to V4L2 pixel format structure for input image.
++ * @pix_output: Pointer to V4L2 pixel format structure for output image.
++ *
++ * Returns 0 if successful, or return value of ispccdc_try_size,
++ * isppreview_try_size, or ispresizer_try_size (depending on the pipeline
++ * configuration) if there is an error.
++ **/
++static int isp_try_size(struct v4l2_pix_format *pix_input,
++			struct v4l2_pix_format *pix_output)
++{
++	int rval = 0;
++
++	if (pix_output->width <= ISPRSZ_MIN_OUTPUT
++	    || pix_output->height <= ISPRSZ_MIN_OUTPUT)
++		return -EINVAL;
++
++	if (pix_output->width >= ISPRSZ_MAX_OUTPUT
++	    || pix_output->height > ISPRSZ_MAX_OUTPUT)
++		return -EINVAL;
++
++	isp_obj.module.ccdc_input_width = pix_input->width;
++	isp_obj.module.ccdc_input_height = pix_input->height;
++	isp_obj.module.resizer_output_width = pix_output->width;
++	isp_obj.module.resizer_output_height = pix_output->height;
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_CCDC) {
++		rval = ispccdc_try_size(isp_obj.module.ccdc_input_width,
++					isp_obj.module.ccdc_input_height,
++					&isp_obj.module.ccdc_output_width,
++					&isp_obj.module.ccdc_output_height);
++		if (rval) {
++			printk(KERN_ERR "ISP_ERR: The dimensions %dx%d are not"
++			       " supported\n", pix_input->width,
++			       pix_input->height);
++			return rval;
++		}
++		pix_output->width = isp_obj.module.ccdc_output_width;
++		pix_output->height = isp_obj.module.ccdc_output_height;
++	}
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW) {
++		isp_obj.module.preview_input_width =
++			isp_obj.module.ccdc_output_width;
++		isp_obj.module.preview_input_height =
++			isp_obj.module.ccdc_output_height;
++		rval = isppreview_try_size(
++			isp_obj.module.preview_input_width,
++			isp_obj.module.preview_input_height,
++			&isp_obj.module.preview_output_width,
++			&isp_obj.module.preview_output_height);
++		if (rval) {
++			printk(KERN_ERR "ISP_ERR: The dimensions %dx%d are not"
++			       " supported\n", pix_input->width,
++			       pix_input->height);
++			return rval;
++		}
++		pix_output->width = isp_obj.module.preview_output_width;
++		pix_output->height = isp_obj.module.preview_output_height;
++	}
++
++	if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER) {
++		isp_obj.module.resizer_input_width =
++			isp_obj.module.preview_output_width;
++		isp_obj.module.resizer_input_height =
++			isp_obj.module.preview_output_height;
++		rval = ispresizer_try_size(
++			&isp_obj.module.resizer_input_width,
++			&isp_obj.module.resizer_input_height,
++			&isp_obj.module.resizer_output_width,
++			&isp_obj.module.resizer_output_height);
++		if (rval) {
++			printk(KERN_ERR "ISP_ERR: The dimensions %dx%d are not"
++			       " supported\n", pix_input->width,
++			       pix_input->height);
++			return rval;
++		}
++		pix_output->width = isp_obj.module.resizer_output_width;
++		pix_output->height = isp_obj.module.resizer_output_height;
++	}
++
++	return rval;
++}
++
++/**
++ * isp_try_fmt - Validates input/output format parameters.
++ * @pix_input: Pointer to V4L2 pixel format structure for input image.
++ * @pix_output: Pointer to V4L2 pixel format structure for output image.
++ *
++ * Always returns 0.
++ **/
++int isp_try_fmt(struct v4l2_pix_format *pix_input,
++		struct v4l2_pix_format *pix_output)
++{
++	int ifmt;
++
++	for (ifmt = 0; ifmt < NUM_ISP_CAPTURE_FORMATS; ifmt++) {
++		if (pix_output->pixelformat == isp_formats[ifmt].pixelformat)
++			break;
++	}
++	if (ifmt == NUM_ISP_CAPTURE_FORMATS)
++		ifmt = 1;
++	pix_output->pixelformat = isp_formats[ifmt].pixelformat;
++	pix_output->field = V4L2_FIELD_NONE;
++	pix_output->bytesperline = pix_output->width * ISP_BYTES_PER_PIXEL;
++	pix_output->sizeimage =
++		PAGE_ALIGN(pix_output->bytesperline * pix_output->height);
++	pix_output->priv = 0;
++	switch (pix_output->pixelformat) {
++	case V4L2_PIX_FMT_YUYV:
++	case V4L2_PIX_FMT_UYVY:
++		pix_output->colorspace = V4L2_COLORSPACE_JPEG;
++		break;
++	default:
++		pix_output->colorspace = V4L2_COLORSPACE_SRGB;
++	}
++
++	isp_obj.module.pix.pixelformat = pix_output->pixelformat;
++	isp_obj.module.pix.width = pix_output->width;
++	isp_obj.module.pix.height = pix_output->height;
++	isp_obj.module.pix.field = pix_output->field;
++	isp_obj.module.pix.bytesperline = pix_output->bytesperline;
++	isp_obj.module.pix.sizeimage = pix_output->sizeimage;
++	isp_obj.module.pix.priv = pix_output->priv;
++	isp_obj.module.pix.colorspace = pix_output->colorspace;
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_try_fmt);
++
++/**
++ * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
++ *
++ * Routine for saving the context of each module in the ISP.
++ * CCDC, HIST, H3A, PREV, RESZ and MMU.
++ **/
++static void isp_save_ctx(void)
++{
++	isp_save_context(isp_reg_list);
++	ispccdc_save_context();
++	ispmmu_save_context();
++	isphist_save_context();
++	isph3a_save_context();
++	isppreview_save_context();
++	ispresizer_save_context();
++}
++
++/**
++ * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
++ *
++ * Routine for restoring the context of each module in the ISP.
++ * CCDC, HIST, H3A, PREV, RESZ and MMU.
++ **/
++static void isp_restore_ctx(void)
++{
++	isp_restore_context(isp_reg_list);
++	ispccdc_restore_context();
++	ispmmu_restore_context();
++	isphist_restore_context();
++	isph3a_restore_context();
++	isppreview_restore_context();
++	ispresizer_restore_context();
++}
++
++static int isp_enable_clocks(void)
++{
++	int r;
++
++	r = clk_enable(isp_obj.cam_ick);
++	if (r) {
++		DPRINTK_ISPCTRL("ISP_ERR: clk_en for ick failed\n");
++		goto out_clk_enable_ick;
++	}
++	r = clk_enable(isp_obj.cam_mclk);
++	if (r) {
++		DPRINTK_ISPCTRL("ISP_ERR: clk_en for mclk failed\n");
++		goto out_clk_enable_mclk;
++	}
++	r = clk_enable(isp_obj.csi2_fck);
++	if (r) {
++		DPRINTK_ISPCTRL("ISP_ERR: clk_en for csi2_fclk"
++				" failed\n");
++		goto out_clk_enable_csi2_fclk;
++	}
++	return 0;
++
++out_clk_enable_csi2_fclk:
++	clk_disable(isp_obj.cam_mclk);
++out_clk_enable_mclk:
++	clk_disable(isp_obj.cam_ick);
++out_clk_enable_ick:
++	return r;
++}
++
++static void isp_disable_clocks(void)
++{
++	clk_disable(isp_obj.cam_ick);
++	clk_disable(isp_obj.cam_mclk);
++	clk_disable(isp_obj.csi2_fck);
++}
++
++/**
++ * isp_get - Adquires the ISP resource.
++ *
++ * Initializes the clocks for the first acquire.
++ **/
++int isp_get(void)
++{
++	static int has_context;
++	int ret_err = 0;
++
++	if (omap3isp == NULL)
++		return -EBUSY;
++
++	DPRINTK_ISPCTRL("isp_get: old %d\n", isp_obj.ref_count);
++	mutex_lock(&(isp_obj.isp_mutex));
++	if (isp_obj.ref_count == 0) {
++		ret_err = isp_enable_clocks();
++		if (ret_err)
++			goto out_err;
++		/* We don't want to restore context before saving it! */
++		if (has_context)
++			isp_restore_ctx();
++		else
++			has_context = 1;
++	} else {
++		mutex_unlock(&isp_obj.isp_mutex);
++		return -EBUSY;
++	}
++	isp_obj.ref_count++;
++	mutex_unlock(&(isp_obj.isp_mutex));
++
++	DPRINTK_ISPCTRL("isp_get: new %d\n", isp_obj.ref_count);
++	return isp_obj.ref_count;
++
++out_err:
++	mutex_unlock(&(isp_obj.isp_mutex));
++	return ret_err;
++}
++EXPORT_SYMBOL(isp_get);
++
++/**
++ * isp_put - Releases the ISP resource.
++ *
++ * Releases the clocks also for the last release.
++ **/
++int isp_put(void)
++{
++	if (omap3isp == NULL)
++		return -EBUSY;
++
++	DPRINTK_ISPCTRL("isp_put: old %d\n", isp_obj.ref_count);
++	mutex_lock(&(isp_obj.isp_mutex));
++	if (isp_obj.ref_count) {
++		if (--isp_obj.ref_count == 0) {
++			isp_save_ctx();
++			isp_tmp_buf_free();
++			isp_release_resources();
++			isp_obj.module.isp_pipeline = 0;
++			isp_disable_clocks();
++			memset(&ispcroprect, 0, sizeof(ispcroprect));
++			memset(&cur_rect, 0, sizeof(cur_rect));
++		}
++	}
++	mutex_unlock(&(isp_obj.isp_mutex));
++	DPRINTK_ISPCTRL("isp_put: new %d\n", isp_obj.ref_count);
++	return isp_obj.ref_count;
++}
++EXPORT_SYMBOL(isp_put);
++
++/**
++ * isp_save_context - Saves the values of the ISP module registers.
++ * @reg_list: Structure containing pairs of register address and value to
++ *            modify on OMAP.
++ **/
++void isp_save_context(struct isp_reg *reg_list)
++{
++	struct isp_reg *next = reg_list;
++
++	for (; next->reg != ISP_TOK_TERM; next++)
++		next->val = isp_reg_readl(next->mmio_range, next->reg);
++}
++EXPORT_SYMBOL(isp_save_context);
++
++/**
++ * isp_restore_context - Restores the values of the ISP module registers.
++ * @reg_list: Structure containing pairs of register address and value to
++ *            modify on OMAP.
++ **/
++void isp_restore_context(struct isp_reg *reg_list)
++{
++	struct isp_reg *next = reg_list;
++
++	for (; next->reg != ISP_TOK_TERM; next++)
++		isp_reg_writel(next->val, next->mmio_range, next->reg);
++}
++EXPORT_SYMBOL(isp_restore_context);
++
++static int isp_remove(struct platform_device *pdev)
++{
++	struct isp_device *isp = platform_get_drvdata(pdev);
++	int i;
++
++	isp_csi2_cleanup();
++	isp_af_exit();
++	isp_resizer_cleanup();
++	isp_preview_cleanup();
++	ispmmu_cleanup();
++	isph3a_aewb_cleanup();
++	isp_hist_cleanup();
++	isp_ccdc_cleanup();
++
++	if (!isp)
++		return 0;
++
++	clk_put(isp_obj.cam_ick);
++	clk_put(isp_obj.cam_mclk);
++	clk_put(isp_obj.csi2_fck);
++
++	free_irq(isp->irq, &isp_obj);
++
++	for (i = 0; i <= OMAP3_ISP_IOMEM_CSI2PHY; i++) {
++		if (isp->mmio_base[i]) {
++			iounmap((void *)isp->mmio_base[i]);
++			isp->mmio_base[i] = 0;
++		}
++
++		if (isp->mmio_base_phys[i]) {
++			release_mem_region(isp->mmio_base_phys[i],
++					   isp->mmio_size[i]);
++			isp->mmio_base_phys[i] = 0;
++		}
++	}
++
++	omap3isp = NULL;
++
++	kfree(isp);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++
++static int isp_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	int reset;
++
++	mutex_lock(&(isp_obj.isp_mutex));
++	DPRINTK_ISPCTRL("isp_suspend: starting\n");
++	if (isp_obj.ref_count == 0)
++		goto out;
++
++	isp_disable_interrupts();
++	reset = isp_suspend_modules();
++	isp_save_ctx();
++	if (reset)
++		isp_reset();
++
++	isp_disable_clocks();
++
++out:
++	DPRINTK_ISPCTRL("isp_suspend: done\n");
++	mutex_unlock(&(isp_obj.isp_mutex));
++	return 0;
++}
++
++static int isp_resume(struct platform_device *pdev)
++{
++	int ret_err = 0;
++
++	DPRINTK_ISPCTRL("isp_resume: starting\n");
++
++	if (omap3isp == NULL)
++		goto out;
++
++	if (isp_obj.ref_count >= 0) {
++		ret_err = isp_enable_clocks();
++		if (ret_err)
++			goto out;
++		isp_restore_ctx();
++		isp_resume_modules();
++		isp_enable_interrupts(RAW_CAPTURE(&isp_obj));
++		isp_start();
++	}
++
++out:
++	DPRINTK_ISPCTRL("isp_resume: done \n");
++	return ret_err;
++}
++
++#else
++
++#define isp_suspend	NULL
++#define isp_resume	NULL
++
++#endif /* CONFIG_PM */
++
++
++static int isp_probe(struct platform_device *pdev)
++{
++	struct isp_device *isp;
++	int ret_err = 0;
++	int i;
++
++	isp = kzalloc(sizeof(*isp), GFP_KERNEL);
++	if (!isp) {
++		dev_err(&pdev->dev, "could not allocate memory\n");
++		return -ENOMEM;
++	}
++
++	platform_set_drvdata(pdev, isp);
++
++	isp->dev = &pdev->dev;
++
++	for (i = 0; i <= OMAP3_ISP_IOMEM_CSI2PHY; i++) {
++		struct resource *mem;
++		/* request the mem region for the camera registers */
++		mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
++		if (!mem) {
++			dev_err(isp->dev, "no mem resource?\n");
++			return -ENODEV;
++		}
++
++		if (!request_mem_region(mem->start, mem->end - mem->start + 1,
++					pdev->name)) {
++			dev_err(isp->dev,
++				"cannot reserve camera register I/O region\n");
++			return -ENODEV;
++
++		}
++		isp->mmio_base_phys[i] = mem->start;
++		isp->mmio_size[i] = mem->end - mem->start + 1;
++
++		/* map the region */
++		isp->mmio_base[i] = (unsigned long)
++			ioremap_nocache(isp->mmio_base_phys[i],
++					isp->mmio_size[i]);
++		if (!isp->mmio_base[i]) {
++			dev_err(isp->dev,
++				"cannot map camera register I/O region\n");
++			return -ENODEV;
++		}
++	}
++
++	isp->irq = platform_get_irq(pdev, 0);
++	if (isp->irq <= 0) {
++		dev_err(isp->dev, "no irq for camera?\n");
++		return -ENODEV;
++	}
++
++	isp_obj.cam_ick = clk_get(&camera_dev, "cam_ick");
++	if (IS_ERR(isp_obj.cam_ick)) {
++		DPRINTK_ISPCTRL("ISP_ERR: clk_get for "
++				"cam_ick failed\n");
++		return PTR_ERR(isp_obj.cam_ick);
++	}
++	isp_obj.cam_mclk = clk_get(&camera_dev, "cam_mclk");
++	if (IS_ERR(isp_obj.cam_mclk)) {
++		DPRINTK_ISPCTRL("ISP_ERR: clk_get for "
++				"cam_mclk failed\n");
++		ret_err = PTR_ERR(isp_obj.cam_mclk);
++		goto out_clk_get_mclk;
++	}
++	isp_obj.csi2_fck = clk_get(&camera_dev, "csi2_96m_fck");
++	if (IS_ERR(isp_obj.csi2_fck)) {
++		DPRINTK_ISPCTRL("ISP_ERR: clk_get for csi2_fclk"
++				" failed\n");
++		ret_err = PTR_ERR(isp_obj.csi2_fck);
++		goto out_clk_get_csi2_fclk;
++	}
++
++	if (request_irq(isp->irq, omap34xx_isp_isr, IRQF_SHARED,
++			"Omap 3 Camera ISP", &isp_obj)) {
++		DPRINTK_ISPCTRL("Could not install ISR\n");
++		ret_err = -EINVAL;
++		goto out_request_irq;
++	}
++
++	isp_obj.ref_count = 0;
++
++	mutex_init(&(isp_obj.isp_mutex));
++	spin_lock_init(&isp_obj.lock);
++	spin_lock_init(&isp_obj.bufs.lock);
++
++	omap3isp = isp;
++
++	ret_err = ispmmu_init();
++	if (ret_err)
++		goto out_ispmmu_init;
++
++	isp_ccdc_init();
++	isp_hist_init();
++	isph3a_aewb_init();
++	isp_preview_init();
++	isp_resizer_init();
++	isp_af_init();
++	isp_csi2_init();
++
++	isp_get();
++	isp_power_settings(1);
++	isp_put();
++
++	isph3a_notify(1);
++	isp_af_notify(1);
++
++	return 0;
++
++out_ispmmu_init:
++	omap3isp = NULL;
++	free_irq(isp->irq, &isp_obj);
++out_request_irq:
++	clk_put(isp_obj.csi2_fck);
++out_clk_get_csi2_fclk:
++	clk_put(isp_obj.cam_mclk);
++out_clk_get_mclk:
++	clk_put(isp_obj.cam_ick);
++
++	return ret_err;
++}
++
++static struct platform_driver omap3isp_driver = {
++	.probe = isp_probe,
++	.remove = isp_remove,
++	.suspend = isp_suspend,
++	.resume = isp_resume,
++	.driver = {
++		.name = "omap3isp",
++	},
++};
++
++/**
++ * isp_init - ISP module initialization.
++ **/
++static int __init isp_init(void)
++{
++	return platform_driver_register(&omap3isp_driver);
++}
++
++/**
++ * isp_cleanup - ISP module cleanup.
++ **/
++static void __exit isp_cleanup(void)
++{
++	platform_driver_unregister(&omap3isp_driver);
++}
++
++/**
++ * isp_print_status - Prints the values of the ISP Control Module registers
++ *
++ * Also prints other debug information stored in the ISP module structure.
++ **/
++void isp_print_status(void)
++{
++	if (!is_ispctrl_debug_enabled())
++		return;
++
++	DPRINTK_ISPCTRL("###ISP_CTRL=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL));
++	DPRINTK_ISPCTRL("###ISP_TCTRL_CTRL=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL));
++	DPRINTK_ISPCTRL("###ISP_SYSCONFIG=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG));
++	DPRINTK_ISPCTRL("###ISP_SYSSTATUS=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_SYSSTATUS));
++	DPRINTK_ISPCTRL("###ISP_IRQ0ENABLE=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE));
++	DPRINTK_ISPCTRL("###ISP_IRQ0STATUS=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS));
++}
++EXPORT_SYMBOL(isp_print_status);
++
++module_init(isp_init);
++module_exit(isp_cleanup);
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("ISP Control Module Library");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/media/video/isp/isp.h b/drivers/media/video/isp/isp.h
+new file mode 100644
+index 0000000..55c98a9
+--- /dev/null
++++ b/drivers/media/video/isp/isp.h
+@@ -0,0 +1,318 @@
++/*
++ * isp.h
++ *
++ * Top level public header file for ISP Control module in
++ * TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments.
++ * Copyright (C) 2009 Nokia.
++ *
++ * Contributors:
++ * 	Sameer Venkatraman <sameerv@ti.com>
++ * 	Mohit Jalori <mjalori@ti.com>
++ * 	Sergio Aguirre <saaguirre@ti.com>
++ * 	Sakari Ailus <sakari.ailus@nokia.com>
++ * 	Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_TOP_H
++#define OMAP_ISP_TOP_H
++#include <mach/cpu.h>
++#include <media/videobuf-dma-sg.h>
++#include <linux/videodev2.h>
++#define OMAP_ISP_CCDC		(1 << 0)
++#define OMAP_ISP_PREVIEW	(1 << 1)
++#define OMAP_ISP_RESIZER	(1 << 2)
++#define OMAP_ISP_AEWB		(1 << 3)
++#define OMAP_ISP_AF		(1 << 4)
++#define OMAP_ISP_HIST		(1 << 5)
++
++#define ISP_TOK_TERM		0xFFFFFFFF	/*
++						 * terminating token for ISP
++						 * modules reg list
++						 */
++#define NUM_BUFS		VIDEO_MAX_FRAME
++
++#ifndef CONFIG_ARCH_OMAP3410
++#define USE_ISP_PREVIEW
++#define USE_ISP_RESZ
++#define is_isppreview_enabled()		1
++#define is_ispresizer_enabled()		1
++#else
++#define is_isppreview_enabled()		0
++#define is_ispresizer_enabled()		0
++#endif
++
++#define ISP_BYTES_PER_PIXEL		2
++#define NUM_ISP_CAPTURE_FORMATS 	(sizeof(isp_formats) /		\
++					 sizeof(isp_formats[0]))
++typedef int (*isp_vbq_callback_ptr) (struct videobuf_buffer *vb);
++typedef void (*isp_callback_t) (unsigned long status,
++				isp_vbq_callback_ptr arg1, void *arg2);
++
++enum isp_mem_resources {
++	OMAP3_ISP_IOMEM_MAIN,
++	OMAP3_ISP_IOMEM_CBUFF,
++	OMAP3_ISP_IOMEM_CCP2,
++	OMAP3_ISP_IOMEM_CCDC,
++	OMAP3_ISP_IOMEM_HIST,
++	OMAP3_ISP_IOMEM_H3A,
++	OMAP3_ISP_IOMEM_PREV,
++	OMAP3_ISP_IOMEM_RESZ,
++	OMAP3_ISP_IOMEM_SBL,
++	OMAP3_ISP_IOMEM_CSI2A,
++	OMAP3_ISP_IOMEM_CSI2PHY
++};
++
++struct isp_device {
++	struct device *dev;
++
++	/*** platform HW resources ***/
++	unsigned int irq;
++
++#define mmio_base_main mmio_base[OMAP3_ISP_IOMEM_MAIN]
++#define mmio_cbuff_main mmio_base[OMAP3_ISP_IOMEM_CBUFF]
++#define mmio_ccp2_main mmio_base[OMAP3_ISP_IOMEM_CCP2]
++#define mmio_ccdc_main mmio_base[OMAP3_ISP_IOMEM_CCDC]
++#define mmio_hist_main mmio_base[OMAP3_ISP_IOMEM_HIST]
++#define mmio_h3a_main mmio_base[OMAP3_ISP_IOMEM_H3A]
++#define mmio_prev_main mmio_base[OMAP3_ISP_IOMEM_PREV]
++#define mmio_resz_main mmio_base[OMAP3_ISP_IOMEM_RESZ]
++#define mmio_sbl_main mmio_base[OMAP3_ISP_IOMEM_SBL]
++#define mmio_csi2_main mmio_base[OMAP3_ISP_IOMEM_CSI2A]
++#define mmio_csi2phy_main mmio_base[OMAP3_ISP_IOMEM_CSI2PHY]
++	unsigned long mmio_base[OMAP3_ISP_IOMEM_CSI2PHY + 1];
++	unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_CSI2PHY + 1];
++	unsigned long mmio_size[OMAP3_ISP_IOMEM_CSI2PHY + 1];
++};
++
++enum isp_interface_type {
++	ISP_PARLL = 1,
++	ISP_CSIA = 2,
++	ISP_CSIB = 4,
++	ISP_NONE = 8 /* memory input to preview / resizer */
++};
++
++enum isp_irqevents {
++	CSIA = 0x01,
++	CSIB = 0x10,
++	CCDC_VD0 = 0x100,
++	CCDC_VD1 = 0x200,
++	CCDC_VD2 = 0x400,
++	CCDC_ERR = 0x800,
++	H3A_AWB_DONE = 0x2000,
++	H3A_AF_DONE = 0x1000,
++	HIST_DONE = 0x10000,
++	PREV_DONE = 0x100000,
++	LSC_DONE = 0x20000,
++	LSC_PRE_COMP = 0x40000,
++	LSC_PRE_ERR = 0x80000,
++	RESZ_DONE = 0x1000000,
++	SBL_OVF = 0x2000000,
++	MMU_ERR = 0x10000000,
++	OCP_ERR = 0x20000000,
++	HS_VS = 0x80000000
++};
++
++enum isp_callback_type {
++	CBK_CCDC_VD0,
++	CBK_CCDC_VD1,
++	CBK_PREV_DONE,
++	CBK_RESZ_DONE,
++	CBK_MMU_ERR,
++	CBK_H3A_AWB_DONE,
++	CBK_HIST_DONE,
++	CBK_HS_VS,
++	CBK_LSC_ISR,
++	CBK_H3A_AF_DONE,
++	CBK_CATCHALL,
++	CBK_CSIA,
++	CBK_CSIB,
++	CBK_END,
++};
++
++/**
++ * struct isp_reg - Structure for ISP register values.
++ * @reg: 32-bit Register address.
++ * @val: 32-bit Register value.
++ */
++struct isp_reg {
++	enum isp_mem_resources mmio_range;
++	u32 reg;
++	u32 val;
++};
++
++/**
++ * struct isp_interface_config - ISP interface configuration.
++ * @ccdc_par_ser: ISP interface type. 0 - Parallel, 1 - CSIA, 2 - CSIB to CCDC.
++ * @par_bridge: CCDC Bridge input control. Parallel interface.
++ *                  0 - Disable, 1 - Enable, first byte->cam_d(bits 7 to 0)
++ *                  2 - Enable, first byte -> cam_d(bits 15 to 8)
++ * @par_clk_pol: Pixel clock polarity on the parallel interface.
++ *                    0 - Non Inverted, 1 - Inverted
++ * @dataline_shift: Data lane shifter.
++ *                      0 - No Shift, 1 - CAMEXT[13 to 2]->CAM[11 to 0]
++ *                      2 - CAMEXT[13 to 4]->CAM[9 to 0]
++ *                      3 - CAMEXT[13 to 6]->CAM[7 to 0]
++ * @hsvs_syncdetect: HS or VS synchronization signal detection.
++ *                       0 - HS Falling, 1 - HS rising
++ *                       2 - VS falling, 3 - VS rising
++ * @strobe: Strobe related parameter.
++ * @prestrobe: PreStrobe related parameter.
++ * @shutter: Shutter related parameter.
++ * @hskip: Horizontal Start Pixel performed in Preview module.
++ * @vskip: Vertical Start Line performed in Preview module.
++ * @wenlog: Store the value for the sensor specific wenlog field.
++ * @wait_hs_vs: Wait for this many hs_vs before anything else in the beginning.
++ */
++struct isp_interface_config {
++	enum isp_interface_type ccdc_par_ser;
++	u8 dataline_shift;
++	u32 hsvs_syncdetect;
++	int strobe;
++	int prestrobe;
++	int shutter;
++	u32 prev_sph;
++	u32 prev_slv;
++	u32 wenlog;
++	int wait_hs_vs;
++	union {
++		struct par {
++			unsigned par_bridge:2;
++			unsigned par_clk_pol:1;
++		} par;
++		struct csi {
++			unsigned crc:1;
++			unsigned mode:1;
++			unsigned edge:1;
++			unsigned signalling:1;
++			unsigned strobe_clock_inv:1;
++			unsigned vs_edge:1;
++			unsigned channel:3;
++			unsigned vpclk:2;	/* Video port output clock */
++			unsigned int data_start;
++			unsigned int data_size;
++			u32 format;		/* V4L2_PIX_FMT_* */
++		} csi;
++	} u;
++};
++
++u32 isp_reg_readl(enum isp_mem_resources isp_mmio_range, u32 reg_offset);
++
++void isp_reg_writel(u32 reg_value, enum isp_mem_resources isp_mmio_range,
++		    u32 reg_offset);
++
++static inline void isp_reg_and(enum isp_mem_resources mmio_range, u32 reg,
++			       u32 and_bits)
++{
++	u32 v = isp_reg_readl(mmio_range, reg);
++
++	isp_reg_writel(v & and_bits, mmio_range, reg);
++}
++
++static inline void isp_reg_or(enum isp_mem_resources mmio_range, u32 reg,
++			      u32 or_bits)
++{
++	u32 v = isp_reg_readl(mmio_range, reg);
++
++	isp_reg_writel(v | or_bits, mmio_range, reg);
++}
++
++static inline void isp_reg_and_or(enum isp_mem_resources mmio_range, u32 reg,
++				  u32 and_bits, u32 or_bits)
++{
++	u32 v = isp_reg_readl(mmio_range, reg);
++
++	isp_reg_writel((v & and_bits) | or_bits, mmio_range, reg);
++}
++
++void isp_start(void);
++
++void isp_stop(void);
++
++int isp_buf_queue(struct videobuf_buffer *vb,
++		  void (*complete)(struct videobuf_buffer *vb, void *priv),
++		  void *priv);
++
++int isp_vbq_setup(struct videobuf_queue *vbq, unsigned int *cnt,
++		  unsigned int *size);
++
++int isp_vbq_prepare(struct videobuf_queue *vbq, struct videobuf_buffer *vb,
++		    enum v4l2_field field);
++
++void isp_vbq_release(struct videobuf_queue *vbq, struct videobuf_buffer *vb);
++
++int isp_set_callback(enum isp_callback_type type, isp_callback_t callback,
++		     isp_vbq_callback_ptr arg1, void *arg2);
++
++int isp_unset_callback(enum isp_callback_type type);
++
++u32 isp_set_xclk(u32 xclk, u8 xclksel);
++
++int isp_configure_interface(struct isp_interface_config *config);
++
++int isp_get(void);
++
++int isp_put(void);
++
++int isp_queryctrl(struct v4l2_queryctrl *a);
++
++int isp_querymenu(struct v4l2_querymenu *a);
++
++int isp_g_ctrl(struct v4l2_control *a);
++
++int isp_s_ctrl(struct v4l2_control *a);
++
++int isp_enum_fmt_cap(struct v4l2_fmtdesc *f);
++
++int isp_try_fmt_cap(struct v4l2_pix_format *pix_input,
++		    struct v4l2_pix_format *pix_output);
++
++void isp_g_fmt_cap(struct v4l2_pix_format *pix);
++
++int isp_s_fmt_cap(struct v4l2_pix_format *pix_input,
++		  struct v4l2_pix_format *pix_output);
++
++int isp_g_crop(struct v4l2_crop *a);
++
++int isp_s_crop(struct v4l2_crop *a, struct v4l2_pix_format *pix);
++
++void isp_config_crop(struct v4l2_pix_format *pix);
++
++int isp_try_fmt(struct v4l2_pix_format *pix_input,
++		struct v4l2_pix_format *pix_output);
++
++int isp_handle_private(int cmd, void *arg);
++
++void isp_save_context(struct isp_reg *);
++
++void isp_restore_context(struct isp_reg *);
++
++void isp_print_status(void);
++
++int __init isp_ccdc_init(void);
++int __init isp_hist_init(void);
++int __init isph3a_aewb_init(void);
++int __init isp_preview_init(void);
++int __init isp_resizer_init(void);
++int __init isp_af_init(void);
++int __init isp_csi2_init(void);
++
++void isp_ccdc_cleanup(void);
++void isp_hist_cleanup(void);
++void isph3a_aewb_cleanup(void);
++void isp_preview_cleanup(void);
++void isp_hist_cleanup(void);
++void isp_resizer_cleanup(void);
++void isp_af_exit(void);
++void isp_csi2_cleanup(void);
++
++#endif	/* OMAP_ISP_TOP_H */
+diff --git a/drivers/media/video/isp/ispreg.h b/drivers/media/video/isp/ispreg.h
+new file mode 100644
+index 0000000..4f8e1ef
+--- /dev/null
++++ b/drivers/media/video/isp/ispreg.h
+@@ -0,0 +1,1674 @@
++/*
++ * ispreg.h
++ *
++ * Header file for all the ISP module in TI's OMAP3 Camera ISP.
++ * It has the OMAP HW register definitions.
++ *
++ * Copyright (C) 2009 Texas Instruments.
++ * Copyright (C) 2009 Nokia.
++ *
++ * Contributors:
++ * 	Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
++ *	Thara Gopinath <thara@ti.com>
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef __ISPREG_H__
++#define __ISPREG_H__
++
++#include <mach/omap34xx.h>
++
++/* Note: Uncomment below defines as needed for enabling module specific debug
++ * messages
++ */
++
++/*
++  #define OMAP_ISPCTRL_DEBUG
++  #define OMAP_ISPCCDC_DEBUG
++  #define OMAP_ISPPREV_DEBUG
++  #define OMAP_ISPRESZ_DEBUG
++  #define OMAP_ISPMMU_DEBUG
++  #define OMAP_ISPH3A_DEBUG
++  #define OMAP_ISP_AF_DEBUG
++  #define OMAP_ISPHIST_DEBUG
++*/
++
++#ifdef OMAP_ISPCTRL_DEBUG
++#define DPRINTK_ISPCTRL(format, ...)				\
++	printk(KERN_INFO "ISPCTRL: " format, ## __VA_ARGS__)
++#define is_ispctrl_debug_enabled()		1
++#else
++#define DPRINTK_ISPCTRL(format, ...)
++#define is_ispctrl_debug_enabled()		0
++#endif
++
++#ifdef OMAP_ISPCCDC_DEBUG
++#define DPRINTK_ISPCCDC(format, ...)				\
++	printk(KERN_INFO "ISPCCDC: " format, ## __VA_ARGS__)
++#define is_ispccdc_debug_enabled()		1
++#else
++#define DPRINTK_ISPCCDC(format, ...)
++#define is_ispccdc_debug_enabled()		0
++#endif
++
++#ifdef OMAP_ISPPREV_DEBUG
++#define DPRINTK_ISPPREV(format, ...)				\
++	printk(KERN_INFO "ISPPREV: " format, ## __VA_ARGS__)
++#define is_ispprev_debug_enabled()		1
++#else
++#define DPRINTK_ISPPREV(format, ...)
++#define is_ispprev_debug_enabled()		0
++#endif
++
++#ifdef OMAP_ISPRESZ_DEBUG
++#define DPRINTK_ISPRESZ(format, ...)				\
++	printk(KERN_INFO "ISPRESZ: " format, ## __VA_ARGS__)
++#define is_ispresz_debug_enabled()		1
++#else
++#define DPRINTK_ISPRESZ(format, ...)
++#define is_ispresz_debug_enabled()		0
++#endif
++
++#ifdef OMAP_ISPMMU_DEBUG
++#define DPRINTK_ISPMMU(format, ...)				\
++	printk(KERN_INFO "ISPMMU: " format, ## __VA_ARGS__)
++#define is_ispmmu_debug_enabled()		1
++#else
++#define DPRINTK_ISPMMU(format, ...)
++#define is_ispmmu_debug_enabled()		0
++#endif
++
++#ifdef OMAP_ISPH3A_DEBUG
++#define DPRINTK_ISPH3A(format, ...)				\
++	printk(KERN_INFO "ISPH3A: " format, ## __VA_ARGS__)
++#define is_isph3a_debug_enabled()		1
++#else
++#define DPRINTK_ISPH3A(format, ...)
++#define is_isph3a_debug_enabled()		0
++#endif
++
++#ifdef OMAP_ISP_AF_DEBUG
++#define DPRINTK_ISP_AF(format, ...)				\
++	printk(KERN_INFO "ISP_AF: " format, ## __VA_ARGS__)
++#define is_isp_af_debug_enabled()		1
++#else
++#define DPRINTK_ISP_AF(format, ...)
++#define is_isp_af_debug_enabled()		0
++#endif
++
++#ifdef OMAP_ISPHIST_DEBUG
++#define DPRINTK_ISPHIST(format, ...)				\
++	printk(KERN_INFO "ISPHIST: " format, ## __VA_ARGS__)
++#define is_isphist_debug_enabled()		1
++#else
++#define DPRINTK_ISPHIST(format, ...)
++#define is_isphist_debug_enabled()		0
++#endif
++
++#define ISP_32B_BOUNDARY_BUF		0xFFFFFFE0
++#define ISP_32B_BOUNDARY_OFFSET		0x0000FFE0
++
++#define CM_CAM_MCLK_HZ			216000000
++
++/* ISP Submodules offset */
++
++#define OMAP3ISP_REG_BASE		OMAP3430_ISP_BASE
++#define OMAP3ISP_REG(offset)		(OMAP3ISP_REG_BASE + (offset))
++
++#define OMAP3ISP_CBUFF_REG_OFFSET	0x0100
++#define OMAP3ISP_CBUFF_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_CBUFF_REG_OFFSET)
++#define OMAP3ISP_CBUFF_REG(offset)	(OMAP3ISP_CBUFF_REG_BASE + (offset))
++
++#define OMAP3ISP_CCP2_REG_OFFSET	0x0400
++#define OMAP3ISP_CCP2_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_CCP2_REG_OFFSET)
++#define OMAP3ISP_CCP2_REG(offset)	(OMAP3ISP_CCP2_REG_BASE + (offset))
++
++#define OMAP3ISP_CCDC_REG_OFFSET	0x0600
++#define OMAP3ISP_CCDC_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_CCDC_REG_OFFSET)
++#define OMAP3ISP_CCDC_REG(offset)	(OMAP3ISP_CCDC_REG_BASE + (offset))
++
++#define OMAP3ISP_HIST_REG_OFFSET	0x0A00
++#define OMAP3ISP_HIST_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_HIST_REG_OFFSET)
++#define OMAP3ISP_HIST_REG(offset)	(OMAP3ISP_HIST_REG_BASE + (offset))
++
++#define OMAP3ISP_H3A_REG_OFFSET		0x0C00
++#define OMAP3ISP_H3A_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_H3A_REG_OFFSET)
++#define OMAP3ISP_H3A_REG(offset)	(OMAP3ISP_H3A_REG_BASE + (offset))
++
++#define OMAP3ISP_PREV_REG_OFFSET	0x0E00
++#define OMAP3ISP_PREV_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_PREV_REG_OFFSET)
++#define OMAP3ISP_PREV_REG(offset)	(OMAP3ISP_PREV_REG_BASE + (offset))
++
++#define OMAP3ISP_RESZ_REG_OFFSET	0x1000
++#define OMAP3ISP_RESZ_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_RESZ_REG_OFFSET)
++#define OMAP3ISP_RESZ_REG(offset)	(OMAP3ISP_RESZ_REG_BASE + (offset))
++
++#define OMAP3ISP_SBL_REG_OFFSET		0x1200
++#define OMAP3ISP_SBL_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_SBL_REG_OFFSET)
++#define OMAP3ISP_SBL_REG(offset)	(OMAP3ISP_SBL_REG_BASE + (offset))
++
++#define OMAP3ISP_MMU_REG_OFFSET		0x1400
++#define OMAP3ISP_MMU_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_MMU_REG_OFFSET)
++#define OMAP3ISP_MMU_REG(offset)	(OMAP3ISP_MMU_REG_BASE + (offset))
++
++#define OMAP3ISP_CSI2A_REG_OFFSET	0x1800
++#define OMAP3ISP_CSI2A_REG_BASE		(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_CSI2A_REG_OFFSET)
++#define OMAP3ISP_CSI2A_REG(offset)	(OMAP3ISP_CSI2A_REG_BASE + (offset))
++
++#define OMAP3ISP_CSI2PHY_REG_OFFSET	0x1970
++#define OMAP3ISP_CSI2PHY_REG_BASE	(OMAP3ISP_REG_BASE +		\
++					 OMAP3ISP_CSI2PHY_REG_OFFSET)
++#define OMAP3ISP_CSI2PHY_REG(offset)	(OMAP3ISP_CSI2PHY_REG_BASE + (offset))
++
++/* ISP module register offset */
++
++#define ISP_REVISION			(0x000)
++#define ISP_SYSCONFIG			(0x004)
++#define ISP_SYSSTATUS			(0x008)
++#define ISP_IRQ0ENABLE			(0x00C)
++#define ISP_IRQ0STATUS			(0x010)
++#define ISP_IRQ1ENABLE			(0x014)
++#define ISP_IRQ1STATUS			(0x018)
++#define ISP_TCTRL_GRESET_LENGTH		(0x030)
++#define ISP_TCTRL_PSTRB_REPLAY		(0x034)
++#define ISP_CTRL			(0x040)
++#define ISP_SECURE			(0x044)
++#define ISP_TCTRL_CTRL			(0x050)
++#define ISP_TCTRL_FRAME			(0x054)
++#define ISP_TCTRL_PSTRB_DELAY		(0x058)
++#define ISP_TCTRL_STRB_DELAY		(0x05C)
++#define ISP_TCTRL_SHUT_DELAY		(0x060)
++#define ISP_TCTRL_PSTRB_LENGTH		(0x064)
++#define ISP_TCTRL_STRB_LENGTH		(0x068)
++#define ISP_TCTRL_SHUT_LENGTH		(0x06C)
++#define ISP_PING_PONG_ADDR		(0x070)
++#define ISP_PING_PONG_MEM_RANGE		(0x074)
++#define ISP_PING_PONG_BUF_SIZE		(0x078)
++
++/* CSI1 receiver registers (ES2.0) */
++#define ISPCSI1_REVISION		(0x000)
++#define ISPCSI1_SYSCONFIG		(0x004)
++#define ISPCSI1_SYSSTATUS		(0x008)
++#define ISPCSI1_LC01_IRQENABLE		(0x00C)
++#define ISPCSI1_LC01_IRQSTATUS		(0x010)
++#define ISPCSI1_LC23_IRQENABLE		(0x014)
++#define ISPCSI1_LC23_IRQSTATUS		(0x018)
++#define ISPCSI1_LCM_IRQENABLE		(0x02C)
++#define ISPCSI1_LCM_IRQSTATUS		(0x030)
++#define ISPCSI1_CTRL			(0x040)
++#define ISPCSI1_DBG			(0x044)
++#define ISPCSI1_GNQ			(0x048)
++#define ISPCSI1_LCx_CTRL(x)		((0x050)+0x30*(x))
++#define ISPCSI1_LCx_CODE(x)		((0x054)+0x30*(x))
++#define ISPCSI1_LCx_STAT_START(x)	((0x058)+0x30*(x))
++#define ISPCSI1_LCx_STAT_SIZE(x)	((0x05C)+0x30*(x))
++#define ISPCSI1_LCx_SOF_ADDR(x)		((0x060)+0x30*(x))
++#define ISPCSI1_LCx_EOF_ADDR(x)		((0x064)+0x30*(x))
++#define ISPCSI1_LCx_DAT_START(x)	((0x068)+0x30*(x))
++#define ISPCSI1_LCx_DAT_SIZE(x)		((0x06C)+0x30*(x))
++#define ISPCSI1_LCx_DAT_PING_ADDR(x)	((0x070)+0x30*(x))
++#define ISPCSI1_LCx_DAT_PONG_ADDR(x)	((0x074)+0x30*(x))
++#define ISPCSI1_LCx_DAT_OFST(x)		((0x078)+0x30*(x))
++#define ISPCSI1_LCM_CTRL		(0x1D0)
++#define ISPCSI1_LCM_VSIZE		(0x1D4)
++#define ISPCSI1_LCM_HSIZE		(0x1D8)
++#define ISPCSI1_LCM_PREFETCH		(0x1DC)
++#define ISPCSI1_LCM_SRC_ADDR		(0x1E0)
++#define ISPCSI1_LCM_SRC_OFST		(0x1E4)
++#define ISPCSI1_LCM_DST_ADDR		(0x1E8)
++#define ISPCSI1_LCM_DST_OFST		(0x1EC)
++#define ISP_CSIB_SYSCONFIG		ISPCSI1_SYSCONFIG
++#define ISP_CSIA_SYSCONFIG		ISPCSI2_SYSCONFIG
++
++/* ISP_CBUFF Registers */
++
++#define ISP_CBUFF_SYSCONFIG		(0x010)
++#define ISP_CBUFF_IRQENABLE		(0x01C)
++
++#define ISP_CBUFF0_CTRL			(0x020)
++#define ISP_CBUFF1_CTRL			(0x024)
++
++#define ISP_CBUFF0_START		(0x040)
++#define ISP_CBUFF1_START		(0x044)
++
++#define ISP_CBUFF0_END			(0x050)
++#define ISP_CBUFF1_END			(0x054)
++
++#define ISP_CBUFF0_WINDOWSIZE		(0x060)
++#define ISP_CBUFF1_WINDOWSIZE		(0x064)
++
++#define ISP_CBUFF0_THRESHOLD		(0x070)
++#define ISP_CBUFF1_THRESHOLD		(0x074)
++
++/* CCDC module register offset */
++
++#define ISPCCDC_PID			(0x000)
++#define ISPCCDC_PCR			(0x004)
++#define ISPCCDC_SYN_MODE		(0x008)
++#define ISPCCDC_HD_VD_WID		(0x00C)
++#define ISPCCDC_PIX_LINES		(0x010)
++#define ISPCCDC_HORZ_INFO		(0x014)
++#define ISPCCDC_VERT_START		(0x018)
++#define ISPCCDC_VERT_LINES		(0x01C)
++#define ISPCCDC_CULLING			(0x020)
++#define ISPCCDC_HSIZE_OFF		(0x024)
++#define ISPCCDC_SDOFST			(0x028)
++#define ISPCCDC_SDR_ADDR		(0x02C)
++#define ISPCCDC_CLAMP			(0x030)
++#define ISPCCDC_DCSUB			(0x034)
++#define ISPCCDC_COLPTN			(0x038)
++#define ISPCCDC_BLKCMP			(0x03C)
++#define ISPCCDC_FPC			(0x040)
++#define ISPCCDC_FPC_ADDR		(0x044)
++#define ISPCCDC_VDINT			(0x048)
++#define ISPCCDC_ALAW			(0x04C)
++#define ISPCCDC_REC656IF		(0x050)
++#define ISPCCDC_CFG			(0x054)
++#define ISPCCDC_FMTCFG			(0x058)
++#define ISPCCDC_FMT_HORZ		(0x05C)
++#define ISPCCDC_FMT_VERT		(0x060)
++#define ISPCCDC_FMT_ADDR0		(0x064)
++#define ISPCCDC_FMT_ADDR1		(0x068)
++#define ISPCCDC_FMT_ADDR2		(0x06C)
++#define ISPCCDC_FMT_ADDR3		(0x070)
++#define ISPCCDC_FMT_ADDR4		(0x074)
++#define ISPCCDC_FMT_ADDR5		(0x078)
++#define ISPCCDC_FMT_ADDR6		(0x07C)
++#define ISPCCDC_FMT_ADDR7		(0x080)
++#define ISPCCDC_PRGEVEN0		(0x084)
++#define ISPCCDC_PRGEVEN1		(0x088)
++#define ISPCCDC_PRGODD0			(0x08C)
++#define ISPCCDC_PRGODD1			(0x090)
++#define ISPCCDC_VP_OUT			(0x094)
++
++#define ISPCCDC_LSC_CONFIG		(0x098)
++#define ISPCCDC_LSC_INITIAL		(0x09C)
++#define ISPCCDC_LSC_TABLE_BASE		(0x0A0)
++#define ISPCCDC_LSC_TABLE_OFFSET	(0x0A4)
++
++/* SBL */
++#define ISPSBL_CCDC_WR_0		(0x028)
++#define ISPSBL_CCDC_WR_0_DATA_READY	(1 << 21)
++#define ISPSBL_CCDC_WR_1		(0x02C)
++#define ISPSBL_CCDC_WR_2		(0x030)
++#define ISPSBL_CCDC_WR_3		(0x034)
++
++/* Histogram registers */
++#define ISPHIST_PID			(0x000)
++#define ISPHIST_PCR			(0x004)
++#define ISPHIST_CNT			(0x008)
++#define ISPHIST_WB_GAIN			(0x00C)
++#define ISPHIST_R0_HORZ			(0x010)
++#define ISPHIST_R0_VERT			(0x014)
++#define ISPHIST_R1_HORZ			(0x018)
++#define ISPHIST_R1_VERT			(0x01C)
++#define ISPHIST_R2_HORZ			(0x020)
++#define ISPHIST_R2_VERT			(0x024)
++#define ISPHIST_R3_HORZ			(0x028)
++#define ISPHIST_R3_VERT			(0x02C)
++#define ISPHIST_ADDR			(0x030)
++#define ISPHIST_DATA			(0x034)
++#define ISPHIST_RADD			(0x038)
++#define ISPHIST_RADD_OFF		(0x03C)
++#define ISPHIST_H_V_INFO		(0x040)
++
++/* H3A module registers */
++#define ISPH3A_PID			(0x000)
++#define ISPH3A_PCR			(0x004)
++#define ISPH3A_AEWWIN1			(0x04C)
++#define ISPH3A_AEWINSTART		(0x050)
++#define ISPH3A_AEWINBLK			(0x054)
++#define ISPH3A_AEWSUBWIN		(0x058)
++#define ISPH3A_AEWBUFST			(0x05C)
++#define ISPH3A_AFPAX1			(0x008)
++#define ISPH3A_AFPAX2			(0x00C)
++#define ISPH3A_AFPAXSTART		(0x010)
++#define ISPH3A_AFIIRSH			(0x014)
++#define ISPH3A_AFBUFST			(0x018)
++#define ISPH3A_AFCOEF010		(0x01C)
++#define ISPH3A_AFCOEF032		(0x020)
++#define ISPH3A_AFCOEF054		(0x024)
++#define ISPH3A_AFCOEF076		(0x028)
++#define ISPH3A_AFCOEF098		(0x02C)
++#define ISPH3A_AFCOEF0010		(0x030)
++#define ISPH3A_AFCOEF110		(0x034)
++#define ISPH3A_AFCOEF132		(0x038)
++#define ISPH3A_AFCOEF154		(0x03C)
++#define ISPH3A_AFCOEF176		(0x040)
++#define ISPH3A_AFCOEF198		(0x044)
++#define ISPH3A_AFCOEF1010		(0x048)
++
++#define ISPPRV_PCR			(0x004)
++#define ISPPRV_HORZ_INFO		(0x008)
++#define ISPPRV_VERT_INFO		(0x00C)
++#define ISPPRV_RSDR_ADDR		(0x010)
++#define ISPPRV_RADR_OFFSET		(0x014)
++#define ISPPRV_DSDR_ADDR		(0x018)
++#define ISPPRV_DRKF_OFFSET		(0x01C)
++#define ISPPRV_WSDR_ADDR		(0x020)
++#define ISPPRV_WADD_OFFSET		(0x024)
++#define ISPPRV_AVE			(0x028)
++#define ISPPRV_HMED			(0x02C)
++#define ISPPRV_NF			(0x030)
++#define ISPPRV_WB_DGAIN			(0x034)
++#define ISPPRV_WBGAIN			(0x038)
++#define ISPPRV_WBSEL			(0x03C)
++#define ISPPRV_CFA			(0x040)
++#define ISPPRV_BLKADJOFF		(0x044)
++#define ISPPRV_RGB_MAT1			(0x048)
++#define ISPPRV_RGB_MAT2			(0x04C)
++#define ISPPRV_RGB_MAT3			(0x050)
++#define ISPPRV_RGB_MAT4			(0x054)
++#define ISPPRV_RGB_MAT5			(0x058)
++#define ISPPRV_RGB_OFF1			(0x05C)
++#define ISPPRV_RGB_OFF2			(0x060)
++#define ISPPRV_CSC0			(0x064)
++#define ISPPRV_CSC1			(0x068)
++#define ISPPRV_CSC2			(0x06C)
++#define ISPPRV_CSC_OFFSET		(0x070)
++#define ISPPRV_CNT_BRT			(0x074)
++#define ISPPRV_CSUP			(0x078)
++#define ISPPRV_SETUP_YC			(0x07C)
++#define ISPPRV_SET_TBL_ADDR		(0x080)
++#define ISPPRV_SET_TBL_DATA		(0x084)
++#define ISPPRV_CDC_THR0			(0x090)
++#define ISPPRV_CDC_THR1			(ISPPRV_CDC_THR0 + (0x4))
++#define ISPPRV_CDC_THR2			(ISPPRV_CDC_THR0 + (0x4) * 2)
++#define ISPPRV_CDC_THR3			(ISPPRV_CDC_THR0 + (0x4) * 3)
++
++#define ISPPRV_REDGAMMA_TABLE_ADDR	0x0000
++#define ISPPRV_GREENGAMMA_TABLE_ADDR	0x0400
++#define ISPPRV_BLUEGAMMA_TABLE_ADDR	0x0800
++#define ISPPRV_NF_TABLE_ADDR		0x0C00
++#define ISPPRV_YENH_TABLE_ADDR		0x1000
++#define ISPPRV_CFA_TABLE_ADDR		0x1400
++
++#define ISPPRV_MAXOUTPUT_WIDTH		1280
++#define ISPPRV_MAXOUTPUT_WIDTH_ES2	3300
++#define ISPRSZ_MIN_OUTPUT		64
++#define ISPRSZ_MAX_OUTPUT		3312
++
++/* Resizer module register offset */
++#define ISPRSZ_PID			(0x000)
++#define ISPRSZ_PCR			(0x004)
++#define ISPRSZ_CNT			(0x008)
++#define ISPRSZ_OUT_SIZE			(0x00C)
++#define ISPRSZ_IN_START			(0x010)
++#define ISPRSZ_IN_SIZE			(0x014)
++#define ISPRSZ_SDR_INADD		(0x018)
++#define ISPRSZ_SDR_INOFF		(0x01C)
++#define ISPRSZ_SDR_OUTADD		(0x020)
++#define ISPRSZ_SDR_OUTOFF		(0x024)
++#define ISPRSZ_HFILT10			(0x028)
++#define ISPRSZ_HFILT32			(0x02C)
++#define ISPRSZ_HFILT54			(0x030)
++#define ISPRSZ_HFILT76			(0x034)
++#define ISPRSZ_HFILT98			(0x038)
++#define ISPRSZ_HFILT1110		(0x03C)
++#define ISPRSZ_HFILT1312		(0x040)
++#define ISPRSZ_HFILT1514		(0x044)
++#define ISPRSZ_HFILT1716		(0x048)
++#define ISPRSZ_HFILT1918		(0x04C)
++#define ISPRSZ_HFILT2120		(0x050)
++#define ISPRSZ_HFILT2322		(0x054)
++#define ISPRSZ_HFILT2524		(0x058)
++#define ISPRSZ_HFILT2726		(0x05C)
++#define ISPRSZ_HFILT2928		(0x060)
++#define ISPRSZ_HFILT3130		(0x064)
++#define ISPRSZ_VFILT10			(0x068)
++#define ISPRSZ_VFILT32			(0x06C)
++#define ISPRSZ_VFILT54			(0x070)
++#define ISPRSZ_VFILT76			(0x074)
++#define ISPRSZ_VFILT98			(0x078)
++#define ISPRSZ_VFILT1110		(0x07C)
++#define ISPRSZ_VFILT1312		(0x080)
++#define ISPRSZ_VFILT1514		(0x084)
++#define ISPRSZ_VFILT1716		(0x088)
++#define ISPRSZ_VFILT1918		(0x08C)
++#define ISPRSZ_VFILT2120		(0x090)
++#define ISPRSZ_VFILT2322		(0x094)
++#define ISPRSZ_VFILT2524		(0x098)
++#define ISPRSZ_VFILT2726		(0x09C)
++#define ISPRSZ_VFILT2928		(0x0A0)
++#define ISPRSZ_VFILT3130		(0x0A4)
++#define ISPRSZ_YENH			(0x0A8)
++
++/* MMU module registers */
++#define ISPMMU_REVISION			(0x000)
++#define ISPMMU_SYSCONFIG		(0x010)
++#define ISPMMU_SYSSTATUS		(0x014)
++#define ISPMMU_IRQSTATUS		(0x018)
++#define ISPMMU_IRQENABLE		(0x01C)
++#define ISPMMU_WALKING_ST		(0x040)
++#define ISPMMU_CNTL			(0x044)
++#define ISPMMU_FAULT_AD			(0x048)
++#define ISPMMU_TTB			(0x04C)
++#define ISPMMU_LOCK			(0x050)
++#define ISPMMU_LD_TLB			(0x054)
++#define ISPMMU_CAM			(0x058)
++#define ISPMMU_RAM			(0x05C)
++#define ISPMMU_GFLUSH			(0x060)
++#define ISPMMU_FLUSH_ENTRY		(0x064)
++#define ISPMMU_READ_CAM			(0x068)
++#define ISPMMU_READ_RAM			(0x06c)
++#define ISPMMU_EMU_FAULT_AD		(0x070)
++
++#define ISP_INT_CLR			0xFF113F11
++#define ISPPRV_PCR_EN			1
++#define ISPPRV_PCR_BUSY			(1 << 1)
++#define ISPPRV_PCR_SOURCE		(1 << 2)
++#define ISPPRV_PCR_ONESHOT		(1 << 3)
++#define ISPPRV_PCR_WIDTH		(1 << 4)
++#define ISPPRV_PCR_INVALAW		(1 << 5)
++#define ISPPRV_PCR_DRKFEN		(1 << 6)
++#define ISPPRV_PCR_DRKFCAP		(1 << 7)
++#define ISPPRV_PCR_HMEDEN		(1 << 8)
++#define ISPPRV_PCR_NFEN			(1 << 9)
++#define ISPPRV_PCR_CFAEN		(1 << 10)
++#define ISPPRV_PCR_CFAFMT_SHIFT		11
++#define ISPPRV_PCR_CFAFMT_MASK		0x7800
++#define ISPPRV_PCR_CFAFMT_BAYER		(0 << 11)
++#define ISPPRV_PCR_CFAFMT_SONYVGA	(1 << 11)
++#define ISPPRV_PCR_CFAFMT_RGBFOVEON	(2 << 11)
++#define ISPPRV_PCR_CFAFMT_DNSPL		(3 << 11)
++#define ISPPRV_PCR_CFAFMT_HONEYCOMB	(4 << 11)
++#define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON	(5 << 11)
++#define ISPPRV_PCR_YNENHEN		(1 << 15)
++#define ISPPRV_PCR_SUPEN		(1 << 16)
++#define ISPPRV_PCR_YCPOS_SHIFT		17
++#define ISPPRV_PCR_YCPOS_YCrYCb		(0 << 17)
++#define ISPPRV_PCR_YCPOS_YCbYCr		(1 << 17)
++#define ISPPRV_PCR_YCPOS_CbYCrY		(2 << 17)
++#define ISPPRV_PCR_YCPOS_CrYCbY		(3 << 17)
++#define ISPPRV_PCR_RSZPORT		(1 << 19)
++#define ISPPRV_PCR_SDRPORT		(1 << 20)
++#define ISPPRV_PCR_SCOMP_EN		(1 << 21)
++#define ISPPRV_PCR_SCOMP_SFT_SHIFT	(22)
++#define ISPPRV_PCR_SCOMP_SFT_MASK	(~(7 << 22))
++#define ISPPRV_PCR_GAMMA_BYPASS		(1 << 26)
++#define ISPPRV_PCR_DCOREN		(1 << 27)
++#define ISPPRV_PCR_DCCOUP		(1 << 28)
++#define ISPPRV_PCR_DRK_FAIL		(1 << 31)
++
++#define ISPPRV_HORZ_INFO_EPH_SHIFT	0
++#define ISPPRV_HORZ_INFO_EPH_MASK	0x3fff
++#define ISPPRV_HORZ_INFO_SPH_SHIFT	16
++#define ISPPRV_HORZ_INFO_SPH_MASK	0x3fff0
++
++#define ISPPRV_VERT_INFO_ELV_SHIFT	0
++#define ISPPRV_VERT_INFO_ELV_MASK	0x3fff
++#define ISPPRV_VERT_INFO_SLV_SHIFT	16
++#define ISPPRV_VERT_INFO_SLV_MASK	0x3fff0
++
++#define ISPPRV_AVE_EVENDIST_SHIFT	2
++#define ISPPRV_AVE_EVENDIST_1		0x0
++#define ISPPRV_AVE_EVENDIST_2		0x1
++#define ISPPRV_AVE_EVENDIST_3		0x2
++#define ISPPRV_AVE_EVENDIST_4		0x3
++#define ISPPRV_AVE_ODDDIST_SHIFT	4
++#define ISPPRV_AVE_ODDDIST_1		0x0
++#define ISPPRV_AVE_ODDDIST_2		0x1
++#define ISPPRV_AVE_ODDDIST_3		0x2
++#define ISPPRV_AVE_ODDDIST_4		0x3
++
++#define ISPPRV_HMED_THRESHOLD_SHIFT	0
++#define ISPPRV_HMED_EVENDIST		(1 << 8)
++#define ISPPRV_HMED_ODDDIST		(1 << 9)
++
++#define ISPPRV_WBGAIN_COEF0_SHIFT	0
++#define ISPPRV_WBGAIN_COEF1_SHIFT	8
++#define ISPPRV_WBGAIN_COEF2_SHIFT	16
++#define ISPPRV_WBGAIN_COEF3_SHIFT	24
++
++#define ISPPRV_WBSEL_COEF0		0x0
++#define ISPPRV_WBSEL_COEF1		0x1
++#define ISPPRV_WBSEL_COEF2		0x2
++#define ISPPRV_WBSEL_COEF3		0x3
++
++#define ISPPRV_WBSEL_N0_0_SHIFT		0
++#define ISPPRV_WBSEL_N0_1_SHIFT		2
++#define ISPPRV_WBSEL_N0_2_SHIFT		4
++#define ISPPRV_WBSEL_N0_3_SHIFT		6
++#define ISPPRV_WBSEL_N1_0_SHIFT		8
++#define ISPPRV_WBSEL_N1_1_SHIFT		10
++#define ISPPRV_WBSEL_N1_2_SHIFT		12
++#define ISPPRV_WBSEL_N1_3_SHIFT		14
++#define ISPPRV_WBSEL_N2_0_SHIFT		16
++#define ISPPRV_WBSEL_N2_1_SHIFT		18
++#define ISPPRV_WBSEL_N2_2_SHIFT		20
++#define ISPPRV_WBSEL_N2_3_SHIFT		22
++#define ISPPRV_WBSEL_N3_0_SHIFT		24
++#define ISPPRV_WBSEL_N3_1_SHIFT		26
++#define ISPPRV_WBSEL_N3_2_SHIFT		28
++#define ISPPRV_WBSEL_N3_3_SHIFT		30
++
++#define ISPPRV_CFA_GRADTH_HOR_SHIFT	0
++#define ISPPRV_CFA_GRADTH_VER_SHIFT	8
++
++#define ISPPRV_BLKADJOFF_B_SHIFT	0
++#define ISPPRV_BLKADJOFF_G_SHIFT	8
++#define ISPPRV_BLKADJOFF_R_SHIFT	16
++
++#define ISPPRV_RGB_MAT1_MTX_RR_SHIFT	0
++#define ISPPRV_RGB_MAT1_MTX_GR_SHIFT	16
++
++#define ISPPRV_RGB_MAT2_MTX_BR_SHIFT	0
++#define ISPPRV_RGB_MAT2_MTX_RG_SHIFT	16
++
++#define ISPPRV_RGB_MAT3_MTX_GG_SHIFT	0
++#define ISPPRV_RGB_MAT3_MTX_BG_SHIFT	16
++
++#define ISPPRV_RGB_MAT4_MTX_RB_SHIFT	0
++#define ISPPRV_RGB_MAT4_MTX_GB_SHIFT	16
++
++#define ISPPRV_RGB_MAT5_MTX_BB_SHIFT	0
++
++#define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT	0
++#define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT	16
++
++#define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT	0
++
++#define ISPPRV_CSC0_RY_SHIFT		0
++#define ISPPRV_CSC0_GY_SHIFT		10
++#define ISPPRV_CSC0_BY_SHIFT		20
++
++#define ISPPRV_CSC1_RCB_SHIFT		0
++#define ISPPRV_CSC1_GCB_SHIFT		10
++#define ISPPRV_CSC1_BCB_SHIFT		20
++
++#define ISPPRV_CSC2_RCR_SHIFT		0
++#define ISPPRV_CSC2_GCR_SHIFT		10
++#define ISPPRV_CSC2_BCR_SHIFT		20
++
++#define ISPPRV_CSC_OFFSET_CR_SHIFT	0
++#define ISPPRV_CSC_OFFSET_CB_SHIFT	8
++#define ISPPRV_CSC_OFFSET_Y_SHIFT	16
++
++#define ISPPRV_CNT_BRT_BRT_SHIFT	0
++#define ISPPRV_CNT_BRT_CNT_SHIFT	8
++
++#define ISPPRV_CONTRAST_MAX		0x10
++#define ISPPRV_CONTRAST_MIN		0xFF
++#define ISPPRV_BRIGHT_MIN		0x00
++#define ISPPRV_BRIGHT_MAX		0xFF
++
++#define ISPPRV_CSUP_CSUPG_SHIFT		0
++#define ISPPRV_CSUP_THRES_SHIFT		8
++#define ISPPRV_CSUP_HPYF_SHIFT		16
++
++#define ISPPRV_SETUP_YC_MINC_SHIFT	0
++#define ISPPRV_SETUP_YC_MAXC_SHIFT	8
++#define ISPPRV_SETUP_YC_MINY_SHIFT	16
++#define ISPPRV_SETUP_YC_MAXY_SHIFT	24
++#define ISPPRV_YC_MAX			0xFF
++#define ISPPRV_YC_MIN			0x0
++
++/* Define bit fields within selected registers */
++#define ISP_REVISION_SHIFT			0
++
++#define ISP_SYSCONFIG_AUTOIDLE			0
++#define ISP_SYSCONFIG_SOFTRESET			(1 << 1)
++#define ISP_SYSCONFIG_MIDLEMODE_SHIFT		12
++#define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY	0x0
++#define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY	0x1
++#define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY	0x2
++
++#define ISP_SYSSTATUS_RESETDONE			0
++
++#define IRQ0ENABLE_CSIA_IRQ			1
++#define IRQ0ENABLE_CSIA_LC1_IRQ			(1 << 1)
++#define IRQ0ENABLE_CSIA_LC2_IRQ			(1 << 2)
++#define IRQ0ENABLE_CSIA_LC3_IRQ			(1 << 3)
++#define IRQ0ENABLE_CSIB_IRQ			(1 << 4)
++#define IRQ0ENABLE_CSIB_LC1_IRQ			(1 << 5)
++#define IRQ0ENABLE_CSIB_LC2_IRQ			(1 << 6)
++#define IRQ0ENABLE_CSIB_LC3_IRQ			(1 << 7)
++#define IRQ0ENABLE_CCDC_VD0_IRQ			(1 << 8)
++#define IRQ0ENABLE_CCDC_VD1_IRQ			(1 << 9)
++#define IRQ0ENABLE_CCDC_VD2_IRQ			(1 << 10)
++#define IRQ0ENABLE_CCDC_ERR_IRQ			(1 << 11)
++#define IRQ0ENABLE_H3A_AF_DONE_IRQ		(1 << 12)
++#define IRQ0ENABLE_H3A_AWB_DONE_IRQ		(1 << 13)
++#define IRQ0ENABLE_HIST_DONE_IRQ		(1 << 16)
++#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ		(1 << 17)
++#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ	(1 << 18)
++#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ	(1 << 19)
++#define IRQ0ENABLE_PRV_DONE_IRQ			(1 << 20)
++#define IRQ0ENABLE_RSZ_DONE_IRQ			(1 << 24)
++#define IRQ0ENABLE_OVF_IRQ			(1 << 25)
++#define IRQ0ENABLE_PING_IRQ			(1 << 26)
++#define IRQ0ENABLE_PONG_IRQ			(1 << 27)
++#define IRQ0ENABLE_MMU_ERR_IRQ			(1 << 28)
++#define IRQ0ENABLE_OCP_ERR_IRQ			(1 << 29)
++#define IRQ0ENABLE_SEC_ERR_IRQ			(1 << 30)
++#define IRQ0ENABLE_HS_VS_IRQ			(1 << 31)
++
++#define IRQ0STATUS_CSIA_IRQ			1
++#define IRQ0STATUS_CSIA_LC1_IRQ			(1 << 1)
++#define IRQ0STATUS_CSIA_LC2_IRQ			(1 << 2)
++#define IRQ0STATUS_CSIA_LC3_IRQ			(1 << 3)
++#define IRQ0STATUS_CSIB_IRQ			(1 << 4)
++#define IRQ0STATUS_CSIB_LC1_IRQ			(1 << 5)
++#define IRQ0STATUS_CSIB_LC2_IRQ			(1 << 6)
++#define IRQ0STATUS_CSIB_LC3_IRQ			(1 << 7)
++#define IRQ0STATUS_CCDC_VD0_IRQ			(1 << 8)
++#define IRQ0STATUS_CCDC_VD1_IRQ			(1 << 9)
++#define IRQ0STATUS_CCDC_VD2_IRQ			(1 << 10)
++#define IRQ0STATUS_CCDC_ERR_IRQ			(1 << 11)
++#define IRQ0STATUS_H3A_AF_DONE_IRQ		(1 << 12)
++#define IRQ0STATUS_H3A_AWB_DONE_IRQ		(1 << 13)
++#define IRQ0STATUS_HIST_DONE_IRQ		(1 << 16)
++#define IRQ0STATUS_PRV_DONE_IRQ			(1 << 20)
++#define IRQ0STATUS_RSZ_DONE_IRQ			(1 << 24)
++#define IRQ0STATUS_OVF_IRQ			(1 << 25)
++#define IRQ0STATUS_PING_IRQ			(1 << 26)
++#define IRQ0STATUS_PONG_IRQ			(1 << 27)
++#define IRQ0STATUS_MMU_ERR_IRQ			(1 << 28)
++#define IRQ0STATUS_OCP_ERR_IRQ			(1 << 29)
++#define IRQ0STATUS_SEC_ERR_IRQ			(1 << 30)
++#define IRQ0STATUS_HS_VS_IRQ			(1 << 31)
++
++#define TCTRL_GRESET_LEN			0
++
++#define TCTRL_PSTRB_REPLAY_DELAY		0
++#define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT	25
++
++#define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL	0x0
++#define ISPCTRL_PAR_SER_CLK_SEL_CSIA		0x1
++#define ISPCTRL_PAR_SER_CLK_SEL_CSIB		0x2
++#define ISPCTRL_PAR_SER_CLK_SEL_MASK		0xFFFFFFFC
++
++#define ISPCTRL_PAR_BRIDGE_SHIFT		2
++#define ISPCTRL_PAR_BRIDGE_DISABLE		(0x0 << 2)
++#define ISPCTRL_PAR_BRIDGE_LENDIAN		(0x2 << 2)
++#define ISPCTRL_PAR_BRIDGE_BENDIAN		(0x3 << 2)
++
++#define ISPCTRL_PAR_CLK_POL_SHIFT		4
++#define ISPCTRL_PAR_CLK_POL_INV			(1 << 4)
++#define ISPCTRL_PING_PONG_EN			(1 << 5)
++#define ISPCTRL_SHIFT_SHIFT			6
++#define ISPCTRL_SHIFT_0				(0x0 << 6)
++#define ISPCTRL_SHIFT_2				(0x1 << 6)
++#define ISPCTRL_SHIFT_4				(0x2 << 6)
++#define ISPCTRL_SHIFT_MASK			(~(0x3 << 6))
++
++#define ISPCTRL_CCDC_CLK_EN			(1 << 8)
++#define ISPCTRL_SCMP_CLK_EN			(1 << 9)
++#define ISPCTRL_H3A_CLK_EN			(1 << 10)
++#define ISPCTRL_HIST_CLK_EN			(1 << 11)
++#define ISPCTRL_PREV_CLK_EN			(1 << 12)
++#define ISPCTRL_RSZ_CLK_EN			(1 << 13)
++#define ISPCTRL_SYNC_DETECT_SHIFT		14
++#define ISPCTRL_SYNC_DETECT_HSFALL	(0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
++#define ISPCTRL_SYNC_DETECT_HSRISE	(0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
++#define ISPCTRL_SYNC_DETECT_VSFALL	(0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
++#define ISPCTRL_SYNC_DETECT_VSRISE	(0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
++#define ISPCTRL_SYNC_DETECT_MASK	(0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
++
++#define ISPCTRL_CCDC_RAM_EN		(1 << 16)
++#define ISPCTRL_PREV_RAM_EN		(1 << 17)
++#define ISPCTRL_SBL_RD_RAM_EN		(1 << 18)
++#define ISPCTRL_SBL_WR1_RAM_EN		(1 << 19)
++#define ISPCTRL_SBL_WR0_RAM_EN		(1 << 20)
++#define ISPCTRL_SBL_AUTOIDLE		(1 << 21)
++#define ISPCTRL_SBL_SHARED_RPORTB	(1 << 28)
++#define ISPCTRL_JPEG_FLUSH		(1 << 30)
++#define ISPCTRL_CCDC_FLUSH		(1 << 31)
++
++#define ISPSECURE_SECUREMODE		0
++
++#define ISPTCTRL_CTRL_DIV_LOW		0x0
++#define ISPTCTRL_CTRL_DIV_HIGH		0x1
++#define ISPTCTRL_CTRL_DIV_BYPASS	0x1F
++
++#define ISPTCTRL_CTRL_DIVA_SHIFT	0
++#define ISPTCTRL_CTRL_DIVA_MASK		(0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
++
++#define ISPTCTRL_CTRL_DIVB_SHIFT	5
++#define ISPTCTRL_CTRL_DIVB_MASK		(0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
++
++#define ISPTCTRL_CTRL_DIVC_SHIFT	10
++#define ISPTCTRL_CTRL_DIVC_NOCLOCK	(0x0 << 10)
++
++#define ISPTCTRL_CTRL_SHUTEN		(1 << 21)
++#define ISPTCTRL_CTRL_PSTRBEN		(1 << 22)
++#define ISPTCTRL_CTRL_STRBEN		(1 << 23)
++#define ISPTCTRL_CTRL_SHUTPOL		(1 << 24)
++#define ISPTCTRL_CTRL_STRBPSTRBPOL	(1 << 26)
++
++#define ISPTCTRL_CTRL_INSEL_SHIFT	27
++#define ISPTCTRL_CTRL_INSEL_PARALLEL	(0x0 << 27)
++#define ISPTCTRL_CTRL_INSEL_CSIA	(0x1 << 27)
++#define ISPTCTRL_CTRL_INSEL_CSIB	(0x2 << 27)
++
++#define ISPTCTRL_CTRL_GRESETEn		(1 << 29)
++#define ISPTCTRL_CTRL_GRESETPOL		(1 << 30)
++#define ISPTCTRL_CTRL_GRESETDIR		(1 << 31)
++
++#define ISPTCTRL_FRAME_SHUT_SHIFT		0
++#define ISPTCTRL_FRAME_PSTRB_SHIFT		6
++#define ISPTCTRL_FRAME_STRB_SHIFT		12
++
++#define ISPCCDC_PID_PREV_SHIFT			0
++#define ISPCCDC_PID_CID_SHIFT			8
++#define ISPCCDC_PID_TID_SHIFT			16
++
++#define ISPCCDC_PCR_EN				1
++#define ISPCCDC_PCR_BUSY			(1 << 1)
++
++#define ISPCCDC_SYN_MODE_VDHDOUT		0x1
++#define ISPCCDC_SYN_MODE_FLDOUT			(1 << 1)
++#define ISPCCDC_SYN_MODE_VDPOL			(1 << 2)
++#define ISPCCDC_SYN_MODE_HDPOL			(1 << 3)
++#define ISPCCDC_SYN_MODE_FLDPOL			(1 << 4)
++#define ISPCCDC_SYN_MODE_EXWEN			(1 << 5)
++#define ISPCCDC_SYN_MODE_DATAPOL		(1 << 6)
++#define ISPCCDC_SYN_MODE_FLDMODE		(1 << 7)
++#define ISPCCDC_SYN_MODE_DATSIZ_MASK		0xFFFFF8FF
++#define ISPCCDC_SYN_MODE_DATSIZ_8_16		(0x0 << 8)
++#define ISPCCDC_SYN_MODE_DATSIZ_12		(0x4 << 8)
++#define ISPCCDC_SYN_MODE_DATSIZ_11		(0x5 << 8)
++#define ISPCCDC_SYN_MODE_DATSIZ_10		(0x6 << 8)
++#define ISPCCDC_SYN_MODE_DATSIZ_8		(0x7 << 8)
++#define ISPCCDC_SYN_MODE_PACK8			(1 << 11)
++#define ISPCCDC_SYN_MODE_INPMOD_MASK		0xFFFFCFFF
++#define ISPCCDC_SYN_MODE_INPMOD_RAW		(0 << 12)
++#define ISPCCDC_SYN_MODE_INPMOD_YCBCR16		(1 << 12)
++#define ISPCCDC_SYN_MODE_INPMOD_YCBCR8		(2 << 12)
++#define ISPCCDC_SYN_MODE_LPF			(1 << 14)
++#define ISPCCDC_SYN_MODE_FLDSTAT		(1 << 15)
++#define ISPCCDC_SYN_MODE_VDHDEN			(1 << 16)
++#define ISPCCDC_SYN_MODE_WEN			(1 << 17)
++#define ISPCCDC_SYN_MODE_VP2SDR			(1 << 18)
++#define ISPCCDC_SYN_MODE_SDR2RSZ		(1 << 19)
++
++#define ISPCCDC_HD_VD_WID_VDW_SHIFT		0
++#define ISPCCDC_HD_VD_WID_HDW_SHIFT		16
++
++#define ISPCCDC_PIX_LINES_HLPRF_SHIFT		0
++#define ISPCCDC_PIX_LINES_PPLN_SHIFT		16
++
++#define ISPCCDC_HORZ_INFO_NPH_SHIFT		0
++#define ISPCCDC_HORZ_INFO_NPH_MASK		0xFFFF8000
++#define ISPCCDC_HORZ_INFO_SPH_MASK		0x1000FFFF
++#define ISPCCDC_HORZ_INFO_SPH_SHIFT		16
++
++#define ISPCCDC_VERT_START_SLV0_SHIFT		16
++#define ISPCCDC_VERT_START_SLV0_MASK		0x1000FFFF
++#define ISPCCDC_VERT_START_SLV1_SHIFT		0
++
++#define ISPCCDC_VERT_LINES_NLV_MASK		0xFFFF8000
++#define ISPCCDC_VERT_LINES_NLV_SHIFT		0
++
++#define ISPCCDC_CULLING_CULV_SHIFT		0
++#define ISPCCDC_CULLING_CULHODD_SHIFT		16
++#define ISPCCDC_CULLING_CULHEVN_SHIFT		24
++
++#define ISPCCDC_HSIZE_OFF_SHIFT			0
++
++#define ISPCCDC_SDOFST_FINV			(1 << 14)
++#define ISPCCDC_SDOFST_FOFST_1L			0
++#define ISPCCDC_SDOFST_FOFST_4L			(3 << 12)
++#define ISPCCDC_SDOFST_LOFST3_SHIFT		0
++#define ISPCCDC_SDOFST_LOFST2_SHIFT		3
++#define ISPCCDC_SDOFST_LOFST1_SHIFT		6
++#define ISPCCDC_SDOFST_LOFST0_SHIFT		9
++#define EVENEVEN				1
++#define ODDEVEN					2
++#define EVENODD					3
++#define ODDODD					4
++
++#define ISPCCDC_CLAMP_OBGAIN_SHIFT		0
++#define ISPCCDC_CLAMP_OBST_SHIFT		10
++#define ISPCCDC_CLAMP_OBSLN_SHIFT		25
++#define ISPCCDC_CLAMP_OBSLEN_SHIFT		28
++#define ISPCCDC_CLAMP_CLAMPEN			(1 << 31)
++
++#define ISPCCDC_COLPTN_R_Ye			0x0
++#define ISPCCDC_COLPTN_Gr_Cy			0x1
++#define ISPCCDC_COLPTN_Gb_G			0x2
++#define ISPCCDC_COLPTN_B_Mg			0x3
++#define ISPCCDC_COLPTN_CP0PLC0_SHIFT		0
++#define ISPCCDC_COLPTN_CP0PLC1_SHIFT		2
++#define ISPCCDC_COLPTN_CP0PLC2_SHIFT		4
++#define ISPCCDC_COLPTN_CP0PLC3_SHIFT		6
++#define ISPCCDC_COLPTN_CP1PLC0_SHIFT		8
++#define ISPCCDC_COLPTN_CP1PLC1_SHIFT		10
++#define ISPCCDC_COLPTN_CP1PLC2_SHIFT		12
++#define ISPCCDC_COLPTN_CP1PLC3_SHIFT		14
++#define ISPCCDC_COLPTN_CP2PLC0_SHIFT		16
++#define ISPCCDC_COLPTN_CP2PLC1_SHIFT		18
++#define ISPCCDC_COLPTN_CP2PLC2_SHIFT		20
++#define ISPCCDC_COLPTN_CP2PLC3_SHIFT		22
++#define ISPCCDC_COLPTN_CP3PLC0_SHIFT		24
++#define ISPCCDC_COLPTN_CP3PLC1_SHIFT		26
++#define ISPCCDC_COLPTN_CP3PLC2_SHIFT		28
++#define ISPCCDC_COLPTN_CP3PLC3_SHIFT		30
++
++#define ISPCCDC_BLKCMP_B_MG_SHIFT		0
++#define ISPCCDC_BLKCMP_GB_G_SHIFT		8
++#define ISPCCDC_BLKCMP_GR_CY_SHIFT		16
++#define ISPCCDC_BLKCMP_R_YE_SHIFT		24
++
++#define ISPCCDC_FPC_FPNUM_SHIFT			0
++#define ISPCCDC_FPC_FPCEN			(1 << 15)
++#define ISPCCDC_FPC_FPERR			(1 << 16)
++
++#define ISPCCDC_VDINT_1_SHIFT			0
++#define ISPCCDC_VDINT_0_SHIFT			16
++#define ISPCCDC_VDINT_0_MASK			0x7FFF
++#define ISPCCDC_VDINT_1_MASK			0x7FFF
++
++#define ISPCCDC_ALAW_GWDI_SHIFT			0
++#define ISPCCDC_ALAW_CCDTBL			(1 << 3)
++
++#define ISPCCDC_REC656IF_R656ON			1
++#define ISPCCDC_REC656IF_ECCFVH			(1 << 1)
++
++#define ISPCCDC_CFG_BW656			(1 << 5)
++#define ISPCCDC_CFG_FIDMD_SHIFT			6
++#define ISPCCDC_CFG_WENLOG			(1 << 8)
++#define ISPCCDC_CFG_WENLOG_AND			(0 << 8)
++#define ISPCCDC_CFG_WENLOG_OR		(1 << 8)
++#define ISPCCDC_CFG_Y8POS			(1 << 11)
++#define ISPCCDC_CFG_BSWD			(1 << 12)
++#define ISPCCDC_CFG_MSBINVI			(1 << 13)
++#define ISPCCDC_CFG_VDLC			(1 << 15)
++
++#define ISPCCDC_FMTCFG_FMTEN			0x1
++#define ISPCCDC_FMTCFG_LNALT			(1 << 1)
++#define ISPCCDC_FMTCFG_LNUM_SHIFT		2
++#define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT		4
++#define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT		8
++#define ISPCCDC_FMTCFG_VPIN_MASK		0xFFFF8000
++#define ISPCCDC_FMTCFG_VPIN_12_3		(0x3 << 12)
++#define ISPCCDC_FMTCFG_VPIN_11_2		(0x4 << 12)
++#define ISPCCDC_FMTCFG_VPIN_10_1		(0x5 << 12)
++#define ISPCCDC_FMTCFG_VPIN_9_0			(0x6 << 12)
++#define ISPCCDC_FMTCFG_VPEN			(1 << 15)
++
++#define ISPCCDC_FMTCF_VPIF_FRQ_MASK		0xFFF8FFFF
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY2		(0x0 << 16)
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY3		(0x1 << 16)
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY4		(0x2 << 16)
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY5		(0x3 << 16)
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY6		(0x4 << 16)
++
++#define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT		0
++#define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT		16
++
++#define ISPCCDC_FMT_VERT_FMTLNV_SHIFT		0
++#define ISPCCDC_FMT_VERT_FMTSLV_SHIFT		16
++
++#define ISPCCDC_FMT_HORZ_FMTSPH_MASK		0x1FFF0000
++#define ISPCCDC_FMT_HORZ_FMTLNH_MASK		0x1FFF
++
++#define ISPCCDC_FMT_VERT_FMTSLV_MASK		0x1FFF0000
++#define ISPCCDC_FMT_VERT_FMTLNV_MASK		0x1FFF
++
++#define ISPCCDC_VP_OUT_HORZ_ST_SHIFT		0
++#define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT		4
++#define ISPCCDC_VP_OUT_VERT_NUM_SHIFT		17
++
++#define ISPRSZ_PID_PREV_SHIFT			0
++#define ISPRSZ_PID_CID_SHIFT			8
++#define ISPRSZ_PID_TID_SHIFT			16
++
++#define ISPRSZ_PCR_ENABLE			0x5
++#define ISPRSZ_PCR_BUSY				(1 << 1)
++
++#define ISPRSZ_CNT_HRSZ_SHIFT			0
++#define ISPRSZ_CNT_HRSZ_MASK			0x3FF
++#define ISPRSZ_CNT_VRSZ_SHIFT			10
++#define ISPRSZ_CNT_VRSZ_MASK			0xFFC00
++#define ISPRSZ_CNT_HSTPH_SHIFT			20
++#define ISPRSZ_CNT_HSTPH_MASK			0x700000
++#define ISPRSZ_CNT_VSTPH_SHIFT			23
++#define	ISPRSZ_CNT_VSTPH_MASK			0x3800000
++#define	ISPRSZ_CNT_CBILIN_MASK			0x20000000
++#define	ISPRSZ_CNT_INPTYP_MASK			0x08000000
++#define	ISPRSZ_CNT_PIXFMT_MASK			0x04000000
++#define ISPRSZ_CNT_YCPOS			(1 << 26)
++#define ISPRSZ_CNT_INPTYP			(1 << 27)
++#define ISPRSZ_CNT_INPSRC			(1 << 28)
++#define ISPRSZ_CNT_CBILIN			(1 << 29)
++
++#define ISPRSZ_OUT_SIZE_HORZ_SHIFT		0
++#define ISPRSZ_OUT_SIZE_HORZ_MASK		0x7FF
++#define ISPRSZ_OUT_SIZE_VERT_SHIFT		16
++#define ISPRSZ_OUT_SIZE_VERT_MASK		0x7FF0000
++
++
++#define ISPRSZ_IN_START_HORZ_ST_SHIFT		0
++#define ISPRSZ_IN_START_HORZ_ST_MASK		0x1FFF
++#define ISPRSZ_IN_START_VERT_ST_SHIFT		16
++#define ISPRSZ_IN_START_VERT_ST_MASK		0x1FFF0000
++
++
++#define ISPRSZ_IN_SIZE_HORZ_SHIFT		0
++#define ISPRSZ_IN_SIZE_HORZ_MASK		0x1FFF
++#define ISPRSZ_IN_SIZE_VERT_SHIFT		16
++#define ISPRSZ_IN_SIZE_VERT_MASK		0x1FFF0000
++
++#define ISPRSZ_SDR_INADD_ADDR_SHIFT		0
++#define ISPRSZ_SDR_INADD_ADDR_MASK		0xFFFFFFFF
++
++#define ISPRSZ_SDR_INOFF_OFFSET_SHIFT		0
++#define ISPRSZ_SDR_INOFF_OFFSET_MASK		0xFFFF
++
++#define ISPRSZ_SDR_OUTADD_ADDR_SHIFT		0
++#define ISPRSZ_SDR_OUTADD_ADDR_MASK		0xFFFFFFFF
++
++
++#define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT		0
++#define ISPRSZ_SDR_OUTOFF_OFFSET_MASK		0xFFFF
++
++#define ISPRSZ_HFILT10_COEF0_SHIFT		0
++#define ISPRSZ_HFILT10_COEF0_MASK		0x3FF
++#define ISPRSZ_HFILT10_COEF1_SHIFT		16
++#define ISPRSZ_HFILT10_COEF1_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT32_COEF2_SHIFT		0
++#define ISPRSZ_HFILT32_COEF2_MASK		0x3FF
++#define ISPRSZ_HFILT32_COEF3_SHIFT		16
++#define ISPRSZ_HFILT32_COEF3_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT54_COEF4_SHIFT		0
++#define ISPRSZ_HFILT54_COEF4_MASK		0x3FF
++#define ISPRSZ_HFILT54_COEF5_SHIFT		16
++#define ISPRSZ_HFILT54_COEF5_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT76_COEFF6_SHIFT		0
++#define ISPRSZ_HFILT76_COEFF6_MASK		0x3FF
++#define ISPRSZ_HFILT76_COEFF7_SHIFT		16
++#define ISPRSZ_HFILT76_COEFF7_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT98_COEFF8_SHIFT		0
++#define ISPRSZ_HFILT98_COEFF8_MASK		0x3FF
++#define ISPRSZ_HFILT98_COEFF9_SHIFT		16
++#define ISPRSZ_HFILT98_COEFF9_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1110_COEF10_SHIFT		0
++#define ISPRSZ_HFILT1110_COEF10_MASK		0x3FF
++#define ISPRSZ_HFILT1110_COEF11_SHIFT		16
++#define ISPRSZ_HFILT1110_COEF11_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1312_COEFF12_SHIFT		0
++#define ISPRSZ_HFILT1312_COEFF12_MASK		0x3FF
++#define ISPRSZ_HFILT1312_COEFF13_SHIFT		16
++#define ISPRSZ_HFILT1312_COEFF13_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1514_COEFF14_SHIFT		0
++#define ISPRSZ_HFILT1514_COEFF14_MASK		0x3FF
++#define ISPRSZ_HFILT1514_COEFF15_SHIFT		16
++#define ISPRSZ_HFILT1514_COEFF15_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1716_COEF16_SHIFT		0
++#define ISPRSZ_HFILT1716_COEF16_MASK		0x3FF
++#define ISPRSZ_HFILT1716_COEF17_SHIFT		16
++#define ISPRSZ_HFILT1716_COEF17_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1918_COEF18_SHIFT		0
++#define ISPRSZ_HFILT1918_COEF18_MASK		0x3FF
++#define ISPRSZ_HFILT1918_COEF19_SHIFT		16
++#define ISPRSZ_HFILT1918_COEF19_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2120_COEF20_SHIFT		0
++#define ISPRSZ_HFILT2120_COEF20_MASK		0x3FF
++#define ISPRSZ_HFILT2120_COEF21_SHIFT		16
++#define ISPRSZ_HFILT2120_COEF21_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2322_COEF22_SHIFT		0
++#define ISPRSZ_HFILT2322_COEF22_MASK		0x3FF
++#define ISPRSZ_HFILT2322_COEF23_SHIFT		16
++#define ISPRSZ_HFILT2322_COEF23_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2524_COEF24_SHIFT		0
++#define ISPRSZ_HFILT2524_COEF24_MASK		0x3FF
++#define ISPRSZ_HFILT2524_COEF25_SHIFT		16
++#define ISPRSZ_HFILT2524_COEF25_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2726_COEF26_SHIFT		0
++#define ISPRSZ_HFILT2726_COEF26_MASK		0x3FF
++#define ISPRSZ_HFILT2726_COEF27_SHIFT		16
++#define ISPRSZ_HFILT2726_COEF27_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2928_COEF28_SHIFT		0
++#define ISPRSZ_HFILT2928_COEF28_MASK		0x3FF
++#define ISPRSZ_HFILT2928_COEF29_SHIFT		16
++#define ISPRSZ_HFILT2928_COEF29_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT3130_COEF30_SHIFT		0
++#define ISPRSZ_HFILT3130_COEF30_MASK		0x3FF
++#define ISPRSZ_HFILT3130_COEF31_SHIFT		16
++#define ISPRSZ_HFILT3130_COEF31_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT10_COEF0_SHIFT		0
++#define ISPRSZ_VFILT10_COEF0_MASK		0x3FF
++#define ISPRSZ_VFILT10_COEF1_SHIFT		16
++#define ISPRSZ_VFILT10_COEF1_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT32_COEF2_SHIFT		0
++#define ISPRSZ_VFILT32_COEF2_MASK		0x3FF
++#define ISPRSZ_VFILT32_COEF3_SHIFT		16
++#define ISPRSZ_VFILT32_COEF3_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT54_COEF4_SHIFT		0
++#define ISPRSZ_VFILT54_COEF4_MASK		0x3FF
++#define ISPRSZ_VFILT54_COEF5_SHIFT		16
++#define ISPRSZ_VFILT54_COEF5_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT76_COEFF6_SHIFT		0
++#define ISPRSZ_VFILT76_COEFF6_MASK		0x3FF
++#define ISPRSZ_VFILT76_COEFF7_SHIFT		16
++#define ISPRSZ_VFILT76_COEFF7_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT98_COEFF8_SHIFT		0
++#define ISPRSZ_VFILT98_COEFF8_MASK		0x3FF
++#define ISPRSZ_VFILT98_COEFF9_SHIFT		16
++#define ISPRSZ_VFILT98_COEFF9_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1110_COEF10_SHIFT		0
++#define ISPRSZ_VFILT1110_COEF10_MASK		0x3FF
++#define ISPRSZ_VFILT1110_COEF11_SHIFT		16
++#define ISPRSZ_VFILT1110_COEF11_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1312_COEFF12_SHIFT		0
++#define ISPRSZ_VFILT1312_COEFF12_MASK		0x3FF
++#define ISPRSZ_VFILT1312_COEFF13_SHIFT		16
++#define ISPRSZ_VFILT1312_COEFF13_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1514_COEFF14_SHIFT		0
++#define ISPRSZ_VFILT1514_COEFF14_MASK		0x3FF
++#define ISPRSZ_VFILT1514_COEFF15_SHIFT		16
++#define ISPRSZ_VFILT1514_COEFF15_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1716_COEF16_SHIFT		0
++#define ISPRSZ_VFILT1716_COEF16_MASK		0x3FF
++#define ISPRSZ_VFILT1716_COEF17_SHIFT		16
++#define ISPRSZ_VFILT1716_COEF17_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1918_COEF18_SHIFT		0
++#define ISPRSZ_VFILT1918_COEF18_MASK		0x3FF
++#define ISPRSZ_VFILT1918_COEF19_SHIFT		16
++#define ISPRSZ_VFILT1918_COEF19_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2120_COEF20_SHIFT		0
++#define ISPRSZ_VFILT2120_COEF20_MASK		0x3FF
++#define ISPRSZ_VFILT2120_COEF21_SHIFT		16
++#define ISPRSZ_VFILT2120_COEF21_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2322_COEF22_SHIFT		0
++#define ISPRSZ_VFILT2322_COEF22_MASK		0x3FF
++#define ISPRSZ_VFILT2322_COEF23_SHIFT		16
++#define ISPRSZ_VFILT2322_COEF23_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2524_COEF24_SHIFT		0
++#define ISPRSZ_VFILT2524_COEF24_MASK		0x3FF
++#define ISPRSZ_VFILT2524_COEF25_SHIFT		16
++#define ISPRSZ_VFILT2524_COEF25_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2726_COEF26_SHIFT		0
++#define ISPRSZ_VFILT2726_COEF26_MASK		0x3FF
++#define ISPRSZ_VFILT2726_COEF27_SHIFT		16
++#define ISPRSZ_VFILT2726_COEF27_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2928_COEF28_SHIFT		0
++#define ISPRSZ_VFILT2928_COEF28_MASK		0x3FF
++#define ISPRSZ_VFILT2928_COEF29_SHIFT		16
++#define ISPRSZ_VFILT2928_COEF29_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT3130_COEF30_SHIFT		0
++#define ISPRSZ_VFILT3130_COEF30_MASK		0x3FF
++#define ISPRSZ_VFILT3130_COEF31_SHIFT		16
++#define ISPRSZ_VFILT3130_COEF31_MASK		0x3FF0000
++
++#define ISPRSZ_YENH_CORE_SHIFT			0
++#define ISPRSZ_YENH_CORE_MASK			0xFF
++#define ISPRSZ_YENH_SLOP_SHIFT			8
++#define ISPRSZ_YENH_SLOP_MASK			0xF00
++#define ISPRSZ_YENH_GAIN_SHIFT			12
++#define ISPRSZ_YENH_GAIN_MASK			0xF000
++#define ISPRSZ_YENH_ALGO_SHIFT			16
++#define ISPRSZ_YENH_ALGO_MASK			0x30000
++
++#define ISPH3A_PCR_AEW_ALAW_EN_SHIFT		1
++#define ISPH3A_PCR_AF_MED_TH_SHIFT		3
++#define ISPH3A_PCR_AF_RGBPOS_SHIFT		11
++#define ISPH3A_PCR_AEW_AVE2LMT_SHIFT		22
++#define ISPH3A_PCR_AEW_AVE2LMT_MASK		0xFFC00000
++#define ISPH3A_PCR_BUSYAF			(1 << 15)
++#define ISPH3A_PCR_BUSYAEAWB			(1 << 18)
++
++#define ISPH3A_AEWWIN1_WINHC_SHIFT		0
++#define ISPH3A_AEWWIN1_WINHC_MASK		0x3F
++#define ISPH3A_AEWWIN1_WINVC_SHIFT		6
++#define ISPH3A_AEWWIN1_WINVC_MASK		0x1FC0
++#define ISPH3A_AEWWIN1_WINW_SHIFT		13
++#define ISPH3A_AEWWIN1_WINW_MASK		0xFE000
++#define ISPH3A_AEWWIN1_WINH_SHIFT		24
++#define ISPH3A_AEWWIN1_WINH_MASK		0x7F000000
++
++#define ISPH3A_AEWINSTART_WINSH_SHIFT		0
++#define ISPH3A_AEWINSTART_WINSH_MASK		0x0FFF
++#define ISPH3A_AEWINSTART_WINSV_SHIFT		16
++#define ISPH3A_AEWINSTART_WINSV_MASK		0x0FFF0000
++
++#define ISPH3A_AEWINBLK_WINH_SHIFT		0
++#define ISPH3A_AEWINBLK_WINH_MASK		0x7F
++#define ISPH3A_AEWINBLK_WINSV_SHIFT		16
++#define ISPH3A_AEWINBLK_WINSV_MASK		0x0FFF0000
++
++#define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT		0
++#define ISPH3A_AEWSUBWIN_AEWINCH_MASK		0x0F
++#define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT		8
++#define ISPH3A_AEWSUBWIN_AEWINCV_MASK		0x0F00
++
++#define ISPHIST_PCR_ENABLE_SHIFT	0
++#define ISPHIST_PCR_ENABLE_MASK		0x01
++#define ISPHIST_PCR_BUSY		0x02
++
++#define ISPHIST_CNT_DATASIZE_SHIFT	8
++#define ISPHIST_CNT_DATASIZE_MASK	0x0100
++#define ISPHIST_CNT_CLEAR_SHIFT		7
++#define ISPHIST_CNT_CLEAR_MASK		0x080
++#define ISPHIST_CNT_CFA_SHIFT		6
++#define ISPHIST_CNT_CFA_MASK		0x040
++#define ISPHIST_CNT_BINS_SHIFT		4
++#define ISPHIST_CNT_BINS_MASK		0x030
++#define ISPHIST_CNT_SOURCE_SHIFT	3
++#define ISPHIST_CNT_SOURCE_MASK		0x08
++#define ISPHIST_CNT_SHIFT_SHIFT		0
++#define ISPHIST_CNT_SHIFT_MASK		0x07
++
++#define ISPHIST_WB_GAIN_WG00_SHIFT	24
++#define ISPHIST_WB_GAIN_WG00_MASK	0xFF000000
++#define ISPHIST_WB_GAIN_WG01_SHIFT	16
++#define ISPHIST_WB_GAIN_WG01_MASK	0xFF0000
++#define ISPHIST_WB_GAIN_WG02_SHIFT	8
++#define ISPHIST_WB_GAIN_WG02_MASK	0xFF00
++#define ISPHIST_WB_GAIN_WG03_SHIFT	0
++#define ISPHIST_WB_GAIN_WG03_MASK	0xFF
++
++#define ISPHIST_REGHORIZ_HSTART_SHIFT		16	/*
++							 * REGION 0 to 3 HORZ
++							 * and VERT
++							 */
++#define ISPHIST_REGHORIZ_HSTART_MASK		0x3FFF0000
++#define ISPHIST_REGHORIZ_HEND_SHIFT		0
++#define ISPHIST_REGHORIZ_HEND_MASK		0x3FFF
++#define ISPHIST_REGVERT_VSTART_SHIFT		16
++#define ISPHIST_REGVERT_VSTART_MASK		0x3FFF0000
++#define ISPHIST_REGVERT_VEND_SHIFT		0
++#define ISPHIST_REGVERT_VEND_MASK		0x3FFF
++
++#define ISPHIST_REGHORIZ_MASK			0x3FFF3FFF
++#define ISPHIST_REGVERT_MASK			0x3FFF3FFF
++
++#define ISPHIST_ADDR_SHIFT			0
++#define ISPHIST_ADDR_MASK			0x3FF
++
++#define ISPHIST_DATA_SHIFT			0
++#define ISPHIST_DATA_MASK			0xFFFFF
++
++#define ISPHIST_RADD_SHIFT			0
++#define ISPHIST_RADD_MASK			0xFFFFFFFF
++
++#define ISPHIST_RADD_OFF_SHIFT			0
++#define ISPHIST_RADD_OFF_MASK			0xFFFF
++
++#define ISPHIST_HV_INFO_HSIZE_SHIFT		16
++#define ISPHIST_HV_INFO_HSIZE_MASK		0x3FFF0000
++#define ISPHIST_HV_INFO_VSIZE_SHIFT		0
++#define ISPHIST_HV_INFO_VSIZE_MASK		0x3FFF
++
++#define ISPHIST_HV_INFO_MASK			0x3FFF3FFF
++
++#define ISPCCDC_LSC_GAIN_MODE_N_MASK		0x700
++#define ISPCCDC_LSC_GAIN_MODE_N_SHIFT		8
++#define ISPCCDC_LSC_GAIN_MODE_M_MASK		0x3800
++#define ISPCCDC_LSC_GAIN_MODE_M_SHIFT		12
++#define ISPCCDC_LSC_GAIN_FORMAT_MASK		0xE
++#define ISPCCDC_LSC_GAIN_FORMAT_SHIFT		1
++#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK	(1<<6)
++
++#define ISPCCDC_LSC_INITIAL_X_MASK		0x3F
++#define ISPCCDC_LSC_INITIAL_X_SHIFT		0
++#define ISPCCDC_LSC_INITIAL_Y_MASK		0x3F0000
++#define ISPCCDC_LSC_INITIAL_Y_SHIFT		16
++
++#define ISPMMU_REVISION_REV_MINOR_MASK		0xF
++#define ISPMMU_REVISION_REV_MAJOR_SHIFT		0x4
++
++#define IRQENABLE_MULTIHITFAULT			(1<<4)
++#define IRQENABLE_TWFAULT			(1<<3)
++#define IRQENABLE_EMUMISS			(1<<2)
++#define IRQENABLE_TRANSLNFAULT			(1<<1)
++#define IRQENABLE_TLBMISS			(1)
++
++#define ISPMMU_MMUCNTL_MMU_EN			(1<<1)
++#define ISPMMU_MMUCNTL_TWL_EN			(1<<2)
++#define ISPMMU_MMUCNTL_EMUTLBUPDATE		(1<<3)
++#define ISPMMU_AUTOIDLE				0x1
++#define ISPMMU_SIDLEMODE_FORCEIDLE		0
++#define ISPMMU_SIDLEMODE_NOIDLE			1
++#define ISPMMU_SIDLEMODE_SMARTIDLE		2
++#define ISPMMU_SIDLEMODE_SHIFT			3
++
++#define ISPCSI1_AUTOIDLE			0x1
++#define ISPCSI1_MIDLEMODE_SHIFT			12
++#define ISPCSI1_MIDLEMODE_FORCESTANDBY		0x0
++#define ISPCSI1_MIDLEMODE_NOSTANDBY		0x1
++#define ISPCSI1_MIDLEMODE_SMARTSTANDBY		0x2
++
++/* CSI2 receiver registers (ES2.0) */
++#define ISPCSI2_REVISION			(0x000)
++#define ISPCSI2_SYSCONFIG			(0x010)
++#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT	12
++#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK		\
++	(0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
++#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE		\
++	(0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
++#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO		\
++	(0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
++#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART		\
++	(0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
++#define ISPCSI2_SYSCONFIG_SOFT_RESET_SHIFT	1
++#define ISPCSI2_SYSCONFIG_SOFT_RESET_MASK		\
++	(0x1 << ISPCSI2_SYSCONFIG_SOFT_RESET_SHIFT)
++#define ISPCSI2_SYSCONFIG_SOFT_RESET_NORMAL		\
++	(0x0 << ISPCSI2_SYSCONFIG_SOFT_RESET_SHIFT)
++#define ISPCSI2_SYSCONFIG_SOFT_RESET_RESET		\
++	(0x1 << ISPCSI2_SYSCONFIG_SOFT_RESET_SHIFT)
++#define ISPCSI2_SYSCONFIG_AUTO_IDLE_SHIFT	0
++#define ISPCSI2_SYSCONFIG_AUTO_IDLE_MASK		\
++	(0x1 << ISPCSI2_SYSCONFIG_AUTO_IDLE_SHIFT)
++#define ISPCSI2_SYSCONFIG_AUTO_IDLE_FREE		\
++	(0x0 << ISPCSI2_SYSCONFIG_AUTO_IDLE_SHIFT)
++#define ISPCSI2_SYSCONFIG_AUTO_IDLE_AUTO		\
++	(0x1 << ISPCSI2_SYSCONFIG_AUTO_IDLE_SHIFT)
++#define ISPCSI2_SYSSTATUS			(0x014)
++#define ISPCSI2_SYSSTATUS_RESET_DONE_SHIFT	0
++#define ISPCSI2_SYSSTATUS_RESET_DONE_MASK		\
++	(0x1 << ISPCSI2_SYSSTATUS_RESET_DONE_SHIFT)
++#define ISPCSI2_SYSSTATUS_RESET_DONE_ONGOING		\
++	(0x0 << ISPCSI2_SYSSTATUS_RESET_DONE_SHIFT)
++#define ISPCSI2_SYSSTATUS_RESET_DONE_DONE		\
++	(0x1 << ISPCSI2_SYSSTATUS_RESET_DONE_SHIFT)
++#define ISPCSI2_IRQSTATUS				(0x018)
++#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ			(1 << 14)
++#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ		(1 << 13)
++#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ		(1 << 12)
++#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ		(1 << 11)
++#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ		(1 << 10)
++#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ		(1 << 9)
++#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ			(1 << 8)
++#define ISPCSI2_IRQSTATUS_CONTEXT(n)			(1 << (n))
++
++#define ISPCSI2_IRQENABLE			(0x01C)
++#define ISPCSI2_CTRL				(0x040)
++#define ISPCSI2_CTRL_VP_CLK_EN_SHIFT	15
++#define ISPCSI2_CTRL_VP_CLK_EN_MASK	(0x1 << ISPCSI2_CTRL_VP_CLK_EN_SHIFT)
++#define ISPCSI2_CTRL_VP_CLK_EN_DISABLE	(0x0 << ISPCSI2_CTRL_VP_CLK_EN_SHIFT)
++#define ISPCSI2_CTRL_VP_CLK_EN_ENABLE	(0x1 << ISPCSI2_CTRL_VP_CLK_EN_SHIFT)
++
++#define ISPCSI2_CTRL_VP_ONLY_EN_SHIFT	11
++#define ISPCSI2_CTRL_VP_ONLY_EN_MASK	(0x1 << ISPCSI2_CTRL_VP_ONLY_EN_SHIFT)
++#define ISPCSI2_CTRL_VP_ONLY_EN_DISABLE	(0x0 << ISPCSI2_CTRL_VP_ONLY_EN_SHIFT)
++#define ISPCSI2_CTRL_VP_ONLY_EN_ENABLE	(0x1 << ISPCSI2_CTRL_VP_ONLY_EN_SHIFT)
++
++#define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT		8
++#define ISPCSI2_CTRL_VP_OUT_CTRL_MASK	(0x3 <<				\
++					 ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
++#define ISPCSI2_CTRL_VP_OUT_CTRL_DISABLE	(0x0 <<			\
++						 ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
++#define ISPCSI2_CTRL_VP_OUT_CTRL_DIV2	(0x1 <<				\
++					 ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
++#define ISPCSI2_CTRL_VP_OUT_CTRL_DIV3	(0x2 <<			\
++					 ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
++#define ISPCSI2_CTRL_VP_OUT_CTRL_DIV4	(0x3 <<			\
++					 ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
++
++#define ISPCSI2_CTRL_DBG_EN_SHIFT	7
++#define ISPCSI2_CTRL_DBG_EN_MASK	(0x1 << ISPCSI2_CTRL_DBG_EN_SHIFT)
++#define ISPCSI2_CTRL_DBG_EN_DISABLE	(0x0 << ISPCSI2_CTRL_DBG_EN_SHIFT)
++#define ISPCSI2_CTRL_DBG_EN_ENABLE	(0x1 << ISPCSI2_CTRL_DBG_EN_SHIFT)
++
++#define ISPCSI2_CTRL_BURST_SIZE_SHIFT	5
++#define ISPCSI2_CTRL_BURST_SIZE_MASK	(0x3 <<			\
++					 ISPCSI2_CTRL_BURST_SIZE_SHIFT)
++#define ISPCSI2_CTRL_BURST_SIZE_MYSTERY_VAL	(0x2 <<		\
++						 ISPCSI2_CTRL_BURST_SIZE_SHIFT)
++
++#define ISPCSI2_CTRL_FRAME_SHIFT	3
++#define ISPCSI2_CTRL_FRAME_MASK		(0x1 << ISPCSI2_CTRL_FRAME_SHIFT)
++#define ISPCSI2_CTRL_FRAME_DISABLE_IMM	(0x0 << ISPCSI2_CTRL_FRAME_SHIFT)
++#define ISPCSI2_CTRL_FRAME_DISABLE_FEC	(0x1 << ISPCSI2_CTRL_FRAME_SHIFT)
++
++#define ISPCSI2_CTRL_ECC_EN_SHIFT	2
++#define ISPCSI2_CTRL_ECC_EN_MASK	(0x1 << ISPCSI2_CTRL_ECC_EN_SHIFT)
++#define ISPCSI2_CTRL_ECC_EN_DISABLE	(0x0 << ISPCSI2_CTRL_ECC_EN_SHIFT)
++#define ISPCSI2_CTRL_ECC_EN_ENABLE	(0x1 << ISPCSI2_CTRL_ECC_EN_SHIFT)
++
++#define ISPCSI2_CTRL_SECURE_SHIFT	1
++#define ISPCSI2_CTRL_SECURE_MASK	(0x1 << ISPCSI2_CTRL_SECURE_SHIFT)
++#define ISPCSI2_CTRL_SECURE_DISABLE	(0x0 << ISPCSI2_CTRL_SECURE_SHIFT)
++#define ISPCSI2_CTRL_SECURE_ENABLE	(0x1 << ISPCSI2_CTRL_SECURE_SHIFT)
++
++#define ISPCSI2_CTRL_IF_EN_SHIFT	0
++#define ISPCSI2_CTRL_IF_EN_MASK		(0x1 << ISPCSI2_CTRL_IF_EN_SHIFT)
++#define ISPCSI2_CTRL_IF_EN_DISABLE	(0x0 << ISPCSI2_CTRL_IF_EN_SHIFT)
++#define ISPCSI2_CTRL_IF_EN_ENABLE	(0x1 << ISPCSI2_CTRL_IF_EN_SHIFT)
++
++#define ISPCSI2_DBG_H				(0x044)
++#define ISPCSI2_GNQ				(0x048)
++#define ISPCSI2_COMPLEXIO_CFG1			(0x050)
++#define ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_SHIFT		29
++#define ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_MASK			\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_ONGOING		\
++	(0x0 << ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_DONE			\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT		27
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_MASK		\
++	(0x3 << ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_OFF		\
++	(0x0 << ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_ON		\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_ULPW		\
++	(0x2 << ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT		25
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_MASK			\
++	(0x3 << ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_OFF			\
++	(0x0 << ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_ON			\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_ULPW			\
++	(0x2 << ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_SHIFT		24
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_MASK		\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_DISABLE		\
++	(0x0 << ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_ENABLE		\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_SHIFT)
++
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(n) 	(3 + ((n) * 4))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POL_MASK(n) \
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(n))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POL_PN(n) \
++	(0x0 << ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(n))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POL_NP(n) \
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(n))
++
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n)	((n) * 4)
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_MASK(n) \
++	(0x7 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_NC(n) \
++	(0x0 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_1(n) \
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_2(n) \
++	(0x2 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_3(n) \
++	(0x3 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_4(n) \
++	(0x4 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
++#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_5(n) \
++	(0x5 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
++
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT		3
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_MASK		\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_PN		\
++	(0x0 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_NP		\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT)
++
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT		0
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_MASK		\
++	(0x7 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_1			\
++	(0x1 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_2			\
++	(0x2 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_3			\
++	(0x3 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_4			\
++	(0x4 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
++#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_5			\
++	(0x5 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
++
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS			(0x054)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEALLULPMEXIT	(1 << 26)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEALLULPMENTER	(1 << 25)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM5		(1 << 24)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM4		(1 << 23)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM3		(1 << 22)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM2		(1 << 21)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM1		(1 << 20)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL5	(1 << 19)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL4	(1 << 18)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL3	(1 << 17)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL2	(1 << 16)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL1	(1 << 15)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC5		(1 << 14)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC4		(1 << 13)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC3		(1 << 12)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC2		(1 << 11)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC1		(1 << 10)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS5	(1 << 9)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS4	(1 << 8)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS3	(1 << 7)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS2	(1 << 6)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS1	(1 << 5)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS5		(1 << 4)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS4		(1 << 3)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS3		(1 << 2)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS2		(1 << 1)
++#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS1		1
++
++#define ISPCSI2_SHORT_PACKET		(0x05C)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE			(0x060)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEALLULPMEXIT	(1 << 26)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEALLULPMENTER	(1 << 25)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM5		(1 << 24)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM4		(1 << 23)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM3		(1 << 22)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM2		(1 << 21)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM1		(1 << 20)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL5	(1 << 19)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL4	(1 << 18)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL3	(1 << 17)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL2	(1 << 16)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL1	(1 << 15)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC5		(1 << 14)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC4		(1 << 13)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC3		(1 << 12)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC2		(1 << 11)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC1		(1 << 10)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS5	(1 << 9)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS4	(1 << 8)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS3	(1 << 7)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS2	(1 << 6)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS1	(1 << 5)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS5		(1 << 4)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS4		(1 << 3)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS3		(1 << 2)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS2		(1 << 1)
++#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS1		1
++#define ISPCSI2_DBG_P			(0x068)
++#define ISPCSI2_TIMING			(0x06C)
++
++
++#define ISPCSI2_TIMING_FORCE_RX_MODE_IO_SHIFT(n) \
++	((16 * ((n) - 1)) + 15)
++#define ISPCSI2_TIMING_FORCE_RX_MODE_IO_MASK(n) \
++	(0x1 << ISPCSI2_TIMING_FORCE_RX_MODE_IO_SHIFT(n))
++#define ISPCSI2_TIMING_FORCE_RX_MODE_IO_DISABLE(n) \
++	(0x0 << ISPCSI2_TIMING_FORCE_RX_MODE_IO_SHIFT(n))
++#define ISPCSI2_TIMING_FORCE_RX_MODE_IO_ENABLE(n) \
++	(0x1 << ISPCSI2_TIMING_FORCE_RX_MODE_IO_SHIFT(n))
++#define ISPCSI2_TIMING_STOP_STATE_X16_IO_SHIFT(n)	((16 * ((n) - 1)) + 14)
++#define ISPCSI2_TIMING_STOP_STATE_X16_IO_MASK(n) \
++	(0x1 << ISPCSI2_TIMING_STOP_STATE_X16_IO_SHIFT(n))
++#define ISPCSI2_TIMING_STOP_STATE_X16_IO_DISABLE(n) \
++	(0x0 << ISPCSI2_TIMING_STOP_STATE_X16_IO_SHIFT(n))
++#define ISPCSI2_TIMING_STOP_STATE_X16_IO_ENABLE(n) \
++	(0x1 << ISPCSI2_TIMING_STOP_STATE_X16_IO_SHIFT(n))
++#define ISPCSI2_TIMING_STOP_STATE_X4_IO_SHIFT(n)	((16 * ((n) - 1)) + 13)
++#define ISPCSI2_TIMING_STOP_STATE_X4_IO_MASK(n)	\
++	(0x1 << ISPCSI2_TIMING_STOP_STATE_X4_IO_SHIFT(n))
++#define ISPCSI2_TIMING_STOP_STATE_X4_IO_DISABLE(n) \
++	(0x0 << ISPCSI2_TIMING_STOP_STATE_X4_IO_SHIFT(n))
++#define ISPCSI2_TIMING_STOP_STATE_X4_IO_ENABLE(n) \
++	(0x1 << ISPCSI2_TIMING_STOP_STATE_X4_IO_SHIFT(n))
++#define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n)	(16 * ((n) - 1))
++#define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n) \
++	(0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
++
++#define ISPCSI2_CTX_CTRL1(n)		((0x070) + 0x20 * (n))
++#define ISPCSI2_CTX_CTRL1_COUNT_SHIFT		8
++#define ISPCSI2_CTX_CTRL1_COUNT_MASK		(0xFF <<		\
++						 ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
++#define ISPCSI2_CTX_CTRL1_EOF_EN_SHIFT		7
++#define ISPCSI2_CTX_CTRL1_EOF_EN_MASK \
++	(0x1 << ISPCSI2_CTX_CTRL1_EOF_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_EOF_EN_DISABLE \
++	(0x0 << ISPCSI2_CTX_CTRL1_EOF_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_EOF_EN_ENABLE	\
++	(0x1 << ISPCSI2_CTX_CTRL1_EOF_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_EOL_EN_SHIFT		6
++#define ISPCSI2_CTX_CTRL1_EOL_EN_MASK \
++	(0x1 << ISPCSI2_CTX_CTRL1_EOL_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_EOL_EN_DISABLE \
++	(0x0 << ISPCSI2_CTX_CTRL1_EOL_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_EOL_EN_ENABLE \
++	(0x1 << ISPCSI2_CTX_CTRL1_EOL_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_CS_EN_SHIFT		5
++#define ISPCSI2_CTX_CTRL1_CS_EN_MASK \
++	(0x1 << ISPCSI2_CTX_CTRL1_CS_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_CS_EN_DISABLE \
++	(0x0 << ISPCSI2_CTX_CTRL1_CS_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_CS_EN_ENABLE \
++	(0x1 << ISPCSI2_CTX_CTRL1_CS_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_SHIFT		4
++#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_MASK \
++	(0x1 <<	ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_DISABLE \
++	(0x0 <<	ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_ENABLE \
++	(0x1 << ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_PING_PONG_SHIFT	3
++#define ISPCSI2_CTX_CTRL1_PING_PONG_MASK \
++	(0x1 <<	ISPCSI2_CTX_CTRL1_PING_PONG_SHIFT)
++#define ISPCSI2_CTX_CTRL1_CTX_EN_SHIFT		0
++#define ISPCSI2_CTX_CTRL1_CTX_EN_MASK \
++	(0x1 << ISPCSI2_CTX_CTRL1_CTX_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_CTX_EN_DISABLE \
++	(0x0 <<	ISPCSI2_CTX_CTRL1_CTX_EN_SHIFT)
++#define ISPCSI2_CTX_CTRL1_CTX_EN_ENABLE \
++	(0x1 <<	ISPCSI2_CTX_CTRL1_CTX_EN_SHIFT)
++
++#define ISPCSI2_CTX_CTRL2(n)		((0x074) + 0x20 * (n))
++#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT	11
++#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \
++	(0x3 <<	ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
++#define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT	0
++#define ISPCSI2_CTX_CTRL2_FORMAT_MASK	(0x3FF <<			\
++					 ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
++
++#define ISPCSI2_CTX_DAT_OFST(n)		((0x078) + 0x20 * (n))
++#define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT	5
++#define ISPCSI2_CTX_DAT_OFST_OFST_MASK	(0x7FF <<			\
++					 ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
++
++#define ISPCSI2_CTX_DAT_PING_ADDR(n)	((0x07C) + 0x20 * (n))
++#define ISPCSI2_CTX_DAT_PONG_ADDR(n)	((0x080) + 0x20 * (n))
++#define ISPCSI2_CTX_IRQENABLE(n)	((0x084) + 0x20 * (n))
++#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ		(1 << 8)
++#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ		(1 << 7)
++#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ		(1 << 6)
++#define ISPCSI2_CTX_IRQENABLE_CS_IRQ			(1 << 5)
++#define ISPCSI2_CTX_IRQENABLE_LE_IRQ			(1 << 3)
++#define ISPCSI2_CTX_IRQENABLE_LS_IRQ			(1 << 2)
++#define ISPCSI2_CTX_IRQENABLE_FE_IRQ			(1 << 1)
++#define ISPCSI2_CTX_IRQENABLE_FS_IRQ			1
++#define ISPCSI2_CTX_IRQSTATUS(n)	((0x088) + 0x20 * (n))
++#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ		(1 << 8)
++#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ		(1 << 7)
++#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ		(1 << 6)
++#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ			(1 << 5)
++#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ			(1 << 3)
++#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ			(1 << 2)
++#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ			(1 << 1)
++#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ			1
++
++#define ISPCSI2_CTX_CTRL3(n)		((0x08C) + 0x20 * (n))
++#define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT	5
++#define ISPCSI2_CTX_CTRL3_ALPHA_MASK	(0x3FFF <<			\
++					 ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
++
++#define ISPCSI2PHY_CFG0				(0x000)
++#define ISPCSI2PHY_CFG0_THS_TERM_SHIFT		8
++#define ISPCSI2PHY_CFG0_THS_TERM_MASK			\
++	(0xFF << ISPCSI2PHY_CFG0_THS_TERM_SHIFT)
++#define ISPCSI2PHY_CFG0_THS_TERM_RESETVAL		\
++	(0x04 << ISPCSI2PHY_CFG0_THS_TERM_SHIFT)
++#define ISPCSI2PHY_CFG0_THS_SETTLE_SHIFT		0
++#define ISPCSI2PHY_CFG0_THS_SETTLE_MASK			\
++	(0xFF << ISPCSI2PHY_CFG0_THS_SETTLE_SHIFT)
++#define ISPCSI2PHY_CFG0_THS_SETTLE_RESETVAL		\
++	(0x27 << ISPCSI2PHY_CFG0_THS_SETTLE_SHIFT)
++#define ISPCSI2PHY_CFG1				(0x004)
++#define ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT		18
++#define ISPCSI2PHY_CFG1_TCLK_TERM_MASK			\
++	(0x7F << ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT)
++#define ISPCSI2PHY_CFG1_TCLK_TERM__RESETVAL		\
++	(0x00 << ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT)
++#define ISPCSI2PHY_CFG1_RESERVED1_SHIFT		10
++#define ISPCSI2PHY_CFG1_RESERVED1_MASK			\
++	(0xFF << ISPCSI2PHY_CFG1_RESERVED1_SHIFT)
++#define ISPCSI2PHY_CFG1_RESERVED1__RESETVAL		\
++	(0xB8 << ISPCSI2PHY_CFG1_RESERVED1_SHIFT)
++#define ISPCSI2PHY_CFG1_TCLK_MISS_SHIFT		8
++#define ISPCSI2PHY_CFG1_TCLK_MISS_MASK			\
++	(0x3 << ISPCSI2PHY_CFG1_TCLK_MISS_SHIFT)
++#define ISPCSI2PHY_CFG1_TCLK_MISS__RESETVAL		\
++	(0x1 << ISPCSI2PHY_CFG1_TCLK_MISS_SHIFT)
++#define ISPCSI2PHY_CFG1_TCLK_SETTLE_SHIFT		0
++#define ISPCSI2PHY_CFG1_TCLK_SETTLE_MASK		\
++	(0xFF << ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT)
++#define ISPCSI2PHY_CFG1_TCLK_SETTLE__RESETVAL		\
++	(0x0E << ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT)
++#define ISPCSI2PHY_CFG1__RESETVAL	(ISPCSI2PHY_CFG1_TCLK_TERM__RESETVAL | \
++					 ISPCSI2PHY_CFG1_RESERVED1__RESETVAL | \
++					 ISPCSI2PHY_CFG1_TCLK_MISS__RESETVAL | \
++					 ISPCSI2PHY_CFG1_TCLK_SETTLE__RESETVAL)
++#define ISPCSI2PHY_CFG1__EDITABLE_MASK	(ISPCSI2PHY_CFG1_TCLK_TERM_MASK | \
++					 ISPCSI2PHY_CFG1_RESERVED1_MASK | \
++					 ISPCSI2PHY_CFG1_TCLK_MISS_MASK | \
++					 ISPCSI2PHY_CFG1_TCLK_SETTLE_MASK)
++
++#endif	/* __ISPREG_H__ */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0002-omap3isp-Add-ISP-MMU-wrapper.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0002-omap3isp-Add-ISP-MMU-wrapper.patch
new file mode 100644
index 0000000000..cfca26723a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0002-omap3isp-Add-ISP-MMU-wrapper.patch
@@ -0,0 +1,209 @@
+From 731527a7dc26533a878c7c5f36fc148fdcaa21b8 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:02 +0200
+Subject: [PATCH] omap3isp: Add ISP MMU wrapper
+
+TODO:
+
+- The ISP driver should start using the IOMMU directly without this wrapper.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ drivers/media/video/isp/ispmmu.c |  141 ++++++++++++++++++++++++++++++++++++++
+ drivers/media/video/isp/ispmmu.h |   36 ++++++++++
+ 2 files changed, 177 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/isp/ispmmu.c
+ create mode 100644 drivers/media/video/isp/ispmmu.h
+
+diff --git a/drivers/media/video/isp/ispmmu.c b/drivers/media/video/isp/ispmmu.c
+new file mode 100644
+index 0000000..f872c71
+--- /dev/null
++++ b/drivers/media/video/isp/ispmmu.c
+@@ -0,0 +1,141 @@
++/*
++ * omap iommu wrapper for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008--2009 Nokia.
++ *
++ * Contributors:
++ *	Hiroshi Doyu <hiroshi.doyu@nokia.com>
++ *	Sakari Ailus <sakari.ailus@nokia.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/module.h>
++
++#include "ispmmu.h"
++#include "isp.h"
++
++#include <mach/iommu.h>
++#include <mach/iovmm.h>
++
++#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
++
++static struct iommu *isp_iommu;
++
++dma_addr_t ispmmu_vmalloc(size_t bytes)
++{
++	return (dma_addr_t)iommu_vmalloc(isp_iommu, 0, bytes, IOMMU_FLAG);
++}
++
++void ispmmu_vfree(const dma_addr_t da)
++{
++	iommu_vfree(isp_iommu, (u32)da);
++}
++
++dma_addr_t ispmmu_kmap(u32 pa, int size)
++{
++	void *da;
++
++	da = (void *)iommu_kmap(isp_iommu, 0, pa, size, IOMMU_FLAG);
++	if (IS_ERR(da))
++		return PTR_ERR(da);
++
++	return (dma_addr_t)da;
++}
++
++void ispmmu_kunmap(dma_addr_t da)
++{
++	iommu_kunmap(isp_iommu, (u32)da);
++}
++
++dma_addr_t ispmmu_vmap(const struct scatterlist *sglist,
++		       int sglen)
++{
++	int err;
++	void *da;
++	struct sg_table *sgt;
++	unsigned int i;
++	struct scatterlist *sg, *src = (struct scatterlist *)sglist;
++
++	/*
++	 * convert isp sglist to iommu sgt
++	 * FIXME: should be fixed in the upper layer?
++	 */
++	sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
++	if (!sgt)
++		return -ENOMEM;
++	err = sg_alloc_table(sgt, sglen, GFP_KERNEL);
++	if (err)
++		goto err_sg_alloc;
++
++	for_each_sg(sgt->sgl, sg, sgt->nents, i)
++		sg_set_buf(sg, phys_to_virt(sg_dma_address(src + i)),
++			   sg_dma_len(src + i));
++
++	da = (void *)iommu_vmap(isp_iommu, 0, sgt, IOMMU_FLAG);
++	if (IS_ERR(da))
++		goto err_vmap;
++
++	return (dma_addr_t)da;
++
++err_vmap:
++	sg_free_table(sgt);
++err_sg_alloc:
++	kfree(sgt);
++	return -ENOMEM;
++}
++EXPORT_SYMBOL_GPL(ispmmu_vmap);
++
++void ispmmu_vunmap(dma_addr_t da)
++{
++	struct sg_table *sgt;
++
++	sgt = iommu_vunmap(isp_iommu, (u32)da);
++	if (!sgt)
++		return;
++	sg_free_table(sgt);
++	kfree(sgt);
++}
++EXPORT_SYMBOL_GPL(ispmmu_vunmap);
++
++void ispmmu_save_context(void)
++{
++	if (isp_iommu)
++		iommu_save_ctx(isp_iommu);
++}
++
++void ispmmu_restore_context(void)
++{
++	if (isp_iommu)
++		iommu_restore_ctx(isp_iommu);
++}
++
++int __init ispmmu_init(void)
++{
++	int err = 0;
++
++	isp_get();
++	isp_iommu = iommu_get("isp");
++	if (IS_ERR(isp_iommu)) {
++		err = PTR_ERR(isp_iommu);
++		isp_iommu = NULL;
++	}
++	isp_put();
++
++	return err;
++}
++
++void ispmmu_cleanup(void)
++{
++	isp_get();
++	if (isp_iommu)
++		iommu_put(isp_iommu);
++	isp_put();
++	isp_iommu = NULL;
++}
+diff --git a/drivers/media/video/isp/ispmmu.h b/drivers/media/video/isp/ispmmu.h
+new file mode 100644
+index 0000000..0bc5bcb
+--- /dev/null
++++ b/drivers/media/video/isp/ispmmu.h
+@@ -0,0 +1,36 @@
++/*
++ * omap iommu wrapper for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008--2009 Nokia.
++ *
++ * Contributors:
++ *	Hiroshi Doyu <hiroshi.doyu@nokia.com>
++ *	Sakari Ailus <sakari.ailus@nokia.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_MMU_H
++#define OMAP_ISP_MMU_H
++
++#include <linux/err.h>
++#include <linux/scatterlist.h>
++
++dma_addr_t ispmmu_vmalloc(size_t bytes);
++void ispmmu_vfree(const dma_addr_t da);
++dma_addr_t ispmmu_kmap(u32 pa, int size);
++void ispmmu_kunmap(dma_addr_t da);
++dma_addr_t ispmmu_vmap(const struct scatterlist *sglist, int sglen);
++void ispmmu_vunmap(dma_addr_t da);
++void ispmmu_save_context(void);
++void ispmmu_restore_context(void);
++int ispmmu_init(void);
++void ispmmu_cleanup(void);
++
++#endif /* OMAP_ISP_MMU_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0003-omap3isp-Add-userspace-header.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0003-omap3isp-Add-userspace-header.patch
new file mode 100644
index 0000000000..66c171f544
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0003-omap3isp-Add-userspace-header.patch
@@ -0,0 +1,696 @@
+From 98ca1ef8c6e2561989aeef981131cf5077eab1d1 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:02 +0200
+Subject: [PATCH] omap3isp: Add userspace header
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ arch/arm/plat-omap/include/mach/isp_user.h |  676 ++++++++++++++++++++++++++++
+ 1 files changed, 676 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/plat-omap/include/mach/isp_user.h
+
+diff --git a/arch/arm/plat-omap/include/mach/isp_user.h b/arch/arm/plat-omap/include/mach/isp_user.h
+new file mode 100644
+index 0000000..b819e26
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/isp_user.h
+@@ -0,0 +1,676 @@
++/*
++ * isp_user.h
++ *
++ * Include file for OMAP ISP module in TI's OMAP3.
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Mohit Jalori <mjalori@ti.com>
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_USER_H
++#define OMAP_ISP_USER_H
++
++/* ISP Private IOCTLs */
++#define VIDIOC_PRIVATE_ISP_CCDC_CFG	\
++	_IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct ispccdc_update_config)
++#define VIDIOC_PRIVATE_ISP_PRV_CFG \
++	_IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct ispprv_update_config)
++#define VIDIOC_PRIVATE_ISP_AEWB_CFG \
++	_IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct isph3a_aewb_config)
++#define VIDIOC_PRIVATE_ISP_AEWB_REQ \
++	_IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct isph3a_aewb_data)
++#define VIDIOC_PRIVATE_ISP_HIST_CFG \
++	_IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct isp_hist_config)
++#define VIDIOC_PRIVATE_ISP_HIST_REQ \
++	_IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct isp_hist_data)
++#define VIDIOC_PRIVATE_ISP_AF_CFG \
++	_IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct af_configuration)
++#define VIDIOC_PRIVATE_ISP_AF_REQ \
++	_IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct isp_af_data)
++
++/* AE/AWB related structures and flags*/
++
++/* Flags for update field */
++#define REQUEST_STATISTICS	(1 << 0)
++#define SET_COLOR_GAINS		(1 << 1)
++#define SET_DIGITAL_GAIN	(1 << 2)
++#define SET_EXPOSURE		(1 << 3)
++#define SET_ANALOG_GAIN		(1 << 4)
++
++#define MAX_FRAME_COUNT		0x0FFF
++#define MAX_FUTURE_FRAMES	10
++
++#define MAX_SATURATION_LIM	1023
++#define MIN_WIN_H		2
++#define MAX_WIN_H		256
++#define MIN_WIN_W		6
++#define MAX_WIN_W		256
++#define MAX_WINVC		128
++#define MAX_WINHC		36
++#define MAX_WINSTART		4095
++#define MIN_SUB_INC		2
++#define MAX_SUB_INC		32
++
++/* Range Constants */
++#define AF_IIRSH_MIN			0
++#define AF_IIRSH_MAX			4094
++#define AF_PAXEL_HORIZONTAL_COUNT_MIN	0
++#define AF_PAXEL_HORIZONTAL_COUNT_MAX	35
++#define AF_PAXEL_VERTICAL_COUNT_MIN	0
++#define AF_PAXEL_VERTICAL_COUNT_MAX	127
++#define AF_PAXEL_INCREMENT_MIN		0
++#define AF_PAXEL_INCREMENT_MAX		14
++#define AF_PAXEL_HEIGHT_MIN		0
++#define AF_PAXEL_HEIGHT_MAX		127
++#define AF_PAXEL_WIDTH_MIN		0
++#define AF_PAXEL_WIDTH_MAX		127
++#define AF_PAXEL_HZSTART_MIN		2
++#define AF_PAXEL_HZSTART_MAX		4094
++
++#define AF_PAXEL_VTSTART_MIN		0
++#define AF_PAXEL_VTSTART_MAX		4095
++#define AF_THRESHOLD_MAX		255
++#define AF_COEF_MAX			4095
++#define AF_PAXEL_SIZE			48
++
++/**
++ * struct isph3a_aewb_config - AE AWB configuration reset values.
++ * saturation_limit: Saturation limit.
++ * @win_height: Window Height. Range 2 - 256, even values only.
++ * @win_width: Window Width. Range 6 - 256, even values only.
++ * @ver_win_count: Vertical Window Count. Range 1 - 128.
++ * @hor_win_count: Horizontal Window Count. Range 1 - 36.
++ * @ver_win_start: Vertical Window Start. Range 0 - 4095.
++ * @hor_win_start: Horizontal Window Start. Range 0 - 4095.
++ * @blk_ver_win_start: Black Vertical Windows Start. Range 0 - 4095.
++ * @blk_win_height: Black Window Height. Range 2 - 256, even values only.
++ * @subsample_ver_inc: Subsample Vertical points increment Range 2 - 32, even
++ *                     values only.
++ * @subsample_hor_inc: Subsample Horizontal points increment Range 2 - 32, even
++ *                     values only.
++ * @alaw_enable: AEW ALAW EN flag.
++ * @aewb_enable: AE AWB stats generation EN flag.
++ */
++struct isph3a_aewb_config {
++	__u16 saturation_limit;
++	__u16 win_height;
++	__u16 win_width;
++	__u16 ver_win_count;
++	__u16 hor_win_count;
++	__u16 ver_win_start;
++	__u16 hor_win_start;
++	__u16 blk_ver_win_start;
++	__u16 blk_win_height;
++	__u16 subsample_ver_inc;
++	__u16 subsample_hor_inc;
++	__u8 alaw_enable;
++	__u8 aewb_enable;
++};
++
++/**
++ * struct isph3a_aewb_data - Structure of data sent to or received from user
++ * @h3a_aewb_statistics_buf: Pointer to pass to user.
++ * @shutter: Shutter speed.
++ * @gain: Sensor analog Gain.
++ * @shutter_cap: Shutter speed for capture.
++ * @gain_cap: Sensor Gain for capture.
++ * @dgain: White balance digital gain.
++ * @wb_gain_b: White balance color gain blue.
++ * @wb_gain_r: White balance color gain red.
++ * @wb_gain_gb: White balance color gain green blue.
++ * @wb_gain_gr: White balance color gain green red.
++ * @frame_number: Frame number of requested stats.
++ * @curr_frame: Current frame number being processed.
++ * @update: Bitwise flags to update parameters.
++ * @ts: Timestamp of returned framestats.
++ * @field_count: Sequence number of returned framestats.
++ */
++struct isph3a_aewb_data {
++	void *h3a_aewb_statistics_buf;
++	__u32 shutter;
++	__u16 gain;
++	__u32 shutter_cap;
++	__u16 gain_cap;
++	__u16 dgain;
++	__u16 wb_gain_b;
++	__u16 wb_gain_r;
++	__u16 wb_gain_gb;
++	__u16 wb_gain_gr;
++	__u16 frame_number;
++	__u16 curr_frame;
++	__u8 update;
++	struct timeval ts;
++	__u32 config_counter;
++	unsigned long field_count;
++};
++
++
++/* Histogram related structs */
++/* Flags for number of bins */
++#define BINS_32			0x0
++#define BINS_64			0x1
++#define BINS_128		0x2
++#define BINS_256		0x3
++
++struct isp_hist_config {
++	__u8 hist_source;		/* CCDC or Memory */
++	__u8 input_bit_width;	/* Needed o know the size per pixel */
++	__u8 hist_frames;		/* Num of frames to be processed and
++				 * accumulated
++				 */
++	__u8 hist_h_v_info;	/* frame-input width and height if source is
++				 * memory
++				 */
++	__u16 hist_radd;		/* frame-input address in memory */
++	__u16 hist_radd_off;	/* line-offset for frame-input */
++	__u16 hist_bins;	/* number of bins: 32, 64, 128, or 256 */
++	__u16 wb_gain_R;	/* White Balance Field-to-Pattern Assignments */
++	__u16 wb_gain_RG;	/* White Balance Field-to-Pattern Assignments */
++	__u16 wb_gain_B;	/* White Balance Field-to-Pattern Assignments */
++	__u16 wb_gain_BG;	/* White Balance Field-to-Pattern Assignments */
++	__u8 num_regions;		/* number of regions to be configured */
++	__u16 reg0_hor;		/* Region 0 size and position */
++	__u16 reg0_ver;		/* Region 0 size and position */
++	__u16 reg1_hor;		/* Region 1 size and position */
++	__u16 reg1_ver;		/* Region 1 size and position */
++	__u16 reg2_hor;		/* Region 2 size and position */
++	__u16 reg2_ver;		/* Region 2 size and position */
++	__u16 reg3_hor;		/* Region 3 size and position */
++	__u16 reg3_ver;		/* Region 3 size and position */
++};
++
++struct isp_hist_data {
++	__u32 *hist_statistics_buf;	/* Pointer to pass to user */
++};
++
++/* Auto Focus related structs */
++
++#define AF_NUMBER_OF_COEF		11
++
++/* Flags for update field */
++#define REQUEST_STATISTICS		(1 << 0)
++#define LENS_DESIRED_POSITION	(1 << 1)
++#define LENS_CURRENT_POSITION	(1 << 2)
++
++/**
++ * struct isp_af_xtrastats - Extra statistics related to AF generated stats.
++ * @ts: Timestamp when the frame gets delivered to the user.
++ * @field_count: Field count of the frame delivered to the user.
++ * @lens_position: Lens position when the stats are being generated.
++ */
++struct isp_af_xtrastats {
++	struct timeval ts;
++	unsigned long field_count;
++	__u16 lens_position; /* deprecated */
++};
++
++/**
++ * struct isp_af_data - AF statistics data to transfer between driver and user.
++ * @af_statistics_buf: Pointer to pass to user.
++ * @lens_current_position: Read value of lens absolute position.
++ * @desired_lens_direction: Lens desired location.
++ * @update: Bitwise flags to update parameters.
++ * @frame_number: Data for which frame is desired/given.
++ * @curr_frame: Current frame number being processed by AF module.
++ * @xtrastats: Extra statistics structure.
++ */
++struct isp_af_data {
++	void *af_statistics_buf;
++	__u16 lens_current_position; /* deprecated */
++	__u16 desired_lens_direction; /* deprecated */
++	__u16 update;
++	__u16 frame_number;
++	__u16 curr_frame;
++	__u32 config_counter;
++	struct isp_af_xtrastats xtrastats;
++};
++
++/* enum used for status of specific feature */
++enum af_alaw_enable {
++	H3A_AF_ALAW_DISABLE = 0,
++	H3A_AF_ALAW_ENABLE = 1
++};
++
++enum af_hmf_enable {
++	H3A_AF_HMF_DISABLE = 0,
++	H3A_AF_HMF_ENABLE = 1
++};
++
++enum af_config_flag {
++	H3A_AF_CFG_DISABLE = 0,
++	H3A_AF_CFG_ENABLE = 1
++};
++
++enum af_mode {
++	ACCUMULATOR_SUMMED = 0,
++	ACCUMULATOR_PEAK = 1
++};
++
++/* Red, Green, and blue pixel location in the AF windows */
++enum rgbpos {
++	GR_GB_BAYER = 0,	/* GR and GB as Bayer pattern */
++	RG_GB_BAYER = 1,	/* RG and GB as Bayer pattern */
++	GR_BG_BAYER = 2,	/* GR and BG as Bayer pattern */
++	RG_BG_BAYER = 3,	/* RG and BG as Bayer pattern */
++	GG_RB_CUSTOM = 4,	/* GG and RB as custom pattern */
++	RB_GG_CUSTOM = 5	/* RB and GG as custom pattern */
++};
++
++/* Contains the information regarding the Horizontal Median Filter */
++struct af_hmf {
++	enum af_hmf_enable enable;	/* Status of Horizontal Median Filter */
++	unsigned int threshold;	/* Threshhold Value for Horizontal Median
++				 * Filter
++				 */
++};
++
++/* Contains the information regarding the IIR Filters */
++struct af_iir {
++	unsigned int hz_start_pos;	/* IIR Start Register Value */
++	int coeff_set0[AF_NUMBER_OF_COEF];	/*
++						 * IIR Filter Coefficient for
++						 * Set 0
++						 */
++	int coeff_set1[AF_NUMBER_OF_COEF];	/*
++						 * IIR Filter Coefficient for
++						 * Set 1
++						 */
++};
++
++/* Contains the information regarding the Paxels Structure in AF Engine */
++struct af_paxel {
++	unsigned int width;	/* Width of the Paxel */
++	unsigned int height;	/* Height of the Paxel */
++	unsigned int hz_start;	/* Horizontal Start Position */
++	unsigned int vt_start;	/* Vertical Start Position */
++	unsigned int hz_cnt;	/* Horizontal Count */
++	unsigned int vt_cnt;	/* vertical Count */
++	unsigned int line_incr;	/* Line Increment */
++};
++/* Contains the parameters required for hardware set up of AF Engine */
++struct af_configuration {
++	enum af_alaw_enable alaw_enable;	/*ALWAW status */
++	struct af_hmf hmf_config;	/*HMF configurations */
++	enum rgbpos rgb_pos;		/*RGB Positions */
++	struct af_iir iir_config;	/*IIR filter configurations */
++	struct af_paxel paxel_config;	/*Paxel parameters */
++	enum af_mode mode;		/*Accumulator mode */
++	enum af_config_flag af_config; /*Flag indicates Engine is configured */
++};
++
++/* ISP CCDC structs */
++
++/* Abstraction layer CCDC configurations */
++#define ISP_ABS_CCDC_ALAW		(1 << 0)
++#define ISP_ABS_CCDC_LPF 		(1 << 1)
++#define ISP_ABS_CCDC_BLCLAMP		(1 << 2)
++#define ISP_ABS_CCDC_BCOMP		(1 << 3)
++#define ISP_ABS_CCDC_FPC		(1 << 4)
++#define ISP_ABS_CCDC_CULL		(1 << 5)
++#define ISP_ABS_CCDC_COLPTN		(1 << 6)
++#define ISP_ABS_CCDC_CONFIG_LSC		(1 << 7)
++#define ISP_ABS_TBL_LSC			(1 << 8)
++
++#define RGB_MAX				3
++
++/* Enumeration constants for Alaw input width */
++enum alaw_ipwidth {
++	ALAW_BIT12_3 = 0x3,
++	ALAW_BIT11_2 = 0x4,
++	ALAW_BIT10_1 = 0x5,
++	ALAW_BIT9_0 = 0x6
++};
++
++/* Enumeration constants for Video Port */
++enum vpin {
++	BIT12_3 = 3,
++	BIT11_2 = 4,
++	BIT10_1 = 5,
++	BIT9_0 = 6
++};
++
++enum vpif_freq {
++	PIXCLKBY2,
++	PIXCLKBY3_5,
++	PIXCLKBY4_5,
++	PIXCLKBY5_5,
++	PIXCLKBY6_5
++};
++
++/**
++ * struct ispccdc_lsc_config - Structure for LSC configuration.
++ * @offset: Table Offset of the gain table.
++ * @gain_mode_n: Vertical dimension of a paxel in LSC configuration.
++ * @gain_mode_m: Horizontal dimension of a paxel in LSC configuration.
++ * @gain_format: Gain table format.
++ * @fmtsph: Start pixel horizontal from start of the HS sync pulse.
++ * @fmtlnh: Number of pixels in horizontal direction to use for the data
++ *          reformatter.
++ * @fmtslv: Start line from start of VS sync pulse for the data reformatter.
++ * @fmtlnv: Number of lines in vertical direction for the data reformatter.
++ * @initial_x: X position, in pixels, of the first active pixel in reference
++ *             to the first active paxel. Must be an even number.
++ * @initial_y: Y position, in pixels, of the first active pixel in reference
++ *             to the first active paxel. Must be an even number.
++ * @size: Size of LSC gain table. Filled when loaded from userspace.
++ */
++struct ispccdc_lsc_config {
++	__u16 offset;
++	__u8 gain_mode_n;
++	__u8 gain_mode_m;
++	__u8 gain_format;
++	__u16 fmtsph;
++	__u16 fmtlnh;
++	__u16 fmtslv;
++	__u16 fmtlnv;
++	__u8 initial_x;
++	__u8 initial_y;
++	__u32 size;
++};
++
++/**
++ * struct ispccdc_bclamp - Structure for Optical & Digital black clamp subtract
++ * @obgain: Optical black average gain.
++ * @obstpixel: Start Pixel w.r.t. HS pulse in Optical black sample.
++ * @oblines: Optical Black Sample lines.
++ * @oblen: Optical Black Sample Length.
++ * @dcsubval: Digital Black Clamp subtract value.
++ */
++struct ispccdc_bclamp {
++	__u8 obgain;
++	__u8 obstpixel;
++	__u8 oblines;
++	__u8 oblen;
++	__u16 dcsubval;
++};
++
++/**
++ * ispccdc_fpc - Structure for FPC
++ * @fpnum: Number of faulty pixels to be corrected in the frame.
++ * @fpcaddr: Memory address of the FPC Table
++ */
++struct ispccdc_fpc {
++	__u16 fpnum;
++	__u32 fpcaddr;
++};
++
++/**
++ * ispccdc_blcomp - Structure for Black Level Compensation parameters.
++ * @b_mg: B/Mg pixels. 2's complement. -128 to +127.
++ * @gb_g: Gb/G pixels. 2's complement. -128 to +127.
++ * @gr_cy: Gr/Cy pixels. 2's complement. -128 to +127.
++ * @r_ye: R/Ye pixels. 2's complement. -128 to +127.
++ */
++struct ispccdc_blcomp {
++	__u8 b_mg;
++	__u8 gb_g;
++	__u8 gr_cy;
++	__u8 r_ye;
++};
++
++/**
++ * struct ispccdc_vp - Structure for Video Port parameters
++ * @bitshift_sel: Video port input select. 3 - bits 12-3, 4 - bits 11-2,
++ *                5 - bits 10-1, 6 - bits 9-0.
++ * @freq_sel: Video port data ready frequency. 1 - 1/3.5, 2 - 1/4.5,
++ *            3 - 1/5.5, 4 - 1/6.5.
++ */
++struct ispccdc_vp {
++	enum vpin bitshift_sel;
++	enum vpif_freq freq_sel;
++};
++
++/**
++ * ispccdc_culling - Structure for Culling parameters.
++ * @v_pattern: Vertical culling pattern.
++ * @h_odd: Horizontal Culling pattern for odd lines.
++ * @h_even: Horizontal Culling pattern for even lines.
++ */
++struct ispccdc_culling {
++	__u8 v_pattern;
++	__u16 h_odd;
++	__u16 h_even;
++};
++
++/**
++ * ispccdc_update_config - Structure for CCDC configuration.
++ * @update: Specifies which CCDC registers should be updated.
++ * @flag: Specifies which CCDC functions should be enabled.
++ * @alawip: Enable/Disable A-Law compression.
++ * @bclamp: Black clamp control register.
++ * @blcomp: Black level compensation value for RGrGbB Pixels. 2's complement.
++ * @fpc: Number of faulty pixels corrected in the frame, address of FPC table.
++ * @cull: Cull control register.
++ * @colptn: Color pattern of the sensor.
++ * @lsc: Pointer to LSC gain table.
++ */
++struct ispccdc_update_config {
++	__u16 update;
++	__u16 flag;
++	enum alaw_ipwidth alawip;
++	struct ispccdc_bclamp *bclamp;
++	struct ispccdc_blcomp *blcomp;
++	struct ispccdc_fpc *fpc;
++	struct ispccdc_lsc_config *lsc_cfg;
++	struct ispccdc_culling *cull;
++	__u32 colptn;
++	__u8 *lsc;
++};
++
++/* Preview configuration */
++
++/*Abstraction layer preview configurations*/
++#define ISP_ABS_PREV_LUMAENH		(1 << 0)
++#define ISP_ABS_PREV_INVALAW		(1 << 1)
++#define ISP_ABS_PREV_HRZ_MED		(1 << 2)
++#define ISP_ABS_PREV_CFA		(1 << 3)
++#define ISP_ABS_PREV_CHROMA_SUPP	(1 << 4)
++#define ISP_ABS_PREV_WB			(1 << 5)
++#define ISP_ABS_PREV_BLKADJ		(1 << 6)
++#define ISP_ABS_PREV_RGB2RGB		(1 << 7)
++#define ISP_ABS_PREV_COLOR_CONV		(1 << 8)
++#define ISP_ABS_PREV_YC_LIMIT		(1 << 9)
++#define ISP_ABS_PREV_DEFECT_COR		(1 << 10)
++#define ISP_ABS_PREV_GAMMABYPASS	(1 << 11)
++#define ISP_ABS_TBL_NF 			(1 << 12)
++#define ISP_ABS_TBL_REDGAMMA		(1 << 13)
++#define ISP_ABS_TBL_GREENGAMMA		(1 << 14)
++#define ISP_ABS_TBL_BLUEGAMMA		(1 << 15)
++
++#define ISPPRV_NF_TBL_SIZE		64
++#define ISPPRV_CFA_TBL_SIZE		576
++#define ISPPRV_GAMMA_TBL_SIZE		1024
++#define ISPPRV_YENH_TBL_SIZE		128
++
++/**
++ * struct ispprev_hmed - Structure for Horizontal Median Filter.
++ * @odddist: Distance between consecutive pixels of same color in the odd line.
++ * @evendist: Distance between consecutive pixels of same color in the even
++ *            line.
++ * @thres: Horizontal median filter threshold.
++ */
++struct ispprev_hmed {
++	__u8 odddist;
++	__u8 evendist;
++	__u8 thres;
++};
++
++/*
++ * Enumeration for CFA Formats supported by preview
++ */
++enum cfa_fmt {
++	CFAFMT_BAYER, CFAFMT_SONYVGA, CFAFMT_RGBFOVEON,
++	CFAFMT_DNSPL, CFAFMT_HONEYCOMB, CFAFMT_RRGGBBFOVEON
++};
++
++/**
++ * struct ispprev_cfa - Structure for CFA Inpterpolation.
++ * @cfafmt: CFA Format Enum value supported by preview.
++ * @cfa_gradthrs_vert: CFA Gradient Threshold - Vertical.
++ * @cfa_gradthrs_horz: CFA Gradient Threshold - Horizontal.
++ * @cfa_table: Pointer to the CFA table.
++ */
++struct ispprev_cfa {
++	enum cfa_fmt cfafmt;
++	__u8 cfa_gradthrs_vert;
++	__u8 cfa_gradthrs_horz;
++	__u32 *cfa_table;
++};
++
++/**
++ * struct ispprev_csup - Structure for Chrominance Suppression.
++ * @gain: Gain.
++ * @thres: Threshold.
++ * @hypf_en: Flag to enable/disable the High Pass Filter.
++ */
++struct ispprev_csup {
++	__u8 gain;
++	__u8 thres;
++	__u8 hypf_en;
++};
++
++/**
++ * struct ispprev_wbal - Structure for White Balance.
++ * @dgain: Digital gain (U10Q8).
++ * @coef3: White balance gain - COEF 3 (U8Q5).
++ * @coef2: White balance gain - COEF 2 (U8Q5).
++ * @coef1: White balance gain - COEF 1 (U8Q5).
++ * @coef0: White balance gain - COEF 0 (U8Q5).
++ */
++struct ispprev_wbal {
++	__u16 dgain;
++	__u8 coef3;
++	__u8 coef2;
++	__u8 coef1;
++	__u8 coef0;
++};
++
++/**
++ * struct ispprev_blkadj - Structure for Black Adjustment.
++ * @red: Black level offset adjustment for Red in 2's complement format
++ * @green: Black level offset adjustment for Green in 2's complement format
++ * @blue: Black level offset adjustment for Blue in 2's complement format
++ */
++struct ispprev_blkadj {
++	/*Black level offset adjustment for Red in 2's complement format */
++	__u8 red;
++	/*Black level offset adjustment for Green in 2's complement format */
++	__u8 green;
++	/* Black level offset adjustment for Blue in 2's complement format */
++	__u8 blue;
++};
++
++/**
++ * struct ispprev_rgbtorgb - Structure for RGB to RGB Blending.
++ * @matrix: Blending values(S12Q8 format)
++ *              [RR] [GR] [BR]
++ *              [RG] [GG] [BG]
++ *              [RB] [GB] [BB]
++ * @offset: Blending offset value for R,G,B in 2's complement integer format.
++ */
++struct ispprev_rgbtorgb {
++	__u16 matrix[3][3];
++	__u16 offset[3];
++};
++
++/**
++ * struct ispprev_csc - Structure for Color Space Conversion from RGB-YCbYCr
++ * @matrix: Color space conversion coefficients(S10Q8)
++ *              [CSCRY]  [CSCGY]  [CSCBY]
++ *              [CSCRCB] [CSCGCB] [CSCBCB]
++ *              [CSCRCR] [CSCGCR] [CSCBCR]
++ * @offset: CSC offset values for Y offset, CB offset and CR offset respectively
++ */
++struct ispprev_csc {
++	__u16 matrix[RGB_MAX][RGB_MAX];
++	__s16 offset[RGB_MAX];
++};
++
++/**
++ * struct ispprev_yclimit - Structure for Y, C Value Limit.
++ * @minC: Minimum C value
++ * @maxC: Maximum C value
++ * @minY: Minimum Y value
++ * @maxY: Maximum Y value
++ */
++struct ispprev_yclimit {
++	__u8 minC;
++	__u8 maxC;
++	__u8 minY;
++	__u8 maxY;
++};
++
++/**
++ * struct ispprev_dcor - Structure for Defect correction.
++ * @couplet_mode_en: Flag to enable or disable the couplet dc Correction in NF
++ * @detect_correct: Thresholds for correction bit 0:10 detect 16:25 correct
++ */
++struct ispprev_dcor {
++	__u8 couplet_mode_en;
++	__u32 detect_correct[4];
++};
++
++/**
++ * struct ispprev_nf - Structure for Noise Filter
++ * @spread: Spread value to be used in Noise Filter
++ * @table: Pointer to the Noise Filter table
++ */
++struct ispprev_nf {
++	__u8 spread;
++	__u32 table[ISPPRV_NF_TBL_SIZE];
++};
++
++/**
++ * struct ispprv_update_config - Structure for Preview Configuration (user).
++ * @update: Specifies which ISP Preview registers should be updated.
++ * @flag: Specifies which ISP Preview functions should be enabled.
++ * @yen: Pointer to luma enhancement table.
++ * @shading_shift: 3bit value of shift used in shading compensation.
++ * @prev_hmed: Pointer to structure containing the odd and even distance.
++ *             between the pixels in the image along with the filter threshold.
++ * @prev_cfa: Pointer to structure containing the CFA interpolation table, CFA.
++ *            format in the image, vertical and horizontal gradient threshold.
++ * @csup: Pointer to Structure for Chrominance Suppression coefficients.
++ * @prev_wbal: Pointer to structure for White Balance.
++ * @prev_blkadj: Pointer to structure for Black Adjustment.
++ * @rgb2rgb: Pointer to structure for RGB to RGB Blending.
++ * @prev_csc: Pointer to structure for Color Space Conversion from RGB-YCbYCr.
++ * @yclimit: Pointer to structure for Y, C Value Limit.
++ * @prev_dcor: Pointer to structure for defect correction.
++ * @prev_nf: Pointer to structure for Noise Filter
++ * @red_gamma: Pointer to red gamma correction table.
++ * @green_gamma: Pointer to green gamma correction table.
++ * @blue_gamma: Pointer to blue gamma correction table.
++ */
++struct ispprv_update_config {
++	__u16 update;
++	__u16 flag;
++	void *yen;
++	__u32 shading_shift;
++	struct ispprev_hmed *prev_hmed;
++	struct ispprev_cfa *prev_cfa;
++	struct ispprev_csup *csup;
++	struct ispprev_wbal *prev_wbal;
++	struct ispprev_blkadj *prev_blkadj;
++	struct ispprev_rgbtorgb *rgb2rgb;
++	struct ispprev_csc *prev_csc;
++	struct ispprev_yclimit *yclimit;
++	struct ispprev_dcor *prev_dcor;
++	struct ispprev_nf *prev_nf;
++	__u32 *red_gamma;
++	__u32 *green_gamma;
++	__u32 *blue_gamma;
++};
++
++#endif /* OMAP_ISP_USER_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0004-omap3isp-Add-ISP-frontend-CCDC.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0004-omap3isp-Add-ISP-frontend-CCDC.patch
new file mode 100644
index 0000000000..4a161729fd
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0004-omap3isp-Add-ISP-frontend-CCDC.patch
@@ -0,0 +1,1875 @@
+From 9ea796fe5383a6961125a6a18185a901fe8627d7 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:02 +0200
+Subject: [PATCH] omap3isp: Add ISP frontend (CCDC)
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ drivers/media/video/isp/ispccdc.c | 1638 +++++++++++++++++++++++++++++++++++++
+ drivers/media/video/isp/ispccdc.h |  209 +++++
+ 2 files changed, 1847 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/isp/ispccdc.c
+ create mode 100644 drivers/media/video/isp/ispccdc.h
+
+diff --git a/drivers/media/video/isp/ispccdc.c b/drivers/media/video/isp/ispccdc.c
+new file mode 100644
+index 0000000..2574ea2
+--- /dev/null
++++ b/drivers/media/video/isp/ispccdc.c
+@@ -0,0 +1,1638 @@
++/*
++ * ispccdc.c
++ *
++ * Driver Library for CCDC module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Senthilvadivu Guruswamy <svadivu@ti.com>
++ *	Pallavi Kulkarni <p-kulkarni@ti.com>
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/mutex.h>
++#include <linux/module.h>
++#include <linux/uaccess.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "ispccdc.h"
++#include "ispmmu.h"
++
++#define LSC_TABLE_INIT_SIZE	50052
++
++static u32 *fpc_table_add;
++static unsigned long fpc_table_add_m;
++
++/**
++ * struct isp_ccdc - Structure for the CCDC module to store its own information
++ * @ccdc_inuse: Flag to determine if CCDC has been reserved or not (0 or 1).
++ * @ccdcout_w: CCDC output width.
++ * @ccdcout_h: CCDC output height.
++ * @ccdcin_w: CCDC input width.
++ * @ccdcin_h: CCDC input height.
++ * @ccdcin_woffset: CCDC input horizontal offset.
++ * @ccdcin_hoffset: CCDC input vertical offset.
++ * @crop_w: Crop width.
++ * @crop_h: Crop weight.
++ * @ccdc_inpfmt: CCDC input format.
++ * @ccdc_outfmt: CCDC output format.
++ * @vpout_en: Video port output enable.
++ * @wen: Data write enable.
++ * @exwen: External data write enable.
++ * @refmt_en: Reformatter enable.
++ * @ccdcslave: CCDC slave mode enable.
++ * @syncif_ipmod: Image
++ * @obclamp_en: Data input format.
++ * @mutexlock: Mutex used to get access to the CCDC.
++ */
++static struct isp_ccdc {
++	u8 ccdc_inuse;
++	u32 ccdcout_w;
++	u32 ccdcout_h;
++	u32 ccdcin_w;
++	u32 ccdcin_h;
++	u32 ccdcin_woffset;
++	u32 ccdcin_hoffset;
++	u32 crop_w;
++	u32 crop_h;
++	u8 ccdc_inpfmt;
++	u8 ccdc_outfmt;
++	u8 vpout_en;
++	u8 wen;
++	u8 exwen;
++	u8 refmt_en;
++	u8 ccdcslave;
++	u8 syncif_ipmod;
++	u8 obclamp_en;
++	u8 pm_state;
++	u8 lsc_enable;
++	int lsc_state;
++	struct mutex mutexlock; /* For checking/modifying ccdc_inuse */
++	u32 wenlog;
++} ispccdc_obj;
++
++static struct ispccdc_lsc_config lsc_config;
++static u8 *lsc_gain_table;
++static unsigned long lsc_ispmmu_addr;
++static int lsc_initialized;
++static u8 *lsc_gain_table_tmp;
++
++/* Structure for saving/restoring CCDC module registers*/
++static struct isp_reg ispccdc_reg_list[] = {
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HD_VD_WID, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PIX_LINES, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HORZ_INFO, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_START, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VERT_LINES, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CULLING, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HSIZE_OFF, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_DCSUB, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_COLPTN, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_BLKCMP, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC_ADDR, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VDINT, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_ALAW, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_HORZ, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_VERT, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_ADDR0, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_ADDR1, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_ADDR2, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_ADDR3, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_ADDR4, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_ADDR5, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_ADDR6, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_ADDR7, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PRGEVEN0, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PRGEVEN1, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PRGODD0, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PRGODD1, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VP_OUT, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_INITIAL, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_BASE, 0},
++	{OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_OFFSET, 0},
++	{0, ISP_TOK_TERM, 0}
++};
++
++/**
++ * omap34xx_isp_ccdc_config - Sets CCDC configuration from userspace
++ * @userspace_add: Structure containing CCDC configuration sent from userspace.
++ *
++ * Returns 0 if successful, -EINVAL if the pointer to the configuration
++ * structure is null, or the copy_from_user function fails to copy user space
++ * memory to kernel space memory.
++ **/
++int omap34xx_isp_ccdc_config(void *userspace_add)
++{
++	struct ispccdc_bclamp bclamp_t;
++	struct ispccdc_blcomp blcomp_t;
++	struct ispccdc_fpc fpc_t;
++	struct ispccdc_culling cull_t;
++	struct ispccdc_update_config *ccdc_struct;
++
++	if (userspace_add == NULL)
++		return -EINVAL;
++
++	ccdc_struct = userspace_add;
++
++	if (ISP_ABS_CCDC_ALAW & ccdc_struct->flag) {
++		if (ISP_ABS_CCDC_ALAW & ccdc_struct->update)
++			ispccdc_config_alaw(ccdc_struct->alawip);
++		ispccdc_enable_alaw(1);
++	} else if (ISP_ABS_CCDC_ALAW & ccdc_struct->update)
++		ispccdc_enable_alaw(0);
++
++	if (ISP_ABS_CCDC_LPF & ccdc_struct->flag)
++		ispccdc_enable_lpf(1);
++	else
++		ispccdc_enable_lpf(0);
++
++	if (ISP_ABS_CCDC_BLCLAMP & ccdc_struct->flag) {
++		if (ISP_ABS_CCDC_BLCLAMP & ccdc_struct->update) {
++			if (copy_from_user(&bclamp_t, (struct ispccdc_bclamp *)
++					   ccdc_struct->bclamp,
++					   sizeof(struct ispccdc_bclamp)))
++				goto copy_from_user_err;
++
++			ispccdc_enable_black_clamp(1);
++			ispccdc_config_black_clamp(bclamp_t);
++		} else
++			ispccdc_enable_black_clamp(1);
++	} else {
++		if (ISP_ABS_CCDC_BLCLAMP & ccdc_struct->update) {
++			if (copy_from_user(&bclamp_t, (struct ispccdc_bclamp *)
++					   ccdc_struct->bclamp,
++					   sizeof(struct ispccdc_bclamp)))
++				goto copy_from_user_err;
++
++			ispccdc_enable_black_clamp(0);
++			ispccdc_config_black_clamp(bclamp_t);
++		}
++	}
++
++	if (ISP_ABS_CCDC_BCOMP & ccdc_struct->update) {
++		if (copy_from_user(&blcomp_t, (struct ispccdc_blcomp *)
++				   ccdc_struct->blcomp,
++				   sizeof(blcomp_t)))
++			goto copy_from_user_err;
++
++		ispccdc_config_black_comp(blcomp_t);
++	}
++
++	if (ISP_ABS_CCDC_FPC & ccdc_struct->flag) {
++		if (ISP_ABS_CCDC_FPC & ccdc_struct->update) {
++			if (copy_from_user(&fpc_t, (struct ispccdc_fpc *)
++					   ccdc_struct->fpc,
++					   sizeof(fpc_t)))
++				goto copy_from_user_err;
++			fpc_table_add = kmalloc(64 + fpc_t.fpnum * 4,
++						GFP_KERNEL | GFP_DMA);
++			if (!fpc_table_add) {
++				printk(KERN_ERR "Cannot allocate memory for"
++				       " FPC table");
++				return -ENOMEM;
++			}
++			while (((unsigned long)fpc_table_add & 0xFFFFFFC0)
++			       != (unsigned long)fpc_table_add)
++				fpc_table_add++;
++
++			fpc_table_add_m = ispmmu_kmap(virt_to_phys
++						      (fpc_table_add),
++						      fpc_t.fpnum * 4);
++
++			if (copy_from_user(fpc_table_add, (u32 *)fpc_t.fpcaddr,
++					   fpc_t.fpnum * 4))
++				goto copy_from_user_err;
++
++			fpc_t.fpcaddr = fpc_table_add_m;
++			ispccdc_config_fpc(fpc_t);
++		}
++		ispccdc_enable_fpc(1);
++	} else if (ISP_ABS_CCDC_FPC & ccdc_struct->update)
++		ispccdc_enable_fpc(0);
++
++	if (ISP_ABS_CCDC_CULL & ccdc_struct->update) {
++		if (copy_from_user(&cull_t, (struct ispccdc_culling *)
++				   ccdc_struct->cull,
++				   sizeof(cull_t)))
++			goto copy_from_user_err;
++		ispccdc_config_culling(cull_t);
++	}
++
++	if (is_isplsc_activated()) {
++		if (ISP_ABS_CCDC_CONFIG_LSC & ccdc_struct->flag) {
++			if (ISP_ABS_CCDC_CONFIG_LSC & ccdc_struct->update) {
++				if (copy_from_user(
++					    &lsc_config,
++					    (struct ispccdc_lsc_config *)
++					    ccdc_struct->lsc_cfg,
++					    sizeof(struct ispccdc_lsc_config)))
++					goto copy_from_user_err;
++				ispccdc_config_lsc(&lsc_config);
++			}
++			ispccdc_enable_lsc(1);
++		} else if (ISP_ABS_CCDC_CONFIG_LSC & ccdc_struct->update) {
++			ispccdc_enable_lsc(0);
++		}
++		if (ISP_ABS_TBL_LSC & ccdc_struct->update) {
++			if (copy_from_user(lsc_gain_table,
++					   ccdc_struct->lsc, lsc_config.size))
++				goto copy_from_user_err;
++			ispccdc_load_lsc(lsc_gain_table, lsc_config.size);
++		}
++	}
++
++	if (ISP_ABS_CCDC_COLPTN & ccdc_struct->update)
++		ispccdc_config_imgattr(ccdc_struct->colptn);
++
++	return 0;
++
++copy_from_user_err:
++	printk(KERN_ERR "CCDC Config:Copy From User Error");
++	return -EINVAL ;
++}
++EXPORT_SYMBOL(omap34xx_isp_ccdc_config);
++
++/**
++ * Set the value to be used for CCDC_CFG.WENLOG.
++ *  w - Value of wenlog.
++ */
++void ispccdc_set_wenlog(u32 wenlog)
++{
++	ispccdc_obj.wenlog = wenlog;
++}
++EXPORT_SYMBOL(ispccdc_set_wenlog);
++
++/**
++ * ispccdc_request - Reserves the CCDC module.
++ *
++ * Reserves the CCDC module and assures that is used only once at a time.
++ *
++ * Returns 0 if successful, or -EBUSY if CCDC module is busy.
++ **/
++int ispccdc_request(void)
++{
++	mutex_lock(&ispccdc_obj.mutexlock);
++	if (ispccdc_obj.ccdc_inuse) {
++		mutex_unlock(&ispccdc_obj.mutexlock);
++		DPRINTK_ISPCCDC("ISP_ERR : CCDC Module Busy\n");
++		return -EBUSY;
++	}
++
++	ispccdc_obj.ccdc_inuse = 1;
++	mutex_unlock(&ispccdc_obj.mutexlock);
++	isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, ISPCTRL_CCDC_RAM_EN |
++		   ISPCTRL_CCDC_CLK_EN |
++		   ISPCTRL_SBL_WR1_RAM_EN);
++	isp_reg_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG, ISPCCDC_CFG_VDLC);
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_request);
++
++/**
++ * ispccdc_free - Frees the CCDC module.
++ *
++ * Frees the CCDC module so it can be used by another process.
++ *
++ * Returns 0 if successful, or -EINVAL if module has been already freed.
++ **/
++int ispccdc_free(void)
++{
++	mutex_lock(&ispccdc_obj.mutexlock);
++	if (!ispccdc_obj.ccdc_inuse) {
++		mutex_unlock(&ispccdc_obj.mutexlock);
++		DPRINTK_ISPCCDC("ISP_ERR: CCDC Module already freed\n");
++		return -EINVAL;
++	}
++
++	ispccdc_obj.ccdc_inuse = 0;
++	mutex_unlock(&ispccdc_obj.mutexlock);
++	isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
++		    ~(ISPCTRL_CCDC_CLK_EN |
++		      ISPCTRL_CCDC_RAM_EN |
++		      ISPCTRL_SBL_WR1_RAM_EN));
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_free);
++
++/**
++ * ispccdc_free_lsc - Frees Lens Shading Compensation table
++ *
++ * Always returns 0.
++ **/
++static int ispccdc_free_lsc(void)
++{
++	if (!lsc_ispmmu_addr)
++		return 0;
++
++	ispccdc_enable_lsc(0);
++	lsc_initialized = 0;
++	isp_reg_writel(0, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_TABLE_BASE);
++	ispmmu_kunmap(lsc_ispmmu_addr);
++	kfree(lsc_gain_table);
++	return 0;
++}
++
++/**
++ * ispccdc_allocate_lsc - Allocate space for Lens Shading Compensation table
++ * @table_size: LSC gain table size.
++ *
++ * Returns 0 if successful, -ENOMEM of its no memory available, or -EINVAL if
++ * table_size is zero.
++ **/
++static int ispccdc_allocate_lsc(u32 table_size)
++{
++	if (table_size == 0)
++		return -EINVAL;
++
++	if ((lsc_config.size >= table_size) && lsc_gain_table)
++		return 0;
++
++	ispccdc_free_lsc();
++
++	lsc_gain_table = kmalloc(table_size, GFP_KERNEL | GFP_DMA);
++
++	if (!lsc_gain_table) {
++		printk(KERN_ERR "Cannot allocate memory for gain tables \n");
++		return -ENOMEM;
++	}
++
++	lsc_ispmmu_addr = ispmmu_kmap(virt_to_phys(lsc_gain_table), table_size);
++	if (lsc_ispmmu_addr <= 0) {
++		printk(KERN_ERR "Cannot map memory for gain tables \n");
++		kfree(lsc_gain_table);
++		return -ENOMEM;
++	}
++
++	return 0;
++}
++
++/**
++ * ispccdc_program_lsc - Program Lens Shading Compensation table.
++ * @table_size: LSC gain table size.
++ *
++ * Returns 0 if successful, or -EINVAL if there's no mapped address for the
++ * table yet.
++ **/
++static int ispccdc_program_lsc(void)
++{
++	if (!lsc_ispmmu_addr)
++		return -EINVAL;
++
++	if (lsc_initialized)
++		return 0;
++
++	isp_reg_writel(lsc_ispmmu_addr, OMAP3_ISP_IOMEM_CCDC,
++		       ISPCCDC_LSC_TABLE_BASE);
++	lsc_initialized = 1;
++	return 0;
++}
++
++/**
++ * ispccdc_load_lsc - Load Lens Shading Compensation table.
++ * @table_addr: LSC gain table MMU Mapped address.
++ * @table_size: LSC gain table size.
++ *
++ * Returns 0 if successful, -ENOMEM of its no memory available, or -EINVAL if
++ * table_size is zero.
++ **/
++int ispccdc_load_lsc(u8 *table_addr, u32 table_size)
++{
++	int ret;
++
++	if (!is_isplsc_activated())
++		return 0;
++
++	if (!table_addr)
++		return -EINVAL;
++
++	ret = ispccdc_allocate_lsc(table_size);
++	if (ret)
++		return ret;
++
++	if (table_addr != lsc_gain_table)
++		memcpy(lsc_gain_table, table_addr, table_size);
++	ret = ispccdc_program_lsc();
++	if (ret)
++		return ret;
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_load_lsc);
++
++/**
++ * ispccdc_config_lsc - Configures the lens shading compensation module
++ * @lsc_cfg: LSC configuration structure
++ **/
++void ispccdc_config_lsc(struct ispccdc_lsc_config *lsc_cfg)
++{
++	int reg;
++
++	if (!is_isplsc_activated())
++		return;
++
++	ispccdc_enable_lsc(0);
++	isp_reg_writel(lsc_cfg->offset, OMAP3_ISP_IOMEM_CCDC,
++		       ISPCCDC_LSC_TABLE_OFFSET);
++
++	reg = 0;
++	reg |= lsc_cfg->gain_mode_n << ISPCCDC_LSC_GAIN_MODE_N_SHIFT;
++	reg |= lsc_cfg->gain_mode_m << ISPCCDC_LSC_GAIN_MODE_M_SHIFT;
++	reg |= lsc_cfg->gain_format << ISPCCDC_LSC_GAIN_FORMAT_SHIFT;
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG);
++
++	reg = 0;
++	reg &= ~ISPCCDC_LSC_INITIAL_X_MASK;
++	reg |= lsc_cfg->initial_x << ISPCCDC_LSC_INITIAL_X_SHIFT;
++	reg &= ~ISPCCDC_LSC_INITIAL_Y_MASK;
++	reg |= lsc_cfg->initial_y << ISPCCDC_LSC_INITIAL_Y_SHIFT;
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_INITIAL);
++}
++EXPORT_SYMBOL(ispccdc_config_lsc);
++
++int __ispccdc_enable_lsc(u8 enable)
++{
++	if (!is_isplsc_activated())
++		return -ENODEV;
++
++	if (enable) {
++		if (!ispccdc_busy()) {
++			isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
++				   ISPCTRL_SBL_SHARED_RPORTB
++				   | ISPCTRL_SBL_RD_RAM_EN);
++
++			isp_reg_or(OMAP3_ISP_IOMEM_CCDC,
++				   ISPCCDC_LSC_CONFIG, 0x1);
++
++			ispccdc_obj.lsc_state = 1;
++		} else {
++			/* Postpone enabling LSC */
++			ispccdc_obj.lsc_enable = 1;
++			return -EBUSY;
++		}
++	} else {
++		isp_reg_and(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG, 0xFFFE);
++		ispccdc_obj.lsc_state = ispccdc_obj.lsc_enable = 0;
++	}
++
++	return 0;
++}
++
++/**
++ * ispccdc_enable_lsc - Enables/Disables the Lens Shading Compensation module.
++ * @enable: 0 Disables LSC, 1 Enables LSC.
++ **/
++void ispccdc_enable_lsc(u8 enable)
++{
++	if (__ispccdc_enable_lsc(enable)) {
++		if (enable)
++			ispccdc_obj.lsc_state = 1;
++		else
++			ispccdc_obj.lsc_state = ispccdc_obj.lsc_enable = 0;
++	}
++}
++EXPORT_SYMBOL(ispccdc_enable_lsc);
++
++void ispccdc_lsc_error_handler(void)
++{
++	int lsc_enable = ispccdc_obj.lsc_state;
++
++	ispccdc_enable_lsc(0);
++
++	ispccdc_obj.lsc_enable = lsc_enable;
++}
++
++/**
++ * ispccdc_config_crop - Configures crop parameters for the ISP CCDC.
++ * @left: Left offset of the crop area.
++ * @top: Top offset of the crop area.
++ * @height: Height of the crop area.
++ * @width: Width of the crop area.
++ *
++ * The following restrictions are applied for the crop settings. If incoming
++ * values do not follow these restrictions then we map the settings to the
++ * closest acceptable crop value.
++ * 1) Left offset is always odd. This can be avoided if we enable byte swap
++ *    option for incoming data into CCDC.
++ * 2) Top offset is always even.
++ * 3) Crop height is always even.
++ * 4) Crop width is always a multiple of 16 pixels
++ **/
++void ispccdc_config_crop(u32 left, u32 top, u32 height, u32 width)
++{
++	ispccdc_obj.ccdcin_woffset = left + (left % 2);
++	ispccdc_obj.ccdcin_hoffset = top + (top % 2);
++
++	ispccdc_obj.crop_w = width - (width % 16);
++	ispccdc_obj.crop_h = height + (height % 2);
++
++	DPRINTK_ISPCCDC("\n\tOffsets L %d T %d W %d H %d\n",
++			ispccdc_obj.ccdcin_woffset,
++			ispccdc_obj.ccdcin_hoffset,
++			ispccdc_obj.crop_w,
++			ispccdc_obj.crop_h);
++}
++
++/**
++ * ispccdc_config_datapath - Specifies the input and output modules for CCDC.
++ * @input: Indicates the module that inputs the image to the CCDC.
++ * @output: Indicates the module to which the CCDC outputs the image.
++ *
++ * Configures the default configuration for the CCDC to work with.
++ *
++ * The valid values for the input are CCDC_RAW (0), CCDC_YUV_SYNC (1),
++ * CCDC_YUV_BT (2), and CCDC_OTHERS (3).
++ *
++ * The valid values for the output are CCDC_YUV_RSZ (0), CCDC_YUV_MEM_RSZ (1),
++ * CCDC_OTHERS_VP (2), CCDC_OTHERS_MEM (3), CCDC_OTHERS_VP_MEM (4).
++ *
++ * Returns 0 if successful, or -EINVAL if wrong I/O combination or wrong input
++ * or output values.
++ **/
++int ispccdc_config_datapath(enum ccdc_input input, enum ccdc_output output)
++{
++	u32 syn_mode = 0;
++	struct ispccdc_vp vpcfg;
++	struct ispccdc_syncif syncif;
++	struct ispccdc_bclamp blkcfg;
++
++	u32 colptn = ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC0_SHIFT |
++		ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC1_SHIFT |
++		ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC2_SHIFT |
++		ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC3_SHIFT |
++		ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC0_SHIFT |
++		ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC1_SHIFT |
++		ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC2_SHIFT |
++		ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC3_SHIFT |
++		ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC0_SHIFT |
++		ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC1_SHIFT |
++		ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC2_SHIFT |
++		ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC3_SHIFT |
++		ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC0_SHIFT |
++		ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC1_SHIFT |
++		ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC2_SHIFT |
++		ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
++
++	/* CCDC does not convert the image format */
++	if ((input == CCDC_RAW || input == CCDC_OTHERS) &&
++	    output == CCDC_YUV_RSZ) {
++		DPRINTK_ISPCCDC("ISP_ERR: Wrong CCDC I/O Combination\n");
++		return -EINVAL;
++	}
++
++	syn_mode = isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
++
++	switch (output) {
++	case CCDC_YUV_RSZ:
++		syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
++		syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
++		break;
++
++	case CCDC_YUV_MEM_RSZ:
++		syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
++		ispccdc_obj.wen = 1;
++		syn_mode |= ISPCCDC_SYN_MODE_WEN;
++		break;
++
++	case CCDC_OTHERS_VP:
++		syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
++		syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
++		syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
++		vpcfg.bitshift_sel = BIT9_0;
++		vpcfg.freq_sel = PIXCLKBY2;
++		ispccdc_config_vp(vpcfg);
++		ispccdc_enable_vp(1);
++		break;
++
++	case CCDC_OTHERS_MEM:
++		syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
++		syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
++		syn_mode |= ISPCCDC_SYN_MODE_WEN;
++		syn_mode &= ~ISPCCDC_SYN_MODE_EXWEN;
++		isp_reg_and(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
++			    ~ISPCCDC_CFG_WENLOG);
++		vpcfg.bitshift_sel = BIT11_2;
++		vpcfg.freq_sel = PIXCLKBY2;
++		ispccdc_config_vp(vpcfg);
++		ispccdc_enable_vp(0);
++		break;
++
++	case CCDC_OTHERS_VP_MEM:
++		syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
++		syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
++		syn_mode |= ISPCCDC_SYN_MODE_WEN;
++		syn_mode &= ~ISPCCDC_SYN_MODE_EXWEN;
++
++		isp_reg_and_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG,
++			       ~ISPCCDC_CFG_WENLOG,
++			       ispccdc_obj.wenlog);
++		vpcfg.bitshift_sel = BIT9_0;
++		vpcfg.freq_sel = PIXCLKBY2;
++		ispccdc_config_vp(vpcfg);
++		ispccdc_enable_vp(1);
++		break;
++	default:
++		DPRINTK_ISPCCDC("ISP_ERR: Wrong CCDC Output\n");
++		return -EINVAL;
++	};
++
++	isp_reg_writel(syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
++
++	switch (input) {
++	case CCDC_RAW:
++		syncif.ccdc_mastermode = 0;
++		syncif.datapol = 0;
++		syncif.datsz = DAT10;
++		syncif.fldmode = 0;
++		syncif.fldout = 0;
++		syncif.fldpol = 0;
++		syncif.fldstat = 0;
++		syncif.hdpol = 0;
++		syncif.ipmod = RAW;
++		syncif.vdpol = 0;
++		ispccdc_config_sync_if(syncif);
++		ispccdc_config_imgattr(colptn);
++		blkcfg.dcsubval = 64;
++		ispccdc_config_black_clamp(blkcfg);
++		if (is_isplsc_activated()) {
++			ispccdc_config_lsc(&lsc_config);
++			ispccdc_load_lsc(lsc_gain_table_tmp,
++					 LSC_TABLE_INIT_SIZE);
++		}
++
++		break;
++	case CCDC_YUV_SYNC:
++		syncif.ccdc_mastermode = 0;
++		syncif.datapol = 0;
++		syncif.datsz = DAT8;
++		syncif.fldmode = 0;
++		syncif.fldout = 0;
++		syncif.fldpol = 0;
++		syncif.fldstat = 0;
++		syncif.hdpol = 0;
++		syncif.ipmod = YUV16;
++		syncif.vdpol = 1;
++		ispccdc_config_imgattr(0);
++		ispccdc_config_sync_if(syncif);
++		blkcfg.dcsubval = 0;
++		ispccdc_config_black_clamp(blkcfg);
++		break;
++	case CCDC_YUV_BT:
++		break;
++	case CCDC_OTHERS:
++		break;
++	default:
++		DPRINTK_ISPCCDC("ISP_ERR: Wrong CCDC Input\n");
++		return -EINVAL;
++	}
++
++	ispccdc_obj.ccdc_inpfmt = input;
++	ispccdc_obj.ccdc_outfmt = output;
++	ispccdc_print_status();
++	isp_print_status();
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_datapath);
++
++/**
++ * ispccdc_config_sync_if - Sets the sync i/f params between sensor and CCDC.
++ * @syncif: Structure containing the sync parameters like field state, CCDC in
++ *          master/slave mode, raw/yuv data, polarity of data, field, hs, vs
++ *          signals.
++ **/
++void ispccdc_config_sync_if(struct ispccdc_syncif syncif)
++{
++	u32 syn_mode = isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
++
++	syn_mode |= ISPCCDC_SYN_MODE_VDHDEN;
++
++	if (syncif.fldstat)
++		syn_mode |= ISPCCDC_SYN_MODE_FLDSTAT;
++	else
++		syn_mode &= ~ISPCCDC_SYN_MODE_FLDSTAT;
++
++	syn_mode &= ISPCCDC_SYN_MODE_INPMOD_MASK;
++	ispccdc_obj.syncif_ipmod = syncif.ipmod;
++
++	switch (syncif.ipmod) {
++	case RAW:
++		break;
++	case YUV16:
++		syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR16;
++		break;
++	case YUV8:
++		syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR8;
++		break;
++	};
++
++	syn_mode &= ISPCCDC_SYN_MODE_DATSIZ_MASK;
++	switch (syncif.datsz) {
++	case DAT8:
++		syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_8;
++		break;
++	case DAT10:
++		syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_10;
++		break;
++	case DAT11:
++		syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_11;
++		break;
++	case DAT12:
++		syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_12;
++		break;
++	};
++
++	if (syncif.fldmode)
++		syn_mode |= ISPCCDC_SYN_MODE_FLDMODE;
++	else
++		syn_mode &= ~ISPCCDC_SYN_MODE_FLDMODE;
++
++	if (syncif.datapol)
++		syn_mode |= ISPCCDC_SYN_MODE_DATAPOL;
++	else
++		syn_mode &= ~ISPCCDC_SYN_MODE_DATAPOL;
++
++	if (syncif.fldpol)
++		syn_mode |= ISPCCDC_SYN_MODE_FLDPOL;
++	else
++		syn_mode &= ~ISPCCDC_SYN_MODE_FLDPOL;
++
++	if (syncif.hdpol)
++		syn_mode |= ISPCCDC_SYN_MODE_HDPOL;
++	else
++		syn_mode &= ~ISPCCDC_SYN_MODE_HDPOL;
++
++	if (syncif.vdpol)
++		syn_mode |= ISPCCDC_SYN_MODE_VDPOL;
++	else
++		syn_mode &= ~ISPCCDC_SYN_MODE_VDPOL;
++
++	if (syncif.ccdc_mastermode) {
++		syn_mode |= ISPCCDC_SYN_MODE_FLDOUT | ISPCCDC_SYN_MODE_VDHDOUT;
++		isp_reg_writel(syncif.hs_width << ISPCCDC_HD_VD_WID_HDW_SHIFT
++			       | syncif.vs_width << ISPCCDC_HD_VD_WID_VDW_SHIFT,
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_HD_VD_WID);
++
++		isp_reg_writel(syncif.ppln << ISPCCDC_PIX_LINES_PPLN_SHIFT
++			       | syncif.hlprf << ISPCCDC_PIX_LINES_HLPRF_SHIFT,
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_PIX_LINES);
++	} else
++		syn_mode &= ~(ISPCCDC_SYN_MODE_FLDOUT |
++			      ISPCCDC_SYN_MODE_VDHDOUT);
++
++	isp_reg_writel(syn_mode, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE);
++
++	if (!(syncif.bt_r656_en)) {
++		isp_reg_and(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_REC656IF,
++			    ~ISPCCDC_REC656IF_R656ON);
++	}
++}
++EXPORT_SYMBOL(ispccdc_config_sync_if);
++
++/**
++ * ispccdc_config_black_clamp - Configures the clamp parameters in CCDC.
++ * @bclamp: Structure containing the optical black average gain, optical black
++ *          sample length, sample lines, and the start pixel position of the
++ *          samples w.r.t the HS pulse.
++ * Configures the clamp parameters in CCDC. Either if its being used the
++ * optical black clamp, or the digital clamp. If its a digital clamp, then
++ * assures to put a valid DC substraction level.
++ *
++ * Returns always 0 when completed.
++ **/
++int ispccdc_config_black_clamp(struct ispccdc_bclamp bclamp)
++{
++	u32 bclamp_val = 0;
++
++	if (ispccdc_obj.obclamp_en) {
++		bclamp_val |= bclamp.obgain << ISPCCDC_CLAMP_OBGAIN_SHIFT;
++		bclamp_val |= bclamp.oblen << ISPCCDC_CLAMP_OBSLEN_SHIFT;
++		bclamp_val |= bclamp.oblines << ISPCCDC_CLAMP_OBSLN_SHIFT;
++		bclamp_val |= bclamp.obstpixel << ISPCCDC_CLAMP_OBST_SHIFT;
++		isp_reg_writel(bclamp_val, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_CLAMP);
++	} else {
++		if (omap_rev() < OMAP3430_REV_ES2_0)
++			if (ispccdc_obj.syncif_ipmod == YUV16 ||
++			    ispccdc_obj.syncif_ipmod == YUV8 ||
++			    isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++					  ISPCCDC_REC656IF) &
++			    ISPCCDC_REC656IF_R656ON)
++				bclamp.dcsubval = 0;
++		isp_reg_writel(bclamp.dcsubval, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_DCSUB);
++	}
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_black_clamp);
++
++/**
++ * ispccdc_enable_black_clamp - Enables/Disables the optical black clamp.
++ * @enable: 0 Disables optical black clamp, 1 Enables optical black clamp.
++ *
++ * Enables or disables the optical black clamp. When disabled, the digital
++ * clamp operates.
++ **/
++void ispccdc_enable_black_clamp(u8 enable)
++{
++	isp_reg_and_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP,
++		       ~ISPCCDC_CLAMP_CLAMPEN,
++		       enable ? ISPCCDC_CLAMP_CLAMPEN : 0);
++	ispccdc_obj.obclamp_en = enable;
++}
++EXPORT_SYMBOL(ispccdc_enable_black_clamp);
++
++/**
++ * ispccdc_config_fpc - Configures the Faulty Pixel Correction parameters.
++ * @fpc: Structure containing the number of faulty pixels corrected in the
++ *       frame, address of the FPC table.
++ *
++ * Returns 0 if successful, or -EINVAL if FPC Address is not on the 64 byte
++ * boundary.
++ **/
++int ispccdc_config_fpc(struct ispccdc_fpc fpc)
++{
++	u32 fpc_val = 0;
++
++	fpc_val = isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
++
++	if ((fpc.fpcaddr & 0xFFFFFFC0) == fpc.fpcaddr) {
++		isp_reg_writel(fpc_val & (~ISPCCDC_FPC_FPCEN),
++			       OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
++		isp_reg_writel(fpc.fpcaddr,
++			       OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC_ADDR);
++	} else {
++		DPRINTK_ISPCCDC("FPC Address should be on 64byte boundary\n");
++		return -EINVAL;
++	}
++	isp_reg_writel(fpc_val | (fpc.fpnum << ISPCCDC_FPC_FPNUM_SHIFT),
++		       OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC);
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_fpc);
++
++/**
++ * ispccdc_enable_fpc - Enables the Faulty Pixel Correction.
++ * @enable: 0 Disables FPC, 1 Enables FPC.
++ **/
++void ispccdc_enable_fpc(u8 enable)
++{
++	isp_reg_and_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FPC,
++		       ~ISPCCDC_FPC_FPCEN,
++		       enable ? ISPCCDC_FPC_FPCEN : 0);
++}
++EXPORT_SYMBOL(ispccdc_enable_fpc);
++
++/**
++ * ispccdc_config_black_comp - Configures Black Level Compensation parameters.
++ * @blcomp: Structure containing the black level compensation value for RGrGbB
++ *          pixels. in 2's complement.
++ **/
++void ispccdc_config_black_comp(struct ispccdc_blcomp blcomp)
++{
++	u32 blcomp_val = 0;
++
++	blcomp_val |= blcomp.b_mg << ISPCCDC_BLKCMP_B_MG_SHIFT;
++	blcomp_val |= blcomp.gb_g << ISPCCDC_BLKCMP_GB_G_SHIFT;
++	blcomp_val |= blcomp.gr_cy << ISPCCDC_BLKCMP_GR_CY_SHIFT;
++	blcomp_val |= blcomp.r_ye << ISPCCDC_BLKCMP_R_YE_SHIFT;
++
++	isp_reg_writel(blcomp_val, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_BLKCMP);
++}
++EXPORT_SYMBOL(ispccdc_config_black_comp);
++
++/**
++ * ispccdc_config_vp - Configures the Video Port Configuration parameters.
++ * @vpcfg: Structure containing the Video Port input frequency, and the 10 bit
++ *         format.
++ **/
++void ispccdc_config_vp(struct ispccdc_vp vpcfg)
++{
++	u32 fmtcfg_vp = isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
++
++	fmtcfg_vp &= ISPCCDC_FMTCFG_VPIN_MASK & ISPCCDC_FMTCF_VPIF_FRQ_MASK;
++
++	switch (vpcfg.bitshift_sel) {
++	case BIT9_0:
++		fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_9_0;
++		break;
++	case BIT10_1:
++		fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_10_1;
++		break;
++	case BIT11_2:
++		fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_11_2;
++		break;
++	case BIT12_3:
++		fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_12_3;
++		break;
++	};
++	switch (vpcfg.freq_sel) {
++	case PIXCLKBY2:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY2;
++		break;
++	case PIXCLKBY3_5:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY3;
++		break;
++	case PIXCLKBY4_5:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY4;
++		break;
++	case PIXCLKBY5_5:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY5;
++		break;
++	case PIXCLKBY6_5:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY6;
++		break;
++	};
++	isp_reg_writel(fmtcfg_vp, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
++}
++EXPORT_SYMBOL(ispccdc_config_vp);
++
++/**
++ * ispccdc_enable_vp - Enables the Video Port.
++ * @enable: 0 Disables VP, 1 Enables VP
++ **/
++void ispccdc_enable_vp(u8 enable)
++{
++	isp_reg_and_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG,
++		       ~ISPCCDC_FMTCFG_VPEN,
++		       enable ? ISPCCDC_FMTCFG_VPEN : 0);
++}
++EXPORT_SYMBOL(ispccdc_enable_vp);
++
++/**
++ * ispccdc_config_reformatter - Configures the Reformatter.
++ * @refmt: Structure containing the memory address to format and the bit fields
++ *         for the reformatter registers.
++ *
++ * Configures the Reformatter register values if line alternating is disabled.
++ * Else, just enabling line alternating is enough.
++ **/
++void ispccdc_config_reformatter(struct ispccdc_refmt refmt)
++{
++	u32 fmtcfg_val = 0;
++
++	fmtcfg_val = isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
++
++	if (refmt.lnalt)
++		fmtcfg_val |= ISPCCDC_FMTCFG_LNALT;
++	else {
++		fmtcfg_val &= ~ISPCCDC_FMTCFG_LNALT;
++		fmtcfg_val &= 0xFFFFF003;
++		fmtcfg_val |= refmt.lnum << ISPCCDC_FMTCFG_LNUM_SHIFT;
++		fmtcfg_val |= refmt.plen_even <<
++			ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT;
++		fmtcfg_val |= refmt.plen_odd << ISPCCDC_FMTCFG_PLEN_ODD_SHIFT;
++
++		isp_reg_writel(refmt.prgeven0, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_PRGEVEN0);
++		isp_reg_writel(refmt.prgeven1, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_PRGEVEN1);
++		isp_reg_writel(refmt.prgodd0, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_PRGODD0);
++		isp_reg_writel(refmt.prgodd1, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_PRGODD1);
++		isp_reg_writel(refmt.fmtaddr0, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_ADDR0);
++		isp_reg_writel(refmt.fmtaddr1, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_ADDR1);
++		isp_reg_writel(refmt.fmtaddr2, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_ADDR2);
++		isp_reg_writel(refmt.fmtaddr3, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_ADDR3);
++		isp_reg_writel(refmt.fmtaddr4, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_ADDR4);
++		isp_reg_writel(refmt.fmtaddr5, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_ADDR5);
++		isp_reg_writel(refmt.fmtaddr6, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_ADDR6);
++		isp_reg_writel(refmt.fmtaddr7, OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_ADDR7);
++	}
++	isp_reg_writel(fmtcfg_val, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG);
++}
++EXPORT_SYMBOL(ispccdc_config_reformatter);
++
++/**
++ * ispccdc_enable_reformatter - Enables the Reformatter.
++ * @enable: 0 Disables Reformatter, 1- Enables Data Reformatter
++ **/
++void ispccdc_enable_reformatter(u8 enable)
++{
++	isp_reg_and_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG,
++		       ~ISPCCDC_FMTCFG_FMTEN,
++		       enable ? ISPCCDC_FMTCFG_FMTEN : 0);
++	ispccdc_obj.refmt_en = enable;
++}
++EXPORT_SYMBOL(ispccdc_enable_reformatter);
++
++/**
++ * ispccdc_config_culling - Configures the culling parameters.
++ * @cull: Structure containing the vertical culling pattern, and horizontal
++ *        culling pattern for odd and even lines.
++ **/
++void ispccdc_config_culling(struct ispccdc_culling cull)
++{
++	u32 culling_val = 0;
++
++	culling_val |= cull.v_pattern << ISPCCDC_CULLING_CULV_SHIFT;
++	culling_val |= cull.h_even << ISPCCDC_CULLING_CULHEVN_SHIFT;
++	culling_val |= cull.h_odd << ISPCCDC_CULLING_CULHODD_SHIFT;
++
++	isp_reg_writel(culling_val, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CULLING);
++}
++EXPORT_SYMBOL(ispccdc_config_culling);
++
++/**
++ * ispccdc_enable_lpf - Enables the Low-Pass Filter (LPF).
++ * @enable: 0 Disables LPF, 1 Enables LPF
++ **/
++void ispccdc_enable_lpf(u8 enable)
++{
++	isp_reg_and_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE,
++		       ~ISPCCDC_SYN_MODE_LPF,
++		       enable ? ISPCCDC_SYN_MODE_LPF : 0);
++}
++EXPORT_SYMBOL(ispccdc_enable_lpf);
++
++/**
++ * ispccdc_config_alaw - Configures the input width for A-law.
++ * @ipwidth: Input width for A-law
++ **/
++void ispccdc_config_alaw(enum alaw_ipwidth ipwidth)
++{
++	isp_reg_writel(ipwidth << ISPCCDC_ALAW_GWDI_SHIFT,
++		       OMAP3_ISP_IOMEM_CCDC, ISPCCDC_ALAW);
++}
++EXPORT_SYMBOL(ispccdc_config_alaw);
++
++/**
++ * ispccdc_enable_alaw - Enables the A-law compression.
++ * @enable: 0 - Disables A-law, 1 - Enables A-law
++ **/
++void ispccdc_enable_alaw(u8 enable)
++{
++	isp_reg_and_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_ALAW,
++		       ~ISPCCDC_ALAW_CCDTBL,
++		       enable ? ISPCCDC_ALAW_CCDTBL : 0);
++}
++EXPORT_SYMBOL(ispccdc_enable_alaw);
++
++/**
++ * ispccdc_config_imgattr - Configures the sensor image specific attributes.
++ * @colptn: Color pattern of the sensor.
++ **/
++void ispccdc_config_imgattr(u32 colptn)
++{
++	isp_reg_writel(colptn, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_COLPTN);
++}
++EXPORT_SYMBOL(ispccdc_config_imgattr);
++
++void ispccdc_config_shadow_registers(void)
++{
++	if (ispccdc_obj.lsc_enable) {
++		ispccdc_enable_lsc(1);
++		ispccdc_obj.lsc_enable = 0;
++	}
++}
++
++/**
++ * ispccdc_try_size - Checks if requested Input/output dimensions are valid
++ * @input_w: input width for the CCDC in number of pixels per line
++ * @input_h: input height for the CCDC in number of lines
++ * @output_w: output width from the CCDC in number of pixels per line
++ * @output_h: output height for the CCDC in number of lines
++ *
++ * Calculates the number of pixels cropped if the reformater is disabled,
++ * Fills up the output width and height variables in the isp_ccdc structure.
++ *
++ * Returns 0 if successful, or -EINVAL if the input width is less than 2 pixels
++ **/
++int ispccdc_try_size(u32 input_w, u32 input_h, u32 *output_w, u32 *output_h)
++{
++	if (input_w < 32 || input_h < 32) {
++		DPRINTK_ISPCCDC("ISP_ERR: CCDC cannot handle input width less"
++				" than 32 pixels or height less than 32\n");
++		return -EINVAL;
++	}
++
++	if (ispccdc_obj.crop_w)
++		*output_w = ispccdc_obj.crop_w;
++	else
++		*output_w = input_w;
++
++	if (ispccdc_obj.crop_h)
++		*output_h = ispccdc_obj.crop_h;
++	else
++		*output_h = input_h;
++
++	if (!ispccdc_obj.refmt_en
++	    && ispccdc_obj.ccdc_outfmt != CCDC_OTHERS_MEM
++	    && ispccdc_obj.ccdc_outfmt != CCDC_OTHERS_VP_MEM)
++		*output_h -= 1;
++
++	if (ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_MEM
++	    || ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_VP_MEM) {
++		if (*output_w % 16) {
++			*output_w -= (*output_w % 16);
++			*output_w += 16;
++		}
++	}
++
++	ispccdc_obj.ccdcout_w = *output_w;
++	ispccdc_obj.ccdcout_h = *output_h;
++	ispccdc_obj.ccdcin_w = input_w;
++	ispccdc_obj.ccdcin_h = input_h;
++
++	DPRINTK_ISPCCDC("try size: ccdcin_w=%u,ccdcin_h=%u,ccdcout_w=%u,"
++			" ccdcout_h=%u\n",
++			ispccdc_obj.ccdcin_w,
++			ispccdc_obj.ccdcin_h,
++			ispccdc_obj.ccdcout_w,
++			ispccdc_obj.ccdcout_h);
++
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_try_size);
++
++/**
++ * ispccdc_config_size - Configure the dimensions of the CCDC input/output
++ * @input_w: input width for the CCDC in number of pixels per line
++ * @input_h: input height for the CCDC in number of lines
++ * @output_w: output width from the CCDC in number of pixels per line
++ * @output_h: output height for the CCDC in number of lines
++ *
++ * Configures the appropriate values stored in the isp_ccdc structure to
++ * HORZ/VERT_INFO registers and the VP_OUT depending on whether the image
++ * is stored in memory or given to the another module in the ISP pipeline.
++ *
++ * Returns 0 if successful, or -EINVAL if try_size was not called before to
++ * validate the requested dimensions.
++ **/
++int ispccdc_config_size(u32 input_w, u32 input_h, u32 output_w, u32 output_h)
++{
++	DPRINTK_ISPCCDC("config size: input_w=%u, input_h=%u, output_w=%u,"
++			" output_h=%u\n",
++			input_w, input_h,
++			output_w, output_h);
++	if (output_w != ispccdc_obj.ccdcout_w
++	    || output_h != ispccdc_obj.ccdcout_h) {
++		DPRINTK_ISPCCDC("ISP_ERR : ispccdc_try_size should"
++				" be called before config size\n");
++		return -EINVAL;
++	}
++
++	if (ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_VP) {
++		isp_reg_writel((ispccdc_obj.ccdcin_woffset <<
++				ISPCCDC_FMT_HORZ_FMTSPH_SHIFT) |
++			       (ispccdc_obj.ccdcin_w <<
++				ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_HORZ);
++		isp_reg_writel((ispccdc_obj.ccdcin_hoffset <<
++				ISPCCDC_FMT_VERT_FMTSLV_SHIFT) |
++			       (ispccdc_obj.ccdcin_h <<
++				ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_VERT);
++		isp_reg_writel((ispccdc_obj.ccdcout_w <<
++				ISPCCDC_VP_OUT_HORZ_NUM_SHIFT) |
++			       (ispccdc_obj.ccdcout_h - 1) <<
++			       ISPCCDC_VP_OUT_VERT_NUM_SHIFT,
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VP_OUT);
++		isp_reg_writel((((ispccdc_obj.ccdcout_h - 25) &
++				 ISPCCDC_VDINT_0_MASK) <<
++				ISPCCDC_VDINT_0_SHIFT) |
++			       ((50 & ISPCCDC_VDINT_1_MASK) <<
++				ISPCCDC_VDINT_1_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VDINT);
++
++	} else if (ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_MEM) {
++		isp_reg_writel(0, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VP_OUT);
++		if (ispccdc_obj.ccdc_inpfmt == CCDC_RAW) {
++			isp_reg_writel(0 << ISPCCDC_HORZ_INFO_SPH_SHIFT
++				       | ((ispccdc_obj.ccdcout_w - 1)
++					  << ISPCCDC_HORZ_INFO_NPH_SHIFT),
++				       OMAP3_ISP_IOMEM_CCDC,
++				       ISPCCDC_HORZ_INFO);
++		} else {
++			isp_reg_writel(0 << ISPCCDC_HORZ_INFO_SPH_SHIFT
++				       | ((ispccdc_obj.ccdcout_w - 1)
++					  << ISPCCDC_HORZ_INFO_NPH_SHIFT),
++				       OMAP3_ISP_IOMEM_CCDC,
++				       ISPCCDC_HORZ_INFO);
++		}
++		isp_reg_writel(0 << ISPCCDC_VERT_START_SLV0_SHIFT,
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VERT_START);
++		isp_reg_writel((ispccdc_obj.ccdcout_h - 1) <<
++			       ISPCCDC_VERT_LINES_NLV_SHIFT,
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VERT_LINES);
++
++		ispccdc_config_outlineoffset(ispccdc_obj.ccdcout_w * 2, 0, 0);
++		isp_reg_writel((((ispccdc_obj.ccdcout_h - 2) &
++				 ISPCCDC_VDINT_0_MASK) <<
++				ISPCCDC_VDINT_0_SHIFT) |
++			       ((100 & ISPCCDC_VDINT_1_MASK) <<
++				ISPCCDC_VDINT_1_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VDINT);
++	} else if (ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_VP_MEM) {
++		isp_reg_writel((0 << ISPCCDC_FMT_HORZ_FMTSPH_SHIFT) |
++			       (ispccdc_obj.ccdcin_w <<
++				ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_HORZ);
++		isp_reg_writel((0 << ISPCCDC_FMT_VERT_FMTSLV_SHIFT) |
++			       ((ispccdc_obj.ccdcin_h) <<
++				ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_FMT_VERT);
++		isp_reg_writel((ispccdc_obj.ccdcout_w
++				<< ISPCCDC_VP_OUT_HORZ_NUM_SHIFT) |
++			       ((ispccdc_obj.ccdcout_h - 1) <<
++				ISPCCDC_VP_OUT_VERT_NUM_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VP_OUT);
++		isp_reg_writel(0 << ISPCCDC_HORZ_INFO_SPH_SHIFT |
++			       ((ispccdc_obj.ccdcout_w - 1) <<
++				ISPCCDC_HORZ_INFO_NPH_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_HORZ_INFO);
++		isp_reg_writel(0 << ISPCCDC_VERT_START_SLV0_SHIFT,
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VERT_START);
++		isp_reg_writel((ispccdc_obj.ccdcout_h - 1) <<
++			       ISPCCDC_VERT_LINES_NLV_SHIFT,
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VERT_LINES);
++		ispccdc_config_outlineoffset(ispccdc_obj.ccdcout_w * 2, 0, 0);
++		isp_reg_writel((((ispccdc_obj.ccdcout_h - 2) &
++				 ISPCCDC_VDINT_0_MASK) <<
++				ISPCCDC_VDINT_0_SHIFT) |
++			       ((100 & ISPCCDC_VDINT_1_MASK) <<
++				ISPCCDC_VDINT_1_SHIFT),
++			       OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_VDINT);
++	}
++
++	if (is_isplsc_activated()) {
++		if (ispccdc_obj.ccdc_inpfmt == CCDC_RAW) {
++			ispccdc_config_lsc(&lsc_config);
++			ispccdc_load_lsc(lsc_gain_table, lsc_config.size);
++		}
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_size);
++
++/**
++ * ispccdc_config_outlineoffset - Configures the output line offset
++ * @offset: Must be twice the Output width and aligned on 32 byte boundary
++ * @oddeven: Specifies the odd/even line pattern to be chosen to store the
++ *           output.
++ * @numlines: Set the value 0-3 for +1-4lines, 4-7 for -1-4lines.
++ *
++ * - Configures the output line offset when stored in memory
++ * - Sets the odd/even line pattern to store the output
++ *    (EVENEVEN (1), ODDEVEN (2), EVENODD (3), ODDODD (4))
++ * - Configures the number of even and odd line fields in case of rearranging
++ * the lines.
++ *
++ * Returns 0 if successful, or -EINVAL if the offset is not in 32 byte
++ * boundary.
++ **/
++int ispccdc_config_outlineoffset(u32 offset, u8 oddeven, u8 numlines)
++{
++	if ((offset & ISP_32B_BOUNDARY_OFFSET) == offset) {
++		isp_reg_writel((offset & 0xFFFF), OMAP3_ISP_IOMEM_CCDC,
++			       ISPCCDC_HSIZE_OFF);
++	} else {
++		DPRINTK_ISPCCDC("ISP_ERR : Offset should be in 32 byte"
++				" boundary\n");
++		return -EINVAL;
++	}
++
++	isp_reg_and(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
++		    ~ISPCCDC_SDOFST_FINV);
++
++	isp_reg_and(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
++		    ~ISPCCDC_SDOFST_FOFST_4L);
++
++	switch (oddeven) {
++	case EVENEVEN:
++		isp_reg_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
++			   (numlines & 0x7) << ISPCCDC_SDOFST_LOFST0_SHIFT);
++		break;
++	case ODDEVEN:
++		isp_reg_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
++			   (numlines & 0x7) << ISPCCDC_SDOFST_LOFST1_SHIFT);
++		break;
++	case EVENODD:
++		isp_reg_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
++			   (numlines & 0x7) << ISPCCDC_SDOFST_LOFST2_SHIFT);
++		break;
++	case ODDODD:
++		isp_reg_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST,
++			   (numlines & 0x7) << ISPCCDC_SDOFST_LOFST3_SHIFT);
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_outlineoffset);
++
++/**
++ * ispccdc_set_outaddr - Sets the memory address where the output will be saved
++ * @addr: 32-bit memory address aligned on 32 byte boundary.
++ *
++ * Sets the memory address where the output will be saved.
++ *
++ * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
++ * boundary.
++ **/
++int ispccdc_set_outaddr(u32 addr)
++{
++	if ((addr & ISP_32B_BOUNDARY_BUF) == addr) {
++		isp_reg_writel(addr, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR);
++		return 0;
++	} else {
++		DPRINTK_ISPCCDC("ISP_ERR : Address should be in 32 byte"
++				" boundary\n");
++		return -EINVAL;
++	}
++
++}
++EXPORT_SYMBOL(ispccdc_set_outaddr);
++
++void __ispccdc_enable(u8 enable)
++{
++	if (enable) {
++		if (ispccdc_obj.lsc_enable
++		    && ispccdc_obj.ccdc_inpfmt == CCDC_RAW)
++			ispccdc_enable_lsc(1);
++
++	} else {
++		ispccdc_obj.lsc_enable = ispccdc_obj.lsc_state;
++	}
++
++	isp_reg_and_or(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR, ~ISPCCDC_PCR_EN,
++		       enable ? ISPCCDC_PCR_EN : 0);
++}
++
++/**
++ * ispccdc_enable - Enables the CCDC module.
++ * @enable: 0 Disables CCDC, 1 Enables CCDC
++ *
++ * Client should configure all the sub modules in CCDC before this.
++ **/
++void ispccdc_enable(u8 enable)
++{
++	__ispccdc_enable(enable);
++	ispccdc_obj.pm_state = enable;
++}
++EXPORT_SYMBOL(ispccdc_enable);
++
++/**
++ * ispccdc_suspend - Suspend the CCDC module.
++ **/
++void ispccdc_suspend(void)
++{
++	if (ispccdc_obj.pm_state) {
++		if (ispccdc_obj.lsc_state)
++			__ispccdc_enable_lsc(0);
++		else if (ispccdc_obj.lsc_enable) {
++			ispccdc_obj.lsc_state = 1;
++			ispccdc_obj.lsc_enable = 0;
++		}
++		__ispccdc_enable(0);
++	}
++}
++EXPORT_SYMBOL(ispccdc_suspend);
++
++/**
++ * ispccdc_resume - Resume the CCDC module.
++ **/
++void ispccdc_resume(void)
++{
++	if (ispccdc_obj.pm_state) {
++		if (ispccdc_obj.lsc_state)
++			__ispccdc_enable_lsc(1);
++		__ispccdc_enable(1);
++	}
++}
++EXPORT_SYMBOL(ispccdc_resume);
++
++/*
++ * Returns zero if the CCDC is idle and the image has been written to
++ * memory, too.
++ */
++int ispccdc_sbl_busy(void)
++{
++	return ispccdc_busy()
++		| (isp_reg_readl(OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_0) &
++		   ISPSBL_CCDC_WR_0_DATA_READY)
++		| (isp_reg_readl(OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_1) &
++		   ISPSBL_CCDC_WR_0_DATA_READY)
++		| (isp_reg_readl(OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_2) &
++		   ISPSBL_CCDC_WR_0_DATA_READY)
++		| (isp_reg_readl(OMAP3_ISP_IOMEM_SBL, ISPSBL_CCDC_WR_3) &
++		   ISPSBL_CCDC_WR_0_DATA_READY);
++}
++EXPORT_SYMBOL(ispccdc_sbl_busy);
++
++/**
++ * ispccdc_busy - Gets busy state of the CCDC.
++ **/
++int ispccdc_busy(void)
++{
++	return isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR) &
++		ISPCCDC_PCR_BUSY;
++}
++EXPORT_SYMBOL(ispccdc_busy);
++
++/**
++ * ispccdc_save_context - Saves the values of the CCDC module registers
++ **/
++void ispccdc_save_context(void)
++{
++	DPRINTK_ISPCCDC("Saving context\n");
++	isp_save_context(ispccdc_reg_list);
++}
++EXPORT_SYMBOL(ispccdc_save_context);
++
++/**
++ * ispccdc_restore_context - Restores the values of the CCDC module registers
++ **/
++void ispccdc_restore_context(void)
++{
++	DPRINTK_ISPCCDC("Restoring context\n");
++	isp_restore_context(ispccdc_reg_list);
++}
++EXPORT_SYMBOL(ispccdc_restore_context);
++
++/**
++ * ispccdc_print_status - Prints the values of the CCDC Module registers
++ *
++ * Also prints other debug information stored in the CCDC module.
++ **/
++void ispccdc_print_status(void)
++{
++	if (!is_ispccdc_debug_enabled())
++		return;
++
++	DPRINTK_ISPCCDC("Module in use =%d\n", ispccdc_obj.ccdc_inuse);
++	DPRINTK_ISPCCDC("Accepted CCDC Input (width = %d,Height = %d)\n",
++			ispccdc_obj.ccdcin_w,
++			ispccdc_obj.ccdcin_h);
++	DPRINTK_ISPCCDC("Accepted CCDC Output (width = %d,Height = %d)\n",
++			ispccdc_obj.ccdcout_w,
++			ispccdc_obj.ccdcout_h);
++	DPRINTK_ISPCCDC("###CCDC PCR=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_PCR));
++	DPRINTK_ISPCCDC("ISP_CTRL =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL));
++	switch (ispccdc_obj.ccdc_inpfmt) {
++	case CCDC_RAW:
++		DPRINTK_ISPCCDC("ccdc input format is CCDC_RAW\n");
++		break;
++	case CCDC_YUV_SYNC:
++		DPRINTK_ISPCCDC("ccdc input format is CCDC_YUV_SYNC\n");
++		break;
++	case CCDC_YUV_BT:
++		DPRINTK_ISPCCDC("ccdc input format is CCDC_YUV_BT\n");
++		break;
++	}
++
++	switch (ispccdc_obj.ccdc_outfmt) {
++	case CCDC_OTHERS_VP:
++		DPRINTK_ISPCCDC("ccdc output format is CCDC_OTHERS_VP\n");
++		break;
++	case CCDC_OTHERS_MEM:
++		DPRINTK_ISPCCDC("ccdc output format is CCDC_OTHERS_MEM\n");
++		break;
++	case CCDC_YUV_RSZ:
++		DPRINTK_ISPCCDC("ccdc output format is CCDC_YUV_RSZ\n");
++		break;
++	}
++
++	DPRINTK_ISPCCDC("###ISP_CTRL in ccdc =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL));
++	DPRINTK_ISPCCDC("###ISP_IRQ0ENABLE in ccdc =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE));
++	DPRINTK_ISPCCDC("###ISP_IRQ0STATUS in ccdc =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS));
++	DPRINTK_ISPCCDC("###CCDC SYN_MODE=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE));
++	DPRINTK_ISPCCDC("###CCDC HORZ_INFO=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HORZ_INFO));
++	DPRINTK_ISPCCDC("###CCDC VERT_START=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++				      ISPCCDC_VERT_START));
++	DPRINTK_ISPCCDC("###CCDC VERT_LINES=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++				      ISPCCDC_VERT_LINES));
++	DPRINTK_ISPCCDC("###CCDC CULLING=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CULLING));
++	DPRINTK_ISPCCDC("###CCDC HSIZE_OFF=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HSIZE_OFF));
++	DPRINTK_ISPCCDC("###CCDC SDOFST=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDOFST));
++	DPRINTK_ISPCCDC("###CCDC SDR_ADDR=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR));
++	DPRINTK_ISPCCDC("###CCDC CLAMP=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CLAMP));
++	DPRINTK_ISPCCDC("###CCDC COLPTN=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_COLPTN));
++	DPRINTK_ISPCCDC("###CCDC CFG=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG));
++	DPRINTK_ISPCCDC("###CCDC VP_OUT=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_VP_OUT));
++	DPRINTK_ISPCCDC("###CCDC_SDR_ADDR= 0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR));
++	DPRINTK_ISPCCDC("###CCDC FMTCFG=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG));
++	DPRINTK_ISPCCDC("###CCDC FMT_HORZ=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_HORZ));
++	DPRINTK_ISPCCDC("###CCDC FMT_VERT=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMT_VERT));
++	DPRINTK_ISPCCDC("###CCDC LSC_CONFIG=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++				      ISPCCDC_LSC_CONFIG));
++	DPRINTK_ISPCCDC("###CCDC LSC_INIT=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++				      ISPCCDC_LSC_INITIAL));
++	DPRINTK_ISPCCDC("###CCDC LSC_TABLE BASE=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++				      ISPCCDC_LSC_TABLE_BASE));
++	DPRINTK_ISPCCDC("###CCDC LSC TABLE OFFSET=0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++				      ISPCCDC_LSC_TABLE_OFFSET));
++}
++EXPORT_SYMBOL(ispccdc_print_status);
++
++/**
++ * isp_ccdc_init - CCDC module initialization.
++ *
++ * Always returns 0
++ **/
++int __init isp_ccdc_init(void)
++{
++	ispccdc_obj.ccdc_inuse = 0;
++	ispccdc_config_crop(0, 0, 0, 0);
++	mutex_init(&ispccdc_obj.mutexlock);
++
++	if (is_isplsc_activated()) {
++		lsc_gain_table_tmp = kmalloc(LSC_TABLE_INIT_SIZE, GFP_KERNEL |
++					     GFP_DMA);
++		memset(lsc_gain_table_tmp, 0x40, LSC_TABLE_INIT_SIZE);
++		lsc_config.initial_x = 0;
++		lsc_config.initial_y = 0;
++		lsc_config.gain_mode_n = 0x6;
++		lsc_config.gain_mode_m = 0x6;
++		lsc_config.gain_format = 0x4;
++		lsc_config.offset = 0x60;
++		lsc_config.size = LSC_TABLE_INIT_SIZE;
++		ispccdc_obj.lsc_enable = 1;
++	}
++
++	return 0;
++}
++
++/**
++ * isp_ccdc_cleanup - CCDC module cleanup.
++ **/
++void isp_ccdc_cleanup(void)
++{
++	if (is_isplsc_activated()) {
++		ispccdc_free_lsc();
++		kfree(lsc_gain_table_tmp);
++	}
++
++	if (fpc_table_add_m != 0) {
++		ispmmu_kunmap(fpc_table_add_m);
++		kfree(fpc_table_add);
++	}
++}
+diff --git a/drivers/media/video/isp/ispccdc.h b/drivers/media/video/isp/ispccdc.h
+new file mode 100644
+index 0000000..4ef40a6
+--- /dev/null
++++ b/drivers/media/video/isp/ispccdc.h
+@@ -0,0 +1,209 @@
++/*
++ * ispccdc.h
++ *
++ * Driver header file for CCDC module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Senthilvadivu Guruswamy <svadivu@ti.com>
++ *	Pallavi Kulkarni <p-kulkarni@ti.com>
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_CCDC_H
++#define OMAP_ISP_CCDC_H
++
++#include <mach/isp_user.h>
++
++#define is_isplsc_activated()		1
++
++/* Enumeration constants for CCDC input output format */
++enum ccdc_input {
++	CCDC_RAW,
++	CCDC_YUV_SYNC,
++	CCDC_YUV_BT,
++	CCDC_OTHERS
++};
++
++enum ccdc_output {
++	CCDC_YUV_RSZ,
++	CCDC_YUV_MEM_RSZ,
++	CCDC_OTHERS_VP,
++	CCDC_OTHERS_MEM,
++	CCDC_OTHERS_VP_MEM
++};
++
++/* Enumeration constants for the sync interface parameters */
++enum inpmode {
++	RAW,
++	YUV16,
++	YUV8
++};
++enum datasize {
++	DAT8,
++	DAT10,
++	DAT11,
++	DAT12
++};
++
++
++/**
++ * struct ispccdc_syncif - Structure for Sync Interface between sensor and CCDC
++ * @ccdc_mastermode: Master mode. 1 - Master, 0 - Slave.
++ * @fldstat: Field state. 0 - Odd Field, 1 - Even Field.
++ * @ipmod: Input mode.
++ * @datsz: Data size.
++ * @fldmode: 0 - Progressive, 1 - Interlaced.
++ * @datapol: 0 - Positive, 1 - Negative.
++ * @fldpol: 0 - Positive, 1 - Negative.
++ * @hdpol: 0 - Positive, 1 - Negative.
++ * @vdpol: 0 - Positive, 1 - Negative.
++ * @fldout: 0 - Input, 1 - Output.
++ * @hs_width: Width of the Horizontal Sync pulse, used for HS/VS Output.
++ * @vs_width: Width of the Vertical Sync pulse, used for HS/VS Output.
++ * @ppln: Number of pixels per line, used for HS/VS Output.
++ * @hlprf: Number of half lines per frame, used for HS/VS Output.
++ * @bt_r656_en: 1 - Enable ITU-R BT656 mode, 0 - Sync mode.
++ */
++struct ispccdc_syncif {
++	u8 ccdc_mastermode;
++	u8 fldstat;
++	enum inpmode ipmod;
++	enum datasize datsz;
++	u8 fldmode;
++	u8 datapol;
++	u8 fldpol;
++	u8 hdpol;
++	u8 vdpol;
++	u8 fldout;
++	u8 hs_width;
++	u8 vs_width;
++	u8 ppln;
++	u8 hlprf;
++	u8 bt_r656_en;
++};
++
++/**
++ * ispccdc_refmt - Structure for Reformatter parameters
++ * @lnalt: Line alternating mode enable. 0 - Enable, 1 - Disable.
++ * @lnum: Number of output lines from 1 input line. 1 to 4 lines.
++ * @plen_even: Number of program entries in even line minus 1.
++ * @plen_odd: Number of program entries in odd line minus 1.
++ * @prgeven0: Program entries 0-7 for even lines register
++ * @prgeven1: Program entries 8-15 for even lines register
++ * @prgodd0: Program entries 0-7 for odd lines register
++ * @prgodd1: Program entries 8-15 for odd lines register
++ * @fmtaddr0: Output line in which the original pixel is to be placed
++ * @fmtaddr1: Output line in which the original pixel is to be placed
++ * @fmtaddr2: Output line in which the original pixel is to be placed
++ * @fmtaddr3: Output line in which the original pixel is to be placed
++ * @fmtaddr4: Output line in which the original pixel is to be placed
++ * @fmtaddr5: Output line in which the original pixel is to be placed
++ * @fmtaddr6: Output line in which the original pixel is to be placed
++ * @fmtaddr7: Output line in which the original pixel is to be placed
++ */
++struct ispccdc_refmt {
++	u8 lnalt;
++	u8 lnum;
++	u8 plen_even;
++	u8 plen_odd;
++	u32 prgeven0;
++	u32 prgeven1;
++	u32 prgodd0;
++	u32 prgodd1;
++	u32 fmtaddr0;
++	u32 fmtaddr1;
++	u32 fmtaddr2;
++	u32 fmtaddr3;
++	u32 fmtaddr4;
++	u32 fmtaddr5;
++	u32 fmtaddr6;
++	u32 fmtaddr7;
++};
++
++int ispccdc_request(void);
++
++int ispccdc_free(void);
++
++int ispccdc_config_datapath(enum ccdc_input input, enum ccdc_output output);
++
++void ispccdc_config_crop(u32 left, u32 top, u32 height, u32 width);
++
++void ispccdc_config_sync_if(struct ispccdc_syncif syncif);
++
++int ispccdc_config_black_clamp(struct ispccdc_bclamp bclamp);
++
++void ispccdc_enable_black_clamp(u8 enable);
++
++int ispccdc_config_fpc(struct ispccdc_fpc fpc);
++
++void ispccdc_enable_fpc(u8 enable);
++
++void ispccdc_config_black_comp(struct ispccdc_blcomp blcomp);
++
++void ispccdc_config_vp(struct ispccdc_vp vp);
++
++void ispccdc_enable_vp(u8 enable);
++
++void ispccdc_config_reformatter(struct ispccdc_refmt refmt);
++
++void ispccdc_enable_reformatter(u8 enable);
++
++void ispccdc_config_culling(struct ispccdc_culling culling);
++
++void ispccdc_enable_lpf(u8 enable);
++
++void ispccdc_config_alaw(enum alaw_ipwidth ipwidth);
++
++void ispccdc_enable_alaw(u8 enable);
++
++int ispccdc_load_lsc(u8 *table_addr, u32 table_size);
++
++void ispccdc_config_lsc(struct ispccdc_lsc_config *lsc_cfg);
++
++void ispccdc_enable_lsc(u8 enable);
++
++void ispccdc_lsc_error_handler(void);
++
++void ispccdc_config_imgattr(u32 colptn);
++
++void ispccdc_config_shadow_registers(void);
++
++int ispccdc_try_size(u32 input_w, u32 input_h, u32 *output_w, u32 *output_h);
++
++int ispccdc_config_size(u32 input_w, u32 input_h, u32 output_w, u32 output_h);
++
++int ispccdc_config_outlineoffset(u32 offset, u8 oddeven, u8 numlines);
++
++int ispccdc_set_outaddr(u32 addr);
++
++void ispccdc_enable(u8 enable);
++
++void ispccdc_suspend(void);
++
++void ispccdc_resume(void);
++
++int ispccdc_sbl_busy(void);
++
++int ispccdc_busy(void);
++
++void ispccdc_save_context(void);
++
++void ispccdc_restore_context(void);
++
++void ispccdc_print_status(void);
++
++int omap34xx_isp_ccdc_config(void *userspace_add);
++
++void ispccdc_set_wenlog(u32 wenlog);
++
++#endif		/* OMAP_ISP_CCDC_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0005-omap3isp-Add-ISP-backend-PRV-and-RSZ.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0005-omap3isp-Add-ISP-backend-PRV-and-RSZ.patch
new file mode 100644
index 0000000000..c549eadc88
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0005-omap3isp-Add-ISP-backend-PRV-and-RSZ.patch
@@ -0,0 +1,3413 @@
+From 926b51afea146826c8076e5fb305eaa0332399b4 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:02 +0200
+Subject: [PATCH] omap3isp: Add ISP backend (PRV and RSZ)
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ drivers/media/video/isp/isppreview.c | 1929 ++++++++++++++++++++++++++++++++++
+ drivers/media/video/isp/isppreview.h |  354 +++++++
+ drivers/media/video/isp/ispresizer.c |  928 ++++++++++++++++
+ drivers/media/video/isp/ispresizer.h |  158 +++
+ 4 files changed, 3369 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/isp/isppreview.c
+ create mode 100644 drivers/media/video/isp/isppreview.h
+ create mode 100644 drivers/media/video/isp/ispresizer.c
+ create mode 100644 drivers/media/video/isp/ispresizer.h
+
+diff --git a/drivers/media/video/isp/isppreview.c b/drivers/media/video/isp/isppreview.c
+new file mode 100644
+index 0000000..17f1abc
+--- /dev/null
++++ b/drivers/media/video/isp/isppreview.c
+@@ -0,0 +1,1929 @@
++/*
++ * isppreview.c
++ *
++ * Driver Library for Preview module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Senthilvadivu Guruswamy <svadivu@ti.com>
++ *	Pallavi Kulkarni <p-kulkarni@ti.com>
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/mutex.h>
++#include <linux/module.h>
++#include <linux/uaccess.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "isppreview.h"
++
++static struct ispprev_nf prev_nf_t;
++static struct prev_params *params;
++static int rg_update, gg_update, bg_update, nf_enable, nf_update;
++
++/* Structure for saving/restoring preview module registers */
++static struct isp_reg ispprev_reg_list[] = {
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_HORZ_INFO, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_VERT_INFO, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RSDR_ADDR, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RADR_OFFSET, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_DSDR_ADDR, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_DRKF_OFFSET, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_WSDR_ADDR, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_WADD_OFFSET, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_AVE, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_HMED, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_NF, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_WB_DGAIN, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_WBSEL, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CFA, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_BLKADJOFF, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT1, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT2, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT3, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT4, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT5, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF1, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF2, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC0, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC1, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC2, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC_OFFSET, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CSUP, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_SETUP_YC, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR0, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR1, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR2, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR3, 0x0000},
++	{OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, 0x0000},
++	{0, ISP_TOK_TERM, 0x0000}
++};
++
++
++/* Default values in Office Flourescent Light for RGBtoRGB Blending */
++static struct ispprev_rgbtorgb flr_rgb2rgb = {
++	{	/* RGB-RGB Matrix */
++		{0x01E2, 0x0F30, 0x0FEE},
++		{0x0F9B, 0x01AC, 0x0FB9},
++		{0x0FE0, 0x0EC0, 0x0260}
++	},	/* RGB Offset */
++	{0x0000, 0x0000, 0x0000}
++};
++
++/* Default values in Office Flourescent Light for RGB to YUV Conversion*/
++static struct ispprev_csc flr_prev_csc[] = {
++	{
++		{	/* CSC Coef Matrix */
++			{66, 129, 25},
++			{-38, -75, 112},
++			{112, -94 , -18}
++		},	/* CSC Offset */
++		{0x0, 0x0, 0x0}
++	},
++	{
++		{	/* CSC Coef Matrix BW */
++			{66, 129, 25},
++			{0, 0, 0},
++			{0, 0, 0}
++		},	/* CSC Offset */
++		{0x0, 0x0, 0x0}
++	},
++	{
++		{	/* CSC Coef Matrix Sepia */
++			{19, 38, 7},
++			{0, 0, 0},
++			{0, 0, 0}
++		},	/* CSC Offset */
++		{0x0, 0xE7, 0x14}
++	}
++};
++
++
++/* Default values in Office Flourescent Light for CFA Gradient*/
++#define FLR_CFA_GRADTHRS_HORZ	0x28
++#define FLR_CFA_GRADTHRS_VERT	0x28
++
++/* Default values in Office Flourescent Light for Chroma Suppression*/
++#define FLR_CSUP_GAIN		0x0D
++#define FLR_CSUP_THRES		0xEB
++
++/* Default values in Office Flourescent Light for Noise Filter*/
++#define FLR_NF_STRGTH		0x03
++
++/* Default values in Office Flourescent Light for White Balance*/
++#define FLR_WBAL_DGAIN		0x100
++#define FLR_WBAL_COEF0		0x20
++#define FLR_WBAL_COEF1		0x29
++#define FLR_WBAL_COEF2		0x2d
++#define FLR_WBAL_COEF3		0x20
++
++#define FLR_WBAL_COEF0_ES1	0x20
++#define FLR_WBAL_COEF1_ES1	0x23
++#define FLR_WBAL_COEF2_ES1	0x39
++#define FLR_WBAL_COEF3_ES1	0x20
++
++/* Default values in Office Flourescent Light for Black Adjustment*/
++#define FLR_BLKADJ_BLUE		0x0
++#define FLR_BLKADJ_GREEN	0x0
++#define FLR_BLKADJ_RED		0x0
++
++static int update_color_matrix;
++
++/**
++ * struct isp_prev - Structure for storing ISP Preview module information
++ * @prev_inuse: Flag to determine if CCDC has been reserved or not (0 or 1).
++ * @prevout_w: Preview output width.
++ * @prevout_h: Preview output height.
++ * @previn_w: Preview input width.
++ * @previn_h: Preview input height.
++ * @prev_inpfmt: Preview input format.
++ * @prev_outfmt: Preview output format.
++ * @hmed_en: Horizontal median filter enable.
++ * @nf_en: Noise filter enable.
++ * @dcor_en: Defect correction enable.
++ * @cfa_en: Color Filter Array (CFA) interpolation enable.
++ * @csup_en: Chrominance suppression enable.
++ * @yenh_en: Luma enhancement enable.
++ * @fmtavg: Number of horizontal pixels to average in input formatter. The
++ *          input width should be a multiple of this number.
++ * @brightness: Brightness in preview module.
++ * @contrast: Contrast in preview module.
++ * @color: Color effect in preview module.
++ * @cfafmt: Color Filter Array (CFA) Format.
++ * @ispprev_mutex: Mutex for isp preview.
++ *
++ * This structure is used to store the OMAP ISP Preview module Information.
++ */
++static struct isp_prev {
++	int pm_state;
++	u8 prev_inuse;
++	u32 prevout_w;
++	u32 prevout_h;
++	u32 previn_w;
++	u32 previn_h;
++	enum preview_input prev_inpfmt;
++	enum preview_output prev_outfmt;
++	u8 hmed_en;
++	u8 nf_en;
++	u8 dcor_en;
++	u8 cfa_en;
++	u8 csup_en;
++	u8 yenh_en;
++	u8 fmtavg;
++	u8 brightness;
++	u8 contrast;
++	enum v4l2_colorfx color;
++	enum cfa_fmt cfafmt;
++	struct mutex ispprev_mutex; /* For checking/modifying prev_inuse */
++	u32 sph;
++	u32 slv;
++} ispprev_obj;
++
++/* Saved parameters */
++static struct prev_params *prev_config_params;
++
++/*
++ * Coeficient Tables for the submodules in Preview.
++ * Array is initialised with the values from.the tables text file.
++ */
++
++/*
++ * CFA Filter Coefficient Table
++ *
++ */
++static u32 cfa_coef_table[] = {
++#include "cfa_coef_table.h"
++};
++
++/*
++ * Gamma Correction Table - Red
++ */
++static u32 redgamma_table[] = {
++#include "redgamma_table.h"
++};
++
++/*
++ * Gamma Correction Table - Green
++ */
++static u32 greengamma_table[] = {
++#include "greengamma_table.h"
++};
++
++/*
++ * Gamma Correction Table - Blue
++ */
++static u32 bluegamma_table[] = {
++#include "bluegamma_table.h"
++};
++
++/*
++ * Noise Filter Threshold table
++ */
++static u32 noise_filter_table[] = {
++#include "noise_filter_table.h"
++};
++
++/*
++ * Luminance Enhancement Table
++ */
++static u32 luma_enhance_table[] = {
++#include "luma_enhance_table.h"
++};
++
++/**
++ * omap34xx_isp_preview_config - Abstraction layer Preview configuration.
++ * @userspace_add: Pointer from Userspace to structure with flags and data to
++ *                 update.
++ **/
++int omap34xx_isp_preview_config(void *userspace_add)
++{
++	struct ispprev_hmed prev_hmed_t;
++	struct ispprev_cfa prev_cfa_t;
++	struct ispprev_csup csup_t;
++	struct ispprev_wbal prev_wbal_t;
++	struct ispprev_blkadj prev_blkadj_t;
++	struct ispprev_rgbtorgb rgb2rgb_t;
++	struct ispprev_csc prev_csc_t;
++	struct ispprev_yclimit yclimit_t;
++	struct ispprev_dcor prev_dcor_t;
++	struct ispprv_update_config *preview_struct;
++	struct isptables_update isp_table_update;
++	int yen_t[ISPPRV_YENH_TBL_SIZE];
++
++	if (userspace_add == NULL)
++		return -EINVAL;
++
++	preview_struct = userspace_add;
++
++	if (ISP_ABS_PREV_LUMAENH & preview_struct->flag) {
++		if (ISP_ABS_PREV_LUMAENH & preview_struct->update) {
++			if (copy_from_user(yen_t, preview_struct->yen,
++					   sizeof(yen_t)))
++				goto err_copy_from_user;
++			isppreview_config_luma_enhancement(yen_t);
++		}
++		params->features |= PREV_LUMA_ENHANCE;
++	} else if (ISP_ABS_PREV_LUMAENH & preview_struct->update)
++		params->features &= ~PREV_LUMA_ENHANCE;
++
++	if (ISP_ABS_PREV_INVALAW & preview_struct->flag) {
++		isppreview_enable_invalaw(1);
++		params->features |= PREV_INVERSE_ALAW;
++	} else {
++		isppreview_enable_invalaw(0);
++		params->features &= ~PREV_INVERSE_ALAW;
++	}
++
++	if (ISP_ABS_PREV_HRZ_MED & preview_struct->flag) {
++		if (ISP_ABS_PREV_HRZ_MED & preview_struct->update) {
++			if (copy_from_user(&prev_hmed_t,
++					   (struct ispprev_hmed *)
++					   preview_struct->prev_hmed,
++					   sizeof(struct ispprev_hmed)))
++				goto err_copy_from_user;
++			isppreview_config_hmed(prev_hmed_t);
++		}
++		isppreview_enable_hmed(1);
++		params->features |= PREV_HORZ_MEDIAN_FILTER;
++	} else if (ISP_ABS_PREV_HRZ_MED & preview_struct->update) {
++		isppreview_enable_hmed(0);
++		params->features &= ~PREV_HORZ_MEDIAN_FILTER;
++	}
++
++	if (ISP_ABS_PREV_CFA & preview_struct->flag) {
++		if (ISP_ABS_PREV_CFA & preview_struct->update) {
++			if (copy_from_user(&prev_cfa_t,
++					   (struct ispprev_cfa *)
++					   preview_struct->prev_cfa,
++					   sizeof(struct ispprev_cfa)))
++				goto err_copy_from_user;
++
++			isppreview_config_cfa(prev_cfa_t);
++		}
++		isppreview_enable_cfa(1);
++		params->features |= PREV_CFA;
++	} else if (ISP_ABS_PREV_CFA & preview_struct->update) {
++		isppreview_enable_cfa(0);
++		params->features &= ~PREV_CFA;
++	}
++
++	if (ISP_ABS_PREV_CHROMA_SUPP & preview_struct->flag) {
++		if (ISP_ABS_PREV_CHROMA_SUPP & preview_struct->update) {
++			if (copy_from_user(&csup_t,
++					   (struct ispprev_csup *)
++					   preview_struct->csup,
++					   sizeof(struct ispprev_csup)))
++				goto err_copy_from_user;
++			isppreview_config_chroma_suppression(csup_t);
++		}
++		isppreview_enable_chroma_suppression(1);
++		params->features |= PREV_CHROMA_SUPPRESS;
++	} else if (ISP_ABS_PREV_CHROMA_SUPP & preview_struct->update) {
++		isppreview_enable_chroma_suppression(0);
++		params->features &= ~PREV_CHROMA_SUPPRESS;
++	}
++
++	if (ISP_ABS_PREV_WB & preview_struct->update) {
++		if (copy_from_user(&prev_wbal_t, (struct ispprev_wbal *)
++				   preview_struct->prev_wbal,
++				   sizeof(struct ispprev_wbal)))
++			goto err_copy_from_user;
++		isppreview_config_whitebalance(prev_wbal_t);
++	}
++
++	if (ISP_ABS_PREV_BLKADJ & preview_struct->update) {
++		if (copy_from_user(&prev_blkadj_t, (struct ispprev_blkadjl *)
++				   preview_struct->prev_blkadj,
++				   sizeof(struct ispprev_blkadj)))
++			goto err_copy_from_user;
++		isppreview_config_blkadj(prev_blkadj_t);
++	}
++
++	if (ISP_ABS_PREV_RGB2RGB & preview_struct->update) {
++		if (copy_from_user(&rgb2rgb_t, (struct ispprev_rgbtorgb *)
++				   preview_struct->rgb2rgb,
++				   sizeof(struct ispprev_rgbtorgb)))
++			goto err_copy_from_user;
++		isppreview_config_rgb_blending(rgb2rgb_t);
++	}
++
++	if (ISP_ABS_PREV_COLOR_CONV & preview_struct->update) {
++		if (copy_from_user(&prev_csc_t, (struct ispprev_csc *)
++				   preview_struct->prev_csc,
++				   sizeof(struct ispprev_csc)))
++			goto err_copy_from_user;
++		isppreview_config_rgb_to_ycbcr(prev_csc_t);
++	}
++
++	if (ISP_ABS_PREV_YC_LIMIT & preview_struct->update) {
++		if (copy_from_user(&yclimit_t, (struct ispprev_yclimit *)
++				   preview_struct->yclimit,
++				   sizeof(struct ispprev_yclimit)))
++			goto err_copy_from_user;
++		isppreview_config_yc_range(yclimit_t);
++	}
++
++	if (ISP_ABS_PREV_DEFECT_COR & preview_struct->flag) {
++		if (ISP_ABS_PREV_DEFECT_COR & preview_struct->update) {
++			if (copy_from_user(&prev_dcor_t,
++					   (struct ispprev_dcor *)
++					   preview_struct->prev_dcor,
++					   sizeof(struct ispprev_dcor)))
++				goto err_copy_from_user;
++			isppreview_config_dcor(prev_dcor_t);
++		}
++		isppreview_enable_dcor(1);
++		params->features |= PREV_DEFECT_COR;
++	} else if (ISP_ABS_PREV_DEFECT_COR & preview_struct->update) {
++		isppreview_enable_dcor(0);
++		params->features &= ~PREV_DEFECT_COR;
++	}
++
++	if (ISP_ABS_PREV_GAMMABYPASS & preview_struct->flag) {
++		isppreview_enable_gammabypass(1);
++		params->features |= PREV_GAMMA_BYPASS;
++	} else {
++		isppreview_enable_gammabypass(0);
++		params->features &= ~PREV_GAMMA_BYPASS;
++	}
++
++	isp_table_update.update = preview_struct->update;
++	isp_table_update.flag = preview_struct->flag;
++	isp_table_update.prev_nf = preview_struct->prev_nf;
++	isp_table_update.red_gamma = preview_struct->red_gamma;
++	isp_table_update.green_gamma = preview_struct->green_gamma;
++	isp_table_update.blue_gamma = preview_struct->blue_gamma;
++
++	if (omap34xx_isp_tables_update(&isp_table_update))
++		goto err_copy_from_user;
++
++	return 0;
++
++err_copy_from_user:
++	printk(KERN_ERR "Preview Config: Copy From User Error\n");
++	return -EFAULT;
++}
++EXPORT_SYMBOL_GPL(omap34xx_isp_preview_config);
++
++/**
++ * omap34xx_isp_tables_update - Abstraction layer Tables update.
++ * @isptables_struct: Pointer from Userspace to structure with flags and table
++ *                 data to update.
++ **/
++int omap34xx_isp_tables_update(struct isptables_update *isptables_struct)
++{
++
++	if (ISP_ABS_TBL_NF & isptables_struct->flag) {
++		nf_enable = 1;
++		params->features |= PREV_NOISE_FILTER;
++		if (ISP_ABS_TBL_NF & isptables_struct->update) {
++			if (copy_from_user(&prev_nf_t, (struct ispprev_nf *)
++					   isptables_struct->prev_nf,
++					   sizeof(struct ispprev_nf)))
++				goto err_copy_from_user;
++
++			nf_update = 1;
++		} else
++			nf_update = 0;
++	} else {
++		nf_enable = 0;
++		params->features &= ~PREV_NOISE_FILTER;
++		if (ISP_ABS_TBL_NF & isptables_struct->update)
++			nf_update = 1;
++		else
++			nf_update = 0;
++	}
++
++	if (ISP_ABS_TBL_REDGAMMA & isptables_struct->update) {
++		if (copy_from_user(redgamma_table, isptables_struct->red_gamma,
++				   sizeof(redgamma_table))) {
++			goto err_copy_from_user;
++		}
++		rg_update = 1;
++	} else
++		rg_update = 0;
++
++	if (ISP_ABS_TBL_GREENGAMMA & isptables_struct->update) {
++		if (copy_from_user(greengamma_table,
++				   isptables_struct->green_gamma,
++				   sizeof(greengamma_table)))
++			goto err_copy_from_user;
++		gg_update = 1;
++	} else
++		gg_update = 0;
++
++	if (ISP_ABS_TBL_BLUEGAMMA & isptables_struct->update) {
++		if (copy_from_user(bluegamma_table,
++				   isptables_struct->blue_gamma,
++				   sizeof(bluegamma_table))) {
++			goto err_copy_from_user;
++		}
++		bg_update = 1;
++	} else
++		bg_update = 0;
++
++	return 0;
++
++err_copy_from_user:
++	printk(KERN_ERR "Preview Tables:Copy From User Error\n");
++	return -EFAULT;
++}
++
++/**
++ * isppreview_config_shadow_registers - Program shadow registers for preview.
++ *
++ * Allows user to program shadow registers associated with preview module.
++ **/
++void isppreview_config_shadow_registers()
++{
++	u8 current_brightness_contrast;
++	int ctr, prv_disabled;
++
++	isppreview_query_brightness(&current_brightness_contrast);
++	if (current_brightness_contrast !=
++	    (ispprev_obj.brightness * ISPPRV_BRIGHT_UNITS)) {
++		DPRINTK_ISPPREV(" Changing Brightness level to %d\n",
++				ispprev_obj.brightness);
++		isppreview_config_brightness(ispprev_obj.brightness *
++					     ISPPRV_BRIGHT_UNITS);
++	}
++
++	isppreview_query_contrast(&current_brightness_contrast);
++	if (current_brightness_contrast !=
++	    (ispprev_obj.contrast * ISPPRV_CONTRAST_UNITS)) {
++		DPRINTK_ISPPREV(" Changing Contrast level to %d\n",
++				ispprev_obj.contrast);
++		isppreview_config_contrast(ispprev_obj.contrast *
++					   ISPPRV_CONTRAST_UNITS);
++	}
++	if (update_color_matrix) {
++		isppreview_config_rgb_to_ycbcr(flr_prev_csc[ispprev_obj.color]);
++		update_color_matrix = 0;
++	}
++	if (gg_update || rg_update || bg_update || nf_update) {
++		isppreview_enable(0);
++		prv_disabled = 1;
++	}
++
++	if (gg_update) {
++		isp_reg_writel(ISPPRV_TBL_ADDR_GREEN_G_START,
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
++
++		for (ctr = 0; ctr < ISP_GAMMA_TABLE_SIZE; ctr++) {
++			isp_reg_writel(greengamma_table[ctr],
++				       OMAP3_ISP_IOMEM_PREV,
++				       ISPPRV_SET_TBL_DATA);
++		}
++		gg_update = 0;
++	}
++
++	if (rg_update) {
++		isp_reg_writel(ISPPRV_TBL_ADDR_RED_G_START,
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
++
++		for (ctr = 0; ctr < ISP_GAMMA_TABLE_SIZE; ctr++) {
++			isp_reg_writel(redgamma_table[ctr],
++				       OMAP3_ISP_IOMEM_PREV,
++				       ISPPRV_SET_TBL_DATA);
++		}
++		rg_update = 0;
++	}
++
++	if (bg_update) {
++		isp_reg_writel(ISPPRV_TBL_ADDR_BLUE_G_START,
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
++
++		for (ctr = 0; ctr < ISP_GAMMA_TABLE_SIZE; ctr++) {
++			isp_reg_writel(bluegamma_table[ctr],
++				       OMAP3_ISP_IOMEM_PREV,
++				       ISPPRV_SET_TBL_DATA);
++		}
++		bg_update = 0;
++	}
++
++	if (nf_update && nf_enable) {
++		isp_reg_writel(0xC00,
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
++		isp_reg_writel(prev_nf_t.spread,
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_NF);
++		for (ctr = 0; ctr < ISPPRV_NF_TBL_SIZE; ctr++) {
++			isp_reg_writel(prev_nf_t.table[ctr],
++				       OMAP3_ISP_IOMEM_PREV,
++				       ISPPRV_SET_TBL_DATA);
++		}
++		isppreview_enable_noisefilter(1);
++		nf_update = 0;
++	}
++
++	if (~nf_update && nf_enable)
++		isppreview_enable_noisefilter(1);
++
++	if (nf_update && ~nf_enable)
++		isppreview_enable_noisefilter(0);
++
++	if (prv_disabled) {
++		isppreview_enable(1);
++		prv_disabled = 0;
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_config_shadow_registers);
++
++/**
++ * isppreview_request - Reserves the preview module.
++ *
++ * Returns 0 if successful, or -EBUSY if the module was already reserved.
++ **/
++int isppreview_request()
++{
++	mutex_lock(&ispprev_obj.ispprev_mutex);
++	if (ispprev_obj.prev_inuse) {
++		mutex_unlock(&ispprev_obj.ispprev_mutex);
++		printk(KERN_ERR "ISP_ERR : Preview Module Busy\n");
++		return -EBUSY;
++	}
++	ispprev_obj.prev_inuse = 1;
++	mutex_unlock(&ispprev_obj.ispprev_mutex);
++	isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, ISPCTRL_PREV_RAM_EN |
++		   ISPCTRL_PREV_CLK_EN |
++		   ISPCTRL_SBL_WR1_RAM_EN);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_request);
++
++/**
++ * isppreview_free - Frees the preview module.
++ *
++ * Returns 0 if successful, or -EINVAL if the module was already freed.
++ **/
++int isppreview_free()
++{
++	mutex_lock(&ispprev_obj.ispprev_mutex);
++	if (ispprev_obj.prev_inuse) {
++		ispprev_obj.prev_inuse = 0;
++		mutex_unlock(&ispprev_obj.ispprev_mutex);
++		isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
++			    ~(ISPCTRL_PREV_CLK_EN |
++			      ISPCTRL_PREV_RAM_EN |
++			      ISPCTRL_SBL_WR1_RAM_EN));
++		return 0;
++	} else {
++		mutex_unlock(&ispprev_obj.ispprev_mutex);
++		DPRINTK_ISPPREV("ISP_ERR : Preview Module already freed\n");
++		return -EINVAL;
++	}
++
++}
++EXPORT_SYMBOL_GPL(isppreview_free);
++
++/** isppreview_config_datapath - Specifies input and output modules for Preview
++ * @input: Indicates the module that gives the image to preview.
++ * @output: Indicates the module to which the preview outputs to.
++ *
++ * Configures the default configuration for the CCDC to work with.
++ *
++ * The valid values for the input are PRV_RAW_CCDC (0), PRV_RAW_MEM (1),
++ * PRV_RGBBAYERCFA (2), PRV_COMPCFA (3), PRV_CCDC_DRKF (4), PRV_OTHERS (5).
++ *
++ * The valid values for the output are PREVIEW_RSZ (0), PREVIEW_MEM (1).
++ *
++ * Returns 0 if successful, or -EINVAL if wrong input or output values are
++ * specified.
++ **/
++int isppreview_config_datapath(enum preview_input input,
++			       enum preview_output output)
++{
++	u32 pcr = 0;
++	u8 enable = 0;
++	struct prev_params *params = prev_config_params;
++	struct ispprev_yclimit yclimit;
++
++	pcr = isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++
++	switch (input) {
++	case PRV_RAW_CCDC:
++		pcr &= ~ISPPRV_PCR_SOURCE;
++		pcr &= ~ISPPRV_PCR_ONESHOT;
++		ispprev_obj.prev_inpfmt = PRV_RAW_CCDC;
++		break;
++	case PRV_RAW_MEM:
++		pcr |= ISPPRV_PCR_SOURCE;
++		pcr |= ISPPRV_PCR_ONESHOT;
++		ispprev_obj.prev_inpfmt = PRV_RAW_MEM;
++		break;
++	case PRV_CCDC_DRKF:
++		pcr |= ISPPRV_PCR_DRKFCAP;
++		pcr |= ISPPRV_PCR_ONESHOT;
++		ispprev_obj.prev_inpfmt = PRV_CCDC_DRKF;
++		break;
++	case PRV_COMPCFA:
++		ispprev_obj.prev_inpfmt = PRV_COMPCFA;
++		break;
++	case PRV_OTHERS:
++		ispprev_obj.prev_inpfmt = PRV_OTHERS;
++		break;
++	case PRV_RGBBAYERCFA:
++		ispprev_obj.prev_inpfmt = PRV_RGBBAYERCFA;
++		break;
++	default:
++		printk(KERN_ERR "ISP_ERR : Wrong Input\n");
++		return -EINVAL;
++	};
++
++	switch (output) {
++	case PREVIEW_RSZ:
++		pcr |= ISPPRV_PCR_RSZPORT;
++		pcr &= ~ISPPRV_PCR_SDRPORT;
++		break;
++	case PREVIEW_MEM:
++		pcr &= ~ISPPRV_PCR_RSZPORT;
++		pcr |= ISPPRV_PCR_SDRPORT;
++		break;
++	default:
++		printk(KERN_ERR "ISP_ERR : Wrong Output\n");
++		return -EINVAL;
++	}
++	ispprev_obj.prev_outfmt = output;
++
++	isp_reg_writel(pcr, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++
++	isppreview_config_ycpos(params->pix_fmt);
++
++	if (params->cfa.cfa_table != NULL)
++		isppreview_config_cfa(params->cfa);
++	if (params->csup.hypf_en == 1)
++		isppreview_config_chroma_suppression(params->csup);
++	if (params->ytable != NULL)
++		isppreview_config_luma_enhancement(params->ytable);
++
++	if (params->gtable.redtable != NULL)
++		isppreview_config_gammacorrn(params->gtable);
++
++	enable = (params->features & PREV_CFA) ? 1 : 0;
++	isppreview_enable_cfa(enable);
++
++	enable = (params->features & PREV_CHROMA_SUPPRESS) ? 1 : 0;
++	isppreview_enable_chroma_suppression(enable);
++
++	enable = (params->features & PREV_LUMA_ENHANCE) ? 1 : 0;
++	isppreview_enable_luma_enhancement(enable);
++
++	enable = (params->features & PREV_NOISE_FILTER) ? 1 : 0;
++	if (enable)
++		isppreview_config_noisefilter(params->nf);
++	isppreview_enable_noisefilter(enable);
++
++	enable = (params->features & PREV_DEFECT_COR) ? 1 : 0;
++	if (enable)
++		isppreview_config_dcor(params->dcor);
++	isppreview_enable_dcor(enable);
++
++	enable = (params->features & PREV_GAMMA_BYPASS) ? 1 : 0;
++	isppreview_enable_gammabypass(enable);
++
++	isppreview_config_whitebalance(params->wbal);
++	isppreview_config_blkadj(params->blk_adj);
++	isppreview_config_rgb_blending(params->rgb2rgb);
++	isppreview_config_rgb_to_ycbcr(params->rgb2ycbcr);
++
++	isppreview_config_contrast(params->contrast * ISPPRV_CONTRAST_UNITS);
++	isppreview_config_brightness(params->brightness * ISPPRV_BRIGHT_UNITS);
++
++	yclimit.minC = ISPPRV_YC_MIN;
++	yclimit.maxC = ISPPRV_YC_MAX;
++	yclimit.minY = ISPPRV_YC_MIN;
++	yclimit.maxY = ISPPRV_YC_MAX;
++	isppreview_config_yc_range(yclimit);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_config_datapath);
++
++/**
++ * isppreview_set_skip - Set the number of rows/columns that should be skipped.
++ *  h - Start Pixel Horizontal.
++ *  v - Start Line Vertical.
++ **/
++void isppreview_set_skip(u32 h, u32 v)
++{
++	ispprev_obj.sph = h;
++	ispprev_obj.slv = v;
++}
++EXPORT_SYMBOL_GPL(isppreview_set_skip);
++
++/**
++ * isppreview_config_ycpos - Configure byte layout of YUV image.
++ * @mode: Indicates the required byte layout.
++ **/
++void isppreview_config_ycpos(enum preview_ycpos_mode mode)
++{
++	u32 pcr = isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++	pcr &= ~ISPPRV_PCR_YCPOS_CrYCbY;
++	pcr |= (mode << ISPPRV_PCR_YCPOS_SHIFT);
++	isp_reg_writel(pcr, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_ycpos);
++
++/**
++ * isppreview_config_averager - Enable / disable / configure averager
++ * @average: Average value to be configured.
++ **/
++void isppreview_config_averager(u8 average)
++{
++	int reg = 0;
++
++	reg = AVE_ODD_PIXEL_DIST | AVE_EVEN_PIXEL_DIST | average;
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_PREV, ISPPRV_AVE);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_averager);
++
++/**
++ * isppreview_enable_invalaw - Enable/Disable Inverse A-Law module in Preview.
++ * @enable: 1 - Reverse the A-Law done in CCDC.
++ **/
++void isppreview_enable_invalaw(u8 enable)
++{
++	u32 pcr_val = 0;
++	pcr_val = isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++
++	if (enable) {
++		isp_reg_writel(pcr_val | ISPPRV_PCR_WIDTH | ISPPRV_PCR_INVALAW,
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++	} else {
++		isp_reg_writel(pcr_val &
++			       ~(ISPPRV_PCR_WIDTH | ISPPRV_PCR_INVALAW),
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_invalaw);
++
++/**
++ * isppreview_enable_drkframe - Enable/Disable of the darkframe subtract.
++ * @enable: 1 - Acquires memory bandwidth since the pixels in each frame is
++ *          subtracted with the pixels in the current frame.
++ *
++ * The proccess is applied for each captured frame.
++ **/
++void isppreview_enable_drkframe(u8 enable)
++{
++	if (enable)
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_DRKFEN);
++	else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_DRKFEN);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_drkframe);
++
++/**
++ * isppreview_enable_shadcomp - Enables/Disables the shading compensation.
++ * @enable: 1 - Enables the shading compensation.
++ *
++ * If dark frame subtract won't be used, then enable this shading
++ * compensation.
++ **/
++void isppreview_enable_shadcomp(u8 enable)
++{
++
++	if (enable) {
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			   ISPPRV_PCR_SCOMP_EN);
++		isppreview_enable_drkframe(1);
++	} else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_SCOMP_EN);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_shadcomp);
++
++/**
++ * isppreview_config_drkf_shadcomp - Configures shift value in shading comp.
++ * @scomp_shtval: 3bit value of shift used in shading compensation.
++ **/
++void isppreview_config_drkf_shadcomp(u8 scomp_shtval)
++{
++	u32 pcr_val = isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++
++	pcr_val &= ISPPRV_PCR_SCOMP_SFT_MASK;
++	isp_reg_writel(pcr_val | (scomp_shtval << ISPPRV_PCR_SCOMP_SFT_SHIFT),
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_drkf_shadcomp);
++
++/**
++ * isppreview_enable_hmed - Enables/Disables of the Horizontal Median Filter.
++ * @enable: 1 - Enables Horizontal Median Filter.
++ **/
++void isppreview_enable_hmed(u8 enable)
++{
++	if (enable)
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_HMEDEN);
++	else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_HMEDEN);
++	}
++	ispprev_obj.hmed_en = enable ? 1 : 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_hmed);
++
++/**
++ * isppreview_config_hmed - Configures the Horizontal Median Filter.
++ * @prev_hmed: Structure containing the odd and even distance between the
++ *             pixels in the image along with the filter threshold.
++ **/
++void isppreview_config_hmed(struct ispprev_hmed prev_hmed)
++{
++
++	u32 odddist = 0;
++	u32 evendist = 0;
++
++	if (prev_hmed.odddist == 1)
++		odddist = ~ISPPRV_HMED_ODDDIST;
++	else
++		odddist = ISPPRV_HMED_ODDDIST;
++
++	if (prev_hmed.evendist == 1)
++		evendist = ~ISPPRV_HMED_EVENDIST;
++	else
++		evendist = ISPPRV_HMED_EVENDIST;
++
++	isp_reg_writel(odddist | evendist | (prev_hmed.thres <<
++					     ISPPRV_HMED_THRESHOLD_SHIFT),
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_HMED);
++
++}
++EXPORT_SYMBOL_GPL(isppreview_config_hmed);
++
++/**
++ * isppreview_config_noisefilter - Configures the Noise Filter.
++ * @prev_nf: Structure containing the noisefilter table, strength to be used
++ *           for the noise filter and the defect correction enable flag.
++ **/
++void isppreview_config_noisefilter(struct ispprev_nf prev_nf)
++{
++	int i = 0;
++
++	isp_reg_writel(prev_nf.spread, OMAP3_ISP_IOMEM_PREV, ISPPRV_NF);
++	isp_reg_writel(ISPPRV_NF_TABLE_ADDR, OMAP3_ISP_IOMEM_PREV,
++		       ISPPRV_SET_TBL_ADDR);
++	for (i = 0; i < ISPPRV_NF_TBL_SIZE; i++) {
++		isp_reg_writel(prev_nf.table[i], OMAP3_ISP_IOMEM_PREV,
++			       ISPPRV_SET_TBL_DATA);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_config_noisefilter);
++
++/**
++ * isppreview_config_dcor - Configures the defect correction
++ * @prev_nf: Structure containing the defect correction structure
++ **/
++void isppreview_config_dcor(struct ispprev_dcor prev_dcor)
++{
++	if (prev_dcor.couplet_mode_en) {
++		isp_reg_writel(prev_dcor.detect_correct[0],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR0);
++		isp_reg_writel(prev_dcor.detect_correct[1],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR1);
++		isp_reg_writel(prev_dcor.detect_correct[2],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR2);
++		isp_reg_writel(prev_dcor.detect_correct[3],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR3);
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_DCCOUP);
++	} else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_DCCOUP);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_config_dcor);
++
++/**
++ * isppreview_config_cfa - Configures the CFA Interpolation parameters.
++ * @prev_cfa: Structure containing the CFA interpolation table, CFA format
++ *            in the image, vertical and horizontal gradient threshold.
++ **/
++void isppreview_config_cfa(struct ispprev_cfa prev_cfa)
++{
++	int i = 0;
++
++	ispprev_obj.cfafmt = prev_cfa.cfafmt;
++
++	isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++		   (prev_cfa.cfafmt << ISPPRV_PCR_CFAFMT_SHIFT));
++
++	isp_reg_writel(
++		(prev_cfa.cfa_gradthrs_vert << ISPPRV_CFA_GRADTH_VER_SHIFT) |
++		(prev_cfa.cfa_gradthrs_horz << ISPPRV_CFA_GRADTH_HOR_SHIFT),
++		OMAP3_ISP_IOMEM_PREV, ISPPRV_CFA);
++
++	isp_reg_writel(ISPPRV_CFA_TABLE_ADDR, OMAP3_ISP_IOMEM_PREV,
++		       ISPPRV_SET_TBL_ADDR);
++
++	for (i = 0; i < ISPPRV_CFA_TBL_SIZE; i++) {
++		isp_reg_writel(prev_cfa.cfa_table[i],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_config_cfa);
++
++/**
++ * isppreview_config_gammacorrn - Configures the Gamma Correction table values
++ * @gtable: Structure containing the table for red, blue, green gamma table.
++ **/
++void isppreview_config_gammacorrn(struct ispprev_gtable gtable)
++{
++	int i = 0;
++
++	isp_reg_writel(ISPPRV_REDGAMMA_TABLE_ADDR,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
++	for (i = 0; i < ISPPRV_GAMMA_TBL_SIZE; i++) {
++		isp_reg_writel(gtable.redtable[i],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
++	}
++
++	isp_reg_writel(ISPPRV_GREENGAMMA_TABLE_ADDR,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
++	for (i = 0; i < ISPPRV_GAMMA_TBL_SIZE; i++) {
++		isp_reg_writel(gtable.greentable[i],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
++	}
++
++	isp_reg_writel(ISPPRV_BLUEGAMMA_TABLE_ADDR,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
++	for (i = 0; i < ISPPRV_GAMMA_TBL_SIZE; i++) {
++		isp_reg_writel(gtable.bluetable[i],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_config_gammacorrn);
++
++/**
++ * isppreview_config_luma_enhancement - Sets the Luminance Enhancement table.
++ * @ytable: Structure containing the table for Luminance Enhancement table.
++ **/
++void isppreview_config_luma_enhancement(u32 *ytable)
++{
++	int i = 0;
++
++	isp_reg_writel(ISPPRV_YENH_TABLE_ADDR,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
++	for (i = 0; i < ISPPRV_YENH_TBL_SIZE; i++) {
++		isp_reg_writel(ytable[i],
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_config_luma_enhancement);
++
++/**
++ * isppreview_config_chroma_suppression - Configures the Chroma Suppression.
++ * @csup: Structure containing the threshold value for suppression
++ *        and the hypass filter enable flag.
++ **/
++void isppreview_config_chroma_suppression(struct ispprev_csup csup)
++{
++	isp_reg_writel(csup.gain | (csup.thres << ISPPRV_CSUP_THRES_SHIFT) |
++		       (csup.hypf_en << ISPPRV_CSUP_HPYF_SHIFT),
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_CSUP);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_chroma_suppression);
++
++/**
++ * isppreview_enable_noisefilter - Enables/Disables the Noise Filter.
++ * @enable: 1 - Enables the Noise Filter.
++ **/
++void isppreview_enable_noisefilter(u8 enable)
++{
++	if (enable)
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_NFEN);
++	else
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ~ISPPRV_PCR_NFEN);
++	ispprev_obj.nf_en = enable ? 1 : 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_noisefilter);
++
++/**
++ * isppreview_enable_dcor - Enables/Disables the defect correction.
++ * @enable: 1 - Enables the defect correction.
++ **/
++void isppreview_enable_dcor(u8 enable)
++{
++	if (enable)
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_DCOREN);
++	else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_DCOREN);
++	}
++	ispprev_obj.dcor_en = enable ? 1 : 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_dcor);
++
++/**
++ * isppreview_enable_cfa - Enable/Disable the CFA Interpolation.
++ * @enable: 1 - Enables the CFA.
++ **/
++void isppreview_enable_cfa(u8 enable)
++{
++	if (enable)
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_CFAEN);
++	else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_CFAEN);
++	}
++	ispprev_obj.cfa_en = enable ? 1 : 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_cfa);
++
++/**
++ * isppreview_enable_gammabypass - Enables/Disables the GammaByPass
++ * @enable: 1 - Bypasses Gamma - 10bit input is cropped to 8MSB.
++ *          0 - Goes through Gamma Correction. input and output is 10bit.
++ **/
++void isppreview_enable_gammabypass(u8 enable)
++{
++	if (enable) {
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			   ISPPRV_PCR_GAMMA_BYPASS);
++	} else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_GAMMA_BYPASS);
++	}
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_gammabypass);
++
++/**
++ * isppreview_enable_luma_enhancement - Enables/Disables Luminance Enhancement
++ * @enable: 1 - Enable the Luminance Enhancement.
++ **/
++void isppreview_enable_luma_enhancement(u8 enable)
++{
++	if (enable) {
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			   ISPPRV_PCR_YNENHEN);
++	} else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_YNENHEN);
++	}
++	ispprev_obj.yenh_en = enable ? 1 : 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_luma_enhancement);
++
++/**
++ * isppreview_enable_chroma_suppression - Enables/Disables Chrominance Suppr.
++ * @enable: 1 - Enable the Chrominance Suppression.
++ **/
++void isppreview_enable_chroma_suppression(u8 enable)
++{
++	if (enable)
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_SUPEN);
++	else {
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
++			    ~ISPPRV_PCR_SUPEN);
++	}
++	ispprev_obj.csup_en = enable ? 1 : 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_enable_chroma_suppression);
++
++/**
++ * isppreview_config_whitebalance - Configures the White Balance parameters.
++ * @prev_wbal: Structure containing the digital gain and white balance
++ *             coefficient.
++ *
++ * Coefficient matrix always with default values.
++ **/
++void isppreview_config_whitebalance(struct ispprev_wbal prev_wbal)
++{
++	u32 val;
++
++	isp_reg_writel(prev_wbal.dgain, OMAP3_ISP_IOMEM_PREV, ISPPRV_WB_DGAIN);
++
++	val = prev_wbal.coef0 << ISPPRV_WBGAIN_COEF0_SHIFT;
++	val |= prev_wbal.coef1 << ISPPRV_WBGAIN_COEF1_SHIFT;
++	val |= prev_wbal.coef2 << ISPPRV_WBGAIN_COEF2_SHIFT;
++	val |= prev_wbal.coef3 << ISPPRV_WBGAIN_COEF3_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN);
++
++	isp_reg_writel(ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_0_SHIFT |
++		       ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_1_SHIFT |
++		       ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_2_SHIFT |
++		       ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_3_SHIFT |
++		       ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_0_SHIFT |
++		       ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_1_SHIFT |
++		       ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_2_SHIFT |
++		       ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_3_SHIFT |
++		       ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_0_SHIFT |
++		       ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_1_SHIFT |
++		       ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_2_SHIFT |
++		       ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_3_SHIFT |
++		       ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_0_SHIFT |
++		       ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_1_SHIFT |
++		       ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_2_SHIFT |
++		       ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_3_SHIFT,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_WBSEL);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_whitebalance);
++
++/**
++ * isppreview_config_whitebalance2 - Configures the White Balance parameters.
++ * @prev_wbal: Structure containing the digital gain and white balance
++ *             coefficient.
++ *
++ * Coefficient matrix can be changed.
++ **/
++void isppreview_config_whitebalance2(struct prev_white_balance prev_wbal)
++{
++	isp_reg_writel(prev_wbal.wb_dgain,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_WB_DGAIN);
++	isp_reg_writel(prev_wbal.wb_gain[0] |
++		       prev_wbal.wb_gain[1] << ISPPRV_WBGAIN_COEF1_SHIFT |
++		       prev_wbal.wb_gain[2] << ISPPRV_WBGAIN_COEF2_SHIFT |
++		       prev_wbal.wb_gain[3] << ISPPRV_WBGAIN_COEF3_SHIFT,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN);
++
++	isp_reg_writel(
++		prev_wbal.wb_coefmatrix[0][0] << ISPPRV_WBSEL_N0_0_SHIFT |
++		prev_wbal.wb_coefmatrix[0][1] << ISPPRV_WBSEL_N0_1_SHIFT |
++		prev_wbal.wb_coefmatrix[0][2] << ISPPRV_WBSEL_N0_2_SHIFT |
++		prev_wbal.wb_coefmatrix[0][3] << ISPPRV_WBSEL_N0_3_SHIFT |
++		prev_wbal.wb_coefmatrix[1][0] << ISPPRV_WBSEL_N1_0_SHIFT |
++		prev_wbal.wb_coefmatrix[1][1] << ISPPRV_WBSEL_N1_1_SHIFT |
++		prev_wbal.wb_coefmatrix[1][2] << ISPPRV_WBSEL_N1_2_SHIFT |
++		prev_wbal.wb_coefmatrix[1][3] << ISPPRV_WBSEL_N1_3_SHIFT |
++		prev_wbal.wb_coefmatrix[2][0] << ISPPRV_WBSEL_N2_0_SHIFT |
++		prev_wbal.wb_coefmatrix[2][1] << ISPPRV_WBSEL_N2_1_SHIFT |
++		prev_wbal.wb_coefmatrix[2][2] << ISPPRV_WBSEL_N2_2_SHIFT |
++		prev_wbal.wb_coefmatrix[2][3] << ISPPRV_WBSEL_N2_3_SHIFT |
++		prev_wbal.wb_coefmatrix[3][0] << ISPPRV_WBSEL_N3_0_SHIFT |
++		prev_wbal.wb_coefmatrix[3][1] << ISPPRV_WBSEL_N3_1_SHIFT |
++		prev_wbal.wb_coefmatrix[3][2] << ISPPRV_WBSEL_N3_2_SHIFT |
++		prev_wbal.wb_coefmatrix[3][3] << ISPPRV_WBSEL_N3_3_SHIFT,
++		OMAP3_ISP_IOMEM_PREV, ISPPRV_WBSEL);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_whitebalance2);
++
++/**
++ * isppreview_config_blkadj - Configures the Black Adjustment parameters.
++ * @prev_blkadj: Structure containing the black adjustment towards red, green,
++ *               blue.
++ **/
++void isppreview_config_blkadj(struct ispprev_blkadj prev_blkadj)
++{
++	isp_reg_writel(prev_blkadj.blue |
++		       (prev_blkadj.green << ISPPRV_BLKADJOFF_G_SHIFT) |
++		       (prev_blkadj.red << ISPPRV_BLKADJOFF_R_SHIFT),
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_BLKADJOFF);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_blkadj);
++
++/**
++ * isppreview_config_rgb_blending - Configures the RGB-RGB Blending matrix.
++ * @rgb2rgb: Structure containing the rgb to rgb blending matrix and the rgb
++ *           offset.
++ **/
++void isppreview_config_rgb_blending(struct ispprev_rgbtorgb rgb2rgb)
++{
++	u32 val = 0;
++
++	val = (rgb2rgb.matrix[0][0] & 0xfff) << ISPPRV_RGB_MAT1_MTX_RR_SHIFT;
++	val |= (rgb2rgb.matrix[0][1] & 0xfff) << ISPPRV_RGB_MAT1_MTX_GR_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT1);
++
++	val = (rgb2rgb.matrix[0][2] & 0xfff) << ISPPRV_RGB_MAT2_MTX_BR_SHIFT;
++	val |= (rgb2rgb.matrix[1][0] & 0xfff) << ISPPRV_RGB_MAT2_MTX_RG_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT2);
++
++	val = (rgb2rgb.matrix[1][1] & 0xfff) << ISPPRV_RGB_MAT3_MTX_GG_SHIFT;
++	val |= (rgb2rgb.matrix[1][2] & 0xfff) << ISPPRV_RGB_MAT3_MTX_BG_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT3);
++
++	val = (rgb2rgb.matrix[2][0] & 0xfff) << ISPPRV_RGB_MAT4_MTX_RB_SHIFT;
++	val |= (rgb2rgb.matrix[2][1] & 0xfff) << ISPPRV_RGB_MAT4_MTX_GB_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT4);
++
++	val = (rgb2rgb.matrix[2][2] & 0xfff) << ISPPRV_RGB_MAT5_MTX_BB_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT5);
++
++	val = (rgb2rgb.offset[0] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT;
++	val |= (rgb2rgb.offset[1] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF1);
++
++	val = (rgb2rgb.offset[2] & 0x3ff) << ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF2);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_rgb_blending);
++
++/**
++ * Configures the RGB-YCbYCr conversion matrix
++ * @prev_csc: Structure containing the RGB to YCbYCr matrix and the
++ *            YCbCr offset.
++ **/
++void isppreview_config_rgb_to_ycbcr(struct ispprev_csc prev_csc)
++{
++	u32 val = 0;
++
++	val = (prev_csc.matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT;
++	val |= (prev_csc.matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT;
++	val |= (prev_csc.matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC0);
++
++	val = (prev_csc.matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT;
++	val |= (prev_csc.matrix[1][1] & 0x3ff) << ISPPRV_CSC1_GCB_SHIFT;
++	val |= (prev_csc.matrix[1][2] & 0x3ff) << ISPPRV_CSC1_BCB_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC1);
++
++	val = (prev_csc.matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT;
++	val |= (prev_csc.matrix[2][1] & 0x3ff) << ISPPRV_CSC2_GCR_SHIFT;
++	val |= (prev_csc.matrix[2][2] & 0x3ff) << ISPPRV_CSC2_BCR_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC2);
++
++	val = (prev_csc.offset[0] & 0xff) << ISPPRV_CSC_OFFSET_CR_SHIFT;
++	val |= (prev_csc.offset[1] & 0xff) << ISPPRV_CSC_OFFSET_CB_SHIFT;
++	val |= (prev_csc.offset[2] & 0xff) << ISPPRV_CSC_OFFSET_Y_SHIFT;
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC_OFFSET);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_rgb_to_ycbcr);
++
++/**
++ * isppreview_query_contrast - Query the contrast.
++ * @contrast: Pointer to hold the current programmed contrast value.
++ **/
++void isppreview_query_contrast(u8 *contrast)
++{
++	u32 brt_cnt_val = 0;
++
++	brt_cnt_val = isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT);
++	*contrast = (brt_cnt_val >> ISPPRV_CNT_BRT_CNT_SHIFT) & 0xff;
++	DPRINTK_ISPPREV(" Current brt cnt value in hw is %x\n", brt_cnt_val);
++}
++EXPORT_SYMBOL_GPL(isppreview_query_contrast);
++
++/**
++ * isppreview_update_contrast - Updates the contrast.
++ * @contrast: Pointer to hold the current programmed contrast value.
++ *
++ * Value should be programmed before enabling the module.
++ **/
++void isppreview_update_contrast(u8 *contrast)
++{
++	ispprev_obj.contrast = *contrast;
++}
++EXPORT_SYMBOL_GPL(isppreview_update_contrast);
++
++/**
++ * isppreview_config_contrast - Configures the Contrast.
++ * @contrast: 8 bit value in U8Q4 format.
++ *
++ * Value should be programmed before enabling the module.
++ **/
++void isppreview_config_contrast(u8 contrast)
++{
++	u32 brt_cnt_val = 0;
++
++	brt_cnt_val = isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT);
++	brt_cnt_val &= ~(0xff << ISPPRV_CNT_BRT_CNT_SHIFT);
++	contrast &= 0xff;
++	isp_reg_writel(brt_cnt_val | contrast << ISPPRV_CNT_BRT_CNT_SHIFT,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_contrast);
++
++/**
++ * isppreview_get_contrast_range - Gets the range contrast value.
++ * @min_contrast: Pointer to hold the minimum Contrast value.
++ * @max_contrast: Pointer to hold the maximum Contrast value.
++ **/
++void isppreview_get_contrast_range(u8 *min_contrast, u8 *max_contrast)
++{
++	*min_contrast = ISPPRV_CONTRAST_MIN;
++	*max_contrast = ISPPRV_CONTRAST_MAX;
++}
++EXPORT_SYMBOL_GPL(isppreview_get_contrast_range);
++
++/**
++ * isppreview_update_brightness - Updates the brightness in preview module.
++ * @brightness: Pointer to hold the current programmed brightness value.
++ *
++ **/
++void isppreview_update_brightness(u8 *brightness)
++{
++	ispprev_obj.brightness = *brightness;
++}
++EXPORT_SYMBOL_GPL(isppreview_update_brightness);
++
++/**
++ * isppreview_config_brightness - Configures the brightness.
++ * @contrast: 8bitvalue in U8Q0 format.
++ **/
++void isppreview_config_brightness(u8 brightness)
++{
++	u32 brt_cnt_val = 0;
++
++	DPRINTK_ISPPREV("\tConfiguring brightness in ISP: %d\n", brightness);
++	brt_cnt_val = isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT);
++	brt_cnt_val &= ~(0xff << ISPPRV_CNT_BRT_BRT_SHIFT);
++	brightness &= 0xff;
++	isp_reg_writel(brt_cnt_val | brightness << ISPPRV_CNT_BRT_BRT_SHIFT,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_brightness);
++
++/**
++ * isppreview_query_brightness - Query the brightness.
++ * @brightness: Pointer to hold the current programmed brightness value.
++ **/
++void isppreview_query_brightness(u8 *brightness)
++{
++	*brightness = isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT);
++}
++EXPORT_SYMBOL_GPL(isppreview_query_brightness);
++
++/**
++ * isppreview_get_brightness_range - Gets the range brightness value
++ * @min_brightness: Pointer to hold the minimum brightness value
++ * @max_brightness: Pointer to hold the maximum brightness value
++ **/
++void isppreview_get_brightness_range(u8 *min_brightness, u8 *max_brightness)
++{
++	*min_brightness = ISPPRV_BRIGHT_MIN;
++	*max_brightness = ISPPRV_BRIGHT_MAX;
++}
++EXPORT_SYMBOL_GPL(isppreview_get_brightness_range);
++
++/**
++ * isppreview_set_color - Sets the color effect.
++ * @mode: Indicates the required color effect.
++ **/
++void isppreview_set_color(u8 *mode)
++{
++	ispprev_obj.color = *mode;
++	update_color_matrix = 1;
++}
++EXPORT_SYMBOL_GPL(isppreview_set_color);
++
++/**
++ * isppreview_get_color - Gets the current color effect.
++ * @mode: Indicates the current color effect.
++ **/
++void isppreview_get_color(u8 *mode)
++{
++	*mode = ispprev_obj.color;
++}
++EXPORT_SYMBOL_GPL(isppreview_get_color);
++
++/**
++ * isppreview_config_yc_range - Configures the max and min Y and C values.
++ * @yclimit: Structure containing the range of Y and C values.
++ **/
++void isppreview_config_yc_range(struct ispprev_yclimit yclimit)
++{
++	isp_reg_writel(yclimit.maxC << ISPPRV_SETUP_YC_MAXC_SHIFT |
++		       yclimit.maxY << ISPPRV_SETUP_YC_MAXY_SHIFT |
++		       yclimit.minC << ISPPRV_SETUP_YC_MINC_SHIFT |
++		       yclimit.minY << ISPPRV_SETUP_YC_MINY_SHIFT,
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_SETUP_YC);
++}
++EXPORT_SYMBOL_GPL(isppreview_config_yc_range);
++
++/**
++ * isppreview_try_size - Calculates output dimensions with the modules enabled.
++ * @input_w: input width for the preview in number of pixels per line
++ * @input_h: input height for the preview in number of lines
++ * @output_w: output width from the preview in number of pixels per line
++ * @output_h: output height for the preview in number of lines
++ *
++ * Calculates the number of pixels cropped in the submodules that are enabled,
++ * Fills up the output width height variables in the isp_prev structure.
++ **/
++int isppreview_try_size(u32 input_w, u32 input_h, u32 *output_w, u32 *output_h)
++{
++	u32 prevout_w = input_w;
++	u32 prevout_h = input_h;
++	u32 div = 0;
++	int max_out;
++
++	ispprev_obj.previn_w = input_w;
++	ispprev_obj.previn_h = input_h;
++
++	if (input_w < 32 || input_h < 32) {
++		printk(KERN_ERR "ISP_ERR : preview does not support "
++		       "width < 16 or height < 32 \n");
++		return -EINVAL;
++	}
++	if (omap_rev() == OMAP3430_REV_ES1_0)
++		max_out = ISPPRV_MAXOUTPUT_WIDTH;
++	else
++		max_out = ISPPRV_MAXOUTPUT_WIDTH_ES2;
++
++	ispprev_obj.fmtavg = 0;
++
++	if (input_w > max_out) {
++		div = (input_w/max_out);
++		if (div >= 2 && div < 4) {
++			ispprev_obj.fmtavg = 1;
++			prevout_w /= 2;
++		} else if (div >= 4 && div < 8) {
++			ispprev_obj.fmtavg = 2;
++			prevout_w /= 4;
++		} else if (div >= 8) {
++			ispprev_obj.fmtavg = 3;
++			prevout_w /= 8;
++		}
++	}
++
++	if (ispprev_obj.hmed_en)
++		prevout_w -= 4;
++	if (ispprev_obj.nf_en) {
++		prevout_w -= 4;
++		prevout_h -= 4;
++	}
++	if (ispprev_obj.cfa_en) {
++		switch (ispprev_obj.cfafmt) {
++		case CFAFMT_BAYER:
++		case CFAFMT_SONYVGA:
++			prevout_w -= 4;
++			prevout_h -= 4;
++			break;
++		case CFAFMT_RGBFOVEON:
++		case CFAFMT_RRGGBBFOVEON:
++		case CFAFMT_DNSPL:
++		case CFAFMT_HONEYCOMB:
++			prevout_h -= 2;
++			break;
++		};
++	}
++	if (ispprev_obj.yenh_en || ispprev_obj.csup_en)
++		prevout_w -= 2;
++
++	/* Start at the correct row/column by skipping
++	 * a Sensor specific amount.
++	 */
++	prevout_w -= ispprev_obj.sph;
++	prevout_h -= ispprev_obj.slv;
++
++
++	if (prevout_w % 2)
++		prevout_w -= 1;
++
++	if (ispprev_obj.prev_outfmt == PREVIEW_MEM) {
++		if (((prevout_w * 2) & ISP_32B_BOUNDARY_OFFSET) !=
++		    (prevout_w * 2)) {
++			prevout_w = ((prevout_w * 2) &
++				     ISP_32B_BOUNDARY_OFFSET) / 2;
++		}
++	}
++	*output_w = prevout_w;
++	ispprev_obj.prevout_w = prevout_w;
++	*output_h = prevout_h;
++	ispprev_obj.prevout_h = prevout_h;
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_try_size);
++
++/**
++ * isppreview_config_size - Sets the size of ISP preview output.
++ * @input_w: input width for the preview in number of pixels per line
++ * @input_h: input height for the preview in number of lines
++ * @output_w: output width from the preview in number of pixels per line
++ * @output_h: output height for the preview in number of lines
++ *
++ * Configures the appropriate values stored in the isp_prev structure to
++ * HORZ/VERT_INFO. Configures PRV_AVE if needed for downsampling as calculated
++ * in trysize.
++ **/
++int isppreview_config_size(u32 input_w, u32 input_h, u32 output_w, u32 output_h)
++{
++	u32 prevsdroff;
++
++	if ((output_w != ispprev_obj.prevout_w) ||
++	    (output_h != ispprev_obj.prevout_h)) {
++		printk(KERN_ERR "ISP_ERR : isppreview_try_size should "
++		       "be called before config size\n");
++		return -EINVAL;
++	}
++
++	isp_reg_writel((ispprev_obj.sph << ISPPRV_HORZ_INFO_SPH_SHIFT) |
++		       (ispprev_obj.previn_w - 1),
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_HORZ_INFO);
++	isp_reg_writel((ispprev_obj.slv << ISPPRV_VERT_INFO_SLV_SHIFT) |
++		       (ispprev_obj.previn_h - 2),
++		       OMAP3_ISP_IOMEM_PREV, ISPPRV_VERT_INFO);
++
++	if (ispprev_obj.cfafmt == CFAFMT_BAYER)
++		isp_reg_writel(ISPPRV_AVE_EVENDIST_2 <<
++			       ISPPRV_AVE_EVENDIST_SHIFT |
++			       ISPPRV_AVE_ODDDIST_2 <<
++			       ISPPRV_AVE_ODDDIST_SHIFT |
++			       ispprev_obj.fmtavg,
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_AVE);
++
++	if (ispprev_obj.prev_outfmt == PREVIEW_MEM) {
++		prevsdroff = ispprev_obj.prevout_w * 2;
++		if ((prevsdroff & ISP_32B_BOUNDARY_OFFSET) != prevsdroff) {
++			DPRINTK_ISPPREV("ISP_WARN: Preview output buffer line"
++					" size is truncated"
++					" to 32byte boundary\n");
++			prevsdroff &= ISP_32B_BOUNDARY_BUF ;
++		}
++		isppreview_config_outlineoffset(prevsdroff);
++	}
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_config_size);
++
++/**
++ * isppreview_config_inlineoffset - Configures the Read address line offset.
++ * @offset: Line Offset for the input image.
++ **/
++int isppreview_config_inlineoffset(u32 offset)
++{
++	if ((offset & ISP_32B_BOUNDARY_OFFSET) == offset) {
++		isp_reg_writel(offset & 0xffff,
++			       OMAP3_ISP_IOMEM_PREV, ISPPRV_RADR_OFFSET);
++	} else {
++		printk(KERN_ERR "ISP_ERR : Offset should be in 32 byte "
++		       "boundary\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_config_inlineoffset);
++
++/**
++ * isppreview_set_inaddr - Sets memory address of input frame.
++ * @addr: 32bit memory address aligned on 32byte boundary.
++ *
++ * Configures the memory address from which the input frame is to be read.
++ **/
++int isppreview_set_inaddr(u32 addr)
++{
++	if ((addr & ISP_32B_BOUNDARY_BUF) == addr)
++		isp_reg_writel(addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_RSDR_ADDR);
++	else {
++		printk(KERN_ERR "ISP_ERR: Address should be in 32 byte "
++		       "boundary\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_set_inaddr);
++
++/**
++ * isppreview_config_outlineoffset - Configures the Write address line offset.
++ * @offset: Line Offset for the preview output.
++ **/
++int isppreview_config_outlineoffset(u32 offset)
++{
++	if ((offset & ISP_32B_BOUNDARY_OFFSET) != offset) {
++		printk(KERN_ERR "ISP_ERR : Offset should be in 32 byte "
++		       "boundary\n");
++		return -EINVAL;
++	}
++	isp_reg_writel(offset & 0xffff, OMAP3_ISP_IOMEM_PREV,
++		       ISPPRV_WADD_OFFSET);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_config_outlineoffset);
++
++/**
++ * isppreview_set_outaddr - Sets the memory address to store output frame
++ * @addr: 32bit memory address aligned on 32byte boundary.
++ *
++ * Configures the memory address to which the output frame is written.
++ **/
++int isppreview_set_outaddr(u32 addr)
++{
++	if ((addr & ISP_32B_BOUNDARY_BUF) != addr) {
++		printk(KERN_ERR "ISP_ERR: Address should be in 32 byte "
++		       "boundary\n");
++		return -EINVAL;
++	}
++	isp_reg_writel(addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_WSDR_ADDR);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_set_outaddr);
++
++/**
++ * isppreview_config_darklineoffset - Sets the Dark frame address line offset.
++ * @offset: Line Offset for the Darkframe.
++ **/
++int isppreview_config_darklineoffset(u32 offset)
++{
++	if ((offset & ISP_32B_BOUNDARY_OFFSET) != offset) {
++		printk(KERN_ERR "ISP_ERR : Offset should be in 32 byte "
++		       "boundary\n");
++		return -EINVAL;
++	}
++	isp_reg_writel(offset & 0xffff, OMAP3_ISP_IOMEM_PREV,
++		       ISPPRV_DRKF_OFFSET);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_config_darklineoffset);
++
++/**
++ * isppreview_set_darkaddr - Sets the memory address to store Dark frame.
++ * @addr: 32bit memory address aligned on 32 bit boundary.
++ **/
++int isppreview_set_darkaddr(u32 addr)
++{
++	if ((addr & ISP_32B_BOUNDARY_BUF) != addr) {
++		printk(KERN_ERR "ISP_ERR : Address should be in 32 byte "
++		       "boundary\n");
++		return -EINVAL;
++	}
++	isp_reg_writel(addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_DSDR_ADDR);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(isppreview_set_darkaddr);
++
++void __isppreview_enable(int enable)
++{
++	if (enable)
++		isp_reg_or(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_EN);
++	else
++		isp_reg_and(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ~ISPPRV_PCR_EN);
++}
++
++/**
++ * isppreview_enable - Enables the Preview module.
++ * @enable: 1 - Enables the preview module.
++ *
++ * Client should configure all the sub modules in Preview before this.
++ **/
++void isppreview_enable(int enable)
++{
++	__isppreview_enable(enable);
++	ispprev_obj.pm_state = enable;
++}
++EXPORT_SYMBOL_GPL(isppreview_enable);
++
++/**
++ * isppreview_suspend - Suspend Preview module.
++ **/
++void isppreview_suspend(void)
++{
++	if (ispprev_obj.pm_state)
++		__isppreview_enable(0);
++}
++EXPORT_SYMBOL_GPL(isppreview_suspend);
++
++/**
++ * isppreview_resume - Resume Preview module.
++ **/
++void isppreview_resume(void)
++{
++	if (ispprev_obj.pm_state)
++		__isppreview_enable(1);
++}
++EXPORT_SYMBOL_GPL(isppreview_resume);
++
++
++/**
++ * isppreview_busy - Gets busy state of preview module.
++ **/
++int isppreview_busy(void)
++{
++	return isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR) &
++		ISPPRV_PCR_BUSY;
++}
++EXPORT_SYMBOL_GPL(isppreview_busy);
++
++/**
++ * isppreview_get_config - Gets parameters of preview module.
++ **/
++struct prev_params *isppreview_get_config(void)
++{
++	return prev_config_params;
++}
++EXPORT_SYMBOL_GPL(isppreview_get_config);
++
++/**
++ * isppreview_save_context - Saves the values of the preview module registers.
++ **/
++void isppreview_save_context(void)
++{
++	DPRINTK_ISPPREV("Saving context\n");
++	isp_save_context(ispprev_reg_list);
++}
++EXPORT_SYMBOL_GPL(isppreview_save_context);
++
++/**
++ * isppreview_restore_context - Restores the values of preview module registers
++ **/
++void isppreview_restore_context(void)
++{
++	DPRINTK_ISPPREV("Restoring context\n");
++	isp_restore_context(ispprev_reg_list);
++}
++EXPORT_SYMBOL_GPL(isppreview_restore_context);
++
++/**
++ * isppreview_print_status - Prints the values of the Preview Module registers.
++ *
++ * Also prints other debug information stored in the preview moduel.
++ **/
++void isppreview_print_status(void)
++{
++	DPRINTK_ISPPREV("Module in use =%d\n", ispprev_obj.prev_inuse);
++	DPRINTK_ISPPREV("Preview Input format =%d, Output Format =%d\n",
++			ispprev_obj.prev_inpfmt,
++			ispprev_obj.prev_outfmt);
++	DPRINTK_ISPPREV("Accepted Preview Input (width = %d,Height = %d)\n",
++			ispprev_obj.previn_w,
++			ispprev_obj.previn_h);
++	DPRINTK_ISPPREV("Accepted Preview Output (width = %d,Height = %d)\n",
++			ispprev_obj.prevout_w,
++			ispprev_obj.prevout_h);
++	DPRINTK_ISPPREV("###ISP_CTRL in preview =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL));
++	DPRINTK_ISPPREV("###ISP_IRQ0ENABLE in preview =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE));
++	DPRINTK_ISPPREV("###ISP_IRQ0STATUS in preview =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS));
++	DPRINTK_ISPPREV("###PRV PCR =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR));
++	DPRINTK_ISPPREV("###PRV HORZ_INFO =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_HORZ_INFO));
++	DPRINTK_ISPPREV("###PRV VERT_INFO =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_VERT_INFO));
++	DPRINTK_ISPPREV("###PRV WSDR_ADDR =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_WSDR_ADDR));
++	DPRINTK_ISPPREV("###PRV WADD_OFFSET =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV,
++				      ISPPRV_WADD_OFFSET));
++	DPRINTK_ISPPREV("###PRV AVE =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_AVE));
++	DPRINTK_ISPPREV("###PRV HMED =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_HMED));
++	DPRINTK_ISPPREV("###PRV NF =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_NF));
++	DPRINTK_ISPPREV("###PRV WB_DGAIN =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_WB_DGAIN));
++	DPRINTK_ISPPREV("###PRV WBGAIN =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN));
++	DPRINTK_ISPPREV("###PRV WBSEL =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_WBSEL));
++	DPRINTK_ISPPREV("###PRV CFA =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CFA));
++	DPRINTK_ISPPREV("###PRV BLKADJOFF =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_BLKADJOFF));
++	DPRINTK_ISPPREV("###PRV RGB_MAT1 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT1));
++	DPRINTK_ISPPREV("###PRV RGB_MAT2 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT2));
++	DPRINTK_ISPPREV("###PRV RGB_MAT3 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT3));
++	DPRINTK_ISPPREV("###PRV RGB_MAT4 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT4));
++	DPRINTK_ISPPREV("###PRV RGB_MAT5 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT5));
++	DPRINTK_ISPPREV("###PRV RGB_OFF1 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF1));
++	DPRINTK_ISPPREV("###PRV RGB_OFF2 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF2));
++	DPRINTK_ISPPREV("###PRV CSC0 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC0));
++	DPRINTK_ISPPREV("###PRV CSC1 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC1));
++	DPRINTK_ISPPREV("###PRV CSC2 =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC2));
++	DPRINTK_ISPPREV("###PRV CSC_OFFSET =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC_OFFSET));
++	DPRINTK_ISPPREV("###PRV CNT_BRT =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT));
++	DPRINTK_ISPPREV("###PRV CSUP =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_CSUP));
++	DPRINTK_ISPPREV("###PRV SETUP_YC =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_PREV, ISPPRV_SETUP_YC));
++}
++EXPORT_SYMBOL_GPL(isppreview_print_status);
++
++/**
++ * isp_preview_init - Module Initialization.
++ **/
++int __init isp_preview_init(void)
++{
++	int i = 0;
++
++	prev_config_params = kmalloc(sizeof(*prev_config_params), GFP_KERNEL);
++	if (!prev_config_params) {
++		printk(KERN_ERR "Can't get memory for isp_preview params!\n");
++		return -ENOMEM;
++	}
++	params = prev_config_params;
++
++	ispprev_obj.prev_inuse = 0;
++	mutex_init(&ispprev_obj.ispprev_mutex);
++
++	/* Init values */
++	ispprev_obj.sph = 2;
++	ispprev_obj.slv = 0;
++	ispprev_obj.color = V4L2_COLORFX_NONE;
++	ispprev_obj.contrast = ISPPRV_CONTRAST_DEF;
++	params->contrast = ISPPRV_CONTRAST_DEF;
++	ispprev_obj.brightness = ISPPRV_BRIGHT_DEF;
++	params->brightness = ISPPRV_BRIGHT_DEF;
++	params->average = NO_AVE;
++	params->lens_shading_shift = 0;
++	params->pix_fmt = YCPOS_YCrYCb;
++	params->cfa.cfafmt = CFAFMT_BAYER;
++	params->cfa.cfa_table = cfa_coef_table;
++	params->cfa.cfa_gradthrs_horz = FLR_CFA_GRADTHRS_HORZ;
++	params->cfa.cfa_gradthrs_vert = FLR_CFA_GRADTHRS_VERT;
++	params->csup.gain = FLR_CSUP_GAIN;
++	params->csup.thres = FLR_CSUP_THRES;
++	params->csup.hypf_en = 0;
++	params->ytable = luma_enhance_table;
++	params->nf.spread = FLR_NF_STRGTH;
++	memcpy(params->nf.table, noise_filter_table, sizeof(params->nf.table));
++	params->dcor.couplet_mode_en = 1;
++	for (i = 0; i < 4; i++)
++		params->dcor.detect_correct[i] = 0xE;
++	params->gtable.bluetable = bluegamma_table;
++	params->gtable.greentable = greengamma_table;
++	params->gtable.redtable = redgamma_table;
++	params->wbal.dgain = FLR_WBAL_DGAIN;
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		params->wbal.coef0 = FLR_WBAL_COEF0_ES1;
++		params->wbal.coef1 = FLR_WBAL_COEF1_ES1;
++		params->wbal.coef2 = FLR_WBAL_COEF2_ES1;
++		params->wbal.coef3 = FLR_WBAL_COEF3_ES1;
++	} else {
++		params->wbal.coef0 = FLR_WBAL_COEF0;
++		params->wbal.coef1 = FLR_WBAL_COEF1;
++		params->wbal.coef2 = FLR_WBAL_COEF2;
++		params->wbal.coef3 = FLR_WBAL_COEF3;
++	}
++	params->blk_adj.red = FLR_BLKADJ_RED;
++	params->blk_adj.green = FLR_BLKADJ_GREEN;
++	params->blk_adj.blue = FLR_BLKADJ_BLUE;
++	params->rgb2rgb = flr_rgb2rgb;
++	params->rgb2ycbcr = flr_prev_csc[ispprev_obj.color];
++
++	params->features = PREV_CFA | PREV_DEFECT_COR | PREV_NOISE_FILTER;
++	params->features &= ~(PREV_AVERAGER | PREV_INVERSE_ALAW |
++			      PREV_HORZ_MEDIAN_FILTER |
++			      PREV_GAMMA_BYPASS |
++			      PREV_DARK_FRAME_SUBTRACT |
++			      PREV_LENS_SHADING |
++			      PREV_DARK_FRAME_CAPTURE |
++			      PREV_CHROMA_SUPPRESS |
++			      PREV_LUMA_ENHANCE);
++	return 0;
++}
++
++/**
++ * isp_preview_cleanup - Module Cleanup.
++ **/
++void isp_preview_cleanup(void)
++{
++	kfree(prev_config_params);
++}
+diff --git a/drivers/media/video/isp/isppreview.h b/drivers/media/video/isp/isppreview.h
+new file mode 100644
+index 0000000..e88c329
+--- /dev/null
++++ b/drivers/media/video/isp/isppreview.h
+@@ -0,0 +1,354 @@
++/*
++ * isppreview.h
++ *
++ * Driver header file for Preview module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Senthilvadivu Guruswamy <svadivu@ti.com>
++ *	Pallavi Kulkarni <p-kulkarni@ti.com>
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_PREVIEW_H
++#define OMAP_ISP_PREVIEW_H
++
++#include <mach/isp_user.h>
++/* Isp query control structure */
++
++#define ISPPRV_BRIGHT_STEP		0x1
++#define ISPPRV_BRIGHT_DEF		0x0
++#define ISPPRV_BRIGHT_LOW		0x0
++#define ISPPRV_BRIGHT_HIGH		0xF
++#define ISPPRV_BRIGHT_UNITS		0x7
++
++#define ISPPRV_CONTRAST_STEP		0x1
++#define ISPPRV_CONTRAST_DEF		0x4
++#define ISPPRV_CONTRAST_LOW		0x0
++#define ISPPRV_CONTRAST_HIGH		0xF
++#define ISPPRV_CONTRAST_UNITS		0x4
++
++#define NO_AVE				0x0
++#define AVE_2_PIX			0x1
++#define AVE_4_PIX			0x2
++#define AVE_8_PIX			0x3
++#define AVE_ODD_PIXEL_DIST		(1 << 4) /* For Bayer Sensors */
++#define AVE_EVEN_PIXEL_DIST		(1 << 2)
++
++#define WB_GAIN_MAX			4
++
++/* Features list */
++#define PREV_AVERAGER			(1 << 0)
++#define PREV_INVERSE_ALAW 		(1 << 1)
++#define PREV_HORZ_MEDIAN_FILTER		(1 << 2)
++#define PREV_NOISE_FILTER 		(1 << 3)
++#define PREV_CFA			(1 << 4)
++#define PREV_GAMMA_BYPASS		(1 << 5)
++#define PREV_LUMA_ENHANCE		(1 << 6)
++#define PREV_CHROMA_SUPPRESS		(1 << 7)
++#define PREV_DARK_FRAME_SUBTRACT	(1 << 8)
++#define PREV_LENS_SHADING		(1 << 9)
++#define PREV_DARK_FRAME_CAPTURE		(1 << 10)
++#define PREV_DEFECT_COR			(1 << 11)
++
++
++#define ISP_NF_TABLE_SIZE 		(1 << 10)
++
++#define ISP_GAMMA_TABLE_SIZE 		(1 << 10)
++
++/* Table addresses */
++#define ISPPRV_TBL_ADDR_RED_G_START  0x00
++#define ISPPRV_TBL_ADDR_BLUE_G_START  0x800
++#define ISPPRV_TBL_ADDR_GREEN_G_START  0x400
++
++/*
++ *Enumeration Constants for input and output format
++ */
++enum preview_input {
++	PRV_RAW_CCDC,
++	PRV_RAW_MEM,
++	PRV_RGBBAYERCFA,
++	PRV_COMPCFA,
++	PRV_CCDC_DRKF,
++	PRV_OTHERS
++};
++enum preview_output {
++	PREVIEW_RSZ,
++	PREVIEW_MEM
++};
++/*
++ * Configure byte layout of YUV image
++ */
++enum preview_ycpos_mode {
++	YCPOS_YCrYCb = 0,
++	YCPOS_YCbYCr = 1,
++	YCPOS_CbYCrY = 2,
++	YCPOS_CrYCbY = 3
++};
++
++/**
++ * struct ispprev_gtable - Structure for Gamma Correction.
++ * @redtable: Pointer to the red gamma table.
++ * @greentable: Pointer to the green gamma table.
++ * @bluetable: Pointer to the blue gamma table.
++ */
++struct ispprev_gtable {
++	u32 *redtable;
++	u32 *greentable;
++	u32 *bluetable;
++};
++
++/**
++ * struct prev_white_balance - Structure for White Balance 2.
++ * @wb_dgain: White balance common gain.
++ * @wb_gain: Individual color gains.
++ * @wb_coefmatrix: Coefficient matrix
++ */
++struct prev_white_balance {
++	u16 wb_dgain; /* white balance common gain */
++	u8 wb_gain[WB_GAIN_MAX]; /* individual color gains */
++	u8 wb_coefmatrix[WB_GAIN_MAX][WB_GAIN_MAX];
++};
++
++/**
++ * struct prev_size_params - Structure for size parameters.
++ * @hstart: Starting pixel.
++ * @vstart: Starting line.
++ * @hsize: Width of input image.
++ * @vsize: Height of input image.
++ * @pixsize: Pixel size of the image in terms of bits.
++ * @in_pitch: Line offset of input image.
++ * @out_pitch: Line offset of output image.
++ */
++struct prev_size_params {
++	unsigned int hstart;
++	unsigned int vstart;
++	unsigned int hsize;
++	unsigned int vsize;
++	unsigned char pixsize;
++	unsigned short in_pitch;
++	unsigned short out_pitch;
++};
++
++/**
++ * struct prev_rgb2ycbcr_coeffs - Structure RGB2YCbCr parameters.
++ * @coeff: Color conversion gains in 3x3 matrix.
++ * @offset: Color conversion offsets.
++ */
++struct prev_rgb2ycbcr_coeffs {
++	short coeff[RGB_MAX][RGB_MAX];
++	short offset[RGB_MAX];
++};
++
++/**
++ * struct prev_darkfrm_params - Structure for Dark frame suppression.
++ * @addr: Memory start address.
++ * @offset: Line offset.
++ */
++struct prev_darkfrm_params {
++	u32 addr;
++	 u32 offset;
++ };
++
++/**
++ * struct prev_params - Structure for all configuration
++ * @features: Set of features enabled.
++ * @pix_fmt: Output pixel format.
++ * @cfa: CFA coefficients.
++ * @csup: Chroma suppression coefficients.
++ * @ytable: Pointer to Luma enhancement coefficients.
++ * @nf: Noise filter coefficients.
++ * @dcor: Noise filter coefficients.
++ * @gtable: Gamma coefficients.
++ * @wbal: White Balance parameters.
++ * @blk_adj: Black adjustment parameters.
++ * @rgb2rgb: RGB blending parameters.
++ * @rgb2ycbcr: RGB to ycbcr parameters.
++ * @hmf_params: Horizontal median filter.
++ * @size_params: Size parameters.
++ * @drkf_params: Darkframe parameters.
++ * @lens_shading_shift:
++ * @average: Downsampling rate for averager.
++ * @contrast: Contrast.
++ * @brightness: Brightness.
++ */
++struct prev_params {
++	u16 features;
++	enum preview_ycpos_mode pix_fmt;
++	struct ispprev_cfa cfa;
++	struct ispprev_csup csup;
++	u32 *ytable;
++	struct ispprev_nf nf;
++	struct ispprev_dcor dcor;
++	struct ispprev_gtable gtable;
++	struct ispprev_wbal wbal;
++	struct ispprev_blkadj blk_adj;
++	struct ispprev_rgbtorgb rgb2rgb;
++	struct ispprev_csc rgb2ycbcr;
++	struct ispprev_hmed hmf_params;
++	struct prev_size_params size_params;
++	struct prev_darkfrm_params drkf_params;
++	u8 lens_shading_shift;
++	u8 average;
++	u8 contrast;
++	u8 brightness;
++};
++
++/**
++ * struct isptables_update - Structure for Table Configuration.
++ * @update: Specifies which tables should be updated.
++ * @flag: Specifies which tables should be enabled.
++ * @prev_nf: Pointer to structure for Noise Filter
++ * @lsc: Pointer to LSC gain table. (currently not used)
++ * @red_gamma: Pointer to red gamma correction table.
++ * @green_gamma: Pointer to green gamma correction table.
++ * @blue_gamma: Pointer to blue gamma correction table.
++ */
++struct isptables_update {
++	u16 update;
++	u16 flag;
++	struct ispprev_nf *prev_nf;
++	u32 *lsc;
++	u32 *red_gamma;
++	u32 *green_gamma;
++	u32 *blue_gamma;
++};
++
++void isppreview_config_shadow_registers(void);
++
++int isppreview_request(void);
++
++int isppreview_free(void);
++
++int isppreview_config_datapath(enum preview_input input,
++			       enum preview_output output);
++
++void isppreview_config_ycpos(enum preview_ycpos_mode mode);
++
++void isppreview_config_averager(u8 average);
++
++void isppreview_enable_invalaw(u8 enable);
++
++void isppreview_enable_drkframe(u8 enable);
++
++void isppreview_enable_shadcomp(u8 enable);
++
++void isppreview_config_drkf_shadcomp(u8 scomp_shtval);
++
++void isppreview_enable_gammabypass(u8 enable);
++
++void isppreview_enable_hmed(u8 enable);
++
++void isppreview_config_hmed(struct ispprev_hmed);
++
++void isppreview_enable_noisefilter(u8 enable);
++
++void isppreview_config_noisefilter(struct ispprev_nf prev_nf);
++
++void isppreview_enable_dcor(u8 enable);
++
++void isppreview_config_dcor(struct ispprev_dcor prev_dcor);
++
++
++void isppreview_config_cfa(struct ispprev_cfa);
++
++void isppreview_config_gammacorrn(struct ispprev_gtable);
++
++void isppreview_config_chroma_suppression(struct ispprev_csup csup);
++
++void isppreview_enable_cfa(u8 enable);
++
++void isppreview_config_luma_enhancement(u32 *ytable);
++
++void isppreview_enable_luma_enhancement(u8 enable);
++
++void isppreview_enable_chroma_suppression(u8 enable);
++
++void isppreview_config_whitebalance(struct ispprev_wbal);
++
++void isppreview_config_blkadj(struct ispprev_blkadj);
++
++void isppreview_config_rgb_blending(struct ispprev_rgbtorgb);
++
++void isppreview_config_rgb_to_ycbcr(struct ispprev_csc);
++
++void isppreview_update_contrast(u8 *contrast);
++
++void isppreview_query_contrast(u8 *contrast);
++
++void isppreview_config_contrast(u8 contrast);
++
++void isppreview_get_contrast_range(u8 *min_contrast, u8 *max_contrast);
++
++void isppreview_update_brightness(u8 *brightness);
++
++void isppreview_config_brightness(u8 brightness);
++
++void isppreview_get_brightness_range(u8 *min_brightness, u8 *max_brightness);
++
++void isppreview_set_color(u8 *mode);
++
++void isppreview_get_color(u8 *mode);
++
++void isppreview_query_brightness(u8 *brightness);
++
++void isppreview_config_yc_range(struct ispprev_yclimit yclimit);
++
++int isppreview_try_size(u32 input_w, u32 input_h, u32 *output_w,
++			u32 *output_h);
++
++int isppreview_config_size(u32 input_w, u32 input_h, u32 output_w,
++			   u32 output_h);
++
++int isppreview_config_inlineoffset(u32 offset);
++
++int isppreview_set_inaddr(u32 addr);
++
++int isppreview_config_outlineoffset(u32 offset);
++
++int isppreview_set_outaddr(u32 addr);
++
++int isppreview_config_darklineoffset(u32 offset);
++
++int isppreview_set_darkaddr(u32 addr);
++
++void isppreview_enable(int enable);
++
++void isppreview_suspend(void);
++
++void isppreview_resume(void);
++
++int isppreview_busy(void);
++
++struct prev_params *isppreview_get_config(void);
++
++void isppreview_print_status(void);
++
++#ifndef CONFIG_ARCH_OMAP3410
++void isppreview_save_context(void);
++#else
++static inline void isppreview_save_context(void) {}
++#endif
++
++#ifndef CONFIG_ARCH_OMAP3410
++void isppreview_restore_context(void);
++#else
++static inline void isppreview_restore_context(void) {}
++#endif
++
++int omap34xx_isp_preview_config(void *userspace_add);
++
++int omap34xx_isp_tables_update(struct isptables_update *isptables_struct);
++
++void isppreview_set_skip(u32 h, u32 v);
++
++#endif/* OMAP_ISP_PREVIEW_H */
+diff --git a/drivers/media/video/isp/ispresizer.c b/drivers/media/video/isp/ispresizer.c
+new file mode 100644
+index 0000000..f78ddb3
+--- /dev/null
++++ b/drivers/media/video/isp/ispresizer.c
+@@ -0,0 +1,928 @@
++/*
++ * ispresizer.c
++ *
++ * Driver Library for Resizer module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C)2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ * 	Sameer Venkatraman <sameerv@ti.com>
++ * 	Mohit Jalori
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/module.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "ispresizer.h"
++
++/* Default configuration of resizer,filter coefficients,yenh for camera isp */
++static struct isprsz_yenh ispreszdefaultyenh = {0, 0, 0, 0};
++static struct isprsz_coef ispreszdefcoef = {
++	{
++		0x0027, 0x00B2, 0x00B2, 0x0027,
++		0x0027, 0x00B2, 0x0027, 0x00B2,
++		0x0027, 0x00B2, 0x0027, 0x00B2,
++		0x0027, 0x00B2, 0x0027, 0x00B2,
++		0x0027, 0x00B2, 0x0027, 0x00B2,
++		0x0027, 0x00B2, 0x0027, 0x00B2,
++		0x0027, 0x00B2, 0x0027, 0x00B2,
++		0x0027, 0x00B2, 0x0027, 0x00B2,
++	},
++	{
++		0x0000, 0x0100, 0x0000, 0x0000,
++		0x03FA, 0x00F6, 0x0010, 0x0000,
++		0x03F9, 0x00DB, 0x002C, 0x0000,
++		0x03FB, 0x00B3, 0x0053, 0x03FF,
++		0x03FD, 0x0082, 0x0084, 0x03FD,
++		0x03FF, 0x0053, 0x00B3, 0x03FB,
++		0x0000, 0x002C, 0x00DB, 0x03F9,
++		0x0000, 0x0010, 0x00F6, 0x03FA
++	},
++	{
++		0x0004, 0x0023, 0x0023, 0x005A,
++		0x005A, 0x0058, 0x0058, 0x0004,
++		0x0023, 0x0023, 0x005A, 0x005A,
++		0x0058, 0x0058, 0x0004, 0x0023,
++		0x0023, 0x005A, 0x005A, 0x0058,
++		0x0058, 0x0004, 0x0023, 0x0023,
++		0x005A, 0x005A, 0x0058, 0x0058
++	},
++	{
++		0x0004, 0x0023, 0x005A, 0x0058,
++		0x0023, 0x0004, 0x0000, 0x0002,
++		0x0018, 0x004d, 0x0060, 0x0031,
++		0x0008, 0x0000, 0x0001, 0x000f,
++		0x003f, 0x0062, 0x003f, 0x000f,
++		0x0001, 0x0000, 0x0008, 0x0031,
++		0x0060, 0x004d, 0x0018, 0x0002
++	}
++};
++
++/**
++ * struct isp_res - Structure for the resizer module to store its information.
++ * @res_inuse: Indicates if resizer module has been reserved. 1 - Reserved,
++ *             0 - Freed.
++ * @h_startphase: Horizontal starting phase.
++ * @v_startphase: Vertical starting phase.
++ * @h_resz: Horizontal resizing value.
++ * @v_resz: Vertical resizing value.
++ * @outputwidth: Output Image Width in pixels.
++ * @outputheight: Output Image Height in pixels.
++ * @inputwidth: Input Image Width in pixels.
++ * @inputheight: Input Image Height in pixels.
++ * @algo: Algorithm select. 0 - Disable, 1 - [-1 2 -1]/2 high-pass filter,
++ *        2 - [-1 -2 6 -2 -1]/4 high-pass filter.
++ * @ipht_crop: Vertical start line for cropping.
++ * @ipwd_crop: Horizontal start pixel for cropping.
++ * @cropwidth: Crop Width.
++ * @cropheight: Crop Height.
++ * @resinput: Resizer input.
++ * @coeflist: Register configuration for Resizer.
++ * @ispres_mutex: Mutex for isp resizer.
++ */
++static struct isp_res {
++	int pm_state;
++	u8 res_inuse;
++	u8 h_startphase;
++	u8 v_startphase;
++	u16 h_resz;
++	u16 v_resz;
++	u32 outputwidth;
++	u32 outputheight;
++	u32 inputwidth;
++	u32 inputheight;
++	u8 algo;
++	u32 ipht_crop;
++	u32 ipwd_crop;
++	u32 cropwidth;
++	u32 cropheight;
++	dma_addr_t tmp_buf;
++	enum ispresizer_input resinput;
++	struct isprsz_coef coeflist;
++	struct mutex ispres_mutex; /* For checking/modifying res_inuse */
++} ispres_obj;
++
++/* Structure for saving/restoring resizer module registers */
++static struct isp_reg isprsz_reg_list[] = {
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_CNT, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_OUT_SIZE, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_IN_START, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_IN_SIZE, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_INADD, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_INOFF, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_OUTADD, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_OUTOFF, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT10, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT32, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT54, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT76, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT98, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT1110, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT1312, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT1514, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT1716, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT1918, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT2120, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT2322, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT2524, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT2726, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT2928, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_HFILT3130, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT10, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT32, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT54, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT76, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT98, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT1110, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT1312, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT1514, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT1716, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT1918, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT2120, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT2322, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT2524, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT2726, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT2928, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_VFILT3130, 0x0000},
++	{OMAP3_ISP_IOMEM_RESZ, ISPRSZ_YENH, 0x0000},
++	{0, ISP_TOK_TERM, 0x0000}
++};
++
++/**
++ * ispresizer_config_shadow_registers - Configure shadow registers.
++ **/
++void ispresizer_config_shadow_registers()
++{
++	return;
++}
++EXPORT_SYMBOL(ispresizer_config_shadow_registers);
++
++/**
++ * ispresizer_trycrop - Validate crop dimensions.
++ * @left: Left distance to start position of crop.
++ * @top: Top distance to start position of crop.
++ * @width: Width of input image.
++ * @height: Height of input image.
++ * @ow: Width of output image.
++ * @oh: Height of output image.
++ **/
++void ispresizer_trycrop(u32 left, u32 top, u32 width, u32 height, u32 ow,
++			u32 oh)
++{
++	ispres_obj.cropwidth = width + 6;
++	ispres_obj.cropheight = height + 6;
++	ispresizer_try_size(&ispres_obj.cropwidth, &ispres_obj.cropheight, &ow,
++			    &oh);
++	ispres_obj.ipht_crop = top;
++	ispres_obj.ipwd_crop = left;
++}
++EXPORT_SYMBOL(ispresizer_trycrop);
++
++/**
++ * ispresizer_applycrop - Apply crop to input image.
++ **/
++void ispresizer_applycrop(void)
++{
++	ispresizer_config_size(ispres_obj.cropwidth, ispres_obj.cropheight,
++			       ispres_obj.outputwidth,
++			       ispres_obj.outputheight);
++	return;
++}
++EXPORT_SYMBOL(ispresizer_applycrop);
++
++/**
++ * ispresizer_request - Reserves the Resizer module.
++ *
++ * Allows only one user at a time.
++ *
++ * Returns 0 if successful, or -EBUSY if resizer module was already requested.
++ **/
++int ispresizer_request()
++{
++	mutex_lock(&ispres_obj.ispres_mutex);
++	if (!ispres_obj.res_inuse) {
++		ispres_obj.res_inuse = 1;
++		mutex_unlock(&ispres_obj.ispres_mutex);
++		isp_reg_writel(isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL) |
++			       ISPCTRL_SBL_WR0_RAM_EN |
++			       ISPCTRL_RSZ_CLK_EN,
++			       OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
++		return 0;
++	} else {
++		mutex_unlock(&ispres_obj.ispres_mutex);
++		printk(KERN_ERR "ISP_ERR : Resizer Module Busy\n");
++		return -EBUSY;
++	}
++}
++EXPORT_SYMBOL(ispresizer_request);
++
++/**
++ * ispresizer_free - Makes Resizer module free.
++ *
++ * Returns 0 if successful, or -EINVAL if resizer module was already freed.
++ **/
++int ispresizer_free()
++{
++	mutex_lock(&ispres_obj.ispres_mutex);
++	if (ispres_obj.res_inuse) {
++		ispres_obj.res_inuse = 0;
++		mutex_unlock(&ispres_obj.ispres_mutex);
++		isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
++			    ~(ISPCTRL_RSZ_CLK_EN | ISPCTRL_SBL_WR0_RAM_EN));
++		return 0;
++	} else {
++		mutex_unlock(&ispres_obj.ispres_mutex);
++		DPRINTK_ISPRESZ("ISP_ERR : Resizer Module already freed\n");
++		return -EINVAL;
++	}
++}
++EXPORT_SYMBOL(ispresizer_free);
++
++/**
++ * ispresizer_config_datapath - Specifies which input to use in resizer module
++ * @input: Indicates the module that gives the image to resizer.
++ *
++ * Sets up the default resizer configuration according to the arguments.
++ *
++ * Returns 0 if successful, or -EINVAL if an unsupported input was requested.
++ **/
++int ispresizer_config_datapath(enum ispresizer_input input)
++{
++	u32 cnt = 0;
++	DPRINTK_ISPRESZ("ispresizer_config_datapath()+\n");
++	ispres_obj.resinput = input;
++	switch (input) {
++	case RSZ_OTFLY_YUV:
++		cnt &= ~ISPRSZ_CNT_INPTYP;
++		cnt &= ~ISPRSZ_CNT_INPSRC;
++		ispresizer_set_inaddr(0);
++		ispresizer_config_inlineoffset(0);
++		break;
++	case RSZ_MEM_YUV:
++		cnt |= ISPRSZ_CNT_INPSRC;
++		cnt &= ~ISPRSZ_CNT_INPTYP;
++		break;
++	case RSZ_MEM_COL8:
++		cnt |= ISPRSZ_CNT_INPSRC;
++		cnt |= ISPRSZ_CNT_INPTYP;
++		break;
++	default:
++		printk(KERN_ERR "ISP_ERR : Wrong Input\n");
++		return -EINVAL;
++	}
++	isp_reg_or(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_CNT, cnt);
++	ispresizer_config_ycpos(0);
++	ispresizer_config_filter_coef(&ispreszdefcoef);
++	ispresizer_enable_cbilin(0);
++	ispresizer_config_luma_enhance(&ispreszdefaultyenh);
++	DPRINTK_ISPRESZ("ispresizer_config_datapath()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_config_datapath);
++
++/**
++ * ispresizer_try_size - Validates input and output images size.
++ * @input_w: input width for the resizer in number of pixels per line
++ * @input_h: input height for the resizer in number of lines
++ * @output_w: output width from the resizer in number of pixels per line
++ *            resizer when writing to memory needs this to be multiple of 16.
++ * @output_h: output height for the resizer in number of lines, must be even.
++ *
++ * Calculates the horizontal and vertical resize ratio, number of pixels to
++ * be cropped in the resizer module and checks the validity of various
++ * parameters. Formula used for calculation is:-
++ *
++ * 8-phase 4-tap mode :-
++ * inputwidth = (32 * sph + (ow - 1) * hrsz + 16) >> 8 + 7
++ * inputheight = (32 * spv + (oh - 1) * vrsz + 16) >> 8 + 4
++ * endpahse for width = ((32 * sph + (ow - 1) * hrsz + 16) >> 5) % 8
++ * endphase for height = ((32 * sph + (oh - 1) * hrsz + 16) >> 5) % 8
++ *
++ * 4-phase 7-tap mode :-
++ * inputwidth = (64 * sph + (ow - 1) * hrsz + 32) >> 8 + 7
++ * inputheight = (64 * spv + (oh - 1) * vrsz + 32) >> 8 + 7
++ * endpahse for width = ((64 * sph + (ow - 1) * hrsz + 32) >> 6) % 4
++ * endphase for height = ((64 * sph + (oh - 1) * hrsz + 32) >> 6) % 4
++ *
++ * Where:
++ * sph = Start phase horizontal
++ * spv = Start phase vertical
++ * ow = Output width
++ * oh = Output height
++ * hrsz = Horizontal resize value
++ * vrsz = Vertical resize value
++ *
++ * Fills up the output/input widht/height, horizontal/vertical resize ratio,
++ * horizontal/vertical crop variables in the isp_res structure.
++ **/
++int ispresizer_try_size(u32 *input_width, u32 *input_height, u32 *output_w,
++			u32 *output_h)
++{
++	u32 rsz, rsz_7, rsz_4;
++	u32 sph;
++	u32 input_w, input_h;
++	int max_in_otf, max_out_7tap;
++
++	input_w = *input_width;
++	input_h = *input_height;
++
++	if (input_w < 32 || input_h < 32) {
++		DPRINTK_ISPCCDC("ISP_ERR: RESIZER cannot handle input width"
++				" less than 32 pixels or height less than"
++				" 32\n");
++		return -EINVAL;
++	}
++	input_w -= 6;
++	input_h -= 6;
++
++	if (input_h > MAX_IN_HEIGHT)
++		return -EINVAL;
++
++	if (*output_w < 16)
++		*output_w = 16;
++
++	if (*output_h < 2)
++		*output_h = 2;
++
++	if (omap_rev() == OMAP3430_REV_ES1_0) {
++		max_in_otf = MAX_IN_WIDTH_ONTHEFLY_MODE;
++		max_out_7tap = MAX_7TAP_VRSZ_OUTWIDTH;
++	} else {
++		max_in_otf = MAX_IN_WIDTH_ONTHEFLY_MODE_ES2;
++		max_out_7tap = MAX_7TAP_VRSZ_OUTWIDTH_ES2;
++	}
++
++	if (ispres_obj.resinput == RSZ_OTFLY_YUV) {
++		if (input_w > max_in_otf)
++			return -EINVAL;
++	} else {
++		if (input_w > MAX_IN_WIDTH_MEMORY_MODE)
++			return -EINVAL;
++	}
++
++	*output_h &= 0xfffffffe;
++	sph = DEFAULTSTPHASE;
++
++	rsz_7 = ((input_h - 7) * 256) / (*output_h - 1);
++	rsz_4 = ((input_h - 4) * 256) / (*output_h - 1);
++
++	rsz = (input_h * 256) / *output_h;
++
++	if (rsz <= MID_RESIZE_VALUE) {
++		rsz = rsz_4;
++		if (rsz < MINIMUM_RESIZE_VALUE) {
++			rsz = MINIMUM_RESIZE_VALUE;
++			*output_h = (((input_h - 4) * 256) / rsz) + 1;
++			printk(KERN_INFO "%s: using output_h %d instead\n",
++			       __func__, *output_h);
++		}
++	} else {
++		rsz = rsz_7;
++		if (*output_w > max_out_7tap)
++			*output_w = max_out_7tap;
++		if (rsz > MAXIMUM_RESIZE_VALUE) {
++			rsz = MAXIMUM_RESIZE_VALUE;
++			*output_h = (((input_h - 7) * 256) / rsz) + 1;
++			printk(KERN_INFO "%s: using output_h %d instead\n",
++			       __func__, *output_h);
++		}
++	}
++
++	if (rsz > MID_RESIZE_VALUE) {
++		input_h =
++			(((64 * sph) + ((*output_h - 1) * rsz) + 32) / 256) + 7;
++	} else {
++		input_h =
++			(((32 * sph) + ((*output_h - 1) * rsz) + 16) / 256) + 4;
++	}
++
++	ispres_obj.outputheight = *output_h;
++	ispres_obj.v_resz = rsz;
++	ispres_obj.inputheight = input_h;
++	ispres_obj.ipht_crop = DEFAULTSTPIXEL;
++	ispres_obj.v_startphase = sph;
++
++	*output_w &= 0xfffffff0;
++	sph = DEFAULTSTPHASE;
++
++	rsz_7 = ((input_w - 7) * 256) / (*output_w - 1);
++	rsz_4 = ((input_w - 4) * 256) / (*output_w - 1);
++
++	rsz = (input_w * 256) / *output_w;
++	if (rsz > MID_RESIZE_VALUE) {
++		rsz = rsz_7;
++		if (rsz > MAXIMUM_RESIZE_VALUE) {
++			rsz = MAXIMUM_RESIZE_VALUE;
++			*output_w = (((input_w - 7) * 256) / rsz) + 1;
++			*output_w = (*output_w + 0xf) & 0xfffffff0;
++			printk(KERN_INFO "%s: using output_w %d instead\n",
++			       __func__, *output_w);
++		}
++	} else {
++		rsz = rsz_4;
++		if (rsz < MINIMUM_RESIZE_VALUE) {
++			rsz = MINIMUM_RESIZE_VALUE;
++			*output_w = (((input_w - 4) * 256) / rsz) + 1;
++			*output_w = (*output_w + 0xf) & 0xfffffff0;
++			printk(KERN_INFO "%s: using output_w %d instead\n",
++			       __func__, *output_w);
++		}
++	}
++
++	/* Recalculate input based on TRM equations */
++	if (rsz > MID_RESIZE_VALUE) {
++		input_w =
++			(((64 * sph) + ((*output_w - 1) * rsz) + 32) / 256) + 7;
++	} else {
++		input_w =
++			(((32 * sph) + ((*output_w - 1) * rsz) + 16) / 256) + 7;
++	}
++
++	ispres_obj.outputwidth = *output_w;
++	ispres_obj.h_resz = rsz;
++	ispres_obj.inputwidth = input_w;
++	ispres_obj.ipwd_crop = DEFAULTSTPIXEL;
++	ispres_obj.h_startphase = sph;
++
++	*input_height = input_h;
++	*input_width = input_w;
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_try_size);
++
++/**
++ * ispresizer_config_size - Configures input and output image size.
++ * @input_w: input width for the resizer in number of pixels per line.
++ * @input_h: input height for the resizer in number of lines.
++ * @output_w: output width from the resizer in number of pixels per line.
++ * @output_h: output height for the resizer in number of lines.
++ *
++ * Configures the appropriate values stored in the isp_res structure in the
++ * resizer registers.
++ *
++ * Returns 0 if successful, or -EINVAL if passed values haven't been verified
++ * with ispresizer_try_size() previously.
++ **/
++int ispresizer_config_size(u32 input_w, u32 input_h, u32 output_w,
++			   u32 output_h)
++{
++	int i, j;
++	u32 res;
++	DPRINTK_ISPRESZ("ispresizer_config_size()+, input_w = %d,input_h ="
++			" %d, output_w = %d, output_h"
++			" = %d,hresz = %d,vresz = %d,"
++			" hcrop = %d, vcrop = %d,"
++			" hstph = %d, vstph = %d\n",
++			ispres_obj.inputwidth,
++			ispres_obj.inputheight,
++			ispres_obj.outputwidth,
++			ispres_obj.outputheight,
++			ispres_obj.h_resz,
++			ispres_obj.v_resz,
++			ispres_obj.ipwd_crop,
++			ispres_obj.ipht_crop,
++			ispres_obj.h_startphase,
++			ispres_obj.v_startphase);
++	if ((output_w != ispres_obj.outputwidth)
++	    || (output_h != ispres_obj.outputheight)) {
++		printk(KERN_ERR "Output parameters passed do not match the"
++		       " values calculated by the"
++		       " trysize passed w %d, h %d"
++		       " \n", output_w , output_h);
++		return -EINVAL;
++	}
++
++	/* Set Resizer input address and offset adderss */
++	ispresizer_config_inlineoffset(isp_reg_readl(OMAP3_ISP_IOMEM_PREV,
++						     ISPPRV_WADD_OFFSET));
++
++	res = isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_CNT) &
++		~(ISPRSZ_CNT_HSTPH_MASK | ISPRSZ_CNT_VSTPH_MASK);
++	isp_reg_writel(res |
++		       (ispres_obj.h_startphase << ISPRSZ_CNT_HSTPH_SHIFT) |
++		       (ispres_obj.v_startphase << ISPRSZ_CNT_VSTPH_SHIFT),
++		       OMAP3_ISP_IOMEM_RESZ,
++		       ISPRSZ_CNT);
++	/* Set start address for cropping */
++	isp_reg_writel(ispres_obj.tmp_buf + 2 *
++		       (ispres_obj.ipht_crop * ispres_obj.inputwidth +
++			(ispres_obj.ipwd_crop & ~15)),
++		       OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_INADD);
++
++	isp_reg_writel(
++		((ispres_obj.ipwd_crop & 15) << ISPRSZ_IN_START_HORZ_ST_SHIFT) |
++		(0x00 << ISPRSZ_IN_START_VERT_ST_SHIFT),
++		OMAP3_ISP_IOMEM_RESZ, ISPRSZ_IN_START);
++
++	isp_reg_writel((0x00 << ISPRSZ_IN_START_HORZ_ST_SHIFT) |
++		       (0x00 << ISPRSZ_IN_START_VERT_ST_SHIFT),
++		       OMAP3_ISP_IOMEM_RESZ,
++		       ISPRSZ_IN_START);
++
++	isp_reg_writel((ispres_obj.inputwidth << ISPRSZ_IN_SIZE_HORZ_SHIFT) |
++		       (ispres_obj.inputheight <<
++			ISPRSZ_IN_SIZE_VERT_SHIFT),
++		       OMAP3_ISP_IOMEM_RESZ,
++		       ISPRSZ_IN_SIZE);
++	if (!ispres_obj.algo) {
++		isp_reg_writel((output_w << ISPRSZ_OUT_SIZE_HORZ_SHIFT) |
++			       (output_h << ISPRSZ_OUT_SIZE_VERT_SHIFT),
++			       OMAP3_ISP_IOMEM_RESZ,
++			       ISPRSZ_OUT_SIZE);
++	} else {
++		isp_reg_writel(((output_w - 4) << ISPRSZ_OUT_SIZE_HORZ_SHIFT) |
++			       (output_h << ISPRSZ_OUT_SIZE_VERT_SHIFT),
++			       OMAP3_ISP_IOMEM_RESZ,
++			       ISPRSZ_OUT_SIZE);
++	}
++
++	res = isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_CNT) &
++		~(ISPRSZ_CNT_HRSZ_MASK | ISPRSZ_CNT_VRSZ_MASK);
++	isp_reg_writel(res |
++		       ((ispres_obj.h_resz - 1) << ISPRSZ_CNT_HRSZ_SHIFT) |
++		       ((ispres_obj.v_resz - 1) << ISPRSZ_CNT_VRSZ_SHIFT),
++		       OMAP3_ISP_IOMEM_RESZ,
++		       ISPRSZ_CNT);
++	if (ispres_obj.h_resz <= MID_RESIZE_VALUE) {
++		j = 0;
++		for (i = 0; i < 16; i++) {
++			isp_reg_writel(
++				(ispres_obj.coeflist.h_filter_coef_4tap[j]
++				 << ISPRSZ_HFILT10_COEF0_SHIFT) |
++				(ispres_obj.coeflist.h_filter_coef_4tap[j + 1]
++				 << ISPRSZ_HFILT10_COEF1_SHIFT),
++				OMAP3_ISP_IOMEM_RESZ,
++				ISPRSZ_HFILT10 + (i * 0x04));
++			j += 2;
++		}
++	} else {
++		j = 0;
++		for (i = 0; i < 16; i++) {
++			if ((i + 1) % 4 == 0) {
++				isp_reg_writel((ispres_obj.coeflist.
++						h_filter_coef_7tap[j] <<
++						ISPRSZ_HFILT10_COEF0_SHIFT),
++					       OMAP3_ISP_IOMEM_RESZ,
++					       ISPRSZ_HFILT10 + (i * 0x04));
++				j += 1;
++			} else {
++				isp_reg_writel((ispres_obj.coeflist.
++						h_filter_coef_7tap[j] <<
++						ISPRSZ_HFILT10_COEF0_SHIFT) |
++					       (ispres_obj.coeflist.
++						h_filter_coef_7tap[j+1] <<
++						ISPRSZ_HFILT10_COEF1_SHIFT),
++					       OMAP3_ISP_IOMEM_RESZ,
++					       ISPRSZ_HFILT10 + (i * 0x04));
++				j += 2;
++			}
++		}
++	}
++	if (ispres_obj.v_resz <= MID_RESIZE_VALUE) {
++		j = 0;
++		for (i = 0; i < 16; i++) {
++			isp_reg_writel((ispres_obj.coeflist.
++					v_filter_coef_4tap[j] <<
++					ISPRSZ_VFILT10_COEF0_SHIFT) |
++				       (ispres_obj.coeflist.
++					v_filter_coef_4tap[j + 1] <<
++					ISPRSZ_VFILT10_COEF1_SHIFT),
++				       OMAP3_ISP_IOMEM_RESZ,
++				       ISPRSZ_VFILT10 + (i * 0x04));
++			j += 2;
++		}
++	} else {
++		j = 0;
++		for (i = 0; i < 16; i++) {
++			if ((i + 1) % 4 == 0) {
++				isp_reg_writel((ispres_obj.coeflist.
++						v_filter_coef_7tap[j] <<
++						ISPRSZ_VFILT10_COEF0_SHIFT),
++					       OMAP3_ISP_IOMEM_RESZ,
++					       ISPRSZ_VFILT10 + (i * 0x04));
++				j += 1;
++			} else {
++				isp_reg_writel((ispres_obj.coeflist.
++						v_filter_coef_7tap[j] <<
++						ISPRSZ_VFILT10_COEF0_SHIFT) |
++					       (ispres_obj.coeflist.
++						v_filter_coef_7tap[j+1] <<
++						ISPRSZ_VFILT10_COEF1_SHIFT),
++					       OMAP3_ISP_IOMEM_RESZ,
++					       ISPRSZ_VFILT10 + (i * 0x04));
++				j += 2;
++			}
++		}
++	}
++
++	ispresizer_config_outlineoffset(output_w*2);
++	DPRINTK_ISPRESZ("ispresizer_config_size()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_config_size);
++
++void __ispresizer_enable(int enable)
++{
++	int val;
++	DPRINTK_ISPRESZ("+ispresizer_enable()+\n");
++	if (enable) {
++		val = (isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_PCR) & 0x2) |
++			ISPRSZ_PCR_ENABLE;
++	} else {
++		val = isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_PCR) &
++			~ISPRSZ_PCR_ENABLE;
++	}
++	isp_reg_writel(val, OMAP3_ISP_IOMEM_RESZ, ISPRSZ_PCR);
++	DPRINTK_ISPRESZ("+ispresizer_enable()-\n");
++}
++
++/**
++ * ispresizer_enable - Enables the resizer module.
++ * @enable: 1 - Enable, 0 - Disable
++ *
++ * Client should configure all the sub modules in resizer before this.
++ **/
++void ispresizer_enable(int enable)
++{
++	__ispresizer_enable(enable);
++	ispres_obj.pm_state = enable;
++}
++EXPORT_SYMBOL(ispresizer_enable);
++
++/**
++ * ispresizer_suspend - Suspend resizer module.
++ **/
++void ispresizer_suspend(void)
++{
++	if (ispres_obj.pm_state)
++		__ispresizer_enable(0);
++}
++EXPORT_SYMBOL(ispresizer_suspend);
++
++/**
++ * ispresizer_resume - Resume resizer module.
++ **/
++void ispresizer_resume(void)
++{
++	if (ispres_obj.pm_state)
++		__ispresizer_enable(1);
++}
++EXPORT_SYMBOL(ispresizer_resume);
++
++/**
++ * ispresizer_busy - Checks if ISP resizer is busy.
++ *
++ * Returns busy field from ISPRSZ_PCR register.
++ **/
++int ispresizer_busy(void)
++{
++	return isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_PCR) &
++		ISPPRV_PCR_BUSY;
++}
++EXPORT_SYMBOL(ispresizer_busy);
++
++/**
++ * ispresizer_config_startphase - Sets the horizontal and vertical start phase.
++ * @hstartphase: horizontal start phase (0 - 7).
++ * @vstartphase: vertical startphase (0 - 7).
++ *
++ * This API just updates the isp_res struct. Actual register write happens in
++ * ispresizer_config_size.
++ **/
++void ispresizer_config_startphase(u8 hstartphase, u8 vstartphase)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_startphase()+\n");
++	ispres_obj.h_startphase = hstartphase;
++	ispres_obj.v_startphase = vstartphase;
++	DPRINTK_ISPRESZ("ispresizer_config_startphase()-\n");
++}
++EXPORT_SYMBOL(ispresizer_config_startphase);
++
++/**
++ * ispresizer_config_ycpos - Specifies if output should be in YC or CY format.
++ * @yc: 0 - YC format, 1 - CY format
++ **/
++void ispresizer_config_ycpos(u8 yc)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_ycpos()+\n");
++	isp_reg_and_or(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_CNT, ~ISPRSZ_CNT_YCPOS,
++		       (yc ? ISPRSZ_CNT_YCPOS : 0));
++	DPRINTK_ISPRESZ("ispresizer_config_ycpos()-\n");
++}
++EXPORT_SYMBOL(ispresizer_config_ycpos);
++
++/**
++ * Sets the chrominance algorithm
++ * @cbilin: 0 - chrominance uses same processing as luminance,
++ *          1 - bilinear interpolation processing
++ **/
++void ispresizer_enable_cbilin(u8 enable)
++{
++	DPRINTK_ISPRESZ("ispresizer_enable_cbilin()+\n");
++	isp_reg_and_or(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_CNT, ~ISPRSZ_CNT_CBILIN,
++		       (enable ? ISPRSZ_CNT_CBILIN : 0));
++	DPRINTK_ISPRESZ("ispresizer_enable_cbilin()-\n");
++}
++EXPORT_SYMBOL(ispresizer_enable_cbilin);
++
++/**
++ * ispresizer_config_luma_enhance - Configures luminance enhancer parameters.
++ * @yenh: Pointer to structure containing desired values for core, slope, gain
++ *        and algo parameters.
++ **/
++void ispresizer_config_luma_enhance(struct isprsz_yenh *yenh)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_luma_enhance()+\n");
++	ispres_obj.algo = yenh->algo;
++	isp_reg_writel((yenh->algo << ISPRSZ_YENH_ALGO_SHIFT) |
++		       (yenh->gain << ISPRSZ_YENH_GAIN_SHIFT) |
++		       (yenh->slope << ISPRSZ_YENH_SLOP_SHIFT) |
++		       (yenh->coreoffset << ISPRSZ_YENH_CORE_SHIFT),
++		       OMAP3_ISP_IOMEM_RESZ,
++		       ISPRSZ_YENH);
++	DPRINTK_ISPRESZ("ispresizer_config_luma_enhance()-\n");
++}
++EXPORT_SYMBOL(ispresizer_config_luma_enhance);
++
++/**
++ * ispresizer_config_filter_coef - Sets filter coefficients for 4 & 7-tap mode.
++ * This API just updates the isp_res struct.Actual register write happens in
++ * ispresizer_config_size.
++ * @coef: Structure containing horizontal and vertical filter coefficients for
++ *        both 4-tap and 7-tap mode.
++ **/
++void ispresizer_config_filter_coef(struct isprsz_coef *coef)
++{
++	int i;
++	DPRINTK_ISPRESZ("ispresizer_config_filter_coef()+\n");
++	for (i = 0; i < 32; i++) {
++		ispres_obj.coeflist.h_filter_coef_4tap[i] =
++			coef->h_filter_coef_4tap[i];
++		ispres_obj.coeflist.v_filter_coef_4tap[i] =
++			coef->v_filter_coef_4tap[i];
++	}
++	for (i = 0; i < 28; i++) {
++		ispres_obj.coeflist.h_filter_coef_7tap[i] =
++			coef->h_filter_coef_7tap[i];
++		ispres_obj.coeflist.v_filter_coef_7tap[i] =
++			coef->v_filter_coef_7tap[i];
++	}
++	DPRINTK_ISPRESZ("ispresizer_config_filter_coef()-\n");
++}
++EXPORT_SYMBOL(ispresizer_config_filter_coef);
++
++/**
++ * ispresizer_config_inlineoffset - Configures the read address line offset.
++ * @offset: Line Offset for the input image.
++ *
++ * Returns 0 if successful, or -EINVAL if offset is not 32 bits aligned.
++ **/
++int ispresizer_config_inlineoffset(u32 offset)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_inlineoffset()+\n");
++	if (offset % 32)
++		return -EINVAL;
++	isp_reg_writel(offset << ISPRSZ_SDR_INOFF_OFFSET_SHIFT,
++		       OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_INOFF);
++	DPRINTK_ISPRESZ("ispresizer_config_inlineoffset()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_config_inlineoffset);
++
++/**
++ * ispresizer_set_inaddr - Sets the memory address of the input frame.
++ * @addr: 32bit memory address aligned on 32byte boundary.
++ *
++ * Returns 0 if successful, or -EINVAL if address is not 32 bits aligned.
++ **/
++int ispresizer_set_inaddr(u32 addr)
++{
++	DPRINTK_ISPRESZ("ispresizer_set_inaddr()+\n");
++	if (addr % 32)
++		return -EINVAL;
++	isp_reg_writel(addr << ISPRSZ_SDR_INADD_ADDR_SHIFT,
++		       OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_INADD);
++	ispres_obj.tmp_buf = addr;
++	DPRINTK_ISPRESZ("ispresizer_set_inaddr()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_set_inaddr);
++
++/**
++ * ispresizer_config_outlineoffset - Configures the write address line offset.
++ * @offset: Line offset for the preview output.
++ *
++ * Returns 0 if successful, or -EINVAL if address is not 32 bits aligned.
++ **/
++int ispresizer_config_outlineoffset(u32 offset)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_outlineoffset()+\n");
++	if (offset % 32)
++		return -EINVAL;
++	isp_reg_writel(offset << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT,
++		       OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_OUTOFF);
++	DPRINTK_ISPRESZ("ispresizer_config_outlineoffset()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_config_outlineoffset);
++
++/**
++ * Configures the memory address to which the output frame is written.
++ * @addr: 32bit memory address aligned on 32byte boundary.
++ **/
++int ispresizer_set_outaddr(u32 addr)
++{
++	DPRINTK_ISPRESZ("ispresizer_set_outaddr()+\n");
++	if (addr % 32)
++		return -EINVAL;
++	isp_reg_writel(addr << ISPRSZ_SDR_OUTADD_ADDR_SHIFT,
++		       OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_OUTADD);
++	DPRINTK_ISPRESZ("ispresizer_set_outaddr()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_set_outaddr);
++
++/**
++ * ispresizer_save_context - Saves the values of the resizer module registers.
++ **/
++void ispresizer_save_context(void)
++{
++	DPRINTK_ISPRESZ("Saving context\n");
++	isp_save_context(isprsz_reg_list);
++}
++EXPORT_SYMBOL(ispresizer_save_context);
++
++/**
++ * ispresizer_restore_context - Restores resizer module register values.
++ **/
++void ispresizer_restore_context(void)
++{
++	DPRINTK_ISPRESZ("Restoring context\n");
++	isp_restore_context(isprsz_reg_list);
++}
++EXPORT_SYMBOL(ispresizer_restore_context);
++
++/**
++ * ispresizer_print_status - Prints the values of the resizer module registers.
++ **/
++void ispresizer_print_status()
++{
++	if (!is_ispresz_debug_enabled())
++		return;
++	DPRINTK_ISPRESZ("###ISP_CTRL inresizer =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL));
++	DPRINTK_ISPRESZ("###ISP_IRQ0ENABLE in resizer =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE));
++	DPRINTK_ISPRESZ("###ISP_IRQ0STATUS in resizer =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS));
++	DPRINTK_ISPRESZ("###RSZ PCR =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_PCR));
++	DPRINTK_ISPRESZ("###RSZ CNT =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_CNT));
++	DPRINTK_ISPRESZ("###RSZ OUT SIZE =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_OUT_SIZE));
++	DPRINTK_ISPRESZ("###RSZ IN START =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_IN_START));
++	DPRINTK_ISPRESZ("###RSZ IN SIZE =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_IN_SIZE));
++	DPRINTK_ISPRESZ("###RSZ SDR INADD =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_INADD));
++	DPRINTK_ISPRESZ("###RSZ SDR INOFF =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_INOFF));
++	DPRINTK_ISPRESZ("###RSZ SDR OUTADD =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_OUTADD));
++	DPRINTK_ISPRESZ("###RSZ SDR OTOFF =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_SDR_OUTOFF));
++	DPRINTK_ISPRESZ("###RSZ YENH =0x%x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_RESZ, ISPRSZ_YENH));
++}
++EXPORT_SYMBOL(ispresizer_print_status);
++
++/**
++ * isp_resizer_init - Module Initialisation.
++ *
++ * Always returns 0.
++ **/
++int __init isp_resizer_init(void)
++{
++	mutex_init(&ispres_obj.ispres_mutex);
++	ispres_obj.pm_state = 0;
++	return 0;
++}
++
++/**
++ * isp_resizer_cleanup - Module Cleanup.
++ **/
++void isp_resizer_cleanup(void)
++{
++}
+diff --git a/drivers/media/video/isp/ispresizer.h b/drivers/media/video/isp/ispresizer.h
+new file mode 100644
+index 0000000..4e92225
+--- /dev/null
++++ b/drivers/media/video/isp/ispresizer.h
+@@ -0,0 +1,158 @@
++/*
++ * ispresizer.h
++ *
++ * Driver header file for Resizer module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ * 	Sameer Venkatraman <sameerv@ti.com>
++ * 	Mohit Jalori
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_RESIZER_H
++#define OMAP_ISP_RESIZER_H
++
++/*
++ * Resizer Constants
++ */
++#define MAX_IN_WIDTH_MEMORY_MODE	4095
++
++#define MAX_IN_WIDTH_ONTHEFLY_MODE	1280
++#define MAX_IN_WIDTH_ONTHEFLY_MODE_ES2	4095
++#define MAX_IN_HEIGHT			4095
++#define MINIMUM_RESIZE_VALUE		64
++#define MAXIMUM_RESIZE_VALUE		1024
++#define MID_RESIZE_VALUE		512
++
++#define MAX_7TAP_HRSZ_OUTWIDTH		1280
++#define MAX_7TAP_VRSZ_OUTWIDTH		640
++
++#define MAX_7TAP_HRSZ_OUTWIDTH_ES2	3300
++#define MAX_7TAP_VRSZ_OUTWIDTH_ES2	1650
++
++#define DEFAULTSTPIXEL			0
++#define DEFAULTSTPHASE			1
++#define DEFAULTHSTPIXEL4TAPMODE		3
++#define FOURPHASE			4
++#define EIGHTPHASE			8
++#define RESIZECONSTANT			256
++#define SHIFTER4TAPMODE			0
++#define SHIFTER7TAPMODE			1
++#define DEFAULTOFFSET			7
++#define OFFSETVERT4TAPMODE		4
++#define OPWDALIGNCONSTANT		0xfffffff0
++
++/*
++ * The client is supposed to call resizer API in the following sequence:
++ * 	- request()
++ * 	- config_datatpath()
++ * 	- optionally config/enable sub modules
++ * 	- try/config size
++ * 	- setup callback
++ * 	- setup in/out memory offsets and ptrs
++ * 	- enable()
++ * 	...
++ * 	- disable()
++ * 	- free()
++ */
++
++enum ispresizer_input {
++	RSZ_OTFLY_YUV,
++	RSZ_MEM_YUV,
++	RSZ_MEM_COL8
++};
++
++/**
++ * struct isprsz_coef - Structure for resizer filter coeffcients.
++ * @h_filter_coef_4tap: Horizontal filter coefficients for 8-phase/4-tap
++ *			mode (.5x-4x)
++ * @v_filter_coef_4tap: Vertical filter coefficients for 8-phase/4-tap
++ *			mode (.5x-4x)
++ * @h_filter_coef_7tap: Horizontal filter coefficients for 4-phase/7-tap
++ *			mode (.25x-.5x)
++ * @v_filter_coef_7tap: Vertical filter coefficients for 4-phase/7-tap
++ *			mode (.25x-.5x)
++ */
++struct isprsz_coef {
++	u16 h_filter_coef_4tap[32];
++	u16 v_filter_coef_4tap[32];
++	u16 h_filter_coef_7tap[28];
++	u16 v_filter_coef_7tap[28];
++};
++
++/**
++ * struct isprsz_yenh - Structure for resizer luminance enhancer parameters.
++ * @algo: Algorithm select.
++ * @gain: Maximum gain.
++ * @slope: Slope.
++ * @coreoffset: Coring offset.
++ */
++struct isprsz_yenh {
++	u8 algo;
++	u8 gain;
++	u8 slope;
++	u8 coreoffset;
++};
++
++void ispresizer_config_shadow_registers(void);
++
++int ispresizer_request(void);
++
++int ispresizer_free(void);
++
++int ispresizer_config_datapath(enum ispresizer_input input);
++
++void ispresizer_enable_cbilin(u8 enable);
++
++void ispresizer_config_ycpos(u8 yc);
++
++void ispresizer_config_startphase(u8 hstartphase, u8 vstartphase);
++
++void ispresizer_config_filter_coef(struct isprsz_coef *coef);
++
++void ispresizer_config_luma_enhance(struct isprsz_yenh *yenh);
++
++int ispresizer_try_size(u32 *input_w, u32 *input_h, u32 *output_w,
++			u32 *output_h);
++
++void ispresizer_applycrop(void);
++
++void ispresizer_trycrop(u32 left, u32 top, u32 width, u32 height, u32 ow,
++			u32 oh);
++
++int ispresizer_config_size(u32 input_w, u32 input_h, u32 output_w,
++			   u32 output_h);
++
++int ispresizer_config_inlineoffset(u32 offset);
++
++int ispresizer_set_inaddr(u32 addr);
++
++int ispresizer_config_outlineoffset(u32 offset);
++
++int ispresizer_set_outaddr(u32 addr);
++
++void ispresizer_enable(int enable);
++
++void ispresizer_suspend(void);
++
++void ispresizer_resume(void);
++
++int ispresizer_busy(void);
++
++void ispresizer_save_context(void);
++
++void ispresizer_restore_context(void);
++
++void ispresizer_print_status(void);
++
++#endif		/* OMAP_ISP_RESIZER_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0006-omap3isp-Add-statistics-collection-modules-H3A-and.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0006-omap3isp-Add-statistics-collection-modules-H3A-and.patch
new file mode 100644
index 0000000000..876ce780f0
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0006-omap3isp-Add-statistics-collection-modules-H3A-and.patch
@@ -0,0 +1,2741 @@
+From 9a39eab5ed1b70711c3b10de95cd90749293ef7a Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:02 +0200
+Subject: [PATCH] omap3isp: Add statistics collection modules (H3A and HIST)
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ drivers/media/video/isp/isp_af.c  |  784 +++++++++++++++++++++++++++++++
+ drivers/media/video/isp/isp_af.h  |  125 +++++
+ drivers/media/video/isp/isph3a.c  |  932 +++++++++++++++++++++++++++++++++++++
+ drivers/media/video/isp/isph3a.h  |  127 +++++
+ drivers/media/video/isp/isphist.c |  608 ++++++++++++++++++++++++
+ drivers/media/video/isp/isphist.h |  105 +++++
+ 6 files changed, 2681 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/isp/isp_af.c
+ create mode 100644 drivers/media/video/isp/isp_af.h
+ create mode 100644 drivers/media/video/isp/isph3a.c
+ create mode 100644 drivers/media/video/isp/isph3a.h
+ create mode 100644 drivers/media/video/isp/isphist.c
+ create mode 100644 drivers/media/video/isp/isphist.h
+
+diff --git a/drivers/media/video/isp/isp_af.c b/drivers/media/video/isp/isp_af.c
+new file mode 100644
+index 0000000..a607b97
+--- /dev/null
++++ b/drivers/media/video/isp/isp_af.c
+@@ -0,0 +1,784 @@
++/*
++ * isp_af.c
++ *
++ * AF module for TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *	Troy Laramy
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++/* Linux specific include files */
++#include <asm/cacheflush.h>
++
++#include <linux/uaccess.h>
++#include <linux/dma-mapping.h>
++#include <asm/atomic.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "isph3a.h"
++#include "isp_af.h"
++#include "ispmmu.h"
++
++/**
++ * struct isp_af_buffer - AF frame stats buffer.
++ * @virt_addr: Virtual address to mmap the buffer.
++ * @phy_addr: Physical address of the buffer.
++ * @addr_align: Virtual Address 32 bytes aligned.
++ * @ispmmu_addr: Address of the buffer mapped by the ISPMMU.
++ * @mmap_addr: Mapped memory area of buffer. For userspace access.
++ * @locked: 1 - Buffer locked from write. 0 - Buffer can be overwritten.
++ * @frame_num: Frame number from which the statistics are taken.
++ * @lens_position: Lens position currently set in the DW9710 Coil motor driver.
++ * @next: Pointer to link next buffer.
++ */
++struct isp_af_buffer {
++	unsigned long virt_addr;
++	unsigned long phy_addr;
++	unsigned long addr_align;
++	unsigned long ispmmu_addr;
++	unsigned long mmap_addr;
++
++	u8 locked;
++	u16 frame_num;
++	u32 config_counter;
++	struct isp_af_xtrastats xtrastats;
++	struct isp_af_buffer *next;
++};
++
++/**
++ * struct isp_af_status - AF status.
++ * @initialized: 1 - Buffers initialized.
++ * @update: 1 - Update registers.
++ * @stats_req: 1 - Future stats requested.
++ * @stats_done: 1 - Stats ready for user.
++ * @frame_req: Number of frame requested for statistics.
++ * @af_buff: Array of statistics buffers to access.
++ * @stats_buf_size: Statistics buffer size.
++ * @curr_cfg_buf_size: Current user configured stats buff size.
++ * @min_buf_size: Minimum statisitics buffer size.
++ * @frame_count: Frame Count.
++ * @stats_wait: Wait primitive for locking/unlocking the stats request.
++ * @buffer_lock: Spinlock for statistics buffers access.
++ */
++static struct isp_af_status {
++	u8 initialized;
++	u8 update;
++	u8 stats_req;
++	u8 stats_done;
++	u16 frame_req;
++
++	struct isp_af_buffer af_buff[H3A_MAX_BUFF];
++	unsigned int stats_buf_size;
++	unsigned int min_buf_size;
++	unsigned int curr_cfg_buf_size;
++
++	int pm_state;
++	u32 frame_count;
++	wait_queue_head_t stats_wait;
++	atomic_t config_counter;
++	spinlock_t buffer_lock;		/* For stats buffers read/write sync */
++} afstat;
++
++struct af_device *af_dev_configptr;
++static struct isp_af_buffer *active_buff;
++static int af_major = -1;
++static int camnotify;
++
++/**
++ * isp_af_setxtrastats - Receives extra statistics from prior frames.
++ * @xtrastats: Pointer to structure containing extra statistics fields like
++ *             field count and timestamp of frame.
++ *
++ * Called from update_vbq in camera driver
++ **/
++void isp_af_setxtrastats(struct isp_af_xtrastats *xtrastats, u8 updateflag)
++{
++	int i, past_i;
++
++	if (active_buff == NULL)
++		return;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if (afstat.af_buff[i].frame_num == active_buff->frame_num)
++			break;
++	}
++
++	if (i == H3A_MAX_BUFF)
++		return;
++
++	if (i == 0) {
++		if (afstat.af_buff[H3A_MAX_BUFF - 1].locked == 0)
++			past_i = H3A_MAX_BUFF - 1;
++		else
++			past_i = H3A_MAX_BUFF - 2;
++	} else if (i == 1) {
++		if (afstat.af_buff[0].locked == 0)
++			past_i = 0;
++		else
++			past_i = H3A_MAX_BUFF - 1;
++	} else {
++		if (afstat.af_buff[i - 1].locked == 0)
++			past_i = i - 1;
++		else
++			past_i = i - 2;
++	}
++
++	if (updateflag & AF_UPDATEXS_TS)
++		afstat.af_buff[past_i].xtrastats.ts = xtrastats->ts;
++
++	if (updateflag & AF_UPDATEXS_FIELDCOUNT)
++		afstat.af_buff[past_i].xtrastats.field_count =
++			xtrastats->field_count;
++}
++EXPORT_SYMBOL(isp_af_setxtrastats);
++
++/*
++ * Helper function to update buffer cache pages
++ */
++static void isp_af_update_req_buffer(struct isp_af_buffer *buffer)
++{
++	int size = afstat.stats_buf_size;
++
++	size = PAGE_ALIGN(size);
++	/* Update the kernel pages of the requested buffer */
++	dmac_inv_range((void *)buffer->addr_align, (void *)buffer->addr_align +
++		       size);
++}
++
++#define IS_OUT_OF_BOUNDS(value, min, max)		\
++	(((value) < (min)) || ((value) > (max)))
++
++/* Function to check paxel parameters */
++int isp_af_check_paxel(void)
++{
++	struct af_paxel *paxel_cfg = &af_dev_configptr->config->paxel_config;
++	struct af_iir *iir_cfg = &af_dev_configptr->config->iir_config;
++
++	/* Check horizontal Count */
++	if (IS_OUT_OF_BOUNDS(paxel_cfg->hz_cnt, AF_PAXEL_HORIZONTAL_COUNT_MIN,
++			     AF_PAXEL_HORIZONTAL_COUNT_MAX)) {
++		DPRINTK_ISP_AF("Error : Horizontal Count is incorrect");
++		return -AF_ERR_HZ_COUNT;
++	}
++
++	/*Check Vertical Count */
++	if (IS_OUT_OF_BOUNDS(paxel_cfg->vt_cnt, AF_PAXEL_VERTICAL_COUNT_MIN,
++			     AF_PAXEL_VERTICAL_COUNT_MAX)) {
++		DPRINTK_ISP_AF("Error : Vertical Count is incorrect");
++		return -AF_ERR_VT_COUNT;
++	}
++
++	/*Check Height */
++	if (IS_OUT_OF_BOUNDS(paxel_cfg->height, AF_PAXEL_HEIGHT_MIN,
++			     AF_PAXEL_HEIGHT_MAX)) {
++		DPRINTK_ISP_AF("Error : Height is incorrect");
++		return -AF_ERR_HEIGHT;
++	}
++
++	/*Check width */
++	if (IS_OUT_OF_BOUNDS(paxel_cfg->width, AF_PAXEL_WIDTH_MIN,
++			     AF_PAXEL_WIDTH_MAX)) {
++		DPRINTK_ISP_AF("Error : Width is incorrect");
++		return -AF_ERR_WIDTH;
++	}
++
++	/*Check Line Increment */
++	if (IS_OUT_OF_BOUNDS(paxel_cfg->line_incr, AF_PAXEL_INCREMENT_MIN,
++			     AF_PAXEL_INCREMENT_MAX)) {
++		DPRINTK_ISP_AF("Error : Line Increment is incorrect");
++		return -AF_ERR_INCR;
++	}
++
++	/*Check Horizontal Start */
++	if ((paxel_cfg->hz_start % 2 != 0) ||
++	    (paxel_cfg->hz_start < (iir_cfg->hz_start_pos + 2)) ||
++	    IS_OUT_OF_BOUNDS(paxel_cfg->hz_start,
++			     AF_PAXEL_HZSTART_MIN, AF_PAXEL_HZSTART_MAX)) {
++		DPRINTK_ISP_AF("Error : Horizontal Start is incorrect");
++		return -AF_ERR_HZ_START;
++	}
++
++	/*Check Vertical Start */
++	if (IS_OUT_OF_BOUNDS(paxel_cfg->vt_start, AF_PAXEL_VTSTART_MIN,
++			     AF_PAXEL_VTSTART_MAX)) {
++		DPRINTK_ISP_AF("Error : Vertical Start is incorrect");
++		return -AF_ERR_VT_START;
++	}
++	return 0;
++}
++
++/**
++ * isp_af_check_iir - Function to check IIR Coefficient.
++ **/
++int isp_af_check_iir(void)
++{
++	struct af_iir *iir_cfg = &af_dev_configptr->config->iir_config;
++	int index;
++
++	for (index = 0; index < AF_NUMBER_OF_COEF; index++) {
++		if ((iir_cfg->coeff_set0[index]) > AF_COEF_MAX) {
++			DPRINTK_ISP_AF("Error : Coefficient for set 0 is "
++				       "incorrect");
++			return -AF_ERR_IIR_COEF;
++		}
++
++		if ((iir_cfg->coeff_set1[index]) > AF_COEF_MAX) {
++			DPRINTK_ISP_AF("Error : Coefficient for set 1 is "
++				       "incorrect");
++			return -AF_ERR_IIR_COEF;
++		}
++	}
++
++	if (IS_OUT_OF_BOUNDS(iir_cfg->hz_start_pos, AF_IIRSH_MIN,
++			     AF_IIRSH_MAX)) {
++		DPRINTK_ISP_AF("Error : IIRSH is incorrect");
++		return -AF_ERR_IIRSH;
++	}
++
++	return 0;
++}
++/**
++ * isp_af_unlock_buffers - Helper function to unlock all buffers.
++ **/
++static void isp_af_unlock_buffers(void)
++{
++	int i;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&afstat.buffer_lock, irqflags);
++	for (i = 0; i < H3A_MAX_BUFF; i++)
++		afstat.af_buff[i].locked = 0;
++
++	spin_unlock_irqrestore(&afstat.buffer_lock, irqflags);
++}
++
++/*
++ * Helper function to link allocated buffers
++ */
++static void isp_af_link_buffers(void)
++{
++	int i;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if ((i + 1) < H3A_MAX_BUFF)
++			afstat.af_buff[i].next = &afstat.af_buff[i + 1];
++		else
++			afstat.af_buff[i].next = &afstat.af_buff[0];
++	}
++}
++
++/* Function to perform hardware set up */
++int isp_af_configure(struct af_configuration *afconfig)
++{
++	int result;
++	int buff_size, i;
++	unsigned int busyaf;
++	struct af_configuration *af_curr_cfg = af_dev_configptr->config;
++
++	if (NULL == afconfig) {
++		printk(KERN_ERR "Null argument in configuration. \n");
++		return -EINVAL;
++	}
++
++	memcpy(af_curr_cfg, afconfig, sizeof(struct af_configuration));
++	/* Get the value of PCR register */
++	busyaf = isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR);
++
++	if ((busyaf & AF_BUSYAF) == AF_BUSYAF) {
++		DPRINTK_ISP_AF("AF_register_setup_ERROR : Engine Busy");
++		DPRINTK_ISP_AF("\n Configuration cannot be done ");
++		return -AF_ERR_ENGINE_BUSY;
++	}
++
++	/* Check IIR Coefficient and start Values */
++	result = isp_af_check_iir();
++	if (result < 0)
++		return result;
++
++	/* Check Paxel Values */
++	result = isp_af_check_paxel();
++	if (result < 0)
++		return result;
++
++	/* Check HMF Threshold Values */
++	if (af_curr_cfg->hmf_config.threshold > AF_THRESHOLD_MAX) {
++		DPRINTK_ISP_AF("Error : HMF Threshold is incorrect");
++		return -AF_ERR_THRESHOLD;
++	}
++
++	/* Compute buffer size */
++	buff_size = (af_curr_cfg->paxel_config.hz_cnt + 1) *
++		(af_curr_cfg->paxel_config.vt_cnt + 1) * AF_PAXEL_SIZE;
++
++	afstat.curr_cfg_buf_size = buff_size;
++	/* Deallocate the previous buffers */
++	if (afstat.stats_buf_size && buff_size > afstat.stats_buf_size) {
++		isp_af_enable(0);
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			ispmmu_kunmap(afstat.af_buff[i].ispmmu_addr);
++			dma_free_coherent(
++				NULL, afstat.min_buf_size,
++				(void *)afstat.af_buff[i].virt_addr,
++				(dma_addr_t)afstat.af_buff[i].phy_addr);
++			afstat.af_buff[i].virt_addr = 0;
++		}
++		afstat.stats_buf_size = 0;
++	}
++
++	if (!afstat.af_buff[0].virt_addr) {
++		afstat.stats_buf_size = buff_size;
++		afstat.min_buf_size = PAGE_ALIGN(afstat.stats_buf_size);
++
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			afstat.af_buff[i].virt_addr =
++				(unsigned long)dma_alloc_coherent(
++					NULL,
++					afstat.min_buf_size,
++					(dma_addr_t *)
++					&afstat.af_buff[i].phy_addr,
++					GFP_KERNEL | GFP_DMA);
++			if (afstat.af_buff[i].virt_addr == 0) {
++				printk(KERN_ERR "Can't acquire memory for "
++				       "buffer[%d]\n", i);
++				return -ENOMEM;
++			}
++			afstat.af_buff[i].addr_align =
++				afstat.af_buff[i].virt_addr;
++			while ((afstat.af_buff[i].addr_align & 0xFFFFFFC0) !=
++			       afstat.af_buff[i].addr_align)
++				afstat.af_buff[i].addr_align++;
++			afstat.af_buff[i].ispmmu_addr =
++				ispmmu_kmap(afstat.af_buff[i].phy_addr,
++					    afstat.min_buf_size);
++		}
++		isp_af_unlock_buffers();
++		isp_af_link_buffers();
++
++		/* First active buffer */
++		if (active_buff == NULL)
++			active_buff = &afstat.af_buff[0];
++		isp_af_set_address(active_buff->ispmmu_addr);
++	}
++
++	result = isp_af_register_setup(af_dev_configptr);
++	if (result < 0)
++		return result;
++	af_dev_configptr->size_paxel = buff_size;
++	atomic_inc(&afstat.config_counter);
++	afstat.initialized = 1;
++	afstat.frame_count = 1;
++	active_buff->frame_num = 1;
++	/* Set configuration flag to indicate HW setup done */
++	if (af_curr_cfg->af_config)
++		isp_af_enable(1);
++	else
++		isp_af_enable(0);
++
++	/* Success */
++	return 0;
++}
++EXPORT_SYMBOL(isp_af_configure);
++
++int isp_af_register_setup(struct af_device *af_dev)
++{
++	unsigned int pcr = 0, pax1 = 0, pax2 = 0, paxstart = 0;
++	unsigned int coef = 0;
++	unsigned int base_coef_set0 = 0;
++	unsigned int base_coef_set1 = 0;
++	int index;
++
++	/* Configure Hardware Registers */
++	/* Read PCR Register */
++	pcr = isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR);
++
++	/* Set Accumulator Mode */
++	if (af_dev->config->mode == ACCUMULATOR_PEAK)
++		pcr |= FVMODE;
++	else
++		pcr &= ~FVMODE;
++
++	/* Set A-law */
++	if (af_dev->config->alaw_enable == H3A_AF_ALAW_ENABLE)
++		pcr |= AF_ALAW_EN;
++	else
++		pcr &= ~AF_ALAW_EN;
++
++	/* Set RGB Position */
++	pcr &= ~RGBPOS;
++	pcr |= af_dev->config->rgb_pos << AF_RGBPOS_SHIFT;
++
++	/* HMF Configurations */
++	if (af_dev->config->hmf_config.enable == H3A_AF_HMF_ENABLE) {
++		pcr &= ~AF_MED_EN;
++		/* Enable HMF */
++		pcr |= AF_MED_EN;
++
++		/* Set Median Threshold */
++		pcr &= ~MED_TH;
++		pcr |= af_dev->config->hmf_config.threshold << AF_MED_TH_SHIFT;
++	} else
++		pcr &= ~AF_MED_EN;
++
++	/* Set PCR Register */
++	isp_reg_writel(pcr, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR);
++
++	pax1 &= ~PAXW;
++	pax1 |= af_dev->config->paxel_config.width << AF_PAXW_SHIFT;
++
++	/* Set height in AFPAX1 */
++	pax1 &= ~PAXH;
++	pax1 |= af_dev->config->paxel_config.height;
++
++	isp_reg_writel(pax1, OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAX1);
++
++	/* Configure AFPAX2 Register */
++	/* Set Line Increment in AFPAX2 Register */
++	pax2 &= ~AFINCV;
++	pax2 |= af_dev->config->paxel_config.line_incr << AF_LINE_INCR_SHIFT;
++	/* Set Vertical Count */
++	pax2 &= ~PAXVC;
++	pax2 |= af_dev->config->paxel_config.vt_cnt << AF_VT_COUNT_SHIFT;
++	/* Set Horizontal Count */
++	pax2 &= ~PAXHC;
++	pax2 |= af_dev->config->paxel_config.hz_cnt;
++	isp_reg_writel(pax2, OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAX2);
++
++	/* Configure PAXSTART Register */
++	/*Configure Horizontal Start */
++	paxstart &= ~PAXSH;
++	paxstart |= af_dev->config->paxel_config.hz_start << AF_HZ_START_SHIFT;
++	/* Configure Vertical Start */
++	paxstart &= ~PAXSV;
++	paxstart |= af_dev->config->paxel_config.vt_start;
++	isp_reg_writel(paxstart, OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAXSTART);
++
++	/*SetIIRSH Register */
++	isp_reg_writel(af_dev->config->iir_config.hz_start_pos,
++		       OMAP3_ISP_IOMEM_H3A, ISPH3A_AFIIRSH);
++
++	/*Set IIR Filter0 Coefficients */
++	base_coef_set0 = ISPH3A_AFCOEF010;
++	for (index = 0; index <= 8; index += 2) {
++		coef &= ~COEF_MASK0;
++		coef |= af_dev->config->iir_config.coeff_set0[index];
++		coef &= ~COEF_MASK1;
++		coef |= af_dev->config->iir_config.coeff_set0[index + 1] <<
++			AF_COEF_SHIFT;
++		isp_reg_writel(coef, OMAP3_ISP_IOMEM_H3A, base_coef_set0);
++		base_coef_set0 = base_coef_set0 + AFCOEF_OFFSET;
++	}
++
++	/* set AFCOEF0010 Register */
++	isp_reg_writel(af_dev->config->iir_config.coeff_set0[10],
++		       OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF010);
++
++	/*Set IIR Filter1 Coefficients */
++
++	base_coef_set1 = ISPH3A_AFCOEF110;
++	for (index = 0; index <= 8; index += 2) {
++		coef &= ~COEF_MASK0;
++		coef |= af_dev->config->iir_config.coeff_set1[index];
++		coef &= ~COEF_MASK1;
++		coef |= af_dev->config->iir_config.coeff_set1[index + 1] <<
++			AF_COEF_SHIFT;
++		isp_reg_writel(coef, OMAP3_ISP_IOMEM_H3A, base_coef_set1);
++
++		base_coef_set1 = base_coef_set1 + AFCOEF_OFFSET;
++	}
++	isp_reg_writel(af_dev->config->iir_config.coeff_set1[10],
++		       OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF1010);
++
++	return 0;
++}
++
++/* Function to set address */
++void isp_af_set_address(unsigned long address)
++{
++	isp_reg_writel(address, OMAP3_ISP_IOMEM_H3A, ISPH3A_AFBUFST);
++}
++
++static int isp_af_stats_available(struct isp_af_data *afdata)
++{
++	int i, ret;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&afstat.buffer_lock, irqflags);
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		DPRINTK_ISP_AF("Checking Stats buff[%d] (%d) for %d\n",
++			       i, afstat.af_buff[i].frame_num,
++			       afdata->frame_number);
++		if (afdata->frame_number == afstat.af_buff[i].frame_num
++		    && afstat.af_buff[i].frame_num != active_buff->frame_num) {
++			afstat.af_buff[i].locked = 1;
++			spin_unlock_irqrestore(&afstat.buffer_lock, irqflags);
++			isp_af_update_req_buffer(&afstat.af_buff[i]);
++			afstat.af_buff[i].frame_num = 0;
++			ret = copy_to_user((void *)afdata->af_statistics_buf,
++					   (void *)afstat.af_buff[i].virt_addr,
++					   afstat.curr_cfg_buf_size);
++			if (ret) {
++				printk(KERN_ERR "Failed copy_to_user for "
++				       "H3A stats buff, %d\n", ret);
++			}
++			afdata->xtrastats.ts = afstat.af_buff[i].xtrastats.ts;
++			afdata->xtrastats.field_count =
++				afstat.af_buff[i].xtrastats.field_count;
++			return 0;
++		}
++	}
++	spin_unlock_irqrestore(&afstat.buffer_lock, irqflags);
++	/* Stats unavailable */
++
++	return -1;
++}
++
++void isp_af_notify(int notify)
++{
++	camnotify = notify;
++	if (camnotify && afstat.initialized) {
++		printk(KERN_DEBUG "Warning Camera Off \n");
++		afstat.stats_req = 0;
++		afstat.stats_done = 1;
++		wake_up_interruptible(&afstat.stats_wait);
++	}
++}
++EXPORT_SYMBOL(isp_af_notify);
++/*
++ * This API allows the user to update White Balance gains, as well as
++ * exposure time and analog gain. It is also used to request frame
++ * statistics.
++ */
++int isp_af_request_statistics(struct isp_af_data *afdata)
++{
++	int ret = 0;
++	u16 frame_diff = 0;
++	u16 frame_cnt = afstat.frame_count;
++	wait_queue_t wqt;
++
++	if (!af_dev_configptr->config->af_config) {
++		printk(KERN_ERR "AF engine not enabled\n");
++		return -EINVAL;
++	}
++
++	if (!(afdata->update & REQUEST_STATISTICS)) {
++		afdata->af_statistics_buf = NULL;
++		goto out;
++	}
++
++	isp_af_unlock_buffers();
++	/* Stats available? */
++	DPRINTK_ISP_AF("Stats available?\n");
++	ret = isp_af_stats_available(afdata);
++	if (!ret)
++		goto out;
++
++	/* Stats in near future? */
++	DPRINTK_ISP_AF("Stats in near future?\n");
++	if (afdata->frame_number > frame_cnt)
++		frame_diff = afdata->frame_number - frame_cnt;
++	else if (afdata->frame_number < frame_cnt) {
++		if (frame_cnt > MAX_FRAME_COUNT - MAX_FUTURE_FRAMES
++		    && afdata->frame_number < MAX_FRAME_COUNT) {
++			frame_diff = afdata->frame_number + MAX_FRAME_COUNT -
++				frame_cnt;
++		} else {
++			/* Frame unavailable */
++			frame_diff = MAX_FUTURE_FRAMES + 1;
++		}
++	}
++
++	if (frame_diff > MAX_FUTURE_FRAMES) {
++		printk(KERN_ERR "Invalid frame requested, returning current"
++		       " frame stats\n");
++		afdata->frame_number = frame_cnt;
++	}
++	if (!camnotify) {
++		/* Block until frame in near future completes */
++		afstat.frame_req = afdata->frame_number;
++		afstat.stats_req = 1;
++		afstat.stats_done = 0;
++		init_waitqueue_entry(&wqt, current);
++		ret = wait_event_interruptible(afstat.stats_wait,
++					       afstat.stats_done == 1);
++		if (ret < 0) {
++			afdata->af_statistics_buf = NULL;
++			return ret;
++		}
++		DPRINTK_ISP_AF("ISP AF request status interrupt raised\n");
++
++		/* Stats now available */
++		ret = isp_af_stats_available(afdata);
++		if (ret) {
++			printk(KERN_ERR "After waiting for stats, stats not"
++			       " available!!\n");
++			afdata->af_statistics_buf = NULL;
++		}
++	}
++
++out:
++	afdata->curr_frame = afstat.frame_count;
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_af_request_statistics);
++
++/* This function will handle the H3A interrupt. */
++static void isp_af_isr(unsigned long status, isp_vbq_callback_ptr arg1,
++		       void *arg2)
++{
++	u16 frame_align;
++
++	if ((H3A_AF_DONE & status) != H3A_AF_DONE)
++		return;
++
++	/* timestamp stats buffer */
++	do_gettimeofday(&active_buff->xtrastats.ts);
++	active_buff->config_counter = atomic_read(&afstat.config_counter);
++
++	/* Exchange buffers */
++	active_buff = active_buff->next;
++	if (active_buff->locked == 1)
++		active_buff = active_buff->next;
++	isp_af_set_address(active_buff->ispmmu_addr);
++
++	/* Update frame counter */
++	afstat.frame_count++;
++	frame_align = afstat.frame_count;
++	if (afstat.frame_count > MAX_FRAME_COUNT) {
++		afstat.frame_count = 1;
++		frame_align++;
++	}
++	active_buff->frame_num = afstat.frame_count;
++
++	/* Future Stats requested? */
++	if (afstat.stats_req) {
++		/* Is the frame we want already done? */
++		if (frame_align >= afstat.frame_req + 1) {
++			afstat.stats_req = 0;
++			afstat.stats_done = 1;
++			wake_up_interruptible(&afstat.stats_wait);
++		}
++	}
++}
++
++int __isp_af_enable(int enable)
++{
++	unsigned int pcr;
++
++	pcr = isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR);
++
++	/* Set AF_EN bit in PCR Register */
++	if (enable) {
++		if (isp_set_callback(CBK_H3A_AF_DONE, isp_af_isr,
++				     (void *)NULL, (void *)NULL)) {
++			printk(KERN_ERR "No callback for AF\n");
++			return -EINVAL;
++		}
++
++		pcr |= AF_EN;
++	} else {
++		isp_unset_callback(CBK_H3A_AF_DONE);
++		pcr &= ~AF_EN;
++	}
++	isp_reg_writel(pcr, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR);
++	return 0;
++}
++
++/* Function to Enable/Disable AF Engine */
++int isp_af_enable(int enable)
++{
++	int rval;
++
++	rval = __isp_af_enable(enable);
++
++	if (!rval)
++		afstat.pm_state = enable;
++
++	return rval;
++}
++
++/* Function to Suspend AF Engine */
++void isp_af_suspend(void)
++{
++	if (afstat.pm_state)
++		__isp_af_enable(0);
++}
++
++/* Function to Resume AF Engine */
++void isp_af_resume(void)
++{
++	if (afstat.pm_state)
++		__isp_af_enable(1);
++}
++
++int isp_af_busy(void)
++{
++	return isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR)
++		& ISPH3A_PCR_BUSYAF;
++}
++
++/* Function to register the AF character device driver. */
++int __init isp_af_init(void)
++{
++	/*allocate memory for device structure and initialize it with 0 */
++	af_dev_configptr = kzalloc(sizeof(struct af_device), GFP_KERNEL);
++	if (!af_dev_configptr)
++		goto err_nomem1;
++
++	active_buff = NULL;
++
++	af_dev_configptr->config = (struct af_configuration *)
++		kzalloc(sizeof(struct af_configuration), GFP_KERNEL);
++
++	if (af_dev_configptr->config == NULL)
++		goto err_nomem2;
++
++	memset(&afstat, 0, sizeof(afstat));
++
++	init_waitqueue_head(&afstat.stats_wait);
++	spin_lock_init(&afstat.buffer_lock);
++
++	return 0;
++
++err_nomem2:
++	kfree(af_dev_configptr);
++err_nomem1:
++	printk(KERN_ERR "Error: kmalloc fail");
++	return -ENOMEM;
++}
++
++void isp_af_exit(void)
++{
++	int i;
++
++	/* Free buffers */
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if (!afstat.af_buff[i].phy_addr)
++			continue;
++
++		ispmmu_kunmap(afstat.af_buff[i].ispmmu_addr);
++
++		dma_free_coherent(NULL,
++				  afstat.min_buf_size,
++				  (void *)afstat.af_buff[i].virt_addr,
++				  (dma_addr_t)afstat.af_buff[i].phy_addr);
++	}
++	kfree(af_dev_configptr->config);
++	kfree(af_dev_configptr);
++
++	memset(&afstat, 0, sizeof(afstat));
++
++	af_major = -1;
++}
+diff --git a/drivers/media/video/isp/isp_af.h b/drivers/media/video/isp/isp_af.h
+new file mode 100644
+index 0000000..ee2b89f
+--- /dev/null
++++ b/drivers/media/video/isp/isp_af.h
+@@ -0,0 +1,125 @@
++/*
++ * isp_af.h
++ *
++ * Include file for AF module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *	Troy Laramy
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++/* Device Constants */
++#ifndef OMAP_ISP_AF_H
++#define OMAP_ISP_AF_H
++
++#include <mach/isp_user.h>
++
++#define AF_MAJOR_NUMBER			0
++#define ISPAF_NAME			"OMAPISP_AF"
++#define AF_NR_DEVS			1
++#define AF_TIMEOUT			((300 * HZ) / 1000)
++
++
++
++/* Print Macros */
++/*list of error code */
++#define AF_ERR_HZ_COUNT			800	/* Invalid Horizontal Count */
++#define AF_ERR_VT_COUNT			801	/* Invalid Vertical Count */
++#define AF_ERR_HEIGHT			802	/* Invalid Height */
++#define AF_ERR_WIDTH			803	/* Invalid width */
++#define AF_ERR_INCR			804	/* Invalid Increment */
++#define AF_ERR_HZ_START			805	/* Invalid horizontal Start */
++#define AF_ERR_VT_START			806	/* Invalud vertical Start */
++#define AF_ERR_IIRSH			807	/* Invalid IIRSH value */
++#define AF_ERR_IIR_COEF			808	/* Invalid Coefficient */
++#define AF_ERR_SETUP			809	/* Setup not done */
++#define AF_ERR_THRESHOLD		810	/* Invalid Threshold */
++#define AF_ERR_ENGINE_BUSY		811	/* Engine is busy */
++
++#define AFPID				0x0	/* Peripheral Revision
++						 * and Class Information
++						 */
++
++#define AFCOEF_OFFSET			0x00000004	/* COEFFICIENT BASE
++							 * ADDRESS
++							 */
++
++/*
++ * PCR fields
++ */
++#define AF_BUSYAF			(1 << 15)
++#define FVMODE				(1 << 14)
++#define RGBPOS				(0x7 << 11)
++#define MED_TH				(0xFF << 3)
++#define AF_MED_EN			(1 << 2)
++#define AF_ALAW_EN			(1 << 1)
++#define AF_EN				(1 << 0)
++
++/*
++ * AFPAX1 fields
++ */
++#define PAXW				(0x7F << 16)
++#define PAXH				0x7F
++
++/*
++ * AFPAX2 fields
++ */
++#define AFINCV				(0xF << 13)
++#define PAXVC				(0x7F << 6)
++#define PAXHC				0x3F
++
++/*
++ * AFPAXSTART fields
++ */
++#define PAXSH				(0xFFF<<16)
++#define PAXSV				0xFFF
++
++/*
++ * COEFFICIENT MASK
++ */
++
++#define COEF_MASK0			0xFFF
++#define COEF_MASK1			(0xFFF<<16)
++
++/* BIT SHIFTS */
++#define AF_RGBPOS_SHIFT			11
++#define AF_MED_TH_SHIFT			3
++#define AF_PAXW_SHIFT			16
++#define AF_LINE_INCR_SHIFT		13
++#define AF_VT_COUNT_SHIFT		6
++#define AF_HZ_START_SHIFT		16
++#define AF_COEF_SHIFT			16
++
++#define AF_UPDATEXS_TS			(1 << 0)
++#define AF_UPDATEXS_FIELDCOUNT	(1 << 1)
++#define AF_UPDATEXS_LENSPOS		(1 << 2)
++
++/* Structure for device of AF Engine */
++struct af_device {
++	struct af_configuration *config; /*Device configuration structure */
++	int size_paxel;		/*Paxel size in bytes */
++};
++
++int isp_af_check_paxel(void);
++int isp_af_check_iir(void);
++int isp_af_register_setup(struct af_device *af_dev);
++int isp_af_enable(int);
++void isp_af_suspend(void);
++void isp_af_resume(void);
++int isp_af_busy(void);
++void isp_af_notify(int notify);
++int isp_af_request_statistics(struct isp_af_data *afdata);
++int isp_af_configure(struct af_configuration *afconfig);
++void isp_af_set_address(unsigned long);
++void isp_af_setxtrastats(struct isp_af_xtrastats *xtrastats, u8 updateflag);
++#endif	/* OMAP_ISP_AF_H */
+diff --git a/drivers/media/video/isp/isph3a.c b/drivers/media/video/isp/isph3a.c
+new file mode 100644
+index 0000000..7ff1c5b
+--- /dev/null
++++ b/drivers/media/video/isp/isph3a.c
+@@ -0,0 +1,932 @@
++/*
++ * isph3a.c
++ *
++ * H3A module for TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *	Troy Laramy
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <asm/cacheflush.h>
++
++#include <linux/dma-mapping.h>
++#include <linux/uaccess.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "isph3a.h"
++#include "ispmmu.h"
++#include "isppreview.h"
++
++/**
++ * struct isph3a_aewb_buffer - AE, AWB frame stats buffer.
++ * @virt_addr: Virtual address to mmap the buffer.
++ * @phy_addr: Physical address of the buffer.
++ * @addr_align: Virtual Address 32 bytes aligned.
++ * @ispmmu_addr: Address of the buffer mapped by the ISPMMU.
++ * @mmap_addr: Mapped memory area of buffer. For userspace access.
++ * @locked: 1 - Buffer locked from write. 0 - Buffer can be overwritten.
++ * @frame_num: Frame number from which the statistics are taken.
++ * @next: Pointer to link next buffer.
++ */
++struct isph3a_aewb_buffer {
++	unsigned long virt_addr;
++	unsigned long phy_addr;
++	unsigned long addr_align;
++	unsigned long ispmmu_addr;
++	unsigned long mmap_addr;	/* For userspace */
++	struct timeval ts;
++	u32 config_counter;
++
++	u8 locked;
++	u16 frame_num;
++	struct isph3a_aewb_buffer *next;
++};
++
++/**
++ * struct isph3a_aewb_status - AE, AWB status.
++ * @initialized: 1 - Buffers initialized.
++ * @update: 1 - Update registers.
++ * @stats_req: 1 - Future stats requested.
++ * @stats_done: 1 - Stats ready for user.
++ * @frame_req: Number of frame requested for statistics.
++ * @h3a_buff: Array of statistics buffers to access.
++ * @stats_buf_size: Statistics buffer size.
++ * @min_buf_size: Minimum statisitics buffer size.
++ * @win_count: Window Count.
++ * @frame_count: Frame Count.
++ * @stats_wait: Wait primitive for locking/unlocking the stats request.
++ * @buffer_lock: Spinlock for statistics buffers access.
++ */
++static struct isph3a_aewb_status {
++	u8 initialized;
++	u8 update;
++	u8 stats_req;
++	u8 stats_done;
++	u16 frame_req;
++	int pm_state;
++
++	struct isph3a_aewb_buffer h3a_buff[H3A_MAX_BUFF];
++	unsigned int stats_buf_size;
++	unsigned int min_buf_size;
++	unsigned int curr_cfg_buf_size;
++
++	atomic_t config_counter;
++
++	u16 win_count;
++	u32 frame_count;
++	wait_queue_head_t stats_wait;
++	spinlock_t buffer_lock;		/* For stats buffers read/write sync */
++} aewbstat;
++
++/**
++ * struct isph3a_aewb_regs - Current value of AE, AWB configuration registers.
++ * reg_pcr: Peripheral control register.
++ * reg_win1: Control register.
++ * reg_start: Start position register.
++ * reg_blk: Black line register.
++ * reg_subwin: Configuration register.
++ */
++static struct isph3a_aewb_regs {
++	u32 reg_pcr;
++	u32 reg_win1;
++	u32 reg_start;
++	u32 reg_blk;
++	u32 reg_subwin;
++} aewb_regs;
++
++static struct isph3a_aewb_config aewb_config_local = {
++	.saturation_limit = 0x3FF,
++	.win_height = 0,
++	.win_width = 0,
++	.ver_win_count = 0,
++	.hor_win_count = 0,
++	.ver_win_start = 0,
++	.hor_win_start = 0,
++	.blk_ver_win_start = 0,
++	.blk_win_height = 0,
++	.subsample_ver_inc = 0,
++	.subsample_hor_inc = 0,
++	.alaw_enable = 0,
++	.aewb_enable = 0,
++};
++
++/* Structure for saving/restoring h3a module registers */
++static struct isp_reg isph3a_reg_list[] = {
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR, 0}, /* Should be the first one */
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWWIN1, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWINSTART, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWINBLK, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWSUBWIN, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWBUFST, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAX1, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAX2, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAXSTART, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFIIRSH, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFBUFST, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF010, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF032, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF054, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF076, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF098, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF0010, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF110, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF132, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF154, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF176, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF198, 0},
++	{OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF1010, 0},
++	{0, ISP_TOK_TERM, 0}
++};
++
++static struct ispprev_wbal h3awb_update;
++static struct isph3a_aewb_buffer *active_buff;
++static struct isph3a_aewb_xtrastats h3a_xtrastats[H3A_MAX_BUFF];
++static int camnotify;
++static int wb_update;
++static void isph3a_print_status(void);
++
++/**
++ * isph3a_aewb_setxtrastats - Receives extra statistics from prior frames.
++ * @xtrastats: Pointer to structure containing extra statistics fields like
++ *             field count and timestamp of frame.
++ *
++ * Called from update_vbq in camera driver
++ **/
++void isph3a_aewb_setxtrastats(struct isph3a_aewb_xtrastats *xtrastats)
++{
++	int i;
++
++	if (active_buff == NULL)
++		return;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if (aewbstat.h3a_buff[i].frame_num != active_buff->frame_num)
++			continue;
++
++		if (i == 0) {
++			if (aewbstat.h3a_buff[H3A_MAX_BUFF - 1].locked == 0) {
++				h3a_xtrastats[H3A_MAX_BUFF - 1] =
++					*xtrastats;
++			} else {
++				h3a_xtrastats[H3A_MAX_BUFF - 2] =
++					*xtrastats;
++			}
++		} else if (i == 1) {
++			if (aewbstat.h3a_buff[0].locked == 0)
++				h3a_xtrastats[0] = *xtrastats;
++			else {
++				h3a_xtrastats[H3A_MAX_BUFF - 1] =
++					*xtrastats;
++			}
++		} else {
++			if (aewbstat.h3a_buff[i - 1].locked == 0)
++				h3a_xtrastats[i - 1] = *xtrastats;
++			else
++				h3a_xtrastats[i - 2] = *xtrastats;
++		}
++		return;
++	}
++}
++EXPORT_SYMBOL(isph3a_aewb_setxtrastats);
++
++void __isph3a_aewb_enable(u8 enable)
++{
++	isp_reg_writel(IRQ0STATUS_H3A_AWB_DONE_IRQ, OMAP3_ISP_IOMEM_MAIN,
++		       ISP_IRQ0STATUS);
++
++	if (enable) {
++		aewb_regs.reg_pcr |= ISPH3A_PCR_AEW_EN;
++		DPRINTK_ISPH3A("    H3A enabled \n");
++	} else {
++		aewb_regs.reg_pcr &= ~ISPH3A_PCR_AEW_EN;
++		DPRINTK_ISPH3A("    H3A disabled \n");
++	}
++	isp_reg_and_or(OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR, ~ISPH3A_PCR_AEW_EN,
++		       (enable ? ISPH3A_PCR_AEW_EN : 0));
++	aewb_config_local.aewb_enable = enable;
++}
++
++/**
++ * isph3a_aewb_enable - Enables AE, AWB engine in the H3A module.
++ * @enable: 1 - Enables the AE & AWB engine.
++ *
++ * Client should configure all the AE & AWB registers in H3A before this.
++ **/
++void isph3a_aewb_enable(u8 enable)
++{
++	__isph3a_aewb_enable(enable);
++	aewbstat.pm_state = enable;
++}
++
++/**
++ * isph3a_aewb_suspend - Suspend AE, AWB engine in the H3A module.
++ **/
++void isph3a_aewb_suspend(void)
++{
++	if (aewbstat.pm_state)
++		__isph3a_aewb_enable(0);
++}
++
++/**
++ * isph3a_aewb_resume - Resume AE, AWB engine in the H3A module.
++ **/
++void isph3a_aewb_resume(void)
++{
++	if (aewbstat.pm_state)
++		__isph3a_aewb_enable(1);
++}
++
++int isph3a_aewb_busy(void)
++{
++	return isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR)
++		& ISPH3A_PCR_BUSYAEAWB;
++}
++
++/**
++ * isph3a_update_wb - Updates WB parameters.
++ *
++ * Needs to be called when no ISP Preview processing is taking place.
++ **/
++void isph3a_update_wb(void)
++{
++	if (wb_update) {
++		isppreview_config_whitebalance(h3awb_update);
++		wb_update = 0;
++	}
++	return;
++}
++EXPORT_SYMBOL(isph3a_update_wb);
++
++/**
++ * isph3a_aewb_update_regs - Helper function to update h3a registers.
++ **/
++static void isph3a_aewb_update_regs(void)
++{
++	isp_reg_writel(aewb_regs.reg_pcr, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR);
++	isp_reg_writel(aewb_regs.reg_win1, OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWWIN1);
++	isp_reg_writel(aewb_regs.reg_start, OMAP3_ISP_IOMEM_H3A,
++		       ISPH3A_AEWINSTART);
++	isp_reg_writel(aewb_regs.reg_blk, OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWINBLK);
++	isp_reg_writel(aewb_regs.reg_subwin, OMAP3_ISP_IOMEM_H3A,
++		       ISPH3A_AEWSUBWIN);
++
++	aewbstat.update = 0;
++	aewbstat.frame_count = 1;
++}
++
++/**
++ * isph3a_aewb_update_req_buffer - Helper function to update buffer cache pages
++ * @buffer: Pointer to structure
++ **/
++static void isph3a_aewb_update_req_buffer(struct isph3a_aewb_buffer *buffer)
++{
++	int size = aewbstat.stats_buf_size;
++
++	size = PAGE_ALIGN(size);
++	dmac_inv_range((void *)buffer->addr_align,
++		       (void *)buffer->addr_align + size);
++}
++
++/**
++ * isph3a_aewb_stats_available - Check for stats available of specified frame.
++ * @aewbdata: Pointer to return AE AWB statistics data
++ *
++ * Returns 0 if successful, or -1 if statistics are unavailable.
++ **/
++static int isph3a_aewb_stats_available(struct isph3a_aewb_data *aewbdata)
++{
++	int i, ret;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&aewbstat.buffer_lock, irqflags);
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		DPRINTK_ISPH3A("Checking Stats buff[%d] (%d) for %d\n",
++			       i, aewbstat.h3a_buff[i].frame_num,
++			       aewbdata->frame_number);
++		if ((aewbdata->frame_number !=
++		     aewbstat.h3a_buff[i].frame_num) ||
++		    (aewbstat.h3a_buff[i].frame_num ==
++		     active_buff->frame_num))
++			continue;
++		aewbstat.h3a_buff[i].locked = 1;
++		spin_unlock_irqrestore(&aewbstat.buffer_lock, irqflags);
++		isph3a_aewb_update_req_buffer(&aewbstat.h3a_buff[i]);
++		aewbstat.h3a_buff[i].frame_num = 0;
++		ret = copy_to_user((void *)aewbdata->h3a_aewb_statistics_buf,
++				   (void *)aewbstat.h3a_buff[i].virt_addr,
++				   aewbstat.curr_cfg_buf_size);
++		if (ret) {
++			printk(KERN_ERR "Failed copy_to_user for "
++			       "H3A stats buff, %d\n", ret);
++		}
++		aewbdata->ts = aewbstat.h3a_buff[i].ts;
++		aewbdata->config_counter = aewbstat.h3a_buff[i].config_counter;
++		aewbdata->field_count = h3a_xtrastats[i].field_count;
++		return 0;
++	}
++	spin_unlock_irqrestore(&aewbstat.buffer_lock, irqflags);
++
++	return -1;
++}
++
++/**
++ * isph3a_aewb_link_buffers - Helper function to link allocated buffers.
++ **/
++static void isph3a_aewb_link_buffers(void)
++{
++	int i;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if ((i + 1) < H3A_MAX_BUFF) {
++			aewbstat.h3a_buff[i].next = &aewbstat.h3a_buff[i + 1];
++			h3a_xtrastats[i].next = &h3a_xtrastats[i + 1];
++		} else {
++			aewbstat.h3a_buff[i].next = &aewbstat.h3a_buff[0];
++			h3a_xtrastats[i].next = &h3a_xtrastats[0];
++		}
++	}
++}
++
++/**
++ * isph3a_aewb_unlock_buffers - Helper function to unlock all buffers.
++ **/
++static void isph3a_aewb_unlock_buffers(void)
++{
++	int i;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&aewbstat.buffer_lock, irqflags);
++	for (i = 0; i < H3A_MAX_BUFF; i++)
++		aewbstat.h3a_buff[i].locked = 0;
++
++	spin_unlock_irqrestore(&aewbstat.buffer_lock, irqflags);
++}
++
++/**
++ * isph3a_aewb_isr - Callback from ISP driver for H3A AEWB interrupt.
++ * @status: IRQ0STATUS in case of MMU error, 0 for H3A interrupt.
++ * @arg1: Not used as of now.
++ * @arg2: Not used as of now.
++ */
++static void isph3a_aewb_isr(unsigned long status, isp_vbq_callback_ptr arg1,
++			    void *arg2)
++{
++	u16 frame_align;
++
++	if ((H3A_AWB_DONE & status) != H3A_AWB_DONE)
++		return;
++
++	do_gettimeofday(&active_buff->ts);
++	active_buff->config_counter = atomic_read(&aewbstat.config_counter);
++	active_buff = active_buff->next;
++	if (active_buff->locked == 1)
++		active_buff = active_buff->next;
++	isp_reg_writel(active_buff->ispmmu_addr, OMAP3_ISP_IOMEM_H3A,
++		       ISPH3A_AEWBUFST);
++
++	aewbstat.frame_count++;
++	frame_align = aewbstat.frame_count;
++	if (aewbstat.frame_count > MAX_FRAME_COUNT) {
++		aewbstat.frame_count = 1;
++		frame_align++;
++	}
++	active_buff->frame_num = aewbstat.frame_count;
++
++	if (aewbstat.stats_req) {
++		DPRINTK_ISPH3A("waiting for frame %d\n", aewbstat.frame_req);
++		if (frame_align >= aewbstat.frame_req + 1) {
++			aewbstat.stats_req = 0;
++			aewbstat.stats_done = 1;
++			wake_up_interruptible(&aewbstat.stats_wait);
++		}
++	}
++
++	if (aewbstat.update)
++		isph3a_aewb_update_regs();
++}
++
++/**
++ * isph3a_aewb_set_params - Helper function to check & store user given params.
++ * @user_cfg: Pointer to AE and AWB parameters struct.
++ *
++ * As most of them are busy-lock registers, need to wait until AEW_BUSY = 0 to
++ * program them during ISR.
++ *
++ * Returns 0 if successful, or -EINVAL if any of the parameters are invalid.
++ **/
++static int isph3a_aewb_set_params(struct isph3a_aewb_config *user_cfg)
++{
++	if (unlikely(user_cfg->saturation_limit > MAX_SATURATION_LIM)) {
++		printk(KERN_ERR "Invalid Saturation_limit: %d\n",
++		       user_cfg->saturation_limit);
++		return -EINVAL;
++	}
++	if (aewb_config_local.saturation_limit != user_cfg->saturation_limit) {
++		WRITE_SAT_LIM(aewb_regs.reg_pcr, user_cfg->saturation_limit);
++		aewb_config_local.saturation_limit =
++			user_cfg->saturation_limit;
++		aewbstat.update = 1;
++	}
++
++	if (aewb_config_local.alaw_enable != user_cfg->alaw_enable) {
++		WRITE_ALAW(aewb_regs.reg_pcr, user_cfg->alaw_enable);
++		aewb_config_local.alaw_enable = user_cfg->alaw_enable;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->win_height < MIN_WIN_H ||
++		     user_cfg->win_height > MAX_WIN_H ||
++		     user_cfg->win_height & 0x01)) {
++		printk(KERN_ERR "Invalid window height: %d\n",
++		       user_cfg->win_height);
++		return -EINVAL;
++	}
++	if (aewb_config_local.win_height != user_cfg->win_height) {
++		WRITE_WIN_H(aewb_regs.reg_win1, user_cfg->win_height);
++		aewb_config_local.win_height = user_cfg->win_height;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->win_width < MIN_WIN_W ||
++		     user_cfg->win_width > MAX_WIN_W ||
++		     user_cfg->win_width & 0x01)) {
++		printk(KERN_ERR "Invalid window width: %d\n",
++		       user_cfg->win_width);
++		return -EINVAL;
++	}
++	if (aewb_config_local.win_width != user_cfg->win_width) {
++		WRITE_WIN_W(aewb_regs.reg_win1, user_cfg->win_width);
++		aewb_config_local.win_width = user_cfg->win_width;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->ver_win_count < 1 ||
++		     user_cfg->ver_win_count > MAX_WINVC)) {
++		printk(KERN_ERR "Invalid vertical window count: %d\n",
++		       user_cfg->ver_win_count);
++		return -EINVAL;
++	}
++	if (aewb_config_local.ver_win_count != user_cfg->ver_win_count) {
++		WRITE_VER_C(aewb_regs.reg_win1, user_cfg->ver_win_count);
++		aewb_config_local.ver_win_count = user_cfg->ver_win_count;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->hor_win_count < 1 ||
++		     user_cfg->hor_win_count > MAX_WINHC)) {
++		printk(KERN_ERR "Invalid horizontal window count: %d\n",
++		       user_cfg->hor_win_count);
++		return -EINVAL;
++	}
++	if (aewb_config_local.hor_win_count != user_cfg->hor_win_count) {
++		WRITE_HOR_C(aewb_regs.reg_win1, user_cfg->hor_win_count);
++		aewb_config_local.hor_win_count	= user_cfg->hor_win_count;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->ver_win_start > MAX_WINSTART)) {
++		printk(KERN_ERR "Invalid vertical window start: %d\n",
++		       user_cfg->ver_win_start);
++		return -EINVAL;
++	}
++	if (aewb_config_local.ver_win_start != user_cfg->ver_win_start) {
++		WRITE_VER_WIN_ST(aewb_regs.reg_start, user_cfg->ver_win_start);
++		aewb_config_local.ver_win_start = user_cfg->ver_win_start;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->hor_win_start > MAX_WINSTART)) {
++		printk(KERN_ERR "Invalid horizontal window start: %d\n",
++		       user_cfg->hor_win_start);
++		return -EINVAL;
++	}
++	if (aewb_config_local.hor_win_start != user_cfg->hor_win_start) {
++		WRITE_HOR_WIN_ST(aewb_regs.reg_start, user_cfg->hor_win_start);
++		aewb_config_local.hor_win_start	= user_cfg->hor_win_start;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->blk_ver_win_start > MAX_WINSTART)) {
++		printk(KERN_ERR "Invalid black vertical window start: %d\n",
++		       user_cfg->blk_ver_win_start);
++		return -EINVAL;
++	}
++	if (aewb_config_local.blk_ver_win_start !=
++	    user_cfg->blk_ver_win_start) {
++		WRITE_BLK_VER_WIN_ST(aewb_regs.reg_blk,
++				     user_cfg->blk_ver_win_start);
++		aewb_config_local.blk_ver_win_start =
++			user_cfg->blk_ver_win_start;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->blk_win_height < MIN_WIN_H ||
++		     user_cfg->blk_win_height > MAX_WIN_H ||
++		     user_cfg->blk_win_height & 0x01)) {
++		printk(KERN_ERR "Invalid black window height: %d\n",
++		       user_cfg->blk_win_height);
++		return -EINVAL;
++	}
++	if (aewb_config_local.blk_win_height != user_cfg->blk_win_height) {
++		WRITE_BLK_WIN_H(aewb_regs.reg_blk, user_cfg->blk_win_height);
++		aewb_config_local.blk_win_height = user_cfg->blk_win_height;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->subsample_ver_inc < MIN_SUB_INC ||
++		     user_cfg->subsample_ver_inc > MAX_SUB_INC ||
++		     user_cfg->subsample_ver_inc & 0x01)) {
++		printk(KERN_ERR "Invalid vertical subsample increment: %d\n",
++		       user_cfg->subsample_ver_inc);
++		return -EINVAL;
++	}
++	if (aewb_config_local.subsample_ver_inc !=
++	    user_cfg->subsample_ver_inc) {
++		WRITE_SUB_VER_INC(aewb_regs.reg_subwin,
++				  user_cfg->subsample_ver_inc);
++		aewb_config_local.subsample_ver_inc =
++			user_cfg->subsample_ver_inc;
++		aewbstat.update = 1;
++	}
++
++	if (unlikely(user_cfg->subsample_hor_inc < MIN_SUB_INC ||
++		     user_cfg->subsample_hor_inc > MAX_SUB_INC ||
++		     user_cfg->subsample_hor_inc & 0x01)) {
++		printk(KERN_ERR "Invalid horizontal subsample increment: %d\n",
++		       user_cfg->subsample_hor_inc);
++		return -EINVAL;
++	}
++	if (aewb_config_local.subsample_hor_inc !=
++	    user_cfg->subsample_hor_inc) {
++		WRITE_SUB_HOR_INC(aewb_regs.reg_subwin,
++				  user_cfg->subsample_hor_inc);
++		aewb_config_local.subsample_hor_inc =
++			user_cfg->subsample_hor_inc;
++		aewbstat.update = 1;
++	}
++
++	if (!aewbstat.initialized || !aewb_config_local.aewb_enable) {
++		isph3a_aewb_update_regs();
++		aewbstat.initialized = 1;
++	}
++	return 0;
++}
++
++/**
++ * isph3a_aewb_configure - Configure AEWB regs, enable/disable H3A engine.
++ * @aewbcfg: Pointer to AEWB config structure.
++ *
++ * Returns 0 if successful, -EINVAL if aewbcfg pointer is NULL, -ENOMEM if
++ * was unable to allocate memory for the buffer, of other errors if H3A
++ * callback is not set or the parameters for AEWB are invalid.
++ **/
++int isph3a_aewb_configure(struct isph3a_aewb_config *aewbcfg)
++{
++	int ret = 0;
++	int i;
++	int win_count = 0;
++
++	if (NULL == aewbcfg) {
++		printk(KERN_ERR "Null argument in configuration. \n");
++		return -EINVAL;
++	}
++
++	if (!aewbstat.initialized) {
++		DPRINTK_ISPH3A("Setting callback for H3A\n");
++		ret = isp_set_callback(CBK_H3A_AWB_DONE, isph3a_aewb_isr,
++				       (void *)NULL, (void *)NULL);
++		if (ret) {
++			printk(KERN_ERR "No callback for H3A\n");
++			return ret;
++		}
++	}
++
++	ret = isph3a_aewb_set_params(aewbcfg);
++	if (ret) {
++		printk(KERN_ERR "Invalid parameters! \n");
++		return ret;
++	}
++
++	win_count = aewbcfg->ver_win_count * aewbcfg->hor_win_count;
++	win_count += aewbcfg->hor_win_count;
++	ret = win_count / 8;
++	win_count += win_count % 8 ? 1 : 0;
++	win_count += ret;
++
++	aewbstat.win_count = win_count;
++	aewbstat.curr_cfg_buf_size = win_count * AEWB_PACKET_SIZE;
++
++	if (aewbstat.stats_buf_size
++	    && win_count * AEWB_PACKET_SIZE > aewbstat.stats_buf_size) {
++		DPRINTK_ISPH3A("There was a previous buffer... "
++			       "Freeing/unmapping current stat busffs\n");
++		isph3a_aewb_enable(0);
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			ispmmu_kunmap(aewbstat.h3a_buff[i].ispmmu_addr);
++			dma_free_coherent(
++				NULL,
++				aewbstat.min_buf_size,
++				(void *)aewbstat.h3a_buff[i].virt_addr,
++				(dma_addr_t)aewbstat.h3a_buff[i].phy_addr);
++			aewbstat.h3a_buff[i].virt_addr = 0;
++		}
++		aewbstat.stats_buf_size = 0;
++	}
++
++	if (!aewbstat.h3a_buff[0].virt_addr) {
++		aewbstat.stats_buf_size = win_count * AEWB_PACKET_SIZE;
++		aewbstat.min_buf_size = PAGE_ALIGN(aewbstat.stats_buf_size);
++
++		DPRINTK_ISPH3A("Allocating/mapping new stat buffs\n");
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			aewbstat.h3a_buff[i].virt_addr =
++				(unsigned long)dma_alloc_coherent(
++					NULL,
++					aewbstat.min_buf_size,
++					(dma_addr_t *)
++					&aewbstat.h3a_buff[i].phy_addr,
++					GFP_KERNEL | GFP_DMA);
++			if (aewbstat.h3a_buff[i].virt_addr == 0) {
++				printk(KERN_ERR "Can't acquire memory for "
++				       "buffer[%d]\n", i);
++				return -ENOMEM;
++			}
++			aewbstat.h3a_buff[i].addr_align =
++				aewbstat.h3a_buff[i].virt_addr;
++			while ((aewbstat.h3a_buff[i].addr_align & 0xFFFFFFC0) !=
++			       aewbstat.h3a_buff[i].addr_align)
++				aewbstat.h3a_buff[i].addr_align++;
++			aewbstat.h3a_buff[i].ispmmu_addr =
++				ispmmu_kmap(aewbstat.h3a_buff[i].phy_addr,
++					    aewbstat.min_buf_size);
++		}
++		isph3a_aewb_unlock_buffers();
++		isph3a_aewb_link_buffers();
++
++		if (active_buff == NULL)
++			active_buff = &aewbstat.h3a_buff[0];
++
++		isp_reg_writel(active_buff->ispmmu_addr, OMAP3_ISP_IOMEM_H3A,
++			       ISPH3A_AEWBUFST);
++	}
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		DPRINTK_ISPH3A("buff[%d] addr is:\n    virt    0x%lX\n"
++			       "    aligned 0x%lX\n"
++			       "    phys    0x%lX\n"
++			       "    ispmmu  0x%08lX\n"
++			       "    mmapped 0x%lX\n"
++			       "    frame_num %d\n", i,
++			       aewbstat.h3a_buff[i].virt_addr,
++			       aewbstat.h3a_buff[i].addr_align,
++			       aewbstat.h3a_buff[i].phy_addr,
++			       aewbstat.h3a_buff[i].ispmmu_addr,
++			       aewbstat.h3a_buff[i].mmap_addr,
++			       aewbstat.h3a_buff[i].frame_num);
++	}
++
++	active_buff->frame_num = 1;
++
++	atomic_inc(&aewbstat.config_counter);
++	isph3a_aewb_enable(aewbcfg->aewb_enable);
++	isph3a_print_status();
++
++	return 0;
++}
++EXPORT_SYMBOL(isph3a_aewb_configure);
++
++/**
++ * isph3a_aewb_request_statistics - REquest statistics and update gains in AEWB
++ * @aewbdata: Pointer to return AE AWB statistics data.
++ *
++ * This API allows the user to update White Balance gains, as well as
++ * exposure time and analog gain. It is also used to request frame
++ * statistics.
++ *
++ * Returns 0 if successful, -EINVAL when H3A engine is not enabled, or other
++ * errors when setting gains.
++ **/
++int isph3a_aewb_request_statistics(struct isph3a_aewb_data *aewbdata)
++{
++	int ret = 0;
++	u16 frame_diff = 0;
++	u16 frame_cnt = aewbstat.frame_count;
++	wait_queue_t wqt;
++
++	if (!aewb_config_local.aewb_enable) {
++		printk(KERN_ERR "H3A engine not enabled\n");
++		return -EINVAL;
++	}
++
++	DPRINTK_ISPH3A("isph3a_aewb_request_statistics: Enter "
++		       "(frame req. => %d, current frame => %d,"
++		       "update => %d)\n",
++		       aewbdata->frame_number, frame_cnt, aewbdata->update);
++	DPRINTK_ISPH3A("User data received: \n");
++	DPRINTK_ISPH3A("Digital gain = 0x%04x\n", aewbdata->dgain);
++	DPRINTK_ISPH3A("WB gain b *=   0x%04x\n", aewbdata->wb_gain_b);
++	DPRINTK_ISPH3A("WB gain r *=   0x%04x\n", aewbdata->wb_gain_r);
++	DPRINTK_ISPH3A("WB gain gb =   0x%04x\n", aewbdata->wb_gain_gb);
++	DPRINTK_ISPH3A("WB gain gr =   0x%04x\n", aewbdata->wb_gain_gr);
++
++	if (!aewbdata->update) {
++		aewbdata->h3a_aewb_statistics_buf = NULL;
++		goto out;
++	}
++	if (aewbdata->update & SET_DIGITAL_GAIN)
++		h3awb_update.dgain = (u16)aewbdata->dgain;
++	if (aewbdata->update & SET_COLOR_GAINS) {
++		h3awb_update.coef0 = (u8)aewbdata->wb_gain_gr;
++		h3awb_update.coef1 = (u8)aewbdata->wb_gain_r;
++		h3awb_update.coef2 = (u8)aewbdata->wb_gain_b;
++		h3awb_update.coef3 = (u8)aewbdata->wb_gain_gb;
++	}
++	if (aewbdata->update & (SET_COLOR_GAINS | SET_DIGITAL_GAIN))
++		wb_update = 1;
++
++	if (!(aewbdata->update & REQUEST_STATISTICS)) {
++		aewbdata->h3a_aewb_statistics_buf = NULL;
++		goto out;
++	}
++
++	if (aewbdata->frame_number < 1) {
++		printk(KERN_ERR "Illeagal frame number "
++		       "requested (%d)\n",
++		       aewbdata->frame_number);
++		return -EINVAL;
++	}
++
++	isph3a_aewb_unlock_buffers();
++
++	DPRINTK_ISPH3A("Stats available?\n");
++	ret = isph3a_aewb_stats_available(aewbdata);
++	if (!ret)
++		goto out;
++
++	DPRINTK_ISPH3A("Stats in near future?\n");
++	if (aewbdata->frame_number > frame_cnt)
++		frame_diff = aewbdata->frame_number - frame_cnt;
++	else if (aewbdata->frame_number < frame_cnt) {
++		if ((frame_cnt > (MAX_FRAME_COUNT - MAX_FUTURE_FRAMES)) &&
++		    (aewbdata->frame_number < MAX_FRAME_COUNT)) {
++			frame_diff = aewbdata->frame_number + MAX_FRAME_COUNT -
++				frame_cnt;
++		} else
++			frame_diff = MAX_FUTURE_FRAMES + 1;
++	}
++
++	if (frame_diff > MAX_FUTURE_FRAMES) {
++		printk(KERN_ERR "Invalid frame requested, returning current"
++		       " frame stats\n");
++		aewbdata->frame_number = frame_cnt;
++	}
++	if (camnotify) {
++		DPRINTK_ISPH3A("NOT Waiting on stats IRQ for frame %d "
++			       "because camnotify set\n",
++			       aewbdata->frame_number);
++		aewbdata->h3a_aewb_statistics_buf = NULL;
++		goto out;
++	}
++	DPRINTK_ISPH3A("Waiting on stats IRQ for frame %d\n",
++		       aewbdata->frame_number);
++	aewbstat.frame_req = aewbdata->frame_number;
++	aewbstat.stats_req = 1;
++	aewbstat.stats_done = 0;
++	init_waitqueue_entry(&wqt, current);
++	ret = wait_event_interruptible(aewbstat.stats_wait,
++				       aewbstat.stats_done == 1);
++	if (ret < 0) {
++		printk(KERN_ERR "isph3a_aewb_request_statistics"
++		       " Error on wait event %d\n", ret);
++		aewbdata->h3a_aewb_statistics_buf = NULL;
++		return ret;
++	}
++
++	DPRINTK_ISPH3A("ISP AEWB request status interrupt raised\n");
++	ret = isph3a_aewb_stats_available(aewbdata);
++	if (ret) {
++		DPRINTK_ISPH3A("After waiting for stats,"
++			       " stats not available!!\n");
++		aewbdata->h3a_aewb_statistics_buf = NULL;
++	}
++out:
++	DPRINTK_ISPH3A("isph3a_aewb_request_statistics: "
++		       "aewbdata->h3a_aewb_statistics_buf => %p\n",
++		       aewbdata->h3a_aewb_statistics_buf);
++	aewbdata->curr_frame = aewbstat.frame_count;
++
++	return 0;
++}
++EXPORT_SYMBOL(isph3a_aewb_request_statistics);
++
++/**
++ * isph3a_aewb_init - Module Initialisation.
++ *
++ * Always returns 0.
++ **/
++int __init isph3a_aewb_init(void)
++{
++	memset(&aewbstat, 0, sizeof(aewbstat));
++	memset(&aewb_regs, 0, sizeof(aewb_regs));
++
++	init_waitqueue_head(&aewbstat.stats_wait);
++	spin_lock_init(&aewbstat.buffer_lock);
++	return 0;
++}
++
++/**
++ * isph3a_aewb_cleanup - Module exit.
++ **/
++void isph3a_aewb_cleanup(void)
++{
++	int i;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if (!aewbstat.h3a_buff[i].phy_addr)
++			continue;
++
++		ispmmu_kunmap(aewbstat.h3a_buff[i].ispmmu_addr);
++		dma_free_coherent(NULL,
++				  aewbstat.min_buf_size,
++				  (void *)aewbstat.h3a_buff[i].virt_addr,
++				  (dma_addr_t)aewbstat.h3a_buff[i].phy_addr);
++	}
++	memset(&aewbstat, 0, sizeof(aewbstat));
++	memset(&aewb_regs, 0, sizeof(aewb_regs));
++}
++
++/**
++ * isph3a_print_status - Debug print. Values of H3A related registers.
++ **/
++static void isph3a_print_status(void)
++{
++	DPRINTK_ISPH3A("ISPH3A_PCR = 0x%08x\n",
++		       isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR));
++	DPRINTK_ISPH3A("ISPH3A_AEWWIN1 = 0x%08x\n",
++		       isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWWIN1));
++	DPRINTK_ISPH3A("ISPH3A_AEWINSTART = 0x%08x\n",
++		       isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWINSTART));
++	DPRINTK_ISPH3A("ISPH3A_AEWINBLK = 0x%08x\n",
++		       isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWINBLK));
++	DPRINTK_ISPH3A("ISPH3A_AEWSUBWIN = 0x%08x\n",
++		       isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWSUBWIN));
++	DPRINTK_ISPH3A("ISPH3A_AEWBUFST = 0x%08x\n",
++		       isp_reg_readl(OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWBUFST));
++	DPRINTK_ISPH3A("stats windows = %d\n", aewbstat.win_count);
++	DPRINTK_ISPH3A("stats buff size = %d\n", aewbstat.stats_buf_size);
++	DPRINTK_ISPH3A("currently configured stats buff size = %d\n",
++		       aewbstat.curr_cfg_buf_size);
++}
++
++/**
++ * isph3a_notify - Unblocks user request for statistics when camera is off
++ * @notify: 1 - Camera is turned off
++ *
++ * Used when the user has requested statistics about a future frame, but the
++ * camera is turned off before it happens, and this function unblocks the
++ * request so the user can continue in its program.
++ **/
++void isph3a_notify(int notify)
++{
++	camnotify = notify;
++	if (camnotify && aewbstat.initialized) {
++		printk(KERN_DEBUG "Warning Camera Off \n");
++		aewbstat.stats_req = 0;
++		aewbstat.stats_done = 1;
++		wake_up_interruptible(&aewbstat.stats_wait);
++	}
++}
++EXPORT_SYMBOL(isph3a_notify);
++
++/**
++ * isph3a_save_context - Saves the values of the h3a module registers.
++ **/
++void isph3a_save_context(void)
++{
++	DPRINTK_ISPH3A(" Saving context\n");
++	isp_save_context(isph3a_reg_list);
++	/* Avoid enable during restore ctx */
++	isph3a_reg_list[0].val &= ~ISPH3A_PCR_AEW_EN;
++}
++EXPORT_SYMBOL(isph3a_save_context);
++
++/**
++ * isph3a_restore_context - Restores the values of the h3a module registers.
++ **/
++void isph3a_restore_context(void)
++{
++	DPRINTK_ISPH3A(" Restoring context\n");
++	isp_restore_context(isph3a_reg_list);
++}
++EXPORT_SYMBOL(isph3a_restore_context);
+diff --git a/drivers/media/video/isp/isph3a.h b/drivers/media/video/isp/isph3a.h
+new file mode 100644
+index 0000000..7d4c765
+--- /dev/null
++++ b/drivers/media/video/isp/isph3a.h
+@@ -0,0 +1,127 @@
++/*
++ * isph3a.h
++ *
++ * Include file for H3A module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *	Troy Laramy
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_H3A_H
++#define OMAP_ISP_H3A_H
++
++#include <mach/isp_user.h>
++
++#define AEWB_PACKET_SIZE	16
++#define H3A_MAX_BUFF		5
++
++/* Flags for changed registers */
++#define PCR_CHNG		(1 << 0)
++#define AEWWIN1_CHNG		(1 << 1)
++#define AEWINSTART_CHNG		(1 << 2)
++#define AEWINBLK_CHNG		(1 << 3)
++#define AEWSUBWIN_CHNG		(1 << 4)
++#define PRV_WBDGAIN_CHNG	(1 << 5)
++#define PRV_WBGAIN_CHNG		(1 << 6)
++
++/* ISPH3A REGISTERS bits */
++#define ISPH3A_PCR_AF_EN	(1 << 0)
++#define ISPH3A_PCR_AF_ALAW_EN	(1 << 1)
++#define ISPH3A_PCR_AF_MED_EN	(1 << 2)
++#define ISPH3A_PCR_AF_BUSY	(1 << 15)
++#define ISPH3A_PCR_AEW_EN	(1 << 16)
++#define ISPH3A_PCR_AEW_ALAW_EN	(1 << 17)
++#define ISPH3A_PCR_AEW_BUSY	(1 << 18)
++
++#define WRITE_SAT_LIM(reg, sat_limit)			\
++	(reg = (reg & (~(ISPH3A_PCR_AEW_AVE2LMT_MASK))) \
++	 | (sat_limit << ISPH3A_PCR_AEW_AVE2LMT_SHIFT))
++
++#define WRITE_ALAW(reg, alaw_en)			\
++	(reg = (reg & (~(ISPH3A_PCR_AEW_ALAW_EN)))	\
++	 | ((alaw_en & ISPH3A_PCR_AF_ALAW_EN)		\
++	    << ISPH3A_PCR_AEW_ALAW_EN_SHIFT))
++
++#define WRITE_WIN_H(reg, height)				\
++	(reg = (reg & (~(ISPH3A_AEWWIN1_WINH_MASK)))		\
++	 | (((height >> 1) - 1) << ISPH3A_AEWWIN1_WINH_SHIFT))
++
++#define WRITE_WIN_W(reg, width)					\
++	(reg = (reg & (~(ISPH3A_AEWWIN1_WINW_MASK)))		\
++	 | (((width >> 1) - 1) << ISPH3A_AEWWIN1_WINW_SHIFT))
++
++#define WRITE_VER_C(reg, ver_count)				\
++	(reg = (reg & ~(ISPH3A_AEWWIN1_WINVC_MASK))		\
++	 | ((ver_count - 1) << ISPH3A_AEWWIN1_WINVC_SHIFT))
++
++#define WRITE_HOR_C(reg, hor_count)				\
++	(reg = (reg & ~(ISPH3A_AEWWIN1_WINHC_MASK))		\
++	 | ((hor_count - 1) << ISPH3A_AEWWIN1_WINHC_SHIFT))
++
++#define WRITE_VER_WIN_ST(reg, ver_win_st)			\
++	(reg = (reg & ~(ISPH3A_AEWINSTART_WINSV_MASK))		\
++	 | (ver_win_st << ISPH3A_AEWINSTART_WINSV_SHIFT))
++
++#define WRITE_HOR_WIN_ST(reg, hor_win_st)			\
++	(reg = (reg & ~(ISPH3A_AEWINSTART_WINSH_MASK))		\
++	 | (hor_win_st << ISPH3A_AEWINSTART_WINSH_SHIFT))
++
++#define WRITE_BLK_VER_WIN_ST(reg, blk_win_st)		\
++	(reg = (reg & ~(ISPH3A_AEWINBLK_WINSV_MASK))	\
++	 | (blk_win_st << ISPH3A_AEWINBLK_WINSV_SHIFT))
++
++#define WRITE_BLK_WIN_H(reg, height)				\
++	(reg = (reg & ~(ISPH3A_AEWINBLK_WINH_MASK))		\
++	 | (((height >> 1) - 1) << ISPH3A_AEWINBLK_WINH_SHIFT))
++
++#define WRITE_SUB_VER_INC(reg, sub_ver_inc)				\
++	(reg = (reg & ~(ISPH3A_AEWSUBWIN_AEWINCV_MASK))			\
++	 | (((sub_ver_inc >> 1) - 1) << ISPH3A_AEWSUBWIN_AEWINCV_SHIFT))
++
++#define WRITE_SUB_HOR_INC(reg, sub_hor_inc)				\
++	(reg = (reg & ~(ISPH3A_AEWSUBWIN_AEWINCH_MASK))			\
++	 | (((sub_hor_inc >> 1) - 1) << ISPH3A_AEWSUBWIN_AEWINCH_SHIFT))
++
++/**
++ * struct isph3a_aewb_xtrastats - Structure with extra statistics sent by cam.
++ * @field_count: Sequence number of returned framestats.
++ * @isph3a_aewb_xtrastats: Pointer to next buffer with extra stats.
++ */
++struct isph3a_aewb_xtrastats {
++	unsigned long field_count;
++	struct isph3a_aewb_xtrastats *next;
++};
++
++void isph3a_aewb_setxtrastats(struct isph3a_aewb_xtrastats *xtrastats);
++
++int isph3a_aewb_configure(struct isph3a_aewb_config *aewbcfg);
++
++int isph3a_aewb_request_statistics(struct isph3a_aewb_data *aewbdata);
++
++void isph3a_save_context(void);
++
++void isph3a_restore_context(void);
++
++void isph3a_aewb_enable(u8 enable);
++
++int isph3a_aewb_busy(void);
++
++void isph3a_aewb_suspend(void);
++
++void isph3a_aewb_resume(void);
++
++void isph3a_update_wb(void);
++
++void isph3a_notify(int notify);
++#endif		/* OMAP_ISP_H3A_H */
+diff --git a/drivers/media/video/isp/isphist.c b/drivers/media/video/isp/isphist.c
+new file mode 100644
+index 0000000..c6f6a77
+--- /dev/null
++++ b/drivers/media/video/isp/isphist.c
+@@ -0,0 +1,608 @@
++/*
++ * isphist.c
++ *
++ * HISTOGRAM module for TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *	Troy Laramy
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <asm/cacheflush.h>
++
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/uaccess.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "isphist.h"
++#include "ispmmu.h"
++
++/**
++ * struct isp_hist_status - Histogram status.
++ * @hist_enable: Enables the histogram module.
++ * @initialized: Flag to indicate that the module is correctly initializated.
++ * @frame_cnt: Actual frame count.
++ * @frame_req: Frame requested by user.
++ * @completed: Flag to indicate if a frame request is completed.
++ */
++struct isp_hist_status {
++	u8 hist_enable;
++	u8 pm_state;
++	u8 initialized;
++	u8 frame_cnt;
++	u8 frame_req;
++	u8 completed;
++} histstat;
++
++/**
++ * struct isp_hist_buffer - Frame histogram buffer.
++ * @virt_addr: Virtual address to mmap the buffer.
++ * @phy_addr: Physical address of the buffer.
++ * @addr_align: Virtual Address 32 bytes aligned.
++ * @ispmmu_addr: Address of the buffer mapped by the ISPMMU.
++ * @mmap_addr: Mapped memory area of buffer. For userspace access.
++ */
++struct isp_hist_buffer {
++	unsigned long virt_addr;
++	unsigned long phy_addr;
++	unsigned long addr_align;
++	unsigned long ispmmu_addr;
++	unsigned long mmap_addr;
++} hist_buff;
++
++/**
++ * struct isp_hist_regs - Current value of Histogram configuration registers.
++ * @reg_pcr: Peripheral control register.
++ * @reg_cnt: Histogram control register.
++ * @reg_wb_gain: Histogram white balance gain register.
++ * @reg_r0_h: Region 0 horizontal register.
++ * @reg_r0_v: Region 0 vertical register.
++ * @reg_r1_h: Region 1 horizontal register.
++ * @reg_r1_v: Region 1 vertical register.
++ * @reg_r2_h: Region 2 horizontal register.
++ * @reg_r2_v: Region 2 vertical register.
++ * @reg_r3_h: Region 3 horizontal register.
++ * @reg_r3_v: Region 3 vertical register.
++ * @reg_hist_addr: Histogram address register.
++ * @reg_hist_data: Histogram data.
++ * @reg_hist_radd: Address register. When input data comes from mem.
++ * @reg_hist_radd_off: Address offset register. When input data comes from mem.
++ * @reg_h_v_info: Image size register. When input data comes from mem.
++ */
++static struct isp_hist_regs {
++	u32 reg_pcr;
++	u32 reg_cnt;
++	u32 reg_wb_gain;
++	u32 reg_r0_h;
++	u32 reg_r0_v;
++	u32 reg_r1_h;
++	u32 reg_r1_v;
++	u32 reg_r2_h;
++	u32 reg_r2_v;
++	u32 reg_r3_h;
++	u32 reg_r3_v;
++	u32 reg_hist_addr;
++	u32 reg_hist_data;
++	u32 reg_hist_radd;
++	u32 reg_hist_radd_off;
++	u32 reg_h_v_info;
++} hist_regs;
++
++/* Structure for saving/restoring histogram module registers */
++struct isp_reg isphist_reg_list[] = {
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_WB_GAIN, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_HORZ, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_VERT, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_HORZ, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_VERT, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_HORZ, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_VERT, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_HORZ, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_VERT, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_RADD, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_RADD_OFF, 0},
++	{OMAP3_ISP_IOMEM_HIST, ISPHIST_H_V_INFO, 0},
++	{0, ISP_TOK_TERM, 0}
++};
++
++static void isp_hist_print_status(void);
++
++void __isp_hist_enable(u8 enable)
++{
++	if (enable)
++		DPRINTK_ISPHIST("   histogram enabled \n");
++	else
++		DPRINTK_ISPHIST("   histogram disabled \n");
++
++	isp_reg_and_or(OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR, ~ISPHIST_PCR_EN,
++						(enable ? ISPHIST_PCR_EN : 0));
++	histstat.hist_enable = enable;
++}
++
++/**
++ * isp_hist_enable - Enables ISP Histogram submodule operation.
++ * @enable: 1 - Enables the histogram submodule.
++ *
++ * Client should configure all the Histogram registers before calling this
++ * function.
++ **/
++void isp_hist_enable(u8 enable)
++{
++	__isp_hist_enable(enable);
++	histstat.pm_state = enable;
++}
++
++/**
++ * isp_hist_suspend - Suspend ISP Histogram submodule.
++ **/
++void isp_hist_suspend(void)
++{
++	if (histstat.pm_state)
++		__isp_hist_enable(0);
++}
++
++/**
++ * isp_hist_resume - Resume ISP Histogram submodule.
++ **/
++void isp_hist_resume(void)
++{
++	if (histstat.pm_state)
++		__isp_hist_enable(1);
++}
++
++int isp_hist_busy(void)
++{
++	return isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR) &
++		ISPHIST_PCR_BUSY;
++}
++
++
++/**
++ * isp_hist_update_regs - Helper function to update Histogram registers.
++ **/
++static void isp_hist_update_regs(void)
++{
++	isp_reg_writel(hist_regs.reg_pcr, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR);
++	isp_reg_writel(hist_regs.reg_cnt, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT);
++	isp_reg_writel(hist_regs.reg_wb_gain, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_WB_GAIN);
++	isp_reg_writel(hist_regs.reg_r0_h, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_R0_HORZ);
++	isp_reg_writel(hist_regs.reg_r0_v, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_R0_VERT);
++	isp_reg_writel(hist_regs.reg_r1_h, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_R1_HORZ);
++	isp_reg_writel(hist_regs.reg_r1_v, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_R1_VERT);
++	isp_reg_writel(hist_regs.reg_r2_h, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_R2_HORZ);
++	isp_reg_writel(hist_regs.reg_r2_v, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_R2_VERT);
++	isp_reg_writel(hist_regs.reg_r3_h, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_R3_HORZ);
++	isp_reg_writel(hist_regs.reg_r3_v, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_R3_VERT);
++	isp_reg_writel(hist_regs.reg_hist_addr, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_ADDR);
++	isp_reg_writel(hist_regs.reg_hist_data, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_DATA);
++	isp_reg_writel(hist_regs.reg_hist_radd, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_RADD);
++	isp_reg_writel(hist_regs.reg_hist_radd_off, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_RADD_OFF);
++	isp_reg_writel(hist_regs.reg_h_v_info, OMAP3_ISP_IOMEM_HIST,
++		       ISPHIST_H_V_INFO);
++}
++
++/**
++ * isp_hist_isr - Callback from ISP driver for HIST interrupt.
++ * @status: IRQ0STATUS in case of MMU error, 0 for hist interrupt.
++ *          arg1 and arg2 Not used as of now.
++ **/
++static void isp_hist_isr(unsigned long status, isp_vbq_callback_ptr arg1,
++			 void *arg2)
++{
++	isp_hist_enable(0);
++
++	if (!(status & HIST_DONE))
++		return;
++
++	if (!histstat.completed) {
++		if (histstat.frame_req == histstat.frame_cnt) {
++			histstat.frame_cnt = 0;
++			histstat.frame_req = 0;
++			histstat.completed = 1;
++		} else {
++			isp_hist_enable(1);
++			histstat.frame_cnt++;
++		}
++	}
++}
++
++/**
++ * isp_hist_reset_mem - clear Histogram memory before start stats engine.
++ *
++ * Returns 0 after histogram memory was cleared.
++ **/
++static int isp_hist_reset_mem(void)
++{
++	int i;
++
++	isp_reg_or(OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLR_EN);
++
++	for (i = 0; i < HIST_MEM_SIZE; i++)
++		isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
++
++	isp_reg_and(OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ~ISPHIST_CNT_CLR_EN);
++
++	return 0;
++}
++
++/**
++ * isp_hist_set_params - Helper function to check and store user given params.
++ * @user_cfg: Pointer to user configuration structure.
++ *
++ * Returns 0 on success configuration.
++ **/
++static int isp_hist_set_params(struct isp_hist_config *user_cfg)
++{
++
++	int reg_num = 0;
++	int bit_shift = 0;
++
++
++	if (isp_hist_busy())
++		return -EINVAL;
++
++	if (user_cfg->input_bit_width > MIN_BIT_WIDTH)
++		WRITE_DATA_SIZE(hist_regs.reg_cnt, 0);
++	else
++		WRITE_DATA_SIZE(hist_regs.reg_cnt, 1);
++
++	WRITE_SOURCE(hist_regs.reg_cnt, user_cfg->hist_source);
++
++	if (user_cfg->hist_source) {
++		WRITE_HV_INFO(hist_regs.reg_h_v_info, user_cfg->hist_h_v_info);
++
++		if ((user_cfg->hist_radd & ISP_32B_BOUNDARY_BUF) ==
++		    user_cfg->hist_radd) {
++			WRITE_RADD(hist_regs.reg_hist_radd,
++				   user_cfg->hist_radd);
++		} else {
++			printk(KERN_ERR "Address should be in 32 byte boundary"
++			       "\n");
++			return -EINVAL;
++		}
++
++		if ((user_cfg->hist_radd_off & ISP_32B_BOUNDARY_OFFSET) ==
++		    user_cfg->hist_radd_off) {
++			WRITE_RADD_OFF(hist_regs.reg_hist_radd_off,
++				       user_cfg->hist_radd_off);
++		} else {
++			printk(KERN_ERR "Offset should be in 32 byte boundary"
++			       "\n");
++			return -EINVAL;
++		}
++
++	}
++
++	isp_hist_reset_mem();
++	DPRINTK_ISPHIST("ISPHIST: Memory Cleared\n");
++	histstat.frame_req = user_cfg->hist_frames;
++
++	if (unlikely(user_cfg->wb_gain_R > MAX_WB_GAIN ||
++		     user_cfg->wb_gain_RG > MAX_WB_GAIN ||
++		     user_cfg->wb_gain_B > MAX_WB_GAIN ||
++		     user_cfg->wb_gain_BG > MAX_WB_GAIN)) {
++		printk(KERN_ERR "Invalid WB gain\n");
++		return -EINVAL;
++	} else {
++		WRITE_WB_R(hist_regs.reg_wb_gain, user_cfg->wb_gain_R);
++		WRITE_WB_RG(hist_regs.reg_wb_gain, user_cfg->wb_gain_RG);
++		WRITE_WB_B(hist_regs.reg_wb_gain, user_cfg->wb_gain_B);
++		WRITE_WB_BG(hist_regs.reg_wb_gain, user_cfg->wb_gain_BG);
++	}
++
++	/* Regions size and position */
++
++	if (user_cfg->num_regions > MAX_REGIONS)
++		return -EINVAL;
++
++	if (likely((user_cfg->reg0_hor & ISPHIST_REGHORIZ_HEND_MASK) -
++		   ((user_cfg->reg0_hor & ISPHIST_REGHORIZ_HSTART_MASK) >>
++		    ISPHIST_REGHORIZ_HSTART_SHIFT))) {
++		WRITE_REG_HORIZ(hist_regs.reg_r0_h, user_cfg->reg0_hor);
++		reg_num++;
++	} else {
++		printk(KERN_ERR "Invalid Region parameters\n");
++		return -EINVAL;
++	}
++
++	if (likely((user_cfg->reg0_ver & ISPHIST_REGVERT_VEND_MASK) -
++		   ((user_cfg->reg0_ver & ISPHIST_REGVERT_VSTART_MASK) >>
++		    ISPHIST_REGVERT_VSTART_SHIFT))) {
++		WRITE_REG_VERT(hist_regs.reg_r0_v, user_cfg->reg0_ver);
++	} else {
++		printk(KERN_ERR "Invalid Region parameters\n");
++		return -EINVAL;
++	}
++
++	if (user_cfg->num_regions >= 1) {
++		if (likely((user_cfg->reg1_hor & ISPHIST_REGHORIZ_HEND_MASK) -
++			   ((user_cfg->reg1_hor &
++			     ISPHIST_REGHORIZ_HSTART_MASK) >>
++			    ISPHIST_REGHORIZ_HSTART_SHIFT))) {
++			WRITE_REG_HORIZ(hist_regs.reg_r1_h, user_cfg->reg1_hor);
++		} else {
++			printk(KERN_ERR "Invalid Region parameters\n");
++			return -EINVAL;
++		}
++
++		if (likely((user_cfg->reg1_ver & ISPHIST_REGVERT_VEND_MASK) -
++			   ((user_cfg->reg1_ver &
++			     ISPHIST_REGVERT_VSTART_MASK) >>
++			    ISPHIST_REGVERT_VSTART_SHIFT))) {
++			WRITE_REG_VERT(hist_regs.reg_r1_v, user_cfg->reg1_ver);
++		} else {
++			printk(KERN_ERR "Invalid Region parameters\n");
++			return -EINVAL;
++		}
++	}
++
++	if (user_cfg->num_regions >= 2) {
++		if (likely((user_cfg->reg2_hor & ISPHIST_REGHORIZ_HEND_MASK) -
++			   ((user_cfg->reg2_hor &
++			     ISPHIST_REGHORIZ_HSTART_MASK) >>
++			    ISPHIST_REGHORIZ_HSTART_SHIFT))) {
++			WRITE_REG_HORIZ(hist_regs.reg_r2_h, user_cfg->reg2_hor);
++		} else {
++			printk(KERN_ERR "Invalid Region parameters\n");
++			return -EINVAL;
++		}
++
++		if (likely((user_cfg->reg2_ver & ISPHIST_REGVERT_VEND_MASK) -
++			   ((user_cfg->reg2_ver &
++			     ISPHIST_REGVERT_VSTART_MASK) >>
++			    ISPHIST_REGVERT_VSTART_SHIFT))) {
++			WRITE_REG_VERT(hist_regs.reg_r2_v, user_cfg->reg2_ver);
++		} else {
++			printk(KERN_ERR "Invalid Region parameters\n");
++			return -EINVAL;
++		}
++	}
++
++	if (user_cfg->num_regions >= 3) {
++		if (likely((user_cfg->reg3_hor & ISPHIST_REGHORIZ_HEND_MASK) -
++			   ((user_cfg->reg3_hor &
++			     ISPHIST_REGHORIZ_HSTART_MASK) >>
++			    ISPHIST_REGHORIZ_HSTART_SHIFT))) {
++			WRITE_REG_HORIZ(hist_regs.reg_r3_h, user_cfg->reg3_hor);
++		} else {
++			printk(KERN_ERR "Invalid Region parameters\n");
++			return -EINVAL;
++		}
++
++		if (likely((user_cfg->reg3_ver & ISPHIST_REGVERT_VEND_MASK) -
++			   ((user_cfg->reg3_ver &
++			     ISPHIST_REGVERT_VSTART_MASK) >>
++			    ISPHIST_REGVERT_VSTART_SHIFT))) {
++			WRITE_REG_VERT(hist_regs.reg_r3_v, user_cfg->reg3_ver);
++		} else {
++			printk(KERN_ERR "Invalid Region parameters\n");
++			return -EINVAL;
++		}
++	}
++	reg_num = user_cfg->num_regions;
++	if (unlikely(((user_cfg->hist_bins > BINS_256) &&
++		      (user_cfg->hist_bins != BINS_32)) ||
++		     ((user_cfg->hist_bins == BINS_256) &&
++		      reg_num != 0) || ((user_cfg->hist_bins ==
++					 BINS_128) && reg_num >= 2))) {
++		printk(KERN_ERR "Invalid Bins Number: %d\n",
++		       user_cfg->hist_bins);
++		return -EINVAL;
++	} else {
++		WRITE_NUM_BINS(hist_regs.reg_cnt, user_cfg->hist_bins);
++	}
++
++	if (user_cfg->input_bit_width > MAX_BIT_WIDTH ||
++	    user_cfg->input_bit_width < MIN_BIT_WIDTH) {
++		printk(KERN_ERR "Invalid Bit Width: %d\n",
++		       user_cfg->input_bit_width);
++		return -EINVAL;
++	} else {
++		switch (user_cfg->hist_bins) {
++		case BINS_256:
++			bit_shift = user_cfg->input_bit_width - 8;
++			break;
++		case BINS_128:
++			bit_shift = user_cfg->input_bit_width - 7;
++			break;
++		case BINS_64:
++			bit_shift = user_cfg->input_bit_width - 6;
++			break;
++		case BINS_32:
++			bit_shift = user_cfg->input_bit_width - 5;
++			break;
++		default:
++			return -EINVAL;
++		}
++		WRITE_BIT_SHIFT(hist_regs.reg_cnt, bit_shift);
++	}
++
++	isp_hist_update_regs();
++	histstat.initialized = 1;
++
++	return 0;
++}
++
++/**
++ * isp_hist_configure - API to configure HIST registers.
++ * @histcfg: Pointer to user configuration structure.
++ *
++ * Returns 0 on success configuration.
++ **/
++int isp_hist_configure(struct isp_hist_config *histcfg)
++{
++
++	int ret = 0;
++
++	if (NULL == histcfg) {
++		printk(KERN_ERR "Null argument in configuration. \n");
++		return -EINVAL;
++	}
++
++	if (!histstat.initialized) {
++		DPRINTK_ISPHIST("Setting callback for HISTOGRAM\n");
++		ret = isp_set_callback(CBK_HIST_DONE, isp_hist_isr,
++				       (void *)NULL, (void *)NULL);
++		if (ret) {
++			printk(KERN_ERR "No callback for HIST\n");
++			return ret;
++		}
++	}
++
++	ret = isp_hist_set_params(histcfg);
++	if (ret) {
++		printk(KERN_ERR "Invalid parameters! \n");
++		return ret;
++	}
++
++	histstat.frame_cnt = 0;
++	histstat.completed = 0;
++	isp_hist_enable(1);
++	isp_hist_print_status();
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_hist_configure);
++
++/**
++ * isp_hist_request_statistics - Request statistics in Histogram.
++ * @histdata: Pointer to data structure.
++ *
++ * This API allows the user to request for histogram statistics.
++ *
++ * Returns 0 on successful request.
++ **/
++int isp_hist_request_statistics(struct isp_hist_data *histdata)
++{
++	int i, ret;
++	u32 curr;
++
++	if (isp_hist_busy())
++		return -EBUSY;
++
++	if (!histstat.completed && histstat.initialized)
++		return -EINVAL;
++
++	isp_reg_or(OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLR_EN);
++
++	for (i = 0; i < HIST_MEM_SIZE; i++) {
++		curr = isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
++		ret = put_user(curr, histdata->hist_statistics_buf + i);
++		if (ret) {
++			printk(KERN_ERR "Failed copy_to_user for "
++			       "HIST stats buff, %d\n", ret);
++		}
++	}
++
++	isp_reg_and(OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
++		    ~ISPHIST_CNT_CLR_EN);
++	histstat.completed = 0;
++	return 0;
++}
++EXPORT_SYMBOL(isp_hist_request_statistics);
++
++/**
++ * isp_hist_init - Module Initialization.
++ *
++ * Returns 0 if successful.
++ **/
++int __init isp_hist_init(void)
++{
++	memset(&histstat, 0, sizeof(histstat));
++	memset(&hist_regs, 0, sizeof(hist_regs));
++
++	return 0;
++}
++
++/**
++ * isp_hist_cleanup - Module cleanup.
++ **/
++void isp_hist_cleanup(void)
++{
++	memset(&histstat, 0, sizeof(histstat));
++	memset(&hist_regs, 0, sizeof(hist_regs));
++}
++
++/**
++ * isphist_save_context - Saves the values of the histogram module registers.
++ **/
++void isphist_save_context(void)
++{
++	DPRINTK_ISPHIST(" Saving context\n");
++	isp_save_context(isphist_reg_list);
++}
++EXPORT_SYMBOL(isphist_save_context);
++
++/**
++ * isphist_restore_context - Restores the values of the histogram module regs.
++ **/
++void isphist_restore_context(void)
++{
++	DPRINTK_ISPHIST(" Restoring context\n");
++	isp_restore_context(isphist_reg_list);
++}
++EXPORT_SYMBOL(isphist_restore_context);
++
++/**
++ * isp_hist_print_status - Debug print
++ **/
++static void isp_hist_print_status(void)
++{
++	DPRINTK_ISPHIST("ISPHIST_PCR = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR));
++	DPRINTK_ISPHIST("ISPHIST_CNT = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT));
++	DPRINTK_ISPHIST("ISPHIST_WB_GAIN = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_WB_GAIN));
++	DPRINTK_ISPHIST("ISPHIST_R0_HORZ = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_HORZ));
++	DPRINTK_ISPHIST("ISPHIST_R0_VERT = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_VERT));
++	DPRINTK_ISPHIST("ISPHIST_R1_HORZ = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_HORZ));
++	DPRINTK_ISPHIST("ISPHIST_R1_VERT = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_VERT));
++	DPRINTK_ISPHIST("ISPHIST_R2_HORZ = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_HORZ));
++	DPRINTK_ISPHIST("ISPHIST_R2_VERT = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_VERT));
++	DPRINTK_ISPHIST("ISPHIST_R3_HORZ = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_HORZ));
++	DPRINTK_ISPHIST("ISPHIST_R3_VERT = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_VERT));
++	DPRINTK_ISPHIST("ISPHIST_ADDR = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR));
++	DPRINTK_ISPHIST("ISPHIST_RADD = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_RADD));
++	DPRINTK_ISPHIST("ISPHIST_RADD_OFF = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_RADD_OFF));
++	DPRINTK_ISPHIST("ISPHIST_H_V_INFO = 0x%08x\n",
++			isp_reg_readl(OMAP3_ISP_IOMEM_HIST, ISPHIST_H_V_INFO));
++}
+diff --git a/drivers/media/video/isp/isphist.h b/drivers/media/video/isp/isphist.h
+new file mode 100644
+index 0000000..6b17c4e
+--- /dev/null
++++ b/drivers/media/video/isp/isphist.h
+@@ -0,0 +1,105 @@
++/*
++ * isphist.h
++ *
++ * Header file for HISTOGRAM module in TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * Contributors:
++ *	Sergio Aguirre <saaguirre@ti.com>
++ *	Troy Laramy
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_HIST_H
++#define OMAP_ISP_HIST_H
++
++#include <mach/isp_user.h>
++
++#define MAX_REGIONS		0x4
++#define MAX_WB_GAIN		255
++#define MIN_WB_GAIN		0x0
++#define MAX_BIT_WIDTH		14
++#define MIN_BIT_WIDTH		8
++
++#define ISPHIST_PCR_EN		(1 << 0)
++#define HIST_MEM_SIZE		1024
++#define ISPHIST_CNT_CLR_EN	(1 << 7)
++
++#define WRITE_SOURCE(reg, source)			\
++	(reg = (reg & ~(ISPHIST_CNT_SOURCE_MASK))	\
++	 | (source << ISPHIST_CNT_SOURCE_SHIFT))
++
++#define WRITE_HV_INFO(reg, hv_info)			\
++	(reg = ((reg & ~(ISPHIST_HV_INFO_MASK))		\
++		| (hv_info & ISPHIST_HV_INFO_MASK)))
++
++#define WRITE_RADD(reg, radd)			\
++	(reg = (reg & ~(ISPHIST_RADD_MASK))	\
++	 | (radd << ISPHIST_RADD_SHIFT))
++
++#define WRITE_RADD_OFF(reg, radd_off)			\
++	(reg = (reg & ~(ISPHIST_RADD_OFF_MASK))		\
++	 | (radd_off << ISPHIST_RADD_OFF_SHIFT))
++
++#define WRITE_BIT_SHIFT(reg, bit_shift)			\
++	(reg = (reg & ~(ISPHIST_CNT_SHIFT_MASK))	\
++	 | (bit_shift << ISPHIST_CNT_SHIFT_SHIFT))
++
++#define WRITE_DATA_SIZE(reg, data_size)			\
++	(reg = (reg & ~(ISPHIST_CNT_DATASIZE_MASK))	\
++	 | (data_size << ISPHIST_CNT_DATASIZE_SHIFT))
++
++#define WRITE_NUM_BINS(reg, num_bins)			\
++	(reg = (reg & ~(ISPHIST_CNT_BINS_MASK))		\
++	 | (num_bins << ISPHIST_CNT_BINS_SHIFT))
++
++#define WRITE_WB_R(reg, reg_wb_gain)				\
++	reg = ((reg & ~(ISPHIST_WB_GAIN_WG00_MASK))		\
++	       | (reg_wb_gain << ISPHIST_WB_GAIN_WG00_SHIFT))
++
++#define WRITE_WB_RG(reg, reg_wb_gain)			\
++	(reg = (reg & ~(ISPHIST_WB_GAIN_WG01_MASK))	\
++	 | (reg_wb_gain << ISPHIST_WB_GAIN_WG01_SHIFT))
++
++#define WRITE_WB_B(reg, reg_wb_gain)			\
++	(reg = (reg & ~(ISPHIST_WB_GAIN_WG02_MASK))	\
++	 | (reg_wb_gain << ISPHIST_WB_GAIN_WG02_SHIFT))
++
++#define WRITE_WB_BG(reg, reg_wb_gain)			\
++	(reg = (reg & ~(ISPHIST_WB_GAIN_WG03_MASK))	\
++	 | (reg_wb_gain << ISPHIST_WB_GAIN_WG03_SHIFT))
++
++#define WRITE_REG_HORIZ(reg, reg_n_hor)			\
++	(reg = ((reg & ~ISPHIST_REGHORIZ_MASK)		\
++		| (reg_n_hor & ISPHIST_REGHORIZ_MASK)))
++
++#define WRITE_REG_VERT(reg, reg_n_vert)			\
++	(reg = ((reg & ~ISPHIST_REGVERT_MASK)		\
++		| (reg_n_vert & ISPHIST_REGVERT_MASK)))
++
++
++void isp_hist_enable(u8 enable);
++
++int isp_hist_busy(void);
++
++int isp_hist_configure(struct isp_hist_config *histcfg);
++
++int isp_hist_request_statistics(struct isp_hist_data *histdata);
++
++void isphist_save_context(void);
++
++void isp_hist_suspend(void);
++
++void isp_hist_resume(void);
++
++void isphist_restore_context(void);
++
++#endif				/* OMAP_ISP_HIST */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0007-omap3isp-Add-CSI2-interface-support.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0007-omap3isp-Add-CSI2-interface-support.patch
new file mode 100644
index 0000000000..842f395388
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0007-omap3isp-Add-CSI2-interface-support.patch
@@ -0,0 +1,2384 @@
+From 9fbe7b786427d981cac890a7407da09232f5d1e2 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:02 +0200
+Subject: [PATCH] omap3isp: Add CSI2 interface support
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ drivers/media/video/isp/ispcsi2.c | 2124 +++++++++++++++++++++++++++++++++++++
+ drivers/media/video/isp/ispcsi2.h |  232 ++++
+ 2 files changed, 2356 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/isp/ispcsi2.c
+ create mode 100644 drivers/media/video/isp/ispcsi2.h
+
+diff --git a/drivers/media/video/isp/ispcsi2.c b/drivers/media/video/isp/ispcsi2.c
+new file mode 100644
+index 0000000..5141b5a
+--- /dev/null
++++ b/drivers/media/video/isp/ispcsi2.c
+@@ -0,0 +1,2124 @@
++/*
++ * ispcsi2.c
++ *
++ * Driver Library for ISP CSI Control module in TI's OMAP3 Camera ISP
++ * ISP CSI interface and IRQ related APIs are defined here.
++ *
++ * Copyright (C) 2009 Texas Instruments.
++ *
++ * Contributors:
++ * 	Sergio Aguirre <saaguirre@ti.com>
++ * 	Dominic Curran <dcurran@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/delay.h>
++#include <media/v4l2-common.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "ispcsi2.h"
++
++static struct isp_csi2_cfg current_csi2_cfg;
++static struct isp_csi2_cfg_update current_csi2_cfg_update;
++
++static bool update_complexio_cfg1;
++static bool update_phy_cfg0;
++static bool update_phy_cfg1;
++static bool update_ctx_ctrl1[8];
++static bool update_ctx_ctrl2[8];
++static bool update_ctx_ctrl3[8];
++static bool update_timing;
++static bool update_ctrl;
++static bool uses_videoport;
++
++/**
++ * isp_csi2_complexio_lanes_config - Configuration of CSI2 ComplexIO lanes.
++ * @reqcfg: Pointer to structure containing desired lane configuration
++ *
++ * Validates and saves to internal driver memory the passed configuration.
++ * Returns 0 if successful, or -EINVAL if null pointer is passed, invalid
++ * lane position or polarity is set, and if 2 lanes try to occupy the same
++ * position. To apply this settings, use the isp_csi2_complexio_lanes_update()
++ * function just after calling this function.
++ **/
++int isp_csi2_complexio_lanes_config(struct isp_csi2_lanes_cfg *reqcfg)
++{
++	int i;
++	bool pos_occupied[5] = {false, false, false, false, false};
++	struct isp_csi2_lanes_cfg *currlanes = &current_csi2_cfg.lanes;
++	struct isp_csi2_lanes_cfg_update *currlanes_u =
++		&current_csi2_cfg_update.lanes;
++
++	/* Validating parameters sent by driver */
++	if (reqcfg == NULL) {
++		printk(KERN_ERR "Invalid Complex IO Configuration sent by"
++		       " sensor\n");
++		goto err_einval;
++	}
++
++	/* Data lanes verification */
++	for (i = 0; i < 4; i++) {
++		if ((reqcfg->data[i].pol > 1) || (reqcfg->data[i].pos > 5)) {
++			printk(KERN_ERR "Invalid CSI-2 Complex IO configuration"
++			       " parameters for data lane #%d\n", i);
++			goto err_einval;
++		}
++		if (pos_occupied[reqcfg->data[i].pos - 1] &&
++		    reqcfg->data[i].pos > 0) {
++			printk(KERN_ERR "Lane #%d already occupied\n",
++			       reqcfg->data[i].pos);
++			goto err_einval;
++		} else
++			pos_occupied[reqcfg->data[i].pos - 1] = true;
++	}
++
++	/* Clock lane verification */
++	if ((reqcfg->clk.pol > 1) || (reqcfg->clk.pos > 5) ||
++	    (reqcfg->clk.pos == 0)) {
++		printk(KERN_ERR "Invalid CSI-2 Complex IO configuration"
++		       " parameters for clock lane\n");
++		goto err_einval;
++	}
++	if (pos_occupied[reqcfg->clk.pos - 1]) {
++		printk(KERN_ERR "Lane #%d already occupied",
++		       reqcfg->clk.pos);
++		goto err_einval;
++	} else
++		pos_occupied[reqcfg->clk.pos - 1] = true;
++
++	for (i = 0; i < 4; i++) {
++		if (currlanes->data[i].pos != reqcfg->data[i].pos) {
++			currlanes->data[i].pos = reqcfg->data[i].pos;
++			currlanes_u->data[i] = true;
++			update_complexio_cfg1 = true;
++		}
++		if (currlanes->data[i].pol != reqcfg->data[i].pol) {
++			currlanes->data[i].pol = reqcfg->data[i].pol;
++			currlanes_u->data[i] = true;
++			update_complexio_cfg1 = true;
++		}
++	}
++
++	if (currlanes->clk.pos != reqcfg->clk.pos) {
++		currlanes->clk.pos = reqcfg->clk.pos;
++		currlanes_u->clk = true;
++		update_complexio_cfg1 = true;
++	}
++	if (currlanes->clk.pol != reqcfg->clk.pol) {
++		currlanes->clk.pol = reqcfg->clk.pol;
++		currlanes_u->clk = true;
++		update_complexio_cfg1 = true;
++	}
++	return 0;
++err_einval:
++	return -EINVAL;
++}
++
++/**
++ * isp_csi2_complexio_lanes_update - Applies CSI2 ComplexIO lanes configuration.
++ * @force_update: Flag to force rewrite of registers, even if they haven't been
++ *                updated with the isp_csi2_complexio_lanes_config() function.
++ *
++ * It only saves settings when they were previously updated using the
++ * isp_csi2_complexio_lanes_config() function, unless the force_update flag is
++ * set to true.
++ * Always returns 0.
++ **/
++int isp_csi2_complexio_lanes_update(bool force_update)
++{
++	struct isp_csi2_lanes_cfg *currlanes = &current_csi2_cfg.lanes;
++	struct isp_csi2_lanes_cfg_update *currlanes_u =
++		&current_csi2_cfg_update.lanes;
++	u32 reg;
++	int i;
++
++	if (!update_complexio_cfg1 && !force_update)
++		return 0;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_COMPLEXIO_CFG1);
++	for (i = 0; i < 4; i++) {
++		if (currlanes_u->data[i] || force_update) {
++			reg &= ~(ISPCSI2_COMPLEXIO_CFG1_DATA_POL_MASK(i + 1) |
++				 ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_MASK(i +
++									   1));
++			reg |= (currlanes->data[i].pol <<
++				ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(i + 1));
++			reg |= (currlanes->data[i].pos <<
++				ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(i +
++									   1));
++			currlanes_u->data[i] = false;
++		}
++	}
++
++	if (currlanes_u->clk || force_update) {
++		reg &= ~(ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_MASK |
++			 ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_MASK);
++		reg |= (currlanes->clk.pol <<
++			ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT);
++		reg |= (currlanes->clk.pos <<
++			ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT);
++		currlanes_u->clk = false;
++	}
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_COMPLEXIO_CFG1);
++
++	update_complexio_cfg1 = false;
++	return 0;
++}
++
++/**
++ * isp_csi2_complexio_lanes_get - Gets CSI2 ComplexIO lanes configuration.
++ *
++ * Gets settings from HW registers and fills in the internal driver memory
++ * Always returns 0.
++ **/
++int isp_csi2_complexio_lanes_get(void)
++{
++	struct isp_csi2_lanes_cfg *currlanes = &current_csi2_cfg.lanes;
++	struct isp_csi2_lanes_cfg_update *currlanes_u =
++		&current_csi2_cfg_update.lanes;
++	u32 reg;
++	int i;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_COMPLEXIO_CFG1);
++	for (i = 0; i < 4; i++) {
++		currlanes->data[i].pol = (reg &
++					  ISPCSI2_COMPLEXIO_CFG1_DATA_POL_MASK(i + 1)) >>
++			ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(i + 1);
++		currlanes->data[i].pos = (reg &
++					  ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_MASK(i + 1)) >>
++			ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(i + 1);
++		currlanes_u->data[i] = false;
++	}
++	currlanes->clk.pol = (reg & ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_MASK) >>
++		ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT;
++	currlanes->clk.pos = (reg &
++			      ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_MASK) >>
++		ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT;
++	currlanes_u->clk = false;
++
++	update_complexio_cfg1 = false;
++	return 0;
++}
++
++/**
++ * isp_csi2_complexio_power_status - Gets CSI2 ComplexIO power status.
++ *
++ * Returns 3 possible valid states: ISP_CSI2_POWER_OFF, ISP_CSI2_POWER_ON,
++ * and ISP_CSI2_POWER_ULPW.
++ **/
++static enum isp_csi2_power_cmds isp_csi2_complexio_power_status(void)
++{
++	enum isp_csi2_power_cmds ret;
++	u32 reg;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_COMPLEXIO_CFG1) &
++		ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_MASK;
++	switch (reg) {
++	case ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_OFF:
++		ret = ISP_CSI2_POWER_OFF;
++		break;
++	case ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_ON:
++		ret = ISP_CSI2_POWER_ON;
++		break;
++	case ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_ULPW:
++		ret = ISP_CSI2_POWER_ULPW;
++		break;
++	default:
++		return -EINVAL;
++	}
++	return ret;
++}
++
++/**
++ * isp_csi2_complexio_power_autoswitch - Sets CSI2 ComplexIO power autoswitch.
++ * @enable: Sets or clears the autoswitch function enable flag.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_complexio_power_autoswitch(bool enable)
++{
++	u32 reg;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_COMPLEXIO_CFG1);
++	reg &= ~ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_MASK;
++
++	if (enable)
++		reg |= ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_ENABLE;
++	else
++		reg |= ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_DISABLE;
++
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_COMPLEXIO_CFG1);
++	return 0;
++}
++
++/**
++ * isp_csi2_complexio_power - Sets the desired power command for CSI2 ComplexIO.
++ * @power_cmd: Power command to be set.
++ *
++ * Returns 0 if successful, or -EBUSY if the retry count is exceeded.
++ **/
++int isp_csi2_complexio_power(enum isp_csi2_power_cmds power_cmd)
++{
++	enum isp_csi2_power_cmds current_state;
++	u32 reg;
++	u8 retry_count;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_COMPLEXIO_CFG1) &
++		~ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_MASK;
++	switch (power_cmd) {
++	case ISP_CSI2_POWER_OFF:
++		reg |= ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_OFF;
++		break;
++	case ISP_CSI2_POWER_ON:
++		reg |= ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_ON;
++		break;
++	case ISP_CSI2_POWER_ULPW:
++		reg |= ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_ULPW;
++		break;
++	default:
++		printk(KERN_ERR "CSI2: ERROR - Wrong Power command!\n");
++		return -EINVAL;
++	}
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_COMPLEXIO_CFG1);
++
++	retry_count = 0;
++	do {
++		udelay(50);
++		current_state = isp_csi2_complexio_power_status();
++
++		if (current_state != power_cmd) {
++			printk(KERN_DEBUG "CSI2: Complex IO power command not"
++			       " yet taken.");
++			if (++retry_count < 100) {
++				printk(KERN_DEBUG " Retrying...\n");
++				udelay(50);
++			} else {
++				printk(KERN_DEBUG " Retry count exceeded!\n");
++			}
++		}
++	} while ((current_state != power_cmd) && (retry_count < 100));
++
++	if (retry_count == 100)
++		return -EBUSY;
++
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_frame_mode - Configure if_en behaviour for CSI2
++ * @frame_mode: Desired action for IF_EN switch off. 0 - disable IF immediately
++ *              1 - disable after all Frame end Code is received in all
++ *              contexts.
++ *
++ * Validates and saves to internal driver memory the passed configuration.
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_config_frame_mode(enum isp_csi2_frame_mode frame_mode)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++
++	if (currctrl->frame_mode != frame_mode) {
++		currctrl->frame_mode = frame_mode;
++		currctrl_u->frame_mode = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_vp_clk_enable - Enables/disables CSI2 Videoport clock.
++ * @vp_clk_enable: Boolean value to specify the Videoport clock state.
++ *
++ * Validates and saves to internal driver memory the passed configuration.
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_config_vp_clk_enable(bool vp_clk_enable)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++
++	if (currctrl->vp_clk_enable != vp_clk_enable) {
++		currctrl->vp_clk_enable = vp_clk_enable;
++		currctrl_u->vp_clk_enable = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_vp_only_enable - Sets CSI2 Videoport clock as exclusive
++ * @vp_only_enable: Boolean value to specify if the Videoport clock is
++ *                  exclusive, setting the OCP port as disabled.
++ *
++ * Validates and saves to internal driver memory the passed configuration.
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_config_vp_only_enable(bool vp_only_enable)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++
++	if (currctrl->vp_only_enable != vp_only_enable) {
++		currctrl->vp_only_enable = vp_only_enable;
++		currctrl_u->vp_only_enable = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_vp_out_ctrl - Sets CSI2 Videoport clock divider
++ * @vp_out_ctrl: Divider value for setting videoport clock frequency based on
++ *               OCP port frequency, valid dividers are between 1 and 4.
++ *
++ * Validates and saves to internal driver memory the passed configuration.
++ * Returns 0 if successful, or -EINVAL if wrong divider value is passed.
++ **/
++int isp_csi2_ctrl_config_vp_out_ctrl(u8 vp_out_ctrl)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++
++	if ((vp_out_ctrl == 0) || (vp_out_ctrl > 4)) {
++		printk(KERN_ERR "CSI2: Wrong divisor value. Must be between"
++		       " 1 and 4");
++		return -EINVAL;
++	}
++
++	if (currctrl->vp_out_ctrl != vp_out_ctrl) {
++		currctrl->vp_out_ctrl = vp_out_ctrl;
++		currctrl_u->vp_out_ctrl = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_debug_enable - Sets CSI2 debug
++ * @debug_enable: Boolean for setting debug configuration on CSI2.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_config_debug_enable(bool debug_enable)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++
++	if (currctrl->debug_enable != debug_enable) {
++		currctrl->debug_enable = debug_enable;
++		currctrl_u->debug_enable = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_burst_size - Sets CSI2 burst size.
++ * @burst_size: Burst size of the memory saving capability of receiver.
++ *
++ * Returns 0 if successful, or -EINVAL if burst size is wrong.
++ **/
++int isp_csi2_ctrl_config_burst_size(u8 burst_size)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++	if (burst_size > 3) {
++		printk(KERN_ERR "CSI2: Wrong burst size. Must be between"
++		       " 0 and 3");
++		return -EINVAL;
++	}
++
++	if (currctrl->burst_size != burst_size) {
++		currctrl->burst_size = burst_size;
++		currctrl_u->burst_size = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_ecc_enable - Enables ECC on CSI2 Receiver
++ * @ecc_enable: Boolean to enable/disable the CSI2 receiver ECC handling.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_config_ecc_enable(bool ecc_enable)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++
++	if (currctrl->ecc_enable != ecc_enable) {
++		currctrl->ecc_enable = ecc_enable;
++		currctrl_u->ecc_enable = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_ecc_enable - Enables ECC on CSI2 Receiver
++ * @ecc_enable: Boolean to enable/disable the CSI2 receiver ECC handling.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_config_secure_mode(bool secure_mode)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++
++	if (currctrl->secure_mode != secure_mode) {
++		currctrl->secure_mode = secure_mode;
++		currctrl_u->secure_mode = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_config_if_enable - Enables CSI2 Receiver interface.
++ * @if_enable: Boolean to enable/disable the CSI2 receiver interface.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_config_if_enable(bool if_enable)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++
++	if (currctrl->if_enable != if_enable) {
++		currctrl->if_enable = if_enable;
++		currctrl_u->if_enable = true;
++		update_ctrl = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_update - Applies CSI2 control configuration.
++ * @force_update: Flag to force rewrite of registers, even if they haven't been
++ *                updated with the isp_csi2_ctrl_config_*() functions.
++ *
++ * It only saves settings when they were previously updated using the
++ * isp_csi2_ctrl_config_*() functions, unless the force_update flag is
++ * set to true.
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_update(bool force_update)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++	u32 reg;
++
++	if (update_ctrl || force_update) {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_CTRL);
++		if (currctrl_u->frame_mode || force_update) {
++			reg &= ~ISPCSI2_CTRL_FRAME_MASK;
++			if (currctrl->frame_mode)
++				reg |= ISPCSI2_CTRL_FRAME_DISABLE_FEC;
++			else
++				reg |= ISPCSI2_CTRL_FRAME_DISABLE_IMM;
++			currctrl_u->frame_mode = false;
++		}
++		if (currctrl_u->vp_clk_enable || force_update) {
++			reg &= ~ISPCSI2_CTRL_VP_CLK_EN_MASK;
++			if (currctrl->vp_clk_enable)
++				reg |= ISPCSI2_CTRL_VP_CLK_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTRL_VP_CLK_EN_DISABLE;
++			currctrl_u->vp_clk_enable = false;
++		}
++		if (currctrl_u->vp_only_enable || force_update) {
++			reg &= ~ISPCSI2_CTRL_VP_ONLY_EN_MASK;
++			uses_videoport = currctrl->vp_only_enable;
++			if (currctrl->vp_only_enable)
++				reg |= ISPCSI2_CTRL_VP_ONLY_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTRL_VP_ONLY_EN_DISABLE;
++			currctrl_u->vp_only_enable = false;
++		}
++		if (currctrl_u->vp_out_ctrl || force_update) {
++			reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK;
++			reg |= (currctrl->vp_out_ctrl - 1) <<
++				ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT;
++			currctrl_u->vp_out_ctrl = false;
++		}
++		if (currctrl_u->debug_enable || force_update) {
++			reg &= ~ISPCSI2_CTRL_DBG_EN_MASK;
++			if (currctrl->debug_enable)
++				reg |= ISPCSI2_CTRL_DBG_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTRL_DBG_EN_DISABLE;
++			currctrl_u->debug_enable = false;
++		}
++		if (currctrl_u->burst_size || force_update) {
++			reg &= ~ISPCSI2_CTRL_BURST_SIZE_MASK;
++			reg |= currctrl->burst_size <<
++				ISPCSI2_CTRL_BURST_SIZE_SHIFT;
++			currctrl_u->burst_size = false;
++		}
++		if (currctrl_u->ecc_enable || force_update) {
++			reg &= ~ISPCSI2_CTRL_ECC_EN_MASK;
++			if (currctrl->ecc_enable)
++				reg |= ISPCSI2_CTRL_ECC_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTRL_ECC_EN_DISABLE;
++			currctrl_u->ecc_enable = false;
++		}
++		if (currctrl_u->secure_mode || force_update) {
++			reg &= ~ISPCSI2_CTRL_SECURE_MASK;
++			if (currctrl->secure_mode)
++				reg |= ISPCSI2_CTRL_SECURE_ENABLE;
++			else
++				reg |= ISPCSI2_CTRL_SECURE_DISABLE;
++			currctrl_u->secure_mode = false;
++		}
++		if (currctrl_u->if_enable || force_update) {
++			reg &= ~ISPCSI2_CTRL_IF_EN_MASK;
++			if (currctrl->if_enable)
++				reg |= ISPCSI2_CTRL_IF_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTRL_IF_EN_DISABLE;
++			currctrl_u->if_enable = false;
++		}
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_CTRL);
++		update_ctrl = false;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctrl_get - Gets CSI2 control configuration
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctrl_get(void)
++{
++	struct isp_csi2_ctrl_cfg *currctrl = &current_csi2_cfg.ctrl;
++	struct isp_csi2_ctrl_cfg_update *currctrl_u =
++		&current_csi2_cfg_update.ctrl;
++	u32 reg;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_CTRL);
++	currctrl->frame_mode = (reg & ISPCSI2_CTRL_FRAME_MASK) >>
++		ISPCSI2_CTRL_FRAME_SHIFT;
++	currctrl_u->frame_mode = false;
++
++	if ((reg & ISPCSI2_CTRL_VP_CLK_EN_MASK) ==
++	    ISPCSI2_CTRL_VP_CLK_EN_ENABLE)
++		currctrl->vp_clk_enable = true;
++	else
++		currctrl->vp_clk_enable = false;
++	currctrl_u->vp_clk_enable = false;
++
++	if ((reg & ISPCSI2_CTRL_VP_ONLY_EN_MASK) ==
++	    ISPCSI2_CTRL_VP_ONLY_EN_ENABLE)
++		currctrl->vp_only_enable = true;
++	else
++		currctrl->vp_only_enable = false;
++	uses_videoport = currctrl->vp_only_enable;
++	currctrl_u->vp_only_enable = false;
++
++	currctrl->vp_out_ctrl = ((reg & ISPCSI2_CTRL_VP_OUT_CTRL_MASK) >>
++				 ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT) + 1;
++	currctrl_u->vp_out_ctrl = false;
++
++	if ((reg & ISPCSI2_CTRL_DBG_EN_MASK) == ISPCSI2_CTRL_DBG_EN_ENABLE)
++		currctrl->debug_enable = true;
++	else
++		currctrl->debug_enable = false;
++	currctrl_u->debug_enable = false;
++
++	currctrl->burst_size = (reg & ISPCSI2_CTRL_BURST_SIZE_MASK) >>
++		ISPCSI2_CTRL_BURST_SIZE_SHIFT;
++	currctrl_u->burst_size = false;
++
++	if ((reg & ISPCSI2_CTRL_ECC_EN_MASK) == ISPCSI2_CTRL_ECC_EN_ENABLE)
++		currctrl->ecc_enable = true;
++	else
++		currctrl->ecc_enable = false;
++	currctrl_u->ecc_enable = false;
++
++	if ((reg & ISPCSI2_CTRL_SECURE_MASK) == ISPCSI2_CTRL_SECURE_ENABLE)
++		currctrl->secure_mode = true;
++	else
++		currctrl->secure_mode = false;
++	currctrl_u->secure_mode = false;
++
++	if ((reg & ISPCSI2_CTRL_IF_EN_MASK) == ISPCSI2_CTRL_IF_EN_ENABLE)
++		currctrl->if_enable = true;
++	else
++		currctrl->if_enable = false;
++	currctrl_u->if_enable = false;
++
++	update_ctrl = false;
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_validate - Validates the context number value
++ * @ctxnum: Pointer to variable containing context number.
++ *
++ * If the value is not in range (3 bits), it is being ANDed with 0x7 to force
++ * it to be on range.
++ **/
++static void isp_csi2_ctx_validate(u8 *ctxnum)
++{
++	if (*ctxnum > 7) {
++		printk(KERN_ERR "Invalid context number. Forcing valid"
++		       " value...\n");
++		*ctxnum &= ~(0x7);
++	}
++}
++
++/**
++ * isp_csi2_ctx_config_virtual_id - Maps a virtual ID with a CSI2 Rx context
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @virtual_id: CSI2 Virtual ID to associate with specified context number.
++ *
++ * Returns 0 if successful, or -EINVAL if Virtual ID is not in range (0-3).
++ **/
++int isp_csi2_ctx_config_virtual_id(u8 ctxnum, u8 virtual_id)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	if (virtual_id > 3) {
++		printk(KERN_ERR "Wrong requested virtual_id\n");
++		return -EINVAL;
++	}
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->virtual_id != virtual_id) {
++		selected_ctx->virtual_id = virtual_id;
++		selected_ctx_u->virtual_id = true;
++		update_ctx_ctrl2[ctxnum] = true;
++	}
++
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_frame_count - Sets frame count to be received in CSI2 Rx.
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @frame_count: Number of frames to acquire.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_config_frame_count(u8 ctxnum, u8 frame_count)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->frame_count != frame_count) {
++		selected_ctx->frame_count = frame_count;
++		selected_ctx_u->frame_count = true;
++		update_ctx_ctrl1[ctxnum] = true;
++	}
++
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_format - Maps a pixel format to a specified context.
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @pixformat: V4L2 structure for pixel format.
++ *
++ * Returns 0 if successful, or -EINVAL if the format is not supported by the
++ * receiver.
++ **/
++int isp_csi2_ctx_config_format(u8 ctxnum, u32 pixformat)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++	struct v4l2_pix_format pix;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	pix.pixelformat = pixformat;
++	switch (pix.pixelformat) {
++	case V4L2_PIX_FMT_RGB565:
++	case V4L2_PIX_FMT_RGB565X:
++	case V4L2_PIX_FMT_YUYV:
++	case V4L2_PIX_FMT_UYVY:
++	case V4L2_PIX_FMT_RGB555:
++	case V4L2_PIX_FMT_RGB555X:
++	case V4L2_PIX_FMT_SGRBG10:
++		break;
++	default:
++		printk(KERN_ERR "Context config pixel format unsupported\n");
++		return -EINVAL;
++	}
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	selected_ctx->format = pix;
++	selected_ctx_u->format = true;
++	update_ctx_ctrl2[ctxnum] = true;
++
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_alpha - Sets the alpha value for pixel format
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @alpha: Alpha value.
++ *
++ * Returns 0 if successful, or -EINVAL if the alpha value is bigger than 16383.
++ **/
++int isp_csi2_ctx_config_alpha(u8 ctxnum, u16 alpha)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	if (alpha > 0x3FFF) {
++		printk(KERN_ERR "Wrong alpha value\n");
++		return -EINVAL;
++	}
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->alpha != alpha) {
++		selected_ctx->alpha = alpha;
++		selected_ctx_u->alpha = true;
++		update_ctx_ctrl3[ctxnum] = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_data_offset - Sets the offset between received lines
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @data_offset: Offset between first pixel of each 2 contiguous lines.
++ *
++ * Returns 0 if successful, or -EINVAL if the line offset is bigger than 1023.
++ **/
++int isp_csi2_ctx_config_data_offset(u8 ctxnum, u16 data_offset)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	if (data_offset > 0x3FF) {
++		printk(KERN_ERR "Wrong line offset\n");
++		return -EINVAL;
++	}
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->data_offset != data_offset) {
++		selected_ctx->data_offset = data_offset;
++		selected_ctx_u->data_offset = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_ping_addr - Sets Ping address for CSI2 Rx. buffer saving
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @ping_addr: 32 bit ISP MMU mapped address.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_config_ping_addr(u8 ctxnum, u32 ping_addr)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	ping_addr &= ~(0x1F);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->ping_addr != ping_addr) {
++		selected_ctx->ping_addr = ping_addr;
++		selected_ctx_u->ping_addr = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_pong_addr - Sets Pong address for CSI2 Rx. buffer saving
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @pong_addr: 32 bit ISP MMU mapped address.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_config_pong_addr(u8 ctxnum, u32 pong_addr)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	pong_addr &= ~(0x1F);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->pong_addr != pong_addr) {
++		selected_ctx->pong_addr = pong_addr;
++		selected_ctx_u->pong_addr = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_eof_enabled - Enables EOF signal assertion
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @eof_enabled: Boolean to enable/disable EOF signal assertion on received
++ *               packets.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_config_eof_enabled(u8 ctxnum, bool eof_enabled)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->eof_enabled != eof_enabled) {
++		selected_ctx->eof_enabled = eof_enabled;
++		selected_ctx_u->eof_enabled = true;
++		update_ctx_ctrl1[ctxnum] = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_eol_enabled - Enables EOL signal assertion
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @eol_enabled: Boolean to enable/disable EOL signal assertion on received
++ *               packets.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_config_eol_enabled(u8 ctxnum, bool eol_enabled)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->eol_enabled != eol_enabled) {
++		selected_ctx->eol_enabled = eol_enabled;
++		selected_ctx_u->eol_enabled = true;
++		update_ctx_ctrl1[ctxnum] = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_checksum_enabled - Enables Checksum check in rcvd packets
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @checksum_enabled: Boolean to enable/disable Checksum check on received
++ *                    packets
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_config_checksum_enabled(u8 ctxnum, bool checksum_enabled)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->checksum_enabled != checksum_enabled) {
++		selected_ctx->checksum_enabled = checksum_enabled;
++		selected_ctx_u->checksum_enabled = true;
++		update_ctx_ctrl1[ctxnum] = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_config_enabled - Enables specified CSI2 context
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @enabled: Boolean to enable/disable specified context.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_config_enabled(u8 ctxnum, bool enabled)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (selected_ctx->enabled != enabled) {
++		selected_ctx->enabled = enabled;
++		selected_ctx_u->enabled = true;
++		update_ctx_ctrl1[ctxnum] = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_update - Applies CSI2 context configuration.
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ * @force_update: Flag to force rewrite of registers, even if they haven't been
++ *                updated with the isp_csi2_ctx_config_*() functions.
++ *
++ * It only saves settings when they were previously updated using the
++ * isp_csi2_ctx_config_*() functions, unless the force_update flag is
++ * set to true.
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_update(u8 ctxnum, bool force_update)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++	u32 reg;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	if (update_ctx_ctrl1[ctxnum] || force_update) {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++				    ISPCSI2_CTX_CTRL1(ctxnum));
++		if (selected_ctx_u->frame_count || force_update) {
++			reg &= ~(ISPCSI2_CTX_CTRL1_COUNT_MASK);
++			reg |= selected_ctx->frame_count <<
++				ISPCSI2_CTX_CTRL1_COUNT_SHIFT;
++			selected_ctx_u->frame_count = false;
++		}
++		if (selected_ctx_u->eof_enabled || force_update) {
++			reg &= ~(ISPCSI2_CTX_CTRL1_EOF_EN_MASK);
++			if (selected_ctx->eof_enabled)
++				reg |= ISPCSI2_CTX_CTRL1_EOF_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTX_CTRL1_EOF_EN_DISABLE;
++			selected_ctx_u->eof_enabled = false;
++		}
++		if (selected_ctx_u->eol_enabled || force_update) {
++			reg &= ~(ISPCSI2_CTX_CTRL1_EOL_EN_MASK);
++			if (selected_ctx->eol_enabled)
++				reg |= ISPCSI2_CTX_CTRL1_EOL_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTX_CTRL1_EOL_EN_DISABLE;
++			selected_ctx_u->eol_enabled = false;
++		}
++		if (selected_ctx_u->checksum_enabled || force_update) {
++			reg &= ~(ISPCSI2_CTX_CTRL1_CS_EN_MASK);
++			if (selected_ctx->checksum_enabled)
++				reg |= ISPCSI2_CTX_CTRL1_CS_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTX_CTRL1_CS_EN_DISABLE;
++			selected_ctx_u->checksum_enabled = false;
++		}
++		if (selected_ctx_u->enabled || force_update) {
++			reg &= ~(ISPCSI2_CTX_CTRL1_CTX_EN_MASK);
++			if (selected_ctx->enabled)
++				reg |= ISPCSI2_CTX_CTRL1_CTX_EN_ENABLE;
++			else
++				reg |= ISPCSI2_CTX_CTRL1_CTX_EN_DISABLE;
++			selected_ctx_u->enabled = false;
++		}
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_CTX_CTRL1(ctxnum));
++		update_ctx_ctrl1[ctxnum] = false;
++	}
++
++	if (update_ctx_ctrl2[ctxnum] || force_update) {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++				    ISPCSI2_CTX_CTRL2(ctxnum));
++		if (selected_ctx_u->virtual_id || force_update) {
++			reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK);
++			reg |= selected_ctx->virtual_id <<
++				ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
++			selected_ctx_u->virtual_id = false;
++		}
++
++		if (selected_ctx_u->format || force_update) {
++			struct v4l2_pix_format *pix;
++			u16 new_format = 0;
++
++			reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK);
++			pix = &selected_ctx->format;
++			switch (pix->pixelformat) {
++			case V4L2_PIX_FMT_RGB565:
++			case V4L2_PIX_FMT_RGB565X:
++				new_format = 0x22;
++				break;
++			case V4L2_PIX_FMT_YUYV:
++			case V4L2_PIX_FMT_UYVY:
++				if (uses_videoport)
++					new_format = 0x9E;
++				else
++					new_format = 0x1E;
++				break;
++			case V4L2_PIX_FMT_RGB555:
++			case V4L2_PIX_FMT_RGB555X:
++				new_format = 0xA1;
++				break;
++			case V4L2_PIX_FMT_SGRBG10:
++				if (uses_videoport)
++					new_format = 0x12F;
++				else
++					new_format = 0xAB;
++				break;
++			}
++			reg |= (new_format << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT);
++			selected_ctx_u->format = false;
++		}
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_CTX_CTRL2(ctxnum));
++		update_ctx_ctrl2[ctxnum] = false;
++	}
++
++	if (update_ctx_ctrl3[ctxnum] || force_update) {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++				    ISPCSI2_CTX_CTRL3(ctxnum));
++		if (selected_ctx_u->alpha || force_update) {
++			reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK);
++			reg |= (selected_ctx->alpha <<
++				ISPCSI2_CTX_CTRL3_ALPHA_SHIFT);
++			selected_ctx_u->alpha = false;
++		}
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_CTX_CTRL3(ctxnum));
++		update_ctx_ctrl3[ctxnum] = false;
++	}
++
++	if (selected_ctx_u->data_offset) {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++				    ISPCSI2_CTX_DAT_OFST(ctxnum));
++		reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK;
++		reg |= selected_ctx->data_offset <<
++			ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_CTX_DAT_OFST(ctxnum));
++		selected_ctx_u->data_offset = false;
++	}
++
++	if (selected_ctx_u->ping_addr) {
++		reg = selected_ctx->ping_addr;
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_CTX_DAT_PING_ADDR(ctxnum));
++		selected_ctx_u->ping_addr = false;
++	}
++
++	if (selected_ctx_u->pong_addr) {
++		reg = selected_ctx->pong_addr;
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_CTX_DAT_PONG_ADDR(ctxnum));
++		selected_ctx_u->pong_addr = false;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_get - Gets specific CSI2 Context configuration
++ * @ctxnum: Context number, valid between 0 and 7 values.
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_get(u8 ctxnum)
++{
++	struct isp_csi2_ctx_cfg *selected_ctx;
++	struct isp_csi2_ctx_cfg_update *selected_ctx_u;
++	u32 reg;
++
++	isp_csi2_ctx_validate(&ctxnum);
++
++	selected_ctx = &current_csi2_cfg.contexts[ctxnum];
++	selected_ctx_u = &current_csi2_cfg_update.contexts[ctxnum];
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_CTX_CTRL1(ctxnum));
++	selected_ctx->frame_count = (reg & ISPCSI2_CTX_CTRL1_COUNT_MASK) >>
++		ISPCSI2_CTX_CTRL1_COUNT_SHIFT;
++	selected_ctx_u->frame_count = false;
++
++	if ((reg & ISPCSI2_CTX_CTRL1_EOF_EN_MASK) ==
++	    ISPCSI2_CTX_CTRL1_EOF_EN_ENABLE)
++		selected_ctx->eof_enabled = true;
++	else
++		selected_ctx->eof_enabled = false;
++	selected_ctx_u->eof_enabled = false;
++
++	if ((reg & ISPCSI2_CTX_CTRL1_EOL_EN_MASK) ==
++	    ISPCSI2_CTX_CTRL1_EOL_EN_ENABLE)
++		selected_ctx->eol_enabled = true;
++	else
++		selected_ctx->eol_enabled = false;
++	selected_ctx_u->eol_enabled = false;
++
++	if ((reg & ISPCSI2_CTX_CTRL1_CS_EN_MASK) ==
++	    ISPCSI2_CTX_CTRL1_CS_EN_ENABLE)
++		selected_ctx->checksum_enabled = true;
++	else
++		selected_ctx->checksum_enabled = false;
++	selected_ctx_u->checksum_enabled = false;
++
++	if ((reg & ISPCSI2_CTX_CTRL1_CTX_EN_MASK) ==
++	    ISPCSI2_CTX_CTRL1_CTX_EN_ENABLE)
++		selected_ctx->enabled = true;
++	else
++		selected_ctx->enabled = false;
++	selected_ctx_u->enabled = false;
++	update_ctx_ctrl1[ctxnum] = false;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_CTX_CTRL2(ctxnum));
++
++	selected_ctx->virtual_id = (reg & ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK) >>
++		ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
++	selected_ctx_u->virtual_id = false;
++
++	switch ((reg & ISPCSI2_CTX_CTRL2_FORMAT_MASK) >>
++		ISPCSI2_CTX_CTRL2_FORMAT_SHIFT) {
++	case 0x22:
++		selected_ctx->format.pixelformat = V4L2_PIX_FMT_RGB565;
++		break;
++	case 0x9E:
++	case 0x1E:
++		selected_ctx->format.pixelformat = V4L2_PIX_FMT_YUYV;
++		break;
++	case 0xA1:
++		selected_ctx->format.pixelformat = V4L2_PIX_FMT_RGB555;
++		break;
++	case 0xAB:
++	case 0x12F:
++		selected_ctx->format.pixelformat = V4L2_PIX_FMT_SGRBG10;
++		break;
++	}
++	selected_ctx_u->format = false;
++	update_ctx_ctrl2[ctxnum] = false;
++
++	selected_ctx->alpha = (isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++					     ISPCSI2_CTX_CTRL3(ctxnum)) &
++			       ISPCSI2_CTX_CTRL3_ALPHA_MASK) >>
++		ISPCSI2_CTX_CTRL3_ALPHA_SHIFT;
++	selected_ctx_u->alpha = false;
++	update_ctx_ctrl3[ctxnum] = false;
++
++	selected_ctx->data_offset = (isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++						   ISPCSI2_CTX_DAT_OFST(ctxnum)) &
++				     ISPCSI2_CTX_DAT_OFST_OFST_MASK) >>
++		ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
++	selected_ctx_u->data_offset = false;
++
++	selected_ctx->ping_addr = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++						ISPCSI2_CTX_DAT_PING_ADDR(ctxnum));
++	selected_ctx_u->ping_addr = false;
++
++	selected_ctx->pong_addr = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++						ISPCSI2_CTX_DAT_PONG_ADDR(ctxnum));
++	selected_ctx_u->pong_addr = false;
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_update_all - Applies all CSI2 context configuration.
++ * @force_update: Flag to force rewrite of registers, even if they haven't been
++ *                updated with the isp_csi2_ctx_config_*() functions.
++ *
++ * It only saves settings when they were previously updated using the
++ * isp_csi2_ctx_config_*() functions, unless the force_update flag is
++ * set to true.
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_update_all(bool force_update)
++{
++	u8 ctxnum;
++
++	for (ctxnum = 0; ctxnum < 8; ctxnum++)
++		isp_csi2_ctx_update(ctxnum, force_update);
++
++	return 0;
++}
++
++/**
++ * isp_csi2_ctx_get_all - Gets all CSI2 Context configurations
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_ctx_get_all(void)
++{
++	u8 ctxnum;
++
++	for (ctxnum = 0; ctxnum < 8; ctxnum++)
++		isp_csi2_ctx_get(ctxnum);
++
++	return 0;
++}
++
++int isp_csi2_phy_config(struct isp_csi2_phy_cfg *desiredphyconfig)
++{
++	struct isp_csi2_phy_cfg *currphy = &current_csi2_cfg.phy;
++	struct isp_csi2_phy_cfg_update *currphy_u =
++						&current_csi2_cfg_update.phy;
++
++	if ((desiredphyconfig->tclk_term > 0x7f) ||
++				(desiredphyconfig->tclk_miss > 0x3)) {
++		printk(KERN_ERR "Invalid PHY configuration sent by the"
++								" driver\n");
++		return -EINVAL;
++	}
++
++	if (currphy->ths_term != desiredphyconfig->ths_term) {
++		currphy->ths_term = desiredphyconfig->ths_term;
++		currphy_u->ths_term = true;
++		update_phy_cfg0 = true;
++	}
++	if (currphy->ths_settle != desiredphyconfig->ths_settle) {
++		currphy->ths_settle = desiredphyconfig->ths_settle;
++		currphy_u->ths_settle = true;
++		update_phy_cfg0 = true;
++	}
++	if (currphy->tclk_term != desiredphyconfig->tclk_term) {
++		currphy->tclk_term = desiredphyconfig->tclk_term;
++		currphy_u->tclk_term = true;
++		update_phy_cfg1 = true;
++	}
++	if (currphy->tclk_miss != desiredphyconfig->tclk_miss) {
++		currphy->tclk_miss = desiredphyconfig->tclk_miss;
++		currphy_u->tclk_miss = true;
++		update_phy_cfg1 = true;
++	}
++	if (currphy->tclk_settle != desiredphyconfig->tclk_settle) {
++		currphy->tclk_settle = desiredphyconfig->tclk_settle;
++		currphy_u->tclk_settle = true;
++		update_phy_cfg1 = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_calc_phy_cfg0 - Calculates D-PHY config based on the MIPIClk speed.
++ * @mipiclk: MIPI clock frequency being used with CSI2 sensor.
++ * @lbound_hs_settle: Lower bound for CSI2 High Speed Settle transition.
++ * @ubound_hs_settle: Upper bound for CSI2 High Speed Settle transition.
++ *
++ * From TRM, we have the same calculation for HS Termination signal.
++ *  THS_TERM  = ceil( 12.5ns / DDRCLK period ) - 1
++ * But for Settle, we use the mid value between the two passed boundaries from
++ * sensor:
++ *  THS_SETTLE = (Upper bound + Lower bound) / 2
++ *
++ * Always returns 0.
++ */
++int isp_csi2_calc_phy_cfg0(u32 mipiclk, u32 lbound_hs_settle,
++							u32 ubound_hs_settle)
++{
++	struct isp_csi2_phy_cfg *currphy = &current_csi2_cfg.phy;
++	struct isp_csi2_phy_cfg_update *currphy_u =
++						&current_csi2_cfg_update.phy;
++	u32 tmp, ddrclk = mipiclk >> 1;
++
++	/* Calculate THS_TERM */
++	tmp = ddrclk / 80000000;
++	if ((ddrclk % 80000000) > 0)
++		tmp++;
++	currphy->ths_term = tmp - 1;
++	currphy_u->ths_term = true;
++
++	/* Calculate THS_SETTLE */
++	currphy->ths_settle = (ubound_hs_settle + lbound_hs_settle) / 2;
++
++	currphy_u->ths_settle = true;
++	isp_csi2_phy_update(true);
++	return 0;
++}
++EXPORT_SYMBOL(isp_csi2_calc_phy_cfg0);
++
++/**
++ * isp_csi2_phy_update - Applies CSI2 D-PHY configuration.
++ * @force_update: Flag to force rewrite of registers, even if they haven't been
++ *                updated with the isp_csi2_phy_config_*() functions.
++ *
++ * It only saves settings when they were previously updated using the
++ * isp_csi2_phy_config_*() functions, unless the force_update flag is
++	* set to true.
++	* Always returns 0.
++	**/
++int isp_csi2_phy_update(bool force_update)
++{
++	struct isp_csi2_phy_cfg *currphy = &current_csi2_cfg.phy;
++	struct isp_csi2_phy_cfg_update *currphy_u =
++		&current_csi2_cfg_update.phy;
++	u32 reg;
++
++	if (update_phy_cfg0 || force_update) {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2PHY, ISPCSI2PHY_CFG0);
++		if (currphy_u->ths_term || force_update) {
++			reg &= ~ISPCSI2PHY_CFG0_THS_TERM_MASK;
++			reg |= (currphy->ths_term <<
++				ISPCSI2PHY_CFG0_THS_TERM_SHIFT);
++			currphy_u->ths_term = false;
++		}
++		if (currphy_u->ths_settle || force_update) {
++			reg &= ~ISPCSI2PHY_CFG0_THS_SETTLE_MASK;
++			reg |= (currphy->ths_settle <<
++				ISPCSI2PHY_CFG0_THS_SETTLE_SHIFT);
++			currphy_u->ths_settle = false;
++		}
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2PHY, ISPCSI2PHY_CFG0);
++		update_phy_cfg0 = false;
++	}
++
++	if (update_phy_cfg1 || force_update) {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2PHY, ISPCSI2PHY_CFG1);
++		if (currphy_u->tclk_term || force_update) {
++			reg &= ~ISPCSI2PHY_CFG1_TCLK_TERM_MASK;
++			reg |= (currphy->tclk_term <<
++				ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT);
++			currphy_u->tclk_term = false;
++		}
++		if (currphy_u->tclk_miss || force_update) {
++			reg &= ~ISPCSI2PHY_CFG1_TCLK_MISS_MASK;
++			reg |= (currphy->tclk_miss <<
++				ISPCSI2PHY_CFG1_TCLK_MISS_SHIFT);
++			currphy_u->tclk_miss = false;
++		}
++		if (currphy_u->tclk_settle || force_update) {
++			reg &= ~ISPCSI2PHY_CFG1_TCLK_SETTLE_MASK;
++			reg |= (currphy->tclk_settle <<
++				ISPCSI2PHY_CFG1_TCLK_SETTLE_SHIFT);
++			currphy_u->tclk_settle = false;
++		}
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2PHY, ISPCSI2PHY_CFG1);
++		update_phy_cfg1 = false;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_phy_get - Gets CSI2 D-PHY configuration
++ *
++ * Gets settings from HW registers and fills in the internal driver memory
++ * Always returns 0.
++ **/
++int isp_csi2_phy_get(void)
++{
++	struct isp_csi2_phy_cfg *currphy = &current_csi2_cfg.phy;
++	struct isp_csi2_phy_cfg_update *currphy_u =
++		&current_csi2_cfg_update.phy;
++	u32 reg;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2PHY, ISPCSI2PHY_CFG0);
++	currphy->ths_term = (reg & ISPCSI2PHY_CFG0_THS_TERM_MASK) >>
++		ISPCSI2PHY_CFG0_THS_TERM_SHIFT;
++	currphy_u->ths_term = false;
++
++	currphy->ths_settle = (reg & ISPCSI2PHY_CFG0_THS_SETTLE_MASK) >>
++		ISPCSI2PHY_CFG0_THS_SETTLE_SHIFT;
++	currphy_u->ths_settle = false;
++	update_phy_cfg0 = false;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2PHY, ISPCSI2PHY_CFG1);
++
++	currphy->tclk_term = (reg & ISPCSI2PHY_CFG1_TCLK_TERM_MASK) >>
++		ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT;
++	currphy_u->tclk_term = false;
++
++	currphy->tclk_miss = (reg & ISPCSI2PHY_CFG1_TCLK_MISS_MASK) >>
++		ISPCSI2PHY_CFG1_TCLK_MISS_SHIFT;
++	currphy_u->tclk_miss = false;
++
++	currphy->tclk_settle = (reg & ISPCSI2PHY_CFG1_TCLK_SETTLE_MASK) >>
++		ISPCSI2PHY_CFG1_TCLK_SETTLE_SHIFT;
++	currphy_u->tclk_settle = false;
++
++	update_phy_cfg1 = false;
++	return 0;
++}
++
++/**
++ * isp_csi2_timings_config_forcerxmode - Sets Force Rx mode on stop state count
++ * @force_rx_mode: Boolean to enable/disable forcing Rx mode in CSI2 receiver
++ *
++ * Returns 0 if successful, or -EINVAL if wrong ComplexIO number is selected.
++ **/
++int isp_csi2_timings_config_forcerxmode(u8 io, bool force_rx_mode)
++{
++	struct isp_csi2_timings_cfg *currtimings;
++	struct isp_csi2_timings_cfg_update *currtimings_u;
++
++	if (io < 1 || io > 2) {
++		printk(KERN_ERR "CSI2 - Timings config: Invalid IO number\n");
++		return -EINVAL;
++	}
++
++	currtimings = &current_csi2_cfg.timings[io - 1];
++	currtimings_u = &current_csi2_cfg_update.timings[io - 1];
++	if (currtimings->force_rx_mode != force_rx_mode) {
++		currtimings->force_rx_mode = force_rx_mode;
++		currtimings_u->force_rx_mode = true;
++		update_timing = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_timings_config_stopstate_16x - Sets 16x factor for L3 cycles
++ * @stop_state_16x: Boolean to use or not use the 16x multiplier for stop count
++ *
++ * Returns 0 if successful, or -EINVAL if wrong ComplexIO number is selected.
++ **/
++int isp_csi2_timings_config_stopstate_16x(u8 io, bool stop_state_16x)
++{
++	struct isp_csi2_timings_cfg *currtimings;
++	struct isp_csi2_timings_cfg_update *currtimings_u;
++
++	if (io < 1 || io > 2) {
++		printk(KERN_ERR "CSI2 - Timings config: Invalid IO number\n");
++		return -EINVAL;
++	}
++
++	currtimings = &current_csi2_cfg.timings[io - 1];
++	currtimings_u = &current_csi2_cfg_update.timings[io - 1];
++	if (currtimings->stop_state_16x != stop_state_16x) {
++		currtimings->stop_state_16x = stop_state_16x;
++		currtimings_u->stop_state_16x = true;
++		update_timing = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_timings_config_stopstate_4x - Sets 4x factor for L3 cycles
++ * @stop_state_4x: Boolean to use or not use the 4x multiplier for stop count
++ *
++ * Returns 0 if successful, or -EINVAL if wrong ComplexIO number is selected.
++ **/
++int isp_csi2_timings_config_stopstate_4x(u8 io, bool stop_state_4x)
++{
++	struct isp_csi2_timings_cfg *currtimings;
++	struct isp_csi2_timings_cfg_update *currtimings_u;
++
++	if (io < 1 || io > 2) {
++		printk(KERN_ERR "CSI2 - Timings config: Invalid IO number\n");
++		return -EINVAL;
++	}
++
++	currtimings = &current_csi2_cfg.timings[io - 1];
++	currtimings_u = &current_csi2_cfg_update.timings[io - 1];
++	if (currtimings->stop_state_4x != stop_state_4x) {
++		currtimings->stop_state_4x = stop_state_4x;
++		currtimings_u->stop_state_4x = true;
++		update_timing = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_timings_config_stopstate_cnt - Sets L3 cycles
++ * @stop_state_counter: Stop state counter value for L3 cycles
++ *
++ * Returns 0 if successful, or -EINVAL if wrong ComplexIO number is selected.
++ **/
++int isp_csi2_timings_config_stopstate_cnt(u8 io, u16 stop_state_counter)
++{
++	struct isp_csi2_timings_cfg *currtimings;
++	struct isp_csi2_timings_cfg_update *currtimings_u;
++
++	if (io < 1 || io > 2) {
++		printk(KERN_ERR "CSI2 - Timings config: Invalid IO number\n");
++		return -EINVAL;
++	}
++
++	currtimings = &current_csi2_cfg.timings[io - 1];
++	currtimings_u = &current_csi2_cfg_update.timings[io - 1];
++	if (currtimings->stop_state_counter != stop_state_counter) {
++		currtimings->stop_state_counter = (stop_state_counter & 0x1FFF);
++		currtimings_u->stop_state_counter = true;
++		update_timing = true;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_timings_update - Applies specified CSI2 timing configuration.
++ * @io: IO number (1 or 2) which specifies which ComplexIO are we updating
++ * @force_update: Flag to force rewrite of registers, even if they haven't been
++ *                updated with the isp_csi2_timings_config_*() functions.
++ *
++ * It only saves settings when they were previously updated using the
++ * isp_csi2_timings_config_*() functions, unless the force_update flag is
++ * set to true.
++ * Returns 0 if successful, or -EINVAL if invalid IO number is passed.
++ **/
++int isp_csi2_timings_update(u8 io, bool force_update)
++{
++	struct isp_csi2_timings_cfg *currtimings;
++	struct isp_csi2_timings_cfg_update *currtimings_u;
++	u32 reg;
++
++	if (io < 1 || io > 2) {
++		printk(KERN_ERR "CSI2 - Timings config: Invalid IO number\n");
++		return -EINVAL;
++	}
++
++	currtimings = &current_csi2_cfg.timings[io - 1];
++	currtimings_u = &current_csi2_cfg_update.timings[io - 1];
++
++	if (update_timing || force_update) {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_TIMING);
++		if (currtimings_u->force_rx_mode || force_update) {
++			reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO_MASK(io);
++			if (currtimings->force_rx_mode)
++				reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO_ENABLE
++					(io);
++			else
++				reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO_DISABLE
++					(io);
++			currtimings_u->force_rx_mode = false;
++		}
++		if (currtimings_u->stop_state_16x || force_update) {
++			reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO_MASK(io);
++			if (currtimings->stop_state_16x)
++				reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO_ENABLE
++					(io);
++			else
++				reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO_DISABLE
++					(io);
++			currtimings_u->stop_state_16x = false;
++		}
++		if (currtimings_u->stop_state_4x || force_update) {
++			reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO_MASK(io);
++			if (currtimings->stop_state_4x) {
++				reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO_ENABLE
++					(io);
++			} else {
++				reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO_DISABLE
++					(io);
++			}
++			currtimings_u->stop_state_4x = false;
++		}
++		if (currtimings_u->stop_state_counter || force_update) {
++			reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(io);
++			reg |= currtimings->stop_state_counter <<
++				ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(io);
++			currtimings_u->stop_state_counter = false;
++		}
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_TIMING);
++		update_timing = false;
++	}
++	return 0;
++}
++
++/**
++ * isp_csi2_timings_get - Gets specific CSI2 ComplexIO timing configuration
++ * @io: IO number (1 or 2) which specifies which ComplexIO are we getting
++ *
++ * Gets settings from HW registers and fills in the internal driver memory
++ * Returns 0 if successful, or -EINVAL if invalid IO number is passed.
++ **/
++int isp_csi2_timings_get(u8 io)
++{
++	struct isp_csi2_timings_cfg *currtimings;
++	struct isp_csi2_timings_cfg_update *currtimings_u;
++	u32 reg;
++
++	if (io < 1 || io > 2) {
++		printk(KERN_ERR "CSI2 - Timings config: Invalid IO number\n");
++		return -EINVAL;
++	}
++
++	currtimings = &current_csi2_cfg.timings[io - 1];
++	currtimings_u = &current_csi2_cfg_update.timings[io - 1];
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_TIMING);
++	if ((reg & ISPCSI2_TIMING_FORCE_RX_MODE_IO_MASK(io)) ==
++	    ISPCSI2_TIMING_FORCE_RX_MODE_IO_ENABLE(io))
++		currtimings->force_rx_mode = true;
++	else
++		currtimings->force_rx_mode = false;
++	currtimings_u->force_rx_mode = false;
++
++	if ((reg & ISPCSI2_TIMING_STOP_STATE_X16_IO_MASK(io)) ==
++	    ISPCSI2_TIMING_STOP_STATE_X16_IO_ENABLE(io))
++		currtimings->stop_state_16x = true;
++	else
++		currtimings->stop_state_16x = false;
++	currtimings_u->stop_state_16x = false;
++
++	if ((reg & ISPCSI2_TIMING_STOP_STATE_X4_IO_MASK(io)) ==
++	    ISPCSI2_TIMING_STOP_STATE_X4_IO_ENABLE(io))
++		currtimings->stop_state_4x = true;
++	else
++		currtimings->stop_state_4x = false;
++	currtimings_u->stop_state_4x = false;
++
++	currtimings->stop_state_counter = (reg &
++					   ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(io)) >>
++		ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(io);
++	currtimings_u->stop_state_counter = false;
++	update_timing = false;
++	return 0;
++}
++
++/**
++ * isp_csi2_timings_update_all - Applies specified CSI2 timing configuration.
++ * @force_update: Flag to force rewrite of registers, even if they haven't been
++ *                updated with the isp_csi2_timings_config_*() functions.
++ *
++ * It only saves settings when they were previously updated using the
++ * isp_csi2_timings_config_*() functions, unless the force_update flag is
++ * set to true.
++ * Always returns 0.
++ **/
++int isp_csi2_timings_update_all(bool force_update)
++{
++	int i;
++
++	for (i = 1; i < 3; i++)
++		isp_csi2_timings_update(i, force_update);
++	return 0;
++}
++
++/**
++ * isp_csi2_timings_get_all - Gets all CSI2 ComplexIO timing configurations
++ *
++ * Always returns 0.
++ **/
++int isp_csi2_timings_get_all(void)
++{
++	int i;
++
++	for (i = 1; i < 3; i++)
++		isp_csi2_timings_get(i);
++	return 0;
++}
++
++/**
++ * isp_csi2_isr - CSI2 interrupt handling.
++ **/
++void isp_csi2_isr(void)
++{
++	u32 csi2_irqstatus, cpxio1_irqstatus, ctxirqstatus;
++
++	csi2_irqstatus = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++				       ISPCSI2_IRQSTATUS);
++	isp_reg_writel(csi2_irqstatus, OMAP3_ISP_IOMEM_CSI2A,
++		       ISPCSI2_IRQSTATUS);
++
++	if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ) {
++		cpxio1_irqstatus = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++						 ISPCSI2_COMPLEXIO1_IRQSTATUS);
++		isp_reg_writel(cpxio1_irqstatus, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_COMPLEXIO1_IRQSTATUS);
++		printk(KERN_ERR "CSI2: ComplexIO Error IRQ %x\n",
++		       cpxio1_irqstatus);
++	}
++
++	if (csi2_irqstatus & ISPCSI2_IRQSTATUS_CONTEXT(0)) {
++		ctxirqstatus = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++					     ISPCSI2_CTX_IRQSTATUS(0));
++		isp_reg_writel(ctxirqstatus, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_CTX_IRQSTATUS(0));
++	}
++
++	if (csi2_irqstatus & ISPCSI2_IRQSTATUS_OCP_ERR_IRQ)
++		printk(KERN_ERR "CSI2: OCP Transmission Error\n");
++
++	if (csi2_irqstatus & ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ)
++		printk(KERN_ERR "CSI2: Short packet receive error\n");
++
++	if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ)
++		printk(KERN_DEBUG "CSI2: ECC correction done\n");
++
++	if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ)
++		printk(KERN_ERR "CSI2: ECC correction failed\n");
++
++	if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ)
++		printk(KERN_ERR "CSI2: ComplexIO #2 failed\n");
++
++	if (csi2_irqstatus & ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ)
++		printk(KERN_ERR "CSI2: FIFO overflow error\n");
++
++	return;
++}
++EXPORT_SYMBOL(isp_csi2_isr);
++
++/**
++ * isp_csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
++ * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
++ **/
++void isp_csi2_irq_complexio1_set(int enable)
++{
++	u32 reg;
++	reg = ISPCSI2_COMPLEXIO1_IRQENABLE_STATEALLULPMEXIT |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_STATEALLULPMENTER |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM5 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL5 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC5 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS5 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS5 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM4 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL4 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC4 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS4 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS4 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM3 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL3 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC3 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS3 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS3 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM2 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL2 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC2 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS2 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS2 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM1 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL1 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC1 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS1 |
++		ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS1;
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++		       ISPCSI2_COMPLEXIO1_IRQSTATUS);
++	if (enable) {
++		reg |= isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++				     ISPCSI2_COMPLEXIO1_IRQENABLE);
++	} else
++		reg = 0;
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++		       ISPCSI2_COMPLEXIO1_IRQENABLE);
++}
++EXPORT_SYMBOL(isp_csi2_irq_complexio1_set);
++
++/**
++ * isp_csi2_irq_ctx_set - Enables CSI2 Context IRQs.
++ * @enable: Enable/disable CSI2 Context interrupts
++ **/
++void isp_csi2_irq_ctx_set(int enable)
++{
++	u32 reg;
++	int i;
++
++	reg = ISPCSI2_CTX_IRQSTATUS_FS_IRQ | ISPCSI2_CTX_IRQSTATUS_FE_IRQ;
++	for (i = 0; i < 8; i++) {
++		isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A,
++			       ISPCSI2_CTX_IRQSTATUS(i));
++		if (enable) {
++			isp_reg_or(OMAP3_ISP_IOMEM_CSI2A,
++				   ISPCSI2_CTX_IRQENABLE(i), reg);
++		} else {
++			isp_reg_writel(0, OMAP3_ISP_IOMEM_CSI2A,
++				       ISPCSI2_CTX_IRQENABLE(i));
++		}
++	}
++
++}
++EXPORT_SYMBOL(isp_csi2_irq_ctx_set);
++
++/**
++ * isp_csi2_irq_status_set - Enables CSI2 Status IRQs.
++ * @enable: Enable/disable CSI2 Status interrupts
++ **/
++void isp_csi2_irq_status_set(int enable)
++{
++	u32 reg;
++	reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
++		ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
++		ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ |
++		ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
++		ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
++		ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ |
++		ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ |
++		ISPCSI2_IRQSTATUS_CONTEXT(0);
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_IRQSTATUS);
++	if (enable)
++		reg |= isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_IRQENABLE);
++	else
++		reg = 0;
++
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_IRQENABLE);
++}
++EXPORT_SYMBOL(isp_csi2_irq_status_set);
++
++/**
++ * isp_csi2_irq_status_set - Enables main CSI2 IRQ.
++ * @enable: Enable/disable main CSI2 interrupt
++ **/
++void isp_csi2_irq_set(int enable)
++{
++	isp_reg_writel(IRQ0STATUS_CSIA_IRQ, OMAP3_ISP_IOMEM_MAIN,
++		       ISP_IRQ0STATUS);
++	isp_reg_and_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++		       ~IRQ0ENABLE_CSIA_IRQ,
++		       (enable ? IRQ0ENABLE_CSIA_IRQ : 0));
++}
++EXPORT_SYMBOL(isp_csi2_irq_set);
++
++/**
++ * isp_csi2_irq_all_set - Enable/disable CSI2 interrupts.
++ * @enable: 0-Disable, 1-Enable.
++ **/
++void isp_csi2_irq_all_set(int enable)
++{
++	if (enable) {
++		isp_csi2_irq_complexio1_set(enable);
++		isp_csi2_irq_ctx_set(enable);
++		isp_csi2_irq_status_set(enable);
++		isp_csi2_irq_set(enable);
++	} else {
++		isp_csi2_irq_set(enable);
++		isp_csi2_irq_status_set(enable);
++		isp_csi2_irq_ctx_set(enable);
++		isp_csi2_irq_complexio1_set(enable);
++	}
++	return;
++}
++EXPORT_SYMBOL(isp_csi2_irq_all_set);
++
++/**
++ * isp_csi2_reset - Resets the CSI2 module.
++ *
++ * Returns 0 if successful, or -EBUSY if power command didn't respond.
++ **/
++int isp_csi2_reset(void)
++{
++	u32 reg;
++	u8 soft_reset_retries = 0;
++	int i;
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_SYSCONFIG);
++	reg |= ISPCSI2_SYSCONFIG_SOFT_RESET_RESET;
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_SYSCONFIG);
++
++	do {
++		reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_SYSSTATUS) &
++			ISPCSI2_SYSSTATUS_RESET_DONE_MASK;
++		if (reg == ISPCSI2_SYSSTATUS_RESET_DONE_DONE)
++			break;
++		soft_reset_retries++;
++		if (soft_reset_retries < 5)
++			udelay(100);
++	} while (soft_reset_retries < 5);
++
++	if (soft_reset_retries == 5) {
++		printk(KERN_ERR "CSI2: Soft reset try count exceeded!\n");
++		return -EBUSY;
++	}
++
++	reg = isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_SYSCONFIG);
++	reg &= ~ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK;
++	reg |= ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO;
++	reg &= ~ISPCSI2_SYSCONFIG_AUTO_IDLE_MASK;
++	isp_reg_writel(reg, OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_SYSCONFIG);
++
++	uses_videoport = false;
++	update_complexio_cfg1 = false;
++	update_phy_cfg0 = false;
++	update_phy_cfg1 = false;
++	for (i = 0; i < 8; i++) {
++		update_ctx_ctrl1[i] = false;
++		update_ctx_ctrl2[i] = false;
++		update_ctx_ctrl3[i] = false;
++	}
++	update_timing = false;
++	update_ctrl = false;
++
++	isp_csi2_complexio_lanes_get();
++	isp_csi2_ctrl_get();
++	isp_csi2_ctx_get_all();
++	isp_csi2_phy_get();
++	isp_csi2_timings_get_all();
++
++	isp_csi2_complexio_power_autoswitch(true);
++	isp_csi2_complexio_power(ISP_CSI2_POWER_ON);
++
++	isp_csi2_timings_config_forcerxmode(1, true);
++	isp_csi2_timings_config_stopstate_cnt(1, 0x1FF);
++	isp_csi2_timings_update_all(true);
++
++	return 0;
++}
++
++/**
++ * isp_csi2_enable - Enables the CSI2 module.
++ * @enable: Enables/disables the CSI2 module.
++ **/
++void isp_csi2_enable(int enable)
++{
++	if (enable) {
++		isp_csi2_ctx_config_enabled(0, true);
++		isp_csi2_ctx_config_eof_enabled(0, true);
++		isp_csi2_ctx_config_checksum_enabled(0, true);
++		isp_csi2_ctx_update(0, false);
++
++		isp_csi2_ctrl_config_ecc_enable(true);
++		isp_csi2_ctrl_config_if_enable(true);
++		isp_csi2_ctrl_update(false);
++	} else {
++		isp_csi2_ctx_config_enabled(0, false);
++		isp_csi2_ctx_config_eof_enabled(0, false);
++		isp_csi2_ctx_config_checksum_enabled(0, false);
++		isp_csi2_ctx_update(0, false);
++
++		isp_csi2_ctrl_config_ecc_enable(false);
++		isp_csi2_ctrl_config_if_enable(false);
++		isp_csi2_ctrl_update(false);
++	}
++}
++EXPORT_SYMBOL(isp_csi2_enable);
++
++/**
++ * isp_csi2_regdump - Prints CSI2 debug information.
++ **/
++void isp_csi2_regdump(void)
++{
++	printk(KERN_DEBUG "-------------Register dump-------------\n");
++
++	printk(KERN_DEBUG "ISP_CTRL: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL));
++	printk(KERN_DEBUG "ISP_TCTRL_CTRL: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL));
++
++	printk(KERN_DEBUG "ISPCCDC_SDR_ADDR: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SDR_ADDR));
++	printk(KERN_DEBUG "ISPCCDC_SYN_MODE: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_SYN_MODE));
++	printk(KERN_DEBUG "ISPCCDC_CFG: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_CFG));
++	printk(KERN_DEBUG "ISPCCDC_FMTCFG: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG));
++	printk(KERN_DEBUG "ISPCCDC_HSIZE_OFF: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HSIZE_OFF));
++	printk(KERN_DEBUG "ISPCCDC_HORZ_INFO: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CCDC, ISPCCDC_HORZ_INFO));
++	printk(KERN_DEBUG "ISPCCDC_VERT_START: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++			     ISPCCDC_VERT_START));
++	printk(KERN_DEBUG "ISPCCDC_VERT_LINES: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CCDC,
++			     ISPCCDC_VERT_LINES));
++
++	printk(KERN_DEBUG "ISPCSI2_COMPLEXIO_CFG1: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_COMPLEXIO_CFG1));
++	printk(KERN_DEBUG "ISPCSI2_SYSSTATUS: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_SYSSTATUS));
++	printk(KERN_DEBUG "ISPCSI2_SYSCONFIG: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_SYSCONFIG));
++	printk(KERN_DEBUG "ISPCSI2_IRQENABLE: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_IRQENABLE));
++	printk(KERN_DEBUG "ISPCSI2_IRQSTATUS: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_IRQSTATUS));
++
++	printk(KERN_DEBUG "ISPCSI2_CTX_IRQENABLE(0): %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_CTX_IRQENABLE(0)));
++	printk(KERN_DEBUG "ISPCSI2_CTX_IRQSTATUS(0): %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_CTX_IRQSTATUS(0)));
++	printk(KERN_DEBUG "ISPCSI2_TIMING: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_TIMING));
++	printk(KERN_DEBUG "ISPCSI2PHY_CFG0: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2PHY,
++			     ISPCSI2PHY_CFG0));
++	printk(KERN_DEBUG "ISPCSI2PHY_CFG1: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2PHY,
++			     ISPCSI2PHY_CFG1));
++	printk(KERN_DEBUG "ISPCSI2_CTX_CTRL1(0): %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_CTX_CTRL1(0)));
++	printk(KERN_DEBUG "ISPCSI2_CTX_CTRL2(0): %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_CTX_CTRL2(0)));
++	printk(KERN_DEBUG "ISPCSI2_CTX_CTRL3(0): %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_CTX_CTRL3(0)));
++	printk(KERN_DEBUG "ISPCSI2_CTX_DAT_OFST(0): %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_CTX_DAT_OFST(0)));
++	printk(KERN_DEBUG "ISPCSI2_CTX_DAT_PING_ADDR(0): %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_CTX_DAT_PING_ADDR(0)));
++	printk(KERN_DEBUG "ISPCSI2_CTX_DAT_PONG_ADDR(0): %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A,
++			     ISPCSI2_CTX_DAT_PONG_ADDR(0)));
++	printk(KERN_DEBUG "ISPCSI2_CTRL: %x\n",
++	       isp_reg_readl(OMAP3_ISP_IOMEM_CSI2A, ISPCSI2_CTRL));
++	printk(KERN_DEBUG "---------------------------------------\n");
++}
++
++/**
++ * isp_csi2_cleanup - Routine for module driver cleanup
++ **/
++void isp_csi2_cleanup(void)
++{
++	return;
++}
++
++/**
++ * isp_csi2_init - Routine for module driver init
++ **/
++int __init isp_csi2_init(void)
++{
++	int i;
++
++	update_complexio_cfg1 = false;
++	update_phy_cfg0 = false;
++	update_phy_cfg1 = false;
++	for (i = 0; i < 8; i++) {
++		update_ctx_ctrl1[i] = false;
++		update_ctx_ctrl2[i] = false;
++		update_ctx_ctrl3[i] = false;
++	}
++	update_timing = false;
++	update_ctrl = false;
++
++	memset(&current_csi2_cfg, 0, sizeof(current_csi2_cfg));
++	memset(&current_csi2_cfg_update, 0, sizeof(current_csi2_cfg_update));
++	return 0;
++}
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("ISP CSI2 Receiver Module");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/media/video/isp/ispcsi2.h b/drivers/media/video/isp/ispcsi2.h
+new file mode 100644
+index 0000000..4582c96
+--- /dev/null
++++ b/drivers/media/video/isp/ispcsi2.h
+@@ -0,0 +1,232 @@
++/*
++ * ispcsi2.h
++ *
++ * Copyright (C) 2009 Texas Instruments.
++ *
++ * Contributors:
++ * 	Sergio Aguirre <saaguirre@ti.com>
++ * 	Dominic Curran <dcurran@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_CSI2_API_H
++#define OMAP_ISP_CSI2_API_H
++#include <linux/videodev2.h>
++
++enum isp_csi2_irqevents {
++	OCP_ERR_IRQ = 0x4000,
++	SHORT_PACKET_IRQ = 0x2000,
++	ECC_CORRECTION_IRQ = 0x1000,
++	ECC_NO_CORRECTION_IRQ = 0x800,
++	COMPLEXIO2_ERR_IRQ = 0x400,
++	COMPLEXIO1_ERR_IRQ = 0x200,
++	FIFO_OVF_IRQ = 0x100,
++	CONTEXT7 = 0x80,
++	CONTEXT6 = 0x40,
++	CONTEXT5 = 0x20,
++	CONTEXT4 = 0x10,
++	CONTEXT3 = 0x8,
++	CONTEXT2 = 0x4,
++	CONTEXT1 = 0x2,
++	CONTEXT0 = 0x1,
++};
++
++enum isp_csi2_ctx_irqevents {
++	CTX_ECC_CORRECTION = 0x100,
++	CTX_LINE_NUMBER = 0x80,
++	CTX_FRAME_NUMBER = 0x40,
++	CTX_CS = 0x20,
++	CTX_LE = 0x8,
++	CTX_LS = 0x4,
++	CTX_FE = 0x2,
++	CTX_FS = 0x1,
++};
++
++enum isp_csi2_power_cmds {
++	ISP_CSI2_POWER_OFF,
++	ISP_CSI2_POWER_ON,
++	ISP_CSI2_POWER_ULPW,
++};
++
++enum isp_csi2_frame_mode {
++	ISP_CSI2_FRAME_IMMEDIATE,
++	ISP_CSI2_FRAME_AFTERFEC,
++};
++
++struct csi2_lanecfg {
++	u8 pos;
++	u8 pol;
++};
++
++struct isp_csi2_lanes_cfg {
++	struct csi2_lanecfg data[4];
++	struct csi2_lanecfg clk;
++};
++
++struct isp_csi2_lanes_cfg_update {
++	bool data[4];
++	bool clk;
++};
++
++struct isp_csi2_phy_cfg {
++	u8 ths_term;
++	u8 ths_settle;
++	u8 tclk_term;
++	unsigned tclk_miss:1;
++	u8 tclk_settle;
++};
++
++struct isp_csi2_phy_cfg_update {
++	bool ths_term;
++	bool ths_settle;
++	bool tclk_term;
++	bool tclk_miss;
++	bool tclk_settle;
++};
++
++struct isp_csi2_ctx_cfg {
++	u8 virtual_id;
++	u8 frame_count;
++	struct v4l2_pix_format format;
++	u16 alpha;
++	u16 data_offset;
++	u32 ping_addr;
++	u32 pong_addr;
++	bool eof_enabled;
++	bool eol_enabled;
++	bool checksum_enabled;
++	bool enabled;
++};
++
++struct isp_csi2_ctx_cfg_update {
++	bool virtual_id;
++	bool frame_count;
++	bool format;
++	bool alpha;
++	bool data_offset;
++	bool ping_addr;
++	bool pong_addr;
++	bool eof_enabled;
++	bool eol_enabled;
++	bool checksum_enabled;
++	bool enabled;
++};
++
++struct isp_csi2_timings_cfg {
++	bool force_rx_mode;
++	bool stop_state_16x;
++	bool stop_state_4x;
++	u16 stop_state_counter;
++};
++
++struct isp_csi2_timings_cfg_update {
++	bool force_rx_mode;
++	bool stop_state_16x;
++	bool stop_state_4x;
++	bool stop_state_counter;
++};
++
++struct isp_csi2_ctrl_cfg {
++	bool vp_clk_enable;
++	bool vp_only_enable;
++	u8 vp_out_ctrl;
++	bool debug_enable;
++	u8 burst_size;
++	enum isp_csi2_frame_mode frame_mode;
++	bool ecc_enable;
++	bool secure_mode;
++	bool if_enable;
++};
++
++struct isp_csi2_ctrl_cfg_update {
++	bool vp_clk_enable;
++	bool vp_only_enable;
++	bool vp_out_ctrl;
++	bool debug_enable;
++	bool burst_size;
++	bool frame_mode;
++	bool ecc_enable;
++	bool secure_mode;
++	bool if_enable;
++};
++
++struct isp_csi2_cfg {
++	struct isp_csi2_lanes_cfg lanes;
++	struct isp_csi2_phy_cfg phy;
++	struct isp_csi2_ctx_cfg contexts[8];
++	struct isp_csi2_timings_cfg timings[2];
++	struct isp_csi2_ctrl_cfg ctrl;
++};
++
++struct isp_csi2_cfg_update {
++	struct isp_csi2_lanes_cfg_update lanes;
++	struct isp_csi2_phy_cfg_update phy;
++	struct isp_csi2_ctx_cfg_update contexts[8];
++	struct isp_csi2_timings_cfg_update timings[2];
++	struct isp_csi2_ctrl_cfg_update ctrl;
++};
++
++int isp_csi2_complexio_lanes_config(struct isp_csi2_lanes_cfg *reqcfg);
++int isp_csi2_complexio_lanes_update(bool force_update);
++int isp_csi2_complexio_lanes_get(void);
++int isp_csi2_complexio_power_autoswitch(bool enable);
++int isp_csi2_complexio_power(enum isp_csi2_power_cmds power_cmd);
++int isp_csi2_ctrl_config_frame_mode(enum isp_csi2_frame_mode frame_mode);
++int isp_csi2_ctrl_config_vp_clk_enable(bool vp_clk_enable);
++int isp_csi2_ctrl_config_vp_only_enable(bool vp_only_enable);
++int isp_csi2_ctrl_config_debug_enable(bool debug_enable);
++int isp_csi2_ctrl_config_burst_size(u8 burst_size);
++int isp_csi2_ctrl_config_ecc_enable(bool ecc_enable);
++int isp_csi2_ctrl_config_secure_mode(bool secure_mode);
++int isp_csi2_ctrl_config_if_enable(bool if_enable);
++int isp_csi2_ctrl_config_vp_out_ctrl(u8 vp_out_ctrl);
++int isp_csi2_ctrl_update(bool force_update);
++int isp_csi2_ctrl_get(void);
++int isp_csi2_ctx_config_virtual_id(u8 ctxnum, u8 virtual_id);
++int isp_csi2_ctx_config_frame_count(u8 ctxnum, u8 frame_count);
++int isp_csi2_ctx_config_format(u8 ctxnum, u32 pixformat);
++int isp_csi2_ctx_config_alpha(u8 ctxnum, u16 alpha);
++int isp_csi2_ctx_config_data_offset(u8 ctxnum, u16 data_offset);
++int isp_csi2_ctx_config_ping_addr(u8 ctxnum, u32 ping_addr);
++int isp_csi2_ctx_config_pong_addr(u8 ctxnum, u32 pong_addr);
++int isp_csi2_ctx_config_eof_enabled(u8 ctxnum, bool eof_enabled);
++int isp_csi2_ctx_config_eol_enabled(u8 ctxnum, bool eol_enabled);
++int isp_csi2_ctx_config_checksum_enabled(u8 ctxnum, bool checksum_enabled);
++int isp_csi2_ctx_config_enabled(u8 ctxnum, bool enabled);
++int isp_csi2_ctx_update(u8 ctxnum, bool force_update);
++int isp_csi2_ctx_get(u8 ctxnum);
++int isp_csi2_ctx_update_all(bool force_update);
++int isp_csi2_ctx_get_all(void);
++int isp_csi2_phy_config(struct isp_csi2_phy_cfg *desiredphyconfig);
++int isp_csi2_calc_phy_cfg0(u32 mipiclk, u32 lbound_hs_settle,
++			   u32 ubound_hs_settle);
++int isp_csi2_phy_update(bool force_update);
++int isp_csi2_phy_get(void);
++int isp_csi2_timings_config_forcerxmode(u8 io, bool force_rx_mode);
++int isp_csi2_timings_config_stopstate_16x(u8 io, bool stop_state_16x);
++int isp_csi2_timings_config_stopstate_4x(u8 io, bool stop_state_4x);
++int isp_csi2_timings_config_stopstate_cnt(u8 io, u16 stop_state_counter);
++int isp_csi2_timings_update(u8 io, bool force_update);
++int isp_csi2_timings_get(u8 io);
++int isp_csi2_timings_update_all(bool force_update);
++int isp_csi2_timings_get_all(void);
++void isp_csi2_irq_complexio1_set(int enable);
++void isp_csi2_irq_ctx_set(int enable);
++void isp_csi2_irq_status_set(int enable);
++void isp_csi2_irq_set(int enable);
++void isp_csi2_irq_all_set(int enable);
++
++void isp_csi2_isr(void);
++int isp_csi2_reset(void);
++void isp_csi2_enable(int enable);
++void isp_csi2_regdump(void);
++
++#endif	/* OMAP_ISP_CSI2_H */
++
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0008-omap3isp-Add-ISP-tables.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0008-omap3isp-Add-ISP-tables.patch
new file mode 100644
index 0000000000..db023e514d
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0008-omap3isp-Add-ISP-tables.patch
@@ -0,0 +1,4018 @@
+From 5de7cb2cac5f7d76cb025ddc8fb09c99a1007e08 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:02 +0200
+Subject: [PATCH] omap3isp: Add ISP tables
+
+* Blue Gamma gain table
+* CFA gain table
+* Green Gamma gain table
+* Luma Enhancement gain table
+* Noise filter gain table
+* Red Gamma gain table
+
+TODO:
+
+- Get rid of this kind of tables. Either generate them at runtime or
+  use a user space program to fill defaults.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ drivers/media/video/isp/bluegamma_table.h    | 1040 ++++++++++++++++++++++++++
+ drivers/media/video/isp/cfa_coef_table.h     |  603 +++++++++++++++
+ drivers/media/video/isp/greengamma_table.h   | 1040 ++++++++++++++++++++++++++
+ drivers/media/video/isp/luma_enhance_table.h |  144 ++++
+ drivers/media/video/isp/noise_filter_table.h |   79 ++
+ drivers/media/video/isp/redgamma_table.h     | 1040 ++++++++++++++++++++++++++
+ 6 files changed, 3946 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/isp/bluegamma_table.h
+ create mode 100644 drivers/media/video/isp/cfa_coef_table.h
+ create mode 100644 drivers/media/video/isp/greengamma_table.h
+ create mode 100644 drivers/media/video/isp/luma_enhance_table.h
+ create mode 100644 drivers/media/video/isp/noise_filter_table.h
+ create mode 100644 drivers/media/video/isp/redgamma_table.h
+
+diff --git a/drivers/media/video/isp/bluegamma_table.h b/drivers/media/video/isp/bluegamma_table.h
+new file mode 100644
+index 0000000..301382a
+--- /dev/null
++++ b/drivers/media/video/isp/bluegamma_table.h
+@@ -0,0 +1,1040 @@
++/*
++ * bluegamma_table.h
++ *
++ * Gamma Table values for BLUE for TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
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+diff --git a/drivers/media/video/isp/cfa_coef_table.h b/drivers/media/video/isp/cfa_coef_table.h
+new file mode 100644
+index 0000000..8cafa1f
+--- /dev/null
++++ b/drivers/media/video/isp/cfa_coef_table.h
+@@ -0,0 +1,603 @@
++/*
++ * cfa_coef_table.h
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ *
++ * Contact: Sakari Ailus <sakari.ailus@nokia.com>
++ *          Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
++ *
++ * Written by Gjorgji Rosikopulos
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++ * 02110-1301 USA
++ *
++ */
++
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+diff --git a/drivers/media/video/isp/greengamma_table.h b/drivers/media/video/isp/greengamma_table.h
+new file mode 100644
+index 0000000..0f5c5e4
+--- /dev/null
++++ b/drivers/media/video/isp/greengamma_table.h
+@@ -0,0 +1,1040 @@
++/*
++ * greengamma_table.h
++ *
++ * Gamma Table values for GREEN for TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
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+diff --git a/drivers/media/video/isp/luma_enhance_table.h b/drivers/media/video/isp/luma_enhance_table.h
+new file mode 100644
+index 0000000..99c8b05
+--- /dev/null
++++ b/drivers/media/video/isp/luma_enhance_table.h
+@@ -0,0 +1,144 @@
++/*
++ * luma_enhance_table.h
++ *
++ * Luminance Enhancement table values for TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
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+diff --git a/drivers/media/video/isp/noise_filter_table.h b/drivers/media/video/isp/noise_filter_table.h
+new file mode 100644
+index 0000000..7345f90
+--- /dev/null
++++ b/drivers/media/video/isp/noise_filter_table.h
+@@ -0,0 +1,79 @@
++/*
++ * noise_filter_table.h
++ *
++ * Noise Filter Table values for TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++16,
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+diff --git a/drivers/media/video/isp/redgamma_table.h b/drivers/media/video/isp/redgamma_table.h
+new file mode 100644
+index 0000000..ad0232a
+--- /dev/null
++++ b/drivers/media/video/isp/redgamma_table.h
+@@ -0,0 +1,1040 @@
++/*
++ * redgamma_table.h
++ *
++ * Gamma Table values for RED for TI's OMAP3 Camera ISP
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
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++226,
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++241,
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++244,
++244,
++245,
++245,
++245,
++245,
++246,
++246,
++246,
++246,
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++246,
++246,
++246,
++246,
++246,
++246,
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++246,
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++246,
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++246,
++246,
++246,
++246,
++246,
++246,
++246,
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++247,
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++247,
++247,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
++248,
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++248,
++248,
++248,
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++249,
++249,
++249,
++249,
++250,
++250,
++250,
++250,
++250,
++250,
++250,
++250,
++250,
++250,
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++250,
++250,
++250,
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++250,
++250,
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++250,
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++250,
++250,
++250,
++250,
++250,
++250,
++250,
++250,
++250,
++250,
++250,
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++250,
++250,
++250,
++250,
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++250,
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++252,
++252,
++252,
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++252,
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++252,
++252,
++252,
++252,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
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++253,
++253,
++253,
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++253,
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++253,
++253,
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++253,
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++253,
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++253,
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++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++253,
++254,
++254,
++254,
++254,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255,
++255
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0009-omap34xxcam-Add-camera-driver.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0009-omap34xxcam-Add-camera-driver.patch
new file mode 100644
index 0000000000..22074be148
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/omap3camera/0009-omap34xxcam-Add-camera-driver.patch
@@ -0,0 +1,2249 @@
+From 0edf5a50dc0164db5bc71b1a5d1aa8bb1838262c Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+Date: Tue, 10 Mar 2009 10:49:03 +0200
+Subject: [PATCH] omap34xxcam: Add camera driver
+
+This is the camera driver for the OMAP 3 camera ISP and v4l2-int-device
+sensors, lenses and (led) flashes. There are a few connections to OMAP
+3 left but after those have been broken this is hardware independent.
+Namely, the OMAP 3 ISP must offer a standard interface through
+v4l2_subdev (or v4l2-int-device) first.
+
+This driver has originated from the omap24xxcam camera driver written
+specifically for OMAP 2.
+
+TODO:
+
+- Convert to use v4l2_subdev instead of v4l2-int-device.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
+---
+ drivers/media/video/Kconfig       |    9 +
+ drivers/media/video/Makefile      |    2 +
+ drivers/media/video/omap34xxcam.c | 1966 +++++++++++++++++++++++++++++++++++++
+ drivers/media/video/omap34xxcam.h |  207 ++++
+ 4 files changed, 2184 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/omap34xxcam.c
+ create mode 100644 drivers/media/video/omap34xxcam.h
+
+diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
+index 19cf3b8..3cdb5a4 100644
+--- a/drivers/media/video/Kconfig
++++ b/drivers/media/video/Kconfig
+@@ -711,6 +711,15 @@ config VIDEO_CAFE_CCIC
+ 	  CMOS camera controller.  This is the controller found on first-
+ 	  generation OLPC systems.
+ 
++config VIDEO_OMAP3
++        tristate "OMAP 3 Camera support"
++	select VIDEOBUF_GEN
++	select VIDEOBUF_DMA_SG
++	select OMAP_IOMMU
++	depends on VIDEO_V4L2 && ARCH_OMAP34XX
++	---help---
++	  Driver for an OMAP 3 camera controller.
++
+ config SOC_CAMERA
+ 	tristate "SoC camera support"
+ 	depends on VIDEO_V4L2 && HAS_DMA
+diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
+index e654270..74a684e 100644
+--- a/drivers/media/video/Makefile
++++ b/drivers/media/video/Makefile
+@@ -108,6 +108,8 @@ obj-$(CONFIG_VIDEO_OV7670) 	+= ov7670.o
+ 
+ obj-y				+= isp/
+ 
++obj-$(CONFIG_VIDEO_OMAP3) += omap34xxcam.o
++
+ obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
+ 
+ obj-$(CONFIG_USB_DABUSB)        += dabusb.o
+diff --git a/drivers/media/video/omap34xxcam.c b/drivers/media/video/omap34xxcam.c
+new file mode 100644
+index 0000000..00fdbf2
+--- /dev/null
++++ b/drivers/media/video/omap34xxcam.c
+@@ -0,0 +1,1966 @@
++/*
++ * omap34xxcam.c
++ *
++ * Copyright (C) 2006--2009 Nokia Corporation
++ * Copyright (C) 2007--2009 Texas Instruments
++ *
++ * Contact: Sakari Ailus <sakari.ailus@nokia.com>
++ *          Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
++ *
++ * Originally based on the OMAP 2 camera driver.
++ *
++ * Written by Sakari Ailus <sakari.ailus@nokia.com>
++ *            Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
++ *            Sergio Aguirre <saaguirre@ti.com>
++ *            Mohit Jalori
++ *            Sameer Venkatraman
++ *            Leonides Martinez
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++ * 02110-1301 USA
++ *
++ */
++
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/pci.h>		/* needed for videobufs */
++#include <linux/delay.h>
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/videodev2.h>
++#include <linux/version.h>
++#include <linux/platform_device.h>
++
++#include <media/v4l2-common.h>
++#include <media/v4l2-ioctl.h>
++
++#include "omap34xxcam.h"
++#include "isp/isp.h"
++#include "isp/ispmmu.h"
++#include "isp/ispreg.h"
++#include "isp/ispccdc.h"
++#include "isp/isph3a.h"
++#include "isp/isp_af.h"
++#include "isp/isphist.h"
++#include "isp/isppreview.h"
++#include "isp/ispresizer.h"
++
++#define OMAP34XXCAM_VERSION KERNEL_VERSION(0, 0, 0)
++
++/* global variables */
++static struct omap34xxcam_device *omap34xxcam;
++
++/*
++ *
++ * Sensor handling.
++ *
++ */
++
++/**
++ * omap34xxcam_slave_power_set - set slave power state
++ * @vdev: per-video device data structure
++ * @power: new power state
++ */
++static int omap34xxcam_slave_power_set(struct omap34xxcam_videodev *vdev,
++				       enum v4l2_power power,
++				       int mask)
++{
++	int rval = 0, i = 0;
++
++	BUG_ON(!mutex_is_locked(&vdev->mutex));
++
++#ifdef OMAP34XXCAM_POWEROFF_DELAY
++	vdev->power_state_wish = -1;
++#endif
++
++	for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++) {
++		if (vdev->slave[i] == v4l2_int_device_dummy())
++			continue;
++
++		if (!(mask & (1 << i))
++		    || power == vdev->power_state[i])
++			continue;
++
++		rval = vidioc_int_s_power(vdev->slave[i], power);
++
++		if (rval && power != V4L2_POWER_OFF) {
++			power = V4L2_POWER_OFF;
++			goto out;
++		}
++
++		vdev->power_state[i] = power;
++	}
++
++	return 0;
++
++out:
++	for (i--; i >= 0; i--) {
++		if (vdev->slave[i] == v4l2_int_device_dummy())
++			continue;
++
++		if (!(mask & (1 << i)))
++			continue;
++
++		vidioc_int_s_power(vdev->slave[i], power);
++		vdev->power_state[i] = power;
++	}
++
++	return rval;
++}
++
++#ifdef OMAP34XXCAM_POWEROFF_DELAY
++static void omap34xxcam_slave_power_work(struct work_struct *work)
++{
++	struct omap34xxcam_videodev *vdev =
++		container_of(work, struct omap34xxcam_videodev, poweroff_work);
++
++	mutex_lock(&vdev->mutex);
++
++	if (vdev->power_state_wish != -1)
++		omap34xxcam_slave_power_set(vdev, vdev->power_state_wish,
++					    vdev->power_state_mask);
++
++	mutex_unlock(&vdev->mutex);
++}
++
++static void omap34xxcam_slave_power_timer(unsigned long ptr)
++{
++	struct omap34xxcam_videodev *vdev = (void *)ptr;
++
++	schedule_work(&vdev->poweroff_work);
++}
++
++/**
++ * omap34xxcam_slave_power_suggest - delayed power state change
++ *
++ * @vdev: per-video device data structure
++ * @power: new power state
++ */
++static void omap34xxcam_slave_power_suggest(struct omap34xxcam_videodev *vdev,
++					    enum v4l2_power power,
++					    int mask)
++{
++	BUG_ON(!mutex_is_locked(&vdev->mutex));
++
++	del_timer(&vdev->poweroff_timer);
++
++	vdev->power_state_wish = power;
++	vdev->power_state_mask = mask;
++
++	mod_timer(&vdev->poweroff_timer, jiffies + OMAP34XXCAM_POWEROFF_DELAY);
++}
++#else /* OMAP34XXCAM_POWEROFF_DELAY */
++#define omap34xxcam_slave_power_suggest(a, b, c) do {} while (0)
++#endif /* OMAP34XXCAM_POWEROFF_DELAY */
++
++/**
++ * omap34xxcam_update_vbq - Updates VBQ with completed input buffer
++ * @vb: ptr. to standard V4L2 video buffer structure
++ *
++ * Updates video buffer queue with completed buffer passed as
++ * input parameter.  Also updates ISP H3A timestamp and field count
++ * statistics.
++ */
++void omap34xxcam_vbq_complete(struct videobuf_buffer *vb, void *priv)
++{
++	struct omap34xxcam_fh *fh = priv;
++
++	do_gettimeofday(&vb->ts);
++	vb->field_count = atomic_add_return(2, &fh->field_count);
++
++	wake_up(&vb->done);
++}
++
++/**
++ * omap34xxcam_vbq_setup - Calcs size and num of buffs allowed in queue
++ * @vbq: ptr. to standard V4L2 video buffer queue structure
++ * @cnt: ptr to location to hold the count of buffers to be in the queue
++ * @size: ptr to location to hold the size of a frame
++ *
++ * Calculates the number of buffers of current image size that can be
++ * supported by the available capture memory.
++ */
++static int omap34xxcam_vbq_setup(struct videobuf_queue *vbq, unsigned int *cnt,
++				 unsigned int *size)
++{
++	struct omap34xxcam_fh *fh = vbq->priv_data;
++	struct omap34xxcam_videodev *vdev = fh->vdev;
++
++	if (*cnt <= 0)
++		*cnt = VIDEO_MAX_FRAME;	/* supply a default number of buffers */
++
++	if (*cnt > VIDEO_MAX_FRAME)
++		*cnt = VIDEO_MAX_FRAME;
++
++	*size = vdev->pix.sizeimage;
++
++	while (*size * *cnt > fh->vdev->vdev_sensor_config.capture_mem)
++		(*cnt)--;
++
++	return isp_vbq_setup(vbq, cnt, size);
++}
++
++/**
++ * omap34xxcam_vbq_release - Free resources for input VBQ and VB
++ * @vbq: ptr. to standard V4L2 video buffer queue structure
++ * @vb: ptr to standard V4L2 video buffer structure
++ *
++ * Unmap and free all memory associated with input VBQ and VB, also
++ * unmap the address in ISP MMU.  Reset the VB state.
++ */
++static void omap34xxcam_vbq_release(struct videobuf_queue *vbq,
++				    struct videobuf_buffer *vb)
++{
++	if (!vbq->streaming) {
++		isp_vbq_release(vbq, vb);
++		videobuf_dma_unmap(vbq, videobuf_to_dma(vb));
++		videobuf_dma_free(videobuf_to_dma(vb));
++		vb->state = VIDEOBUF_NEEDS_INIT;
++	}
++	return;
++}
++
++/**
++ * omap34xxcam_vbq_prepare - V4L2 video ops buf_prepare handler
++ * @vbq: ptr. to standard V4L2 video buffer queue structure
++ * @vb: ptr to standard V4L2 video buffer structure
++ * @field: standard V4L2 field enum
++ *
++ * Verifies there is sufficient locked memory for the requested
++ * buffer, or if there is not, allocates, locks and initializes
++ * it.
++ */
++static int omap34xxcam_vbq_prepare(struct videobuf_queue *vbq,
++				   struct videobuf_buffer *vb,
++				   enum v4l2_field field)
++{
++	struct omap34xxcam_fh *fh = vbq->priv_data;
++	struct omap34xxcam_videodev *vdev = fh->vdev;
++	int err = 0;
++
++	/*
++	 * Accessing pix here is okay since it's constant while
++	 * streaming is on (and we only get called then).
++	 */
++	if (vb->baddr) {
++		/* This is a userspace buffer. */
++		if (vdev->pix.sizeimage > vb->bsize)
++			/* The buffer isn't big enough. */
++			return -EINVAL;
++	} else {
++		if (vb->state != VIDEOBUF_NEEDS_INIT
++		    && vdev->pix.sizeimage > vb->bsize)
++			/*
++			 * We have a kernel bounce buffer that has
++			 * already been allocated.
++			 */
++			omap34xxcam_vbq_release(vbq, vb);
++	}
++
++	vb->size = vdev->pix.bytesperline * vdev->pix.height;
++	vb->width = vdev->pix.width;
++	vb->height = vdev->pix.height;
++	vb->field = field;
++
++	if (vb->state == VIDEOBUF_NEEDS_INIT) {
++		err = videobuf_iolock(vbq, vb, NULL);
++		if (!err) {
++			/* isp_addr will be stored locally inside isp code */
++			err = isp_vbq_prepare(vbq, vb, field);
++		}
++	}
++
++	if (!err)
++		vb->state = VIDEOBUF_PREPARED;
++	else
++		omap34xxcam_vbq_release(vbq, vb);
++
++	return err;
++}
++
++/**
++ * omap34xxcam_vbq_queue - V4L2 video ops buf_queue handler
++ * @vbq: ptr. to standard V4L2 video buffer queue structure
++ * @vb: ptr to standard V4L2 video buffer structure
++ *
++ * Maps the video buffer to sgdma and through the isp, sets
++ * the isp buffer done callback and sets the video buffer state
++ * to active.
++ */
++static void omap34xxcam_vbq_queue(struct videobuf_queue *vbq,
++				  struct videobuf_buffer *vb)
++{
++	struct omap34xxcam_fh *fh = vbq->priv_data;
++
++	vb->state = VIDEOBUF_ACTIVE;
++
++	isp_buf_queue(vb, omap34xxcam_vbq_complete, (void *)fh);
++}
++
++static struct videobuf_queue_ops omap34xxcam_vbq_ops = {
++	.buf_setup = omap34xxcam_vbq_setup,
++	.buf_prepare = omap34xxcam_vbq_prepare,
++	.buf_queue = omap34xxcam_vbq_queue,
++	.buf_release = omap34xxcam_vbq_release,
++};
++
++/*
++ *
++ * IOCTL interface.
++ *
++ */
++
++/**
++ * vidioc_querycap - V4L2 query capabilities IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @cap: ptr to standard V4L2 capability structure
++ *
++ * Fill in the V4L2 capabliity structure for the camera device
++ */
++static int vidioc_querycap(struct file *file, void *fh,
++			   struct v4l2_capability *cap)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++
++	strlcpy(cap->driver, CAM_SHORT_NAME, sizeof(cap->driver));
++	strlcpy(cap->card, vdev->vfd->name, sizeof(cap->card));
++	cap->version = OMAP34XXCAM_VERSION;
++	if (vdev->vdev_sensor != v4l2_int_device_dummy())
++		cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++
++	return 0;
++}
++
++/**
++ * vidioc_enum_fmt_vid_cap - V4L2 enumerate format capabilities IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @f: ptr to standard V4L2 format description structure
++ *
++ * Fills in enumerate format capabilities information for sensor (if SOC
++ * sensor attached) or ISP (if raw sensor attached).
++ */
++static int vidioc_enum_fmt_vid_cap(struct file *file, void *fh,
++				   struct v4l2_fmtdesc *f)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int rval;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	if (vdev->vdev_sensor_config.sensor_isp)
++		rval = vidioc_int_enum_fmt_cap(vdev->vdev_sensor, f);
++	else
++		rval = isp_enum_fmt_cap(f);
++
++	return rval;
++}
++
++/**
++ * vidioc_g_fmt_vid_cap - V4L2 get format capabilities IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @f: ptr to standard V4L2 format structure
++ *
++ * Fills in format capabilities for sensor (if SOC sensor attached) or ISP
++ * (if raw sensor attached).
++ */
++static int vidioc_g_fmt_vid_cap(struct file *file, void *fh,
++				struct v4l2_format *f)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++	f->fmt.pix = vdev->pix;
++	mutex_unlock(&vdev->mutex);
++
++	return 0;
++}
++
++static int try_pix_parm(struct omap34xxcam_videodev *vdev,
++			struct v4l2_pix_format *best_pix_in,
++			struct v4l2_pix_format *wanted_pix_out,
++			struct v4l2_fract *best_ival)
++{
++	int fps;
++	int fmtd_index;
++	int rval;
++	struct v4l2_pix_format best_pix_out;
++
++	if (best_ival->numerator == 0
++	    || best_ival->denominator == 0)
++		*best_ival = vdev->vdev_sensor_config.ival_default;
++
++	fps = best_ival->denominator / best_ival->numerator;
++
++	best_ival->denominator = 0;
++	best_pix_out.height = INT_MAX >> 1;
++	best_pix_out.width = best_pix_out.height;
++
++	for (fmtd_index = 0; ; fmtd_index++) {
++		int size_index;
++		struct v4l2_fmtdesc fmtd;
++
++		fmtd.index = fmtd_index;
++		fmtd.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++		rval = vidioc_int_enum_fmt_cap(vdev->vdev_sensor, &fmtd);
++		if (rval)
++			break;
++		dev_info(&vdev->vfd->dev, "trying fmt %8.8x (%d)\n",
++			 fmtd.pixelformat, fmtd_index);
++		/*
++		 * Get supported resolutions.
++		 */
++		for (size_index = 0; ; size_index++) {
++			struct v4l2_frmsizeenum frms;
++			struct v4l2_pix_format pix_tmp_in, pix_tmp_out;
++			int ival_index;
++
++			frms.index = size_index;
++			frms.pixel_format = fmtd.pixelformat;
++
++			rval = vidioc_int_enum_framesizes(vdev->vdev_sensor,
++							  &frms);
++			if (rval)
++				break;
++
++			pix_tmp_in.pixelformat = frms.pixel_format;
++			pix_tmp_in.width = frms.discrete.width;
++			pix_tmp_in.height = frms.discrete.height;
++			pix_tmp_out = *wanted_pix_out;
++			/* Don't do upscaling. */
++			if (pix_tmp_out.width > pix_tmp_in.width)
++				pix_tmp_out.width = pix_tmp_in.width;
++			if (pix_tmp_out.height > pix_tmp_in.height)
++				pix_tmp_out.height = pix_tmp_in.height;
++			rval = isp_try_fmt_cap(&pix_tmp_in, &pix_tmp_out);
++			if (rval)
++				return rval;
++
++			dev_info(&vdev->vfd->dev, "this w %d\th %d\tfmt %8.8x\t"
++				 "-> w %d\th %d\t fmt %8.8x"
++				 "\twanted w %d\th %d\t fmt %8.8x\n",
++				 pix_tmp_in.width, pix_tmp_in.height,
++				 pix_tmp_in.pixelformat,
++				 pix_tmp_out.width, pix_tmp_out.height,
++				 pix_tmp_out.pixelformat,
++				 wanted_pix_out->width, wanted_pix_out->height,
++				 wanted_pix_out->pixelformat);
++
++#define IS_SMALLER_OR_EQUAL(pix1, pix2)				\
++			((pix1)->width + (pix1)->height		\
++			 < (pix2)->width + (pix2)->height)
++#define SIZE_DIFF(pix1, pix2)						\
++			(abs((pix1)->width - (pix2)->width)		\
++			 + abs((pix1)->height - (pix2)->height))
++
++			/*
++			 * Don't use modes that are farther from wanted size
++			 * that what we already got.
++			 */
++			if (SIZE_DIFF(&pix_tmp_out, wanted_pix_out)
++			    > SIZE_DIFF(&best_pix_out, wanted_pix_out)) {
++				dev_info(&vdev->vfd->dev, "size diff bigger: "
++					 "w %d\th %d\tw %d\th %d\n",
++					 pix_tmp_out.width, pix_tmp_out.height,
++					 best_pix_out.width,
++					 best_pix_out.height);
++				continue;
++			}
++
++			/*
++			 * There's an input mode that can provide output
++			 * closer to wanted.
++			 */
++			if (SIZE_DIFF(&pix_tmp_out, wanted_pix_out)
++			    < SIZE_DIFF(&best_pix_out, wanted_pix_out)) {
++				/* Force renegotation of fps etc. */
++				best_ival->denominator = 0;
++				dev_info(&vdev->vfd->dev, "renegotiate: "
++					 "w %d\th %d\tw %d\th %d\n",
++					 pix_tmp_out.width, pix_tmp_out.height,
++					 best_pix_out.width,
++					 best_pix_out.height);
++			}
++
++			for (ival_index = 0; ; ival_index++) {
++				struct v4l2_frmivalenum frmi;
++
++				frmi.index = ival_index;
++				frmi.pixel_format = frms.pixel_format;
++				frmi.width = frms.discrete.width;
++				frmi.height = frms.discrete.height;
++				/* FIXME: try to fix standard... */
++				frmi.reserved[0] = 0xdeafbeef;
++
++				rval = vidioc_int_enum_frameintervals(
++					vdev->vdev_sensor, &frmi);
++				if (rval)
++					break;
++
++				dev_info(&vdev->vfd->dev, "fps %d\n",
++					 frmi.discrete.denominator
++					 / frmi.discrete.numerator);
++
++				if (best_ival->denominator == 0)
++					goto do_it_now;
++
++				/*
++				 * We aim to use maximum resolution
++				 * from the sensor, provided that the
++				 * fps is at least as close as on the
++				 * current mode.
++				 */
++#define FPS_ABS_DIFF(fps, ival) abs(fps - (ival).denominator / (ival).numerator)
++
++				/* Select mode with closest fps. */
++				if (FPS_ABS_DIFF(fps, frmi.discrete)
++				    < FPS_ABS_DIFF(fps, *best_ival)) {
++					dev_info(&vdev->vfd->dev, "closer fps: "
++						 "fps %d\t fps %d\n",
++						 FPS_ABS_DIFF(fps,
++							      frmi.discrete),
++						 FPS_ABS_DIFF(fps, *best_ival));
++					goto do_it_now;
++				}
++
++				/*
++				 * Select bigger resolution if it's available
++				 * at same fps.
++				 */
++				if (frmi.width + frmi.height
++				    > best_pix_in->width + best_pix_in->height
++				    && FPS_ABS_DIFF(fps, frmi.discrete)
++				    <= FPS_ABS_DIFF(fps, *best_ival)) {
++					dev_info(&vdev->vfd->dev, "bigger res, "
++						 "same fps: "
++						 "w %d\th %d\tw %d\th %d\n",
++						 frmi.width, frmi.height,
++						 best_pix_in->width,
++						 best_pix_in->height);
++					goto do_it_now;
++				}
++
++				dev_info(&vdev->vfd->dev, "falling through\n");
++
++				continue;
++
++do_it_now:
++				*best_ival = frmi.discrete;
++				best_pix_out = pix_tmp_out;
++				best_pix_in->width = frmi.width;
++				best_pix_in->height = frmi.height;
++				best_pix_in->pixelformat = frmi.pixel_format;
++
++				dev_info(&vdev->vfd->dev,
++					 "best_pix_in: w %d\th %d\tfmt %8.8x"
++					 "\tival %d/%d\n",
++					 best_pix_in->width,
++					 best_pix_in->height,
++					 best_pix_in->pixelformat,
++					 best_ival->numerator,
++					 best_ival->denominator);
++			}
++		}
++	}
++
++	if (best_ival->denominator == 0)
++		return -EINVAL;
++
++	*wanted_pix_out = best_pix_out;
++
++	dev_info(&vdev->vfd->dev, "w %d, h %d, fmt %8.8x -> w %d, h %d\n",
++		 best_pix_in->width, best_pix_in->height,
++		 best_pix_in->pixelformat,
++		 best_pix_out.width, best_pix_out.height);
++
++	return isp_try_fmt_cap(best_pix_in, wanted_pix_out);
++}
++
++static int s_pix_parm(struct omap34xxcam_videodev *vdev,
++		      struct v4l2_pix_format *best_pix,
++		      struct v4l2_pix_format *pix,
++		      struct v4l2_fract *best_ival)
++{
++	struct v4l2_streamparm a;
++	struct v4l2_format fmt;
++	int rval;
++
++	rval = try_pix_parm(vdev, best_pix, pix, best_ival);
++	if (rval)
++		return rval;
++
++	rval = isp_s_fmt_cap(best_pix, pix);
++	if (rval)
++		return rval;
++
++	fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	fmt.fmt.pix = *best_pix;
++	rval = vidioc_int_s_fmt_cap(vdev->vdev_sensor, &fmt);
++	if (rval)
++		return rval;
++
++	a.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	a.parm.capture.timeperframe = *best_ival;
++	rval = vidioc_int_s_parm(vdev->vdev_sensor, &a);
++
++	return rval;
++}
++
++/**
++ * vidioc_s_fmt_vid_cap - V4L2 set format capabilities IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @f: ptr to standard V4L2 format structure
++ *
++ * Attempts to set input format with the sensor driver (first) and then the
++ * ISP.  Returns the return code from vidioc_g_fmt_vid_cap().
++ */
++static int vidioc_s_fmt_vid_cap(struct file *file, void *fh,
++				struct v4l2_format *f)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	struct v4l2_pix_format pix_tmp;
++	struct v4l2_fract timeperframe;
++	int rval;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++	if (vdev->streaming) {
++		rval = -EBUSY;
++		goto out;
++	}
++
++	vdev->want_pix = f->fmt.pix;
++
++	timeperframe = vdev->want_timeperframe;
++
++	rval = s_pix_parm(vdev, &pix_tmp, &f->fmt.pix, &timeperframe);
++	if (!rval)
++		vdev->pix = f->fmt.pix;
++
++out:
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_try_fmt_vid_cap - V4L2 try format capabilities IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @f: ptr to standard V4L2 format structure
++ *
++ * Checks if the given format is supported by the sensor driver and
++ * by the ISP.
++ */
++static int vidioc_try_fmt_vid_cap(struct file *file, void *fh,
++				  struct v4l2_format *f)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	struct v4l2_pix_format pix_tmp;
++	struct v4l2_fract timeperframe;
++	int rval;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++
++	timeperframe = vdev->want_timeperframe;
++
++	rval = try_pix_parm(vdev, &pix_tmp, &f->fmt.pix, &timeperframe);
++
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_reqbufs - V4L2 request buffers IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @b: ptr to standard V4L2 request buffers structure
++ *
++ * Attempts to get a buffer from the buffer queue associated with the
++ * fh through the video buffer library API.
++ */
++static int vidioc_reqbufs(struct file *file, void *fh,
++			  struct v4l2_requestbuffers *b)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int rval;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++	if (vdev->streaming) {
++		mutex_unlock(&vdev->mutex);
++		return -EBUSY;
++	}
++
++	rval = videobuf_reqbufs(&ofh->vbq, b);
++
++	mutex_unlock(&vdev->mutex);
++
++	/*
++	 * Either videobuf_reqbufs failed or the buffers are not
++	 * memory-mapped (which would need special attention).
++	 */
++	if (rval < 0 || b->memory != V4L2_MEMORY_MMAP)
++		goto out;
++
++out:
++	return rval;
++}
++
++/**
++ * vidioc_querybuf - V4L2 query buffer IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @b: ptr to standard V4L2 buffer structure
++ *
++ * Attempts to fill in the v4l2_buffer structure for the buffer queue
++ * associated with the fh through the video buffer library API.
++ */
++static int vidioc_querybuf(struct file *file, void *fh, struct v4l2_buffer *b)
++{
++	struct omap34xxcam_fh *ofh = fh;
++
++	return videobuf_querybuf(&ofh->vbq, b);
++}
++
++/**
++ * vidioc_qbuf - V4L2 queue buffer IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @b: ptr to standard V4L2 buffer structure
++ *
++ * Attempts to queue the v4l2_buffer on the buffer queue
++ * associated with the fh through the video buffer library API.
++ */
++static int vidioc_qbuf(struct file *file, void *fh, struct v4l2_buffer *b)
++{
++	struct omap34xxcam_fh *ofh = fh;
++
++	return videobuf_qbuf(&ofh->vbq, b);
++}
++
++/**
++ * vidioc_dqbuf - V4L2 dequeue buffer IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @b: ptr to standard V4L2 buffer structure
++ *
++ * Attempts to dequeue the v4l2_buffer from the buffer queue
++ * associated with the fh through the video buffer library API.  If the
++ * buffer is a user space buffer, then this function will also requeue it,
++ * as user does not expect to do this.
++ */
++static int vidioc_dqbuf(struct file *file, void *fh, struct v4l2_buffer *b)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	int rval;
++
++videobuf_dqbuf_again:
++	rval = videobuf_dqbuf(&ofh->vbq, b, file->f_flags & O_NONBLOCK);
++
++	/*
++	 * This is a hack. We don't want to show -EIO to the user
++	 * space. Requeue the buffer and try again if we're not doing
++	 * this in non-blocking mode.
++	 */
++	if (rval == -EIO) {
++		videobuf_qbuf(&ofh->vbq, b);
++		if (!(file->f_flags & O_NONBLOCK))
++			goto videobuf_dqbuf_again;
++		/*
++		 * We don't have a videobuf_buffer now --- maybe next
++		 * time...
++		 */
++		rval = -EAGAIN;
++	}
++
++	return rval;
++}
++
++/**
++ * vidioc_streamon - V4L2 streamon IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @i: V4L2 buffer type
++ *
++ * Attempts to start streaming by enabling the sensor interface and turning
++ * on video buffer streaming through the video buffer library API.  Upon
++ * success the function returns 0, otherwise an error code is returned.
++ */
++static int vidioc_streamon(struct file *file, void *fh, enum v4l2_buf_type i)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int rval;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++	if (vdev->streaming) {
++		rval = -EBUSY;
++		goto out;
++	}
++
++	rval = omap34xxcam_slave_power_set(vdev, V4L2_POWER_ON,
++					   OMAP34XXCAM_SLAVE_POWER_SENSOR_LENS);
++	if (rval) {
++		dev_dbg(&vdev->vfd->dev,
++			"omap34xxcam_slave_power_set failed\n");
++		goto out;
++	}
++
++	rval = videobuf_streamon(&ofh->vbq);
++	if (rval)
++		omap34xxcam_slave_power_set(
++			vdev, V4L2_POWER_OFF,
++			OMAP34XXCAM_SLAVE_POWER_SENSOR_LENS);
++	else
++		vdev->streaming = file;
++
++out:
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_streamoff - V4L2 streamoff IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @i: V4L2 buffer type
++ *
++ * Attempts to stop streaming by flushing all scheduled work, waiting on
++ * any queued buffers to complete and then stopping the ISP and turning
++ * off video buffer streaming through the video buffer library API.  Upon
++ * success the function returns 0, otherwise an error code is returned.
++ */
++static int vidioc_streamoff(struct file *file, void *fh, enum v4l2_buf_type i)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	struct videobuf_queue *q = &ofh->vbq;
++	int rval;
++
++	mutex_lock(&vdev->mutex);
++
++	if (vdev->streaming == file)
++		isp_stop();
++
++	rval = videobuf_streamoff(q);
++	if (!rval) {
++		vdev->streaming = NULL;
++
++		omap34xxcam_slave_power_set(vdev, V4L2_POWER_STANDBY,
++					    OMAP34XXCAM_SLAVE_POWER_SENSOR);
++		omap34xxcam_slave_power_suggest(vdev, V4L2_POWER_STANDBY,
++						OMAP34XXCAM_SLAVE_POWER_LENS);
++	}
++
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_enum_input - V4L2 enumerate input IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @inp: V4L2 input type information structure
++ *
++ * Fills in v4l2_input structure.  Returns 0.
++ */
++static int vidioc_enum_input(struct file *file, void *fh,
++			     struct v4l2_input *inp)
++{
++	if (inp->index > 0)
++		return -EINVAL;
++
++	strlcpy(inp->name, "camera", sizeof(inp->name));
++	inp->type = V4L2_INPUT_TYPE_CAMERA;
++
++	return 0;
++}
++
++/**
++ * vidioc_g_input - V4L2 get input IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @i: address to hold index of input supported
++ *
++ * Sets index to 0.
++ */
++static int vidioc_g_input(struct file *file, void *fh, unsigned int *i)
++{
++	*i = 0;
++
++	return 0;
++}
++
++/**
++ * vidioc_s_input - V4L2 set input IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @i: index of input selected
++ *
++ * 0 is only index supported.
++ */
++static int vidioc_s_input(struct file *file, void *fh, unsigned int i)
++{
++	if (i > 0)
++		return -EINVAL;
++
++	return 0;
++}
++
++/**
++ * vidioc_queryctrl - V4L2 query control IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @a: standard V4L2 query control ioctl structure
++ *
++ * If the requested control is supported, returns the control information
++ * in the v4l2_queryctrl structure.  Otherwise, returns -EINVAL if the
++ * control is not supported.  If the sensor being used is a "smart sensor",
++ * this request is passed to the sensor driver, otherwise the ISP is
++ * queried and if it does not support the requested control, the request
++ * is forwarded to the "raw" sensor driver to see if it supports it.
++ */
++static int vidioc_queryctrl(struct file *file, void *fh,
++			    struct v4l2_queryctrl *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	struct v4l2_queryctrl a_tmp;
++	int best_slave = -1;
++	u32 best_ctrl = (u32)-1;
++	int i;
++
++	if (vdev->vdev_sensor_config.sensor_isp)
++		return vidioc_int_queryctrl(vdev->vdev_sensor, a);
++
++	/* No next flags: try slaves directly. */
++	if (!(a->id & V4L2_CTRL_FLAG_NEXT_CTRL)) {
++		for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++) {
++			if (!vidioc_int_queryctrl(vdev->slave[i], a))
++				return 0;
++		}
++		return isp_queryctrl(a);
++	}
++
++	/* Find slave with smallest next control id. */
++	for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++) {
++		a_tmp = *a;
++
++		if (vidioc_int_queryctrl(vdev->slave[i], &a_tmp))
++			continue;
++
++		if (a_tmp.id < best_ctrl) {
++			best_slave = i;
++			best_ctrl = a_tmp.id;
++		}
++	}
++
++	a_tmp = *a;
++	if (!isp_queryctrl(&a_tmp)) {
++		if (a_tmp.id < best_ctrl) {
++			*a = a_tmp;
++
++			return 0;
++		}
++	}
++
++	if (best_slave == -1)
++		return -EINVAL;
++
++	a->id = best_ctrl;
++	return vidioc_int_queryctrl(vdev->slave[best_slave], a);
++}
++
++/**
++ * vidioc_querymenu - V4L2 query menu IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @a: standard V4L2 query menu ioctl structure
++ *
++ * If the requested control is supported, returns the menu information
++ * in the v4l2_querymenu structure.  Otherwise, returns -EINVAL if the
++ * control is not supported or is not a menu.  If the sensor being used
++ * is a "smart sensor", this request is passed to the sensor driver,
++ * otherwise the ISP is queried and if it does not support the requested
++ * menu control, the request is forwarded to the "raw" sensor driver to
++ * see if it supports it.
++ */
++static int vidioc_querymenu(struct file *file, void *fh,
++			    struct v4l2_querymenu *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int i;
++
++	if (vdev->vdev_sensor_config.sensor_isp)
++		return vidioc_int_querymenu(vdev->vdev_sensor, a);
++
++	/* Try slaves directly. */
++	for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++) {
++		if (!vidioc_int_querymenu(vdev->slave[i], a))
++			return 0;
++	}
++	return isp_querymenu(a);
++}
++
++static int vidioc_g_ext_ctrls(struct file *file, void *fh,
++			      struct v4l2_ext_controls *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int i, ctrl_idx, rval = 0;
++
++	mutex_lock(&vdev->mutex);
++
++	for (ctrl_idx = 0; ctrl_idx < a->count; ctrl_idx++) {
++		struct v4l2_control ctrl;
++
++		ctrl.id = a->controls[ctrl_idx].id;
++
++		if (vdev->vdev_sensor_config.sensor_isp) {
++			rval = vidioc_int_g_ctrl(vdev->vdev_sensor, &ctrl);
++		} else {
++			for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++) {
++				rval = vidioc_int_g_ctrl(vdev->slave[i], &ctrl);
++				if (!rval)
++					break;
++			}
++		}
++
++		if (rval)
++			rval = isp_g_ctrl(&ctrl);
++
++		if (rval) {
++			a->error_idx = ctrl_idx;
++			break;
++		}
++
++		a->controls[ctrl_idx].value = ctrl.value;
++	}
++
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++static int vidioc_s_ext_ctrls(struct file *file, void *fh,
++			      struct v4l2_ext_controls *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int i, ctrl_idx, rval = 0;
++
++	mutex_lock(&vdev->mutex);
++
++	for (ctrl_idx = 0; ctrl_idx < a->count; ctrl_idx++) {
++		struct v4l2_control ctrl;
++
++		ctrl.id = a->controls[ctrl_idx].id;
++		ctrl.value = a->controls[ctrl_idx].value;
++
++		if (vdev->vdev_sensor_config.sensor_isp) {
++			rval = vidioc_int_s_ctrl(vdev->vdev_sensor, &ctrl);
++		} else {
++			for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++) {
++				rval = vidioc_int_s_ctrl(vdev->slave[i], &ctrl);
++				if (!rval)
++					break;
++			}
++		}
++
++		if (rval)
++			rval = isp_s_ctrl(&ctrl);
++
++		if (rval) {
++			a->error_idx = ctrl_idx;
++			break;
++		}
++
++		a->controls[ctrl_idx].value = ctrl.value;
++	}
++
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_g_parm - V4L2 get parameters IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @a: standard V4L2 stream parameters structure
++ *
++ * If request is for video capture buffer type, handles request by
++ * forwarding to sensor driver.
++ */
++static int vidioc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int rval;
++
++	if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++	rval = vidioc_int_g_parm(vdev->vdev_sensor, a);
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_s_parm - V4L2 set parameters IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @a: standard V4L2 stream parameters structure
++ *
++ * If request is for video capture buffer type, handles request by
++ * first getting current stream parameters from sensor, then forwarding
++ * request to set new parameters to sensor driver.  It then attempts to
++ * enable the sensor interface with the new parameters.  If this fails, it
++ * reverts back to the previous parameters.
++ */
++static int vidioc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	struct v4l2_pix_format pix_tmp_sensor, pix_tmp;
++	int rval;
++
++	if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++		return -EINVAL;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++	if (vdev->streaming) {
++		rval = -EBUSY;
++		goto out;
++	}
++
++	vdev->want_timeperframe = a->parm.capture.timeperframe;
++
++	pix_tmp = vdev->want_pix;
++
++	rval = s_pix_parm(vdev, &pix_tmp_sensor, &pix_tmp,
++			  &a->parm.capture.timeperframe);
++
++out:
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_cropcap - V4L2 crop capture IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @a: standard V4L2 crop capture structure
++ *
++ * If using a "smart" sensor, just forwards request to the sensor driver,
++ * otherwise fills in the v4l2_cropcap values locally.
++ */
++static int vidioc_cropcap(struct file *file, void *fh, struct v4l2_cropcap *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	struct v4l2_cropcap *cropcap = a;
++	int rval;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++
++	rval = vidioc_int_cropcap(vdev->vdev_sensor, a);
++
++	if (rval && !vdev->vdev_sensor_config.sensor_isp) {
++		struct v4l2_format f;
++
++		/* cropcap failed, try to do this via g_fmt_cap */
++		rval = vidioc_int_g_fmt_cap(vdev->vdev_sensor, &f);
++		if (!rval) {
++			cropcap->bounds.top = 0;
++			cropcap->bounds.left = 0;
++			cropcap->bounds.width = f.fmt.pix.width;
++			cropcap->bounds.height = f.fmt.pix.height;
++			cropcap->defrect = cropcap->bounds;
++			cropcap->pixelaspect.numerator = 1;
++			cropcap->pixelaspect.denominator = 1;
++		}
++	}
++
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_g_crop - V4L2 get capture crop IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @a: standard V4L2 crop structure
++ *
++ * If using a "smart" sensor, just forwards request to the sensor driver,
++ * otherwise calls the isp functions to fill in current crop values.
++ */
++static int vidioc_g_crop(struct file *file, void *fh, struct v4l2_crop *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int rval = 0;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++
++	if (vdev->vdev_sensor_config.sensor_isp)
++		rval = vidioc_int_g_crop(vdev->vdev_sensor, a);
++	else
++		rval = isp_g_crop(a);
++
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++/**
++ * vidioc_s_crop - V4L2 set capture crop IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @a: standard V4L2 crop structure
++ *
++ * If using a "smart" sensor, just forwards request to the sensor driver,
++ * otherwise calls the isp functions to set the current crop values.
++ */
++static int vidioc_s_crop(struct file *file, void *fh, struct v4l2_crop *a)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int rval = 0;
++
++	if (vdev->vdev_sensor == v4l2_int_device_dummy())
++		return -EINVAL;
++
++	mutex_lock(&vdev->mutex);
++
++	if (vdev->vdev_sensor_config.sensor_isp)
++		rval = vidioc_int_s_crop(vdev->vdev_sensor, a);
++	else
++		rval = isp_s_crop(a, &vdev->pix);
++
++	mutex_unlock(&vdev->mutex);
++
++	return rval;
++}
++
++static int vidioc_enum_framesizes(struct file *file, void *fh,
++				  struct v4l2_frmsizeenum *frms)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	u32 pixel_format;
++	int rval;
++
++	mutex_lock(&vdev->mutex);
++
++	if (vdev->vdev_sensor_config.sensor_isp) {
++		rval = vidioc_int_enum_framesizes(vdev->vdev_sensor, frms);
++	} else {
++		pixel_format = frms->pixel_format;
++		frms->pixel_format = -1;	/* ISP does format conversion */
++		rval = vidioc_int_enum_framesizes(vdev->vdev_sensor, frms);
++		frms->pixel_format = pixel_format;
++	}
++
++	mutex_unlock(&vdev->mutex);
++	return rval;
++}
++
++static int vidioc_enum_frameintervals(struct file *file, void *fh,
++				      struct v4l2_frmivalenum *frmi)
++{
++	struct omap34xxcam_fh *ofh = fh;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	u32 pixel_format;
++	int rval;
++
++	mutex_lock(&vdev->mutex);
++
++	if (vdev->vdev_sensor_config.sensor_isp) {
++		rval = vidioc_int_enum_frameintervals(vdev->vdev_sensor, frmi);
++	} else {
++		pixel_format = frmi->pixel_format;
++		frmi->pixel_format = -1;	/* ISP does format conversion */
++		rval = vidioc_int_enum_frameintervals(vdev->vdev_sensor, frmi);
++		frmi->pixel_format = pixel_format;
++	}
++
++	mutex_unlock(&vdev->mutex);
++	return rval;
++}
++
++/**
++ * vidioc_default - private IOCTL handler
++ * @file: ptr. to system file structure
++ * @fh: ptr to hold address of omap34xxcam_fh struct (per-filehandle data)
++ * @cmd: ioctl cmd value
++ * @arg: ioctl arg value
++ *
++ * If the sensor being used is a "smart sensor", this request is returned to
++ * caller with -EINVAL err code.  Otherwise if the control id is the private
++ * VIDIOC_PRIVATE_ISP_AEWB_REQ to update the analog gain or exposure,
++ * then this request is forwared directly to the sensor to incorporate the
++ * feedback. The request is then passed on to the ISP private IOCTL handler,
++ * isp_handle_private()
++ */
++static long vidioc_default(struct file *file, void *fh, int cmd, void *arg)
++{
++	struct omap34xxcam_fh *ofh = file->private_data;
++	struct omap34xxcam_videodev *vdev = ofh->vdev;
++	int rval;
++
++	if (vdev->vdev_sensor_config.sensor_isp) {
++		rval = -EINVAL;
++	} else {
++		switch (cmd) {
++		case VIDIOC_PRIVATE_ISP_AEWB_REQ:
++		{
++			/* Need to update sensor first */
++			struct isph3a_aewb_data *data;
++			struct v4l2_control vc;
++
++			data = (struct isph3a_aewb_data *) arg;
++			if (data->update & SET_EXPOSURE) {
++				dev_info(&vdev->vfd->dev, "using "
++					 "VIDIOC_PRIVATE_ISP_AEWB_REQ to set "
++					 "exposure is deprecated!\n");
++				vc.id = V4L2_CID_EXPOSURE;
++				vc.value = data->shutter;
++				mutex_lock(&vdev->mutex);
++				rval = vidioc_int_s_ctrl(vdev->vdev_sensor,
++							 &vc);
++				mutex_unlock(&vdev->mutex);
++				if (rval)
++					goto out;
++			}
++			if (data->update & SET_ANALOG_GAIN) {
++				dev_info(&vdev->vfd->dev, "using "
++					 "VIDIOC_PRIVATE_ISP_AEWB_REQ to set "
++					 "gain is deprecated!\n");
++				vc.id = V4L2_CID_GAIN;
++				vc.value = data->gain;
++				mutex_lock(&vdev->mutex);
++				rval = vidioc_int_s_ctrl(vdev->vdev_sensor,
++							 &vc);
++				mutex_unlock(&vdev->mutex);
++				if (rval)
++					goto out;
++			}
++		}
++		break;
++		case VIDIOC_PRIVATE_ISP_AF_REQ: {
++			/* Need to update lens first */
++			struct isp_af_data *data;
++			struct v4l2_control vc;
++
++			if (!vdev->vdev_lens) {
++				rval = -EINVAL;
++				goto out;
++			}
++			data = (struct isp_af_data *) arg;
++			if (data->update & LENS_DESIRED_POSITION) {
++				dev_info(&vdev->vfd->dev, "using "
++					 "VIDIOC_PRIVATE_ISP_AF_REQ to set "
++					 "lens position is deprecated!\n");
++				vc.id = V4L2_CID_FOCUS_ABSOLUTE;
++				vc.value = data->desired_lens_direction;
++				mutex_lock(&vdev->mutex);
++				rval = vidioc_int_s_ctrl(vdev->vdev_lens, &vc);
++				mutex_unlock(&vdev->mutex);
++				if (rval)
++					goto out;
++			}
++		}
++			break;
++		}
++
++		mutex_lock(&vdev->mutex);
++		rval = isp_handle_private(cmd, arg);
++		mutex_unlock(&vdev->mutex);
++	}
++out:
++	return rval;
++}
++
++/*
++ *
++ * File operations.
++ *
++ */
++
++/**
++ * omap34xxcam_poll - file operations poll handler
++ * @file: ptr. to system file structure
++ * @wait: system poll table structure
++ *
++ */
++static unsigned int omap34xxcam_poll(struct file *file,
++				     struct poll_table_struct *wait)
++{
++	struct omap34xxcam_fh *fh = file->private_data;
++	struct omap34xxcam_videodev *vdev = fh->vdev;
++	struct videobuf_buffer *vb;
++
++	mutex_lock(&vdev->mutex);
++	if (vdev->streaming != file) {
++		mutex_unlock(&vdev->mutex);
++		return POLLERR;
++	}
++	mutex_unlock(&vdev->mutex);
++
++	mutex_lock(&fh->vbq.vb_lock);
++	if (list_empty(&fh->vbq.stream)) {
++		mutex_unlock(&fh->vbq.vb_lock);
++		return POLLERR;
++	}
++	vb = list_entry(fh->vbq.stream.next, struct videobuf_buffer, stream);
++	mutex_unlock(&fh->vbq.vb_lock);
++
++	poll_wait(file, &vb->done, wait);
++
++	if (vb->state == VIDEOBUF_DONE || vb->state == VIDEOBUF_ERROR)
++		return POLLIN | POLLRDNORM;
++
++	return 0;
++}
++
++/**
++ * omap34xxcam_mmap - file operations mmap handler
++ * @file: ptr. to system file structure
++ * @vma: system virt. mem. area structure
++ *
++ * Maps a virtual memory area via the video buffer API
++ */
++static int omap34xxcam_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	struct omap34xxcam_fh *fh = file->private_data;
++	return videobuf_mmap_mapper(&fh->vbq, vma);
++}
++
++/**
++ * omap34xxcam_open - file operations open handler
++ * @inode: ptr. to system inode structure
++ * @file: ptr. to system file structure
++ *
++ * Allocates and initializes the per-filehandle data (omap34xxcam_fh),
++ * enables the sensor, opens/initializes the ISP interface and the
++ * video buffer queue.  Note that this function will allow multiple
++ * file handles to be open simultaneously, however only the first
++ * handle opened will initialize the ISP.  It is the application
++ * responsibility to only use one handle for streaming and the others
++ * for control only.
++ * This function returns 0 upon success and -ENODEV upon error.
++ */
++static int omap34xxcam_open(struct file *file)
++{
++	int rval = 0;
++	struct omap34xxcam_videodev *vdev = NULL;
++	struct omap34xxcam_device *cam = omap34xxcam;
++	struct omap34xxcam_fh *fh;
++	struct v4l2_format format;
++	int i;
++
++	for (i = 0; i < OMAP34XXCAM_VIDEODEVS; i++) {
++		if (cam->vdevs[i].vfd
++		    && cam->vdevs[i].vfd->minor ==
++		    iminor(file->f_dentry->d_inode)) {
++			vdev = &cam->vdevs[i];
++			break;
++		}
++	}
++
++	if (!vdev || !vdev->vfd)
++		return -ENODEV;
++
++	fh = kzalloc(sizeof(*fh), GFP_KERNEL);
++	if (fh == NULL)
++		return -ENOMEM;
++
++	mutex_lock(&vdev->mutex);
++	for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++) {
++		if (vdev->slave[i] != v4l2_int_device_dummy()
++		    && !try_module_get(vdev->slave[i]->module)) {
++			mutex_unlock(&vdev->mutex);
++			dev_err(&vdev->vfd->dev, "can't try_module_get %s\n",
++				vdev->slave[i]->name);
++			rval = -ENODEV;
++			goto out_try_module_get;
++		}
++	}
++
++	if (atomic_inc_return(&vdev->users) == 1) {
++		rval = isp_get();
++		if (rval < 0) {
++			dev_err(&vdev->vfd->dev, "can't get isp\n");
++			goto out_isp_get;
++		}
++		if (omap34xxcam_slave_power_set(vdev, V4L2_POWER_ON,
++						OMAP34XXCAM_SLAVE_POWER_ALL)) {
++			dev_err(&vdev->vfd->dev, "can't power up slaves\n");
++			rval = -EBUSY;
++			goto out_slave_power_set_standby;
++		}
++		omap34xxcam_slave_power_set(
++			vdev, V4L2_POWER_STANDBY,
++			OMAP34XXCAM_SLAVE_POWER_SENSOR);
++		omap34xxcam_slave_power_suggest(
++			vdev, V4L2_POWER_STANDBY,
++			OMAP34XXCAM_SLAVE_POWER_LENS);
++	}
++
++	fh->vdev = vdev;
++
++	if (!vdev->pix.width
++	    && vdev->vdev_sensor != v4l2_int_device_dummy()) {
++		memset(&format, 0, sizeof(format));
++		if (vidioc_int_g_fmt_cap(vdev->vdev_sensor, &format)) {
++			dev_err(&vdev->vfd->dev,
++				"can't get current pix from sensor!\n");
++			goto out_vidioc_int_g_fmt_cap;
++		}
++		if (!vdev->vdev_sensor_config.sensor_isp) {
++			struct v4l2_pix_format pix = format.fmt.pix;
++			if (isp_s_fmt_cap(&pix, &format.fmt.pix)) {
++				dev_err(&vdev->vfd->dev,
++					"isp doesn't like the sensor!\n");
++				goto out_isp_s_fmt_cap;
++			}
++		}
++		vdev->pix = format.fmt.pix;
++	}
++
++	mutex_unlock(&vdev->mutex);
++
++	file->private_data = fh;
++
++	spin_lock_init(&fh->vbq_lock);
++
++	videobuf_queue_sg_init(&fh->vbq, &omap34xxcam_vbq_ops, NULL,
++				&fh->vbq_lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
++				V4L2_FIELD_NONE,
++				sizeof(struct videobuf_buffer), fh);
++
++	return 0;
++
++out_isp_s_fmt_cap:
++out_vidioc_int_g_fmt_cap:
++	omap34xxcam_slave_power_set(vdev, V4L2_POWER_OFF,
++				    OMAP34XXCAM_SLAVE_POWER_ALL);
++out_slave_power_set_standby:
++	isp_put();
++
++out_isp_get:
++	atomic_dec(&vdev->users);
++	mutex_unlock(&vdev->mutex);
++
++out_try_module_get:
++	for (i--; i >= 0; i--)
++		if (vdev->slave[i] != v4l2_int_device_dummy())
++			module_put(vdev->slave[i]->module);
++
++	kfree(fh);
++
++	return rval;
++}
++
++/**
++ * omap34xxcam_release - file operations release handler
++ * @inode: ptr. to system inode structure
++ * @file: ptr. to system file structure
++ *
++ * Complement of omap34xxcam_open.  This function will flush any scheduled
++ * work, disable the sensor, close the ISP interface, stop the
++ * video buffer queue from streaming and free the per-filehandle data
++ * (omap34xxcam_fh).  Note that because multiple open file handles
++ * are allowed, this function will only close the ISP and disable the
++ * sensor when the last open file handle (by count) is closed.
++ * This function returns 0.
++ */
++static int omap34xxcam_release(struct file *file)
++{
++	struct omap34xxcam_fh *fh = file->private_data;
++	struct omap34xxcam_videodev *vdev = fh->vdev;
++	int i;
++
++	mutex_lock(&vdev->mutex);
++	if (vdev->streaming == file) {
++		isp_stop();
++		videobuf_streamoff(&fh->vbq);
++		omap34xxcam_slave_power_set(
++			vdev, V4L2_POWER_STANDBY,
++			OMAP34XXCAM_SLAVE_POWER_SENSOR);
++		omap34xxcam_slave_power_suggest(
++			vdev, V4L2_POWER_STANDBY,
++			OMAP34XXCAM_SLAVE_POWER_LENS);
++		vdev->streaming = NULL;
++	}
++
++	if (atomic_dec_return(&vdev->users) == 0) {
++		omap34xxcam_slave_power_set(vdev, V4L2_POWER_OFF,
++					    OMAP34XXCAM_SLAVE_POWER_ALL);
++		isp_put();
++	}
++	mutex_unlock(&vdev->mutex);
++
++	file->private_data = NULL;
++
++	for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++)
++		if (vdev->slave[i] != v4l2_int_device_dummy())
++			module_put(vdev->slave[i]->module);
++
++	kfree(fh);
++
++	return 0;
++}
++
++static struct v4l2_file_operations omap34xxcam_fops = {
++	.owner = THIS_MODULE,
++	.unlocked_ioctl = video_ioctl2,
++	.poll = omap34xxcam_poll,
++	.mmap = omap34xxcam_mmap,
++	.open = omap34xxcam_open,
++	.release = omap34xxcam_release,
++};
++
++static void omap34xxcam_vfd_name_update(struct omap34xxcam_videodev *vdev)
++{
++	struct video_device *vfd = vdev->vfd;
++	int i;
++
++	strlcpy(vfd->name, CAM_SHORT_NAME, sizeof(vfd->name));
++	for (i = 0; i <= OMAP34XXCAM_SLAVE_FLASH; i++) {
++		strlcat(vfd->name, "/", sizeof(vfd->name));
++		if (vdev->slave[i] == v4l2_int_device_dummy())
++			continue;
++		strlcat(vfd->name, vdev->slave[i]->name, sizeof(vfd->name));
++	}
++	dev_info(&vdev->vfd->dev, "video%d is now %s\n", vfd->num, vfd->name);
++}
++
++/**
++ * omap34xxcam_device_unregister - V4L2 detach handler
++ * @s: ptr. to standard V4L2 device information structure
++ *
++ * Detach sensor and unregister and release the video device.
++ */
++static void omap34xxcam_device_unregister(struct v4l2_int_device *s)
++{
++	struct omap34xxcam_videodev *vdev = s->u.slave->master->priv;
++	struct omap34xxcam_hw_config hwc;
++
++	BUG_ON(vidioc_int_g_priv(s, &hwc) < 0);
++
++	mutex_lock(&vdev->mutex);
++
++	if (vdev->slave[hwc.dev_type] != v4l2_int_device_dummy()) {
++		vdev->slave[hwc.dev_type] = v4l2_int_device_dummy();
++		vdev->slaves--;
++		omap34xxcam_vfd_name_update(vdev);
++	}
++
++	if (vdev->slaves == 0 && vdev->vfd) {
++		if (vdev->vfd->minor == -1) {
++			/*
++			 * The device was never registered, so release the
++			 * video_device struct directly.
++			 */
++			video_device_release(vdev->vfd);
++		} else {
++			/*
++			 * The unregister function will release the
++			 * video_device struct as well as
++			 * unregistering it.
++			 */
++			video_unregister_device(vdev->vfd);
++		}
++		vdev->vfd = NULL;
++	}
++
++	mutex_unlock(&vdev->mutex);
++}
++
++static const struct v4l2_ioctl_ops omap34xxcam_ioctl_ops = {
++	.vidioc_querycap		= vidioc_querycap,
++	.vidioc_enum_fmt_vid_cap	= vidioc_enum_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap		= vidioc_g_fmt_vid_cap,
++	.vidioc_s_fmt_vid_cap		= vidioc_s_fmt_vid_cap,
++	.vidioc_try_fmt_vid_cap		= vidioc_try_fmt_vid_cap,
++	.vidioc_reqbufs			= vidioc_reqbufs,
++	.vidioc_querybuf		= vidioc_querybuf,
++	.vidioc_qbuf			= vidioc_qbuf,
++	.vidioc_dqbuf			= vidioc_dqbuf,
++	.vidioc_streamon		= vidioc_streamon,
++	.vidioc_streamoff		= vidioc_streamoff,
++	.vidioc_enum_input		= vidioc_enum_input,
++	.vidioc_g_input			= vidioc_g_input,
++	.vidioc_s_input			= vidioc_s_input,
++	.vidioc_queryctrl		= vidioc_queryctrl,
++	.vidioc_querymenu		= vidioc_querymenu,
++	.vidioc_g_ext_ctrls		= vidioc_g_ext_ctrls,
++	.vidioc_s_ext_ctrls		= vidioc_s_ext_ctrls,
++	.vidioc_g_parm			= vidioc_g_parm,
++	.vidioc_s_parm			= vidioc_s_parm,
++	.vidioc_cropcap			= vidioc_cropcap,
++	.vidioc_g_crop			= vidioc_g_crop,
++	.vidioc_s_crop			= vidioc_s_crop,
++	.vidioc_enum_framesizes		= vidioc_enum_framesizes,
++	.vidioc_enum_frameintervals	= vidioc_enum_frameintervals,
++	.vidioc_default			= vidioc_default,
++};
++
++/**
++ * omap34xxcam_device_register - V4L2 attach handler
++ * @s: ptr. to standard V4L2 device information structure
++ *
++ * Allocates and initializes the V4L2 video_device structure, initializes
++ * the sensor, and finally
++ registers the device with V4L2 based on the
++ * video_device structure.
++ *
++ * Returns 0 on success, otherwise an appropriate error code on
++ * failure.
++ */
++static int omap34xxcam_device_register(struct v4l2_int_device *s)
++{
++	struct omap34xxcam_videodev *vdev = s->u.slave->master->priv;
++	struct omap34xxcam_hw_config hwc;
++	int rval;
++
++	/* We need to check rval just once. The place is here. */
++	if (vidioc_int_g_priv(s, &hwc))
++		return -ENODEV;
++
++	if (vdev->index != hwc.dev_index)
++		return -ENODEV;
++
++	if (hwc.dev_type < 0 || hwc.dev_type > OMAP34XXCAM_SLAVE_FLASH)
++		return -EINVAL;
++
++	if (vdev->slave[hwc.dev_type] != v4l2_int_device_dummy())
++		return -EBUSY;
++
++	mutex_lock(&vdev->mutex);
++	if (atomic_read(&vdev->users)) {
++		printk(KERN_ERR "%s: we're open (%d), can't register\n",
++		       __func__, atomic_read(&vdev->users));
++		mutex_unlock(&vdev->mutex);
++		return -EBUSY;
++	}
++
++	vdev->slaves++;
++	vdev->slave[hwc.dev_type] = s;
++	vdev->slave_config[hwc.dev_type] = hwc;
++
++	if (hwc.dev_type == OMAP34XXCAM_SLAVE_SENSOR) {
++		rval = isp_get();
++		if (rval < 0) {
++			printk(KERN_ERR "%s: can't get ISP, "
++			       "sensor init failed\n", __func__);
++			goto err;
++		}
++	}
++	rval = omap34xxcam_slave_power_set(vdev, V4L2_POWER_ON,
++					   1 << hwc.dev_type);
++	if (rval)
++		goto err_omap34xxcam_slave_power_set;
++	if (hwc.dev_type == OMAP34XXCAM_SLAVE_SENSOR) {
++		struct v4l2_format format;
++
++		format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++		rval = vidioc_int_g_fmt_cap(vdev->vdev_sensor, &format);
++		if (rval)
++			rval = -EBUSY;
++
++		vdev->want_pix = format.fmt.pix;
++	}
++	omap34xxcam_slave_power_set(vdev, V4L2_POWER_OFF, 1 << hwc.dev_type);
++	if (hwc.dev_type == OMAP34XXCAM_SLAVE_SENSOR)
++		isp_put();
++
++	if (rval)
++		goto err;
++
++	/* Are we the first slave? */
++	if (vdev->slaves == 1) {
++		/* initialize the video_device struct */
++		vdev->vfd = video_device_alloc();
++		if (!vdev->vfd) {
++			printk(KERN_ERR "%s: could not allocate "
++			       "video device struct\n", __func__);
++			rval = -ENOMEM;
++			goto err;
++		}
++		vdev->vfd->release	= video_device_release;
++		vdev->vfd->minor	= -1;
++		vdev->vfd->fops		= &omap34xxcam_fops;
++		vdev->vfd->ioctl_ops	= &omap34xxcam_ioctl_ops;
++		video_set_drvdata(vdev->vfd, vdev);
++
++		if (video_register_device(vdev->vfd, VFL_TYPE_GRABBER,
++					  hwc.dev_minor) < 0) {
++			printk(KERN_ERR "%s: could not register V4L device\n",
++				__func__);
++			vdev->vfd->minor = -1;
++			rval = -EBUSY;
++			goto err;
++		}
++	}
++
++	omap34xxcam_vfd_name_update(vdev);
++
++	mutex_unlock(&vdev->mutex);
++
++	return 0;
++
++err_omap34xxcam_slave_power_set:
++	if (hwc.dev_type == OMAP34XXCAM_SLAVE_SENSOR)
++		isp_put();
++
++err:
++	if (s == vdev->slave[hwc.dev_type]) {
++		vdev->slave[hwc.dev_type] = v4l2_int_device_dummy();
++		vdev->slaves--;
++	}
++
++	mutex_unlock(&vdev->mutex);
++	omap34xxcam_device_unregister(s);
++
++	return rval;
++}
++
++static struct v4l2_int_master omap34xxcam_master = {
++	.attach = omap34xxcam_device_register,
++	.detach = omap34xxcam_device_unregister,
++};
++
++/*
++ *
++ * Module initialisation and deinitialisation
++ *
++ */
++
++static void omap34xxcam_exit(void)
++{
++	struct omap34xxcam_device *cam = omap34xxcam;
++	int i;
++
++	if (!cam)
++		return;
++
++	for (i = 0; i < OMAP34XXCAM_VIDEODEVS; i++) {
++		if (cam->vdevs[i].cam == NULL)
++			continue;
++
++		v4l2_int_device_unregister(&cam->vdevs[i].master);
++		cam->vdevs[i].cam = NULL;
++	}
++
++	omap34xxcam = NULL;
++
++	kfree(cam);
++}
++
++static int __init omap34xxcam_init(void)
++{
++	struct omap34xxcam_device *cam;
++	int i;
++
++	cam = kzalloc(sizeof(*cam), GFP_KERNEL);
++	if (!cam) {
++		printk(KERN_ERR "%s: could not allocate memory\n", __func__);
++		return -ENOMEM;
++	}
++
++	omap34xxcam = cam;
++
++	for (i = 0; i < OMAP34XXCAM_VIDEODEVS; i++) {
++		struct omap34xxcam_videodev *vdev = &cam->vdevs[i];
++		struct v4l2_int_device *m = &vdev->master;
++
++		m->module       = THIS_MODULE;
++		strlcpy(m->name, CAM_NAME, sizeof(m->name));
++		m->type         = v4l2_int_type_master;
++		m->u.master     = &omap34xxcam_master;
++		m->priv		= vdev;
++
++		mutex_init(&vdev->mutex);
++		vdev->index             = i;
++		vdev->cam               = cam;
++		vdev->vdev_sensor =
++			vdev->vdev_lens =
++			vdev->vdev_flash = v4l2_int_device_dummy();
++#ifdef OMAP34XXCAM_POWEROFF_DELAY
++		setup_timer(&vdev->poweroff_timer,
++			    omap34xxcam_slave_power_timer, (unsigned long)vdev);
++		INIT_WORK(&vdev->poweroff_work, omap34xxcam_slave_power_work);
++#endif /* OMAP34XXCAM_POWEROFF_DELAY */
++
++		if (v4l2_int_device_register(m))
++			goto err;
++	}
++
++	return 0;
++
++err:
++	omap34xxcam_exit();
++	return -ENODEV;
++}
++
++MODULE_AUTHOR("Sakari Ailus <sakari.ailus@nokia.com>");
++MODULE_DESCRIPTION("OMAP34xx Video for Linux camera driver");
++MODULE_LICENSE("GPL");
++
++late_initcall(omap34xxcam_init);
++module_exit(omap34xxcam_exit);
+diff --git a/drivers/media/video/omap34xxcam.h b/drivers/media/video/omap34xxcam.h
+new file mode 100644
+index 0000000..9859d15
+--- /dev/null
++++ b/drivers/media/video/omap34xxcam.h
+@@ -0,0 +1,207 @@
++/*
++ * omap34xxcam.h
++ *
++ * Copyright (C) 2006--2009 Nokia Corporation
++ * Copyright (C) 2007--2009 Texas Instruments
++ *
++ * Contact: Sakari Ailus <sakari.ailus@nokia.com>
++ *          Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
++ *
++ * Originally based on the OMAP 2 camera driver.
++ *
++ * Written by Sakari Ailus <sakari.ailus@nokia.com>
++ *            Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
++ *            Sergio Aguirre <saaguirre@ti.com>
++ *            Mohit Jalori
++ *            Sameer Venkatraman
++ *            Leonides Martinez
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++ * 02110-1301 USA
++ *
++ */
++
++#ifndef OMAP34XXCAM_H
++#define OMAP34XXCAM_H
++
++#include <media/v4l2-int-device.h>
++#include "isp/isp.h"
++
++#define CAM_NAME			"omap34xxcam"
++#define CAM_SHORT_NAME			"omap3"
++
++#define OMAP_ISP_AF     	(1 << 4)
++#define OMAP_ISP_HIST   	(1 << 5)
++#define OMAP34XXCAM_XCLK_NONE	-1
++#define OMAP34XXCAM_XCLK_A	0
++#define OMAP34XXCAM_XCLK_B	1
++
++#define OMAP34XXCAM_SLAVE_SENSOR	0
++#define OMAP34XXCAM_SLAVE_LENS		1
++#define OMAP34XXCAM_SLAVE_FLASH		2 /* This is the last slave! */
++
++/* mask for omap34xxcam_slave_power_set */
++#define OMAP34XXCAM_SLAVE_POWER_SENSOR	(1 << OMAP34XXCAM_SLAVE_SENSOR)
++#define OMAP34XXCAM_SLAVE_POWER_LENS	(1 << OMAP34XXCAM_SLAVE_LENS)
++#define OMAP34XXCAM_SLAVE_POWER_SENSOR_LENS \
++	(OMAP34XXCAM_SLAVE_POWER_SENSOR | OMAP34XXCAM_SLAVE_POWER_LENS)
++#define OMAP34XXCAM_SLAVE_POWER_FLASH	(1 << OMAP34XXCAM_SLAVE_FLASH)
++#define OMAP34XXCAM_SLAVE_POWER_ALL	-1
++
++#define OMAP34XXCAM_VIDEODEVS		4
++
++/* #define OMAP34XXCAM_POWEROFF_DELAY (2 * HZ) */
++
++struct omap34xxcam_device;
++struct omap34xxcam_videodev;
++
++struct omap34xxcam_sensor_config {
++	int xclk;
++	int sensor_isp;
++	u32 capture_mem;
++	struct v4l2_fract ival_default;
++};
++
++struct omap34xxcam_lens_config {
++};
++
++struct omap34xxcam_flash_config {
++};
++
++/**
++ * struct omap34xxcam_hw_config - struct for vidioc_int_g_priv ioctl
++ * @xclk: OMAP34XXCAM_XCLK_A or OMAP34XXCAM_XCLK_B
++ * @sensor_isp: Is sensor smart/SOC or raw
++ * @s_pix_sparm: Access function to set pix and sparm.
++ * Pix will override sparm
++ */
++struct omap34xxcam_hw_config {
++	int dev_index; /* Index in omap34xxcam_sensors */
++	int dev_minor; /* Video device minor number */
++	int dev_type; /* OMAP34XXCAM_SLAVE_* */
++	union {
++		struct omap34xxcam_sensor_config sensor;
++		struct omap34xxcam_lens_config lens;
++		struct omap34xxcam_flash_config flash;
++	} u;
++};
++
++/**
++ * struct omap34xxcam_videodev - per /dev/video* structure
++ * @mutex: serialises access to this structure
++ * @cam: pointer to cam hw structure
++ * @master: we are v4l2_int_device master
++ * @sensor: sensor device
++ * @lens: lens device
++ * @flash: flash device
++ * @slaves: how many slaves we have at the moment
++ * @vfd: our video device
++ * @capture_mem: maximum kernel-allocated capture memory
++ * @if_u: sensor interface stuff
++ * @index: index of this structure in cam->vdevs
++ * @users: how many users we have
++ * @power_state: Current power state
++ * @power_state_wish: New power state when poweroff_timer expires
++ * @power_state_mask: Bitmask of devices to set the new power state
++ * @poweroff_timer: Timer for dispatching poweroff_work
++ * @poweroff_work: Work for slave power state change
++ * @sensor_config: ISP-speicific sensor configuration
++ * @lens_config: ISP-speicific lens configuration
++ * @flash_config: ISP-speicific flash configuration
++ * @want_timeperframe: Desired timeperframe
++ * @want_pix: Desired pix
++ * @pix: Current pix
++ * @streaming: streaming file handle, if streaming is enabled
++ */
++struct omap34xxcam_videodev {
++	struct mutex mutex; /* serialises access to this structure */
++
++	struct omap34xxcam_device *cam;
++	struct v4l2_int_device master;
++
++#define vdev_sensor slave[OMAP34XXCAM_SLAVE_SENSOR]
++#define vdev_lens slave[OMAP34XXCAM_SLAVE_LENS]
++#define vdev_flash slave[OMAP34XXCAM_SLAVE_FLASH]
++	struct v4l2_int_device *slave[OMAP34XXCAM_SLAVE_FLASH + 1];
++
++	/* number of slaves attached */
++	int slaves;
++
++	/*** video device parameters ***/
++	struct video_device *vfd;
++	int capture_mem;
++
++	/*** general driver state information ***/
++	int index;
++	atomic_t users;
++	enum v4l2_power power_state[OMAP34XXCAM_SLAVE_FLASH + 1];
++#ifdef OMAP34XXCAM_POWEROFF_DELAY
++	enum v4l2_power power_state_wish;
++	int power_state_mask;
++	struct timer_list poweroff_timer;
++	struct work_struct poweroff_work;
++#endif /* OMAP34XXCAM_POWEROFF_DELAY */
++
++#define vdev_sensor_config slave_config[OMAP34XXCAM_SLAVE_SENSOR].u.sensor
++#define vdev_lens_config slave_config[OMAP34XXCAM_SLAVE_LENS].u.lens
++#define vdev_flash_config slave_config[OMAP34XXCAM_SLAVE_FLASH].u.flash
++	struct omap34xxcam_hw_config slave_config[OMAP34XXCAM_SLAVE_FLASH + 1];
++
++	/*** capture data ***/
++	struct file *streaming;
++	struct v4l2_fract want_timeperframe;
++	struct v4l2_pix_format want_pix;
++	spinlock_t pix_lock;
++	struct v4l2_pix_format pix;
++};
++
++/**
++ * struct omap34xxcam_device - per-device data structure
++ * @mutex: mutex serialises access to this structure
++ * @sgdma_in_queue: Number or sgdma requests in scatter-gather queue,
++ * protected by the lock above.
++ * @sgdma: ISP sgdma subsystem information structure
++ * @dma_notify: DMA notify flag
++ * @dev: device structure
++ * @vdevs: /dev/video specific structures
++ * @fck: camera module fck clock information
++ * @ick: camera module ick clock information
++ */
++struct omap34xxcam_device {
++	struct mutex mutex; /* serialises access to this structure */
++
++	/*** interfaces and device ***/
++	struct omap34xxcam_videodev vdevs[OMAP34XXCAM_VIDEODEVS];
++
++	/*** camera module clocks ***/
++	struct clk *fck;
++	struct clk *ick;
++	bool sensor_if_enabled;
++};
++
++/**
++ * struct omap34xxcam_fh - per-filehandle data structure
++ * @vbq_lock: spinlock for the videobuf queue
++ * @vbq: V4L2 video buffer queue structure
++ * @field_count: field counter for videobuf_buffer
++ * @vdev: our /dev/video specific structure
++ */
++struct omap34xxcam_fh {
++	spinlock_t vbq_lock; /* spinlock for the videobuf queue */
++	struct videobuf_queue vbq;
++	atomic_t field_count;
++	struct omap34xxcam_videodev *vdev;
++};
++
++#endif /* ifndef OMAP34XXCAM_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0023-OMAP-Resizer-Basic-Resizer-refreshed-with-latest-gi.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0023-OMAP-Resizer-Basic-Resizer-refreshed-with-latest-gi.patch
new file mode 100644
index 0000000000..3390599292
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0023-OMAP-Resizer-Basic-Resizer-refreshed-with-latest-gi.patch
@@ -0,0 +1,1890 @@
+From 38f3cd5564a466e5251fc2ff47e0504148922304 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <vaibhav@psp-nfs-02.india.ti.com>
+Date: Wed, 29 Apr 2009 17:18:56 +0530
+Subject: [PATCH 23/26] OMAP-Resizer: Basic Resizer refreshed with latest gitorious tree
+
+This is same resizer driver patch posted by Sergio onto
+mailing list quite a some time back. This commit refreshes
+the same patch on top of latest gitorious.org tree.
+
+List of New/Modified files:
+ modified:   drivers/media/video/Kconfig
+ modified:   drivers/media/video/isp/Makefile
+ modified:   drivers/media/video/isp/isp.c
+ modified:   drivers/media/video/isp/ispreg.h
+ new file:   drivers/media/video/isp/omap_resizer.c
+ new file:   include/linux/omap_resizer.h
+
+TODO:
+ - Resizer driver needs to be independent from camera and ISP
+ - Custom patches implemented ontop of PSP1.0.2 release
+   to fix some V4L2-buf layer issues.
+ -
+---
+ drivers/media/video/Kconfig            |    7 +
+ drivers/media/video/isp/Makefile       |    4 +
+ drivers/media/video/isp/isp.c          |   15 +
+ drivers/media/video/isp/omap_resizer.c | 1634 ++++++++++++++++++++++++++++++++
+ include/linux/omap_resizer.h           |  136 +++
+ 5 files changed, 1796 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/isp/omap_resizer.c
+ create mode 100644 include/linux/omap_resizer.h
+
+diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
+index 3cdb5a4..d2b4ae1 100644
+--- a/drivers/media/video/Kconfig
++++ b/drivers/media/video/Kconfig
+@@ -720,6 +720,13 @@ config VIDEO_OMAP3
+ 	---help---
+ 	  Driver for an OMAP 3 camera controller.
+ 
++config VIDEO_OMAP34XX_ISP_RESIZER
++	tristate "OMAP ISP Resizer"
++	depends on VIDEO_V4L2 && ARCH_OMAP34XX
++	select VIDEOBUF_GEN
++	select VIDEOBUF_DMA_SG
++	select OMAP_IOMMU
++
+ config SOC_CAMERA
+ 	tristate "SoC camera support"
+ 	depends on VIDEO_V4L2 && HAS_DMA
+diff --git a/drivers/media/video/isp/Makefile b/drivers/media/video/isp/Makefile
+index f14d617..d171fb9 100644
+--- a/drivers/media/video/isp/Makefile
++++ b/drivers/media/video/isp/Makefile
+@@ -7,6 +7,10 @@ else
+ isp-mod-objs += \
+ 	isp.o ispccdc.o ispmmu.o \
+ 	isppreview.o ispresizer.o isph3a.o isphist.o isp_af.o ispcsi2.o
++
++obj-$(CONFIG_VIDEO_OMAP34XX_ISP_RESIZER) += \
++	omap_resizer.o
++
+ endif
+ 
+ obj-$(CONFIG_VIDEO_OMAP3) += isp-mod.o
+diff --git a/drivers/media/video/isp/isp.c b/drivers/media/video/isp/isp.c
+index 54c839b..f1f92b4 100644
+--- a/drivers/media/video/isp/isp.c
++++ b/drivers/media/video/isp/isp.c
+@@ -505,6 +505,12 @@ int isp_set_callback(enum isp_callback_type type, isp_callback_t callback,
+ 		isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
+ 			   IRQ0ENABLE_PRV_DONE_IRQ);
+ 		break;
++	case CBK_RESZ_DONE:
++		isp_reg_writel(IRQ0ENABLE_RSZ_DONE_IRQ,
++				OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
++		isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++				IRQ0ENABLE_RSZ_DONE_IRQ);
++		break;
+ 	default:
+ 		break;
+ 	}
+@@ -556,6 +562,10 @@ int isp_unset_callback(enum isp_callback_type type)
+ 		isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
+ 			    ~IRQ0ENABLE_PRV_DONE_IRQ);
+ 		break;
++	case CBK_RESZ_DONE:
++		isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
++				~IRQ0ENABLE_RSZ_DONE_IRQ);
++		break;
+ 	default:
+ 		break;
+ 	}
+@@ -938,6 +948,11 @@ static irqreturn_t omap34xx_isp_isr(int irq, void *_isp)
+ 			if (!ispresizer_busy())
+ 				ispresizer_config_shadow_registers();
+ 			isp_buf_process(bufs);
++		} else {
++			if (irqdis->isp_callbk[CBK_RESZ_DONE])
++				irqdis->isp_callbk[CBK_RESZ_DONE](RESZ_DONE,
++						irqdis->isp_callbk_arg1[CBK_RESZ_DONE],
++						irqdis->isp_callbk_arg2[CBK_RESZ_DONE]);
+ 		}
+ 	}
+ 
+diff --git a/drivers/media/video/isp/omap_resizer.c b/drivers/media/video/isp/omap_resizer.c
+new file mode 100644
+index 0000000..54bc425
+--- /dev/null
++++ b/drivers/media/video/isp/omap_resizer.c
+@@ -0,0 +1,1634 @@
++/*
++ * drivers/media/video/isp/omap_resizer.c
++ *
++ * Wrapper for Resizer module in TI's OMAP3430 ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * Contributors:
++ * 	Sergio Aguirre <saaguirre@ti.com>
++ * 	Troy Laramy <t-laramy@ti.com>
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/mutex.h>
++#include <linux/cdev.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/uaccess.h>
++#include <media/v4l2-dev.h>
++#include <asm/cacheflush.h>
++
++#include "isp.h"
++#include "ispmmu.h"
++#include "ispreg.h"
++#include "ispresizer.h"
++#include <linux/omap_resizer.h>
++
++#define OMAP_REZR_NAME		"omap-resizer"
++
++/* Defines and Constants*/
++#define MAX_CHANNELS		16
++#define MAX_IMAGE_WIDTH		2047
++#define MAX_IMAGE_WIDTH_HIGH	2047
++#define ALIGNMENT		16
++#define CHANNEL_BUSY		1
++#define CHANNEL_FREE		0
++#define PIXEL_EVEN		2
++#define RATIO_MULTIPLIER	256
++/* Bit position Macro */
++/* macro for bit set and clear */
++#define BITSET(variable, bit)	((variable) | (1 << bit))
++#define BITRESET(variable, bit)	((variable) & ~(0x00000001 << (bit)))
++#define SET_BIT_INPUTRAM	28
++#define SET_BIT_CBLIN		29
++#define SET_BIT_INPTYP		27
++#define SET_BIT_YCPOS		26
++#define INPUT_RAM		1
++#define UP_RSZ_RATIO		64
++#define DOWN_RSZ_RATIO		512
++#define UP_RSZ_RATIO1		513
++#define DOWN_RSZ_RATIO1		1024
++#define RSZ_IN_SIZE_VERT_SHIFT	16
++#define MAX_HORZ_PIXEL_8BIT	31
++#define MAX_HORZ_PIXEL_16BIT	15
++#define NUM_PHASES		8
++#define NUM_TAPS		4
++#define NUM_D2PH		4	/* for downsampling * 2+x ~ 4x,
++					 * number of phases
++					 */
++#define NUM_D2TAPS		7 	/* for downsampling * 2+x ~ 4x,
++					 * number of taps
++					 */
++#define ALIGN32			32
++#define MAX_COEF_COUNTER	16
++#define COEFF_ADDRESS_OFFSET	0x04
++
++/* Global structure which contains information about number of channels
++   and protection variables */
++struct device_params {
++
++	unsigned char opened;			/* state of the device */
++	struct completion compl_isr;		/* Completion for interrupt */
++	struct mutex reszwrap_mutex;		/* Semaphore for array */
++
++	struct videobuf_queue_ops vbq_ops;	/* videobuf queue operations */
++};
++
++/* Register mapped structure which contains the every register
++   information */
++struct resizer_config {
++	u32 rsz_pcr;				/* pcr register mapping
++						 * variable.
++						 */
++	u32 rsz_in_start;			/* in_start register mapping
++						 * variable.
++						 */
++	u32 rsz_in_size;			/* in_size register mapping
++						 * variable.
++						 */
++	u32 rsz_out_size;			/* out_size register mapping
++						 * variable.
++						 */
++	u32 rsz_cnt;				/* rsz_cnt register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_inadd;			/* sdr_inadd register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_inoff;			/* sdr_inoff register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_outadd;			/* sdr_outadd register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_outoff;			/* sdr_outbuff register
++						 * mapping variable.
++						 */
++	u32 rsz_coeff_horz[16];			/* horizontal coefficients
++						 * mapping array.
++						 */
++	u32 rsz_coeff_vert[16];			/* vertical coefficients
++						 * mapping array.
++						 */
++	u32 rsz_yehn;				/* yehn(luma)register mapping
++						 * variable.
++						 */
++};
++
++struct rsz_mult {
++	int in_hsize;				/* input frame horizontal
++						 * size.
++						 */
++	int in_vsize;				/* input frame vertical size.
++						 */
++	int out_hsize;				/* output frame horizontal
++						 * size.
++						 */
++	int out_vsize;				/* output frame vertical
++						 * size.
++						 */
++	int in_pitch;				/* offset between two rows of
++						 * input frame.
++						 */
++	int out_pitch;				/* offset between two rows of
++						 * output frame.
++						 */
++	int end_hsize;
++	int end_vsize;
++	int num_htap;				/* 0 = 7tap; 1 = 4tap */
++	int num_vtap;				/* 0 = 7tap; 1 = 4tap */
++	int active;
++	int inptyp;
++	int vrsz;
++	int hrsz;
++	int hstph;				/* for specifying horizontal
++						 * starting phase.
++						 */
++	int vstph;
++	int pix_fmt;				/* # defined, UYVY or YUYV. */
++	int cbilin;				/* # defined, filter with luma
++						 * or bi-linear.
++						 */
++	u16 tap4filt_coeffs[32];		/* horizontal filter
++						 * coefficients.
++						 */
++	u16 tap7filt_coeffs[32];		/* vertical filter
++						 * coefficients.
++						 */
++};
++/* Channel specific structure contains information regarding
++   the every channel */
++struct channel_config {
++	struct resizer_config register_config;	/* Instance of register set
++						 * mapping structure
++						 */
++	int status;				/* Specifies whether the
++						 * channel is busy or not
++						 */
++	struct mutex chanprotection_mutex;
++	enum config_done config_state;
++	u8 input_buf_index;
++	u8 output_buf_index;
++
++};
++
++/* per-filehandle data structure */
++struct rsz_fh {
++	struct rsz_params *params;
++	struct channel_config *config;
++	struct rsz_mult *multipass;		/* Multipass to support
++						 * resizing ration outside
++						 * of 0.25x to 4x
++						 */
++	spinlock_t vbq_lock;			/* spinlock for videobuf
++						 * queues.
++						 */
++	enum v4l2_buf_type type;
++	struct videobuf_queue vbq;
++	struct device_params *device;
++
++	dma_addr_t isp_addr_read;		/* Input/Output address */
++	dma_addr_t isp_addr_write;		/* Input/Output address */
++	u32 rsz_bufsize;			/* channel specific buffersize
++						 */
++};
++
++static struct device_params *device_config;
++static struct device *rsz_device;
++static int rsz_major = -1;
++/* functions declaration */
++static void rsz_hardware_setup(struct channel_config *rsz_conf_chan);
++static int rsz_set_params(struct rsz_mult *multipass, struct rsz_params *,
++						struct channel_config *);
++static int rsz_get_params(struct rsz_params *, struct channel_config *);
++static void rsz_copy_data(struct rsz_mult *multipass,
++						struct rsz_params *params);
++static void rsz_isr(unsigned long status, isp_vbq_callback_ptr arg1,
++						void *arg2);
++static void rsz_calculate_crop(struct channel_config *rsz_conf_chan,
++					struct rsz_cropsize *cropsize);
++static int rsz_set_multipass(struct rsz_mult *multipass,
++					struct channel_config *rsz_conf_chan);
++static int rsz_set_ratio(struct rsz_mult *multipass,
++					struct channel_config *rsz_conf_chan);
++static void rsz_config_ratio(struct rsz_mult *multipass,
++					struct channel_config *rsz_conf_chan);
++
++/**
++ * rsz_hardware_setup - Sets hardware configuration registers
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Set hardware configuration registers
++ **/
++static void rsz_hardware_setup(struct channel_config *rsz_conf_chan)
++{
++	int coeffcounter;
++	int coeffoffset = 0;
++
++	omap_writel(rsz_conf_chan->register_config.rsz_cnt,
++					OMAP3ISP_RESZ_REG(ISPRSZ_CNT));
++
++	omap_writel(rsz_conf_chan->register_config.rsz_in_start,
++					OMAP3ISP_RESZ_REG(ISPRSZ_IN_START));
++	omap_writel(rsz_conf_chan->register_config.rsz_in_size,
++					OMAP3ISP_RESZ_REG(ISPRSZ_IN_SIZE));
++
++	omap_writel(rsz_conf_chan->register_config.rsz_out_size,
++					OMAP3ISP_RESZ_REG(ISPRSZ_OUT_SIZE));
++	omap_writel(rsz_conf_chan->register_config.rsz_sdr_inadd,
++					OMAP3ISP_RESZ_REG(ISPRSZ_SDR_INADD));
++	omap_writel(rsz_conf_chan->register_config.rsz_sdr_inoff,
++					OMAP3ISP_RESZ_REG(ISPRSZ_SDR_INOFF));
++	omap_writel(rsz_conf_chan->register_config.rsz_sdr_outadd,
++					OMAP3ISP_RESZ_REG(ISPRSZ_SDR_OUTADD));
++	omap_writel(rsz_conf_chan->register_config.rsz_sdr_outoff,
++					OMAP3ISP_RESZ_REG(ISPRSZ_SDR_OUTOFF));
++	omap_writel(rsz_conf_chan->register_config.rsz_yehn, OMAP3ISP_RESZ_REG(ISPRSZ_YENH));
++
++	for (coeffcounter = 0; coeffcounter < MAX_COEF_COUNTER;
++							coeffcounter++) {
++		omap_writel(rsz_conf_chan->register_config.
++					rsz_coeff_horz[coeffcounter],
++					OMAP3ISP_RESZ_REG(ISPRSZ_HFILT10
++						+ coeffoffset));
++
++		omap_writel(rsz_conf_chan->register_config.
++					rsz_coeff_vert[coeffcounter],
++					OMAP3ISP_RESZ_REG(ISPRSZ_VFILT10
++						+ coeffoffset));
++		coeffoffset = coeffoffset + COEFF_ADDRESS_OFFSET;
++	}
++}
++
++/**
++ * rsz_start - Enables Resizer Wrapper
++ * @arg: Currently not used.
++ * @device: Structure containing ISP resizer wrapper global information
++ *
++ * Submits a resizing task specified by the rsz_resize structure. The call can
++ * either be blocked until the task is completed or returned immediately based
++ * on the value of the blocking argument in the rsz_resize structure. If it is
++ * blocking, the status of the task can be checked by calling ioctl
++ * RSZ_G_STATUS. Only one task can be outstanding for each logical channel.
++ *
++ * Returns 0 if successful, or -EINVAL if could not set callback for RSZR IRQ
++ * event or the state of the channel is not configured.
++ **/
++int rsz_start(int *arg, struct rsz_fh *fh)
++{
++	struct channel_config *rsz_conf_chan = fh->config;
++	struct rsz_mult *multipass = fh->multipass;
++	struct videobuf_queue *q = &fh->vbq;
++	int ret;
++
++	if (rsz_conf_chan->config_state) {
++		dev_err(rsz_device, "State not configured \n");
++		goto err_einval;
++	}
++
++	rsz_conf_chan->status = CHANNEL_BUSY;
++
++	rsz_hardware_setup(rsz_conf_chan);
++
++	if (isp_set_callback(CBK_RESZ_DONE, rsz_isr, (void *) NULL,
++							(void *)NULL)) {
++		dev_err(rsz_device, "No callback for RSZR\n");
++		goto err_einval;
++	}
++mult:
++	device_config->compl_isr.done = 0;
++
++	ispresizer_enable(1);
++
++	ret = wait_for_completion_interruptible(&device_config->compl_isr);
++	if (ret != 0) {
++		dev_dbg(rsz_device, "Unexpected exit from "
++				"wait_for_completion_interruptible\n");
++		wait_for_completion(&device_config->compl_isr);
++	}
++
++	if (multipass->active) {
++		rsz_set_multipass(multipass, rsz_conf_chan);
++		goto mult;
++	}
++
++	if (fh->isp_addr_read) {
++		ispmmu_unmap(fh->isp_addr_read);
++		fh->isp_addr_read = 0;
++	}
++	if (fh->isp_addr_write) {
++		ispmmu_unmap(fh->isp_addr_write);
++		fh->isp_addr_write = 0;
++	}
++
++	rsz_conf_chan->status = CHANNEL_FREE;
++	q->bufs[rsz_conf_chan->input_buf_index]->state = VIDEOBUF_NEEDS_INIT;
++	q->bufs[rsz_conf_chan->output_buf_index]->state = VIDEOBUF_NEEDS_INIT;
++	rsz_conf_chan->register_config.rsz_sdr_outadd = 0;
++	rsz_conf_chan->register_config.rsz_sdr_inadd = 0;
++
++	/* Unmap and free the DMA memory allocated for buffers */
++	videobuf_dma_unmap(q, videobuf_to_dma(
++				q->bufs[rsz_conf_chan->input_buf_index]));
++	videobuf_dma_unmap(q, videobuf_to_dma(
++				q->bufs[rsz_conf_chan->output_buf_index]));
++	videobuf_dma_free(videobuf_to_dma(
++				q->bufs[rsz_conf_chan->input_buf_index]));
++	videobuf_dma_free(videobuf_to_dma(
++				q->bufs[rsz_conf_chan->output_buf_index]));
++
++	isp_unset_callback(CBK_RESZ_DONE);
++
++	return 0;
++err_einval:
++	return -EINVAL;
++}
++
++/**
++ * rsz_set_multipass - Set resizer multipass
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Returns always 0
++ **/
++static int rsz_set_multipass(struct rsz_mult *multipass,
++			struct channel_config *rsz_conf_chan)
++{
++	multipass->in_hsize = multipass->out_hsize;
++	multipass->in_vsize = multipass->out_vsize;
++	multipass->out_hsize = multipass->end_hsize;
++	multipass->out_vsize = multipass->end_vsize;
++
++	multipass->out_pitch = (multipass->inptyp ? multipass->out_hsize
++						: (multipass->out_hsize * 2));
++	multipass->in_pitch = (multipass->inptyp ? multipass->in_hsize
++						: (multipass->in_hsize * 2));
++
++	rsz_set_ratio(multipass, rsz_conf_chan);
++	rsz_config_ratio(multipass, rsz_conf_chan);
++	rsz_hardware_setup(rsz_conf_chan);
++	return 0;
++}
++
++/**
++ * rsz_copy_data - Copy data
++ * @params: Structure containing the Resizer Wrapper parameters
++ *
++ * Copy data
++ **/
++static void rsz_copy_data(struct rsz_mult *multipass, struct rsz_params *params)
++{
++	int i;
++	multipass->in_hsize = params->in_hsize;
++	multipass->in_vsize = params->in_vsize;
++	multipass->out_hsize = params->out_hsize;
++	multipass->out_vsize = params->out_vsize;
++	multipass->end_hsize = params->out_hsize;
++	multipass->end_vsize = params->out_vsize;
++	multipass->in_pitch = params->in_pitch;
++	multipass->out_pitch = params->out_pitch;
++	multipass->hstph = params->hstph;
++	multipass->vstph = params->vstph;
++	multipass->inptyp = params->inptyp;
++	multipass->pix_fmt = params->pix_fmt;
++	multipass->cbilin = params->cbilin;
++
++	for (i = 0; i < 32; i++) {
++		multipass->tap4filt_coeffs[i] = params->tap4filt_coeffs[i];
++		multipass->tap7filt_coeffs[i] = params->tap7filt_coeffs[i];
++	}
++}
++
++/**
++ * rsz_set_params - Set parameters for resizer wrapper
++ * @params: Structure containing the Resizer Wrapper parameters
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Used to set the parameters of the Resizer hardware, including input and
++ * output image size, horizontal and vertical poly-phase filter coefficients,
++ * luma enchancement filter coefficients, etc.
++ **/
++static int rsz_set_params(struct rsz_mult *multipass, struct rsz_params *params,
++					struct channel_config *rsz_conf_chan)
++{
++	int mul = 1;
++	if ((params->yenh_params.type < 0) || (params->yenh_params.type > 2)) {
++		dev_err(rsz_device, "rsz_set_params: Wrong yenh type\n");
++		return -EINVAL;
++	}
++	if ((params->in_vsize <= 0) || (params->in_hsize <= 0) ||
++			(params->out_vsize <= 0) || (params->out_hsize <= 0) ||
++			(params->in_pitch <= 0) || (params->out_pitch <= 0)) {
++		dev_err(rsz_device, "rsz_set_params: Invalid size params\n");
++		return -EINVAL;
++	}
++	if ((params->inptyp != RSZ_INTYPE_YCBCR422_16BIT) &&
++			(params->inptyp != RSZ_INTYPE_PLANAR_8BIT)) {
++		dev_err(rsz_device, "rsz_set_params: Invalid input type\n");
++		return -EINVAL;
++	}
++	if ((params->pix_fmt != RSZ_PIX_FMT_UYVY) &&
++			(params->pix_fmt != RSZ_PIX_FMT_YUYV)) {
++		dev_err(rsz_device, "rsz_set_params: Invalid pixel format\n");
++		return -EINVAL;
++	}
++	if (params->inptyp == RSZ_INTYPE_YCBCR422_16BIT)
++		mul = 2;
++	else
++		mul = 1;
++	if (params->in_pitch < (params->in_hsize * mul)) {
++		dev_err(rsz_device, "rsz_set_params: Pitch is incorrect\n");
++		return -EINVAL;
++	}
++	if (params->out_pitch < (params->out_hsize * mul)) {
++		dev_err(rsz_device, "rsz_set_params: Out pitch cannot be less"
++					" than out hsize\n");
++		return -EINVAL;
++	}
++	/* Output H size should be even */
++	if ((params->out_hsize % PIXEL_EVEN) != 0) {
++		dev_err(rsz_device, "rsz_set_params: Output H size should"
++					" be even\n");
++		return -EINVAL;
++	}
++	if (params->horz_starting_pixel < 0) {
++		dev_err(rsz_device, "rsz_set_params: Horz start pixel cannot"
++					" be less than zero\n");
++		return -EINVAL;
++	}
++
++	rsz_copy_data(multipass, params);
++	if (0 != rsz_set_ratio(multipass, rsz_conf_chan))
++		goto err_einval;
++
++	if (params->yenh_params.type) {
++		if ((multipass->num_htap && multipass->out_hsize >
++				1280) ||
++				(!multipass->num_htap && multipass->out_hsize >
++				640))
++			goto err_einval;
++	}
++
++	if (INPUT_RAM)
++		params->vert_starting_pixel = 0;
++
++	rsz_conf_chan->register_config.rsz_in_start =
++						(params->vert_starting_pixel
++						<< ISPRSZ_IN_SIZE_VERT_SHIFT)
++						& ISPRSZ_IN_SIZE_VERT_MASK;
++
++	if (params->inptyp == RSZ_INTYPE_PLANAR_8BIT) {
++		if (params->horz_starting_pixel > MAX_HORZ_PIXEL_8BIT)
++			goto err_einval;
++	}
++	if (params->inptyp == RSZ_INTYPE_YCBCR422_16BIT) {
++		if (params->horz_starting_pixel > MAX_HORZ_PIXEL_16BIT)
++			goto err_einval;
++	}
++
++	rsz_conf_chan->register_config.rsz_in_start |=
++						params->horz_starting_pixel
++						& ISPRSZ_IN_START_HORZ_ST_MASK;
++
++	rsz_conf_chan->register_config.rsz_yehn =
++						(params->yenh_params.type
++						<< ISPRSZ_YENH_ALGO_SHIFT)
++						& ISPRSZ_YENH_ALGO_MASK;
++
++	if (params->yenh_params.type) {
++		rsz_conf_chan->register_config.rsz_yehn |=
++						params->yenh_params.core
++						& ISPRSZ_YENH_CORE_MASK;
++
++		rsz_conf_chan->register_config.rsz_yehn |=
++						(params->yenh_params.gain
++						<< ISPRSZ_YENH_GAIN_SHIFT)
++						& ISPRSZ_YENH_GAIN_MASK;
++
++		rsz_conf_chan->register_config.rsz_yehn |=
++						(params->yenh_params.slop
++						<< ISPRSZ_YENH_SLOP_SHIFT)
++						& ISPRSZ_YENH_SLOP_MASK;
++	}
++
++	rsz_config_ratio(multipass, rsz_conf_chan);
++
++	rsz_conf_chan->config_state = STATE_CONFIGURED;
++
++	return 0;
++err_einval:
++	return -EINVAL;
++}
++
++/**
++ * rsz_set_ratio - Set ratio
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Returns 0 if successful, -EINVAL if invalid output size, upscaling ratio is
++ * being requested, or other ratio configuration value is out of bounds
++ **/
++static int rsz_set_ratio(struct rsz_mult *multipass,
++				struct channel_config *rsz_conf_chan)
++{
++	int alignment = 0;
++
++	rsz_conf_chan->register_config.rsz_cnt = 0;
++
++	if ((multipass->out_hsize > MAX_IMAGE_WIDTH) ||
++			(multipass->out_vsize > MAX_IMAGE_WIDTH)) {
++		dev_err(rsz_device, "Invalid output size!");
++		goto err_einval;
++	}
++	if (multipass->cbilin) {
++		rsz_conf_chan->register_config.rsz_cnt =
++				BITSET(rsz_conf_chan->register_config.rsz_cnt,
++				SET_BIT_CBLIN);
++	}
++	if (INPUT_RAM) {
++		rsz_conf_chan->register_config.rsz_cnt =
++				BITSET(rsz_conf_chan->register_config.rsz_cnt,
++				SET_BIT_INPUTRAM);
++	}
++	if (multipass->inptyp == RSZ_INTYPE_PLANAR_8BIT) {
++		rsz_conf_chan->register_config.rsz_cnt =
++				BITSET(rsz_conf_chan->register_config.rsz_cnt,
++				SET_BIT_INPTYP);
++	} else {
++		rsz_conf_chan->register_config.rsz_cnt =
++				BITRESET(rsz_conf_chan->register_config.
++				rsz_cnt, SET_BIT_INPTYP);
++
++		if (multipass->pix_fmt == RSZ_PIX_FMT_UYVY) {
++			rsz_conf_chan->register_config.rsz_cnt =
++				BITRESET(rsz_conf_chan->register_config.
++				rsz_cnt, SET_BIT_YCPOS);
++		} else if (multipass->pix_fmt == RSZ_PIX_FMT_YUYV) {
++			rsz_conf_chan->register_config.rsz_cnt =
++					BITSET(rsz_conf_chan->register_config.
++					rsz_cnt, SET_BIT_YCPOS);
++		}
++
++	}
++	multipass->vrsz =
++		(multipass->in_vsize * RATIO_MULTIPLIER) / multipass->out_vsize;
++	multipass->hrsz =
++		(multipass->in_hsize * RATIO_MULTIPLIER) / multipass->out_hsize;
++	if (UP_RSZ_RATIO > multipass->vrsz || UP_RSZ_RATIO > multipass->hrsz) {
++		dev_err(rsz_device, "Upscaling ratio not supported!");
++		goto err_einval;
++	}
++	multipass->vrsz = (multipass->in_vsize - NUM_D2TAPS) * RATIO_MULTIPLIER
++						/ (multipass->out_vsize - 1);
++	multipass->hrsz = ((multipass->in_hsize - NUM_D2TAPS)
++						* RATIO_MULTIPLIER) /
++						(multipass->out_hsize - 1);
++
++	if (multipass->hrsz <= 512) {
++		multipass->hrsz = (multipass->in_hsize - NUM_TAPS)
++						* RATIO_MULTIPLIER
++						/ (multipass->out_hsize - 1);
++		if (multipass->hrsz < 64)
++			multipass->hrsz = 64;
++		if (multipass->hrsz > 512)
++			multipass->hrsz = 512;
++		if (multipass->hstph > NUM_PHASES)
++			goto err_einval;
++		multipass->num_htap = 1;
++	} else if (multipass->hrsz >= 513 && multipass->hrsz <= 1024) {
++		if (multipass->hstph > NUM_D2PH)
++			goto err_einval;
++		multipass->num_htap = 0;
++	}
++
++	if (multipass->vrsz <= 512) {
++		multipass->vrsz = (multipass->in_vsize - NUM_TAPS)
++						* RATIO_MULTIPLIER
++						/ (multipass->out_vsize - 1);
++		if (multipass->vrsz < 64)
++			multipass->vrsz = 64;
++		if (multipass->vrsz > 512)
++			multipass->vrsz = 512;
++		if (multipass->vstph > NUM_PHASES)
++			goto err_einval;
++		multipass->num_vtap = 1;
++	} else if (multipass->vrsz >= 513 && multipass->vrsz <= 1024) {
++		if (multipass->vstph > NUM_D2PH)
++			goto err_einval;
++		multipass->num_vtap = 0;
++	}
++
++	if ((multipass->in_pitch) % ALIGN32) {
++		dev_err(rsz_device, "Invalid input pitch: %d \n",
++							multipass->in_pitch);
++		goto err_einval;
++	}
++	if ((multipass->out_pitch) % ALIGN32) {
++		dev_err(rsz_device, "Invalid output pitch %d \n",
++							multipass->out_pitch);
++		goto err_einval;
++	}
++
++	if (multipass->vrsz < 256 &&
++			(multipass->in_vsize < multipass->out_vsize)) {
++		if (multipass->inptyp == RSZ_INTYPE_PLANAR_8BIT)
++			alignment = ALIGNMENT;
++		else if (multipass->inptyp == RSZ_INTYPE_YCBCR422_16BIT)
++			alignment = (ALIGNMENT / 2);
++		else
++			dev_err(rsz_device, "Invalid input type\n");
++
++		if (!(((multipass->out_hsize % PIXEL_EVEN) == 0)
++				&& (multipass->out_hsize % alignment) == 0)) {
++			dev_err(rsz_device, "wrong hsize\n");
++			goto err_einval;
++		}
++	}
++	if (multipass->hrsz >= 64 && multipass->hrsz <= 1024) {
++		if (multipass->out_hsize > MAX_IMAGE_WIDTH) {
++			dev_err(rsz_device, "wrong width\n");
++			goto err_einval;
++		}
++		multipass->active = 0;
++
++	} else if (multipass->hrsz > 1024) {
++		if (multipass->out_hsize > MAX_IMAGE_WIDTH) {
++			dev_err(rsz_device, "wrong width\n");
++			goto err_einval;
++		}
++		if (multipass->hstph > NUM_D2PH)
++			goto err_einval;
++		multipass->num_htap = 0;
++		multipass->out_hsize = multipass->in_hsize * 256 / 1024;
++		if (multipass->out_hsize % ALIGN32) {
++			multipass->out_hsize +=
++				abs((multipass->out_hsize % ALIGN32) - ALIGN32);
++		}
++		multipass->out_pitch = ((multipass->inptyp) ?
++						multipass->out_hsize :
++						(multipass->out_hsize * 2));
++		multipass->hrsz = ((multipass->in_hsize - NUM_D2TAPS)
++						* RATIO_MULTIPLIER)
++						/ (multipass->out_hsize - 1);
++		multipass->active = 1;
++
++	}
++
++	if (multipass->vrsz > 1024) {
++		if (multipass->out_vsize > MAX_IMAGE_WIDTH_HIGH) {
++			dev_err(rsz_device, "wrong width\n");
++			goto err_einval;
++		}
++
++		multipass->out_vsize = multipass->in_vsize * 256 / 1024;
++		multipass->vrsz = ((multipass->in_vsize - NUM_D2TAPS)
++						* RATIO_MULTIPLIER)
++						/ (multipass->out_vsize - 1);
++		multipass->active = 1;
++		multipass->num_vtap = 0;
++
++	}
++	rsz_conf_chan->register_config.rsz_out_size =
++						multipass->out_hsize
++						& ISPRSZ_OUT_SIZE_HORZ_MASK;
++
++	rsz_conf_chan->register_config.rsz_out_size |=
++						(multipass->out_vsize
++						<< ISPRSZ_OUT_SIZE_VERT_SHIFT)
++						& ISPRSZ_OUT_SIZE_VERT_MASK;
++
++	rsz_conf_chan->register_config.rsz_sdr_inoff =
++						multipass->in_pitch
++						& ISPRSZ_SDR_INOFF_OFFSET_MASK;
++
++	rsz_conf_chan->register_config.rsz_sdr_outoff =
++					multipass->out_pitch
++					& ISPRSZ_SDR_OUTOFF_OFFSET_MASK;
++
++	if (multipass->hrsz >= 64 && multipass->hrsz <= 512) {
++		if (multipass->hstph > NUM_PHASES)
++			goto err_einval;
++	} else if (multipass->hrsz >= 64 && multipass->hrsz <= 512) {
++		if (multipass->hstph > NUM_D2PH)
++			goto err_einval;
++	}
++
++	rsz_conf_chan->register_config.rsz_cnt |=
++						(multipass->hstph
++						<< ISPRSZ_CNT_HSTPH_SHIFT)
++						& ISPRSZ_CNT_HSTPH_MASK;
++
++	if (multipass->vrsz >= 64 && multipass->hrsz <= 512) {
++		if (multipass->vstph > NUM_PHASES)
++			goto err_einval;
++	} else if (multipass->vrsz >= 64 && multipass->vrsz <= 512) {
++		if (multipass->vstph > NUM_D2PH)
++			goto err_einval;
++	}
++
++	rsz_conf_chan->register_config.rsz_cnt |=
++						(multipass->vstph
++						<< ISPRSZ_CNT_VSTPH_SHIFT)
++						& ISPRSZ_CNT_VSTPH_MASK;
++
++	rsz_conf_chan->register_config.rsz_cnt |=
++						(multipass->hrsz - 1)
++						& ISPRSZ_CNT_HRSZ_MASK;
++
++	rsz_conf_chan->register_config.rsz_cnt |=
++						((multipass->vrsz - 1)
++						<< ISPRSZ_CNT_VRSZ_SHIFT)
++						& ISPRSZ_CNT_VRSZ_MASK;
++
++	return 0;
++err_einval:
++	return -EINVAL;
++}
++
++/**
++ * rsz_config_ratio - Configure ratio
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Configure ratio
++ **/
++static void rsz_config_ratio(struct rsz_mult *multipass,
++				struct channel_config *rsz_conf_chan)
++{
++	int hsize;
++	int vsize;
++	int coeffcounter;
++
++	if (multipass->hrsz <= 512) {
++		hsize = ((32 * multipass->hstph + (multipass->out_hsize - 1)
++					* multipass->hrsz + 16) >> 8) + 7;
++	} else {
++		hsize = ((64 * multipass->hstph + (multipass->out_hsize - 1)
++					* multipass->hrsz + 32) >> 8) + 7;
++	}
++	if (multipass->vrsz <= 512) {
++		vsize = ((32 * multipass->vstph + (multipass->out_vsize - 1)
++					* multipass->vrsz + 16) >> 8) + 4;
++	} else {
++		vsize = ((64 * multipass->vstph + (multipass->out_vsize - 1)
++					* multipass->vrsz + 32) >> 8) + 7;
++	}
++	rsz_conf_chan->register_config.rsz_in_size = hsize;
++
++	rsz_conf_chan->register_config.rsz_in_size |=
++					((vsize << ISPRSZ_IN_SIZE_VERT_SHIFT)
++					& ISPRSZ_IN_SIZE_VERT_MASK);
++
++	for (coeffcounter = 0; coeffcounter < MAX_COEF_COUNTER;
++							coeffcounter++) {
++		if (multipass->num_htap) {
++			rsz_conf_chan->register_config.
++					rsz_coeff_horz[coeffcounter] =
++					(multipass->tap4filt_coeffs[2
++					* coeffcounter]
++					& ISPRSZ_HFILT10_COEF0_MASK);
++			rsz_conf_chan->register_config.
++					rsz_coeff_horz[coeffcounter] |=
++					((multipass->tap4filt_coeffs[2
++					* coeffcounter + 1]
++					<< ISPRSZ_HFILT10_COEF1_SHIFT)
++					& ISPRSZ_HFILT10_COEF1_MASK);
++		} else {
++			rsz_conf_chan->register_config.
++					rsz_coeff_horz[coeffcounter] =
++					(multipass->tap7filt_coeffs[2
++					* coeffcounter]
++					& ISPRSZ_HFILT10_COEF0_MASK);
++
++			rsz_conf_chan->register_config.
++					rsz_coeff_horz[coeffcounter] |=
++					((multipass->tap7filt_coeffs[2
++					* coeffcounter + 1]
++					<< ISPRSZ_HFILT10_COEF1_SHIFT)
++					& ISPRSZ_HFILT10_COEF1_MASK);
++		}
++
++		if (multipass->num_vtap) {
++			rsz_conf_chan->register_config.
++					rsz_coeff_vert[coeffcounter] =
++					(multipass->tap4filt_coeffs[2
++					* coeffcounter]
++					& ISPRSZ_VFILT10_COEF0_MASK);
++
++			rsz_conf_chan->register_config.
++					rsz_coeff_vert[coeffcounter] |=
++					((multipass->tap4filt_coeffs[2
++					* coeffcounter + 1]
++					<< ISPRSZ_VFILT10_COEF1_SHIFT) &
++					ISPRSZ_VFILT10_COEF1_MASK);
++		} else {
++			rsz_conf_chan->register_config.
++					rsz_coeff_vert[coeffcounter] =
++					(multipass->tap7filt_coeffs[2
++					* coeffcounter]
++					& ISPRSZ_VFILT10_COEF0_MASK);
++			rsz_conf_chan->register_config.
++					rsz_coeff_vert[coeffcounter] |=
++					((multipass->tap7filt_coeffs[2
++					* coeffcounter + 1]
++					<< ISPRSZ_VFILT10_COEF1_SHIFT)
++					& ISPRSZ_VFILT10_COEF1_MASK);
++		}
++	}
++}
++
++/**
++ * rsz_get_params - Gets the parameter values
++ * @params: Structure containing the Resizer Wrapper parameters
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Used to get the Resizer hardware settings associated with the
++ * current logical channel represented by fd.
++ **/
++static int rsz_get_params(struct rsz_params *params,
++					struct channel_config *rsz_conf_chan)
++{
++	int coeffcounter;
++
++	if (rsz_conf_chan->config_state) {
++		dev_err(rsz_device, "state not configured\n");
++		return -EINVAL;
++	}
++
++	params->in_hsize = rsz_conf_chan->register_config.rsz_in_size
++					& ISPRSZ_IN_SIZE_HORZ_MASK;
++	params->in_vsize = (rsz_conf_chan->register_config.rsz_in_size
++					& ISPRSZ_IN_SIZE_VERT_MASK)
++					>> ISPRSZ_IN_SIZE_VERT_SHIFT;
++
++	params->in_pitch = rsz_conf_chan->register_config.rsz_sdr_inoff
++					& ISPRSZ_SDR_INOFF_OFFSET_MASK;
++
++	params->out_hsize = rsz_conf_chan->register_config.rsz_out_size
++					& ISPRSZ_OUT_SIZE_HORZ_MASK;
++
++	params->out_vsize = (rsz_conf_chan->register_config.rsz_out_size
++					& ISPRSZ_OUT_SIZE_VERT_MASK)
++					>> ISPRSZ_OUT_SIZE_VERT_SHIFT;
++
++	params->out_pitch = rsz_conf_chan->register_config.rsz_sdr_outoff
++					& ISPRSZ_SDR_OUTOFF_OFFSET_MASK;
++
++	params->cbilin = (rsz_conf_chan->register_config.rsz_cnt
++					& SET_BIT_CBLIN) >> SET_BIT_CBLIN;
++
++	params->inptyp = (rsz_conf_chan->register_config.rsz_cnt
++					& ISPRSZ_CNT_INPTYP_MASK)
++					>> SET_BIT_INPTYP;
++	params->horz_starting_pixel = ((rsz_conf_chan->register_config.
++					rsz_in_start
++					& ISPRSZ_IN_START_HORZ_ST_MASK));
++	params->vert_starting_pixel = ((rsz_conf_chan->register_config.
++					rsz_in_start
++					& ISPRSZ_IN_START_VERT_ST_MASK)
++					>> ISPRSZ_IN_START_VERT_ST_SHIFT);
++
++	params->hstph = ((rsz_conf_chan->register_config.rsz_cnt
++					& ISPRSZ_CNT_HSTPH_MASK
++					>> ISPRSZ_CNT_HSTPH_SHIFT));
++	params->vstph = ((rsz_conf_chan->register_config.rsz_cnt
++					& ISPRSZ_CNT_VSTPH_MASK
++					>> ISPRSZ_CNT_VSTPH_SHIFT));
++
++	for (coeffcounter = 0; coeffcounter < MAX_COEF_COUNTER;
++							coeffcounter++) {
++		params->tap4filt_coeffs[2 * coeffcounter] =
++					rsz_conf_chan->register_config.
++					rsz_coeff_horz[coeffcounter]
++					& ISPRSZ_HFILT10_COEF0_MASK;
++
++		params->tap4filt_coeffs[2 * coeffcounter + 1] =
++					(rsz_conf_chan->register_config.
++					rsz_coeff_horz[coeffcounter]
++					& ISPRSZ_HFILT10_COEF1_MASK)
++					>> ISPRSZ_HFILT10_COEF1_SHIFT;
++
++		params->tap7filt_coeffs[2 * coeffcounter] =
++					rsz_conf_chan->register_config.
++					rsz_coeff_vert[coeffcounter]
++					& ISPRSZ_VFILT10_COEF0_MASK;
++
++		params->tap7filt_coeffs[2 * coeffcounter + 1] =
++					(rsz_conf_chan->register_config.
++					rsz_coeff_vert[coeffcounter]
++					& ISPRSZ_VFILT10_COEF1_MASK)
++					>> ISPRSZ_VFILT10_COEF1_SHIFT;
++
++	}
++
++	params->yenh_params.type = (rsz_conf_chan->register_config.rsz_yehn
++					& ISPRSZ_YENH_ALGO_MASK)
++					>> ISPRSZ_YENH_ALGO_SHIFT;
++
++	params->yenh_params.core = rsz_conf_chan->register_config.rsz_yehn
++					& ISPRSZ_YENH_CORE_MASK;
++
++	params->yenh_params.gain = (rsz_conf_chan->register_config.rsz_yehn
++					& ISPRSZ_YENH_GAIN_MASK)
++					>> ISPRSZ_YENH_GAIN_SHIFT;
++
++	params->yenh_params.slop = (rsz_conf_chan->register_config.rsz_yehn
++					& ISPRSZ_YENH_SLOP_MASK)
++					>> ISPRSZ_YENH_SLOP_SHIFT;
++
++	params->pix_fmt = ((rsz_conf_chan->register_config.rsz_cnt
++					& ISPRSZ_CNT_PIXFMT_MASK)
++					>> SET_BIT_YCPOS);
++
++	if (params->pix_fmt)
++		params->pix_fmt = RSZ_PIX_FMT_UYVY;
++	else
++		params->pix_fmt = RSZ_PIX_FMT_YUYV;
++
++	return 0;
++}
++
++/**
++ * rsz_calculate_crop - Calculate Crop values
++ * @rsz_conf_chan: Structure containing channel configuration
++ * @cropsize: Structure containing crop parameters
++ *
++ * Calculate Crop values
++ **/
++static void rsz_calculate_crop(struct channel_config *rsz_conf_chan,
++						struct rsz_cropsize *cropsize)
++{
++	int luma_enable;
++
++	cropsize->hcrop = 0;
++	cropsize->vcrop = 0;
++
++	luma_enable = (rsz_conf_chan->register_config.rsz_yehn
++						& ISPRSZ_YENH_ALGO_MASK)
++						>> ISPRSZ_YENH_ALGO_SHIFT;
++
++	if (luma_enable)
++		cropsize->hcrop += 2;
++}
++
++/**
++ * rsz_vbq_release - Videobuffer queue release
++ * @q: Structure containing the videobuffer queue file handle, and device
++ *     structure which contains the actual configuration.
++ * @vb: Structure containing the videobuffer used for resizer processing.
++ **/
++static void rsz_vbq_release(struct videobuf_queue *q,
++						struct videobuf_buffer *vb)
++{
++	int i;
++	struct rsz_fh *fh = q->priv_data;
++
++	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
++		struct videobuf_dmabuf *dma = NULL;
++		if (!q->bufs[i])
++			continue;
++		if (q->bufs[i]->memory != V4L2_MEMORY_MMAP)
++			continue;
++		dma = videobuf_to_dma(q->bufs[i]);
++		videobuf_dma_unmap(q, dma);
++		videobuf_dma_free(dma);
++	}
++
++	ispmmu_unmap(fh->isp_addr_read);
++	ispmmu_unmap(fh->isp_addr_write);
++	fh->isp_addr_read = 0;
++	fh->isp_addr_write = 0;
++	spin_lock(&fh->vbq_lock);
++	vb->state = VIDEOBUF_NEEDS_INIT;
++	spin_unlock(&fh->vbq_lock);
++
++}
++
++/**
++ * rsz_vbq_setup - Sets up the videobuffer size and validates count.
++ * @q: Structure containing the videobuffer queue file handle, and device
++ *     structure which contains the actual configuration.
++ * @cnt: Number of buffers requested
++ * @size: Size in bytes of the buffer used for previewing
++ *
++ * Always returns 0.
++ **/
++static int rsz_vbq_setup(struct videobuf_queue *q, unsigned int *cnt,
++							unsigned int *size)
++{
++	struct rsz_fh *fh = q->priv_data;
++	struct rsz_mult *multipass = fh->multipass;
++	u32 insize, outsize;
++
++	spin_lock(&fh->vbq_lock);
++	if (*cnt <= 0)
++		*cnt = VIDEO_MAX_FRAME;
++
++	if (*cnt > VIDEO_MAX_FRAME)
++		*cnt = VIDEO_MAX_FRAME;
++
++	outsize = multipass->out_pitch * multipass->out_vsize;
++	insize = multipass->in_pitch * multipass->in_vsize;
++	if (*cnt == 1 && (outsize > insize)) {
++		dev_err(rsz_device, "2 buffers are required for Upscaling "
++								"mode\n");
++		goto err_einval;
++	}
++	if (!fh->params->in_hsize || !fh->params->in_vsize) {
++		dev_err(rsz_device, "Can't setup buffer size\n");
++		goto err_einval;
++	} else {
++		if (outsize > insize)
++			*size = outsize;
++		else
++			*size = insize;
++
++		fh->rsz_bufsize = *size;
++	}
++	spin_unlock(&fh->vbq_lock);
++
++	return 0;
++err_einval:
++	spin_unlock(&fh->vbq_lock);
++	return -EINVAL;
++}
++
++/**
++ * rsz_vbq_prepare - Videobuffer is prepared and mmapped.
++ * @q: Structure containing the videobuffer queue file handle, and device
++ *     structure which contains the actual configuration.
++ * @vb: Structure containing the videobuffer used for resizer processing.
++ * @field: Type of field to set in videobuffer device.
++ *
++ * Returns 0 if successful, or -EINVAL if buffer couldn't get allocated, or
++ * -EIO if the ISP MMU mapping fails
++ **/
++static int rsz_vbq_prepare(struct videobuf_queue *q,
++						struct videobuf_buffer *vb,
++						enum v4l2_field field)
++{
++	struct rsz_fh *fh = q->priv_data;
++	struct channel_config *rsz_conf_chan = fh->config;
++	struct rsz_mult *multipass = fh->multipass;
++	int err = 0;
++	unsigned int isp_addr, insize, outsize;
++	struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
++
++	spin_lock(&fh->vbq_lock);
++	if (vb->baddr) {
++		vb->size = fh->rsz_bufsize;
++		vb->bsize = fh->rsz_bufsize;
++	} else {
++		spin_unlock(&fh->vbq_lock);
++		dev_err(rsz_device, "No user buffer allocated\n");
++		goto out;
++	}
++	if (vb->i) {
++		vb->width = fh->params->out_hsize;
++		vb->height = fh->params->out_vsize;
++	} else {
++		vb->width = fh->params->in_hsize;
++		vb->height = fh->params->in_vsize;
++	}
++
++	vb->field = field;
++	spin_unlock(&fh->vbq_lock);
++
++	if (vb->state == VIDEOBUF_NEEDS_INIT) {
++		err = videobuf_iolock(q, vb, NULL);
++		if (!err) {
++			isp_addr = ispmmu_map_sg(dma->sglist, dma->sglen);
++			if (!isp_addr)
++				err = -EIO;
++			else {
++				if (vb->i) {
++					rsz_conf_chan->register_config.
++							rsz_sdr_outadd
++							= isp_addr;
++					fh->isp_addr_write = isp_addr;
++					rsz_conf_chan->output_buf_index = vb->i;
++				} else {
++					rsz_conf_chan->register_config.
++							rsz_sdr_inadd
++							= isp_addr;
++					rsz_conf_chan->input_buf_index = vb->i;
++					outsize = multipass->out_pitch *
++							multipass->out_vsize;
++					insize = multipass->in_pitch *
++							multipass->in_vsize;
++					if (outsize < insize) {
++						rsz_conf_chan->register_config.
++								rsz_sdr_outadd
++								= isp_addr;
++						rsz_conf_chan->
++							output_buf_index =
++							vb->i;
++					}
++
++					fh->isp_addr_read = isp_addr;
++				}
++			}
++		}
++
++	}
++
++	if (!err) {
++		spin_lock(&fh->vbq_lock);
++		vb->state = VIDEOBUF_PREPARED;
++		spin_unlock(&fh->vbq_lock);
++		flush_cache_user_range(NULL, vb->baddr, (vb->baddr
++								+ vb->bsize));
++	} else
++		rsz_vbq_release(q, vb);
++
++out:
++	return err;
++}
++
++static void rsz_vbq_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
++{
++	return;
++}
++
++/**
++ * rsz_open - Initializes and opens the Resizer Wrapper
++ * @inode: Inode structure associated with the Resizer Wrapper
++ * @filp: File structure associated with the Resizer Wrapper
++ *
++ * Returns 0 if successful, -EBUSY if its already opened or the ISP module is
++ * not available, or -ENOMEM if its unable to allocate the device in kernel
++ * space memory.
++ **/
++static int rsz_open(struct inode *inode, struct file *filp)
++{
++	int ret = 0;
++	struct channel_config *rsz_conf_chan;
++	struct rsz_fh *fh;
++	struct device_params *device = device_config;
++	struct rsz_params *params;
++	struct rsz_mult *multipass;
++
++	if ((filp->f_flags & O_NONBLOCK) == O_NONBLOCK) {
++		printk(KERN_DEBUG "omap-resizer: Device is opened in "
++					"non blocking mode\n");
++	} else {
++		printk(KERN_DEBUG "omap-resizer: Device is opened in blocking "
++					"mode\n");
++	}
++	fh = kzalloc(sizeof(struct rsz_fh), GFP_KERNEL);
++	if (NULL == fh)
++		return -ENOMEM;
++
++	isp_get();
++
++	rsz_conf_chan = kzalloc(sizeof(struct channel_config), GFP_KERNEL);
++	if (rsz_conf_chan == NULL) {
++		dev_err(rsz_device, "\n cannot allocate memory to config");
++		ret = -ENOMEM;
++		goto err_enomem0;
++	}
++	params = kzalloc(sizeof(struct rsz_params), GFP_KERNEL);
++	if (params == NULL) {
++		dev_err(rsz_device, "\n cannot allocate memory to params");
++		ret = -ENOMEM;
++		goto err_enomem1;
++	}
++	multipass = kzalloc(sizeof(struct rsz_mult), GFP_KERNEL);
++	if (multipass == NULL) {
++		dev_err(rsz_device, "\n cannot allocate memory to multipass");
++		ret = -ENOMEM;
++		goto err_enomem2;
++	}
++
++	fh->multipass = multipass;
++	fh->params = params;
++	fh->config = rsz_conf_chan;
++
++	if (mutex_lock_interruptible(&device->reszwrap_mutex)) {
++		ret = -EINTR;
++		goto err_enomem2;
++	}
++	device->opened++;
++	mutex_unlock(&device->reszwrap_mutex);
++
++	rsz_conf_chan->config_state = STATE_NOT_CONFIGURED;
++	rsz_conf_chan->status = CHANNEL_FREE;
++
++	filp->private_data = fh;
++	fh->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	fh->device = device;
++
++	videobuf_queue_sg_init(&fh->vbq, &device->vbq_ops, NULL,
++					&fh->vbq_lock, fh->type,
++					V4L2_FIELD_NONE,
++					sizeof(struct videobuf_buffer), fh);
++
++	spin_lock_init(&fh->vbq_lock);
++	mutex_init(&rsz_conf_chan->chanprotection_mutex);
++
++	return 0;
++err_enomem2:
++	kfree(params);
++err_enomem1:
++	kfree(rsz_conf_chan);
++err_enomem0:
++	kfree(fh);
++	return ret;
++}
++
++/**
++ * rsz_release - Releases Resizer Wrapper and frees up allocated memory
++ * @inode: Inode structure associated with the Resizer Wrapper
++ * @filp: File structure associated with the Resizer Wrapper
++ *
++ * Returns 0 if successful, or -EBUSY if channel is being used.
++ **/
++static int rsz_release(struct inode *inode, struct file *filp)
++{
++	u32 timeout = 0;
++	struct rsz_fh *fh = filp->private_data;
++	struct channel_config *rsz_conf_chan = fh->config;
++	struct rsz_params *params = fh->params;
++	struct rsz_mult *multipass = fh->multipass;
++	struct videobuf_queue *q = &fh->vbq;
++
++	while ((rsz_conf_chan->status != CHANNEL_FREE) && (timeout < 20)) {
++		timeout++;
++		schedule();
++	}
++	if (mutex_lock_interruptible(&device_config->reszwrap_mutex))
++		return -EINTR;
++	device_config->opened--;
++	mutex_unlock(&device_config->reszwrap_mutex);
++	/* This will Free memory allocated to the buffers,
++	 * and flushes the queue
++	 */
++	videobuf_queue_cancel(q);
++	fh->params = NULL;
++	fh->config = NULL;
++
++	fh->rsz_bufsize = 0;
++	filp->private_data = NULL;
++
++	kfree(rsz_conf_chan);
++	kfree(params);
++	kfree(multipass);
++	kfree(fh);
++
++	isp_put();
++
++	return 0;
++}
++
++/**
++ * rsz_mmap - Memory maps the Resizer Wrapper module.
++ * @file: File structure associated with the Resizer Wrapper
++ * @vma: Virtual memory area structure.
++ *
++ * Returns 0 if successful, or returned value by the videobuf_mmap_mapper()
++ * function.
++ **/
++static int rsz_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	struct rsz_fh *fh = file->private_data;
++
++	return videobuf_mmap_mapper(&fh->vbq, vma);
++}
++
++/**
++ * rsz_ioctl - I/O control function for Resizer Wrapper
++ * @inode: Inode structure associated with the Resizer Wrapper.
++ * @file: File structure associated with the Resizer Wrapper.
++ * @cmd: Type of command to execute.
++ * @arg: Argument to send to requested command.
++ *
++ * Returns 0 if successful, -EBUSY if channel is being used, -1 if bad command
++ * passed or access is denied, -EFAULT if copy_from_user() or copy_to_user()
++ * fails, -EINVAL if parameter validation fails or parameter structure is not
++ * present.
++ **/
++static long rsz_unlocked_ioctl(struct file *file, unsigned int cmd,
++							unsigned long arg)
++{
++	int ret = 0;
++	struct rsz_fh *fh = file->private_data;
++	struct device_params *device = fh->device;
++	struct channel_config *rsz_conf_chan = fh->config;
++
++	if ((_IOC_TYPE(cmd) != RSZ_IOC_BASE)
++					|| (_IOC_NR(cmd) > RSZ_IOC_MAXNR)) {
++		dev_err(rsz_device, "Bad command value \n");
++		return -1;
++	}
++
++	if (_IOC_DIR(cmd) & _IOC_READ)
++		ret = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
++	else if (_IOC_DIR(cmd) & _IOC_WRITE)
++		ret = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
++
++	if (ret) {
++		dev_err(rsz_device, "Access denied\n");
++		return -1;
++	}
++
++	switch (cmd) {
++	case RSZ_REQBUF:
++	{
++		struct v4l2_requestbuffers req_buf;
++		if (copy_from_user(&req_buf, (struct v4l2_requestbuffers *)arg,
++					sizeof(struct v4l2_requestbuffers))) {
++			return -EFAULT;
++		}
++		if (mutex_lock_interruptible(&rsz_conf_chan->
++							chanprotection_mutex))
++			return -EINTR;
++		ret = videobuf_reqbufs(&fh->vbq, (void *)&req_buf);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		break;
++	}
++	case RSZ_QUERYBUF:
++	{
++		struct v4l2_buffer buf;
++		if (copy_from_user(&buf, (struct v4l2_buffer *)arg,
++						sizeof(struct v4l2_buffer))) {
++			return -EFAULT;
++		}
++		if (mutex_lock_interruptible(&rsz_conf_chan->
++							chanprotection_mutex))
++			return -EINTR;
++		ret = videobuf_querybuf(&fh->vbq, (void *)&buf);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		if (copy_to_user((struct v4l2_buffer *)arg, &buf,
++						sizeof(struct v4l2_buffer)))
++			return -EFAULT;
++		break;
++	}
++	case RSZ_QUEUEBUF:
++	{
++		struct v4l2_buffer buf;
++		if (copy_from_user(&buf, (struct v4l2_buffer *)arg,
++						sizeof(struct v4l2_buffer))) {
++			return -EFAULT;
++		}
++		if (mutex_lock_interruptible(&rsz_conf_chan->
++							chanprotection_mutex))
++			return -EINTR;
++		ret = videobuf_qbuf(&fh->vbq, (void *)&buf);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		break;
++	}
++	case RSZ_S_PARAM:
++	{
++		struct rsz_params *params = fh->params;
++		if (copy_from_user(params, (struct rsz_params *)arg,
++						sizeof(struct rsz_params))) {
++			return -EFAULT;
++		}
++		if (mutex_lock_interruptible(&rsz_conf_chan->
++							chanprotection_mutex))
++			return -EINTR;
++		ret = rsz_set_params(fh->multipass, params, rsz_conf_chan);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		break;
++	}
++	case RSZ_G_PARAM:
++		ret = rsz_get_params((struct rsz_params *)arg, rsz_conf_chan);
++		break;
++
++	case RSZ_G_STATUS:
++	{
++		struct rsz_status *status;
++		status = (struct rsz_status *)arg;
++		status->chan_busy = rsz_conf_chan->status;
++		status->hw_busy = ispresizer_busy();
++		status->src = INPUT_RAM;
++		break;
++	}
++	case RSZ_RESIZE:
++		if (file->f_flags & O_NONBLOCK) {
++			if (ispresizer_busy())
++				return -EBUSY;
++			else {
++				if (!mutex_trylock(&device->reszwrap_mutex))
++					return -EBUSY;
++			}
++		} else {
++			if (mutex_lock_interruptible(&device->reszwrap_mutex))
++				return -EINTR;
++		}
++		ret = rsz_start((int *)arg, fh);
++		mutex_unlock(&device->reszwrap_mutex);
++		break;
++	case RSZ_GET_CROPSIZE:
++		rsz_calculate_crop(rsz_conf_chan, (struct rsz_cropsize *)arg);
++		break;
++
++	default:
++		dev_err(rsz_device, "resizer_ioctl: Invalid Command Value");
++		return -EINVAL;
++	}
++
++	return (long)ret;
++}
++
++static struct file_operations rsz_fops = {
++	.owner = THIS_MODULE,
++	.open = rsz_open,
++	.release = rsz_release,
++	.mmap = rsz_mmap,
++	.unlocked_ioctl = rsz_unlocked_ioctl,
++};
++
++/**
++ * rsz_isr - Interrupt Service Routine for Resizer wrapper
++ * @status: ISP IRQ0STATUS register value
++ * @arg1: Currently not used
++ * @arg2: Currently not used
++ *
++ * Interrupt Service Routine for Resizer wrapper
++ **/
++static void rsz_isr(unsigned long status, isp_vbq_callback_ptr arg1, void *arg2)
++{
++
++	if ((status & RESZ_DONE) != RESZ_DONE)
++		return;
++
++	complete(&(device_config->compl_isr));
++
++}
++
++/**
++ * resizer_platform_release - Acts when Reference count is zero
++ * @device: Structure containing ISP resizer wrapper global information
++ *
++ * This is called when the reference count goes to zero.
++ **/
++static void resizer_platform_release(struct device *device)
++{
++}
++
++/**
++ * resizer_probe - Checks for device presence
++ * @device: Structure containing details of the current device.
++ *
++ * Always returns 0.
++ **/
++static int __init resizer_probe(struct platform_device *device)
++{
++	return 0;
++}
++
++/**
++ * resizer_remove - Handles the removal of the driver
++ * @omap_resizer_device: Structure containing details of the current device.
++ *
++ * Always returns 0.
++ **/
++static int resizer_remove(struct platform_device *omap_resizer_device)
++{
++	return 0;
++}
++
++static struct class *rsz_class;
++static struct cdev c_dev;
++static dev_t dev;
++static struct platform_device omap_resizer_device = {
++	.name = OMAP_REZR_NAME,
++	.id = 2,
++	.dev = {
++		.release = resizer_platform_release,}
++};
++
++static struct platform_driver omap_resizer_driver = {
++	.probe = resizer_probe,
++	.remove = resizer_remove,
++	.driver = {
++			.bus = &platform_bus_type,
++			.name = OMAP_REZR_NAME,
++	},
++};
++
++/**
++ * omap_rsz_init - Initialization of Resizer Wrapper
++ *
++ * Returns 0 if successful, -ENOMEM if could not allocate memory, -ENODEV if
++ * could not register the wrapper as a character device, or other errors if the
++ * device or driver can't register.
++ **/
++static int __init omap_rsz_init(void)
++{
++	int ret = 0;
++	struct device_params *device;
++	device = kzalloc(sizeof(struct device_params), GFP_KERNEL);
++	if (!device) {
++		dev_err(rsz_device, OMAP_REZR_NAME ": could not allocate "
++								"memory\n");
++		return -ENOMEM;
++	}
++
++	ret = alloc_chrdev_region(&dev, 0, 1, OMAP_REZR_NAME);
++	if (ret < 0) {
++		dev_err(rsz_device, OMAP_REZR_NAME ": intialization failed. "
++			"Could not allocate region "
++			"for character device\n");
++		kfree(device);
++		return -ENODEV;
++	}
++
++	/* Register the driver in the kernel */
++	/* Initialize of character device */
++	cdev_init(&c_dev, &rsz_fops);
++	c_dev.owner = THIS_MODULE;
++	c_dev.ops = &rsz_fops;
++
++	/* Addding character device */
++	ret = cdev_add(&c_dev, dev, 1);
++	if (ret) {
++		dev_err(rsz_device, OMAP_REZR_NAME ": Error adding "
++			"device - %d\n", ret);
++		goto fail2;
++	}
++	rsz_major = MAJOR(dev);
++
++	/* register driver as a platform driver */
++	ret = platform_driver_register(&omap_resizer_driver);
++	if (ret) {
++		dev_err(rsz_device, OMAP_REZR_NAME
++				": Failed to register platform driver!\n");
++		goto fail3;
++	}
++
++	/* Register the drive as a platform device */
++	ret = platform_device_register(&omap_resizer_device);
++	if (ret) {
++		dev_err(rsz_device, OMAP_REZR_NAME
++				": Failed to register platform device!\n");
++		goto fail4;
++	}
++
++	rsz_class = class_create(THIS_MODULE, OMAP_REZR_NAME);
++	if (!rsz_class) {
++		dev_err(rsz_device, OMAP_REZR_NAME
++			": Failed to create class!\n");
++		goto fail5;
++	}
++
++	/* make entry in the devfs */
++	rsz_device = device_create(rsz_class, rsz_device,
++						MKDEV(rsz_major, 0), NULL,
++						OMAP_REZR_NAME);
++	dev_dbg(rsz_device, OMAP_REZR_NAME ": Registered Resizer Wrapper\n");
++	device->opened = 0;
++
++	device->vbq_ops.buf_setup = rsz_vbq_setup;
++	device->vbq_ops.buf_prepare = rsz_vbq_prepare;
++	device->vbq_ops.buf_release = rsz_vbq_release;
++	device->vbq_ops.buf_queue = rsz_vbq_queue;
++	init_completion(&device->compl_isr);
++	mutex_init(&device->reszwrap_mutex);
++
++	device_config = device;
++	return 0;
++
++fail5:
++	platform_device_unregister(&omap_resizer_device);
++fail4:
++	platform_driver_unregister(&omap_resizer_driver);
++fail3:
++	cdev_del(&c_dev);
++fail2:
++	unregister_chrdev_region(dev, 1);
++	kfree(device);
++	return ret;
++}
++
++/**
++ * omap_rsz_exit - Close of Resizer Wrapper
++ **/
++void __exit omap_rsz_exit(void)
++{
++	device_destroy(rsz_class, dev);
++	class_destroy(rsz_class);
++	platform_device_unregister(&omap_resizer_device);
++	platform_driver_unregister(&omap_resizer_driver);
++	cdev_del(&c_dev);
++	unregister_chrdev_region(dev, 1);
++	kfree(device_config);
++}
++
++module_init(omap_rsz_init)
++module_exit(omap_rsz_exit)
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("OMAP ISP Resizer");
++MODULE_LICENSE("GPL");
+diff --git a/include/linux/omap_resizer.h b/include/linux/omap_resizer.h
+new file mode 100644
+index 0000000..5ac0c88
+--- /dev/null
++++ b/include/linux/omap_resizer.h
+@@ -0,0 +1,136 @@
++/*
++ * drivers/media/video/isp/omap_resizer.h
++ *
++ * Include file for Resizer module wrapper in TI's OMAP3430 ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_RESIZER_H
++#define OMAP_RESIZER_H
++
++#include <linux/types.h>
++
++/* ioctls definition */
++#define RSZ_IOC_BASE		'R'
++#define RSZ_IOC_MAXNR		8
++
++/*Ioctl options which are to be passed while calling the ioctl*/
++#define RSZ_REQBUF		_IOWR(RSZ_IOC_BASE, 1,\
++					struct v4l2_requestbuffers)
++#define RSZ_QUERYBUF		_IOWR(RSZ_IOC_BASE, 2, struct v4l2_buffer)
++#define RSZ_S_PARAM		_IOWR(RSZ_IOC_BASE, 3, struct rsz_params)
++#define RSZ_G_PARAM		_IOWR(RSZ_IOC_BASE, 4, struct rsz_params)
++#define RSZ_RESIZE		_IOWR(RSZ_IOC_BASE, 5, __s32)
++#define RSZ_G_STATUS		_IOWR(RSZ_IOC_BASE, 6, struct rsz_status)
++#define RSZ_QUEUEBUF		_IOWR(RSZ_IOC_BASE, 7, struct v4l2_buffer)
++#define RSZ_GET_CROPSIZE	_IOWR(RSZ_IOC_BASE, 8, struct rsz_cropsize)
++
++#define RSZ_INTYPE_YCBCR422_16BIT	0
++#define RSZ_INTYPE_PLANAR_8BIT		1
++#define RSZ_PIX_FMT_UYVY		1	/* cb:y:cr:y */
++#define RSZ_PIX_FMT_YUYV		0	/* y:cb:y:cr */
++
++enum config_done {
++	STATE_CONFIGURED,			/* Resizer driver configured
++						 * by application.
++						 */
++	STATE_NOT_CONFIGURED			/* Resizer driver not
++						 * configured by application.
++						 */
++};
++
++/* Structure Definitions */
++
++/* used to luma enhancement options */
++
++struct rsz_yenh {
++	__s32 type;				/* represents luma enable or
++						 * disable.
++						 */
++	__u8 gain;			/* represents gain. */
++	__u8 slop;			/* represents slop. */
++	__u8 core;			/* Represents core value. */
++};
++
++/* Conatins all the parameters for resizing. This structure
++ * is used to configure resiser parameters
++ */
++struct rsz_params {
++	__s32 in_hsize;				/* input frame horizontal
++						 * size.
++						 */
++	__s32 in_vsize;				/* input frame vertical size */
++	__s32 in_pitch;				/* offset between two rows of
++						 * input frame.
++						 */
++	__s32 inptyp;				/* for determining 16 bit or
++						 * 8 bit data.
++						 */
++	__s32 vert_starting_pixel;		/* for specifying vertical
++						 * starting pixel in input.
++						 */
++	__s32 horz_starting_pixel;		/* for specyfing horizontal
++						 * starting pixel in input.
++						 */
++	__s32 cbilin;				/* # defined, filter with luma
++						 * or bi-linear interpolation.
++						 */
++	__s32 pix_fmt;				/* # defined, UYVY or YUYV */
++	__s32 out_hsize;			/* output frame horizontal
++						 * size.
++						 */
++	__s32 out_vsize;				/* output frame vertical
++						 * size.
++						 */
++	__s32 out_pitch;			/* offset between two rows of
++						 * output frame.
++						 */
++	__s32 hstph;				/* for specifying horizontal
++						 * starting phase.
++						 */
++	__s32 vstph;				/* for specifying vertical
++						 * starting phase.
++						 */
++	__u16 tap4filt_coeffs[32];		/* horizontal filter
++						 * coefficients.
++						 */
++	__u16 tap7filt_coeffs[32];		/* vertical filter
++						 * coefficients.
++						 */
++	struct rsz_yenh yenh_params;
++};
++
++/* Contains the status of hardware and channel */
++struct rsz_status {
++	__s32 chan_busy;				/* 1: channel is busy,
++						 * 0: channel is not busy
++						 */
++	__s32 hw_busy;				/* 1: hardware is busy,
++						 * 0: hardware is not busy
++						 */
++	__s32 src;				/* # defined, can be either
++						 * SD-RAM or CCDC/PREVIEWER
++						 */
++};
++
++/* Passed by application for getting crop size */
++struct rsz_cropsize {
++	__u32 hcrop;			/* Number of pixels per line
++						 * cropped in output image.
++						 */
++
++	__u32 vcrop;			/* Number of lines cropped
++						 * in output image.
++						 */
++};
++
++#endif
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0024-OMAP3-Resizer-V4L2-buf-layer-issues-fixed.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0024-OMAP3-Resizer-V4L2-buf-layer-issues-fixed.patch
new file mode 100644
index 0000000000..2c3023643e
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0024-OMAP3-Resizer-V4L2-buf-layer-issues-fixed.patch
@@ -0,0 +1,729 @@
+From ad3bbadb7fc39a946dfd0cdac19e2ec8647b2c2c Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <vaibhav@psp-nfs-02.india.ti.com>
+Date: Wed, 29 Apr 2009 17:20:27 +0530
+Subject: [PATCH 24/26] OMAP3-Resizer: V4L2-buf layer issues fixed
+
+V4L2-Buffer layer issues fixed under this commit.
+This patch is same as available with PSP1.0.2 release
+
+The discussion is initiated on this with V4L2 mailing list.
+
+Please note that this patch is not being tested.
+---
+ drivers/media/video/isp/omap_resizer.c |  417 ++++++++++++++++++++++++--------
+ include/linux/omap_resizer.h           |    3 +-
+ 2 files changed, 321 insertions(+), 99 deletions(-)
+
+diff --git a/drivers/media/video/isp/omap_resizer.c b/drivers/media/video/isp/omap_resizer.c
+index 54bc425..8059c70 100644
+--- a/drivers/media/video/isp/omap_resizer.c
++++ b/drivers/media/video/isp/omap_resizer.c
+@@ -28,6 +28,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+ #include <linux/uaccess.h>
++#include <linux/pci.h>
+ #include <media/v4l2-dev.h>
+ #include <asm/cacheflush.h>
+ 
+@@ -76,6 +77,10 @@
+ #define MAX_COEF_COUNTER	16
+ #define COEFF_ADDRESS_OFFSET	0x04
+ 
++#define RSZ_DEF_REQ_EXP		0xE	/* Default read operation expand
++					 * for the Resizer driver; value
++					 * taken from Davinci.
++					 */
+ /* Global structure which contains information about number of channels
+    and protection variables */
+ struct device_params {
+@@ -85,6 +90,7 @@ struct device_params {
+ 	struct mutex reszwrap_mutex;		/* Semaphore for array */
+ 
+ 	struct videobuf_queue_ops vbq_ops;	/* videobuf queue operations */
++	unsigned long extra_page_addr;
+ };
+ 
+ /* Register mapped structure which contains the every register
+@@ -126,6 +132,9 @@ struct resizer_config {
+ 	u32 rsz_yehn;				/* yehn(luma)register mapping
+ 						 * variable.
+ 						 */
++	u32 sdr_req_exp;			/* Configuration for Non
++						 * real time read expand
++						 */
+ };
+ 
+ struct rsz_mult {
+@@ -179,6 +188,7 @@ struct channel_config {
+ 						 * channel is busy or not
+ 						 */
+ 	struct mutex chanprotection_mutex;
++	int buf_address[VIDEO_MAX_FRAME];
+ 	enum config_done config_state;
+ 	u8 input_buf_index;
+ 	u8 output_buf_index;
+@@ -200,8 +210,6 @@ struct rsz_fh {
+ 	struct videobuf_queue vbq;
+ 	struct device_params *device;
+ 
+-	dma_addr_t isp_addr_read;		/* Input/Output address */
+-	dma_addr_t isp_addr_write;		/* Input/Output address */
+ 	u32 rsz_bufsize;			/* channel specific buffersize
+ 						 */
+ };
+@@ -227,6 +235,10 @@ static int rsz_set_ratio(struct rsz_mult *multipass,
+ static void rsz_config_ratio(struct rsz_mult *multipass,
+ 					struct channel_config *rsz_conf_chan);
+ 
++static void inline rsz_set_exp(unsigned int exp)
++{
++	omap_writel(((exp & 0x3FF) << 10), OMAP3ISP_SBL_REG(0xF8));
++}
+ /**
+  * rsz_hardware_setup - Sets hardware configuration registers
+  * @rsz_conf_chan: Structure containing channel configuration
+@@ -271,12 +283,15 @@ static void rsz_hardware_setup(struct channel_config *rsz_conf_chan)
+ 						+ coeffoffset));
+ 		coeffoffset = coeffoffset + COEFF_ADDRESS_OFFSET;
+ 	}
++	/* Configure the read expand register */
++	rsz_set_exp(rsz_conf_chan->register_config.sdr_req_exp);
+ }
+ 
+ /**
+  * rsz_start - Enables Resizer Wrapper
+  * @arg: Currently not used.
+- * @device: Structure containing ISP resizer wrapper global information
++ * @fh: File structure containing ISP resizer information specific to
++ *      channel opened.
+  *
+  * Submits a resizing task specified by the rsz_resize structure. The call can
+  * either be blocked until the task is completed or returned immediately based
+@@ -292,12 +307,18 @@ int rsz_start(int *arg, struct rsz_fh *fh)
+ 	struct channel_config *rsz_conf_chan = fh->config;
+ 	struct rsz_mult *multipass = fh->multipass;
+ 	struct videobuf_queue *q = &fh->vbq;
++	struct videobuf_buffer *buf;
+ 	int ret;
+ 
+ 	if (rsz_conf_chan->config_state) {
+ 		dev_err(rsz_device, "State not configured \n");
+ 		goto err_einval;
+ 	}
++	if (!rsz_conf_chan->register_config.rsz_sdr_inadd ||
++			!rsz_conf_chan->register_config.rsz_sdr_outadd) {
++		dev_err(rsz_device, "address is null\n");
++		goto err_einval;
++	}
+ 
+ 	rsz_conf_chan->status = CHANNEL_BUSY;
+ 
+@@ -325,33 +346,22 @@ mult:
+ 		goto mult;
+ 	}
+ 
+-	if (fh->isp_addr_read) {
+-		ispmmu_unmap(fh->isp_addr_read);
+-		fh->isp_addr_read = 0;
+-	}
+-	if (fh->isp_addr_write) {
+-		ispmmu_unmap(fh->isp_addr_write);
+-		fh->isp_addr_write = 0;
+-	}
+-
+ 	rsz_conf_chan->status = CHANNEL_FREE;
+-	q->bufs[rsz_conf_chan->input_buf_index]->state = VIDEOBUF_NEEDS_INIT;
+-	q->bufs[rsz_conf_chan->output_buf_index]->state = VIDEOBUF_NEEDS_INIT;
+ 	rsz_conf_chan->register_config.rsz_sdr_outadd = 0;
+ 	rsz_conf_chan->register_config.rsz_sdr_inadd = 0;
+ 
+-	/* Unmap and free the DMA memory allocated for buffers */
+-	videobuf_dma_unmap(q, videobuf_to_dma(
+-				q->bufs[rsz_conf_chan->input_buf_index]));
+-	videobuf_dma_unmap(q, videobuf_to_dma(
+-				q->bufs[rsz_conf_chan->output_buf_index]));
+-	videobuf_dma_free(videobuf_to_dma(
+-				q->bufs[rsz_conf_chan->input_buf_index]));
+-	videobuf_dma_free(videobuf_to_dma(
+-				q->bufs[rsz_conf_chan->output_buf_index]));
+-
+ 	isp_unset_callback(CBK_RESZ_DONE);
+ 
++	/* Empty the Videobuf queue which was filled during the qbuf */
++	buf = q->bufs[rsz_conf_chan->input_buf_index];
++	buf->state = VIDEOBUF_IDLE;
++	list_del(&buf->stream);
++	if (rsz_conf_chan->input_buf_index != rsz_conf_chan->output_buf_index) {
++		buf = q->bufs[rsz_conf_chan->output_buf_index];
++		buf->state = VIDEOBUF_IDLE;
++		list_del(&buf->stream);
++	}
++
+ 	return 0;
+ err_einval:
+ 	return -EINVAL;
+@@ -359,6 +369,8 @@ err_einval:
+ 
+ /**
+  * rsz_set_multipass - Set resizer multipass
++ * @multipass: Structure containing channel configuration
++			for multipass support
+  * @rsz_conf_chan: Structure containing channel configuration
+  *
+  * Returns always 0
+@@ -384,6 +396,8 @@ static int rsz_set_multipass(struct rsz_mult *multipass,
+ 
+ /**
+  * rsz_copy_data - Copy data
++ * @multipass: Structure containing channel configuration
++			for multipass support
+  * @params: Structure containing the Resizer Wrapper parameters
+  *
+  * Copy data
+@@ -413,6 +427,8 @@ static void rsz_copy_data(struct rsz_mult *multipass, struct rsz_params *params)
+ 
+ /**
+  * rsz_set_params - Set parameters for resizer wrapper
++ * @multipass: Structure containing channel configuration
++			for multipass support
+  * @params: Structure containing the Resizer Wrapper parameters
+  * @rsz_conf_chan: Structure containing channel configuration
+  *
+@@ -524,6 +540,8 @@ static int rsz_set_params(struct rsz_mult *multipass, struct rsz_params *params,
+ 	}
+ 
+ 	rsz_config_ratio(multipass, rsz_conf_chan);
++	/* Default value for read expand:Taken from Davinci */
++	rsz_conf_chan->register_config.sdr_req_exp = RSZ_DEF_REQ_EXP;
+ 
+ 	rsz_conf_chan->config_state = STATE_CONFIGURED;
+ 
+@@ -534,6 +552,8 @@ err_einval:
+ 
+ /**
+  * rsz_set_ratio - Set ratio
++ * @multipass: Structure containing channel configuration
++			for multipass support
+  * @rsz_conf_chan: Structure containing channel configuration
+  *
+  * Returns 0 if successful, -EINVAL if invalid output size, upscaling ratio is
+@@ -548,7 +568,8 @@ static int rsz_set_ratio(struct rsz_mult *multipass,
+ 
+ 	if ((multipass->out_hsize > MAX_IMAGE_WIDTH) ||
+ 			(multipass->out_vsize > MAX_IMAGE_WIDTH)) {
+-		dev_err(rsz_device, "Invalid output size!");
++		dev_err(rsz_device, "Invalid output size! - %d", \
++					multipass->out_hsize);
+ 		goto err_einval;
+ 	}
+ 	if (multipass->cbilin) {
+@@ -758,6 +779,8 @@ err_einval:
+ 
+ /**
+  * rsz_config_ratio - Configure ratio
++ * @multipass: Structure containing channel configuration
++			for multipass support
+  * @rsz_conf_chan: Structure containing channel configuration
+  *
+  * Configure ratio
+@@ -789,6 +812,20 @@ static void rsz_config_ratio(struct rsz_mult *multipass,
+ 					((vsize << ISPRSZ_IN_SIZE_VERT_SHIFT)
+ 					& ISPRSZ_IN_SIZE_VERT_MASK);
+ 
++	/* This is another workaround for the ISP-MMU translation fault.
++	   For the parameters whose image size comes exactly to PAGE_SIZE
++	   generates ISP-MMU translation fault. The root-cause is the equation
++		input width = (32*sph + (ow - 1)*hrsz + 16) >> 8 + 7
++			= (64*sph + (ow - 1)*hrsz + 32) >> 8 + 7
++		input height = (32*spv + (oh - 1)*vrsz + 16) >> 8 + 4
++		= (64*spv + (oh - 1)*vrsz + 32) >> 8 + 7
++
++	   we are adjusting the input width to suit for Resizer module,
++	   application should use this configuration henceforth.
++	 */
++	multipass->in_hsize = hsize;
++	multipass->in_vsize = vsize;
++
+ 	for (coeffcounter = 0; coeffcounter < MAX_COEF_COUNTER;
+ 							coeffcounter++) {
+ 		if (multipass->num_htap) {
+@@ -990,24 +1027,15 @@ static void rsz_calculate_crop(struct channel_config *rsz_conf_chan,
+ static void rsz_vbq_release(struct videobuf_queue *q,
+ 						struct videobuf_buffer *vb)
+ {
+-	int i;
+ 	struct rsz_fh *fh = q->priv_data;
++	struct videobuf_dmabuf *dma = NULL;
+ 
+-	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+-		struct videobuf_dmabuf *dma = NULL;
+-		if (!q->bufs[i])
+-			continue;
+-		if (q->bufs[i]->memory != V4L2_MEMORY_MMAP)
+-			continue;
+-		dma = videobuf_to_dma(q->bufs[i]);
+-		videobuf_dma_unmap(q, dma);
+-		videobuf_dma_free(dma);
+-	}
++	dma = videobuf_to_dma(q->bufs[vb->i]);
++	videobuf_dma_unmap(q, dma);
++	videobuf_dma_free(dma);
++	ispmmu_unmap(fh->config->buf_address[vb->i]);
++	fh->config->buf_address[vb->i] = 0;
+ 
+-	ispmmu_unmap(fh->isp_addr_read);
+-	ispmmu_unmap(fh->isp_addr_write);
+-	fh->isp_addr_read = 0;
+-	fh->isp_addr_write = 0;
+ 	spin_lock(&fh->vbq_lock);
+ 	vb->state = VIDEOBUF_NEEDS_INIT;
+ 	spin_unlock(&fh->vbq_lock);
+@@ -1062,7 +1090,105 @@ err_einval:
+ 	spin_unlock(&fh->vbq_lock);
+ 	return -EINVAL;
+ }
++/*
++ * This function is work around for the videobuf_iolock API,
++ * for User memory allocated with ioremap (VM_IO flag) the API
++ * get_user_pages fails.
++ *
++ * To fulfill this requirement, we have completely ignored VM layer of
++ * Linux, and configuring the ISP MMU with physical address.
++ */
++static int omap_videobuf_dma_init_user(struct videobuf_buffer *vb,
++		unsigned long physp, unsigned long asize)
++{
++	struct videobuf_dmabuf *dma;
++	struct scatterlist *sglist;
++	unsigned long data, first, last;
++	int len, i = 0;
++
++	dma = videobuf_to_dma(vb);
++	data = vb->baddr;
++
++        first = (data & PAGE_MASK) >> PAGE_SHIFT;
++        last  = ((data+asize-1) & PAGE_MASK) >> PAGE_SHIFT;
++        dma->offset   = data & ~PAGE_MASK;
++        dma->nr_pages = last-first+1;
++
++	dma->direction = PCI_DMA_FROMDEVICE;
++	/*
++	 * Allocate array of sglen + 1, to add entry of extra page
++	 * for input buffer. Driver always uses 0th buffer as input buffer.
++	 */
++	len = dma->nr_pages + (vb->i ? 0 : 1);
++	sglist = kcalloc(len, sizeof(*sglist), GFP_KERNEL);
++	if (NULL == sglist)
++                return -ENOMEM;
++
++	sglist[0].offset = 0;
++	sglist[0].length = PAGE_SIZE - dma->offset;
++	sglist[0].dma_address = (dma_addr_t)physp;
++	physp += sglist[0].length;
++	/*
++	 * Iterate in a loop for the number of pages
++	 */
++	for (i = 1; i < (len - (vb->i ? 0 : 1)); i++) {
++		sglist[i].offset = 0;
++		sglist[i].length = PAGE_SIZE;
++		sglist[i].dma_address = (dma_addr_t)physp;
++		physp += PAGE_SIZE;
++	}
++	if (0 == vb->i) {
++		sglist[i].offset = 0;
++		sglist[i].length = PAGE_SIZE;
++		sglist[i].dma_address =
++			(dma_addr_t)device_config->extra_page_addr;
++        }
++	dma->sglist = sglist;
++	dma->sglen = len;
++        return 0;
++
++		}
++/*
++ * This function is workaround for the issue, where ISP-MMU generated
++ * translation fault for specific params whose size is aligned to PAGE_SIZE.
++
++ * As a workaround we are padding one extra page for input buffer. This page
++ * we are allocating during init time and will not be released through-out
++ * life time of resizer driver. Please note that Resizer module only reads
++ * from this extra page.
++ */
++int omap_create_sg(struct videobuf_queue *q, struct videobuf_dmabuf *dma)
++{
++	struct scatterlist *sglist;
++	int sglen;
+ 
++	sglen = dma->sglen;
++	sglist = kcalloc(sglen + 1, sizeof(*sglist), GFP_KERNEL);
++	if (NULL == sglist)
++		return -ENOMEM;
++	/*
++	 * Copy the sglist locally
++	 */
++	memcpy(sglist, dma->sglist, sglen * sizeof(*sglist));
++	/*
++	 * Release the old sglist, since we already copied it locally
++	 */
++	videobuf_dma_unmap(q, dma);
++	/*
++	 * Add extra entry to sglist to work with specific params, whose
++	 * buffer address alined to PAGE_SIZE.
++	 */
++	sglist[sglen].offset = 0;
++	sglist[sglen].length = PAGE_SIZE;
++	sglist[sglen].dma_address = (dma_addr_t)device_config->extra_page_addr;
++	sglen++;
++	/*
++	 * Save the sglist for mapping to ISP-MMU space
++	 */
++	dma->sglist = sglist;
++	dma->sglen = sglen;
++	return 0;
++}
+ /**
+  * rsz_vbq_prepare - Videobuffer is prepared and mmapped.
+  * @q: Structure containing the videobuffer queue file handle, and device
+@@ -1079,19 +1205,24 @@ static int rsz_vbq_prepare(struct videobuf_queue *q,
+ {
+ 	struct rsz_fh *fh = q->priv_data;
+ 	struct channel_config *rsz_conf_chan = fh->config;
+-	struct rsz_mult *multipass = fh->multipass;
+ 	int err = 0;
+ 	unsigned int isp_addr, insize, outsize;
+-	struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
+-
++	struct rsz_mult *multipass = fh->multipass;
+ 	spin_lock(&fh->vbq_lock);
+ 	if (vb->baddr) {
++		/* Check for 32 byte alignement */
++		if (vb->baddr != (vb->baddr & ~0x1F)) {
++			spin_unlock(&fh->vbq_lock);
++			dev_err(rsz_device, "Buffer address should be aligned \
++					to 32 byte\n");
++			return -EINVAL;
++		}
+ 		vb->size = fh->rsz_bufsize;
+ 		vb->bsize = fh->rsz_bufsize;
+ 	} else {
+ 		spin_unlock(&fh->vbq_lock);
+ 		dev_err(rsz_device, "No user buffer allocated\n");
+-		goto out;
++		return -EINVAL;
+ 	}
+ 	if (vb->i) {
+ 		vb->width = fh->params->out_hsize;
+@@ -1103,55 +1234,128 @@ static int rsz_vbq_prepare(struct videobuf_queue *q,
+ 
+ 	vb->field = field;
+ 	spin_unlock(&fh->vbq_lock);
++	/*
++	 * Calculate input and output sizes, will be used while mapping
++	 * user pages
++	 */
++	outsize = multipass->out_pitch * multipass->out_vsize;
++	insize = multipass->in_pitch * multipass->in_vsize;
+ 
+ 	if (vb->state == VIDEOBUF_NEEDS_INIT) {
+-		err = videobuf_iolock(q, vb, NULL);
+-		if (!err) {
+-			isp_addr = ispmmu_map_sg(dma->sglist, dma->sglen);
+-			if (!isp_addr)
+-				err = -EIO;
+-			else {
+-				if (vb->i) {
+-					rsz_conf_chan->register_config.
+-							rsz_sdr_outadd
+-							= isp_addr;
+-					fh->isp_addr_write = isp_addr;
+-					rsz_conf_chan->output_buf_index = vb->i;
+-				} else {
++		struct videobuf_dmabuf *dma;
++		struct vm_area_struct *vma;
++		spin_lock(&fh->vbq_lock);
++		dma = videobuf_to_dma(vb);
++		vma = find_vma(current->mm, vb->baddr);
++		if ((vma) && (vma->vm_flags & VM_IO) && (vma->vm_pgoff)) {
++			/* This will catch ioremaped buffers to the kernel.
++			 *  It gives two possible scenarios -
++			 *  - Driver allocates buffer using either
++			 *    dma_alloc_coherent or get_free_pages,
++			 *    and maps to user space using
++			 *    io_remap_pfn_range/remap_pfn_range
++			 *  - Drivers maps memory outside from Linux using
++			 *    io_remap
++			 */
++			unsigned long physp = 0, asize;
++			asize = vb->i ? outsize : insize;
++			if ((vb->baddr + asize) > vma->vm_end) {
++				spin_unlock(&fh->vbq_lock);
++				dev_err(rsz_device, "User Buffer Allocation:" \
++					"err=%lu[%lu]\n",\
++					(vma->vm_end - vb->baddr), asize);
++				return -ENOMEM;
++			}
++			physp = (vma->vm_pgoff << PAGE_SHIFT) +
++					(vb->baddr - vma->vm_start);
++			err = omap_videobuf_dma_init_user(vb, physp, asize);
++			spin_unlock(&fh->vbq_lock);
++			if (0 != err)
++				return err;
++		} else {
++			err = videobuf_iolock(q, vb, NULL);
++			/*
++			 * In case of user pointer mode, the get_user_pages
++			 * will fail if user has allocated less memory than
++			 * vb->size. But it is not error from resizer driver
++			 * point of view. so handled seperately
++			 */
++			if ((err < 0) && (dma->nr_pages > 0))
++				err = videobuf_dma_map(q, dma);
++			if (err)
++				goto buf_release;
++			/*
++			 * Add one extra page for input buffer
++			 */
++			if (0 == vb->i)
++				err = omap_create_sg(q, dma);
++			if (err)
++				goto buf_release;
++			spin_unlock(&fh->vbq_lock);
++		}
++		isp_addr = ispmmu_map_sg(dma->sglist, dma->sglen);
++		if (!isp_addr)
++			err = -EIO;
++		else {
++			if (vb->i) {
++				rsz_conf_chan->buf_address[vb->i] = isp_addr;
++				rsz_conf_chan->register_config.
++					rsz_sdr_outadd
++					= isp_addr;
++				rsz_conf_chan->output_buf_index = vb->i;
++			} else {
++				rsz_conf_chan->buf_address[vb->i] = isp_addr;
++				rsz_conf_chan->register_config.
++					rsz_sdr_inadd
++					= isp_addr;
++				rsz_conf_chan->input_buf_index = vb->i;
++				if (outsize < insize && rsz_conf_chan->
++						register_config.
++						rsz_sdr_outadd == 0) {
+ 					rsz_conf_chan->register_config.
+-							rsz_sdr_inadd
+-							= isp_addr;
+-					rsz_conf_chan->input_buf_index = vb->i;
+-					outsize = multipass->out_pitch *
+-							multipass->out_vsize;
+-					insize = multipass->in_pitch *
+-							multipass->in_vsize;
+-					if (outsize < insize) {
+-						rsz_conf_chan->register_config.
+-								rsz_sdr_outadd
+-								= isp_addr;
+-						rsz_conf_chan->
+-							output_buf_index =
+-							vb->i;
+-					}
+-
+-					fh->isp_addr_read = isp_addr;
++						rsz_sdr_outadd
++						= isp_addr;
++					rsz_conf_chan->
++						output_buf_index =
++						vb->i;
+ 				}
+ 			}
+ 		}
+ 
+-	}
++	} else {
++		if(vb->i) {
++			rsz_conf_chan->register_config.
++				rsz_sdr_outadd =
++					rsz_conf_chan->buf_address[vb->i];
++			rsz_conf_chan->output_buf_index = vb->i;
++		} else {
++			rsz_conf_chan->register_config.
++				rsz_sdr_inadd =
++					rsz_conf_chan->buf_address[vb->i];
++			rsz_conf_chan->input_buf_index = vb->i;
++			if(outsize < insize && rsz_conf_chan->
++					register_config.
++					rsz_sdr_outadd == 0) {
++				rsz_conf_chan->register_config.
++					rsz_sdr_outadd
++					= rsz_conf_chan->buf_address[vb->i];
++				rsz_conf_chan->output_buf_index = vb->i;
++			}
++
++		}
+ 
++	}
+ 	if (!err) {
+ 		spin_lock(&fh->vbq_lock);
+ 		vb->state = VIDEOBUF_PREPARED;
+ 		spin_unlock(&fh->vbq_lock);
+-		flush_cache_user_range(NULL, vb->baddr, (vb->baddr
+-								+ vb->bsize));
+ 	} else
+ 		rsz_vbq_release(q, vb);
+ 
+-out:
++	return err;
++buf_release:
++	spin_unlock(&fh->vbq_lock);
++	rsz_vbq_release(q, vb);
+ 	return err;
+ }
+ 
+@@ -1255,7 +1459,8 @@ err_enomem0:
+  **/
+ static int rsz_release(struct inode *inode, struct file *filp)
+ {
+-	u32 timeout = 0;
++	int i;
++	unsigned int timeout = 0;
+ 	struct rsz_fh *fh = filp->private_data;
+ 	struct channel_config *rsz_conf_chan = fh->config;
+ 	struct rsz_params *params = fh->params;
+@@ -1266,17 +1471,17 @@ static int rsz_release(struct inode *inode, struct file *filp)
+ 		timeout++;
+ 		schedule();
+ 	}
+-	if (mutex_lock_interruptible(&device_config->reszwrap_mutex))
+-		return -EINTR;
+-	device_config->opened--;
+-	mutex_unlock(&device_config->reszwrap_mutex);
+-	/* This will Free memory allocated to the buffers,
+-	 * and flushes the queue
+-	 */
+-	videobuf_queue_cancel(q);
+-	fh->params = NULL;
+-	fh->config = NULL;
++	/* Free memory allocated to the buffers */
++	for (i = 0 ; i < VIDEO_MAX_FRAME ; i++) {
++		struct videobuf_dmabuf *dma = NULL;
++		if (!q->bufs[i])
++			continue;
++		dma = videobuf_to_dma(q->bufs[i]);
++		videobuf_dma_unmap(q, dma);
++		videobuf_dma_free(dma);
++	}
+ 
++	videobuf_mmap_free(q);
+ 	fh->rsz_bufsize = 0;
+ 	filp->private_data = NULL;
+ 
+@@ -1286,7 +1491,8 @@ static int rsz_release(struct inode *inode, struct file *filp)
+ 	kfree(fh);
+ 
+ 	isp_put();
+-
++	fh->params = NULL;
++	fh->config = NULL;
+ 	return 0;
+ }
+ 
+@@ -1353,6 +1559,12 @@ static long rsz_unlocked_ioctl(struct file *file, unsigned int cmd,
+ 							chanprotection_mutex))
+ 			return -EINTR;
+ 		ret = videobuf_reqbufs(&fh->vbq, (void *)&req_buf);
++		if (ret >= 0) {
++			if (copy_to_user((struct v4l2_requestbuffers *)arg,
++						&req_buf, sizeof(struct
++						v4l2_requestbuffers)))
++				return -EFAULT;
++		}
+ 		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
+ 		break;
+ 	}
+@@ -1394,11 +1606,7 @@ static long rsz_unlocked_ioctl(struct file *file, unsigned int cmd,
+ 						sizeof(struct rsz_params))) {
+ 			return -EFAULT;
+ 		}
+-		if (mutex_lock_interruptible(&rsz_conf_chan->
+-							chanprotection_mutex))
+-			return -EINTR;
+-		ret = rsz_set_params(fh->multipass, params, rsz_conf_chan);
+-		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		ret = rsz_set_params(fh->multipass, fh->params,	rsz_conf_chan);
+ 		break;
+ 	}
+ 	case RSZ_G_PARAM:
+@@ -1433,6 +1641,12 @@ static long rsz_unlocked_ioctl(struct file *file, unsigned int cmd,
+ 		rsz_calculate_crop(rsz_conf_chan, (struct rsz_cropsize *)arg);
+ 		break;
+ 
++	case RSZ_S_EXP:
++		if (mutex_lock_interruptible(&rsz_conf_chan->chanprotection_mutex))
++			return -EINTR;
++		rsz_conf_chan->register_config.sdr_req_exp = *((unsigned int *)arg);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		break;
+ 	default:
+ 		dev_err(rsz_device, "resizer_ioctl: Invalid Command Value");
+ 		return -EINVAL;
+@@ -1535,14 +1749,18 @@ static int __init omap_rsz_init(void)
+ 								"memory\n");
+ 		return -ENOMEM;
+ 	}
+-
++	device->extra_page_addr = __get_free_pages(GFP_KERNEL | GFP_DMA, 0);
++	if (!device->extra_page_addr) {
++		dev_err(rsz_device, OMAP_REZR_NAME ":Allocation failed. ");
++		kfree(device);
++		return -ENOMEM;
++	}
+ 	ret = alloc_chrdev_region(&dev, 0, 1, OMAP_REZR_NAME);
+ 	if (ret < 0) {
+ 		dev_err(rsz_device, OMAP_REZR_NAME ": intialization failed. "
+ 			"Could not allocate region "
+ 			"for character device\n");
+-		kfree(device);
+-		return -ENODEV;
++		goto fail1;
+ 	}
+ 
+ 	/* Register the driver in the kernel */
+@@ -1608,6 +1826,8 @@ fail3:
+ 	cdev_del(&c_dev);
+ fail2:
+ 	unregister_chrdev_region(dev, 1);
++fail1:
++	free_pages((unsigned long)device->extra_page_addr, 0);
+ 	kfree(device);
+ 	return ret;
+ }
+@@ -1623,6 +1843,7 @@ void __exit omap_rsz_exit(void)
+ 	platform_driver_unregister(&omap_resizer_driver);
+ 	cdev_del(&c_dev);
+ 	unregister_chrdev_region(dev, 1);
++	free_pages((unsigned long)device_config->extra_page_addr, 0);
+ 	kfree(device_config);
+ }
+ 
+diff --git a/include/linux/omap_resizer.h b/include/linux/omap_resizer.h
+index 5ac0c88..47b8dd8 100644
+--- a/include/linux/omap_resizer.h
++++ b/include/linux/omap_resizer.h
+@@ -21,7 +21,7 @@
+ 
+ /* ioctls definition */
+ #define RSZ_IOC_BASE		'R'
+-#define RSZ_IOC_MAXNR		8
++#define RSZ_IOC_MAXNR		9
+ 
+ /*Ioctl options which are to be passed while calling the ioctl*/
+ #define RSZ_REQBUF		_IOWR(RSZ_IOC_BASE, 1,\
+@@ -33,6 +33,7 @@
+ #define RSZ_G_STATUS		_IOWR(RSZ_IOC_BASE, 6, struct rsz_status)
+ #define RSZ_QUEUEBUF		_IOWR(RSZ_IOC_BASE, 7, struct v4l2_buffer)
+ #define RSZ_GET_CROPSIZE	_IOWR(RSZ_IOC_BASE, 8, struct rsz_cropsize)
++#define RSZ_S_EXP		_IOWR(RSZ_IOC_BASE, 9, __s32)
+ 
+ #define RSZ_INTYPE_YCBCR422_16BIT	0
+ #define RSZ_INTYPE_PLANAR_8BIT		1
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0025-OMAP3-Resizer-Build-issues-fixed.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0025-OMAP3-Resizer-Build-issues-fixed.patch
new file mode 100644
index 0000000000..143a846e3c
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/resizer/0025-OMAP3-Resizer-Build-issues-fixed.patch
@@ -0,0 +1,36 @@
+From 9fec955e98b4ef7922f629e3a81d2d1af216e028 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <vaibhav@psp-nfs-02.india.ti.com>
+Date: Wed, 29 Apr 2009 18:12:42 +0530
+Subject: [PATCH 25/26] OMAP3-Resizer: Build issues fixed
+
+There were some building issues with latest gitorious tree,
+fixed them.
+---
+ drivers/media/video/isp/omap_resizer.c |    4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/video/isp/omap_resizer.c b/drivers/media/video/isp/omap_resizer.c
+index 8059c70..dd90b24 100644
+--- a/drivers/media/video/isp/omap_resizer.c
++++ b/drivers/media/video/isp/omap_resizer.c
+@@ -1033,7 +1033,7 @@ static void rsz_vbq_release(struct videobuf_queue *q,
+ 	dma = videobuf_to_dma(q->bufs[vb->i]);
+ 	videobuf_dma_unmap(q, dma);
+ 	videobuf_dma_free(dma);
+-	ispmmu_unmap(fh->config->buf_address[vb->i]);
++	ispmmu_vunmap(fh->config->buf_address[vb->i]);
+ 	fh->config->buf_address[vb->i] = 0;
+ 
+ 	spin_lock(&fh->vbq_lock);
+@@ -1293,7 +1293,7 @@ static int rsz_vbq_prepare(struct videobuf_queue *q,
+ 				goto buf_release;
+ 			spin_unlock(&fh->vbq_lock);
+ 		}
+-		isp_addr = ispmmu_map_sg(dma->sglist, dma->sglen);
++		isp_addr = ispmmu_vmap(dma->sglist, dma->sglen);
+ 		if (!isp_addr)
+ 			err = -EIO;
+ 		else {
+-- 
+1.6.2.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0001-V4L2-Add-COLORFX-user-control.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0001-V4L2-Add-COLORFX-user-control.patch
new file mode 100644
index 0000000000..d9e4243b4a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0001-V4L2-Add-COLORFX-user-control.patch
@@ -0,0 +1,44 @@
+From ad422f476ce04636f911557bbfd066c516e9b472 Mon Sep 17 00:00:00 2001
+From: Aguirre Rodriguez, Sergio Alberto <saaguirre@ti.com>
+Date: Tue, 20 Jan 2009 16:29:26 -0600
+Subject: [PATCH] V4L2: Add COLORFX user control
+
+From 07396d67b39bf7bcc81440d3e72d253ad6c54f11 Mon Sep 17 00:00:00 2001
+From: Sergio Aguirre <saaguirre@ti.com>
+Date: Tue, 20 Jan 2009 15:34:43 -0600
+Subject: [PATCH v2] V4L2: Add COLORFX user control
+
+This is a common feature on many cameras. the options are:
+Default colors,
+B & W,
+Sepia
+
+Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
+---
+ include/linux/videodev2.h |    9 ++++++++-
+ 1 files changed, 8 insertions(+), 1 deletions(-)
+
+diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
+index 5571dbe..8e4e25e 100644
+--- a/include/linux/videodev2.h
++++ b/include/linux/videodev2.h
+@@ -879,8 +879,15 @@ enum v4l2_power_line_frequency {
+ #define V4L2_CID_BACKLIGHT_COMPENSATION 	(V4L2_CID_BASE+28)
+ #define V4L2_CID_CHROMA_AGC                     (V4L2_CID_BASE+29)
+ #define V4L2_CID_COLOR_KILLER                   (V4L2_CID_BASE+30)
++#define V4L2_CID_COLORFX			(V4L2_CID_BASE+31)
++enum v4l2_colorfx {
++	V4L2_COLORFX_NONE	= 0,
++	V4L2_COLORFX_BW		= 1,
++	V4L2_COLORFX_SEPIA	= 2,
++};
++
+ /* last CID + 1 */
+-#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+31)
++#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+32)
+ 
+ /*  MPEG-class control IDs defined by V4L2 */
+ #define V4L2_CID_MPEG_BASE 			(V4L2_CTRL_CLASS_MPEG | 0x900)
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0002-V4L-Int-if-v4l2_int_device_try_attach_all-requires.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0002-V4L-Int-if-v4l2_int_device_try_attach_all-requires.patch
new file mode 100644
index 0000000000..45e27a2fda
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0002-V4L-Int-if-v4l2_int_device_try_attach_all-requires.patch
@@ -0,0 +1,50 @@
+From 5b007183d51543624bc9f582966f245a64157b57 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@nokia.com>
+Date: Fri, 31 Oct 2008 11:51:30 +0200
+Subject: [PATCH] V4L: Int if: v4l2_int_device_try_attach_all requires mutex
+
+Signed-off-by: Sakari Ailus <sakari.ailus@nokia.com>
+---
+ drivers/media/video/v4l2-int-device.c |   12 ++++++++++--
+ 1 files changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/video/v4l2-int-device.c b/drivers/media/video/v4l2-int-device.c
+index a935bae..eb8dc84 100644
+--- a/drivers/media/video/v4l2-int-device.c
++++ b/drivers/media/video/v4l2-int-device.c
+@@ -32,7 +32,7 @@
+ static DEFINE_MUTEX(mutex);
+ static LIST_HEAD(int_list);
+ 
+-void v4l2_int_device_try_attach_all(void)
++static void __v4l2_int_device_try_attach_all(void)
+ {
+ 	struct v4l2_int_device *m, *s;
+ 
+@@ -66,6 +66,14 @@ void v4l2_int_device_try_attach_all(void)
+ 		}
+ 	}
+ }
++
++void v4l2_int_device_try_attach_all(void)
++{
++	mutex_lock(&mutex);
++	__v4l2_int_device_try_attach_all();
++	mutex_unlock(&mutex);
++}
++
+ EXPORT_SYMBOL_GPL(v4l2_int_device_try_attach_all);
+ 
+ static int ioctl_sort_cmp(const void *a, const void *b)
+@@ -89,7 +97,7 @@ int v4l2_int_device_register(struct v4l2_int_device *d)
+ 		     &ioctl_sort_cmp, NULL);
+ 	mutex_lock(&mutex);
+ 	list_add(&d->head, &int_list);
+-	v4l2_int_device_try_attach_all();
++	__v4l2_int_device_try_attach_all();
+ 	mutex_unlock(&mutex);
+ 
+ 	return 0;
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0003-V4L-Int-if-Dummy-slave.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0003-V4L-Int-if-Dummy-slave.patch
new file mode 100644
index 0000000000..829810fab0
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0003-V4L-Int-if-Dummy-slave.patch
@@ -0,0 +1,61 @@
+From cc1d76e0f50321e80f7f50e9e214de2c9a45628a Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@nokia.com>
+Date: Wed, 22 Oct 2008 18:41:20 +0300
+Subject: [PATCH] V4L: Int if: Dummy slave
+
+This patch implements a dummy slave that has no functionality. Helps
+managing slaves in the OMAP 3 camera driver; no need to check for NULL
+pointers.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@nokia.com>
+---
+ drivers/media/video/v4l2-int-device.c |   19 +++++++++++++++++++
+ include/media/v4l2-int-device.h       |    2 ++
+ 2 files changed, 21 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/media/video/v4l2-int-device.c b/drivers/media/video/v4l2-int-device.c
+index eb8dc84..483ee2e 100644
+--- a/drivers/media/video/v4l2-int-device.c
++++ b/drivers/media/video/v4l2-int-device.c
+@@ -67,6 +67,25 @@ static void __v4l2_int_device_try_attach_all(void)
+ 	}
+ }
+ 
++static struct v4l2_int_slave dummy_slave = {
++	/* Dummy pointer to avoid underflow in find_ioctl. */
++	.ioctls = (void *)sizeof(struct v4l2_int_ioctl_desc),
++	.num_ioctls = 0,
++};
++
++static struct v4l2_int_device dummy = {
++	.type = v4l2_int_type_slave,
++	.u = {
++		.slave = &dummy_slave,
++	},
++};
++
++struct v4l2_int_device *v4l2_int_device_dummy()
++{
++	return &dummy;
++}
++EXPORT_SYMBOL_GPL(v4l2_int_device_dummy);
++
+ void v4l2_int_device_try_attach_all(void)
+ {
+ 	mutex_lock(&mutex);
+diff --git a/include/media/v4l2-int-device.h b/include/media/v4l2-int-device.h
+index fbf5855..5d254c4 100644
+--- a/include/media/v4l2-int-device.h
++++ b/include/media/v4l2-int-device.h
+@@ -84,6 +84,8 @@ struct v4l2_int_device {
+ 	void *priv;
+ };
+ 
++struct v4l2_int_device *v4l2_int_device_dummy(void);
++
+ void v4l2_int_device_try_attach_all(void);
+ 
+ int v4l2_int_device_register(struct v4l2_int_device *d);
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0004-V4L-int-device-add-support-for-VIDIOC_QUERYMENU.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0004-V4L-int-device-add-support-for-VIDIOC_QUERYMENU.patch
new file mode 100644
index 0000000000..b81b20419e
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0004-V4L-int-device-add-support-for-VIDIOC_QUERYMENU.patch
@@ -0,0 +1,33 @@
+From e041e57cafca24cf92430cdf3cc091060a271e19 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@nokia.com>
+Date: Fri, 31 Oct 2008 10:20:31 +0200
+Subject: [PATCH] V4L: int device: add support for VIDIOC_QUERYMENU
+
+Signed-off-by: Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
+---
+ include/media/v4l2-int-device.h |    2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/include/media/v4l2-int-device.h b/include/media/v4l2-int-device.h
+index 5d254c4..81f4863 100644
+--- a/include/media/v4l2-int-device.h
++++ b/include/media/v4l2-int-device.h
+@@ -178,6 +178,7 @@ enum v4l2_int_ioctl_num {
+ 	vidioc_int_s_fmt_cap_num,
+ 	vidioc_int_try_fmt_cap_num,
+ 	vidioc_int_queryctrl_num,
++	vidioc_int_querymenu_num,
+ 	vidioc_int_g_ctrl_num,
+ 	vidioc_int_s_ctrl_num,
+ 	vidioc_int_cropcap_num,
+@@ -282,6 +283,7 @@ V4L2_INT_WRAPPER_1(g_fmt_cap, struct v4l2_format, *);
+ V4L2_INT_WRAPPER_1(s_fmt_cap, struct v4l2_format, *);
+ V4L2_INT_WRAPPER_1(try_fmt_cap, struct v4l2_format, *);
+ V4L2_INT_WRAPPER_1(queryctrl, struct v4l2_queryctrl, *);
++V4L2_INT_WRAPPER_1(querymenu, struct v4l2_querymenu, *);
+ V4L2_INT_WRAPPER_1(g_ctrl, struct v4l2_control, *);
+ V4L2_INT_WRAPPER_1(s_ctrl, struct v4l2_control, *);
+ V4L2_INT_WRAPPER_1(cropcap, struct v4l2_cropcap, *);
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0005-V4L-Int-if-Add-vidioc_int_querycap.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0005-V4L-Int-if-Add-vidioc_int_querycap.patch
new file mode 100644
index 0000000000..a9e06290fa
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/isp/v4l/0005-V4L-Int-if-Add-vidioc_int_querycap.patch
@@ -0,0 +1,35 @@
+From dc05ee10583dca44e0f8d4109bd1397ee3c5ffae Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@nokia.com>
+Date: Thu, 2 Oct 2008 11:55:07 +0300
+Subject: [PATCH] V4L: Int if: Add vidioc_int_querycap
+
+Signed-off-by: Sakari Ailus <sakari.ailus@nokia.com>
+---
+ include/media/v4l2-int-device.h |    4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/include/media/v4l2-int-device.h b/include/media/v4l2-int-device.h
+index 81f4863..2830ae1 100644
+--- a/include/media/v4l2-int-device.h
++++ b/include/media/v4l2-int-device.h
+@@ -173,7 +173,8 @@ enum v4l2_int_ioctl_num {
+ 	 * "Proper" V4L ioctls, as in struct video_device.
+ 	 *
+ 	 */
+-	vidioc_int_enum_fmt_cap_num = 1,
++	vidioc_int_querycap_num = 1,
++	vidioc_int_enum_fmt_cap_num,
+ 	vidioc_int_g_fmt_cap_num,
+ 	vidioc_int_s_fmt_cap_num,
+ 	vidioc_int_try_fmt_cap_num,
+@@ -278,6 +279,7 @@ enum v4l2_int_ioctl_num {
+ 		return desc;						\
+ 	}
+ 
++V4L2_INT_WRAPPER_1(querycap, struct v4l2_capability, *);
+ V4L2_INT_WRAPPER_1(enum_fmt_cap, struct v4l2_fmtdesc, *);
+ V4L2_INT_WRAPPER_1(g_fmt_cap, struct v4l2_format, *);
+ V4L2_INT_WRAPPER_1(s_fmt_cap, struct v4l2_format, *);
+-- 
+1.5.6.5
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/make-alignment-visible.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/make-alignment-visible.diff
new file mode 100644
index 0000000000..9b3958f82a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/make-alignment-visible.diff
@@ -0,0 +1,26 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Mon, 13 Oct 2008 19:32:16 +0000 (+0100)
+Subject: ARM: Add prompt for CONFIG_ALIGNMENT_TRAP
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=60d60f0ca47fcf4fbb649e45aa64f5a0a4c2f2c8
+
+ARM: Add prompt for CONFIG_ALIGNMENT_TRAP
+
+This adds a prompt text for CONFIG_ALIGNMENT_TRAP, thus making it
+visible in make *config.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 61314f6..18d3119 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -971,7 +971,7 @@ config LEDS_CPU
+ 	  will overrule the CPU usage LED.
+ 
+ config ALIGNMENT_TRAP
+-	bool
++	bool "Enable alignment trap"
+ 	depends on CPU_CP15_MMU
+ 	default y if !ARCH_EBSA110
+ 	help
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/mmctiming.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/mmctiming.patch
new file mode 100644
index 0000000000..ec540ab3cb
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/mmctiming.patch
@@ -0,0 +1,16 @@
+Index: git/drivers/mmc/core/core.c
+===================================================================
+--- git.orig/drivers/mmc/core/core.c
++++ git/drivers/mmc/core/core.c
+@@ -284,9 +284,9 @@ void mmc_set_data_timeout(struct mmc_dat
+ 			 * The limit is really 250 ms, but that is
+ 			 * insufficient for some crappy cards.
+ 			 */
+-			limit_us = 300000;
++			limit_us = 500000;
+ 		else
+-			limit_us = 100000;
++			limit_us = 200000;
+ 
+ 		/*
+ 		 * SDHC cards always use these fixed values.
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/modedb-hd720.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/modedb-hd720.patch
new file mode 100644
index 0000000000..0166de651a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/modedb-hd720.patch
@@ -0,0 +1,13 @@
+--- orig/drivers/video/modedb.c.orig	2009-04-07 11:40:10.000000000 +0200
++++ git/drivers/video/modedb.c	2009-04-07 10:35:29.000000000 +0200
+@@ -44,6 +44,10 @@
+ 	NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
+ 	0, FB_VMODE_NONINTERLACED
+     }, {
++	/* 1280x720 @ 60 Hz, 45 kHz hsync, CEA 681-E Format 4 */
++	"hd720", 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,
++	0, FB_VMODE_NONINTERLACED
++    }, {
+ 	/* 800x600 @ 56 Hz, 35.15 kHz hsync */
+ 	NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2,
+ 	0, FB_VMODE_NONINTERLACED
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0001-USB-musb-only-turn-off-vbus-in-OTG-hosts.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0001-USB-musb-only-turn-off-vbus-in-OTG-hosts.patch
new file mode 100644
index 0000000000..a7898d1440
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0001-USB-musb-only-turn-off-vbus-in-OTG-hosts.patch
@@ -0,0 +1,43 @@
+From a9199e8ab6d6fb105aa251d6bf2192e7eafac8ee Mon Sep 17 00:00:00 2001
+From: Ajay Kumar Gupta <ajay.gupta-l0cyMroinI0@public.gmane.org>
+Date: Tue, 24 Mar 2009 17:22:53 -0700
+Subject: [PATCH] USB: musb: only turn off vbus in OTG hosts
+
+Except on DaVinci, VBUS is now switched off as part of idling the
+USB link (after a_wait_bcon) whenever a device is disconnected
+from host.  This is correct for OTG hosts, where either SRP or
+an ID interrupt could turn VBUS on again.
+
+However, for non-OTG hosts there's no way to turn VBUS on again,
+so the host becomes unusable.  And the procfs entry which once
+allowed a manual workaround for this is now gone.
+
+This patch adds an is_otg_enabled() check before scheduling the
+switch-off timer in disconnect path, supporting a "classic host"
+mode where SRP is unavailable.
+
+[ dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org: tweak patch description ]
+
+Signed-off-by: Ajay Kumar Gupta <ajay.gupta-l0cyMroinI0@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh-l3A5Bk7waGM@public.gmane.org>
+---
+ drivers/usb/musb/musb_core.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index af77e46..338cd16 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -769,7 +769,7 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
+ 		case OTG_STATE_A_SUSPEND:
+ 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
+ 			musb_root_disconnect(musb);
+-			if (musb->a_wait_bcon != 0)
++			if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
+ 				musb_platform_try_idle(musb, jiffies
+ 					+ msecs_to_jiffies(musb->a_wait_bcon));
+ 			break;
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0002-USB-composite-avoid-inconsistent-lock-state.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0002-USB-composite-avoid-inconsistent-lock-state.patch
new file mode 100644
index 0000000000..5cb7bcb065
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0002-USB-composite-avoid-inconsistent-lock-state.patch
@@ -0,0 +1,76 @@
+From 83eb44b1c84f99d9a5c67612bd94b4ed7c43f64c Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <felipe.balbi-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
+Date: Tue, 24 Mar 2009 17:22:49 -0700
+Subject: [PATCH] USB: composite: avoid inconsistent lock state
+
+Avoid the following INFO from lock debugging:
+
+[  369.126112] =================================
+[  369.132063] [ INFO: inconsistent lock state ]
+[  369.136457] 2.6.28-maemo1 #1
+[  369.139387] ---------------------------------
+[  369.143782] inconsistent {hardirq-on-W} -> {in-hardirq-W} usage.
+[  369.149855] swapper/0 [HC1[1]:SC0[0]:HE0:SE1] takes:
+[  369.154890]  (&cdev->lock){+-..}, at: [<bf1979f0>] composite_disconnect+0x1c/0]
+[  369.163404] {hardirq-on-W} state was registered at:
+[  369.168348]   [<c00788a8>] __lock_acquire+0x5d0/0x7d8
+[  369.173506]   [<c0078b14>] lock_acquire+0x64/0x78
+[  369.178266]   [<c0263a34>] _spin_lock+0x4c/0x80
+[  369.182905]   [<bf19597c>] usb_function_deactivate+0x20/0x70 [g_nokia]
+[  369.189527]   [<bf1a0a88>] 0xbf1a0a88
+[  369.193281]   [<bf19f450>] 0xbf19f450
+[  369.197004]   [<bf19fa3c>] 0xbf19fa3c
+[  369.200758]   [<bf1a03a0>] 0xbf1a03a0
+[  369.204481]   [<bf19f254>] 0xbf19f254
+[  369.208204]   [<bf1a0158>] 0xbf1a0158
+[  369.211927]   [<bf1a130c>] 0xbf1a130c
+[  369.215650]   [<c01c21f0>] usb_gadget_register_driver+0x12c/0x28c
+[  369.221846]   [<bf1a06bc>] 0xbf1a06bc
+[  369.225569]   [<bf1a06e8>] 0xbf1a06e8
+[  369.229322]   [<c002c2dc>] __exception_text_end+0x64/0x19c
+[  369.234877]   [<c0081628>] sys_init_module+0x9c/0x194
+[  369.240004]   [<c002c8e0>] ret_fast_syscall+0x0/0x2c
+[  369.245039]   [<ffffffff>] 0xffffffff
+[  369.248793] irq event stamp: 218356
+[  369.252302] hardirqs last  enabled at (218355): [<c003a77c>] omap3_enter_idle+8
+[  369.260420] hardirqs last disabled at (218356): [<c0264774>] __irq_svc+0x34/0x0
+[  369.267927] softirqs last  enabled at (218348): [<c00585a4>] __do_softirq+0x134
+[  369.275892] softirqs last disabled at (218335): [<c005899c>] irq_exit+0x60/0xb0
+[  369.283308]
+[  369.283308] other info that might help us debug this:
+[  369.289930] no locks held by swapper/0.
+
+Cc: David Brownell <david-b-yBeKhBN/0LDR7s880joybQ@public.gmane.org>
+Signed-off-by: Felipe Balbi <felipe.balbi-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh-l3A5Bk7waGM@public.gmane.org>
+---
+ drivers/usb/gadget/composite.c |    5 +++--
+ 1 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
+index 5d11c29..40f1da7 100644
+--- a/drivers/usb/gadget/composite.c
++++ b/drivers/usb/gadget/composite.c
+@@ -149,16 +149,17 @@ done:
+ int usb_function_deactivate(struct usb_function *function)
+ {
+ 	struct usb_composite_dev	*cdev = function->config->cdev;
++	unsigned long			flags;
+ 	int				status = 0;
+ 
+-	spin_lock(&cdev->lock);
++	spin_lock_irqsave(&cdev->lock, flags);
+ 
+ 	if (cdev->deactivations == 0)
+ 		status = usb_gadget_disconnect(cdev->gadget);
+ 	if (status == 0)
+ 		cdev->deactivations++;
+ 
+-	spin_unlock(&cdev->lock);
++	spin_unlock_irqrestore(&cdev->lock, flags);
+ 	return status;
+ }
+ 
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0003-USB-musb-NAK-timeout-scheme-on-bulk-RX-endpoint.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0003-USB-musb-NAK-timeout-scheme-on-bulk-RX-endpoint.patch
new file mode 100644
index 0000000000..fadad9e44a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0003-USB-musb-NAK-timeout-scheme-on-bulk-RX-endpoint.patch
@@ -0,0 +1,218 @@
+From ba7b26e69f4bb41f10be444c5fded853330f82b5 Mon Sep 17 00:00:00 2001
+From: Ajay Kumar Gupta <ajay.gupta-l0cyMroinI0@public.gmane.org>
+Date: Tue, 24 Mar 2009 17:22:51 -0700
+Subject: [PATCH] USB: musb: NAK timeout scheme on bulk RX endpoint
+
+Fixes endpoint starvation issue when more than one bulk QH is
+multiplexed on the reserved bulk RX endpoint, which is normal
+for cases like serial and ethernet adapters.
+
+This patch sets the NAK timeout interval for such QHs, and when
+a timeout triggers the next QH will be scheduled.  (This resembles
+the bulk scheduling done in hardware by EHCI, OHCI, and UHCI.)
+
+This scheme doesn't work for devices which are connected to a
+high to full speed tree (transaction translator) as there is
+no NAK timeout interrupt from the musb controller from such
+devices.
+
+Tested with PIO, Inventra DMA, CPPI DMA.
+
+[ dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org:  fold in start_urb() update;
+  clarify only for bulk RX; don't accidentally clear WZC bits ]
+
+Signed-off-by: Ajay Kumar Gupta <ajay.gupta-l0cyMroinI0@public.gmane.org>
+Cc: Felipe Balbi <felipe.balbi-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh-l3A5Bk7waGM@public.gmane.org>
+---
+ drivers/usb/musb/musb_host.c |  112 ++++++++++++++++++++++++++++++++----------
+ 1 files changed, 85 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index 6dbbd07..bd1d5ae 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -64,11 +64,8 @@
+  *
+  * - DMA (Mentor/OMAP) ...has at least toggle update problems
+  *
+- * - Still no traffic scheduling code to make NAKing for bulk or control
+- *   transfers unable to starve other requests; or to make efficient use
+- *   of hardware with periodic transfers.  (Note that network drivers
+- *   commonly post bulk reads that stay pending for a long time; these
+- *   would make very visible trouble.)
++ * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
++ *   starvation ... nothing yet for TX, interrupt, or bulk.
+  *
+  * - Not tested with HNP, but some SRP paths seem to behave.
+  *
+@@ -88,11 +85,8 @@
+  *
+  * CONTROL transfers all go through ep0.  BULK ones go through dedicated IN
+  * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
+- *
+  * (Yes, bulk _could_ use more of the endpoints than that, and would even
+- * benefit from it ... one remote device may easily be NAKing while others
+- * need to perform transfers in that same direction.  The same thing could
+- * be done in software though, assuming dma cooperates.)
++ * benefit from it.)
+  *
+  * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
+  * So far that scheduling is both dumb and optimistic:  the endpoint will be
+@@ -201,8 +195,9 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
+ 		len = urb->iso_frame_desc[0].length;
+ 		break;
+ 	default:		/* bulk, interrupt */
+-		buf = urb->transfer_buffer;
+-		len = urb->transfer_buffer_length;
++		/* actual_length may be nonzero on retry paths */
++		buf = urb->transfer_buffer + urb->actual_length;
++		len = urb->transfer_buffer_length - urb->actual_length;
+ 	}
+ 
+ 	DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
+@@ -1045,7 +1040,8 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
+ 
+ 		/* NOTE:  this code path would be a good place to PAUSE a
+ 		 * control transfer, if another one is queued, so that
+-		 * ep0 is more likely to stay busy.
++		 * ep0 is more likely to stay busy.  That's already done
++		 * for bulk RX transfers.
+ 		 *
+ 		 * if (qh->ring.next != &musb->control), then
+ 		 * we have a candidate... NAKing is *NOT* an error
+@@ -1197,6 +1193,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
+ 		/* NOTE:  this code path would be a good place to PAUSE a
+ 		 * transfer, if there's some other (nonperiodic) tx urb
+ 		 * that could use this fifo.  (dma complicates it...)
++		 * That's already done for bulk RX transfers.
+ 		 *
+ 		 * if (bulk && qh->ring.next != &musb->out_bulk), then
+ 		 * we have a candidate... NAKing is *NOT* an error
+@@ -1358,6 +1355,50 @@ finish:
+ 
+ #endif
+ 
++/* Schedule next QH from musb->in_bulk and move the current qh to
++ * the end; avoids starvation for other endpoints.
++ */
++static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
++{
++	struct dma_channel	*dma;
++	struct urb		*urb;
++	void __iomem		*mbase = musb->mregs;
++	void __iomem		*epio = ep->regs;
++	struct musb_qh		*cur_qh, *next_qh;
++	u16			rx_csr;
++
++	musb_ep_select(mbase, ep->epnum);
++	dma = is_dma_capable() ? ep->rx_channel : NULL;
++
++	/* clear nak timeout bit */
++	rx_csr = musb_readw(epio, MUSB_RXCSR);
++	rx_csr |= MUSB_RXCSR_H_WZC_BITS;
++	rx_csr &= ~MUSB_RXCSR_DATAERROR;
++	musb_writew(epio, MUSB_RXCSR, rx_csr);
++
++	cur_qh = first_qh(&musb->in_bulk);
++	if (cur_qh) {
++		urb = next_urb(cur_qh);
++		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
++			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
++			musb->dma_controller->channel_abort(dma);
++			urb->actual_length += dma->actual_len;
++			dma->actual_len = 0L;
++		}
++		musb_save_toggle(ep, 1, urb);
++
++		/* move cur_qh to end of queue */
++		list_move_tail(&cur_qh->ring, &musb->in_bulk);
++
++		/* get the next qh from musb->in_bulk */
++		next_qh = first_qh(&musb->in_bulk);
++
++		/* set rx_reinit and schedule the next qh */
++		ep->rx_reinit = 1;
++		musb_start_urb(musb, 1, next_qh);
++	}
++}
++
+ /*
+  * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
+  * and high-bandwidth IN transfer cases.
+@@ -1421,18 +1462,26 @@ void musb_host_rx(struct musb *musb, u8 epnum)
+ 	} else if (rx_csr & MUSB_RXCSR_DATAERROR) {
+ 
+ 		if (USB_ENDPOINT_XFER_ISOC != qh->type) {
+-			/* NOTE this code path would be a good place to PAUSE a
+-			 * transfer, if there's some other (nonperiodic) rx urb
+-			 * that could use this fifo.  (dma complicates it...)
++			DBG(6, "RX end %d NAK timeout\n", epnum);
++
++			/* NOTE: NAKing is *NOT* an error, so we want to
++			 * continue.  Except ... if there's a request for
++			 * another QH, use that instead of starving it.
+ 			 *
+-			 * if (bulk && qh->ring.next != &musb->in_bulk), then
+-			 * we have a candidate... NAKing is *NOT* an error
++			 * Devices like Ethernet and serial adapters keep
++			 * reads posted at all times, which will starve
++			 * other devices without this logic.
+ 			 */
+-			DBG(6, "RX end %d NAK timeout\n", epnum);
++			if (usb_pipebulk(urb->pipe)
++					&& qh->mux == 1
++					&& !list_is_singular(&musb->in_bulk)) {
++				musb_bulk_rx_nak_timeout(musb, hw_ep);
++				return;
++			}
+ 			musb_ep_select(mbase, epnum);
+-			musb_writew(epio, MUSB_RXCSR,
+-					MUSB_RXCSR_H_WZC_BITS
+-					| MUSB_RXCSR_H_REQPKT);
++			rx_csr |= MUSB_RXCSR_H_WZC_BITS;
++			rx_csr &= ~MUSB_RXCSR_DATAERROR;
++			musb_writew(epio, MUSB_RXCSR, rx_csr);
+ 
+ 			goto finish;
+ 		} else {
+@@ -1756,6 +1805,17 @@ static int musb_schedule(
+ 			head = &musb->in_bulk;
+ 		else
+ 			head = &musb->out_bulk;
++
++		/* Enable bulk RX NAK timeout scheme when bulk requests are
++		 * multiplexed.  This scheme doen't work in high speed to full
++		 * speed scenario as NAK interrupts are not coming from a
++		 * full speed device connected to a high speed device.
++		 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
++		 * 4 (8 frame or 8ms) for FS device.
++		 */
++		if (is_in && qh->dev)
++			qh->intv_reg =
++				(USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
+ 		goto success;
+ 	} else if (best_end < 0) {
+ 		return -ENOSPC;
+@@ -1888,13 +1948,11 @@ static int musb_urb_enqueue(
+ 		 *
+ 		 * The downside of disabling this is that transfer scheduling
+ 		 * gets VERY unfair for nonperiodic transfers; a misbehaving
+-		 * peripheral could make that hurt.  Or for reads, one that's
+-		 * perfectly normal:  network and other drivers keep reads
+-		 * posted at all times, having one pending for a week should
+-		 * be perfectly safe.
++		 * peripheral could make that hurt.  That's perfectly normal
++		 * for reads from network or serial adapters ... so we have
++		 * partial NAKlimit support for bulk RX.
+ 		 *
+-		 * The upside of disabling it is avoidng transfer scheduling
+-		 * code to put this aside for while.
++		 * The upside of disabling it is simpler transfer scheduling.
+ 		 */
+ 		interval = 0;
+ 	}
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0004-USB-musb-rewrite-host-periodic-endpoint-allocation.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0004-USB-musb-rewrite-host-periodic-endpoint-allocation.patch
new file mode 100644
index 0000000000..438f11cf7a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0004-USB-musb-rewrite-host-periodic-endpoint-allocation.patch
@@ -0,0 +1,106 @@
+From 9ebf351bcd28a89a0b1ba8d0496fffbc72421611 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Tue, 24 Mar 2009 17:22:50 -0700
+Subject: [PATCH] USB: musb: rewrite host periodic endpoint allocation
+
+The current MUSB host code doesn't make use of all the available
+FIFOs in for periodic transfers since it wrongly assumes the RX
+and TX sides of any given hw_ep always share one FIFO.
+
+Change:  use 'in_qh' and 'out_qh' fields of the 'struct musb_hw_ep'
+to check the endpoint's business; get rid of the now-unused 'periodic'
+array in the 'struct musb'.  Also optimize a loop induction variable
+in the endpoint lookup code.
+
+(Based on a previous patch from Ajay Kumar Gupta <ajay.gupta-l0cyMroinI0@public.gmane.org>)
+
+[ dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org: clarify description and origin
+  of this fix; whitespace ]
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Cc: Felipe Balbi <felipe.balbi-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh-l3A5Bk7waGM@public.gmane.org>
+---
+ drivers/usb/musb/musb_core.h |    1 -
+ drivers/usb/musb/musb_host.c |   28 +++++++++++-----------------
+ 2 files changed, 11 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
+index 630946a..adf1806 100644
+--- a/drivers/usb/musb/musb_core.h
++++ b/drivers/usb/musb/musb_core.h
+@@ -331,7 +331,6 @@ struct musb {
+ 	struct list_head	control;	/* of musb_qh */
+ 	struct list_head	in_bulk;	/* of musb_qh */
+ 	struct list_head	out_bulk;	/* of musb_qh */
+-	struct musb_qh		*periodic[32];	/* tree of interrupt+iso */
+ #endif
+ 
+ 	/* called with IRQs blocked; ON/nonzero implies starting a session,
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index bd1d5ae..499c431 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -390,7 +390,6 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
+ 			 * de-allocated if it's tracked and allocated;
+ 			 * and where we'd update the schedule tree...
+ 			 */
+-			musb->periodic[ep->epnum] = NULL;
+ 			kfree(qh);
+ 			qh = NULL;
+ 			break;
+@@ -1760,31 +1759,27 @@ static int musb_schedule(
+ 
+ 	/* else, periodic transfers get muxed to other endpoints */
+ 
+-	/* FIXME this doesn't consider direction, so it can only
+-	 * work for one half of the endpoint hardware, and assumes
+-	 * the previous cases handled all non-shared endpoints...
+-	 */
+-
+-	/* we know this qh hasn't been scheduled, so all we need to do
++	/*
++	 * We know this qh hasn't been scheduled, so all we need to do
+ 	 * is choose which hardware endpoint to put it on ...
+ 	 *
+ 	 * REVISIT what we really want here is a regular schedule tree
+-	 * like e.g. OHCI uses, but for now musb->periodic is just an
+-	 * array of the _single_ logical endpoint associated with a
+-	 * given physical one (identity mapping logical->physical).
+-	 *
+-	 * that simplistic approach makes TT scheduling a lot simpler;
+-	 * there is none, and thus none of its complexity...
++	 * like e.g. OHCI uses.
+ 	 */
+ 	best_diff = 4096;
+ 	best_end = -1;
+ 
+-	for (epnum = 1; epnum < musb->nr_endpoints; epnum++) {
++	for (epnum = 1, hw_ep = musb->endpoints + 1;
++			epnum < musb->nr_endpoints;
++			epnum++, hw_ep++) {
+ 		int	diff;
+ 
+-		if (musb->periodic[epnum])
++		if (is_in || hw_ep->is_shared_fifo) {
++			if (hw_ep->in_qh  != NULL)
++				continue;
++		} else	if (hw_ep->out_qh != NULL)
+ 			continue;
+-		hw_ep = &musb->endpoints[epnum];
++
+ 		if (hw_ep == musb->bulk_ep)
+ 			continue;
+ 
+@@ -1824,7 +1819,6 @@ static int musb_schedule(
+ 	idle = 1;
+ 	qh->mux = 0;
+ 	hw_ep = musb->endpoints + best_end;
+-	musb->periodic[best_end] = qh;
+ 	DBG(4, "qh %p periodic slot %d\n", qh, best_end);
+ success:
+ 	if (head) {
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0005-USB-TWL-disable-VUSB-regulators-when-cable-unplugg.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0005-USB-TWL-disable-VUSB-regulators-when-cable-unplugg.patch
new file mode 100644
index 0000000000..db3481b87b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0005-USB-TWL-disable-VUSB-regulators-when-cable-unplugg.patch
@@ -0,0 +1,181 @@
+From 60e7ce93befe795357db05001fe4caab522a421d Mon Sep 17 00:00:00 2001
+From: Jouni Hogander <jouni.hogander-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
+Date: Tue, 24 Mar 2009 17:22:57 -0700
+Subject: [PATCH] USB: TWL: disable VUSB regulators when cable unplugged
+
+This patch disables USB regulators VUSB1V5, VUSB1V8, and VUSB3V1
+when the USB cable is unplugged to reduce power consumption.
+Added a depencency from twl4030 usb driver to TWL_REGULATOR.
+
+Signed-off-by: Jouni Hogander <jouni.hogander-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
+Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi-sMOQStClEysAvxtiuMwx3w@public.gmane.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh-l3A5Bk7waGM@public.gmane.org>
+---
+ drivers/usb/otg/Kconfig       |    2 +-
+ drivers/usb/otg/twl4030-usb.c |   73 ++++++++++++++++++++++++++++++++++++-----
+ 2 files changed, 65 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
+index ee55b44..5790a5b 100644
+--- a/drivers/usb/otg/Kconfig
++++ b/drivers/usb/otg/Kconfig
+@@ -43,7 +43,7 @@ config ISP1301_OMAP
+ 
+ config TWL4030_USB
+ 	tristate "TWL4030 USB Transceiver Driver"
+-	depends on TWL4030_CORE
++	depends on TWL4030_CORE && REGULATOR_TWL4030
+ 	select USB_OTG_UTILS
+ 	help
+ 	  Enable this to support the USB OTG transceiver on TWL4030
+diff --git a/drivers/usb/otg/twl4030-usb.c b/drivers/usb/otg/twl4030-usb.c
+index 416e441..d9478d0 100644
+--- a/drivers/usb/otg/twl4030-usb.c
++++ b/drivers/usb/otg/twl4030-usb.c
+@@ -34,6 +34,8 @@
+ #include <linux/delay.h>
+ #include <linux/usb/otg.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/regulator/consumer.h>
++#include <linux/err.h>
+ 
+ 
+ /* Register defines */
+@@ -246,6 +248,11 @@ struct twl4030_usb {
+ 	struct otg_transceiver	otg;
+ 	struct device		*dev;
+ 
++	/* TWL4030 internal USB regulator supplies */
++	struct regulator	*usb1v5;
++	struct regulator	*usb1v8;
++	struct regulator	*usb3v1;
++
+ 	/* for vbus reporting with irqs disabled */
+ 	spinlock_t		lock;
+ 
+@@ -434,6 +441,18 @@ static void twl4030_phy_power(struct twl4030_usb *twl, int on)
+ 
+ 	pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
+ 	if (on) {
++		regulator_enable(twl->usb3v1);
++		regulator_enable(twl->usb1v8);
++		/*
++		 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
++		 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
++		 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
++		 * SLEEP. We work around this by clearing the bit after usv3v1
++		 * is re-activated. This ensures that VUSB3V1 is really active.
++		 */
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0,
++							VUSB_DEDICATED2);
++		regulator_enable(twl->usb1v5);
+ 		pwr &= ~PHY_PWR_PHYPWD;
+ 		WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
+ 		twl4030_usb_write(twl, PHY_CLK_CTRL,
+@@ -443,6 +462,9 @@ static void twl4030_phy_power(struct twl4030_usb *twl, int on)
+ 	} else  {
+ 		pwr |= PHY_PWR_PHYPWD;
+ 		WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
++		regulator_disable(twl->usb1v5);
++		regulator_disable(twl->usb1v8);
++		regulator_disable(twl->usb3v1);
+ 	}
+ }
+ 
+@@ -468,7 +490,7 @@ static void twl4030_phy_resume(struct twl4030_usb *twl)
+ 	twl->asleep = 0;
+ }
+ 
+-static void twl4030_usb_ldo_init(struct twl4030_usb *twl)
++static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
+ {
+ 	/* Enable writing to power configuration registers */
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0xC0, PROTECT_KEY);
+@@ -480,20 +502,45 @@ static void twl4030_usb_ldo_init(struct twl4030_usb *twl)
+ 	/* input to VUSB3V1 LDO is from VBAT, not VBUS */
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
+ 
+-	/* turn on 3.1V regulator */
+-	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB3V1_DEV_GRP);
++	/* Initialize 3.1V regulator */
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
++
++	twl->usb3v1 = regulator_get(twl->dev, "usb3v1");
++	if (IS_ERR(twl->usb3v1))
++		return -ENODEV;
++
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
+ 
+-	/* turn on 1.5V regulator */
+-	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB1V5_DEV_GRP);
++	/* Initialize 1.5V regulator */
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
++
++	twl->usb1v5 = regulator_get(twl->dev, "usb1v5");
++	if (IS_ERR(twl->usb1v5))
++		goto fail1;
++
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
+ 
+-	/* turn on 1.8V regulator */
+-	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB1V8_DEV_GRP);
++	/* Initialize 1.8V regulator */
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
++
++	twl->usb1v8 = regulator_get(twl->dev, "usb1v8");
++	if (IS_ERR(twl->usb1v8))
++		goto fail2;
++
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
+ 
+ 	/* disable access to power configuration registers */
+ 	twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, PROTECT_KEY);
++
++	return 0;
++
++fail2:
++	regulator_put(twl->usb1v5);
++	twl->usb1v5 = NULL;
++fail1:
++	regulator_put(twl->usb3v1);
++	twl->usb3v1 = NULL;
++	return -ENODEV;
+ }
+ 
+ static ssize_t twl4030_usb_vbus_show(struct device *dev,
+@@ -598,7 +645,7 @@ static int __init twl4030_usb_probe(struct platform_device *pdev)
+ {
+ 	struct twl4030_usb_data *pdata = pdev->dev.platform_data;
+ 	struct twl4030_usb	*twl;
+-	int			status;
++	int			status, err;
+ 
+ 	if (!pdata) {
+ 		dev_dbg(&pdev->dev, "platform_data not available\n");
+@@ -622,7 +669,12 @@ static int __init twl4030_usb_probe(struct platform_device *pdev)
+ 	/* init spinlock for workqueue */
+ 	spin_lock_init(&twl->lock);
+ 
+-	twl4030_usb_ldo_init(twl);
++	err = twl4030_usb_ldo_init(twl);
++	if (err) {
++		dev_err(&pdev->dev, "ldo init failed\n");
++		kfree(twl);
++		return err;
++	}
+ 	otg_set_transceiver(&twl->otg);
+ 
+ 	platform_set_drvdata(pdev, twl);
+@@ -688,6 +740,9 @@ static int __exit twl4030_usb_remove(struct platform_device *pdev)
+ 	twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
+ 
+ 	twl4030_phy_power(twl, 0);
++	regulator_put(twl->usb1v5);
++	regulator_put(twl->usb1v8);
++	regulator_put(twl->usb3v1);
+ 
+ 	kfree(twl);
+ 
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0006-USB-gadget-composite-device-level-suspend-resume-h.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0006-USB-gadget-composite-device-level-suspend-resume-h.patch
new file mode 100644
index 0000000000..3f49a4d636
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0006-USB-gadget-composite-device-level-suspend-resume-h.patch
@@ -0,0 +1,84 @@
+From 7eef82d231578140c6000d04846a48bdaf341a65 Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Tue, 24 Mar 2009 17:23:19 -0700
+Subject: [PATCH] USB: gadget: composite device-level suspend/resume hooks
+
+Address one open question in the composite gadget framework:
+Yes, we should have device-level suspend/resume callbacks
+in addition to the function-level ones.  We have at least one
+scenario (with gadget zero in OTG test mode) that's awkward
+to handle without it.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Cc: Felipe Balbi <felipe.balbi-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh-l3A5Bk7waGM@public.gmane.org>
+---
+ drivers/usb/gadget/composite.c |    8 ++++++--
+ include/linux/usb/composite.h  |    8 ++++++++
+ 2 files changed, 14 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
+index 40f1da7..59e8523 100644
+--- a/drivers/usb/gadget/composite.c
++++ b/drivers/usb/gadget/composite.c
+@@ -1014,7 +1014,7 @@ composite_suspend(struct usb_gadget *gadget)
+ 	struct usb_composite_dev	*cdev = get_gadget_data(gadget);
+ 	struct usb_function		*f;
+ 
+-	/* REVISIT:  should we have config and device level
++	/* REVISIT:  should we have config level
+ 	 * suspend/resume callbacks?
+ 	 */
+ 	DBG(cdev, "suspend\n");
+@@ -1024,6 +1024,8 @@ composite_suspend(struct usb_gadget *gadget)
+ 				f->suspend(f);
+ 		}
+ 	}
++	if (composite->suspend)
++		composite->suspend(cdev);
+ }
+ 
+ static void
+@@ -1032,10 +1034,12 @@ composite_resume(struct usb_gadget *gadget)
+ 	struct usb_composite_dev	*cdev = get_gadget_data(gadget);
+ 	struct usb_function		*f;
+ 
+-	/* REVISIT:  should we have config and device level
++	/* REVISIT:  should we have config level
+ 	 * suspend/resume callbacks?
+ 	 */
+ 	DBG(cdev, "resume\n");
++	if (composite->resume)
++		composite->resume(cdev);
+ 	if (cdev->config) {
+ 		list_for_each_entry(f, &cdev->config->functions, list) {
+ 			if (f->resume)
+diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
+index 935c380..acd7b0f 100644
+--- a/include/linux/usb/composite.h
++++ b/include/linux/usb/composite.h
+@@ -244,6 +244,10 @@ int usb_add_config(struct usb_composite_dev *,
+  *	value; it should return zero on successful initialization.
+  * @unbind: Reverses @bind(); called as a side effect of unregistering
+  *	this driver.
++ * @suspend: Notifies when the host stops sending USB traffic,
++ *	after function notifications
++ * @resume: Notifies configuration when the host restarts USB traffic,
++ *	before function notifications
+  *
+  * Devices default to reporting self powered operation.  Devices which rely
+  * on bus powered operation should report this in their @bind() method.
+@@ -268,6 +272,10 @@ struct usb_composite_driver {
+ 
+ 	int			(*bind)(struct usb_composite_dev *);
+ 	int			(*unbind)(struct usb_composite_dev *);
++
++	/* global suspend hooks */
++	void			(*suspend)(struct usb_composite_dev *);
++	void			(*resume)(struct usb_composite_dev *);
+ };
+ 
+ extern int usb_composite_register(struct usb_composite_driver *);
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0007-usb-gadget-fix-ethernet-link-reports-to-ethtool.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0007-usb-gadget-fix-ethernet-link-reports-to-ethtool.patch
new file mode 100644
index 0000000000..a89bc2ff5c
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0007-usb-gadget-fix-ethernet-link-reports-to-ethtool.patch
@@ -0,0 +1,47 @@
+From 00c4bd07a64061ec9ab9c35f5bf01ec6187138f4 Mon Sep 17 00:00:00 2001
+From: Jonathan McDowell <noodles-4QvXXjU8Dv4@public.gmane.org>
+Date: Thu, 26 Mar 2009 00:45:27 -0700
+Subject: [PATCH] usb gadget: fix ethernet link reports to ethtool
+
+The g_ether USB gadget driver currently decides whether or not there's a
+link to report back for eth_get_link based on if the USB link speed is
+set. The USB gadget speed is however often set even before the device is
+enumerated. It seems more sensible to only report a "link" if we're
+actually connected to a host that wants to talk to us. The patch below
+does this for me - tested with the PXA27x UDC driver.
+
+Signed-Off-By: Jonathan McDowell <noodles-4QvXXjU8Dv4@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/gadget/u_ether.c |    8 +-------
+ 1 files changed, 1 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/usb/gadget/u_ether.c b/drivers/usb/gadget/u_ether.c
+index 96d65ca..4007770 100644
+--- a/drivers/usb/gadget/u_ether.c
++++ b/drivers/usb/gadget/u_ether.c
+@@ -175,12 +175,6 @@ static void eth_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *p)
+ 	strlcpy(p->bus_info, dev_name(&dev->gadget->dev), sizeof p->bus_info);
+ }
+ 
+-static u32 eth_get_link(struct net_device *net)
+-{
+-	struct eth_dev	*dev = netdev_priv(net);
+-	return dev->gadget->speed != USB_SPEED_UNKNOWN;
+-}
+-
+ /* REVISIT can also support:
+  *   - WOL (by tracking suspends and issuing remote wakeup)
+  *   - msglevel (implies updated messaging)
+@@ -189,7 +183,7 @@ static u32 eth_get_link(struct net_device *net)
+ 
+ static struct ethtool_ops ops = {
+ 	.get_drvinfo = eth_get_drvinfo,
+-	.get_link = eth_get_link
++	.get_link = ethtool_op_get_link,
+ };
+ 
+ static void defer_kevent(struct eth_dev *dev, int flag)
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0008-usb-musb_host-minor-enqueue-locking-fix-v2.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0008-usb-musb_host-minor-enqueue-locking-fix-v2.patch
new file mode 100644
index 0000000000..8627825b5a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0008-usb-musb_host-minor-enqueue-locking-fix-v2.patch
@@ -0,0 +1,60 @@
+From c3b527a21104b6bb61558fba6c65aa80f63e0772 Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Thu, 26 Mar 2009 17:36:57 -0700
+Subject: [PATCH] usb: musb_host, minor enqueue locking fix (v2)
+
+Someone noted that the enqueue path used an unlocked access
+for usb_host_endpoint->hcpriv ... fix that, by being safe
+and always accessing it under spinlock protection.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_host.c |   17 ++++++++---------
+ 1 files changed, 8 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index 499c431..ff09595 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -1841,7 +1841,7 @@ static int musb_urb_enqueue(
+ 	unsigned long			flags;
+ 	struct musb			*musb = hcd_to_musb(hcd);
+ 	struct usb_host_endpoint	*hep = urb->ep;
+-	struct musb_qh			*qh = hep->hcpriv;
++	struct musb_qh			*qh;
+ 	struct usb_endpoint_descriptor	*epd = &hep->desc;
+ 	int				ret;
+ 	unsigned			type_reg;
+@@ -1853,22 +1853,21 @@ static int musb_urb_enqueue(
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+ 	ret = usb_hcd_link_urb_to_ep(hcd, urb);
++	qh = ret ? NULL : hep->hcpriv;
++	if (qh)
++		urb->hcpriv = qh;
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+-	if (ret)
+-		return ret;
+ 
+ 	/* DMA mapping was already done, if needed, and this urb is on
+-	 * hep->urb_list ... so there's little to do unless hep wasn't
+-	 * yet scheduled onto a live qh.
++	 * hep->urb_list now ... so we're done, unless hep wasn't yet
++	 * scheduled onto a live qh.
+ 	 *
+ 	 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
+ 	 * disabled, testing for empty qh->ring and avoiding qh setup costs
+ 	 * except for the first urb queued after a config change.
+ 	 */
+-	if (qh) {
+-		urb->hcpriv = qh;
+-		return 0;
+-	}
++	if (qh || ret)
++		return ret;
+ 
+ 	/* Allocate and initialize qh, minimizing the work done each time
+ 	 * hw_ep gets reprogrammed, or with irqs blocked.  Then schedule it.
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0009-usb-musb_host-fix-ep0-fifo-flushing.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0009-usb-musb_host-fix-ep0-fifo-flushing.patch
new file mode 100644
index 0000000000..09fc0a17d0
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0009-usb-musb_host-fix-ep0-fifo-flushing.patch
@@ -0,0 +1,93 @@
+From 48ce47b15bfd420982ee275c595a9139eb6fabf7 Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Thu, 26 Mar 2009 17:38:30 -0700
+Subject: [PATCH] usb: musb_host, fix ep0 fifo flushing
+
+The MUSB host side can't share generic TX FIFO flush logic
+with EP0; the EP0 TX status register bits are different
+from those for other entpoints.
+
+Resolve this issue by providing a new EP0-specific routine
+to flush and reset the FIFO, which pays careful attention to
+restrictions listed in the latest programmer's guide.  This
+gets rid of an open issue whereby the usbtest control write
+test (#14) failed.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_host.c |   38 +++++++++++++++++++++++++-------------
+ 1 files changed, 25 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index ff09595..a5d75aa 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -125,6 +125,29 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
+ 	}
+ }
+ 
++static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
++{
++	void __iomem	*epio = ep->regs;
++	u16		csr;
++	int		retries = 5;
++
++	/* scrub any data left in the fifo */
++	do {
++		csr = musb_readw(epio, MUSB_TXCSR);
++		if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
++			break;
++		musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
++		csr = musb_readw(epio, MUSB_TXCSR);
++		udelay(10);
++	} while (--retries);
++
++	WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
++			ep->epnum, csr);
++
++	/* and reset for the next transfer */
++	musb_writew(epio, MUSB_TXCSR, 0);
++}
++
+ /*
+  * Start transmit. Caller is responsible for locking shared resources.
+  * musb must be locked.
+@@ -693,11 +716,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 			musb_writew(epio, MUSB_TXCSR, csr);
+ 			csr = musb_readw(epio, MUSB_TXCSR);
+ 		} else {
+-			/* endpoint 0: just flush */
+-			musb_writew(epio, MUSB_CSR0,
+-				csr | MUSB_CSR0_FLUSHFIFO);
+-			musb_writew(epio, MUSB_CSR0,
+-				csr | MUSB_CSR0_FLUSHFIFO);
++			musb_h_ep0_flush_fifo(hw_ep);
+ 		}
+ 
+ 		/* target addr and (for multipoint) hub addr/port */
+@@ -1063,11 +1082,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
+ 			csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
+ 			musb_writew(epio, MUSB_CSR0, csr);
+ 		} else {
+-			csr |= MUSB_CSR0_FLUSHFIFO;
+-			musb_writew(epio, MUSB_CSR0, csr);
+-			musb_writew(epio, MUSB_CSR0, csr);
+-			csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
+-			musb_writew(epio, MUSB_CSR0, csr);
++			musb_h_ep0_flush_fifo(hw_ep);
+ 		}
+ 
+ 		musb_writeb(epio, MUSB_NAKLIMIT0, 0);
+@@ -1081,9 +1096,6 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
+ 		 * SHOULD NEVER HAPPEN! */
+ 		ERR("no URB for end 0\n");
+ 
+-		musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO);
+-		musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO);
+-		musb_writew(epio, MUSB_CSR0, 0);
+ 
+ 		goto done;
+ 	}
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0010-musb-sanitize-clearing-TXCSR-DMA-bits-take-2.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0010-musb-sanitize-clearing-TXCSR-DMA-bits-take-2.patch
new file mode 100644
index 0000000000..bcbe3bbe39
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0010-musb-sanitize-clearing-TXCSR-DMA-bits-take-2.patch
@@ -0,0 +1,361 @@
+From c99f4a68268801a2e2ffbef9766c3ac89e4fb22c Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Thu, 26 Mar 2009 18:27:47 -0700
+Subject: [PATCH] musb: sanitize clearing TXCSR DMA bits (take 2)
+
+The MUSB code clears TXCSR_DMAMODE incorrectly in several
+places, either asserting that TXCSR_DMAENAB is clear (when
+sometimes it isn't) or clearing both bits together.  Recent
+versions of the programmer's guide require DMAENAB to be
+cleared first, although some older ones didn't.
+
+Fix this and while at it:
+
+ - In musb_gadget::txstate(), stop clearing the AUTOSET
+   and DMAMODE bits for the CPPI case since they never
+   get set anyway (the former bit is reserved on DaVinci);
+   but do clear the DMAENAB bit on the DMA error path.
+
+ - In musb_host::musb_ep_program(), remove the duplicate
+   DMA controller specific code code clearing the TXCSR
+   previous state, add the code to clear TXCSR DMA bits
+   on the Inventra DMA error path, to replace such code
+   (executed late) on the PIO path.
+
+ - In musbhsdma::dma_channel_abort()/dma_controller_irq(),
+   add/use the 'offset' variable to avoid MUSB_EP_OFFSET()
+   invocations on every RXCSR/TXCSR access.
+
+[dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org: don't introduce CamelCase,
+shrink diff]
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_gadget.c |   33 +++++++++++------
+ drivers/usb/musb/musb_host.c   |   79 ++++++++++++++++------------------------
+ drivers/usb/musb/musbhsdma.c   |   59 ++++++++++++++++++------------
+ 3 files changed, 90 insertions(+), 81 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
+index c7ebd08..f79440c 100644
+--- a/drivers/usb/musb/musb_gadget.c
++++ b/drivers/usb/musb/musb_gadget.c
+@@ -165,9 +165,15 @@ static void nuke(struct musb_ep *ep, const int status)
+ 	if (is_dma_capable() && ep->dma) {
+ 		struct dma_controller	*c = ep->musb->dma_controller;
+ 		int value;
++
+ 		if (ep->is_in) {
++			/*
++			 * The programming guide says that we must not clear
++			 * the DMAMODE bit before DMAENAB, so we only
++			 * clear it in the second write...
++			 */
+ 			musb_writew(epio, MUSB_TXCSR,
+-					0 | MUSB_TXCSR_FLUSHFIFO);
++				    MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
+ 			musb_writew(epio, MUSB_TXCSR,
+ 					0 | MUSB_TXCSR_FLUSHFIFO);
+ 		} else {
+@@ -230,7 +236,7 @@ static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
+ 		  |	IN token(s) are recd from Host.
+ 		  |		-> DMA interrupt on completion
+ 		  |		   calls TxAvail.
+-		  |		      -> stop DMA, ~DmaEenab,
++		  |		      -> stop DMA, ~DMAENAB,
+ 		  |		      -> set TxPktRdy for last short pkt or zlp
+ 		  |		      -> Complete Request
+ 		  |		      -> Continue next request (call txstate)
+@@ -315,9 +321,17 @@ static void txstate(struct musb *musb, struct musb_request *req)
+ 					request->dma, request_size);
+ 			if (use_dma) {
+ 				if (musb_ep->dma->desired_mode == 0) {
+-					/* ASSERT: DMAENAB is clear */
+-					csr &= ~(MUSB_TXCSR_AUTOSET |
+-							MUSB_TXCSR_DMAMODE);
++					/*
++					 * We must not clear the DMAMODE bit
++					 * before the DMAENAB bit -- and the
++					 * latter doesn't always get cleared
++					 * before we get here...
++					 */
++					csr &= ~(MUSB_TXCSR_AUTOSET
++						| MUSB_TXCSR_DMAENAB);
++					musb_writew(epio, MUSB_TXCSR, csr
++						| MUSB_TXCSR_P_WZC_BITS);
++					csr &= ~MUSB_TXCSR_DMAMODE;
+ 					csr |= (MUSB_TXCSR_DMAENAB |
+ 							MUSB_TXCSR_MODE);
+ 					/* against programming guide */
+@@ -334,10 +348,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
+ 
+ #elif defined(CONFIG_USB_TI_CPPI_DMA)
+ 		/* program endpoint CSR first, then setup DMA */
+-		csr &= ~(MUSB_TXCSR_AUTOSET
+-				| MUSB_TXCSR_DMAMODE
+-				| MUSB_TXCSR_P_UNDERRUN
+-				| MUSB_TXCSR_TXPKTRDY);
++		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
+ 		csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_DMAENAB;
+ 		musb_writew(epio, MUSB_TXCSR,
+ 			(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
+@@ -364,8 +375,8 @@ static void txstate(struct musb *musb, struct musb_request *req)
+ 		if (!use_dma) {
+ 			c->channel_release(musb_ep->dma);
+ 			musb_ep->dma = NULL;
+-			/* ASSERT: DMAENAB clear */
+-			csr &= ~(MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
++			csr &= ~MUSB_TXCSR_DMAENAB;
++			musb_writew(epio, MUSB_TXCSR, csr);
+ 			/* invariant: prequest->buf is non-null */
+ 		}
+ #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index a5d75aa..6591282 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -590,10 +590,17 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
+ 		csr = musb_readw(ep->regs, MUSB_TXCSR);
+ 		if (csr & MUSB_TXCSR_MODE) {
+ 			musb_h_tx_flush_fifo(ep);
++			csr = musb_readw(ep->regs, MUSB_TXCSR);
+ 			musb_writew(ep->regs, MUSB_TXCSR,
+-					MUSB_TXCSR_FRCDATATOG);
++				    csr | MUSB_TXCSR_FRCDATATOG);
+ 		}
+-		/* clear mode (and everything else) to enable Rx */
++
++		/*
++		 * Clear the MODE bit (and everything else) to enable Rx.
++		 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
++		 */
++		if (csr & MUSB_TXCSR_DMAMODE)
++			musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
+ 		musb_writew(ep->regs, MUSB_TXCSR, 0);
+ 
+ 	/* scrub all previous state, clearing toggle */
+@@ -690,12 +697,17 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 
+ 		/* general endpoint setup */
+ 		if (epnum) {
+-			/* ASSERT:  TXCSR_DMAENAB was already cleared */
+-
+ 			/* flush all old state, set default */
+ 			musb_h_tx_flush_fifo(hw_ep);
++
++			/*
++			 * We must not clear the DMAMODE bit before or in
++			 * the same cycle with the DMAENAB bit, so we clear
++			 * the latter first...
++			 */
+ 			csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
+-					| MUSB_TXCSR_DMAMODE
++					| MUSB_TXCSR_AUTOSET
++					| MUSB_TXCSR_DMAENAB
+ 					| MUSB_TXCSR_FRCDATATOG
+ 					| MUSB_TXCSR_H_RXSTALL
+ 					| MUSB_TXCSR_H_ERROR
+@@ -703,16 +715,15 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 					);
+ 			csr |= MUSB_TXCSR_MODE;
+ 
+-			if (usb_gettoggle(urb->dev,
+-					qh->epnum, 1))
++			if (usb_gettoggle(urb->dev, qh->epnum, 1))
+ 				csr |= MUSB_TXCSR_H_WR_DATATOGGLE
+ 					| MUSB_TXCSR_H_DATATOGGLE;
+ 			else
+ 				csr |= MUSB_TXCSR_CLRDATATOG;
+ 
+-			/* twice in case of double packet buffering */
+ 			musb_writew(epio, MUSB_TXCSR, csr);
+ 			/* REVISIT may need to clear FLUSHFIFO ... */
++			csr &= ~MUSB_TXCSR_DMAMODE;
+ 			musb_writew(epio, MUSB_TXCSR, csr);
+ 			csr = musb_readw(epio, MUSB_TXCSR);
+ 		} else {
+@@ -755,34 +766,19 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 
+ #ifdef CONFIG_USB_INVENTRA_DMA
+ 		if (dma_channel) {
+-
+-			/* clear previous state */
+-			csr = musb_readw(epio, MUSB_TXCSR);
+-			csr &= ~(MUSB_TXCSR_AUTOSET
+-				| MUSB_TXCSR_DMAMODE
+-				| MUSB_TXCSR_DMAENAB);
+-			csr |= MUSB_TXCSR_MODE;
+-			musb_writew(epio, MUSB_TXCSR,
+-				csr | MUSB_TXCSR_MODE);
+-
+ 			qh->segsize = min(len, dma_channel->max_len);
+-
+ 			if (qh->segsize <= packet_sz)
+ 				dma_channel->desired_mode = 0;
+ 			else
+ 				dma_channel->desired_mode = 1;
+ 
+-
+ 			if (dma_channel->desired_mode == 0) {
+-				csr &= ~(MUSB_TXCSR_AUTOSET
+-					| MUSB_TXCSR_DMAMODE);
++				/* Against the programming guide */
+ 				csr |= (MUSB_TXCSR_DMAENAB);
+-					/* against programming guide */
+ 			} else
+ 				csr |= (MUSB_TXCSR_AUTOSET
+ 					| MUSB_TXCSR_DMAENAB
+ 					| MUSB_TXCSR_DMAMODE);
+-
+ 			musb_writew(epio, MUSB_TXCSR, csr);
+ 
+ 			dma_ok = dma_controller->channel_program(
+@@ -799,6 +795,17 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 				else
+ 					hw_ep->rx_channel = NULL;
+ 				dma_channel = NULL;
++
++				/*
++				 * The programming guide says that we must
++				 * clear the DMAENAB bit before DMAMODE...
++				 */
++				csr = musb_readw(epio, MUSB_TXCSR);
++				csr &= ~(MUSB_TXCSR_DMAENAB
++						| MUSB_TXCSR_AUTOSET);
++				musb_writew(epio, MUSB_TXCSR, csr);
++				csr &= ~MUSB_TXCSR_DMAMODE;
++				musb_writew(epio, MUSB_TXCSR, csr);
+ 			}
+ 		}
+ #endif
+@@ -806,18 +813,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 		/* candidate for DMA */
+ 		if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
+ 
+-			/* program endpoint CSRs first, then setup DMA.
+-			 * assume CPPI setup succeeds.
+-			 * defer enabling dma.
+-			 */
+-			csr = musb_readw(epio, MUSB_TXCSR);
+-			csr &= ~(MUSB_TXCSR_AUTOSET
+-					| MUSB_TXCSR_DMAMODE
+-					| MUSB_TXCSR_DMAENAB);
+-			csr |= MUSB_TXCSR_MODE;
+-			musb_writew(epio, MUSB_TXCSR,
+-				csr | MUSB_TXCSR_MODE);
+-
++			/* Defer enabling DMA */
+ 			dma_channel->actual_len = 0L;
+ 			qh->segsize = len;
+ 
+@@ -846,20 +842,9 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 		}
+ 
+ 		if (load_count) {
+-			/* ASSERT:  TXCSR_DMAENAB was already cleared */
+-
+ 			/* PIO to load FIFO */
+ 			qh->segsize = load_count;
+ 			musb_write_fifo(hw_ep, load_count, buf);
+-			csr = musb_readw(epio, MUSB_TXCSR);
+-			csr &= ~(MUSB_TXCSR_DMAENAB
+-				| MUSB_TXCSR_DMAMODE
+-				| MUSB_TXCSR_AUTOSET);
+-			/* write CSR */
+-			csr |= MUSB_TXCSR_MODE;
+-
+-			if (epnum)
+-				musb_writew(epio, MUSB_TXCSR, csr);
+ 		}
+ 
+ 		/* re-enable interrupt */
+diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
+index 8662e9e..40709c3 100644
+--- a/drivers/usb/musb/musbhsdma.c
++++ b/drivers/usb/musb/musbhsdma.c
+@@ -195,30 +195,32 @@ static int dma_channel_abort(struct dma_channel *channel)
+ 	void __iomem *mbase = musb_channel->controller->base;
+ 
+ 	u8 bchannel = musb_channel->idx;
++	int offset;
+ 	u16 csr;
+ 
+ 	if (channel->status == MUSB_DMA_STATUS_BUSY) {
+ 		if (musb_channel->transmit) {
+-
+-			csr = musb_readw(mbase,
+-				MUSB_EP_OFFSET(musb_channel->epnum,
+-						MUSB_TXCSR));
+-			csr &= ~(MUSB_TXCSR_AUTOSET |
+-				 MUSB_TXCSR_DMAENAB |
+-				 MUSB_TXCSR_DMAMODE);
+-			musb_writew(mbase,
+-				MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
+-				csr);
++			offset = MUSB_EP_OFFSET(musb_channel->epnum,
++						MUSB_TXCSR);
++
++			/*
++			 * The programming guide says that we must clear
++			 * the DMAENAB bit before the DMAMODE bit...
++			 */
++			csr = musb_readw(mbase, offset);
++			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
++			musb_writew(mbase, offset, csr);
++			csr &= ~MUSB_TXCSR_DMAMODE;
++			musb_writew(mbase, offset, csr);
+ 		} else {
+-			csr = musb_readw(mbase,
+-				MUSB_EP_OFFSET(musb_channel->epnum,
+-						MUSB_RXCSR));
++			offset = MUSB_EP_OFFSET(musb_channel->epnum,
++						MUSB_RXCSR);
++
++			csr = musb_readw(mbase, offset);
+ 			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
+ 				 MUSB_RXCSR_DMAENAB |
+ 				 MUSB_RXCSR_DMAMODE);
+-			musb_writew(mbase,
+-				MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
+-				csr);
++			musb_writew(mbase, offset, csr);
+ 		}
+ 
+ 		musb_writew(mbase,
+@@ -296,14 +298,25 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
+ 					&& ((channel->desired_mode == 0)
+ 					    || (channel->actual_len &
+ 					    (musb_channel->max_packet_sz - 1)))
+-					 ) {
++				    ) {
++					u8  epnum  = musb_channel->epnum;
++					int offset = MUSB_EP_OFFSET(epnum,
++								    MUSB_TXCSR);
++					u16 txcsr;
++
++					/*
++					 * The programming guide says that we
++					 * must clear DMAENAB before DMAMODE.
++					 */
++					musb_ep_select(mbase, epnum);
++					txcsr = musb_readw(mbase, offset);
++					txcsr &= ~(MUSB_TXCSR_DMAENAB
++							| MUSB_TXCSR_AUTOSET);
++					musb_writew(mbase, offset, txcsr);
+ 					/* Send out the packet */
+-					musb_ep_select(mbase,
+-						musb_channel->epnum);
+-					musb_writew(mbase, MUSB_EP_OFFSET(
+-							musb_channel->epnum,
+-							MUSB_TXCSR),
+-						MUSB_TXCSR_TXPKTRDY);
++					txcsr &= ~MUSB_TXCSR_DMAMODE;
++					txcsr |=  MUSB_TXCSR_TXPKTRDY;
++					musb_writew(mbase, offset, txcsr);
+ 				} else {
+ 					musb_dma_completion(
+ 						musb,
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0011-musb-fix-isochronous-TXDMA-take-2.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0011-musb-fix-isochronous-TXDMA-take-2.patch
new file mode 100644
index 0000000000..7d546e10b0
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0011-musb-fix-isochronous-TXDMA-take-2.patch
@@ -0,0 +1,417 @@
+From 035cd4a26e9b1638b4b0419b98409026176563ca Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Thu, 26 Mar 2009 18:29:19 -0700
+Subject: [PATCH] musb: fix isochronous TXDMA (take 2)
+
+Multi-frame isochronous TX URBs transfers in DMA mode never
+complete with CPPI DMA because musb_host_tx() doesn't restart
+DMA on the second frame, only emitting a debug message.
+With Inventra DMA they complete, but in PIO mode.  To fix:
+
+ - Factor out programming of the DMA transfer from
+   musb_ep_program() into musb_tx_dma_program();
+
+ - Reorder the code at the end of musb_host_tx() to
+   facilitate the fallback to PIO iff DMA fails;
+
+ - Handle the buffer offset consistently for both
+   PIO and DMA modes;
+
+ - Add an argument to musb_ep_program() for the same
+   reason (it only worked correctly with non-zero
+   offset of the first frame in PIO mode);
+
+ - Set the completed isochronous frame descriptor's
+   'actual_length' and 'status' fields correctly in
+   DMA mode.
+
+Also, since CPPI reportedly doesn't like sending isochronous
+packets in the RNDIS mode, change the criterion for this
+mode to be used only for multi-packet transfers.  (There's
+no need for that mode in the single-packet case anyway.)
+
+[ dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org: split comment paragraph
+into bullet list, shrink patch delta, style tweaks ]
+
+Signed-off-by: Pavel Kiryukhin <pkiryukhin-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/cppi_dma.c  |    1 +
+ drivers/usb/musb/musb_host.c |  227 +++++++++++++++++++-----------------------
+ 2 files changed, 105 insertions(+), 123 deletions(-)
+
+diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
+index 569ef0f..ac7227c 100644
+--- a/drivers/usb/musb/cppi_dma.c
++++ b/drivers/usb/musb/cppi_dma.c
+@@ -579,6 +579,7 @@ cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
+ 	 * trigger the "send a ZLP?" confusion.
+ 	 */
+ 	rndis = (maxpacket & 0x3f) == 0
++		&& length > maxpacket
+ 		&& length < 0xffff
+ 		&& (length % maxpacket) != 0;
+ 
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index 6591282..f6e84a0 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -96,8 +96,8 @@
+ 
+ 
+ static void musb_ep_program(struct musb *musb, u8 epnum,
+-			struct urb *urb, unsigned int nOut,
+-			u8 *buf, u32 len);
++			struct urb *urb, int is_out,
++			u8 *buf, u32 offset, u32 len);
+ 
+ /*
+  * Clear TX fifo. Needed to avoid BABBLE errors.
+@@ -189,9 +189,10 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
+ {
+ 	u16			frame;
+ 	u32			len;
+-	void			*buf;
+ 	void __iomem		*mbase =  musb->mregs;
+ 	struct urb		*urb = next_urb(qh);
++	void			*buf = urb->transfer_buffer;
++	u32			offset = 0;
+ 	struct musb_hw_ep	*hw_ep = qh->hw_ep;
+ 	unsigned		pipe = urb->pipe;
+ 	u8			address = usb_pipedevice(pipe);
+@@ -214,7 +215,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
+ 	case USB_ENDPOINT_XFER_ISOC:
+ 		qh->iso_idx = 0;
+ 		qh->frame = 0;
+-		buf = urb->transfer_buffer + urb->iso_frame_desc[0].offset;
++		offset = urb->iso_frame_desc[0].offset;
+ 		len = urb->iso_frame_desc[0].length;
+ 		break;
+ 	default:		/* bulk, interrupt */
+@@ -232,14 +233,14 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
+ 			case USB_ENDPOINT_XFER_ISOC:	s = "-iso"; break;
+ 			default:			s = "-intr"; break;
+ 			}; s; }),
+-			epnum, buf, len);
++			epnum, buf + offset, len);
+ 
+ 	/* Configure endpoint */
+ 	if (is_in || hw_ep->is_shared_fifo)
+ 		hw_ep->in_qh = qh;
+ 	else
+ 		hw_ep->out_qh = qh;
+-	musb_ep_program(musb, epnum, urb, !is_in, buf, len);
++	musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
+ 
+ 	/* transmit may have more work: start it when it is time */
+ 	if (is_in)
+@@ -250,7 +251,6 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
+ 	case USB_ENDPOINT_XFER_ISOC:
+ 	case USB_ENDPOINT_XFER_INT:
+ 		DBG(3, "check whether there's still time for periodic Tx\n");
+-		qh->iso_idx = 0;
+ 		frame = musb_readw(mbase, MUSB_FRAME);
+ 		/* FIXME this doesn't implement that scheduling policy ...
+ 		 * or handle framecounter wrapping
+@@ -631,14 +631,68 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
+ 	ep->rx_reinit = 0;
+ }
+ 
++static bool musb_tx_dma_program(struct dma_controller *dma,
++		struct musb_hw_ep *hw_ep, struct musb_qh *qh,
++		struct urb *urb, u32 offset, u32 length)
++{
++	struct dma_channel	*channel = hw_ep->tx_channel;
++	void __iomem		*epio = hw_ep->regs;
++	u16			pkt_size = qh->maxpacket;
++	u16			csr;
++	u8			mode;
++
++#ifdef	CONFIG_USB_INVENTRA_DMA
++	if (length > channel->max_len)
++		length = channel->max_len;
++
++	csr = musb_readw(epio, MUSB_TXCSR);
++	if (length > pkt_size) {
++		mode = 1;
++		csr |= MUSB_TXCSR_AUTOSET
++			| MUSB_TXCSR_DMAMODE
++			| MUSB_TXCSR_DMAENAB;
++	} else {
++		mode = 0;
++		csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
++		csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
++	}
++	channel->desired_mode = mode;
++	musb_writew(epio, MUSB_TXCSR, csr);
++#else
++	if (!is_cppi_enabled() && !tusb_dma_omap())
++		return false;
++
++	channel->actual_len = 0;
++
++	/*
++	 * TX uses "RNDIS" mode automatically but needs help
++	 * to identify the zero-length-final-packet case.
++	 */
++	mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
++#endif
++
++	qh->segsize = length;
++
++	if (!dma->channel_program(channel, pkt_size, mode,
++			urb->transfer_dma + offset, length)) {
++		dma->channel_release(channel);
++		hw_ep->tx_channel = NULL;
++
++		csr = musb_readw(epio, MUSB_TXCSR);
++		csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
++		musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
++		return false;
++	}
++	return true;
++}
+ 
+ /*
+  * Program an HDRC endpoint as per the given URB
+  * Context: irqs blocked, controller lock held
+  */
+ static void musb_ep_program(struct musb *musb, u8 epnum,
+-			struct urb *urb, unsigned int is_out,
+-			u8 *buf, u32 len)
++			struct urb *urb, int is_out,
++			u8 *buf, u32 offset, u32 len)
+ {
+ 	struct dma_controller	*dma_controller;
+ 	struct dma_channel	*dma_channel;
+@@ -764,82 +818,9 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 		else
+ 			load_count = min((u32) packet_sz, len);
+ 
+-#ifdef CONFIG_USB_INVENTRA_DMA
+-		if (dma_channel) {
+-			qh->segsize = min(len, dma_channel->max_len);
+-			if (qh->segsize <= packet_sz)
+-				dma_channel->desired_mode = 0;
+-			else
+-				dma_channel->desired_mode = 1;
+-
+-			if (dma_channel->desired_mode == 0) {
+-				/* Against the programming guide */
+-				csr |= (MUSB_TXCSR_DMAENAB);
+-			} else
+-				csr |= (MUSB_TXCSR_AUTOSET
+-					| MUSB_TXCSR_DMAENAB
+-					| MUSB_TXCSR_DMAMODE);
+-			musb_writew(epio, MUSB_TXCSR, csr);
+-
+-			dma_ok = dma_controller->channel_program(
+-					dma_channel, packet_sz,
+-					dma_channel->desired_mode,
+-					urb->transfer_dma,
+-					qh->segsize);
+-			if (dma_ok) {
+-				load_count = 0;
+-			} else {
+-				dma_controller->channel_release(dma_channel);
+-				if (is_out)
+-					hw_ep->tx_channel = NULL;
+-				else
+-					hw_ep->rx_channel = NULL;
+-				dma_channel = NULL;
+-
+-				/*
+-				 * The programming guide says that we must
+-				 * clear the DMAENAB bit before DMAMODE...
+-				 */
+-				csr = musb_readw(epio, MUSB_TXCSR);
+-				csr &= ~(MUSB_TXCSR_DMAENAB
+-						| MUSB_TXCSR_AUTOSET);
+-				musb_writew(epio, MUSB_TXCSR, csr);
+-				csr &= ~MUSB_TXCSR_DMAMODE;
+-				musb_writew(epio, MUSB_TXCSR, csr);
+-			}
+-		}
+-#endif
+-
+-		/* candidate for DMA */
+-		if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
+-
+-			/* Defer enabling DMA */
+-			dma_channel->actual_len = 0L;
+-			qh->segsize = len;
+-
+-			/* TX uses "rndis" mode automatically, but needs help
+-			 * to identify the zero-length-final-packet case.
+-			 */
+-			dma_ok = dma_controller->channel_program(
+-					dma_channel, packet_sz,
+-					(urb->transfer_flags
+-							& URB_ZERO_PACKET)
+-						== URB_ZERO_PACKET,
+-					urb->transfer_dma,
+-					qh->segsize);
+-			if (dma_ok) {
+-				load_count = 0;
+-			} else {
+-				dma_controller->channel_release(dma_channel);
+-				hw_ep->tx_channel = NULL;
+-				dma_channel = NULL;
+-
+-				/* REVISIT there's an error path here that
+-				 * needs handling:  can't do dma, but
+-				 * there's no pio buffer address...
+-				 */
+-			}
+-		}
++		if (dma_channel && musb_tx_dma_program(dma_controller,
++					hw_ep, qh, urb, offset, len))
++			load_count = 0;
+ 
+ 		if (load_count) {
+ 			/* PIO to load FIFO */
+@@ -899,7 +880,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 						dma_channel, packet_sz,
+ 						!(urb->transfer_flags
+ 							& URB_SHORT_NOT_OK),
+-						urb->transfer_dma,
++						urb->transfer_dma + offset,
+ 						qh->segsize);
+ 				if (!dma_ok) {
+ 					dma_controller->channel_release(
+@@ -1142,8 +1123,8 @@ void musb_host_tx(struct musb *musb, u8 epnum)
+ 	int			pipe;
+ 	bool			done = false;
+ 	u16			tx_csr;
+-	size_t			wLength = 0;
+-	u8			*buf = NULL;
++	size_t			length = 0;
++	size_t			offset = 0;
+ 	struct urb		*urb;
+ 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
+ 	void __iomem		*epio = hw_ep->regs;
+@@ -1161,7 +1142,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
+ 	/* with CPPI, DMA sometimes triggers "extra" irqs */
+ 	if (!urb) {
+ 		DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
+-		goto finish;
++		return;
+ 	}
+ 
+ 	pipe = urb->pipe;
+@@ -1198,7 +1179,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
+ 		musb_writew(epio, MUSB_TXCSR,
+ 				MUSB_TXCSR_H_WZC_BITS
+ 				| MUSB_TXCSR_TXPKTRDY);
+-		goto finish;
++		return;
+ 	}
+ 
+ 	if (status) {
+@@ -1230,29 +1211,28 @@ void musb_host_tx(struct musb *musb, u8 epnum)
+ 	/* second cppi case */
+ 	if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
+ 		DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
+-		goto finish;
+-
++		return;
+ 	}
+ 
+-	/* REVISIT this looks wrong... */
+ 	if (!status || dma || usb_pipeisoc(pipe)) {
+ 		if (dma)
+-			wLength = dma->actual_len;
++			length = dma->actual_len;
+ 		else
+-			wLength = qh->segsize;
+-		qh->offset += wLength;
++			length = qh->segsize;
++		qh->offset += length;
+ 
+ 		if (usb_pipeisoc(pipe)) {
+ 			struct usb_iso_packet_descriptor	*d;
+ 
+ 			d = urb->iso_frame_desc + qh->iso_idx;
+-			d->actual_length = qh->segsize;
++			d->actual_length = length;
++			d->status = status;
+ 			if (++qh->iso_idx >= urb->number_of_packets) {
+ 				done = true;
+ 			} else {
+ 				d++;
+-				buf = urb->transfer_buffer + d->offset;
+-				wLength = d->length;
++				offset = d->offset;
++				length = d->length;
+ 			}
+ 		} else if (dma) {
+ 			done = true;
+@@ -1265,10 +1245,8 @@ void musb_host_tx(struct musb *musb, u8 epnum)
+ 						& URB_ZERO_PACKET))
+ 				done = true;
+ 			if (!done) {
+-				buf = urb->transfer_buffer
+-						+ qh->offset;
+-				wLength = urb->transfer_buffer_length
+-						- qh->offset;
++				offset = qh->offset;
++				length = urb->transfer_buffer_length - offset;
+ 			}
+ 		}
+ 	}
+@@ -1287,28 +1265,31 @@ void musb_host_tx(struct musb *musb, u8 epnum)
+ 		urb->status = status;
+ 		urb->actual_length = qh->offset;
+ 		musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
++		return;
++	} else	if (usb_pipeisoc(pipe) && dma) {
++		if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
++				offset, length))
++			return;
++	} else	if (tx_csr & MUSB_TXCSR_DMAENAB) {
++		DBG(1, "not complete, but DMA enabled?\n");
++		return;
++	}
+ 
+-	} else if (!(tx_csr & MUSB_TXCSR_DMAENAB)) {
+-		/* WARN_ON(!buf); */
+-
+-		/* REVISIT:  some docs say that when hw_ep->tx_double_buffered,
+-		 * (and presumably, fifo is not half-full) we should write TWO
+-		 * packets before updating TXCSR ... other docs disagree ...
+-		 */
+-		/* PIO:  start next packet in this URB */
+-		if (wLength > qh->maxpacket)
+-			wLength = qh->maxpacket;
+-		musb_write_fifo(hw_ep, wLength, buf);
+-		qh->segsize = wLength;
+-
+-		musb_ep_select(mbase, epnum);
+-		musb_writew(epio, MUSB_TXCSR,
+-				MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
+-	} else
+-		DBG(1, "not complete, but dma enabled?\n");
++	/*
++	 * PIO: start next packet in this URB.
++	 *
++	 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
++	 * (and presumably, FIFO is not half-full) we should write *two*
++	 * packets before updating TXCSR; other docs disagree...
++	 */
++	if (length > qh->maxpacket)
++		length = qh->maxpacket;
++	musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
++	qh->segsize = length;
+ 
+-finish:
+-	return;
++	musb_ep_select(mbase, epnum);
++	musb_writew(epio, MUSB_TXCSR,
++			MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
+ }
+ 
+ 
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0012-musb-fix-possible-panic-while-resuming.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0012-musb-fix-possible-panic-while-resuming.patch
new file mode 100644
index 0000000000..2bbde84c16
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0012-musb-fix-possible-panic-while-resuming.patch
@@ -0,0 +1,56 @@
+From b9a61b80ea89d9d6d78a23d96a28df94fd612298 Mon Sep 17 00:00:00 2001
+From: Kim Kyuwon <q1.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+Date: Thu, 26 Mar 2009 18:56:51 -0700
+Subject: [PATCH] musb: fix possible panic while resuming
+
+During driver resume processing, musb could cause a kernel panic.
+Fix by enabling the clock earlier, with the resume_early method.
+
+Signed-off-by: Kim Kyuwon <q1.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_core.c |    8 ++------
+ 1 files changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index 338cd16..3019725 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -2170,16 +2170,13 @@ static int musb_suspend(struct platform_device *pdev, pm_message_t message)
+ 	return 0;
+ }
+ 
+-static int musb_resume(struct platform_device *pdev)
++static int musb_resume_early(struct platform_device *pdev)
+ {
+-	unsigned long	flags;
+ 	struct musb	*musb = dev_to_musb(&pdev->dev);
+ 
+ 	if (!musb->clock)
+ 		return 0;
+ 
+-	spin_lock_irqsave(&musb->lock, flags);
+-
+ 	if (musb->set_clock)
+ 		musb->set_clock(musb->clock, 1);
+ 	else
+@@ -2189,7 +2186,6 @@ static int musb_resume(struct platform_device *pdev)
+ 	 * unless for some reason the whole soc powered down and we're
+ 	 * not treating that as a whole-system restart (e.g. swsusp)
+ 	 */
+-	spin_unlock_irqrestore(&musb->lock, flags);
+ 	return 0;
+ }
+ 
+@@ -2207,7 +2203,7 @@ static struct platform_driver musb_driver = {
+ 	.remove		= __devexit_p(musb_remove),
+ 	.shutdown	= musb_shutdown,
+ 	.suspend	= musb_suspend,
+-	.resume		= musb_resume,
++	.resume_early	= musb_resume_early,
+ };
+ 
+ /*-------------------------------------------------------------------------*/
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0013-musb_host-refactor-musb_save_toggle-take-2.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0013-musb_host-refactor-musb_save_toggle-take-2.patch
new file mode 100644
index 0000000000..0202871d41
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0013-musb_host-refactor-musb_save_toggle-take-2.patch
@@ -0,0 +1,91 @@
+From 2658f7c9029967501cd4d749364f2e02d02eebd5 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Fri, 27 Mar 2009 12:54:21 -0700
+Subject: [PATCH] musb_host: refactor musb_save_toggle() (take 2)
+
+Refactor musb_save_toggle() as follows:
+
+ - replace 'struct musb_hw_ep *ep' parameter by 'struct
+   musb_qh *qh' to avoid re-calculating this value
+
+ - move usb_settogle() call out of the *if* operator.
+
+This is a net minor shrink of source and object code.
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_host.c |   35 ++++++++++++-----------------------
+ 1 files changed, 12 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index f6e84a0..dc32ce4 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -318,35 +318,24 @@ __acquires(musb->lock)
+ 	spin_lock(&musb->lock);
+ }
+ 
+-/* for bulk/interrupt endpoints only */
+-static inline void
+-musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb)
++/* For bulk/interrupt endpoints only */
++static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
++				    struct urb *urb)
+ {
+-	struct usb_device	*udev = urb->dev;
++	void __iomem		*epio = qh->hw_ep->regs;
+ 	u16			csr;
+-	void __iomem		*epio = ep->regs;
+-	struct musb_qh		*qh;
+ 
+-	/* FIXME:  the current Mentor DMA code seems to have
++	/*
++	 * FIXME: the current Mentor DMA code seems to have
+ 	 * problems getting toggle correct.
+ 	 */
+ 
+-	if (is_in || ep->is_shared_fifo)
+-		qh = ep->in_qh;
++	if (is_in)
++		csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
+ 	else
+-		qh = ep->out_qh;
++		csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
+ 
+-	if (!is_in) {
+-		csr = musb_readw(epio, MUSB_TXCSR);
+-		usb_settoggle(udev, qh->epnum, 1,
+-			(csr & MUSB_TXCSR_H_DATATOGGLE)
+-				? 1 : 0);
+-	} else {
+-		csr = musb_readw(epio, MUSB_RXCSR);
+-		usb_settoggle(udev, qh->epnum, 0,
+-			(csr & MUSB_RXCSR_H_DATATOGGLE)
+-				? 1 : 0);
+-	}
++	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
+ }
+ 
+ /* caller owns controller lock, irqs are blocked */
+@@ -362,7 +351,7 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
+ 	switch (qh->type) {
+ 	case USB_ENDPOINT_XFER_BULK:
+ 	case USB_ENDPOINT_XFER_INT:
+-		musb_save_toggle(ep, is_in, urb);
++		musb_save_toggle(qh, is_in, urb);
+ 		break;
+ 	case USB_ENDPOINT_XFER_ISOC:
+ 		if (status == 0 && urb->error_count)
+@@ -1362,7 +1351,7 @@ static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
+ 			urb->actual_length += dma->actual_len;
+ 			dma->actual_len = 0L;
+ 		}
+-		musb_save_toggle(ep, 1, urb);
++		musb_save_toggle(cur_qh, 1, urb);
+ 
+ 		/* move cur_qh to end of queue */
+ 		list_move_tail(&cur_qh->ring, &musb->in_bulk);
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0014-musb_gadget-suppress-parasitic-TX-interrupts-with.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0014-musb_gadget-suppress-parasitic-TX-interrupts-with.patch
new file mode 100644
index 0000000000..08e08a8538
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0014-musb_gadget-suppress-parasitic-TX-interrupts-with.patch
@@ -0,0 +1,32 @@
+From 7766f2ea909b73f56d21746485069e02839b75f1 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Fri, 27 Mar 2009 12:53:32 -0700
+Subject: [PATCH] musb_gadget: suppress "parasitic" TX interrupts with CPPI
+
+Suppress "parasitic" endpoint interrupts in the DMA mode
+when using CPPI DMA driver; they're caused by the MUSB gadget
+driver using the DMA request mode 0 instead of the mode 1.
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_gadget.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
+index f79440c..bc197b2 100644
+--- a/drivers/usb/musb/musb_gadget.c
++++ b/drivers/usb/musb/musb_gadget.c
+@@ -349,7 +349,8 @@ static void txstate(struct musb *musb, struct musb_request *req)
+ #elif defined(CONFIG_USB_TI_CPPI_DMA)
+ 		/* program endpoint CSR first, then setup DMA */
+ 		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
+-		csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_DMAENAB;
++		csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
++		       MUSB_TXCSR_MODE;
+ 		musb_writew(epio, MUSB_TXCSR,
+ 			(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
+ 				| csr);
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0015-musb_gadget-fix-unhandled-endpoint-0-IRQs.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0015-musb_gadget-fix-unhandled-endpoint-0-IRQs.patch
new file mode 100644
index 0000000000..7115b152d9
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0015-musb_gadget-fix-unhandled-endpoint-0-IRQs.patch
@@ -0,0 +1,202 @@
+From 5424305125492a2417bde7c6d23ee4b84e25f6be Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Fri, 27 Mar 2009 12:52:43 -0700
+Subject: [PATCH] musb_gadget: fix unhandled endpoint 0 IRQs
+
+The gadget EP0 code routinely ignores an interrupt at end of
+the data phase because of musb_g_ep0_giveback() resetting the
+state machine to "idle, waiting for SETUP" phase prematurely.
+
+The driver also prematurely leaves the status phase on
+receiving the SetupEnd interrupt.
+
+As there were still unhandled endpoint 0 interrupts happening
+from time to time after fixing these issues, there turned to
+be yet another culprit: two distinct gadget states collapsed
+into one.
+
+The (missing) state that comes after STATUS IN/OUT states was
+typically indiscernible from them since the corresponding
+interrupts tend to happen within too little period of time
+(due to only a zero-length status packet in between) and so
+they got coalesced; yet this state is not the same as the next
+one which is associated with the reception of a SETUP packet.
+
+Adding this extra state seems to have fixed the rest of the
+unhandled interrupts that generic_interrupt() and
+davinci_interrupt() hid by faking their result and only
+emitting a debug message -- so, stop doing that.
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/davinci.c         |    7 +----
+ drivers/usb/musb/musb_core.c       |    8 +-----
+ drivers/usb/musb/musb_core.h       |    3 +-
+ drivers/usb/musb/musb_gadget_ep0.c |   45 +++++++++++++++++++++++++++++++----
+ 4 files changed, 43 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
+index 2dc7606..399c435 100644
+--- a/drivers/usb/musb/davinci.c
++++ b/drivers/usb/musb/davinci.c
+@@ -357,12 +357,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
+ 
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+ 
+-	/* REVISIT we sometimes get unhandled IRQs
+-	 * (e.g. ep0).  not clear why...
+-	 */
+-	if (retval != IRQ_HANDLED)
+-		DBG(5, "unhandled? %08x\n", tmp);
+-	return IRQ_HANDLED;
++	return retval;
+ }
+ 
+ int musb_platform_set_mode(struct musb *musb, u8 mode)
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index 3019725..a1de43b 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -1481,13 +1481,7 @@ static irqreturn_t generic_interrupt(int irq, void *__hci)
+ 
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+ 
+-	/* REVISIT we sometimes get spurious IRQs on g_ep0
+-	 * not clear why...
+-	 */
+-	if (retval != IRQ_HANDLED)
+-		DBG(5, "spurious?\n");
+-
+-	return IRQ_HANDLED;
++	return retval;
+ }
+ 
+ #else
+diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
+index adf1806..f56a56c 100644
+--- a/drivers/usb/musb/musb_core.h
++++ b/drivers/usb/musb/musb_core.h
+@@ -171,7 +171,8 @@ enum musb_h_ep0_state {
+ 
+ /* peripheral side ep0 states */
+ enum musb_g_ep0_state {
+-	MUSB_EP0_STAGE_SETUP,		/* idle, waiting for setup */
++	MUSB_EP0_STAGE_IDLE,		/* idle, waiting for SETUP */
++	MUSB_EP0_STAGE_SETUP,		/* received SETUP */
+ 	MUSB_EP0_STAGE_TX,		/* IN data */
+ 	MUSB_EP0_STAGE_RX,		/* OUT data */
+ 	MUSB_EP0_STAGE_STATUSIN,	/* (after OUT data) */
+diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
+index 3f5e30d..ec0e899 100644
+--- a/drivers/usb/musb/musb_gadget_ep0.c
++++ b/drivers/usb/musb/musb_gadget_ep0.c
+@@ -4,6 +4,7 @@
+  * Copyright 2005 Mentor Graphics Corporation
+  * Copyright (C) 2005-2006 by Texas Instruments
+  * Copyright (C) 2006-2007 Nokia Corporation
++ * Copyright (C) 2008-2009 MontaVista Software, Inc. <source-Igf4POYTYCDQT0dZR+AlfA@public.gmane.org>
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License
+@@ -58,7 +59,8 @@
+ static char *decode_ep0stage(u8 stage)
+ {
+ 	switch (stage) {
+-	case MUSB_EP0_STAGE_SETUP:	return "idle";
++	case MUSB_EP0_STAGE_IDLE:	return "idle";
++	case MUSB_EP0_STAGE_SETUP:	return "setup";
+ 	case MUSB_EP0_STAGE_TX:		return "in";
+ 	case MUSB_EP0_STAGE_RX:		return "out";
+ 	case MUSB_EP0_STAGE_ACKWAIT:	return "wait";
+@@ -628,7 +630,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
+ 		musb_writew(regs, MUSB_CSR0,
+ 				csr & ~MUSB_CSR0_P_SENTSTALL);
+ 		retval = IRQ_HANDLED;
+-		musb->ep0_state = MUSB_EP0_STAGE_SETUP;
++		musb->ep0_state = MUSB_EP0_STAGE_IDLE;
+ 		csr = musb_readw(regs, MUSB_CSR0);
+ 	}
+ 
+@@ -636,7 +638,18 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
+ 	if (csr & MUSB_CSR0_P_SETUPEND) {
+ 		musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
+ 		retval = IRQ_HANDLED;
+-		musb->ep0_state = MUSB_EP0_STAGE_SETUP;
++		/* Transition into the early status phase */
++		switch (musb->ep0_state) {
++		case MUSB_EP0_STAGE_TX:
++			musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
++			break;
++		case MUSB_EP0_STAGE_RX:
++			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
++			break;
++		default:
++			ERR("SetupEnd came in a wrong ep0stage %s",
++			    decode_ep0stage(musb->ep0_state));
++		}
+ 		csr = musb_readw(regs, MUSB_CSR0);
+ 		/* NOTE:  request may need completion */
+ 	}
+@@ -697,11 +710,31 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
+ 			if (req)
+ 				musb_g_ep0_giveback(musb, req);
+ 		}
++
++		/*
++		 * In case when several interrupts can get coalesced,
++		 * check to see if we've already received a SETUP packet...
++		 */
++		if (csr & MUSB_CSR0_RXPKTRDY)
++			goto setup;
++
++		retval = IRQ_HANDLED;
++		musb->ep0_state = MUSB_EP0_STAGE_IDLE;
++		break;
++
++	case MUSB_EP0_STAGE_IDLE:
++		/*
++		 * This state is typically (but not always) indiscernible
++		 * from the status states since the corresponding interrupts
++		 * tend to happen within too little period of time (with only
++		 * a zero-length packet in between) and so get coalesced...
++		 */
+ 		retval = IRQ_HANDLED;
+ 		musb->ep0_state = MUSB_EP0_STAGE_SETUP;
+ 		/* FALLTHROUGH */
+ 
+ 	case MUSB_EP0_STAGE_SETUP:
++setup:
+ 		if (csr & MUSB_CSR0_RXPKTRDY) {
+ 			struct usb_ctrlrequest	setup;
+ 			int			handled = 0;
+@@ -783,7 +816,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
+ stall:
+ 				DBG(3, "stall (%d)\n", handled);
+ 				musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
+-				musb->ep0_state = MUSB_EP0_STAGE_SETUP;
++				musb->ep0_state = MUSB_EP0_STAGE_IDLE;
+ finish:
+ 				musb_writew(regs, MUSB_CSR0,
+ 						musb->ackpend);
+@@ -803,7 +836,7 @@ finish:
+ 		/* "can't happen" */
+ 		WARN_ON(1);
+ 		musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
+-		musb->ep0_state = MUSB_EP0_STAGE_SETUP;
++		musb->ep0_state = MUSB_EP0_STAGE_IDLE;
+ 		break;
+ 	}
+ 
+@@ -959,7 +992,7 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
+ 
+ 		csr |= MUSB_CSR0_P_SENDSTALL;
+ 		musb_writew(regs, MUSB_CSR0, csr);
+-		musb->ep0_state = MUSB_EP0_STAGE_SETUP;
++		musb->ep0_state = MUSB_EP0_STAGE_IDLE;
+ 		musb->ackpend = 0;
+ 		break;
+ 	default:
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0016-musb_host-factor-out-musb_ep_-get-set-_qh.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0016-musb_host-factor-out-musb_ep_-get-set-_qh.patch
new file mode 100644
index 0000000000..a2f54ff47b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0016-musb_host-factor-out-musb_ep_-get-set-_qh.patch
@@ -0,0 +1,146 @@
+From f9ca8154cf395ec00129f12016697ef610a826ff Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Fri, 27 Mar 2009 12:55:16 -0700
+Subject: [PATCH] musb_host: factor out musb_ep_{get|set}_qh()
+
+Factor out the often used code to get/set the active 'qh'
+pointer for the hardware endpoint.  Change the way the case
+of a shared FIFO is handled by setting *both* 'in_qh' and
+'out_qh' fields of 'struct musb_hw_ep'.  That seems more
+consistent and makes getting to the current 'qh' easy when
+the code knows the direction beforehand.
+
+While at it, turn some assignments into intializers and
+fix declaration style in the vicinity.
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_host.c |   56 ++++++++++++++++-------------------------
+ 1 files changed, 22 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index dc32ce4..bc89079 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -178,6 +178,19 @@ static inline void cppi_host_txdma_start(struct musb_hw_ep *ep)
+ 	musb_writew(ep->regs, MUSB_TXCSR, txcsr);
+ }
+ 
++static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
++{
++	if (is_in != 0 || ep->is_shared_fifo)
++		ep->in_qh  = qh;
++	if (is_in == 0 || ep->is_shared_fifo)
++		ep->out_qh = qh;
++}
++
++static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
++{
++	return is_in ? ep->in_qh : ep->out_qh;
++}
++
+ /*
+  * Start the URB at the front of an endpoint's queue
+  * end must be claimed from the caller.
+@@ -207,7 +220,6 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
+ 	case USB_ENDPOINT_XFER_CONTROL:
+ 		/* control transfers always start with SETUP */
+ 		is_in = 0;
+-		hw_ep->out_qh = qh;
+ 		musb->ep0_stage = MUSB_EP0_START;
+ 		buf = urb->setup_packet;
+ 		len = 8;
+@@ -236,10 +248,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
+ 			epnum, buf + offset, len);
+ 
+ 	/* Configure endpoint */
+-	if (is_in || hw_ep->is_shared_fifo)
+-		hw_ep->in_qh = qh;
+-	else
+-		hw_ep->out_qh = qh;
++	musb_ep_set_qh(hw_ep, is_in, qh);
+ 	musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
+ 
+ 	/* transmit may have more work: start it when it is time */
+@@ -374,11 +383,8 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
+ 		else
+ 			ep->tx_reinit = 1;
+ 
+-		/* clobber old pointers to this qh */
+-		if (is_in || ep->is_shared_fifo)
+-			ep->in_qh = NULL;
+-		else
+-			ep->out_qh = NULL;
++		/* Clobber old pointers to this qh */
++		musb_ep_set_qh(ep, is_in, NULL);
+ 		qh->hep->hcpriv = NULL;
+ 
+ 		switch (qh->type) {
+@@ -421,12 +427,7 @@ static void
+ musb_advance_schedule(struct musb *musb, struct urb *urb,
+ 		struct musb_hw_ep *hw_ep, int is_in)
+ {
+-	struct musb_qh	*qh;
+-
+-	if (is_in || hw_ep->is_shared_fifo)
+-		qh = hw_ep->in_qh;
+-	else
+-		qh = hw_ep->out_qh;
++	struct musb_qh		*qh = musb_ep_get_qh(hw_ep, is_in);
+ 
+ 	if (urb->status == -EINPROGRESS)
+ 		qh = musb_giveback(qh, urb, 0);
+@@ -689,15 +690,8 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
+ 	void __iomem		*mbase = musb->mregs;
+ 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
+ 	void __iomem		*epio = hw_ep->regs;
+-	struct musb_qh		*qh;
+-	u16			packet_sz;
+-
+-	if (!is_out || hw_ep->is_shared_fifo)
+-		qh = hw_ep->in_qh;
+-	else
+-		qh = hw_ep->out_qh;
+-
+-	packet_sz = qh->maxpacket;
++	struct musb_qh		*qh = musb_ep_get_qh(hw_ep, !is_out);
++	u16			packet_sz = qh->maxpacket;
+ 
+ 	DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
+ 				"h_addr%02x h_port%02x bytes %d\n",
+@@ -1114,17 +1108,14 @@ void musb_host_tx(struct musb *musb, u8 epnum)
+ 	u16			tx_csr;
+ 	size_t			length = 0;
+ 	size_t			offset = 0;
+-	struct urb		*urb;
+ 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
+ 	void __iomem		*epio = hw_ep->regs;
+-	struct musb_qh		*qh = hw_ep->is_shared_fifo ? hw_ep->in_qh
+-							    : hw_ep->out_qh;
++	struct musb_qh		*qh = hw_ep->out_qh;
++	struct urb		*urb = next_urb(qh);
+ 	u32			status = 0;
+ 	void __iomem		*mbase = musb->mregs;
+ 	struct dma_channel	*dma;
+ 
+-	urb = next_urb(qh);
+-
+ 	musb_ep_select(mbase, epnum);
+ 	tx_csr = musb_readw(epio, MUSB_TXCSR);
+ 
+@@ -1741,10 +1732,7 @@ static int musb_schedule(
+ 			epnum++, hw_ep++) {
+ 		int	diff;
+ 
+-		if (is_in || hw_ep->is_shared_fifo) {
+-			if (hw_ep->in_qh  != NULL)
+-				continue;
+-		} else	if (hw_ep->out_qh != NULL)
++		if (musb_ep_get_qh(hw_ep, is_in) != NULL)
+ 			continue;
+ 
+ 		if (hw_ep == musb->bulk_ep)
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0017-musb_host-refactor-URB-giveback.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0017-musb_host-refactor-URB-giveback.patch
new file mode 100644
index 0000000000..4a520dff87
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0017-musb_host-refactor-URB-giveback.patch
@@ -0,0 +1,132 @@
+From 013056a09afd324e729d64b9a0e66a004604e1d6 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Fri, 27 Mar 2009 12:58:31 -0700
+Subject: [PATCH] musb_host: refactor URB giveback
+
+As musb_advance_schedule() is now the only remaning
+caller of musb_giveback() (and the only valid context
+of such call), just fold the latter into the former
+and then rename __musb_giveback() into musb_giveback().
+
+This is a net minor shrink.
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_host.c |   54 +++++++++++++++--------------------------
+ 1 files changed, 20 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index bc89079..e833959 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -292,9 +292,8 @@ start:
+ 	}
+ }
+ 
+-/* caller owns controller lock, irqs are blocked */
+-static void
+-__musb_giveback(struct musb *musb, struct urb *urb, int status)
++/* Context: caller owns controller lock, IRQs are blocked */
++static void musb_giveback(struct musb *musb, struct urb *urb, int status)
+ __releases(musb->lock)
+ __acquires(musb->lock)
+ {
+@@ -347,14 +346,22 @@ static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
+ 	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
+ }
+ 
+-/* caller owns controller lock, irqs are blocked */
+-static struct musb_qh *
+-musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
++/*
++ * Advance this hardware endpoint's queue, completing the specified URB and
++ * advancing to either the next URB queued to that qh, or else invalidating
++ * that qh and advancing to the next qh scheduled after the current one.
++ *
++ * Context: caller owns controller lock, IRQs are blocked
++ */
++static void musb_advance_schedule(struct musb *musb, struct urb *urb,
++				  struct musb_hw_ep *hw_ep, int is_in)
+ {
++	struct musb_qh		*qh = musb_ep_get_qh(hw_ep, is_in);
+ 	struct musb_hw_ep	*ep = qh->hw_ep;
+-	struct musb		*musb = ep->musb;
+-	int			is_in = usb_pipein(urb->pipe);
+ 	int			ready = qh->is_ready;
++	int			status;
++
++	status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
+ 
+ 	/* save toggle eagerly, for paranoia */
+ 	switch (qh->type) {
+@@ -363,13 +370,13 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
+ 		musb_save_toggle(qh, is_in, urb);
+ 		break;
+ 	case USB_ENDPOINT_XFER_ISOC:
+-		if (status == 0 && urb->error_count)
++		if (urb->error_count)
+ 			status = -EXDEV;
+ 		break;
+ 	}
+ 
+ 	qh->is_ready = 0;
+-	__musb_giveback(musb, urb, status);
++	musb_giveback(musb, urb, status);
+ 	qh->is_ready = ready;
+ 
+ 	/* reclaim resources (and bandwidth) ASAP; deschedule it, and
+@@ -413,31 +420,10 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
+ 			break;
+ 		}
+ 	}
+-	return qh;
+-}
+-
+-/*
+- * Advance this hardware endpoint's queue, completing the specified urb and
+- * advancing to either the next urb queued to that qh, or else invalidating
+- * that qh and advancing to the next qh scheduled after the current one.
+- *
+- * Context: caller owns controller lock, irqs are blocked
+- */
+-static void
+-musb_advance_schedule(struct musb *musb, struct urb *urb,
+-		struct musb_hw_ep *hw_ep, int is_in)
+-{
+-	struct musb_qh		*qh = musb_ep_get_qh(hw_ep, is_in);
+-
+-	if (urb->status == -EINPROGRESS)
+-		qh = musb_giveback(qh, urb, 0);
+-	else
+-		qh = musb_giveback(qh, urb, urb->status);
+ 
+ 	if (qh != NULL && qh->is_ready) {
+ 		DBG(4, "... next ep%d %cX urb %p\n",
+-				hw_ep->epnum, is_in ? 'R' : 'T',
+-				next_urb(qh));
++		    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
+ 		musb_start_urb(musb, is_in, qh);
+ 	}
+ }
+@@ -2080,7 +2066,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+ 
+ 		ret = 0;
+ 		qh->is_ready = 0;
+-		__musb_giveback(musb, urb, 0);
++		musb_giveback(musb, urb, 0);
+ 		qh->is_ready = ready;
+ 
+ 		/* If nothing else (usually musb_giveback) is using it
+@@ -2164,7 +2150,7 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
+ 		 * will activate any of these as it advances.
+ 		 */
+ 		while (!list_empty(&hep->urb_list))
+-			__musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
++			musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
+ 
+ 		hep->hcpriv = NULL;
+ 		list_del(&qh->ring);
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0018-musb-split-out-CPPI-interrupt-handler.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0018-musb-split-out-CPPI-interrupt-handler.patch
new file mode 100644
index 0000000000..bf3d6e7021
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0018-musb-split-out-CPPI-interrupt-handler.patch
@@ -0,0 +1,167 @@
+From b91b067c531c9322f3719951b07303e790b13475 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Fri, 27 Mar 2009 12:59:46 -0700
+Subject: [PATCH] musb: split out CPPI interrupt handler
+
+As DaVinci DM646x has a dedicated CPPI DMA interrupt, replace
+cppi_completion() (which has always been kind of layering
+violation) by a complete CPPI interrupt handler.
+
+[ dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org: only cppi_dma.c needs platform
+device header, not cppi_dma.h ]
+
+Signed-off-by: Dmitry Krivoschekov <dkrivoschekov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/cppi_dma.c |   34 +++++++++++++++++++++++++++++++---
+ drivers/usb/musb/cppi_dma.h |    6 ++++--
+ drivers/usb/musb/davinci.c  |   14 ++++----------
+ 3 files changed, 39 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
+index ac7227c..6ff3c67 100644
+--- a/drivers/usb/musb/cppi_dma.c
++++ b/drivers/usb/musb/cppi_dma.c
+@@ -6,6 +6,7 @@
+  * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci.
+  */
+ 
++#include <linux/platform_device.h>
+ #include <linux/usb.h>
+ 
+ #include "musb_core.h"
+@@ -1145,17 +1146,27 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
+ 	return completed;
+ }
+ 
+-void cppi_completion(struct musb *musb, u32 rx, u32 tx)
++irqreturn_t cppi_interrupt(int irq, void *dev_id)
+ {
+-	void __iomem		*tibase;
+-	int			i, index;
++	struct musb		*musb = dev_id;
+ 	struct cppi		*cppi;
++	void __iomem		*tibase;
+ 	struct musb_hw_ep	*hw_ep = NULL;
++	u32			rx, tx;
++	int			i, index;
+ 
+ 	cppi = container_of(musb->dma_controller, struct cppi, controller);
+ 
+ 	tibase = musb->ctrl_base;
+ 
++	tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
++	rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
++
++	if (!tx && !rx)
++		return IRQ_NONE;
++
++	DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
++
+ 	/* process TX channels */
+ 	for (index = 0; tx; tx = tx >> 1, index++) {
+ 		struct cppi_channel		*tx_ch;
+@@ -1293,6 +1304,8 @@ void cppi_completion(struct musb *musb, u32 rx, u32 tx)
+ 
+ 	/* write to CPPI EOI register to re-enable interrupts */
+ 	musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
++
++	return IRQ_HANDLED;
+ }
+ 
+ /* Instantiate a software object representing a DMA controller. */
+@@ -1300,6 +1313,9 @@ struct dma_controller *__init
+ dma_controller_create(struct musb *musb, void __iomem *mregs)
+ {
+ 	struct cppi		*controller;
++	struct device		*dev = musb->controller;
++	struct platform_device	*pdev = to_platform_device(dev);
++	int			irq = platform_get_irq(pdev, 1);
+ 
+ 	controller = kzalloc(sizeof *controller, GFP_KERNEL);
+ 	if (!controller)
+@@ -1330,6 +1346,15 @@ dma_controller_create(struct musb *musb, void __iomem *mregs)
+ 		return NULL;
+ 	}
+ 
++	if (irq > 0) {
++		if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
++			dev_err(dev, "request_irq %d failed!\n", irq);
++			dma_controller_destroy(&controller->controller);
++			return NULL;
++		}
++		controller->irq = irq;
++	}
++
+ 	return &controller->controller;
+ }
+ 
+@@ -1342,6 +1367,9 @@ void dma_controller_destroy(struct dma_controller *c)
+ 
+ 	cppi = container_of(c, struct cppi, controller);
+ 
++	if (cppi->irq)
++		free_irq(cppi->irq, cppi->musb);
++
+ 	/* assert:  caller stopped the controller first */
+ 	dma_pool_destroy(cppi->pool);
+ 
+diff --git a/drivers/usb/musb/cppi_dma.h b/drivers/usb/musb/cppi_dma.h
+index 729b407..8a39de3 100644
+--- a/drivers/usb/musb/cppi_dma.h
++++ b/drivers/usb/musb/cppi_dma.h
+@@ -119,6 +119,8 @@ struct cppi {
+ 	void __iomem			*mregs;		/* Mentor regs */
+ 	void __iomem			*tibase;	/* TI/CPPI regs */
+ 
++	int				irq;
++
+ 	struct cppi_channel		tx[4];
+ 	struct cppi_channel		rx[4];
+ 
+@@ -127,7 +129,7 @@ struct cppi {
+ 	struct list_head		tx_complete;
+ };
+ 
+-/* irq handling hook */
+-extern void cppi_completion(struct musb *, u32 rx, u32 tx);
++/* CPPI IRQ handler */
++extern irqreturn_t cppi_interrupt(int, void *);
+ 
+ #endif				/* end of ifndef _CPPI_DMA_H_ */
+diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
+index 399c435..9fd74bf 100644
+--- a/drivers/usb/musb/davinci.c
++++ b/drivers/usb/musb/davinci.c
+@@ -250,6 +250,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
+ 	irqreturn_t	retval = IRQ_NONE;
+ 	struct musb	*musb = __hci;
+ 	void __iomem	*tibase = musb->ctrl_base;
++	struct cppi	*cppi;
+ 	u32		tmp;
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+@@ -266,16 +267,9 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
+ 	/* CPPI interrupts share the same IRQ line, but have their own
+ 	 * mask, state, "vector", and EOI registers.
+ 	 */
+-	if (is_cppi_enabled()) {
+-		u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
+-		u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
+-
+-		if (cppi_tx || cppi_rx) {
+-			DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
+-			cppi_completion(musb, cppi_rx, cppi_tx);
+-			retval = IRQ_HANDLED;
+-		}
+-	}
++	cppi = container_of(musb->dma_controller, struct cppi, controller);
++	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
++		retval = cppi_interrupt(irq, __hci);
+ 
+ 	/* ack and handle non-CPPI interrupts */
+ 	tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0019-musb_host-simplify-check-for-active-URB.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0019-musb_host-simplify-check-for-active-URB.patch
new file mode 100644
index 0000000000..c0e57155c8
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0019-musb_host-simplify-check-for-active-URB.patch
@@ -0,0 +1,158 @@
+From 69242ddd26151d45f46011cf7abc581b14699fb2 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Fri, 27 Mar 2009 12:56:26 -0700
+Subject: [PATCH] musb_host: simplify check for active URB
+
+The existance of the scheduling list shouldn't matter in
+determining whether there's currectly an URB executing on a
+hardware endpoint. What should actually matter is the 'in_qh'
+or 'out_qh' fields of the 'struct musb_hw_ep' -- those are
+set in musb_start_urb() and cleared in musb_giveback() when
+the endpoint's URB list drains. Hence we should be able to
+replace the big *switch* statements in musb_urb_dequeue()
+and musb_h_disable() with mere musb_ep_get_qh() calls...
+
+While at it, do some more changes:
+
+ - add 'is_in' variable to musb_urb_dequeue();
+
+ - remove the unnecessary 'epnum' variable from musb_h_disable();
+
+ - fix the comment style in the vicinity.
+
+This is a minor shrink of source and object code.
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_host.c |   72 ++++++++---------------------------------
+ 1 files changed, 14 insertions(+), 58 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index e833959..e121e0e 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -2008,14 +2008,14 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+ {
+ 	struct musb		*musb = hcd_to_musb(hcd);
+ 	struct musb_qh		*qh;
+-	struct list_head	*sched;
+ 	unsigned long		flags;
++	int			is_in  = usb_pipein(urb->pipe);
+ 	int			ret;
+ 
+ 	DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
+ 			usb_pipedevice(urb->pipe),
+ 			usb_pipeendpoint(urb->pipe),
+-			usb_pipein(urb->pipe) ? "in" : "out");
++			is_in ? "in" : "out");
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+ 	ret = usb_hcd_check_unlink_urb(hcd, urb, status);
+@@ -2026,45 +2026,23 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+ 	if (!qh)
+ 		goto done;
+ 
+-	/* Any URB not actively programmed into endpoint hardware can be
++	/* 
++	 * Any URB not actively programmed into endpoint hardware can be
+ 	 * immediately given back; that's any URB not at the head of an
+ 	 * endpoint queue, unless someday we get real DMA queues.  And even
+ 	 * if it's at the head, it might not be known to the hardware...
+ 	 *
+-	 * Otherwise abort current transfer, pending dma, etc.; urb->status
++	 * Otherwise abort current transfer, pending DMA, etc.; urb->status
+ 	 * has already been updated.  This is a synchronous abort; it'd be
+ 	 * OK to hold off until after some IRQ, though.
++	 *
++	 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
+ 	 */
+-	if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list)
+-		ret = -EINPROGRESS;
+-	else {
+-		switch (qh->type) {
+-		case USB_ENDPOINT_XFER_CONTROL:
+-			sched = &musb->control;
+-			break;
+-		case USB_ENDPOINT_XFER_BULK:
+-			if (qh->mux == 1) {
+-				if (usb_pipein(urb->pipe))
+-					sched = &musb->in_bulk;
+-				else
+-					sched = &musb->out_bulk;
+-				break;
+-			}
+-		default:
+-			/* REVISIT when we get a schedule tree, periodic
+-			 * transfers won't always be at the head of a
+-			 * singleton queue...
+-			 */
+-			sched = NULL;
+-			break;
+-		}
+-	}
+-
+-	/* NOTE:  qh is invalid unless !list_empty(&hep->urb_list) */
+-	if (ret < 0 || (sched && qh != first_qh(sched))) {
++	if (!qh->is_ready
++			|| urb->urb_list.prev != &qh->hep->urb_list
++			|| musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
+ 		int	ready = qh->is_ready;
+ 
+-		ret = 0;
+ 		qh->is_ready = 0;
+ 		musb_giveback(musb, urb, 0);
+ 		qh->is_ready = ready;
+@@ -2088,13 +2066,11 @@ done:
+ static void
+ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
+ {
+-	u8			epnum = hep->desc.bEndpointAddress;
++	u8			is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
+ 	unsigned long		flags;
+ 	struct musb		*musb = hcd_to_musb(hcd);
+-	u8			is_in = epnum & USB_DIR_IN;
+ 	struct musb_qh		*qh;
+ 	struct urb		*urb;
+-	struct list_head	*sched;
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+ 
+@@ -2102,31 +2078,11 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
+ 	if (qh == NULL)
+ 		goto exit;
+ 
+-	switch (qh->type) {
+-	case USB_ENDPOINT_XFER_CONTROL:
+-		sched = &musb->control;
+-		break;
+-	case USB_ENDPOINT_XFER_BULK:
+-		if (qh->mux == 1) {
+-			if (is_in)
+-				sched = &musb->in_bulk;
+-			else
+-				sched = &musb->out_bulk;
+-			break;
+-		}
+-	default:
+-		/* REVISIT when we get a schedule tree, periodic transfers
+-		 * won't always be at the head of a singleton queue...
+-		 */
+-		sched = NULL;
+-		break;
+-	}
+-
+-	/* NOTE:  qh is invalid unless !list_empty(&hep->urb_list) */
++	/* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
+ 
+-	/* kick first urb off the hardware, if needed */
++	/* Kick the first URB off the hardware, if needed */
+ 	qh->is_ready = 0;
+-	if (!sched || qh == first_qh(sched)) {
++	if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
+ 		urb = next_urb(qh);
+ 
+ 		/* make software (then hardware) stop ASAP */
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0020-musb_host-streamline-musb_cleanup_urb-calls.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0020-musb_host-streamline-musb_cleanup_urb-calls.patch
new file mode 100644
index 0000000000..d89eaadd61
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0020-musb_host-streamline-musb_cleanup_urb-calls.patch
@@ -0,0 +1,58 @@
+From d408894fa4263440ed8a9e68566bacea7e6f6bed Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Date: Fri, 27 Mar 2009 12:57:50 -0700
+Subject: [PATCH] musb_host: streamline musb_cleanup_urb() calls
+
+The argument for the 'is_in' parameter of musb_cleanup_urb()
+is always extracted from an URB that's passed to the function.
+So that parameter is superfluous; remove it.
+
+Signed-off-by: Sergei Shtylyov <sshtylyov-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_host.c |    9 +++++----
+ 1 files changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index e121e0e..71e835e 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -1950,14 +1950,15 @@ done:
+  * called with controller locked, irqs blocked
+  * that hardware queue advances to the next transfer, unless prevented
+  */
+-static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in)
++static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
+ {
+ 	struct musb_hw_ep	*ep = qh->hw_ep;
+ 	void __iomem		*epio = ep->regs;
+ 	unsigned		hw_end = ep->epnum;
+ 	void __iomem		*regs = ep->musb->mregs;
+-	u16			csr;
++	int			is_in = usb_pipein(urb->pipe);
+ 	int			status = 0;
++	u16			csr;
+ 
+ 	musb_ep_select(regs, hw_end);
+ 
+@@ -2056,7 +2057,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+ 			kfree(qh);
+ 		}
+ 	} else
+-		ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
++		ret = musb_cleanup_urb(urb, qh);
+ done:
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+ 	return ret;
+@@ -2090,7 +2091,7 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
+ 			urb->status = -ESHUTDOWN;
+ 
+ 		/* cleanup */
+-		musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
++		musb_cleanup_urb(urb, qh);
+ 
+ 		/* Then nuke all the others ... and advance the
+ 		 * queue on hw_ep (e.g. bulk ring) when we're done.
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0021-twl4030-usb-fix-minor-reporting-goofage.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0021-twl4030-usb-fix-minor-reporting-goofage.patch
new file mode 100644
index 0000000000..d9733f92b0
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0021-twl4030-usb-fix-minor-reporting-goofage.patch
@@ -0,0 +1,70 @@
+From c4804e5a447275553c55bbb0ab1748954cb8fbfc Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Tue, 31 Mar 2009 12:26:10 -0700
+Subject: [PATCH] twl4030-usb: fix minor reporting goofage
+
+Fix a reporting glitch in the twl4030 USB transceiver code.
+It wasn't properly distinguishing the two types of active
+USB link:  ID grounded, vs not.  In the current code that
+distinction doesn't much matter; in the future this bugfix
+should help support better USB controller communications.
+
+Provide a comment sorting out some of the cryptic bits of
+the manual:  different sections use different names for
+key signals, and the register definitions don't help much
+without the explanations and diagrams.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/otg/twl4030-usb.c |   26 +++++++++++++++++++-------
+ 1 files changed, 19 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/usb/otg/twl4030-usb.c b/drivers/usb/otg/twl4030-usb.c
+index d9478d0..f740390 100644
+--- a/drivers/usb/otg/twl4030-usb.c
++++ b/drivers/usb/otg/twl4030-usb.c
+@@ -217,6 +217,7 @@
+ 
+ /* In module TWL4030_MODULE_PM_MASTER */
+ #define PROTECT_KEY			0x0E
++#define STS_HW_CONDITIONS		0x0F
+ 
+ /* In module TWL4030_MODULE_PM_RECEIVER */
+ #define VUSB_DEDICATED1			0x7D
+@@ -351,15 +352,26 @@ static enum linkstat twl4030_usb_linkstat(struct twl4030_usb *twl)
+ 	int	status;
+ 	int	linkstat = USB_LINK_UNKNOWN;
+ 
+-	/* STS_HW_CONDITIONS */
+-	status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER, 0x0f);
++	/*
++	 * For ID/VBUS sensing, see manual section 15.4.8 ...
++	 * except when using only battery backup power, two
++	 * comparators produce VBUS_PRES and ID_PRES signals,
++	 * which don't match docs elsewhere.  But ... BIT(7)
++	 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
++	 * seem to match up.  If either is true the USB_PRES
++	 * signal is active, the OTG module is activated, and
++	 * its interrupt may be raised (may wake the system).
++	 */
++	status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER,
++			STS_HW_CONDITIONS);
+ 	if (status < 0)
+ 		dev_err(twl->dev, "USB link status err %d\n", status);
+-	else if (status & BIT(7))
+-		linkstat = USB_LINK_VBUS;
+-	else if (status & BIT(2))
+-		linkstat = USB_LINK_ID;
+-	else
++	else if (status & (BIT(7) | BIT(2))) {
++		if (status & BIT(2))
++			linkstat = USB_LINK_ID;
++		else
++			linkstat = USB_LINK_VBUS;
++	} else
+ 		linkstat = USB_LINK_NONE;
+ 
+ 	dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0022-musb-use-dma-mode-1-for-TX-if-transfer-size-equals.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0022-musb-use-dma-mode-1-for-TX-if-transfer-size-equals.patch
new file mode 100644
index 0000000000..16b5b9908b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0022-musb-use-dma-mode-1-for-TX-if-transfer-size-equals.patch
@@ -0,0 +1,38 @@
+From ba59a0812ba0e223bd0af8f4dea6c971b6289696 Mon Sep 17 00:00:00 2001
+From: Anand Gadiyar <gadiyar-l0cyMroinI0@public.gmane.org>
+Date: Thu, 2 Apr 2009 12:07:08 -0700
+Subject: [PATCH] musb: use dma mode 1 for TX if transfer size equals maxpacket (v2)
+
+Currently, with Inventra DMA, we use Mode 0 if transfer size is less
+than or equal to the endpoint's maxpacket size.  This requires that
+we explicitly set TXPKTRDY for that transfer.
+
+However the musb_g_tx code will not set TXPKTRDY twice if the last
+transfer is exactly equal to maxpacket, even if request->zero is set.
+Using Mode 1 will solve this; a better fix might be in musb_g_tx().
+
+Without this change, musb will not correctly send out a ZLP if the
+last transfer is the maxpacket size and request->zero is set.
+
+Signed-off-by: Anand Gadiyar <gadiyar-l0cyMroinI0@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_gadget.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
+index bc197b2..e8f920c 100644
+--- a/drivers/usb/musb/musb_gadget.c
++++ b/drivers/usb/musb/musb_gadget.c
+@@ -310,7 +310,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
+ 			/* setup DMA, then program endpoint CSR */
+ 			request_size = min(request->length,
+ 						musb_ep->dma->max_len);
+-			if (request_size <= musb_ep->packet_sz)
++			if (request_size < musb_ep->packet_sz)
+ 				musb_ep->dma->desired_mode = 0;
+ 			else
+ 				musb_ep->dma->desired_mode = 1;
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0023-musb-add-high-bandwidth-ISO-support.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0023-musb-add-high-bandwidth-ISO-support.patch
new file mode 100644
index 0000000000..3038dd171d
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0023-musb-add-high-bandwidth-ISO-support.patch
@@ -0,0 +1,187 @@
+From 2e049a88b729ae2fdc0ecdabad1857810bd62737 Mon Sep 17 00:00:00 2001
+From: Ajay Kumar Gupta <ajay.gupta-l0cyMroinI0@public.gmane.org>
+Date: Fri, 3 Apr 2009 16:16:17 -0700
+Subject: [PATCH] musb: add high bandwidth ISO support
+
+Tested on OMAP3 host side with Creative (Live! Cam Optia) USB camera
+which uses high bandwidth isochronous IN endpoints.  FIFO mode 4 is
+updated to provide the needed 4K endpoint buffer without breaking
+the g_nokia composite gadget configuration.  (This is the only
+gadget driver known to use enough endpoints to notice the change.)
+
+Signed-off-by: Ajay Kumar Gupta <ajay.gupta-l0cyMroinI0@public.gmane.org>
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_core.c |   19 ++++++++---------
+ drivers/usb/musb/musb_core.h |    3 ++
+ drivers/usb/musb/musb_host.c |   47 +++++++++++++++++++++++++++++++----------
+ drivers/usb/musb/musb_host.h |    1 +
+ 4 files changed, 48 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index a1de43b..d953305 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -1068,14 +1068,13 @@ static struct fifo_cfg __initdata mode_4_cfg[] = {
+ { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
+ { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
+ { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
+-{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 512, },
+-{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 512, },
+-{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 512, },
+-{ .hw_ep_num = 13, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num = 13, .style = FIFO_RX,   .maxpacket = 512, },
++{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
++{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
++{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
++{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
++{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
++{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
++{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
+ { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
+ { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
+ };
+@@ -1335,11 +1334,11 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
+ 	}
+ 	if (reg & MUSB_CONFIGDATA_HBRXE) {
+ 		strcat(aInfo, ", HB-ISO Rx");
+-		strcat(aInfo, " (X)");		/* no driver support */
++		musb->hb_iso_rx = true;
+ 	}
+ 	if (reg & MUSB_CONFIGDATA_HBTXE) {
+ 		strcat(aInfo, ", HB-ISO Tx");
+-		strcat(aInfo, " (X)");		/* no driver support */
++		musb->hb_iso_tx = true;
+ 	}
+ 	if (reg & MUSB_CONFIGDATA_SOFTCONE)
+ 		strcat(aInfo, ", SoftConn");
+diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
+index f56a56c..0ac4faf 100644
+--- a/drivers/usb/musb/musb_core.h
++++ b/drivers/usb/musb/musb_core.h
+@@ -387,6 +387,9 @@ struct musb {
+ 	unsigned is_multipoint:1;
+ 	unsigned ignore_disconnect:1;	/* during bus resets */
+ 
++	unsigned		hb_iso_rx:1;	/* high bandwidth iso rx? */
++	unsigned		hb_iso_tx:1;	/* high bandwidth iso tx? */
++
+ #ifdef C_MP_TX
+ 	unsigned bulk_split:1;
+ #define	can_bulk_split(musb,type) \
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index 71e835e..ece5122 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -602,7 +602,8 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
+ 	musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
+ 	musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
+ 	/* NOTE: bulk combining rewrites high bits of maxpacket */
+-	musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket);
++	musb_writew(ep->regs, MUSB_RXMAXP,
++			qh->maxpacket | ((qh->hb_mult - 1) << 11));
+ 
+ 	ep->rx_reinit = 0;
+ }
+@@ -624,9 +625,10 @@ static bool musb_tx_dma_program(struct dma_controller *dma,
+ 	csr = musb_readw(epio, MUSB_TXCSR);
+ 	if (length > pkt_size) {
+ 		mode = 1;
+-		csr |= MUSB_TXCSR_AUTOSET
+-			| MUSB_TXCSR_DMAMODE
+-			| MUSB_TXCSR_DMAENAB;
++		csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
++		/* autoset shouldn't be set in high bandwidth */
++		if (qh->hb_mult == 1)
++			csr |= MUSB_TXCSR_AUTOSET;
+ 	} else {
+ 		mode = 0;
+ 		csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
+@@ -1432,6 +1434,10 @@ void musb_host_rx(struct musb *musb, u8 epnum)
+ 			/* packet error reported later */
+ 			iso_err = true;
+ 		}
++	} else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
++		DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
++				epnum);
++		status = -EPROTO;
+ 	}
+ 
+ 	/* faults abort the transfer */
+@@ -1639,7 +1645,11 @@ void musb_host_rx(struct musb *musb, u8 epnum)
+ 				val &= ~MUSB_RXCSR_H_AUTOREQ;
+ 			else
+ 				val |= MUSB_RXCSR_H_AUTOREQ;
+-			val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
++			val |= MUSB_RXCSR_DMAENAB;
++
++			/* autoclear shouldn't be set in high bandwidth */
++			if (qh->hb_mult == 1)
++				val |= MUSB_RXCSR_AUTOCLEAR;
+ 
+ 			musb_writew(epio, MUSB_RXCSR,
+ 				MUSB_RXCSR_H_WZC_BITS | val);
+@@ -1725,9 +1735,10 @@ static int musb_schedule(
+ 			continue;
+ 
+ 		if (is_in)
+-			diff = hw_ep->max_packet_sz_rx - qh->maxpacket;
++			diff = hw_ep->max_packet_sz_rx;
+ 		else
+-			diff = hw_ep->max_packet_sz_tx - qh->maxpacket;
++			diff = hw_ep->max_packet_sz_tx;
++		diff -= (qh->maxpacket * qh->hb_mult);
+ 
+ 		if (diff >= 0 && best_diff > diff) {
+ 			best_diff = diff;
+@@ -1830,15 +1841,27 @@ static int musb_urb_enqueue(
+ 	qh->is_ready = 1;
+ 
+ 	qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
++	qh->type = usb_endpoint_type(epd);
+ 
+-	/* no high bandwidth support yet */
+-	if (qh->maxpacket & ~0x7ff) {
+-		ret = -EMSGSIZE;
+-		goto done;
++	/* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
++	 * Some musb cores don't support high bandwidth ISO transfers; and
++	 * we don't (yet!) support high bandwidth interrupt transfers.
++	 */
++	qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
++	if (qh->hb_mult > 1) {
++		int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
++
++		if (ok)
++			ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
++				|| (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
++		if (!ok) {
++			ret = -EMSGSIZE;
++			goto done;
++		}
++		qh->maxpacket &= 0x7ff;
+ 	}
+ 
+ 	qh->epnum = usb_endpoint_num(epd);
+-	qh->type = usb_endpoint_type(epd);
+ 
+ 	/* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
+ 	qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
+diff --git a/drivers/usb/musb/musb_host.h b/drivers/usb/musb/musb_host.h
+index 0b7fbcd..14b0077 100644
+--- a/drivers/usb/musb/musb_host.h
++++ b/drivers/usb/musb/musb_host.h
+@@ -67,6 +67,7 @@ struct musb_qh {
+ 	u8			is_ready;	/* safe to modify hw_ep */
+ 	u8			type;		/* XFERTYPE_* */
+ 	u8			epnum;
++	u8			hb_mult;	/* high bandwidth pkts per uf */
+ 	u16			maxpacket;
+ 	u16			frame;		/* for periodic schedule */
+ 	unsigned		iso_idx;	/* in urb->iso_frame_desc[] */
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0024-USB-otg-adding-nop-usb-transceiver.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0024-USB-otg-adding-nop-usb-transceiver.patch
new file mode 100644
index 0000000000..67004d7ec6
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0024-USB-otg-adding-nop-usb-transceiver.patch
@@ -0,0 +1,259 @@
+From de835357b3597af5304742cbd89771d70533292a Mon Sep 17 00:00:00 2001
+From: Ajay Kumar Gupta <ajay.gupta@ti.com>
+Date: Fri, 6 Feb 2009 17:32:35 +0530
+Subject: [PATCH] USB: otg: adding nop usb transceiver
+
+NOP transceiver is used by all the usb transceiver which are mostly
+autonomous and doesn't require any programming or which are built
+into the usb ip itself.NOP transceiver only allocates the memory
+for struct xceiv and calls otg_set_transceiver() so function call
+to otg_get_transceiver() will return a valid transceiver.
+
+NOP transceiver device should be registered by calling
+usb_nop_xceiv_register() from platform files.
+
+Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
+Cc: Felipe Balbi <felipe.balbi@nokia.com>
+Cc: David Brownell <dbrownell@users.sourceforge.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+---
+ drivers/usb/otg/Kconfig         |    8 ++
+ drivers/usb/otg/Makefile        |    1 +
+ drivers/usb/otg/nop-usb-xceiv.c |  180 +++++++++++++++++++++++++++++++++++++++
+ include/linux/usb/otg.h         |    4 +
+ 4 files changed, 193 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/usb/otg/nop-usb-xceiv.c
+
+diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
+index 5790a5b..aa884d0 100644
+--- a/drivers/usb/otg/Kconfig
++++ b/drivers/usb/otg/Kconfig
+@@ -51,4 +51,12 @@ config TWL4030_USB
+ 	  This transceiver supports high and full speed devices plus,
+ 	  in host mode, low speed.
+ 
++config NOP_USB_XCEIV
++	tristate "NOP USB Transceiver Driver"
++	select USB_OTG_UTILS
++	help
++	 this driver is to be used by all the usb transceiver which are either
++	 built-in with usb ip or which are autonomous and doesn't require any
++	 phy programming such as ISP1x04 etc.
++
+ endif # USB || OTG
+diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
+index d73c7cf..2081678 100644
+--- a/drivers/usb/otg/Makefile
++++ b/drivers/usb/otg/Makefile
+@@ -9,6 +9,7 @@ obj-$(CONFIG_USB_OTG_UTILS)	+= otg.o
+ obj-$(CONFIG_USB_GPIO_VBUS)	+= gpio_vbus.o
+ obj-$(CONFIG_ISP1301_OMAP)	+= isp1301_omap.o
+ obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
++obj-$(CONFIG_NOP_USB_XCEIV)	+= nop-usb-xceiv.o
+ 
+ ccflags-$(CONFIG_USB_DEBUG)	+= -DDEBUG
+ ccflags-$(CONFIG_USB_GADGET_DEBUG) += -DDEBUG
+diff --git a/drivers/usb/otg/nop-usb-xceiv.c b/drivers/usb/otg/nop-usb-xceiv.c
+new file mode 100644
+index 0000000..4b933f6
+--- /dev/null
++++ b/drivers/usb/otg/nop-usb-xceiv.c
+@@ -0,0 +1,180 @@
++/*
++ * drivers/usb/otg/nop-usb-xceiv.c
++ *
++ * NOP USB transceiver for all USB transceiver which are either built-in
++ * into USB IP or which are mostly autonomous.
++ *
++ * Copyright (C) 2009 Texas Instruments Inc
++ * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Current status:
++ * 	this is to add "nop" transceiver for all those phy which is
++ * 	autonomous such as isp1504 etc.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/dma-mapping.h>
++#include <linux/usb/otg.h>
++
++struct nop_usb_xceiv {
++	struct otg_transceiver	otg;
++	struct device		*dev;
++};
++
++static u64 nop_xceiv_dmamask = DMA_32BIT_MASK;
++
++static struct platform_device nop_xceiv_device = {
++	.name           = "nop_usb_xceiv",
++	.id             = -1,
++	.dev = {
++		.dma_mask               = &nop_xceiv_dmamask,
++		.coherent_dma_mask      = DMA_32BIT_MASK,
++		.platform_data          = NULL,
++	},
++};
++
++void usb_nop_xceiv_register(void)
++{
++	if (platform_device_register(&nop_xceiv_device) < 0) {
++		printk(KERN_ERR "Unable to register usb nop transceiver\n");
++		return;
++	}
++}
++
++void usb_nop_xceiv_unregister(void)
++{
++	platform_device_unregister(&nop_xceiv_device);
++}
++
++static inline struct nop_usb_xceiv *xceiv_to_nop(struct otg_transceiver *x)
++{
++	return container_of(x, struct nop_usb_xceiv, otg);
++}
++
++static int nop_set_suspend(struct otg_transceiver *x, int suspend)
++{
++	return 0;
++}
++
++static int nop_set_peripheral(struct otg_transceiver *x,
++		struct usb_gadget *gadget)
++{
++	struct nop_usb_xceiv *nop;
++
++	if (!x)
++		return -ENODEV;
++
++	nop = xceiv_to_nop(x);
++
++	if (!gadget) {
++		nop->otg.gadget = NULL;
++		return -ENODEV;
++	}
++
++	nop->otg.gadget = gadget;
++	nop->otg.state = OTG_STATE_B_IDLE;
++	return 0;
++}
++
++static int nop_set_host(struct otg_transceiver *x, struct usb_bus *host)
++{
++	struct nop_usb_xceiv *nop;
++
++	if (!x)
++		return -ENODEV;
++
++	nop = xceiv_to_nop(x);
++
++	if (!host) {
++		nop->otg.host = NULL;
++		return -ENODEV;
++	}
++
++	nop->otg.host = host;
++	return 0;
++}
++
++static int __devinit nop_usb_xceiv_probe(struct platform_device *pdev)
++{
++	struct nop_usb_xceiv	*nop;
++	int err;
++
++	nop = kzalloc(sizeof *nop, GFP_KERNEL);
++	if (!nop)
++		return -ENOMEM;
++
++	nop->dev		= &pdev->dev;
++	nop->otg.dev		= nop->dev;
++	nop->otg.label		= "nop-xceiv";
++	nop->otg.state		= OTG_STATE_UNDEFINED;
++	nop->otg.set_host	= nop_set_host;
++	nop->otg.set_peripheral	= nop_set_peripheral;
++	nop->otg.set_suspend	= nop_set_suspend;
++
++	err = otg_set_transceiver(&nop->otg);
++	if (err) {
++		dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
++			err);
++		goto exit;
++	}
++
++	platform_set_drvdata(pdev, nop);
++
++	return 0;
++exit:
++	kfree(nop);
++	return err;
++}
++
++static int __devexit nop_usb_xceiv_remove(struct platform_device *pdev)
++{
++	struct nop_usb_xceiv *nop = platform_get_drvdata(pdev);
++
++	otg_set_transceiver(NULL);
++
++	platform_set_drvdata(pdev, NULL);
++	kfree(nop);
++
++	return 0;
++}
++
++static struct platform_driver nop_usb_xceiv_driver = {
++	.probe		= nop_usb_xceiv_probe,
++	.remove		= __devexit_p(nop_usb_xceiv_remove),
++	.driver		= {
++		.name	= "nop_usb_xceiv",
++		.owner	= THIS_MODULE,
++	},
++};
++
++static int __init nop_usb_xceiv_init(void)
++{
++	return platform_driver_register(&nop_usb_xceiv_driver);
++}
++subsys_initcall(nop_usb_xceiv_init);
++
++static void __exit nop_usb_xceiv_exit(void)
++{
++	platform_driver_unregister(&nop_usb_xceiv_driver);
++}
++module_exit(nop_usb_xceiv_exit);
++
++MODULE_ALIAS("platform:nop_usb_xceiv");
++MODULE_AUTHOR("Texas Instruments Inc");
++MODULE_DESCRIPTION("NOP USB Transceiver driver");
++MODULE_LICENSE("GPL");
+diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
+index 94df4fe..54f2424 100644
+--- a/include/linux/usb/otg.h
++++ b/include/linux/usb/otg.h
+@@ -80,6 +80,10 @@ struct otg_transceiver {
+ 
+ /* for board-specific init logic */
+ extern int otg_set_transceiver(struct otg_transceiver *);
++#ifdef CONFIG_NOP_USB_XCEIV
++extern void usb_nop_xceiv_register(void);
++extern void usb_nop_xceiv_unregister(void);
++#endif
+ 
+ 
+ /* for usb host and peripheral controller drivers */
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0025-nop-usb-xceiv-behave-when-linked-as-a-module.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0025-nop-usb-xceiv-behave-when-linked-as-a-module.patch
new file mode 100644
index 0000000000..21fe7bea17
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0025-nop-usb-xceiv-behave-when-linked-as-a-module.patch
@@ -0,0 +1,90 @@
+From ae4f027580168814f734cf3c41a662a7f10c744c Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Tue, 31 Mar 2009 12:28:31 -0700
+Subject: [PATCH] nop-usb-xceiv: behave when linked as a module
+
+The NOP OTG transceiver driver needs to be usable from modules.
+Make sure its symbols are always accessible at both compile and
+link time, and make sure the device instance is allocated from
+the heap so that device lifetime rules are obeyed.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/otg/nop-usb-xceiv.c |   25 ++++++++++---------------
+ include/linux/usb/otg.h         |    4 ++--
+ 2 files changed, 12 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/usb/otg/nop-usb-xceiv.c b/drivers/usb/otg/nop-usb-xceiv.c
+index 4b933f6..9ed5ea5 100644
+--- a/drivers/usb/otg/nop-usb-xceiv.c
++++ b/drivers/usb/otg/nop-usb-xceiv.c
+@@ -22,8 +22,8 @@
+  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  *
+  * Current status:
+- * 	this is to add "nop" transceiver for all those phy which is
+- * 	autonomous such as isp1504 etc.
++ *	This provides a "nop" transceiver for PHYs which are
++ *	autonomous such as isp1504, isp1707, etc.
+  */
+ 
+ #include <linux/module.h>
+@@ -36,30 +36,25 @@ struct nop_usb_xceiv {
+ 	struct device		*dev;
+ };
+ 
+-static u64 nop_xceiv_dmamask = DMA_32BIT_MASK;
+-
+-static struct platform_device nop_xceiv_device = {
+-	.name           = "nop_usb_xceiv",
+-	.id             = -1,
+-	.dev = {
+-		.dma_mask               = &nop_xceiv_dmamask,
+-		.coherent_dma_mask      = DMA_32BIT_MASK,
+-		.platform_data          = NULL,
+-	},
+-};
++static struct platform_device *pd;
+ 
+ void usb_nop_xceiv_register(void)
+ {
+-	if (platform_device_register(&nop_xceiv_device) < 0) {
++	if (pd)
++		return;
++	pd = platform_device_register_simple("nop_usb_xceiv", -1, NULL, 0);
++	if (!pd) {
+ 		printk(KERN_ERR "Unable to register usb nop transceiver\n");
+ 		return;
+ 	}
+ }
++EXPORT_SYMBOL(usb_nop_xceiv_register);
+ 
+ void usb_nop_xceiv_unregister(void)
+ {
+-	platform_device_unregister(&nop_xceiv_device);
++	platform_device_unregister(pd);
+ }
++EXPORT_SYMBOL(usb_nop_xceiv_unregister);
+ 
+ static inline struct nop_usb_xceiv *xceiv_to_nop(struct otg_transceiver *x)
+ {
+diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
+index 54f2424..7df8bae 100644
+--- a/include/linux/usb/otg.h
++++ b/include/linux/usb/otg.h
+@@ -80,10 +80,10 @@ struct otg_transceiver {
+ 
+ /* for board-specific init logic */
+ extern int otg_set_transceiver(struct otg_transceiver *);
+-#ifdef CONFIG_NOP_USB_XCEIV
++
++/* sometimes transceivers are accessed only through e.g. ULPI */
+ extern void usb_nop_xceiv_register(void);
+ extern void usb_nop_xceiv_unregister(void);
+-#endif
+ 
+ 
+ /* for usb host and peripheral controller drivers */
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0026-musb-proper-hookup-to-transceiver-drivers.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0026-musb-proper-hookup-to-transceiver-drivers.patch
new file mode 100644
index 0000000000..035a6c7676
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0026-musb-proper-hookup-to-transceiver-drivers.patch
@@ -0,0 +1,1109 @@
+From 43ee46723ffa9dd43d611362064d235440aa04e7 Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Tue, 31 Mar 2009 12:30:04 -0700
+Subject: [PATCH] musb: proper hookup to transceiver drivers
+
+Let the otg_transceiver in MUSB be managed by an external driver;
+don't assume it's integrated.  OMAP3 chips need it to be external,
+and there may be ways to interact with the transceiver which add
+functionality to the system.
+
+Platform init code is responsible for setting up the transeciver,
+probably using the NOP transceiver for integrated transceivers.
+External ones will use whatever the board init code provided,
+such as twl4030 or something more hands-off.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/Kconfig        |    2 +
+ drivers/usb/musb/blackfin.c     |   11 +++-
+ drivers/usb/musb/davinci.c      |   33 +++++++++-----
+ drivers/usb/musb/musb_core.c    |   96 +++++++++++++++++++++------------------
+ drivers/usb/musb/musb_core.h    |    2 +-
+ drivers/usb/musb/musb_gadget.c  |   38 +++++++--------
+ drivers/usb/musb/musb_host.c    |    2 +-
+ drivers/usb/musb/musb_virthub.c |   20 ++++----
+ drivers/usb/musb/omap2430.c     |   62 +++++++++----------------
+ drivers/usb/musb/tusb6010.c     |   70 ++++++++++++++++++-----------
+ 10 files changed, 181 insertions(+), 155 deletions(-)
+
+diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
+index 9985db0..9eea991 100644
+--- a/drivers/usb/musb/Kconfig
++++ b/drivers/usb/musb/Kconfig
+@@ -10,6 +10,7 @@ comment "Enable Host or Gadget support to see Inventra options"
+ config USB_MUSB_HDRC
+ 	depends on (USB || USB_GADGET) && HAVE_CLK
+ 	depends on !SUPERH
++	select NOP_USB_XCEIV if ARCH_DAVINCI
+ 	select TWL4030_USB if MACH_OMAP_3430SDP
+ 	select USB_OTG_UTILS
+ 	tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
+@@ -55,6 +56,7 @@ comment "Blackfin high speed USB Support"
+ config USB_TUSB6010
+ 	boolean "TUSB 6010 support"
+ 	depends on USB_MUSB_HDRC && !USB_MUSB_SOC
++	select NOP_USB_XCEIV
+ 	default y
+ 	help
+ 	  The TUSB 6010 chip, from Texas Instruments, connects a discrete
+diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
+index 7861348..f2f66eb 100644
+--- a/drivers/usb/musb/blackfin.c
++++ b/drivers/usb/musb/blackfin.c
+@@ -143,7 +143,7 @@ static void musb_conn_timer_handler(unsigned long _musb)
+ 	u16 val;
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_A_IDLE:
+ 	case OTG_STATE_A_WAIT_BCON:
+ 		/* Start a new session */
+@@ -154,7 +154,7 @@ static void musb_conn_timer_handler(unsigned long _musb)
+ 		val = musb_readw(musb->mregs, MUSB_DEVCTL);
+ 		if (!(val & MUSB_DEVCTL_BDEVICE)) {
+ 			gpio_set_value(musb->config->gpio_vrsel, 1);
+-			musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
++			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+ 		} else {
+ 			gpio_set_value(musb->config->gpio_vrsel, 0);
+ 
+@@ -247,6 +247,11 @@ int __init musb_platform_init(struct musb *musb)
+ 	}
+ 	gpio_direction_output(musb->config->gpio_vrsel, 0);
+ 
++	usb_nop_xceiv_register();
++	musb->xceiv = otg_get_transceiver();
++	if (!musb->xceiv)
++		return -ENODEV;
++
+ 	if (ANOMALY_05000346) {
+ 		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
+ 		SSYNC();
+@@ -291,7 +296,7 @@ int __init musb_platform_init(struct musb *musb)
+ 			musb_conn_timer_handler, (unsigned long) musb);
+ 	}
+ 	if (is_peripheral_enabled(musb))
+-		musb->xceiv.set_power = bfin_set_power;
++		musb->xceiv->set_power = bfin_set_power;
+ 
+ 	musb->isr = blackfin_interrupt;
+ 
+diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
+index 9fd74bf..81de742 100644
+--- a/drivers/usb/musb/davinci.c
++++ b/drivers/usb/musb/davinci.c
+@@ -200,7 +200,7 @@ static void otg_timer(unsigned long _musb)
+ 	DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_A_WAIT_VFALL:
+ 		/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
+ 		 * seems to mis-handle session "start" otherwise (or in our
+@@ -211,7 +211,7 @@ static void otg_timer(unsigned long _musb)
+ 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ 			break;
+ 		}
+-		musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
++		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+ 		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
+ 			MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
+ 		break;
+@@ -236,7 +236,7 @@ static void otg_timer(unsigned long _musb)
+ 		if (devctl & MUSB_DEVCTL_BDEVICE)
+ 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ 		else
+-			musb->xceiv.state = OTG_STATE_A_IDLE;
++			musb->xceiv->state = OTG_STATE_A_IDLE;
+ 		break;
+ 	default:
+ 		break;
+@@ -310,21 +310,21 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
+ 			 * to stop registering in devctl.
+ 			 */
+ 			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+-			musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
++			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+ 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ 			WARNING("VBUS error workaround (delay coming)\n");
+ 		} else if (is_host_enabled(musb) && drvvbus) {
+ 			musb->is_active = 1;
+ 			MUSB_HST_MODE(musb);
+-			musb->xceiv.default_a = 1;
+-			musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
++			musb->xceiv->default_a = 1;
++			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+ 			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
+ 			del_timer(&otg_workaround);
+ 		} else {
+ 			musb->is_active = 0;
+ 			MUSB_DEV_MODE(musb);
+-			musb->xceiv.default_a = 0;
+-			musb->xceiv.state = OTG_STATE_B_IDLE;
++			musb->xceiv->default_a = 0;
++			musb->xceiv->state = OTG_STATE_B_IDLE;
+ 			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
+ 		}
+ 
+@@ -346,7 +346,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
+ 
+ 	/* poll for ID change */
+ 	if (is_otg_enabled(musb)
+-			&& musb->xceiv.state == OTG_STATE_B_IDLE)
++			&& musb->xceiv->state == OTG_STATE_B_IDLE)
+ 		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ 
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+@@ -365,6 +365,11 @@ int __init musb_platform_init(struct musb *musb)
+ 	void __iomem	*tibase = musb->ctrl_base;
+ 	u32		revision;
+ 
++	usb_nop_xceiv_register();
++	musb->xceiv = otg_get_transceiver();
++	if (!musb->xceiv)
++		return -ENODEV;
++
+ 	musb->mregs += DAVINCI_BASE_OFFSET;
+ 
+ 	clk_enable(musb->clock);
+@@ -372,7 +377,7 @@ int __init musb_platform_init(struct musb *musb)
+ 	/* returns zero if e.g. not clocked */
+ 	revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
+ 	if (revision == 0)
+-		return -ENODEV;
++		goto fail;
+ 
+ 	if (is_host_enabled(musb))
+ 		setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
+@@ -396,6 +401,10 @@ int __init musb_platform_init(struct musb *musb)
+ 
+ 	musb->isr = davinci_interrupt;
+ 	return 0;
++
++fail:
++	usb_nop_xceiv_unregister();
++	return -ENODEV;
+ }
+ 
+ int musb_platform_exit(struct musb *musb)
+@@ -406,7 +415,7 @@ int musb_platform_exit(struct musb *musb)
+ 	davinci_source_power(musb, 0 /*off*/, 1);
+ 
+ 	/* delay, to avoid problems with module reload */
+-	if (is_host_enabled(musb) && musb->xceiv.default_a) {
++	if (is_host_enabled(musb) && musb->xceiv->default_a) {
+ 		int	maxdelay = 30;
+ 		u8	devctl, warn = 0;
+ 
+@@ -435,5 +444,7 @@ int musb_platform_exit(struct musb *musb)
+ 
+ 	clk_disable(musb->clock);
+ 
++	usb_nop_xceiv_unregister();
++
+ 	return 0;
+ }
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index d953305..ac150af 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -267,7 +267,7 @@ void musb_load_testpacket(struct musb *musb)
+ 
+ const char *otg_state_string(struct musb *musb)
+ {
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_A_IDLE:		return "a_idle";
+ 	case OTG_STATE_A_WAIT_VRISE:	return "a_wait_vrise";
+ 	case OTG_STATE_A_WAIT_BCON:	return "a_wait_bcon";
+@@ -302,11 +302,11 @@ void musb_otg_timer_func(unsigned long data)
+ 	unsigned long	flags;
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_B_WAIT_ACON:
+ 		DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
+ 		musb_g_disconnect(musb);
+-		musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
++		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ 		musb->is_active = 0;
+ 		break;
+ 	case OTG_STATE_A_WAIT_BCON:
+@@ -331,20 +331,20 @@ void musb_hnp_stop(struct musb *musb)
+ 	void __iomem	*mbase = musb->mregs;
+ 	u8	reg;
+ 
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_A_PERIPHERAL:
+ 	case OTG_STATE_A_WAIT_VFALL:
+ 	case OTG_STATE_A_WAIT_BCON:
+ 		DBG(1, "HNP: Switching back to A-host\n");
+ 		musb_g_disconnect(musb);
+-		musb->xceiv.state = OTG_STATE_A_IDLE;
++		musb->xceiv->state = OTG_STATE_A_IDLE;
+ 		MUSB_HST_MODE(musb);
+ 		musb->is_active = 0;
+ 		break;
+ 	case OTG_STATE_B_HOST:
+ 		DBG(1, "HNP: Disabling HR\n");
+ 		hcd->self.is_b_host = 0;
+-		musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
++		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ 		MUSB_DEV_MODE(musb);
+ 		reg = musb_readb(mbase, MUSB_POWER);
+ 		reg |= MUSB_POWER_SUSPENDM;
+@@ -402,7 +402,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 
+ 		if (devctl & MUSB_DEVCTL_HM) {
+ #ifdef CONFIG_USB_MUSB_HDRC_HCD
+-			switch (musb->xceiv.state) {
++			switch (musb->xceiv->state) {
+ 			case OTG_STATE_A_SUSPEND:
+ 				/* remote wakeup?  later, GetPortStatus
+ 				 * will stop RESUME signaling
+@@ -425,12 +425,12 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 				musb->rh_timer = jiffies
+ 						+ msecs_to_jiffies(20);
+ 
+-				musb->xceiv.state = OTG_STATE_A_HOST;
++				musb->xceiv->state = OTG_STATE_A_HOST;
+ 				musb->is_active = 1;
+ 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
+ 				break;
+ 			case OTG_STATE_B_WAIT_ACON:
+-				musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
++				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ 				musb->is_active = 1;
+ 				MUSB_DEV_MODE(musb);
+ 				break;
+@@ -441,11 +441,11 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 			}
+ #endif
+ 		} else {
+-			switch (musb->xceiv.state) {
++			switch (musb->xceiv->state) {
+ #ifdef CONFIG_USB_MUSB_HDRC_HCD
+ 			case OTG_STATE_A_SUSPEND:
+ 				/* possibly DISCONNECT is upcoming */
+-				musb->xceiv.state = OTG_STATE_A_HOST;
++				musb->xceiv->state = OTG_STATE_A_HOST;
+ 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
+ 				break;
+ #endif
+@@ -490,7 +490,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 		 */
+ 		musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
+ 		musb->ep0_stage = MUSB_EP0_START;
+-		musb->xceiv.state = OTG_STATE_A_IDLE;
++		musb->xceiv->state = OTG_STATE_A_IDLE;
+ 		MUSB_HST_MODE(musb);
+ 		musb_set_vbus(musb, 1);
+ 
+@@ -516,7 +516,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 		 * REVISIT:  do delays from lots of DEBUG_KERNEL checks
+ 		 * make trouble here, keeping VBUS < 4.4V ?
+ 		 */
+-		switch (musb->xceiv.state) {
++		switch (musb->xceiv->state) {
+ 		case OTG_STATE_A_HOST:
+ 			/* recovery is dicey once we've gotten past the
+ 			 * initial stages of enumeration, but if VBUS
+@@ -602,11 +602,11 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 		MUSB_HST_MODE(musb);
+ 
+ 		/* indicate new connection to OTG machine */
+-		switch (musb->xceiv.state) {
++		switch (musb->xceiv->state) {
+ 		case OTG_STATE_B_PERIPHERAL:
+ 			if (int_usb & MUSB_INTR_SUSPEND) {
+ 				DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
+-				musb->xceiv.state = OTG_STATE_B_HOST;
++				musb->xceiv->state = OTG_STATE_B_HOST;
+ 				hcd->self.is_b_host = 1;
+ 				int_usb &= ~MUSB_INTR_SUSPEND;
+ 			} else
+@@ -614,13 +614,13 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 			break;
+ 		case OTG_STATE_B_WAIT_ACON:
+ 			DBG(1, "HNP: Waiting to switch to b_host state\n");
+-			musb->xceiv.state = OTG_STATE_B_HOST;
++			musb->xceiv->state = OTG_STATE_B_HOST;
+ 			hcd->self.is_b_host = 1;
+ 			break;
+ 		default:
+ 			if ((devctl & MUSB_DEVCTL_VBUS)
+ 					== (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
+-				musb->xceiv.state = OTG_STATE_A_HOST;
++				musb->xceiv->state = OTG_STATE_A_HOST;
+ 				hcd->self.is_b_host = 0;
+ 			}
+ 			break;
+@@ -650,7 +650,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 			}
+ 		} else if (is_peripheral_capable()) {
+ 			DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
+-			switch (musb->xceiv.state) {
++			switch (musb->xceiv->state) {
+ #ifdef CONFIG_USB_OTG
+ 			case OTG_STATE_A_SUSPEND:
+ 				/* We need to ignore disconnect on suspend
+@@ -673,12 +673,12 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 			case OTG_STATE_B_WAIT_ACON:
+ 				DBG(1, "HNP: RESET (%s), to b_peripheral\n",
+ 					otg_state_string(musb));
+-				musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
++				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ 				musb_g_reset(musb);
+ 				break;
+ #endif
+ 			case OTG_STATE_B_IDLE:
+-				musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
++				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ 				/* FALLTHROUGH */
+ 			case OTG_STATE_B_PERIPHERAL:
+ 				musb_g_reset(musb);
+@@ -763,7 +763,7 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
+ 				MUSB_MODE(musb), devctl);
+ 		handled = IRQ_HANDLED;
+ 
+-		switch (musb->xceiv.state) {
++		switch (musb->xceiv->state) {
+ #ifdef CONFIG_USB_MUSB_HDRC_HCD
+ 		case OTG_STATE_A_HOST:
+ 		case OTG_STATE_A_SUSPEND:
+@@ -805,7 +805,7 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
+ 				otg_state_string(musb), devctl, power);
+ 		handled = IRQ_HANDLED;
+ 
+-		switch (musb->xceiv.state) {
++		switch (musb->xceiv->state) {
+ #ifdef	CONFIG_USB_MUSB_OTG
+ 		case OTG_STATE_A_PERIPHERAL:
+ 			/*
+@@ -817,10 +817,10 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
+ 		case OTG_STATE_B_PERIPHERAL:
+ 			musb_g_suspend(musb);
+ 			musb->is_active = is_otg_enabled(musb)
+-					&& musb->xceiv.gadget->b_hnp_enable;
++					&& musb->xceiv->gadget->b_hnp_enable;
+ 			if (musb->is_active) {
+ #ifdef	CONFIG_USB_MUSB_OTG
+-				musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
++				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
+ 				DBG(1, "HNP: Setting timer for b_ase0_brst\n");
+ 				musb_otg_timer.data = (unsigned long)musb;
+ 				mod_timer(&musb_otg_timer, jiffies
+@@ -834,9 +834,9 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
+ 					+ msecs_to_jiffies(musb->a_wait_bcon));
+ 			break;
+ 		case OTG_STATE_A_HOST:
+-			musb->xceiv.state = OTG_STATE_A_SUSPEND;
++			musb->xceiv->state = OTG_STATE_A_SUSPEND;
+ 			musb->is_active = is_otg_enabled(musb)
+-					&& musb->xceiv.host->b_hnp_enable;
++					&& musb->xceiv->host->b_hnp_enable;
+ 			break;
+ 		case OTG_STATE_B_HOST:
+ 			/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
+@@ -1681,7 +1681,7 @@ musb_vbus_store(struct device *dev, struct device_attribute *attr,
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+ 	musb->a_wait_bcon = val;
+-	if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
++	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
+ 		musb->is_active = 0;
+ 	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+@@ -1742,8 +1742,8 @@ static void musb_irq_work(struct work_struct *data)
+ 	struct musb *musb = container_of(data, struct musb, irq_work);
+ 	static int old_state;
+ 
+-	if (musb->xceiv.state != old_state) {
+-		old_state = musb->xceiv.state;
++	if (musb->xceiv->state != old_state) {
++		old_state = musb->xceiv->state;
+ 		sysfs_notify(&musb->controller->kobj, NULL, "mode");
+ 	}
+ }
+@@ -1840,7 +1840,7 @@ static void musb_free(struct musb *musb)
+ 	}
+ 
+ #ifdef CONFIG_USB_MUSB_OTG
+-	put_device(musb->xceiv.dev);
++	put_device(musb->xceiv->dev);
+ #endif
+ 
+ #ifdef CONFIG_USB_MUSB_HDRC_HCD
+@@ -1921,10 +1921,18 @@ bad_config:
+ 		}
+ 	}
+ 
+-	/* assume vbus is off */
+-
+-	/* platform adjusts musb->mregs and musb->isr if needed,
+-	 * and activates clocks
++	/* The musb_platform_init() call:
++	 *   - adjusts musb->mregs and musb->isr if needed,
++	 *   - may initialize an integrated tranceiver
++	 *   - initializes musb->xceiv, usually by otg_get_transceiver()
++	 *   - activates clocks.
++	 *   - stops powering VBUS
++	 *   - assigns musb->board_set_vbus if host mode is enabled
++	 *
++	 * There are various transciever configurations.  Blackfin,
++	 * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
++	 * external/discrete ones in various flavors (twl4030 family,
++	 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
+ 	 */
+ 	musb->isr = generic_interrupt;
+ 	status = musb_platform_init(musb);
+@@ -1992,17 +2000,17 @@ bad_config:
+ 				? "DMA" : "PIO",
+ 			musb->nIrq);
+ 
+-#ifdef CONFIG_USB_MUSB_HDRC_HCD
+-	/* host side needs more setup, except for no-host modes */
+-	if (musb->board_mode != MUSB_PERIPHERAL) {
++	/* host side needs more setup */
++	if (is_host_enabled(musb)) {
+ 		struct usb_hcd	*hcd = musb_to_hcd(musb);
+ 
+-		if (musb->board_mode == MUSB_OTG)
++		otg_set_host(musb->xceiv, &hcd->self);
++
++		if (is_otg_enabled(musb))
+ 			hcd->self.otg_port = 1;
+-		musb->xceiv.host = &hcd->self;
++		musb->xceiv->host = &hcd->self;
+ 		hcd->power_budget = 2 * (plat->power ? : 250);
+ 	}
+-#endif				/* CONFIG_USB_MUSB_HDRC_HCD */
+ 
+ 	/* For the host-only role, we can activate right away.
+ 	 * (We expect the ID pin to be forcibly grounded!!)
+@@ -2010,8 +2018,8 @@ bad_config:
+ 	 */
+ 	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
+ 		MUSB_HST_MODE(musb);
+-		musb->xceiv.default_a = 1;
+-		musb->xceiv.state = OTG_STATE_A_IDLE;
++		musb->xceiv->default_a = 1;
++		musb->xceiv->state = OTG_STATE_A_IDLE;
+ 
+ 		status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
+ 		if (status)
+@@ -2026,8 +2034,8 @@ bad_config:
+ 
+ 	} else /* peripheral is enabled */ {
+ 		MUSB_DEV_MODE(musb);
+-		musb->xceiv.default_a = 0;
+-		musb->xceiv.state = OTG_STATE_B_IDLE;
++		musb->xceiv->default_a = 0;
++		musb->xceiv->state = OTG_STATE_B_IDLE;
+ 
+ 		status = musb_gadget_setup(musb);
+ 		if (status)
+diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
+index 0ac4faf..c3ee348 100644
+--- a/drivers/usb/musb/musb_core.h
++++ b/drivers/usb/musb/musb_core.h
+@@ -356,7 +356,7 @@ struct musb {
+ 	u16			int_rx;
+ 	u16			int_tx;
+ 
+-	struct otg_transceiver	xceiv;
++	struct otg_transceiver	*xceiv;
+ 
+ 	int nIrq;
+ 	unsigned		irq_wake:1;
+diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
+index e8f920c..2fbfba5 100644
+--- a/drivers/usb/musb/musb_gadget.c
++++ b/drivers/usb/musb/musb_gadget.c
+@@ -1406,7 +1406,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+ 
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_B_PERIPHERAL:
+ 		/* NOTE:  OTG state machine doesn't include B_SUSPENDED;
+ 		 * that's part of the standard usb 1.1 state machine, and
+@@ -1508,9 +1508,9 @@ static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
+ {
+ 	struct musb	*musb = gadget_to_musb(gadget);
+ 
+-	if (!musb->xceiv.set_power)
++	if (!musb->xceiv->set_power)
+ 		return -EOPNOTSUPP;
+-	return otg_set_power(&musb->xceiv, mA);
++	return otg_set_power(musb->xceiv, mA);
+ }
+ 
+ static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
+@@ -1733,11 +1733,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+ 
+ 		spin_lock_irqsave(&musb->lock, flags);
+ 
+-		/* REVISIT always use otg_set_peripheral(), handling
+-		 * issues including the root hub one below ...
+-		 */
+-		musb->xceiv.gadget = &musb->g;
+-		musb->xceiv.state = OTG_STATE_B_IDLE;
++		otg_set_peripheral(musb->xceiv, &musb->g);
+ 		musb->is_active = 1;
+ 
+ 		/* FIXME this ignores the softconnect flag.  Drivers are
+@@ -1749,6 +1745,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+ 		if (!is_otg_enabled(musb))
+ 			musb_start(musb);
+ 
++		otg_set_peripheral(musb->xceiv, &musb->g);
++
+ 		spin_unlock_irqrestore(&musb->lock, flags);
+ 
+ 		if (is_otg_enabled(musb)) {
+@@ -1762,8 +1760,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+ 			if (retval < 0) {
+ 				DBG(1, "add_hcd failed, %d\n", retval);
+ 				spin_lock_irqsave(&musb->lock, flags);
+-				musb->xceiv.gadget = NULL;
+-				musb->xceiv.state = OTG_STATE_UNDEFINED;
++				otg_set_peripheral(musb->xceiv, NULL);
+ 				musb->gadget_driver = NULL;
+ 				musb->g.dev.driver = NULL;
+ 				spin_unlock_irqrestore(&musb->lock, flags);
+@@ -1846,8 +1843,9 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+ 
+ 		(void) musb_gadget_vbus_draw(&musb->g, 0);
+ 
+-		musb->xceiv.state = OTG_STATE_UNDEFINED;
++		musb->xceiv->state = OTG_STATE_UNDEFINED;
+ 		stop_activity(musb, driver);
++		otg_set_peripheral(musb->xceiv, NULL);
+ 
+ 		DBG(3, "unregistering driver %s\n", driver->function);
+ 		spin_unlock_irqrestore(&musb->lock, flags);
+@@ -1883,7 +1881,7 @@ EXPORT_SYMBOL(usb_gadget_unregister_driver);
+ void musb_g_resume(struct musb *musb)
+ {
+ 	musb->is_suspended = 0;
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_B_IDLE:
+ 		break;
+ 	case OTG_STATE_B_WAIT_ACON:
+@@ -1909,10 +1907,10 @@ void musb_g_suspend(struct musb *musb)
+ 	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ 	DBG(3, "devctl %02x\n", devctl);
+ 
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_B_IDLE:
+ 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
+-			musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
++			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ 		break;
+ 	case OTG_STATE_B_PERIPHERAL:
+ 		musb->is_suspended = 1;
+@@ -1958,22 +1956,22 @@ void musb_g_disconnect(struct musb *musb)
+ 		spin_lock(&musb->lock);
+ 	}
+ 
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	default:
+ #ifdef	CONFIG_USB_MUSB_OTG
+ 		DBG(2, "Unhandled disconnect %s, setting a_idle\n",
+ 			otg_state_string(musb));
+-		musb->xceiv.state = OTG_STATE_A_IDLE;
++		musb->xceiv->state = OTG_STATE_A_IDLE;
+ 		break;
+ 	case OTG_STATE_A_PERIPHERAL:
+-		musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
++		musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+ 		break;
+ 	case OTG_STATE_B_WAIT_ACON:
+ 	case OTG_STATE_B_HOST:
+ #endif
+ 	case OTG_STATE_B_PERIPHERAL:
+ 	case OTG_STATE_B_IDLE:
+-		musb->xceiv.state = OTG_STATE_B_IDLE;
++		musb->xceiv->state = OTG_STATE_B_IDLE;
+ 		break;
+ 	case OTG_STATE_B_SRP_INIT:
+ 		break;
+@@ -2029,10 +2027,10 @@ __acquires(musb->lock)
+ 	 * or else after HNP, as A-Device
+ 	 */
+ 	if (devctl & MUSB_DEVCTL_BDEVICE) {
+-		musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
++		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ 		musb->g.is_a_peripheral = 0;
+ 	} else if (is_otg_enabled(musb)) {
+-		musb->xceiv.state = OTG_STATE_A_PERIPHERAL;
++		musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
+ 		musb->g.is_a_peripheral = 1;
+ 	} else
+ 		WARN_ON(1);
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index ece5122..795dabe 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -2169,7 +2169,7 @@ static int musb_bus_suspend(struct usb_hcd *hcd)
+ {
+ 	struct musb	*musb = hcd_to_musb(hcd);
+ 
+-	if (musb->xceiv.state == OTG_STATE_A_SUSPEND)
++	if (musb->xceiv->state == OTG_STATE_A_SUSPEND)
+ 		return 0;
+ 
+ 	if (is_host_active(musb) && musb->is_active) {
+diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
+index e0e9ce5..7e7900f 100644
+--- a/drivers/usb/musb/musb_virthub.c
++++ b/drivers/usb/musb/musb_virthub.c
+@@ -78,18 +78,18 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
+ 		DBG(3, "Root port suspended, power %02x\n", power);
+ 
+ 		musb->port1_status |= USB_PORT_STAT_SUSPEND;
+-		switch (musb->xceiv.state) {
++		switch (musb->xceiv->state) {
+ 		case OTG_STATE_A_HOST:
+-			musb->xceiv.state = OTG_STATE_A_SUSPEND;
++			musb->xceiv->state = OTG_STATE_A_SUSPEND;
+ 			musb->is_active = is_otg_enabled(musb)
+-					&& musb->xceiv.host->b_hnp_enable;
++					&& musb->xceiv->host->b_hnp_enable;
+ 			musb_platform_try_idle(musb, 0);
+ 			break;
+ #ifdef	CONFIG_USB_MUSB_OTG
+ 		case OTG_STATE_B_HOST:
+-			musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
++			musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
+ 			musb->is_active = is_otg_enabled(musb)
+-					&& musb->xceiv.host->b_hnp_enable;
++					&& musb->xceiv->host->b_hnp_enable;
+ 			musb_platform_try_idle(musb, 0);
+ 			break;
+ #endif
+@@ -116,7 +116,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
+ 	void __iomem	*mbase = musb->mregs;
+ 
+ #ifdef CONFIG_USB_MUSB_OTG
+-	if (musb->xceiv.state == OTG_STATE_B_IDLE) {
++	if (musb->xceiv->state == OTG_STATE_B_IDLE) {
+ 		DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n");
+ 		musb->port1_status &= ~USB_PORT_STAT_RESET;
+ 		return;
+@@ -186,14 +186,14 @@ void musb_root_disconnect(struct musb *musb)
+ 	usb_hcd_poll_rh_status(musb_to_hcd(musb));
+ 	musb->is_active = 0;
+ 
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_A_HOST:
+ 	case OTG_STATE_A_SUSPEND:
+-		musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
++		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+ 		musb->is_active = 0;
+ 		break;
+ 	case OTG_STATE_A_WAIT_VFALL:
+-		musb->xceiv.state = OTG_STATE_B_IDLE;
++		musb->xceiv->state = OTG_STATE_B_IDLE;
+ 		break;
+ 	default:
+ 		DBG(1, "host disconnect (%s)\n", otg_state_string(musb));
+@@ -332,7 +332,7 @@ int musb_hub_control(
+ 			musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
+ 			usb_hcd_poll_rh_status(musb_to_hcd(musb));
+ 			/* NOTE: it might really be A_WAIT_BCON ... */
+-			musb->xceiv.state = OTG_STATE_A_HOST;
++			musb->xceiv->state = OTG_STATE_A_HOST;
+ 		}
+ 
+ 		put_unaligned(cpu_to_le32(musb->port1_status
+diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
+index 901dffd..5f67b03 100644
+--- a/drivers/usb/musb/omap2430.c
++++ b/drivers/usb/musb/omap2430.c
+@@ -62,17 +62,17 @@ static void musb_do_idle(unsigned long _musb)
+ 
+ 	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ 
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_A_WAIT_BCON:
+ 		devctl &= ~MUSB_DEVCTL_SESSION;
+ 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+ 
+ 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ 		if (devctl & MUSB_DEVCTL_BDEVICE) {
+-			musb->xceiv.state = OTG_STATE_B_IDLE;
++			musb->xceiv->state = OTG_STATE_B_IDLE;
+ 			MUSB_DEV_MODE(musb);
+ 		} else {
+-			musb->xceiv.state = OTG_STATE_A_IDLE;
++			musb->xceiv->state = OTG_STATE_A_IDLE;
+ 			MUSB_HST_MODE(musb);
+ 		}
+ 		break;
+@@ -90,7 +90,7 @@ static void musb_do_idle(unsigned long _musb)
+ 			musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
+ 			usb_hcd_poll_rh_status(musb_to_hcd(musb));
+ 			/* NOTE: it might really be A_WAIT_BCON ... */
+-			musb->xceiv.state = OTG_STATE_A_HOST;
++			musb->xceiv->state = OTG_STATE_A_HOST;
+ 		}
+ 		break;
+ #endif
+@@ -98,9 +98,9 @@ static void musb_do_idle(unsigned long _musb)
+ 	case OTG_STATE_A_HOST:
+ 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ 		if (devctl &  MUSB_DEVCTL_BDEVICE)
+-			musb->xceiv.state = OTG_STATE_B_IDLE;
++			musb->xceiv->state = OTG_STATE_B_IDLE;
+ 		else
+-			musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
++			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+ #endif
+ 	default:
+ 		break;
+@@ -119,7 +119,7 @@ void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
+ 
+ 	/* Never idle if active, or when VBUS timeout is not set as host */
+ 	if (musb->is_active || ((musb->a_wait_bcon == 0)
+-			&& (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
++			&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
+ 		DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+ 		del_timer(&musb_idle_timer);
+ 		last_timer = jiffies;
+@@ -164,8 +164,8 @@ static void omap_set_vbus(struct musb *musb, int is_on)
+ 
+ 	if (is_on) {
+ 		musb->is_active = 1;
+-		musb->xceiv.default_a = 1;
+-		musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
++		musb->xceiv->default_a = 1;
++		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+ 		devctl |= MUSB_DEVCTL_SESSION;
+ 
+ 		MUSB_HST_MODE(musb);
+@@ -176,8 +176,8 @@ static void omap_set_vbus(struct musb *musb, int is_on)
+ 		 * jumping right to B_IDLE...
+ 		 */
+ 
+-		musb->xceiv.default_a = 0;
+-		musb->xceiv.state = OTG_STATE_B_IDLE;
++		musb->xceiv->default_a = 0;
++		musb->xceiv->state = OTG_STATE_B_IDLE;
+ 		devctl &= ~MUSB_DEVCTL_SESSION;
+ 
+ 		MUSB_DEV_MODE(musb);
+@@ -189,10 +189,6 @@ static void omap_set_vbus(struct musb *musb, int is_on)
+ 		otg_state_string(musb),
+ 		musb_readb(musb->mregs, MUSB_DEVCTL));
+ }
+-static int omap_set_power(struct otg_transceiver *x, unsigned mA)
+-{
+-	return 0;
+-}
+ 
+ static int musb_platform_resume(struct musb *musb);
+ 
+@@ -203,24 +199,6 @@ int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
+ 	devctl |= MUSB_DEVCTL_SESSION;
+ 	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+ 
+-	switch (musb_mode) {
+-#ifdef CONFIG_USB_MUSB_HDRC_HCD
+-	case MUSB_HOST:
+-		otg_set_host(&musb->xceiv, musb->xceiv.host);
+-		break;
+-#endif
+-#ifdef CONFIG_USB_GADGET_MUSB_HDRC
+-	case MUSB_PERIPHERAL:
+-		otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
+-		break;
+-#endif
+-#ifdef CONFIG_USB_MUSB_OTG
+-	case MUSB_OTG:
+-		break;
+-#endif
+-	default:
+-		return -EINVAL;
+-	}
+ 	return 0;
+ }
+ 
+@@ -232,6 +210,16 @@ int __init musb_platform_init(struct musb *musb)
+ 	omap_cfg_reg(AE5_2430_USB0HS_STP);
+ #endif
+ 
++	/* We require some kind of external transceiver, hooked
++	 * up through ULPI.  TWL4030-family PMICs include one,
++	 * which needs a driver, drivers aren't always needed.
++	 */
++	musb->xceiv = otg_get_transceiver();
++	if (!musb->xceiv) {
++		pr_err("HS USB OTG: no transceiver configured\n");
++		return -ENODEV;
++	}
++
+ 	musb_platform_resume(musb);
+ 
+ 	l = omap_readl(OTG_SYSCONFIG);
+@@ -258,8 +246,6 @@ int __init musb_platform_init(struct musb *musb)
+ 
+ 	if (is_host_enabled(musb))
+ 		musb->board_set_vbus = omap_set_vbus;
+-	if (is_peripheral_enabled(musb))
+-		musb->xceiv.set_power = omap_set_power;
+ 	musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
+ 
+ 	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
+@@ -283,8 +269,7 @@ int musb_platform_suspend(struct musb *musb)
+ 	l |= ENABLEWAKEUP;	/* enable wakeup */
+ 	omap_writel(l, OTG_SYSCONFIG);
+ 
+-	if (musb->xceiv.set_suspend)
+-		musb->xceiv.set_suspend(&musb->xceiv, 1);
++	otg_set_suspend(musb->xceiv, 1);
+ 
+ 	if (musb->set_clock)
+ 		musb->set_clock(musb->clock, 0);
+@@ -301,8 +286,7 @@ static int musb_platform_resume(struct musb *musb)
+ 	if (!musb->clock)
+ 		return 0;
+ 
+-	if (musb->xceiv.set_suspend)
+-		musb->xceiv.set_suspend(&musb->xceiv, 0);
++	otg_set_suspend(musb->xceiv, 0);
+ 
+ 	if (musb->set_clock)
+ 		musb->set_clock(musb->clock, 1);
+diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
+index 9e20fd0..c473dec 100644
+--- a/drivers/usb/musb/tusb6010.c
++++ b/drivers/usb/musb/tusb6010.c
+@@ -260,6 +260,8 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
+ 		tusb_fifo_read_unaligned(fifo, buf, len);
+ }
+ 
++static struct musb *the_musb;
++
+ #ifdef CONFIG_USB_GADGET_MUSB_HDRC
+ 
+ /* This is used by gadget drivers, and OTG transceiver logic, allowing
+@@ -270,7 +272,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
+  */
+ static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
+ {
+-	struct musb	*musb = container_of(x, struct musb, xceiv);
++	struct musb	*musb = the_musb;
+ 	void __iomem	*tbase = musb->ctrl_base;
+ 	u32		reg;
+ 
+@@ -420,7 +422,7 @@ static void musb_do_idle(unsigned long _musb)
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+ 
+-	switch (musb->xceiv.state) {
++	switch (musb->xceiv->state) {
+ 	case OTG_STATE_A_WAIT_BCON:
+ 		if ((musb->a_wait_bcon != 0)
+ 			&& (musb->idle_timeout == 0
+@@ -484,7 +486,7 @@ void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
+ 
+ 	/* Never idle if active, or when VBUS timeout is not set as host */
+ 	if (musb->is_active || ((musb->a_wait_bcon == 0)
+-			&& (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
++			&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
+ 		DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+ 		del_timer(&musb_idle_timer);
+ 		last_timer = jiffies;
+@@ -533,8 +535,8 @@ static void tusb_source_power(struct musb *musb, int is_on)
+ 		if (musb->set_clock)
+ 			musb->set_clock(musb->clock, 1);
+ 		timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
+-		musb->xceiv.default_a = 1;
+-		musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
++		musb->xceiv->default_a = 1;
++		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+ 		devctl |= MUSB_DEVCTL_SESSION;
+ 
+ 		conf |= TUSB_DEV_CONF_USB_HOST_MODE;
+@@ -547,24 +549,24 @@ static void tusb_source_power(struct musb *musb, int is_on)
+ 		/* If ID pin is grounded, we want to be a_idle */
+ 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
+ 		if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
+-			switch (musb->xceiv.state) {
++			switch (musb->xceiv->state) {
+ 			case OTG_STATE_A_WAIT_VRISE:
+ 			case OTG_STATE_A_WAIT_BCON:
+-				musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
++				musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+ 				break;
+ 			case OTG_STATE_A_WAIT_VFALL:
+-				musb->xceiv.state = OTG_STATE_A_IDLE;
++				musb->xceiv->state = OTG_STATE_A_IDLE;
+ 				break;
+ 			default:
+-				musb->xceiv.state = OTG_STATE_A_IDLE;
++				musb->xceiv->state = OTG_STATE_A_IDLE;
+ 			}
+ 			musb->is_active = 0;
+-			musb->xceiv.default_a = 1;
++			musb->xceiv->default_a = 1;
+ 			MUSB_HST_MODE(musb);
+ 		} else {
+ 			musb->is_active = 0;
+-			musb->xceiv.default_a = 0;
+-			musb->xceiv.state = OTG_STATE_B_IDLE;
++			musb->xceiv->default_a = 0;
++			musb->xceiv->state = OTG_STATE_B_IDLE;
+ 			MUSB_DEV_MODE(musb);
+ 		}
+ 
+@@ -675,7 +677,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
+ 		else
+ 			default_a = is_host_enabled(musb);
+ 		DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
+-		musb->xceiv.default_a = default_a;
++		musb->xceiv->default_a = default_a;
+ 		tusb_source_power(musb, default_a);
+ 
+ 		/* Don't allow idling immediately */
+@@ -687,7 +689,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
+ 	if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
+ 
+ 		/* B-dev state machine:  no vbus ~= disconnect */
+-		if ((is_otg_enabled(musb) && !musb->xceiv.default_a)
++		if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
+ 				|| !is_host_enabled(musb)) {
+ #ifdef CONFIG_USB_MUSB_HDRC_HCD
+ 			/* ? musb_root_disconnect(musb); */
+@@ -702,9 +704,9 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
+ 
+ 			if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
+ 				DBG(1, "Forcing disconnect (no interrupt)\n");
+-				if (musb->xceiv.state != OTG_STATE_B_IDLE) {
++				if (musb->xceiv->state != OTG_STATE_B_IDLE) {
+ 					/* INTR_DISCONNECT can hide... */
+-					musb->xceiv.state = OTG_STATE_B_IDLE;
++					musb->xceiv->state = OTG_STATE_B_IDLE;
+ 					musb->int_usb |= MUSB_INTR_DISCONNECT;
+ 				}
+ 				musb->is_active = 0;
+@@ -718,7 +720,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
+ 			DBG(2, "vbus change, %s, otg %03x\n",
+ 				otg_state_string(musb), otg_stat);
+ 
+-			switch (musb->xceiv.state) {
++			switch (musb->xceiv->state) {
+ 			case OTG_STATE_A_IDLE:
+ 				DBG(2, "Got SRP, turning on VBUS\n");
+ 				musb_set_vbus(musb, 1);
+@@ -766,7 +768,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
+ 
+ 		DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
+ 
+-		switch (musb->xceiv.state) {
++		switch (musb->xceiv->state) {
+ 		case OTG_STATE_A_WAIT_VRISE:
+ 			/* VBUS has probably been valid for a while now,
+ 			 * but may well have bounced out of range a bit
+@@ -778,7 +780,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
+ 					DBG(2, "devctl %02x\n", devctl);
+ 					break;
+ 				}
+-				musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
++				musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+ 				musb->is_active = 0;
+ 				idle_timeout = jiffies
+ 					+ msecs_to_jiffies(musb->a_wait_bcon);
+@@ -1094,9 +1096,14 @@ int __init musb_platform_init(struct musb *musb)
+ {
+ 	struct platform_device	*pdev;
+ 	struct resource		*mem;
+-	void __iomem		*sync;
++	void __iomem		*sync = NULL;
+ 	int			ret;
+ 
++	usb_nop_xceiv_register();
++	musb->xceiv = otg_get_transceiver();
++	if (!musb->xceiv)
++		return -ENODEV;
++
+ 	pdev = to_platform_device(musb->controller);
+ 
+ 	/* dma address for async dma */
+@@ -1107,14 +1114,16 @@ int __init musb_platform_init(struct musb *musb)
+ 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ 	if (!mem) {
+ 		pr_debug("no sync dma resource?\n");
+-		return -ENODEV;
++		ret = -ENODEV;
++		goto done;
+ 	}
+ 	musb->sync = mem->start;
+ 
+ 	sync = ioremap(mem->start, mem->end - mem->start + 1);
+ 	if (!sync) {
+ 		pr_debug("ioremap for sync failed\n");
+-		return -ENOMEM;
++		ret = -ENOMEM;
++		goto done;
+ 	}
+ 	musb->sync_va = sync;
+ 
+@@ -1127,28 +1136,37 @@ int __init musb_platform_init(struct musb *musb)
+ 	if (ret) {
+ 		printk(KERN_ERR "Could not start tusb6010 (%d)\n",
+ 				ret);
+-		return -ENODEV;
++		goto done;
+ 	}
+ 	musb->isr = tusb_interrupt;
+ 
+ 	if (is_host_enabled(musb))
+ 		musb->board_set_vbus = tusb_source_power;
+-	if (is_peripheral_enabled(musb))
+-		musb->xceiv.set_power = tusb_draw_power;
++	if (is_peripheral_enabled(musb)) {
++		musb->xceiv->set_power = tusb_draw_power;
++		the_musb = musb;
++	}
+ 
+ 	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
+ 
++done:
++	if (ret < 0) {
++		if (sync)
++			iounmap(sync);
++		usb_nop_xceiv_unregister();
++	}
+ 	return ret;
+ }
+ 
+ int musb_platform_exit(struct musb *musb)
+ {
+ 	del_timer_sync(&musb_idle_timer);
++	the_musb = NULL;
+ 
+ 	if (musb->board_set_power)
+ 		musb->board_set_power(0);
+ 
+ 	iounmap(musb->sync_va);
+-
++	usb_nop_xceiv_unregister();
+ 	return 0;
+ }
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0027-musb-otg-timer-cleanup.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0027-musb-otg-timer-cleanup.patch
new file mode 100644
index 0000000000..f41b766cfe
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0027-musb-otg-timer-cleanup.patch
@@ -0,0 +1,198 @@
+From b4b8c1e7604784b9877f07400ff2a718118ef05c Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Tue, 31 Mar 2009 12:32:12 -0700
+Subject: [PATCH] musb: otg timer cleanup
+
+Minor cleanup of OTG timer handling:
+    * unify decls for OTG time constants, in the core header
+    * set up and use that timer in a more normal way
+    * move to the driver struct, so it's usable outside core
+
+And tighten use and setup of T(a_wait_bcon) so that if it's used,
+it's always valid.  (If that timer expires, the A-device will
+stop powering VBUS.  For non-OTG systems, that will be a surprise.)
+No behavioral changes, other than more consistency when applying
+that core HNP timeout.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_core.c |   41 ++++++++++++++++++++++-------------------
+ drivers/usb/musb/musb_core.h |   14 +++++++++++---
+ drivers/usb/musb/omap2430.c  |    2 --
+ 3 files changed, 33 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index ac150af..05c5dd3 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -112,6 +112,7 @@
+ #include "davinci.h"
+ #endif
+ 
++#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
+ 
+ 
+ unsigned musb_debug;
+@@ -288,12 +289,6 @@ const char *otg_state_string(struct musb *musb)
+ #ifdef	CONFIG_USB_MUSB_OTG
+ 
+ /*
+- * See also USB_OTG_1-3.pdf 6.6.5 Timers
+- * REVISIT: Are the other timers done in the hardware?
+- */
+-#define TB_ASE0_BRST		100	/* Min 3.125 ms */
+-
+-/*
+  * Handles OTG hnp timeouts, such as b_ase0_brst
+  */
+ void musb_otg_timer_func(unsigned long data)
+@@ -320,10 +315,8 @@ void musb_otg_timer_func(unsigned long data)
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+ }
+ 
+-static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
+-
+ /*
+- * Stops the B-device HNP state. Caller must take care of locking.
++ * Stops the HNP transition. Caller must take care of locking.
+  */
+ void musb_hnp_stop(struct musb *musb)
+ {
+@@ -661,11 +654,12 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 				musb_g_reset(musb);
+ 				/* FALLTHROUGH */
+ 			case OTG_STATE_A_WAIT_BCON:	/* OPT TD.4.7-900ms */
+-				DBG(1, "HNP: Setting timer as %s\n",
+-						otg_state_string(musb));
+-				musb_otg_timer.data = (unsigned long)musb;
+-				mod_timer(&musb_otg_timer, jiffies
+-					+ msecs_to_jiffies(100));
++				/* never use invalid T(a_wait_bcon) */
++				DBG(1, "HNP: in %s, %d msec timeout\n",
++						otg_state_string(musb),
++						TA_WAIT_BCON(musb));
++				mod_timer(&musb->otg_timer, jiffies
++					+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
+ 				break;
+ 			case OTG_STATE_A_PERIPHERAL:
+ 				musb_hnp_stop(musb);
+@@ -822,9 +816,9 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
+ #ifdef	CONFIG_USB_MUSB_OTG
+ 				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
+ 				DBG(1, "HNP: Setting timer for b_ase0_brst\n");
+-				musb_otg_timer.data = (unsigned long)musb;
+-				mod_timer(&musb_otg_timer, jiffies
+-					+ msecs_to_jiffies(TB_ASE0_BRST));
++				mod_timer(&musb->otg_timer, jiffies
++					+ msecs_to_jiffies(
++							OTG_TIME_B_ASE0_BRST));
+ #endif
+ 			}
+ 			break;
+@@ -1680,7 +1674,8 @@ musb_vbus_store(struct device *dev, struct device_attribute *attr,
+ 	}
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+-	musb->a_wait_bcon = val;
++	/* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
++	musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
+ 	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
+ 		musb->is_active = 0;
+ 	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
+@@ -1699,10 +1694,13 @@ musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
+ 
+ 	spin_lock_irqsave(&musb->lock, flags);
+ 	val = musb->a_wait_bcon;
++	/* FIXME get_vbus_status() is normally #defined as false...
++	 * and is effectively TUSB-specific.
++	 */
+ 	vbus = musb_platform_get_vbus_status(musb);
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+ 
+-	return sprintf(buf, "Vbus %s, timeout %lu\n",
++	return sprintf(buf, "Vbus %s, timeout %lu msec\n",
+ 			vbus ? "on" : "off", val);
+ }
+ static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
+@@ -1775,6 +1773,7 @@ allocate_instance(struct device *dev,
+ 	hcd->uses_new_polling = 1;
+ 
+ 	musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
++	musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
+ #else
+ 	musb = kzalloc(sizeof *musb, GFP_KERNEL);
+ 	if (!musb)
+@@ -1969,6 +1968,10 @@ bad_config:
+ 	if (status < 0)
+ 		goto fail2;
+ 
++#ifdef CONFIG_USB_OTG
++	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
++#endif
++
+ 	/* Init IRQ workqueue before request_irq */
+ 	INIT_WORK(&musb->irq_work, musb_irq_work);
+ 
+diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
+index c3ee348..cf3ccb0 100644
+--- a/drivers/usb/musb/musb_core.h
++++ b/drivers/usb/musb/musb_core.h
+@@ -40,6 +40,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/smp_lock.h>
+ #include <linux/errno.h>
++#include <linux/timer.h>
+ #include <linux/clk.h>
+ #include <linux/device.h>
+ #include <linux/usb/ch9.h>
+@@ -180,10 +181,15 @@ enum musb_g_ep0_state {
+ 	MUSB_EP0_STAGE_ACKWAIT,		/* after zlp, before statusin */
+ } __attribute__ ((packed));
+ 
+-/* OTG protocol constants */
++/*
++ * OTG protocol constants.  See USB OTG 1.3 spec,
++ * sections 5.5 "Device Timings" and 6.6.5 "Timers".
++ */
+ #define OTG_TIME_A_WAIT_VRISE	100		/* msec (max) */
+-#define OTG_TIME_A_WAIT_BCON	0		/* 0=infinite; min 1000 msec */
+-#define OTG_TIME_A_IDLE_BDIS	200		/* msec (min) */
++#define OTG_TIME_A_WAIT_BCON	1100		/* min 1 second */
++#define OTG_TIME_A_AIDL_BDIS	200		/* min 200 msec */
++#define OTG_TIME_B_ASE0_BRST	100		/* min 3.125 ms */
++
+ 
+ /*************************** REGISTER ACCESS ********************************/
+ 
+@@ -332,6 +338,8 @@ struct musb {
+ 	struct list_head	control;	/* of musb_qh */
+ 	struct list_head	in_bulk;	/* of musb_qh */
+ 	struct list_head	out_bulk;	/* of musb_qh */
++
++	struct timer_list	otg_timer;
+ #endif
+ 
+ 	/* called with IRQs blocked; ON/nonzero implies starting a session,
+diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
+index 5f67b03..3fbc807 100644
+--- a/drivers/usb/musb/omap2430.c
++++ b/drivers/usb/musb/omap2430.c
+@@ -45,7 +45,6 @@
+ #define	get_cpu_rev()	2
+ #endif
+ 
+-#define MUSB_TIMEOUT_A_WAIT_BCON	1100
+ 
+ static struct timer_list musb_idle_timer;
+ 
+@@ -246,7 +245,6 @@ int __init musb_platform_init(struct musb *musb)
+ 
+ 	if (is_host_enabled(musb))
+ 		musb->board_set_vbus = omap_set_vbus;
+-	musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
+ 
+ 	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
+ 
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0028-musb-make-initial-HNP-roleswitch-work-v2.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0028-musb-make-initial-HNP-roleswitch-work-v2.patch
new file mode 100644
index 0000000000..6269016223
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0028-musb-make-initial-HNP-roleswitch-work-v2.patch
@@ -0,0 +1,133 @@
+From a637c5056ef52fbb7c41eb7537a9ec3d150231ad Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Thu, 2 Apr 2009 10:16:11 -0700
+Subject: [PATCH] musb: make initial HNP roleswitch work (v2)
+
+Minor HNP bugfixes, so the initial role switch works:
+
+ - A-Device:
+     * disconnect-during-suspend enters A_PERIPHERAL state
+     * kill OTG timer after reset as A_PERIPHERAL ...
+     * ... and also pass that reset to the gadget
+     * once HNP succeeds, clear the "ignore_disconnect" flag
+     * from A_PERIPHERAL, disconnect transitions to A_WAIT_BCON
+
+ - B-Device:
+     * kill OTG timer on entry to B_HOST state (HNP succeeded)
+     * once HNP succeeds, clear "ignore_disconnect" flag
+     * kick the root hub only _after_ the state is adjusted
+
+Other state transitions are left alone.  Notably, exit paths from
+the "roles have switched" state ... A_PERIPHERAL handling of that
+stays seriously broken.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_core.c    |   27 ++++++++++++++++-----------
+ drivers/usb/musb/musb_gadget.c  |    2 +-
+ drivers/usb/musb/musb_virthub.c |   11 ++++++++++-
+ 3 files changed, 27 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index 05c5dd3..9dc995a 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -587,28 +587,23 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 		if (devctl & MUSB_DEVCTL_LSDEV)
+ 			musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
+ 
+-		if (hcd->status_urb)
+-			usb_hcd_poll_rh_status(hcd);
+-		else
+-			usb_hcd_resume_root_hub(hcd);
+-
+-		MUSB_HST_MODE(musb);
+-
+ 		/* indicate new connection to OTG machine */
+ 		switch (musb->xceiv->state) {
+ 		case OTG_STATE_B_PERIPHERAL:
+ 			if (int_usb & MUSB_INTR_SUSPEND) {
+ 				DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
+-				musb->xceiv->state = OTG_STATE_B_HOST;
+-				hcd->self.is_b_host = 1;
+ 				int_usb &= ~MUSB_INTR_SUSPEND;
++				goto b_host;
+ 			} else
+ 				DBG(1, "CONNECT as b_peripheral???\n");
+ 			break;
+ 		case OTG_STATE_B_WAIT_ACON:
+-			DBG(1, "HNP: Waiting to switch to b_host state\n");
++			DBG(1, "HNP: CONNECT, now b_host\n");
++b_host:
+ 			musb->xceiv->state = OTG_STATE_B_HOST;
+ 			hcd->self.is_b_host = 1;
++			musb->ignore_disconnect = 0;
++			del_timer(&musb->otg_timer);
+ 			break;
+ 		default:
+ 			if ((devctl & MUSB_DEVCTL_VBUS)
+@@ -618,6 +613,14 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 			}
+ 			break;
+ 		}
++
++		/* poke the root hub */
++		MUSB_HST_MODE(musb);
++		if (hcd->status_urb)
++			usb_hcd_poll_rh_status(hcd);
++		else
++			usb_hcd_resume_root_hub(hcd);
++
+ 		DBG(1, "CONNECT (%s) devctl %02x\n",
+ 				otg_state_string(musb), devctl);
+ 	}
+@@ -662,7 +665,9 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
+ 					+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
+ 				break;
+ 			case OTG_STATE_A_PERIPHERAL:
+-				musb_hnp_stop(musb);
++				musb->ignore_disconnect = 0;
++				del_timer(&musb->otg_timer);
++				musb_g_reset(musb);
+ 				break;
+ 			case OTG_STATE_B_WAIT_ACON:
+ 				DBG(1, "HNP: RESET (%s), to b_peripheral\n",
+diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
+index 2fbfba5..7dd3d59 100644
+--- a/drivers/usb/musb/musb_gadget.c
++++ b/drivers/usb/musb/musb_gadget.c
+@@ -1964,7 +1964,7 @@ void musb_g_disconnect(struct musb *musb)
+ 		musb->xceiv->state = OTG_STATE_A_IDLE;
+ 		break;
+ 	case OTG_STATE_A_PERIPHERAL:
+-		musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
++		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+ 		break;
+ 	case OTG_STATE_B_WAIT_ACON:
+ 	case OTG_STATE_B_HOST:
+diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
+index 7e7900f..14f7cf3 100644
+--- a/drivers/usb/musb/musb_virthub.c
++++ b/drivers/usb/musb/musb_virthub.c
+@@ -187,8 +187,17 @@ void musb_root_disconnect(struct musb *musb)
+ 	musb->is_active = 0;
+ 
+ 	switch (musb->xceiv->state) {
+-	case OTG_STATE_A_HOST:
+ 	case OTG_STATE_A_SUSPEND:
++#ifdef	CONFIG_USB_MUSB_OTG
++		if (is_otg_enabled(musb)
++				&& musb->xceiv->host->b_hnp_enable) {
++			musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
++			musb->g.is_a_peripheral = 1;
++			break;
++		}
++#endif
++		/* FALLTHROUGH */
++	case OTG_STATE_A_HOST:
+ 		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+ 		musb->is_active = 0;
+ 		break;
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0029-musb-support-disconnect-after-HNP-roleswitch.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0029-musb-support-disconnect-after-HNP-roleswitch.patch
new file mode 100644
index 0000000000..fc34fb983e
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/musb/0029-musb-support-disconnect-after-HNP-roleswitch.patch
@@ -0,0 +1,145 @@
+From 4288b7df4ae6629a4fb14aca2c489da01d4d19c3 Mon Sep 17 00:00:00 2001
+From: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+Date: Tue, 31 Mar 2009 12:35:09 -0700
+Subject: [PATCH] musb: support disconnect after HNP roleswitch
+
+Adjust HNP state machines in MUSB driver so that they handle the
+case where the cable is disconnected.  The A-side machine was
+very wrong (unrecoverable); the B-Side was much less so.
+
+ - A_PERIPHERAL ... as usual, the non-observability of the ID
+   pin through Mentor's registers makes trouble.  We can't go
+   directly to A_WAIT_VFALL to end the session and start the
+   disconnect processing.  We can however sense link suspending,
+   go to A_WAIT_BCON, and from there use OTG timeouts to finally
+   trigger that A_WAIT_VFALL transition.  (Hoping that nobody
+   reconnects quickly to that port and notices the wrong state.)
+
+ - B_HOST ... actually clear the Host Request (HR) bit as the
+   messages say, disconnect the peripheral from the root hub,
+   and don't detour through a suspend state.  (In some cases
+   this would eventually have cleaned up.)
+
+Also adjust the A_SUSPEND transition to respect the A_AIDL_BDIS
+timeout, so if HNP doesn't trigger quickly enough the A_WAIT_VFALL
+transition happens as it should.
+
+Signed-off-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
+---
+ drivers/usb/musb/musb_core.c    |   41 +++++++++++++++++++++++++++-----------
+ drivers/usb/musb/musb_gadget.c  |    2 +
+ drivers/usb/musb/musb_virthub.c |    4 +++
+ 3 files changed, 35 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index 9dc995a..5770ccb 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -304,9 +304,11 @@ void musb_otg_timer_func(unsigned long data)
+ 		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ 		musb->is_active = 0;
+ 		break;
++	case OTG_STATE_A_SUSPEND:
+ 	case OTG_STATE_A_WAIT_BCON:
+-		DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
+-		musb_hnp_stop(musb);
++		DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
++		musb_set_vbus(musb, 0);
++		musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+ 		break;
+ 	default:
+ 		DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
+@@ -324,15 +326,12 @@ void musb_hnp_stop(struct musb *musb)
+ 	void __iomem	*mbase = musb->mregs;
+ 	u8	reg;
+ 
++	DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
++
+ 	switch (musb->xceiv->state) {
+ 	case OTG_STATE_A_PERIPHERAL:
+-	case OTG_STATE_A_WAIT_VFALL:
+-	case OTG_STATE_A_WAIT_BCON:
+-		DBG(1, "HNP: Switching back to A-host\n");
+ 		musb_g_disconnect(musb);
+-		musb->xceiv->state = OTG_STATE_A_IDLE;
+-		MUSB_HST_MODE(musb);
+-		musb->is_active = 0;
++		DBG(1, "HNP: back to %s\n", otg_state_string(musb));
+ 		break;
+ 	case OTG_STATE_B_HOST:
+ 		DBG(1, "HNP: Disabling HR\n");
+@@ -775,7 +774,16 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
+ #endif	/* HOST */
+ #ifdef CONFIG_USB_MUSB_OTG
+ 		case OTG_STATE_B_HOST:
+-			musb_hnp_stop(musb);
++			/* REVISIT this behaves for "real disconnect"
++			 * cases; make sure the other transitions from
++			 * from B_HOST act right too.  The B_HOST code
++			 * in hnp_stop() is currently not used...
++			 */
++			musb_root_disconnect(musb);
++			musb_to_hcd(musb)->self.is_b_host = 0;
++			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++			MUSB_DEV_MODE(musb);
++			musb_g_disconnect(musb);
+ 			break;
+ 		case OTG_STATE_A_PERIPHERAL:
+ 			musb_hnp_stop(musb);
+@@ -807,10 +815,19 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
+ 		switch (musb->xceiv->state) {
+ #ifdef	CONFIG_USB_MUSB_OTG
+ 		case OTG_STATE_A_PERIPHERAL:
+-			/*
+-			 * We cannot stop HNP here, devctl BDEVICE might be
+-			 * still set.
++			/* We also come here if the cable is removed, since
++			 * this silicon doesn't report ID-no-longer-grounded.
++			 *
++			 * We depend on T(a_wait_bcon) to shut us down, and
++			 * hope users don't do anything dicey during this
++			 * undesired detour through A_WAIT_BCON.
+ 			 */
++			musb_hnp_stop(musb);
++			usb_hcd_resume_root_hub(musb_to_hcd(musb));
++			musb_root_disconnect(musb);
++			musb_platform_try_idle(musb, jiffies
++					+ msecs_to_jiffies(musb->a_wait_bcon
++						? : OTG_TIME_A_WAIT_BCON));
+ 			break;
+ #endif
+ 		case OTG_STATE_B_PERIPHERAL:
+diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
+index 7dd3d59..8b3c4e2 100644
+--- a/drivers/usb/musb/musb_gadget.c
++++ b/drivers/usb/musb/musb_gadget.c
+@@ -1962,9 +1962,11 @@ void musb_g_disconnect(struct musb *musb)
+ 		DBG(2, "Unhandled disconnect %s, setting a_idle\n",
+ 			otg_state_string(musb));
+ 		musb->xceiv->state = OTG_STATE_A_IDLE;
++		MUSB_HST_MODE(musb);
+ 		break;
+ 	case OTG_STATE_A_PERIPHERAL:
+ 		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
++		MUSB_HST_MODE(musb);
+ 		break;
+ 	case OTG_STATE_B_WAIT_ACON:
+ 	case OTG_STATE_B_HOST:
+diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
+index 14f7cf3..e8ef925 100644
+--- a/drivers/usb/musb/musb_virthub.c
++++ b/drivers/usb/musb/musb_virthub.c
+@@ -83,6 +83,10 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
+ 			musb->xceiv->state = OTG_STATE_A_SUSPEND;
+ 			musb->is_active = is_otg_enabled(musb)
+ 					&& musb->xceiv->host->b_hnp_enable;
++			if (musb->is_active)
++				mod_timer(&musb->otg_timer, jiffies
++					+ msecs_to_jiffies(
++						OTG_TIME_A_AIDL_BDIS));
+ 			musb_platform_try_idle(musb, 0);
+ 			break;
+ #ifdef	CONFIG_USB_MUSB_OTG
+-- 
+1.6.0.4
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/no-cortex-deadlock.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/no-cortex-deadlock.patch
new file mode 100644
index 0000000000..78547c8969
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/no-cortex-deadlock.patch
@@ -0,0 +1,77 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Sat, 16 Aug 2008 23:03:06 +0000 (+0100)
+Subject: ARM: Workaround for erratum 451034
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=b84fa87873ffb68ad23930cf6cddeea8bec43ede
+
+ARM: Workaround for erratum 451034
+
+On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer
+store in the store buffer, can cause a processor deadlock under
+certain conditions.
+
+Executing a DMB instruction before saving NEON/VFP registers and before
+return to userspace makes it safe to run code which includes similar
+counter-measures.  Userspace code can still trigger the deadlock, so
+a different workaround is required to safely run untrusted code.
+
+See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index aa475d9..41d536e 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1117,6 +1117,22 @@ config NEON
+ 	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
+ 	  Extension.
+ 
++config ARM_ERRATUM_451034
++	bool "Enable workaround for ARM erratum 451034"
++	depends on VFPv3
++	help
++	  On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer
++	  store in the store buffer, can cause a processor deadlock under
++	  certain conditions.
++
++	  See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details.
++
++	  Say Y to include a partial workaround.
++
++	  WARNING: Even with this option enabled, userspace code can trigger
++	  the deadlock.	 To safely run untrusted code, a different fix is
++	  required.
++
+ endmenu
+ 
+ menu "Userspace binary formats"
+diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
+index 422f3cc..934798b 100644
+--- a/arch/arm/include/asm/vfpmacros.h
++++ b/arch/arm/include/asm/vfpmacros.h
+@@ -32,6 +32,9 @@
+ 
+ 	@ write all the working registers out of the VFP
+ 	.macro	VFPFSTMIA, base, tmp
++#ifdef CONFIG_ARM_ERRATUM_451034
++	dmb
++#endif
+ #if __LINUX_ARM_ARCH__ < 6
+ 	STC	p11, cr0, [\base],#33*4		    @ FSTMIAX \base!, {d0-d15}
+ #else
+diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
+index 060d7e2..9799a35 100644
+--- a/arch/arm/kernel/entry-common.S
++++ b/arch/arm/kernel/entry-common.S
+@@ -69,6 +69,10 @@ no_work_pending:
+ 	/* perform architecture specific actions before user return */
+ 	arch_ret_to_user r1, lr
+ 
++#ifdef CONFIG_ARM_ERRATUM_451034
++	dmb
++#endif
++
+ 	@ slow_restore_user_regs
+ 	ldr	r1, [sp, #S_PSR]		@ get calling cpsr
+ 	ldr	lr, [sp, #S_PC]!		@ get pc
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/no-empty-flash-warnings.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/no-empty-flash-warnings.patch
new file mode 100644
index 0000000000..ab344b0449
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/no-empty-flash-warnings.patch
@@ -0,0 +1,15 @@
+diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c
+index 1d437de..33b3feb 100644
+--- a/fs/jffs2/scan.c
++++ b/fs/jffs2/scan.c
+@@ -647,8 +647,8 @@ scan_more:
+ 			inbuf_ofs = ofs - buf_ofs;
+ 			while (inbuf_ofs < scan_end) {
+ 				if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) {
+-					printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
+-					       empty_start, ofs);
++//					printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
++//					       empty_start, ofs);
+ 					if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start)))
+ 						return err;
+ 					goto scan_more;
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/no-harry-potter.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/no-harry-potter.diff
new file mode 100644
index 0000000000..2bb20ab9c0
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/no-harry-potter.diff
@@ -0,0 +1,11 @@
+--- /tmp/Makefile	2008-04-24 14:36:20.509598016 +0200
++++ git/arch/arm/Makefile	2008-04-24 14:36:31.949546584 +0200
+@@ -47,7 +47,7 @@
+ # Note that GCC does not numerically define an architecture version
+ # macro, but instead defines a whole series of macros which makes
+ # testing for a specific architecture or later rather impossible.
+-arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
++arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+ arch-$(CONFIG_CPU_32v6)		:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+ # Only override the compiler option if ARMv6. The ARMv6K extensions are
+ # always available in ARMv7
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap-2430-lcd.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/omap-2430-lcd.patch
new file mode 100644
index 0000000000..8f8a687c06
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap-2430-lcd.patch
@@ -0,0 +1,11 @@
+--- git/drivers/video/omap/lcd_2430sdp.c.orig	2007-08-13 14:35:17.000000000 -0700
++++ git/drivers/video/omap/lcd_2430sdp.c	2007-08-13 14:35:55.000000000 -0700
+@@ -32,7 +32,7 @@
+ #define LCD_PANEL_BACKLIGHT_GPIO	91
+ #define LCD_PANEL_ENABLE_GPIO		154
+ #define LCD_PIXCLOCK_MAX		5400 /* freq 5.4 MHz */
+-#define PM_RECEIVER             TWL4030_MODULE_PM_RECIEVER
++#define PM_RECEIVER             TWL4030_MODULE_PM_RECEIVER
+ #define ENABLE_VAUX2_DEDICATED  0x09
+ #define ENABLE_VAUX2_DEV_GRP    0x20
+ 
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap1710h3/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/omap1710h3/defconfig
new file mode 100644
index 0000000000..21f7c54e4e
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap1710h3/defconfig
@@ -0,0 +1,1224 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23-rc2-omap1
+# Tue Aug 21 23:10:57 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+CONFIG_ARCH_OMAP1=y
+# CONFIG_ARCH_OMAP2 is not set
+# CONFIG_ARCH_OMAP3 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_RESET_CLOCKS is not set
+# CONFIG_OMAP_BOOT_TAG is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_MPU_TIMER=y
+# CONFIG_OMAP_32K_TIMER is not set
+# CONFIG_OMAP_DM_TIMER is not set
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_OMAP_DSP is not set
+
+#
+# OMAP Core Type
+#
+# CONFIG_ARCH_OMAP730 is not set
+# CONFIG_ARCH_OMAP15XX is not set
+CONFIG_ARCH_OMAP16XX=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_INNOVATOR is not set
+# CONFIG_MACH_OMAP_H2 is not set
+CONFIG_MACH_OMAP_H3=y
+# CONFIG_MACH_OMAP_OSK is not set
+# CONFIG_MACH_NOKIA770 is not set
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP CPU Speed
+#
+# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
+# CONFIG_OMAP_ARM_216MHZ is not set
+# CONFIG_OMAP_ARM_192MHZ is not set
+CONFIG_OMAP_ARM_168MHZ=y
+# CONFIG_OMAP_ARM_120MHZ is not set
+# CONFIG_OMAP_ARM_60MHZ is not set
+# CONFIG_OMAP_ARM_30MHZ is not set
+# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x10C08000
+CONFIG_ZBOOT_ROM_BSS=0x10200000
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 initrd=0x10A00000,8M root=/dev/ram0 rw ip=dhcp devfs=mount"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_IRDA=y
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+
+#
+# Old SIR device drivers
+#
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Old Serial dongle support
+#
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_OMAP_IR is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=y
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_OMAP=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_OMAP_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_OMAP=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+CONFIG_ISP1301_OMAP=m
+CONFIG_TPS65010=y
+# CONFIG_SENSORS_TLV320AIC23 is not set
+CONFIG_GPIOEXPANDER_OMAP=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_OMAP_UWIRE=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC2101 is not set
+# CONFIG_SPI_TSC2102 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_NEW_LEDS is not set
+
+#
+# Multimedia devices
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_TUNER_3036 is not set
+# CONFIG_TUNER_TEA5761 is not set
+# CONFIG_VIDEO_OMAP_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_VIDEO_OVCAMCHIP is not set
+# CONFIG_USB_W9968CF is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_RADIO_TEA5761 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_FB_OMAP_DMA_TUNE is not set
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+# CONFIG_SND is not set
+
+#
+# Open Sound System
+#
+CONFIG_SOUND_PRIME=y
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_OMAP=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_OMAP=y
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap2420h4/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/omap2420h4/defconfig
new file mode 100644
index 0000000000..c1133eef9a
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap2420h4/defconfig
@@ -0,0 +1,1119 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23-rc2-omap1
+# Tue Aug 21 22:58:34 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2=y
+# CONFIG_ARCH_OMAP3 is not set
+
+#
+# OMAP Feature Selections
+#
+CONFIG_OMAP_DEBUG_DEVICES=y
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+# CONFIG_OMAP_BOOT_REASON is not set
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_MPU_TIMER=y
+# CONFIG_OMAP_32K_TIMER is not set
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_OMAP_DSP is not set
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP Core Type
+#
+CONFIG_ARCH_OMAP24XX=y
+CONFIG_ARCH_OMAP2420=y
+# CONFIG_ARCH_OMAP2430 is not set
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_NOKIA_N800 is not set
+CONFIG_MACH_OMAP_H4=y
+# CONFIG_MACH_OMAP_H4_TUSB is not set
+# CONFIG_MACH_OMAP_H4_OTG is not set
+# CONFIG_MACH_OMAP2_H4_USB1 is not set
+# CONFIG_MACH_OMAP_APOLLON is not set
+# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
+# CONFIG_MACH_OMAP_2430SDP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_IRDA=y
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=y
+CONFIG_IRCOMM=y
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+
+#
+# Old SIR device drivers
+#
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Old Serial dongle support
+#
+
+#
+# FIR device drivers
+#
+CONFIG_OMAP_IR=y
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_OMAP=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_OMAP=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_TLV320AIC23 is not set
+CONFIG_GPIOEXPANDER_OMAP=y
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+CONFIG_MENELAUS=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_NEW_LEDS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_OMAP=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap2430sdp/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/omap2430sdp/defconfig
new file mode 100644
index 0000000000..f3897e48a3
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap2430sdp/defconfig
@@ -0,0 +1,1303 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23-rc2-omap1
+# Sun Aug 12 17:38:46 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2=y
+# CONFIG_ARCH_OMAP3 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+# CONFIG_OMAP_BOOT_REASON is not set
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+# CONFIG_OMAP_MUX_WARNINGS is not set
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_MPU_TIMER=y
+# CONFIG_OMAP_32K_TIMER is not set
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_OMAP_DSP is not set
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP Core Type
+#
+CONFIG_ARCH_OMAP24XX=y
+# CONFIG_ARCH_OMAP2420 is not set
+CONFIG_ARCH_OMAP2430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_NOKIA_N800 is not set
+# CONFIG_MACH_OMAP_H4 is not set
+# CONFIG_MACH_OMAP_APOLLON is not set
+# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
+CONFIG_MACH_OMAP_2430SDP=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_OMAP is not set
+CONFIG_KEYBOARD_TWL4030=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_TSC2102 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_OMAP=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_TLV320AIC23 is not set
+# CONFIG_GPIOEXPANDER_OMAP is not set
+# CONFIG_MENELAUS is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_GPIO=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_OMAP24XX is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC2101 is not set
+# CONFIG_SPI_TSC2102 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_NEW_LEDS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_PERSIST is not set
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 243x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_USB_INVENTRA_FIFO is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+CONFIG_USB_INVENTRA_HCD_LOGGING=1
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ZERO_HNPTEST is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_OMAP=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap3-pandora/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/omap3-pandora/defconfig
new file mode 100644
index 0000000000..8ac420cc31
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap3-pandora/defconfig
@@ -0,0 +1,2186 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc7-omap1
+# Fri Dec 12 19:50:40 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_DEBUG=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+CONFIG_OMAP2_DSS_VENC=y
+# CONFIG_OMAP2_DSS_SDI is not set
+CONFIG_OMAP2_DSS_DSI=y
+# CONFIG_OMAP2_DSS_USE_DSI_PLL is not set
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OVERO is not set
+CONFIG_MACH_OMAP3_PANDORA=y
+CONFIG_OMAP_TICK_GPTIMER=12
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=n
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+CONFIG_ARM_ERRATUM_451034=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=y
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=y
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+CONFIG_IEEE80211_CRYPT_CCMP=y
+CONFIG_IEEE80211_CRYPT_TKIP=y
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_93CX6=m
+# CONFIG_ICS932S401 is not set
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+CONFIG_REALTEK_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_TWL4030=y
+# CONFIG_KEYBOARD_LM8323 is not set
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_USB=y
+CONFIG_TWL4030_PWRBUTTON=y
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_LP5521 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX2341X=m
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+# CONFIG_VIDEO_EM28XX is not set
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_USBVIDEO=m
+CONFIG_USB_VICAM=m
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_KONICAWC=m
+CONFIG_USB_QUICKCAM_MESSENGER=m
+# CONFIG_USB_ET61X251 is not set
+CONFIG_VIDEO_OVCAMCHIP=m
+CONFIG_USB_W9968CF=m
+CONFIG_USB_OV511=m
+CONFIG_USB_SE401=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_STV680=m
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_ZR364XX=m
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+# CONFIG_DVB_USB_DW2102 is not set
+# CONFIG_DVB_USB_CINERGY_T2 is not set
+# CONFIG_DVB_USB_ANYSEE is not set
+# CONFIG_DVB_USB_DTV5100 is not set
+# CONFIG_DVB_USB_AF9015 is not set
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+# CONFIG_DVB_SIANO_SMS1XXX is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_SI21XX is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+# CONFIG_DVB_DRX397XD is not set
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+# CONFIG_DVB_LGS8GL5 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# CONFIG_DVB_AF9013 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=14
+CONFIG_FB_OMAP2=y
+# CONFIG_FB_OMAP2_DEBUG is not set
+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
+CONFIG_FB_OMAP2_NUM_FBS=3
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_DVI=y
+# CONFIG_PANEL_DVI_640X480 is not set
+# CONFIG_PANEL_DVI_800X600 is not set
+CONFIG_PANEL_DVI_1024X768=y
+# CONFIG_PANEL_DVI_1280X1024 is not set
+CONFIG_PANEL_SHARP_LS037V7DW01=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+CONFIG_LCD_ILI9320=y
+# CONFIG_LCD_TDO24M is not set
+CONFIG_LCD_VGG2432A4=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+# CONFIG_USB_BERRY_CHARGE is not set
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SPI=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+# CONFIG_LEDS_OMAP is not set
+# CONFIG_LEDS_OMAP_PWM is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACER_MAX_TRACE=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+CONFIG_PREEMPT_TRACER=y
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/defconfig
new file mode 100644
index 0000000000..05f1dddaad
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/defconfig
@@ -0,0 +1,2126 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-omap1
+# Thu Jul 16 16:20:40 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_IOMMU is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_TICK_GPTIMER=12
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+CONFIG_MACH_OMAP3EVM=y
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+# CONFIG_ALIGNMENT_TRAP is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+CONFIG_ARM_ERRATUM_451034=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=y
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+CONFIG_EEPROM_93CX6=m
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_FIXED_PHY=y
+CONFIG_MDIO_BITBANG=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=y
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_TWL4030=y
+# CONFIG_KEYBOARD_LM8323 is not set
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX2341X=m
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_VIDEO_OMAP3 is not set
+# CONFIG_VIDEO_OMAP34XX_ISP_RESIZER is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+# CONFIG_VIDEO_EM28XX is not set
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_USBVIDEO=m
+CONFIG_USB_VICAM=m
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_KONICAWC=m
+CONFIG_USB_QUICKCAM_MESSENGER=m
+# CONFIG_USB_ET61X251 is not set
+CONFIG_VIDEO_OVCAMCHIP=m
+CONFIG_USB_W9968CF=m
+CONFIG_USB_OV511=m
+CONFIG_USB_SE401=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_STV680=m
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_ZR364XX=m
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+# CONFIG_DVB_USB_DW2102 is not set
+# CONFIG_DVB_USB_CINERGY_T2 is not set
+# CONFIG_DVB_USB_ANYSEE is not set
+# CONFIG_DVB_USB_DTV5100 is not set
+# CONFIG_DVB_USB_AF9015 is not set
+# CONFIG_DVB_SIANO_SMS1XXX is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# Multistandard (satellite) frontends
+#
+# CONFIG_DVB_STB0899 is not set
+# CONFIG_DVB_STB6100 is not set
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+# CONFIG_DVB_TDA8261 is not set
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+# CONFIG_DVB_TUNER_CX24113 is not set
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_SI21XX is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+# CONFIG_DVB_DRX397XD is not set
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+# CONFIG_DVB_LGDT3304 is not set
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_S921 is not set
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+# CONFIG_DVB_LGS8GL5 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# CONFIG_DVB_AF9013 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_VRAM_SIZE=4
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+CONFIG_OMAP2_DSS_VENC=y
+# CONFIG_OMAP2_DSS_SDI is not set
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_USE_DSI_PLL=y
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_GENERIC=y
+# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set
+CONFIG_PANEL_SHARP_LS037V7DW01=y
+# CONFIG_PANEL_N800 is not set
+# CONFIG_CTRL_BLIZZARD is not set
+CONFIG_FB_OMAP2=y
+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
+CONFIG_FB_OMAP2_NUM_FBS=3
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+CONFIG_LCD_ILI9320=y
+# CONFIG_LCD_TDO24M is not set
+CONFIG_LCD_VGG2432A4=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_NTRIG is not set
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+# CONFIG_USB_SERIAL_OPTICON is not set
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+# CONFIG_USB_BERRY_CHARGE is not set
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_GPIO_VBUS=y
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SPI=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+# CONFIG_LEDS_OMAP is not set
+# CONFIG_LEDS_OMAP_PWM is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=m
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACER_MAX_TRACE=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+CONFIG_PREEMPT_TRACER=y
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/omap3evm-dss2.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/omap3evm-dss2.diff
new file mode 100644
index 0000000000..60832e72ca
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/omap3evm-dss2.diff
@@ -0,0 +1,443 @@
+From: hvaibhav@ti.com
+To: linux-fbdev-devel@lists.sourceforge.net, linux-omap@vger.kernel.org
+Cc: Vaibhav Hiremath <hvaibhav@ti.com>
+Subject: [REVIEW PATCH] Added OMAP3EVM support on Tomis FBDEV/DSS Patches
+Date: 	Fri, 14 Nov 2008 12:02:32 +0530
+
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+
+Tested LCD, TV, DVI (480P) out on OMAP3EVM board.
+
+Please make sure that you change the option
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=7  and apply the
+Mans Rullgard clock patches to support set_rate and round_rate API.
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c |  224 ++++++++++++++++++++++++++++++++--
+ drivers/video/omap2/Kconfig          |    5 +
+ drivers/video/omap2/Makefile         |    1 +
+ drivers/video/omap2/panel-omap3evm.c |  110 +++++++++++++++++
+ 5 files changed, 341 insertions(+), 53 deletions(-)
+ create mode 100644 drivers/video/omap2/panel-omap3evm.c
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 42ab826..e244fa7 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -37,6 +37,8 @@
+ #include <mach/usb-ehci.h>
+ #include <mach/common.h>
+ #include <mach/mcspi.h>
++#include <mach/omapfb.h>
++#include <mach/display.h>
+
+ #include "sdram-micron-mt46h32m32lf-6.h"
+ #include "twl4030-generic-scripts.h"
+@@ -161,14 +163,215 @@ static int __init omap3_evm_i2c_init(void)
+ 	omap_register_i2c_bus(3, 400, NULL, 0);
+ 	return 0;
+ }
++static struct omap_fbmem_config evm_fbmem0_config = {
++		.size = 480*720*4,
++		.start = OMAPFB_MEMTYPE_SDRAM,
++};
+
+-static struct platform_device omap3_evm_lcd_device = {
+-	.name		= "omap3evm_lcd",
+-	.id		= -1,
++static struct omap_fbmem_config evm_fbmem1_config = {
++		.size = 480*720*4,
++		.start = OMAPFB_MEMTYPE_SDRAM,
+ };
+
+-static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
++static struct omap_fbmem_config evm_fbmem2_config = {
++		.size = 480*720*4,
++		.start = OMAPFB_MEMTYPE_SDRAM,
++};
++#define LCD_PANEL_LR		2
++#define LCD_PANEL_UD		3
++#define LCD_PANEL_INI		152
++#define LCD_PANEL_ENABLE_GPIO	153
++#define LCD_PANEL_QVGA		154
++#define LCD_PANEL_RESB		155
++
++#define ENABLE_VDAC_DEDICATED	0x03
++#define ENABLE_VDAC_DEV_GRP	0x20
++#define ENABLE_VPLL2_DEDICATED	0x05
++#define ENABLE_VPLL2_DEV_GRP	0xE0
++
++#define TWL4030_GPIODATA_IN3	0x03
++#define TWL4030_GPIODATA_DIR3	0x06
++#define TWL4030_VPLL2_DEV_GRP	0x33
++#define TWL4030_VPLL2_DEDICATED	0x36
++
++static int lcd_enabled;
++static int dvi_enabled;
++
++static void __init evm_display_init(void)
++{
++	int r;
++	r = gpio_request(LCD_PANEL_LR, "lcd_panel_lr");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_LR\n");
++		return;
++	}
++	r = gpio_request(LCD_PANEL_UD, "lcd_panel_ud");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_UD\n");
++		goto err_1;
++	}
++
++	r = gpio_request(LCD_PANEL_INI, "lcd_panel_ini");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_INI\n");
++		goto err_2;
++	}
++	r = gpio_request(LCD_PANEL_RESB, "lcd_panel_resb");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_RESB\n");
++		goto err_3;
++	}
++	r = gpio_request(LCD_PANEL_QVGA, "lcd_panel_qvga");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_QVGA\n");
++		goto err_4;
++	}
++
++	gpio_direction_output(LCD_PANEL_LR, 0);
++	gpio_direction_output(LCD_PANEL_UD, 0);
++	gpio_direction_output(LCD_PANEL_INI, 0);
++	gpio_direction_output(LCD_PANEL_RESB, 0);
++	gpio_direction_output(LCD_PANEL_QVGA, 0);
++
++#define TWL_LED_LEDEN           0x00
++#define TWL_PWMA_PWMAON         0x00
++#define TWL_PWMA_PWMAOFF        0x01
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
++
++	gpio_direction_output(LCD_PANEL_RESB, 1);
++	gpio_direction_output(LCD_PANEL_INI, 1);
++	gpio_direction_output(LCD_PANEL_QVGA, 0);
++	gpio_direction_output(LCD_PANEL_LR, 1);
++	gpio_direction_output(LCD_PANEL_UD, 1);
++
++	return;
++
++err_4:
++	gpio_free(LCD_PANEL_RESB);
++err_3:
++	gpio_free(LCD_PANEL_INI);
++err_2:
++	gpio_free(LCD_PANEL_UD);
++err_1:
++	gpio_free(LCD_PANEL_LR);
++
++}
++
++static int panel_enable_lcd(struct omap_display *display)
++{
++	if (dvi_enabled) {
++		printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++		return -EINVAL;
++	}
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
++	}
++	gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
++	lcd_enabled = 1;
++	return 0;
++}
++
++static void panel_disable_lcd(struct omap_display *display)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEV_GRP);
++	}
++	gpio_set_value(LCD_PANEL_ENABLE_GPIO, 1);
++	lcd_enabled = 0;
++}
++
++static struct omap_display_data evm_display_data = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "lcd",
++	.panel_name = "panel-sdp3430",
++	.u.dpi.data_lines = 16,
++	.panel_enable = panel_enable_lcd,
++	.panel_disable = panel_disable_lcd,
++};
++
++static int panel_enable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEDICATED, TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++	return 0;
++}
++
++static void panel_disable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_display_data evm_display_data_tv = {
++	.type = OMAP_DISPLAY_TYPE_VENC,
++	.name = "tv",
++	.u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++	.panel_enable = panel_enable_tv,
++	.panel_disable = panel_disable_tv,
++};
++
++
++static int panel_enable_dvi(struct omap_display *display)
++{
++	if (lcd_enabled) {
++		printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++		return -EINVAL;
++	}
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++			TWL4030_GPIODATA_IN3);
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++			TWL4030_GPIODATA_DIR3);
++	dvi_enabled = 1;
++
++	return 0;
++}
++
++static void panel_disable_dvi(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++			TWL4030_GPIODATA_IN3);
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++			TWL4030_GPIODATA_DIR3);
++	dvi_enabled = 0;
++}
++
++
++static struct omap_display_data evm_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-dvi",
++	.u.dpi.data_lines = 24,
++	.panel_enable = panel_enable_dvi,
++	.panel_disable = panel_disable_dvi,
++};
++
++static struct omap_dss_platform_data evm_dss_data = {
++	.num_displays = 3,
++	.displays = {
++		&evm_display_data,
++		&evm_display_data_dvi,
++		&evm_display_data_tv,
++	}
++};
++static struct platform_device evm_dss_device = {
++	.name		= "omap-dss",
++	.id		= -1,
++	.dev            = {
++		.platform_data = &evm_dss_data,
++	},
+ };
+
+ static void ads7846_dev_init(void)
+@@ -227,11 +430,13 @@ static void __init omap3_evm_init_irq(void)
+
+ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&omap3_evm_uart_config },
+-	{ OMAP_TAG_LCD,		&omap3_evm_lcd_config },
++	{ OMAP_TAG_FBMEM,       &evm_fbmem0_config },
++	{ OMAP_TAG_FBMEM,       &evm_fbmem1_config },
++	{ OMAP_TAG_FBMEM,       &evm_fbmem2_config },
+ };
+
+ static struct platform_device *omap3_evm_devices[] __initdata = {
+-	&omap3_evm_lcd_device,
++	&evm_dss_device,
+ 	&omap3evm_smc911x_device,
+ };
+
+@@ -250,8 +455,6 @@ static void __init omap3_evm_init(void)
+ 	omap3_evm_i2c_init();
+
+ 	platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
+-	omap_board_config = omap3_evm_config;
+-	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
+
+ 	spi_register_board_info(omap3evm_spi_board_info,
+ 				ARRAY_SIZE(omap3evm_spi_board_info));
+@@ -262,10 +465,13 @@ static void __init omap3_evm_init(void)
+ 	usb_ehci_init();
+ 	omap3evm_flash_init();
+ 	ads7846_dev_init();
++	evm_display_init();
+ }
+
+ static void __init omap3_evm_map_io(void)
+ {
++	omap_board_config = omap3_evm_config;
++	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
+ 	omap2_set_globals_343x();
+ 	omap2_map_common_io();
+ }
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index 95691ad..8211ffd 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -51,4 +51,9 @@ config PANEL_SDP3430
+         help
+           SDP3430 LCD
+
++config PANEL_OMAP3EVM
++        tristate "OMAP3EVM Panel"
++        depends on OMAP2_DSS
++        help
++          OMAP3EVM LCD Panel
+ endmenu
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index 73ab1c0..668e8c6 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -3,3 +3,4 @@ omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
+
+ obj-$(CONFIG_PANEL_DVI) += panel-dvi.o
+ obj-$(CONFIG_PANEL_SDP3430) += panel-sdp3430.o
++obj-$(CONFIG_PANEL_OMAP3EVM) += panel-omap3evm.o
+diff --git a/drivers/video/omap2/panel-omap3evm.c b/drivers/video/omap2/panel-omap3evm.c
+new file mode 100644
+index 0000000..4a00b02
+--- /dev/null
++++ b/drivers/video/omap2/panel-omap3evm.c
+@@ -0,0 +1,110 @@
++/*
++ * LCD panel support for the TI OMAP3EVM board
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
++ *
++ * Derived from drivers/video/omap2/panel-sdp3430.c
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int omap3evm_panel_init(struct omap_display *display)
++{
++	return 0;
++}
++
++static void omap3evm_panel_cleanup(struct omap_display *display)
++{
++}
++
++static int omap3evm_panel_enable(struct omap_display *display)
++{
++	int r = 0;
++
++	if (display->hw_config.panel_enable)
++		r = display->hw_config.panel_enable(display);
++
++	return r;
++}
++
++static void omap3evm_panel_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++}
++
++static int omap3evm_panel_suspend(struct omap_display *display)
++{
++	omap3evm_panel_disable(display);
++	return 0;
++}
++
++static int omap3evm_panel_resume(struct omap_display *display)
++{
++	return omap3evm_panel_enable(display);
++}
++
++static struct omap_panel omap3evm_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "panel-evm",
++	.init		= omap3evm_panel_init,
++	.cleanup	= omap3evm_panel_cleanup,
++	.enable		= omap3evm_panel_enable,
++	.disable	= omap3evm_panel_disable,
++	.suspend	= omap3evm_panel_suspend,
++	.resume		= omap3evm_panel_resume,
++	/*.set_mode	= omap3evm_set_mode, */
++
++	.timings = {
++		.pixel_clock	= 26000,
++
++		.hsw		= 4,
++		.hfp		= 4,
++		.hbp		= 40,
++
++		.vsw		= 2,
++		.vfp		= 2,
++		.vbp		= 7,
++	},
++
++	.acb		= 0x28,
++
++	.config		= OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
++		OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
++
++	.x_res = 480,
++	.y_res = 640,
++	.bpp = 18,
++};
++
++
++static int __init omap3evm_panel_drv_init(void)
++{
++	omap_dss_register_panel(&omap3evm_panel);
++	return 0;
++}
++
++static void __exit omap3evm_panel_drv_exit(void)
++{
++	omap_dss_unregister_panel(&omap3evm_panel);
++}
++
++module_init(omap3evm_panel_drv_init);
++module_exit(omap3evm_panel_drv_exit);
++MODULE_LICENSE("GPL");
+--
+1.5.6
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/omap3evm-lcd-redtint.diff b/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/omap3evm-lcd-redtint.diff
new file mode 100644
index 0000000000..54ea3c9f68
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap3evm/omap3evm-lcd-redtint.diff
@@ -0,0 +1,66 @@
+Message-ID: <c656a4d20809270046u341aec27k6d896d4b42e799d4@mail.gmail.com>
+Date: 	Sat, 27 Sep 2008 03:46:18 -0400
+From: "arun c" <arun.edarath@gmail.com>
+To: "Daniel Schaeffer" <daniel.schaeffer@timesys.com>
+Subject: Re: OMAP3EVM LCD red tint
+
+Hi Daniel Schaeffer
+
+On Fri, Sep 26, 2008 at 4:20 PM, Daniel Schaeffer
+<daniel.schaeffer@timesys.com> wrote:
+> Has anyone looked into why the LCD display on the OMAP3EVM is always tinted
+> red? I created a couple of color test images that I cat'ed to /dev/fb and it
+> looks like the blue color channel is completely ignored.  I was testing on
+> v2.6.26-omap2 but is doesn't look like there have been any changes to the fb
+> driver since then so I'm assuming the issue is also present in the head of
+> the git tree.
+>
+> Regards,
+>
+> Daniel Schaeffer
+>
+
+Try the patch below(Remember that you may have to manually edit because
+this patch is against current HEAD)
+
+
+diff --git a/drivers/video/omap/lcd_omap3evm.c
+b/drivers/video/omap/lcd_omap3evm.c
+index a564ca5..821bafe 100644
+--- a/drivers/video/omap/lcd_omap3evm.c
++++ b/drivers/video/omap/lcd_omap3evm.c
+@@ -44,6 +44,8 @@
+ #define ENABLE_VDAC_DEV_GRP	0x20
+ #define ENABLE_VPLL2_DEDICATED	0x05
+ #define ENABLE_VPLL2_DEV_GRP	0xE0
++#define TWL4030_VPLL2_DEV_GRP	0x33
++#define TWL4030_VPLL2_DEDICATED	0x36
+
+ #define TWL_LED_LEDEN		0x00
+ #define TWL_PWMA_PWMAON		0x00
+@@ -86,12 +88,24 @@ static void omap3evm_panel_cleanup(struct lcd_panel *panel)
+
+ static int omap3evm_panel_enable(struct lcd_panel *panel)
+ {
++	if (omap_rev > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
++	}
+ 	omap_set_gpio_dataout(LCD_PANEL_ENABLE_GPIO, 0);
+ 	return 0;
+ }
+
+ static void omap3evm_panel_disable(struct lcd_panel *panel)
+ {
++	if (omap_rev > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++			TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++			TWL4030_VPLL2_DEV_GRP);
++	}
+ 	omap_set_gpio_dataout(LCD_PANEL_ENABLE_GPIO, 1);
+ }
+
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omap5912osk/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/omap5912osk/defconfig
new file mode 100644
index 0000000000..3c334868ea
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omap5912osk/defconfig
@@ -0,0 +1,1098 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23-rc2-omap1
+# Tue Aug 21 23:22:37 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+CONFIG_ARCH_OMAP1=y
+# CONFIG_ARCH_OMAP2 is not set
+# CONFIG_ARCH_OMAP3 is not set
+
+#
+# OMAP Feature Selections
+#
+CONFIG_OMAP_RESET_CLOCKS=y
+# CONFIG_OMAP_BOOT_TAG is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+# CONFIG_OMAP_DM_TIMER is not set
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_OMAP_DSP is not set
+
+#
+# OMAP Core Type
+#
+# CONFIG_ARCH_OMAP730 is not set
+# CONFIG_ARCH_OMAP15XX is not set
+CONFIG_ARCH_OMAP16XX=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_INNOVATOR is not set
+# CONFIG_MACH_OMAP_H2 is not set
+# CONFIG_MACH_OMAP_H3 is not set
+CONFIG_MACH_OMAP_OSK=y
+# CONFIG_OMAP_OSK_MISTRAL is not set
+# CONFIG_MACH_NOKIA770 is not set
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP CPU Speed
+#
+# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
+# CONFIG_OMAP_ARM_216MHZ is not set
+CONFIG_OMAP_ARM_192MHZ=y
+# CONFIG_OMAP_ARM_168MHZ is not set
+# CONFIG_OMAP_ARM_120MHZ is not set
+# CONFIG_OMAP_ARM_60MHZ is not set
+# CONFIG_OMAP_ARM_30MHZ is not set
+# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+CONFIG_OMAP_CF=y
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_IDE=m
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_OMAP=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_OMAP=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TPS65010=y
+# CONFIG_SENSORS_TLV320AIC23 is not set
+# CONFIG_GPIOEXPANDER_OMAP is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_NEW_LEDS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_FB_OMAP_DMA_TUNE is not set
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/omapzoom/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/omapzoom/defconfig
new file mode 100644
index 0000000000..aa11eb04fc
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/omapzoom/defconfig
@@ -0,0 +1,1951 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-omap1
+# Mon Mar 30 15:25:29 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_TICK_GPTIMER=1
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_OMAP_SERIAL_WAKE=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_NOKIA_RX51 is not set
+CONFIG_MACH_OMAP_LDP=y
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=n
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+# CONFIG_ARM_ERRATUM_451034 is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_SUSPEND is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+CONFIG_BT_HCIBTSDIO=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+CONFIG_LIB80211_CRYPT_WEP=y
+CONFIG_LIB80211_CRYPT_CCMP=y
+CONFIG_LIB80211_CRYPT_TKIP=y
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+CONFIG_EEPROM_93CX6=y
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=y
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=y
+CONFIG_USB_NET_RNDIS_WLAN=y
+CONFIG_RTL8187=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_P54_COMMON=y
+CONFIG_P54_USB=y
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_ZD1211RW=y
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_RT2X00=y
+CONFIG_RT2500USB=y
+CONFIG_RT73USB=y
+CONFIG_RT2X00_LIB_USB=y
+CONFIG_RT2X00_LIB=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=y
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+CONFIG_USB_NET_RNDIS_HOST=y
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=y
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_TWL4030=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+CONFIG_TWL4030_MADC=y
+# CONFIG_TWL4030_POWEROFF is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+CONFIG_W1=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2490 is not set
+# CONFIG_W1_MASTER_DS2482 is not set
+# CONFIG_W1_MASTER_DS1WM is not set
+# CONFIG_W1_MASTER_GPIO is not set
+CONFIG_HDQ_MASTER_OMAP=y
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+# CONFIG_W1_SLAVE_DS2760 is not set
+CONFIG_W1_SLAVE_BQ27000=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+CONFIG_TWL4030_BCI_BATTERY=y
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_POWER is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders/decoders and other helper chips
+#
+
+#
+# Audio decoders
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA9875 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VIDEO_CLASS is not set
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+CONFIG_FB_FOREIGN_ENDIAN=y
+CONFIG_FB_BOTH_ENDIAN=y
+# CONFIG_FB_BIG_ENDIAN is not set
+# CONFIG_FB_LITTLE_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_OMAP=y
+CONFIG_FB_OMAP_LCD_VGA=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=14
+# CONFIG_OMAP2_DSS is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+CONFIG_LCD_ILI9320=y
+# CONFIG_LCD_TDO24M is not set
+CONFIG_LCD_VGG2432A4=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=y
+# CONFIG_SND_USB_CAIAQ_INPUT is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+CONFIG_LEDS_OMAP=y
+CONFIG_LEDS_OMAP_PWM=y
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+CONFIG_REGULATOR_BQ24022=y
+CONFIG_REGULATOR_TWL4030=y
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/overo/defconfig b/recipes/kexecboot/linux-kexecboot-2.6.29/overo/defconfig
new file mode 100644
index 0000000000..0101ca5099
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/overo/defconfig
@@ -0,0 +1,2248 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-omap1
+# Wed Apr  8 18:20:57 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_IOMMU is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_TICK_GPTIMER=1
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+CONFIG_MACH_OVERO=y
+# CONFIG_MACH_OMAP3_PANDORA is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+# CONFIG_ARM_ERRATUM_451034 is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+CONFIG_BT_HCIBTSDIO=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+# CONFIG_BT_HCIUART_LL is not set
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_EEPROM_93CX6=m
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=m
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=m
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_DEBUG=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=m
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=m
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_POWER is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX2341X=m
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_VIDEO_OMAP3 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+# CONFIG_VIDEO_EM28XX is not set
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_USBVIDEO=m
+CONFIG_USB_VICAM=m
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_KONICAWC=m
+CONFIG_USB_QUICKCAM_MESSENGER=m
+# CONFIG_USB_ET61X251 is not set
+CONFIG_VIDEO_OVCAMCHIP=m
+CONFIG_USB_W9968CF=m
+CONFIG_USB_OV511=m
+CONFIG_USB_SE401=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_STV680=m
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_ZR364XX=m
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+# CONFIG_DVB_USB_DW2102 is not set
+# CONFIG_DVB_USB_CINERGY_T2 is not set
+# CONFIG_DVB_USB_ANYSEE is not set
+# CONFIG_DVB_USB_DTV5100 is not set
+# CONFIG_DVB_USB_AF9015 is not set
+# CONFIG_DVB_SIANO_SMS1XXX is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# Multistandard (satellite) frontends
+#
+# CONFIG_DVB_STB0899 is not set
+# CONFIG_DVB_STB6100 is not set
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+# CONFIG_DVB_TDA8261 is not set
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+# CONFIG_DVB_TUNER_CX24113 is not set
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_SI21XX is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+# CONFIG_DVB_DRX397XD is not set
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+# CONFIG_DVB_LGDT3304 is not set
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_S921 is not set
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+# CONFIG_DVB_LGS8GL5 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# CONFIG_DVB_AF9013 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_VRAM_SIZE=10
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+CONFIG_OMAP2_DSS_VENC=y
+# CONFIG_OMAP2_DSS_SDI is not set
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_USE_DSI_PLL=y
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_GENERIC=y
+CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C=y
+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_PANEL_N800 is not set
+# CONFIG_CTRL_BLIZZARD is not set
+CONFIG_FB_OMAP2=y
+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
+CONFIG_FB_OMAP2_NUM_FBS=3
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_HRTIMER=m
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_OVERO=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TWL4030=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_NTRIG is not set
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_OMAP_EHCI_PHY_MODE=y
+# CONFIG_OMAP_EHCI_TLL_MODE is not set
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+CONFIG_USB_MUSB_DEBUG=y
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=y
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=m
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_OPTION=m
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+# CONFIG_USB_BERRY_CHARGE is not set
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SISUSBVGA_CON=y
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+CONFIG_USB_GADGET_OMAP=y
+CONFIG_USB_OMAP=y
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+# CONFIG_LEDS_OMAP is not set
+# CONFIG_LEDS_OMAP_PWM is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_TWL4030=y
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/overo/ehci.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/overo/ehci.patch
new file mode 100644
index 0000000000..72c6b9bec3
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/overo/ehci.patch
@@ -0,0 +1,113 @@
+diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
+index 489439d..2c6305b 100644
+--- a/arch/arm/mach-omap2/usb-ehci.c
++++ b/arch/arm/mach-omap2/usb-ehci.c
+@@ -152,9 +152,7 @@ static void setup_ehci_io_mux(void)
+ 
+ void __init usb_ehci_init(void)
+ {
+-	/* Setup Pin IO MUX for EHCI */
+-	if (cpu_is_omap34xx())
+-		setup_ehci_io_mux();
++	/* TODO: Setup Pin IO MUX for EHCI - moved this temporarily to U-boot */
+ 
+ 	if (platform_device_register(&ehci_device) < 0) {
+ 		printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
+
+diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
+index 1b3266c..8472996 100644
+--- a/drivers/usb/host/ehci-omap.c
++++ b/drivers/usb/host/ehci-omap.c
+@@ -48,16 +48,26 @@
+  *		to get the PHY state machine in working state
+  */
+ #define EXTERNAL_PHY_RESET
++#ifdef CONFIG_MACH_OVERO
++#define	EXT_PHY_RESET_GPIO_PORT2	(183)
++#else
+ #define	EXT_PHY_RESET_GPIO_PORT1	(57)
+ #define	EXT_PHY_RESET_GPIO_PORT2	(61)
++#endif
+ #define	EXT_PHY_RESET_DELAY		(10)
+ 
++#define PHY_STP_PULLUP_ENABLE           (0x10)
++#define PHY_STP_PULLUP_DISABLE          (0x90)
++
++
+ /* ISSUE2:
+  * USBHOST supports External charge pump PHYs only
+  * Use the VBUS from Port1 to power VBUS of Port2 externally
+  * So use Port2 as the working ULPI port
+  */
++#ifndef CONFIG_MACH_OVERO
+ #define VBUS_INTERNAL_CHARGEPUMP_HACK
++#endif
+ 
+ #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
+ 
+@@ -225,14 +235,43 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 
+ #ifdef EXTERNAL_PHY_RESET
+ 	/* Refer: ISSUE1 */
++#ifndef CONFIG_MACH_OVERO
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT1, "USB1 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT1, 0);
++#endif
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT2, "USB2 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT2, 0);
++	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 0);
+ 	/* Hold the PHY in RESET for enough time till DIR is high */
+ 	udelay(EXT_PHY_RESET_DELAY);
+ #endif
+ 
++        /*
++         * The PHY register 0x7 - Interface Control register is
++         * configured to disable the integrated STP pull-up resistor
++         * used for interface protection.
++	 *
++	 * May not need to be here.
++         */
++        omap_writel((0x7 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* interface reg */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (PHY_STP_PULLUP_DISABLE),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
++        /* Force PHY to HS */
++        omap_writel((0x4 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* function ctrl */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (0x40),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
+ 	/* Configure TLL for 60Mhz clk for ULPI */
+ 	ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
+ 	if (IS_ERR(ehci_clocks->usbtll_fck_clk))
+@@ -307,7 +346,9 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 	 * Hold the PHY in RESET for enough time till PHY is settled and ready
+ 	 */
+ 	udelay(EXT_PHY_RESET_DELAY);
++#ifndef CONFIG_MACH_OVERO
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT1, 1);
++#endif
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 1);
+ #endif
+ 
+@@ -393,7 +434,9 @@ static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 
+ 
+ #ifdef EXTERNAL_PHY_RESET
++#ifndef CONFIG_MACH_OVERO
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT1);
++#endif
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT2);
+ #endif
+
+--
+1.6.0.4.790.gaa14a 
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/read_die_ids.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/read_die_ids.patch
new file mode 100644
index 0000000000..3f6c930cc1
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/read_die_ids.patch
@@ -0,0 +1,23 @@
+OMAP2/3 TAP: enable debug messages
+
+From: Paul Walmsley <paul@pwsan.com>
+
+This patch causes the OMAP2/3 chip ID code to display the full DIE_ID registers at boot.
+
+---
+
+ arch/arm/mach-omap2/id.c |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
+index c7f9ab7..a154b5e 100644
+--- a/arch/arm/mach-omap2/id.c
++++ b/arch/arm/mach-omap2/id.c
+@@ -10,6 +10,7 @@
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
++#define DEBUG
+ 
+ #include <linux/module.h>
+ #include <linux/kernel.h>
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/timer-suppression.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/timer-suppression.patch
new file mode 100644
index 0000000000..04362c96e3
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/timer-suppression.patch
@@ -0,0 +1,43 @@
+diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
+index b854a89..26f5569 100644
+--- a/kernel/time/tick-sched.c
++++ b/kernel/time/tick-sched.c
+@@ -253,6 +253,16 @@ void tick_nohz_stop_sched_tick(void)
+ 
+ 	/* Schedule the tick, if we are at least one jiffie off */
+ 	if ((long)delta_jiffies >= 1) {
++		/*
++		 * calculate the expiry time for the next timer wheel
++		 * timer
++		 */
++		expires = ktime_add_ns(last_update, tick_period.tv64 *
++					delta_jiffies);
++
++		/* Skip reprogram of event if its not changed */
++		if(ts->tick_stopped && ktime_equal(expires, dev->next_event))
++		goto out2;
+ 
+ 		if (delta_jiffies > 1)
+ 			cpu_set(cpu, nohz_cpu_mask);
+@@ -304,12 +314,7 @@ void tick_nohz_stop_sched_tick(void)
+ 			goto out;
+ 		}
+ 
+-		/*
+-		 * calculate the expiry time for the next timer wheel
+-		 * timer
+-		 */
+-		expires = ktime_add_ns(last_update, tick_period.tv64 *
+-				       delta_jiffies);
++		/* Mark expiries */
+ 		ts->idle_expires = expires;
+ 
+ 		if (ts->nohz_mode == NOHZ_MODE_HIGHRES) {
+@@ -328,6 +333,7 @@ void tick_nohz_stop_sched_tick(void)
+ 		tick_do_update_jiffies64(ktime_get());
+ 		cpu_clear(cpu, nohz_cpu_mask);
+ 	}
++out2:	
+ 	raise_softirq_irqoff(TIMER_SOFTIRQ);
+ out:
+ 	ts->next_jiffies = next_jiffies;
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/touchscreen.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/touchscreen.patch
new file mode 100644
index 0000000000..2325c401e4
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/touchscreen.patch
@@ -0,0 +1,22 @@
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index d8109ae..f8ce669 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -128,8 +128,16 @@ static int ads7846_get_pendown_state(void)
+ }
+ 
+ struct ads7846_platform_data ads7846_config = {
++	.x_max			= 0x0fff,
++	.y_max			= 0x0fff,
++	.x_plate_ohms		= 180,
++	.pressure_max		= 255,
++	.debounce_max		= 10,
++	.debounce_tol		= 3,
++	.debounce_rep		= 1,
+ 	.get_pendown_state	= ads7846_get_pendown_state,
+ 	.keep_vref_on		= 1,
++	.settle_delay_usecs	= 150,
+ };
+ 
+ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/usbttyfix.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/usbttyfix.patch
new file mode 100644
index 0000000000..997705a31b
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/usbttyfix.patch
@@ -0,0 +1,29 @@
+To get USB HOST mode working on USB OTG Port with USB TTY enabled U-boot
+
+Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
+---
+--- linux-2.6.git/drivers/usb/musb/omap2430.c	2009-01-19 22:42:18.000000000 +0530
++++ linux-2.6.git/drivers/usb/musb/omap2430.c	2009-02-19 12:45:22.000000000 +0530
+@@ -33,6 +33,7 @@
+ #include <linux/list.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
++#include <linux/i2c/twl4030.h>
+ 
+ #include <asm/mach-types.h>
+ #include <mach/hardware.h>
+@@ -233,6 +234,14 @@ int __init musb_platform_init(struct mus
+ 	omap_cfg_reg(AE5_2430_USB0HS_STP);
+ #endif
+ 
++	/* Reset MUSB Controller */
++	omap_writel(SOFTRST,OTG_SYSCONFIG);
++
++#if defined(CONFIG_TWL4030_USB)
++	/* Reset the TWL USB PHY */
++	twl4030_i2c_write_u8(TWL4030_MODULE_USB, 0x60, 0x4);
++#endif
++
+ 	musb->xceiv = *x;
+ 	musb_platform_resume(musb);
+ 
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/01-vfp-pm.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/01-vfp-pm.patch
new file mode 100644
index 0000000000..70d4d1efc5
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/01-vfp-pm.patch
@@ -0,0 +1,128 @@
+From: Ben Dooks <ben-linux@fluff.org>
+Date: Thu, 18 Dec 2008 10:26:54 +0000 (+0100)
+Subject: 5349/1: VFP: Add PM code to save and restore current VFP state
+X-Git-Url: http://siarhei.siamashka.name/gitweb/?p=linux-omap-2.6.git;a=commitdiff_plain;h=d504d72ad38e54b5feda67e956834348d6a500e1
+
+5349/1: VFP: Add PM code to save and restore current VFP state
+
+[ARM] 5349/1: VFP: Add PM code to save and restore current VFP state
+
+When CONFIG_PM is selected, the VFP code does not have any handler
+installed to deal with either saving the VFP state of the current
+task, nor does it do anything to try and restore the VFP after a
+resume.
+
+On resume, the VFP will have been reset and the co-processor access
+control registers are in an indeterminate state (very probably the
+CP10 and CP11 the VFP uses will have been disabled by the ARM core
+reset). When this happens, resume will break as soon as it tries to
+unfreeze the tasks and restart scheduling.
+
+Add a sys device to allow us to hook the suspend call to save the
+current thread state if the thread is using VFP and a resume hook
+which restores the CP10/CP11 access and ensures the VFP is disabled
+so that the lazy swapping will take place on next access.
+
+Signed-off-by: Ben Dooks <ben-linux@fluff.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+---
+
+diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
+index c85860b..8de86e4 100644
+--- a/arch/arm/vfp/vfp.h
++++ b/arch/arm/vfp/vfp.h
+@@ -377,6 +377,6 @@ struct op {
+ 	u32 flags;
+ };
+ 
+-#ifdef CONFIG_SMP
++#if defined(CONFIG_SMP) || defined(CONFIG_PM)
+ extern void vfp_save_state(void *location, u32 fpexc);
+ #endif
+diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
+index a62dcf7..b21f43f 100644
+--- a/arch/arm/vfp/vfphw.S
++++ b/arch/arm/vfp/vfphw.S
+@@ -166,7 +166,7 @@ process_exception:
+ 					@ retry the faulted instruction
+ ENDPROC(vfp_support_entry)
+ 
+-#ifdef CONFIG_SMP
++#if defined(CONFIG_SMP) || defined(CONFIG_PM)
+ ENTRY(vfp_save_state)
+ 	@ Save the current VFP state
+ 	@ r0 - save location
+diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
+index 67ca340..9f476a1 100644
+--- a/arch/arm/vfp/vfpmodule.c
++++ b/arch/arm/vfp/vfpmodule.c
+@@ -322,6 +322,61 @@ static void vfp_enable(void *unused)
+ 	set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
+ }
+ 
++#ifdef CONFIG_PM
++#include <linux/sysdev.h>
++
++static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state)
++{
++	struct thread_info *ti = current_thread_info();
++	u32 fpexc = fmrx(FPEXC);
++
++	/* if vfp is on, then save state for resumption */
++	if (fpexc & FPEXC_EN) {
++		printk(KERN_DEBUG "%s: saving vfp state\n", __func__);
++		vfp_save_state(&ti->vfpstate, fpexc);
++
++		/* disable, just in case */
++		fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
++	}
++
++	/* clear any information we had about last context state */
++	memset(last_VFP_context, 0, sizeof(last_VFP_context));
++
++	return 0;
++}
++
++static int vfp_pm_resume(struct sys_device *dev)
++{
++	/* ensure we have access to the vfp */
++	vfp_enable(NULL);
++
++	/* and disable it to ensure the next usage restores the state */
++	fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
++
++	return 0;
++}
++
++static struct sysdev_class vfp_pm_sysclass = {
++	.name		= "vfp",
++	.suspend	= vfp_pm_suspend,
++	.resume		= vfp_pm_resume,
++};
++
++static struct sys_device vfp_pm_sysdev = {
++	.cls	= &vfp_pm_sysclass,
++};
++
++static void vfp_pm_init(void)
++{
++	sysdev_class_register(&vfp_pm_sysclass);
++	sysdev_register(&vfp_pm_sysdev);
++}
++
++
++#else
++static inline void vfp_pm_init(void) { }
++#endif /* CONFIG_PM */
++
+ #include <linux/smp.h>
+ 
+ /*
+@@ -365,6 +420,7 @@ static int __init vfp_init(void)
+ 		vfp_vector = vfp_support_entry;
+ 
+ 		thread_register_notifier(&vfp_notifier_block);
++		vfp_pm_init();
+ 
+ 		/*
+ 		 * We detected VFP, and the support code is
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/02-vfp-ptrace.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/02-vfp-ptrace.patch
new file mode 100644
index 0000000000..feba206f95
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/02-vfp-ptrace.patch
@@ -0,0 +1,231 @@
+From: Catalin Marinas <catalin.marinas@arm.com>
+Date: Wed, 11 Feb 2009 11:12:56 +0000 (+0100)
+Subject: 5387/1: Add ptrace VFP support on ARM
+X-Git-Url: http://siarhei.siamashka.name/gitweb/?p=linux-omap-2.6.git;a=commitdiff_plain;h=4dd5beb2244f15c895aba46474bd89545327d1a6
+
+5387/1: Add ptrace VFP support on ARM
+
+[ARM] 5387/1: Add ptrace VFP support on ARM
+
+This patch adds ptrace support for setting and getting the VFP registers
+using PTRACE_SETVFPREGS and PTRACE_GETVFPREGS. The user_vfp structure
+defined in asm/user.h contains 32 double registers (to cover VFPv3 and
+Neon hardware) and the FPSCR register.
+
+Cc: Paul Brook <paul@codesourcery.com>
+Cc: Daniel Jacobowitz <dan@codesourcery.com>
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+---
+
+diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
+index 7319261..236a06b 100644
+--- a/arch/arm/include/asm/ptrace.h
++++ b/arch/arm/include/asm/ptrace.h
+@@ -27,6 +27,8 @@
+ /* PTRACE_SYSCALL is 24 */
+ #define PTRACE_GETCRUNCHREGS	25
+ #define PTRACE_SETCRUNCHREGS	26
++#define PTRACE_GETVFPREGS	27
++#define PTRACE_SETVFPREGS	28
+ 
+ /*
+  * PSR bits
+diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
+index 68b9ec8..b9dc8a8 100644
+--- a/arch/arm/include/asm/thread_info.h
++++ b/arch/arm/include/asm/thread_info.h
+@@ -113,6 +113,8 @@ extern void iwmmxt_task_restore(struct thread_info *, void *);
+ extern void iwmmxt_task_release(struct thread_info *);
+ extern void iwmmxt_task_switch(struct thread_info *);
+ 
++extern void vfp_sync_state(struct thread_info *thread);
++
+ #endif
+ 
+ /*
+diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h
+index 825c1e7..df95e05 100644
+--- a/arch/arm/include/asm/user.h
++++ b/arch/arm/include/asm/user.h
+@@ -81,4 +81,13 @@ struct user{
+ #define HOST_TEXT_START_ADDR (u.start_code)
+ #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
+ 
++/*
++ * User specific VFP registers. If only VFPv2 is present, registers 16 to 31
++ * are ignored by the ptrace system call.
++ */
++struct user_vfp {
++	unsigned long long fpregs[32];
++	unsigned long fpscr;
++};
++
+ #endif /* _ARM_USER_H */
+diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
+index df653ea..89882a1 100644
+--- a/arch/arm/kernel/ptrace.c
++++ b/arch/arm/kernel/ptrace.c
+@@ -653,6 +653,54 @@ static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp)
+ }
+ #endif
+ 
++#ifdef CONFIG_VFP
++/*
++ * Get the child VFP state.
++ */
++static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
++{
++	struct thread_info *thread = task_thread_info(tsk);
++	union vfp_state *vfp = &thread->vfpstate;
++	struct user_vfp __user *ufp = data;
++
++	vfp_sync_state(thread);
++
++	/* copy the floating point registers */
++	if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
++			 sizeof(vfp->hard.fpregs)))
++		return -EFAULT;
++
++	/* copy the status and control register */
++	if (put_user(vfp->hard.fpscr, &ufp->fpscr))
++		return -EFAULT;
++
++	return 0;
++}
++
++/*
++ * Set the child VFP state.
++ */
++static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
++{
++	struct thread_info *thread = task_thread_info(tsk);
++	union vfp_state *vfp = &thread->vfpstate;
++	struct user_vfp __user *ufp = data;
++
++	vfp_sync_state(thread);
++
++	/* copy the floating point registers */
++	if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
++			   sizeof(vfp->hard.fpregs)))
++		return -EFAULT;
++
++	/* copy the status and control register */
++	if (get_user(vfp->hard.fpscr, &ufp->fpscr))
++		return -EFAULT;
++
++	return 0;
++}
++#endif
++
+ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+ {
+ 	int ret;
+@@ -775,6 +823,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+ 			break;
+ #endif
+ 
++#ifdef CONFIG_VFP
++		case PTRACE_GETVFPREGS:
++			ret = ptrace_getvfpregs(child, (void __user *)data);
++			break;
++
++		case PTRACE_SETVFPREGS:
++			ret = ptrace_setvfpregs(child, (void __user *)data);
++			break;
++#endif
++
+ 		default:
+ 			ret = ptrace_request(child, request, addr, data);
+ 			break;
+diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
+index 8de86e4..c8c98dd 100644
+--- a/arch/arm/vfp/vfp.h
++++ b/arch/arm/vfp/vfp.h
+@@ -377,6 +377,4 @@ struct op {
+ 	u32 flags;
+ };
+ 
+-#if defined(CONFIG_SMP) || defined(CONFIG_PM)
+ extern void vfp_save_state(void *location, u32 fpexc);
+-#endif
+diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
+index b21f43f..902d396 100644
+--- a/arch/arm/vfp/vfphw.S
++++ b/arch/arm/vfp/vfphw.S
+@@ -166,7 +166,6 @@ process_exception:
+ 					@ retry the faulted instruction
+ ENDPROC(vfp_support_entry)
+ 
+-#if defined(CONFIG_SMP) || defined(CONFIG_PM)
+ ENTRY(vfp_save_state)
+ 	@ Save the current VFP state
+ 	@ r0 - save location
+@@ -181,7 +180,6 @@ ENTRY(vfp_save_state)
+ 	stmia	r0, {r1, r2, r3, r12}	@ save FPEXC, FPSCR, FPINST, FPINST2
+ 	mov	pc, lr
+ ENDPROC(vfp_save_state)
+-#endif
+ 
+ last_VFP_context_address:
+ 	.word	last_VFP_context
+diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
+index 9f476a1..7e12390 100644
+--- a/arch/arm/vfp/vfpmodule.c
++++ b/arch/arm/vfp/vfpmodule.c
+@@ -377,6 +377,55 @@ static void vfp_pm_init(void)
+ static inline void vfp_pm_init(void) { }
+ #endif /* CONFIG_PM */
+ 
++/*
++ * Synchronise the hardware VFP state of a thread other than current with the
++ * saved one. This function is used by the ptrace mechanism.
++ */
++#ifdef CONFIG_SMP
++void vfp_sync_state(struct thread_info *thread)
++{
++	/*
++	 * On SMP systems, the VFP state is automatically saved at every
++	 * context switch. We mark the thread VFP state as belonging to a
++	 * non-existent CPU so that the saved one will be reloaded when
++	 * needed.
++	 */
++	thread->vfpstate.hard.cpu = NR_CPUS;
++}
++#else
++void vfp_sync_state(struct thread_info *thread)
++{
++	unsigned int cpu = get_cpu();
++	u32 fpexc = fmrx(FPEXC);
++
++	/*
++	 * If VFP is enabled, the previous state was already saved and
++	 * last_VFP_context updated.
++	 */
++	if (fpexc & FPEXC_EN)
++		goto out;
++
++	if (!last_VFP_context[cpu])
++		goto out;
++
++	/*
++	 * Save the last VFP state on this CPU.
++	 */
++	fmxr(FPEXC, fpexc | FPEXC_EN);
++	vfp_save_state(last_VFP_context[cpu], fpexc);
++	fmxr(FPEXC, fpexc);
++
++	/*
++	 * Set the context to NULL to force a reload the next time the thread
++	 * uses the VFP.
++	 */
++	last_VFP_context[cpu] = NULL;
++
++out:
++	put_cpu();
++}
++#endif
++
+ #include <linux/smp.h>
+ 
+ /*
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/03-vfp-corruption.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/03-vfp-corruption.patch
new file mode 100644
index 0000000000..216d4f5eaa
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/03-vfp-corruption.patch
@@ -0,0 +1,136 @@
+From: George G. Davis <gdavis@mvista.com>
+Date: Wed, 1 Apr 2009 18:27:18 +0000 (+0100)
+Subject: 5440/1: Fix VFP state corruption due to preemption during VFP exceptions
+X-Git-Url: http://siarhei.siamashka.name/gitweb/?p=linux-omap-2.6.git;a=commitdiff_plain;h=4f7720780dc4a298a6d59c0ec39f7687022cc36f
+
+5440/1: Fix VFP state corruption due to preemption during VFP exceptions
+
+[ARM] 5440/1: Fix VFP state corruption due to preemption during VFP exceptions
+
+We've observed that ARM VFP state can be corrupted during VFP exception
+handling when PREEMPT is enabled.  The exact conditions are difficult
+to reproduce but appear to occur during VFP exception handling when a
+task causes a VFP exception which is handled via VFP_bounce and is then
+preempted by yet another task which in turn causes yet another VFP
+exception.  Since the VFP_bounce code is not preempt safe, VFP state then
+becomes corrupt.  In order to prevent preemption from occuring while
+handling a VFP exception, this patch disables preemption while handling
+VFP exceptions.
+
+Signed-off-by: George G. Davis <gdavis@mvista.com>
+Acked-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+---
+
+diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
+index ba592a9..a2bed62 100644
+--- a/arch/arm/vfp/entry.S
++++ b/arch/arm/vfp/entry.S
+@@ -15,13 +15,16 @@
+  *  r10 = thread_info structure
+  *  lr  = failure return
+  */
+-#include <linux/linkage.h>
+-#include <linux/init.h>
+-#include <asm/asm-offsets.h>
+-#include <asm/assembler.h>
++#include <asm/thread_info.h>
+ #include <asm/vfpmacros.h>
++#include "../kernel/entry-header.S"
+ 
+ ENTRY(do_vfp)
++#ifdef CONFIG_PREEMPT
++	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
++	add	r11, r4, #1		@ increment it
++	str	r11, [r10, #TI_PREEMPT]
++#endif
+ 	enable_irq
+  	ldr	r4, .LCvfp
+ 	ldr	r11, [r10, #TI_CPU]	@ CPU number
+@@ -30,6 +33,12 @@ ENTRY(do_vfp)
+ ENDPROC(do_vfp)
+ 
+ ENTRY(vfp_null_entry)
++#ifdef CONFIG_PREEMPT
++	get_thread_info	r10
++	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
++	sub	r11, r4, #1		@ decrement it
++	str	r11, [r10, #TI_PREEMPT]
++#endif
+ 	mov	pc, lr
+ ENDPROC(vfp_null_entry)
+ 
+@@ -41,6 +50,12 @@ ENDPROC(vfp_null_entry)
+ 
+ 	__INIT
+ ENTRY(vfp_testing_entry)
++#ifdef CONFIG_PREEMPT
++	get_thread_info	r10
++	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
++	sub	r11, r4, #1		@ decrement it
++	str	r11, [r10, #TI_PREEMPT]
++#endif
+ 	ldr	r0, VFP_arch_address
+ 	str	r5, [r0]		@ known non-zero value
+ 	mov	pc, r9			@ we have handled the fault
+diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
+index 902d396..ea0a156 100644
+--- a/arch/arm/vfp/vfphw.S
++++ b/arch/arm/vfp/vfphw.S
+@@ -131,6 +131,12 @@ check_for_exception:
+ 	VFPFMXR	FPEXC, r1		@ restore FPEXC last
+ 	sub	r2, r2, #4
+ 	str	r2, [sp, #S_PC]		@ retry the instruction
++#ifdef CONFIG_PREEMPT
++	get_thread_info	r10
++	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
++	sub	r11, r4, #1		@ decrement it
++	str	r11, [r10, #TI_PREEMPT]
++#endif
+ 	mov	pc, r9			@ we think we have handled things
+ 
+ 
+@@ -149,6 +155,12 @@ look_for_VFP_exceptions:
+ 	@ not recognised by VFP
+ 
+ 	DBGSTR	"not VFP"
++#ifdef CONFIG_PREEMPT
++	get_thread_info	r10
++	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
++	sub	r11, r4, #1		@ decrement it
++	str	r11, [r10, #TI_PREEMPT]
++#endif
+ 	mov	pc, lr
+ 
+ process_exception:
+diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
+index 75457b3..01599c4 100644
+--- a/arch/arm/vfp/vfpmodule.c
++++ b/arch/arm/vfp/vfpmodule.c
+@@ -266,7 +266,7 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
+ 		 * on VFP subarch 1.
+ 		 */
+ 		 vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs);
+-		 return;
++		goto exit;
+ 	}
+ 
+ 	/*
+@@ -297,7 +297,7 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
+ 	 * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1.
+ 	 */
+ 	if (fpexc ^ (FPEXC_EX | FPEXC_FP2V))
+-		return;
++		goto exit;
+ 
+ 	/*
+ 	 * The barrier() here prevents fpinst2 being read
+@@ -310,6 +310,8 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
+ 	exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs);
+ 	if (exceptions)
+ 		vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
++ exit:
++	preempt_enable();
+ }
+ 
+ static void vfp_enable(void *unused)
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/04-vfp-threads.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/04-vfp-threads.patch
new file mode 100644
index 0000000000..221b2774a1
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/04-vfp-threads.patch
@@ -0,0 +1,98 @@
+From: Imre Deak <imre.deak@nokia.com>
+Date: Wed, 1 Jul 2009 21:20:59 +0000 (+0300)
+Subject: So far vfp_sync_state worked only for threads other than the current one. This worked... 
+X-Git-Url: http://siarhei.siamashka.name/gitweb/?p=linux-omap-2.6.git;a=commitdiff_plain;h=23671113997664ae55c8132fc4a56e676d5b46c7
+
+So far vfp_sync_state worked only for threads other than the current one. This worked for tracing other threads, but not for PTRACE_TRACEME. Syncing for the current thread will also be needed by an upcoming patch adding support for VFP context save / restore around signal handlers.
+
+For SMP we need get_cpu now, since we have to protect the FPEXC
+register, other than this things remained the same for threads other
+than the current.
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+
+diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
+index 01599c4..969b77a 100644
+--- a/arch/arm/vfp/vfpmodule.c
++++ b/arch/arm/vfp/vfpmodule.c
+@@ -380,12 +380,19 @@ static inline void vfp_pm_init(void) { }
+ #endif /* CONFIG_PM */
+ 
+ /*
+- * Synchronise the hardware VFP state of a thread other than current with the
+- * saved one. This function is used by the ptrace mechanism.
++ * Synchronise the hardware VFP state of a thread with the saved one.
++ * This function is used by the ptrace mechanism and the signal handler path.
+  */
+-#ifdef CONFIG_SMP
+ void vfp_sync_state(struct thread_info *thread)
+ {
++	unsigned int cpu = get_cpu();
++	u32 fpexc = fmrx(FPEXC);
++	int vfp_enabled;
++	int self;
++
++	vfp_enabled = fpexc & FPEXC_EN;
++	self = thread == current_thread_info();
++#ifdef CONFIG_SMP
+ 	/*
+ 	 * On SMP systems, the VFP state is automatically saved at every
+ 	 * context switch. We mark the thread VFP state as belonging to a
+@@ -393,18 +400,22 @@ void vfp_sync_state(struct thread_info *thread)
+ 	 * needed.
+ 	 */
+ 	thread->vfpstate.hard.cpu = NR_CPUS;
+-}
+-#else
+-void vfp_sync_state(struct thread_info *thread)
+-{
+-	unsigned int cpu = get_cpu();
+-	u32 fpexc = fmrx(FPEXC);
+-
+ 	/*
+-	 * If VFP is enabled, the previous state was already saved and
+-	 * last_VFP_context updated.
++	 * Only the current thread's saved VFP context can be out-of-date.
++	 * For others there is nothing else to do, since we already ensured
++	 * force loading above.
+ 	 */
+-	if (fpexc & FPEXC_EN)
++	if (!self)
++		goto out;
++#endif
++	/*
++	 * If the VFP is enabled only the current thread's saved VFP
++	 * context can get out-of-date. For other threads the context
++	 * was updated when the current thread started to use the VFP.
++	 * This also means that the context will be reloaded next time
++	 * the thread uses the VFP, so no need to enforce it.
++	 */
++	if (vfp_enabled && !self)
+ 		goto out;
+ 
+ 	if (!last_VFP_context[cpu])
+@@ -413,8 +424,14 @@ void vfp_sync_state(struct thread_info *thread)
+ 	/*
+ 	 * Save the last VFP state on this CPU.
+ 	 */
+-	fmxr(FPEXC, fpexc | FPEXC_EN);
++	if (!vfp_enabled)
++		fmxr(FPEXC, fpexc | FPEXC_EN);
+ 	vfp_save_state(last_VFP_context[cpu], fpexc);
++	/*
++	 * Disable VFP in case it was enabled so that the force reload
++	 * can happen.
++	 */
++	fpexc &= ~FPEXC_EN;
+ 	fmxr(FPEXC, fpexc);
+ 
+ 	/*
+@@ -426,7 +443,6 @@ void vfp_sync_state(struct thread_info *thread)
+ out:
+ 	put_cpu();
+ }
+-#endif
+ 
+ #include <linux/smp.h>
+ 
diff --git a/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/05-vfp-signal-handlers.patch b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/05-vfp-signal-handlers.patch
new file mode 100644
index 0000000000..f648188584
--- /dev/null
+++ b/recipes/kexecboot/linux-kexecboot-2.6.29/vfp/05-vfp-signal-handlers.patch
@@ -0,0 +1,148 @@
+From: Imre Deak <imre.deak@nokia.com>
+Date: Wed, 1 Jul 2009 21:21:06 +0000 (+0300)
+Subject: Signal handlers can use floating point, so prevent them to corrupt the main thread... 
+X-Git-Url: http://siarhei.siamashka.name/gitweb/?p=linux-omap-2.6.git;a=commitdiff_plain;h=4daa6b5d833c401a9de6f136ea23daa971fc4fdc
+
+Signal handlers can use floating point, so prevent them to corrupt the main thread's VFP context. So far there were two signal stack frame formats defined based on the VFP implementation, but recently a new user struct was added for ptrace that covers all possibilities, so use it for the signal stack too.
+
+Signed-off-by: Imre Deak <imre.deak@nokia.com>
+---
+
+diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h
+index bf65e9f..5534653 100644
+--- a/arch/arm/include/asm/ucontext.h
++++ b/arch/arm/include/asm/ucontext.h
+@@ -59,23 +59,19 @@ struct iwmmxt_sigframe {
+ #endif /* CONFIG_IWMMXT */
+ 
+ #ifdef CONFIG_VFP
+-#if __LINUX_ARM_ARCH__ < 6
+-/* For ARM pre-v6, we use fstmiax and fldmiax.  This adds one extra
+- * word after the registers, and a word of padding at the end for
+- * alignment.  */
+ #define VFP_MAGIC		0x56465001
+-#define VFP_STORAGE_SIZE	152
+-#else
+-#define VFP_MAGIC		0x56465002
+-#define VFP_STORAGE_SIZE	144
+-#endif
+ 
+ struct vfp_sigframe
+ {
+ 	unsigned long		magic;
+ 	unsigned long		size;
+-	union vfp_state		storage;
+-};
++	struct user_vfp		ufp;
++	unsigned long		reserved;
++} __attribute__((__aligned__(8)));
++
++/* 8 byte for magic and size, 260 byte for ufp and 4 byte padding */
++#define VFP_STORAGE_SIZE	sizeof(struct vfp_sigframe)
++
+ #endif /* CONFIG_VFP */
+ 
+ /*
+@@ -91,7 +87,7 @@ struct aux_sigframe {
+ #ifdef CONFIG_IWMMXT
+ 	struct iwmmxt_sigframe	iwmmxt;
+ #endif
+-#if 0 && defined CONFIG_VFP /* Not yet saved.  */
++#ifdef CONFIG_VFP
+ 	struct vfp_sigframe	vfp;
+ #endif
+ 	/* Something that isn't a valid magic number for any coprocessor.  */
+diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
+index 80b8b5c..a5ef7f5 100644
+--- a/arch/arm/kernel/signal.c
++++ b/arch/arm/kernel/signal.c
+@@ -196,6 +196,67 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
+ 
+ #endif
+ 
++#ifdef CONFIG_VFP
++
++static int preserve_vfp_context(struct vfp_sigframe __user *frame)
++{
++	struct thread_info *thread = current_thread_info();
++	struct vfp_hard_struct *h = &thread->vfpstate.hard;
++	const unsigned long magic = VFP_MAGIC;
++	const unsigned long size = VFP_STORAGE_SIZE;
++	int err = 0;
++
++	vfp_sync_state(thread);
++	__put_user_error(magic, &frame->magic, err);
++	__put_user_error(size, &frame->size, err);
++
++	/*
++	 * Copy the floating point registers. There can be unused
++	 * registers see asm/hwcap.h for details.
++	 */
++	err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
++			      sizeof(h->fpregs));
++	/*
++	 * Copy the status and control register.
++	 */
++	__put_user_error(h->fpscr, &frame->ufp.fpscr, err);
++
++	return err ? -EFAULT : 0;
++}
++
++static int restore_vfp_context(struct vfp_sigframe __user *frame)
++{
++	struct thread_info *thread = current_thread_info();
++	struct vfp_hard_struct *h = &thread->vfpstate.hard;
++	unsigned long magic;
++	unsigned long size;
++	int err = 0;
++
++	vfp_sync_state(thread);
++	__get_user_error(magic, &frame->magic, err);
++	__get_user_error(size, &frame->size, err);
++
++	if (err)
++		return -EFAULT;
++	if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
++		return -EINVAL;
++
++	/*
++	 * Copy the floating point registers. There can be unused
++	 * registers see asm/hwcap.h for details.
++	 */
++	err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
++				sizeof(h->fpregs));
++	/*
++	 * Copy the status and control register.
++	 */
++	__get_user_error(h->fpscr, &frame->ufp.fpscr, err);
++
++	return err ? -EFAULT : 0;
++}
++
++#endif
++
+ /*
+  * Do a signal return; undo the signal stack.  These are aligned to 64-bit.
+  */
+@@ -254,8 +315,8 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
+ 		err |= restore_iwmmxt_context(&aux->iwmmxt);
+ #endif
+ #ifdef CONFIG_VFP
+-//	if (err == 0)
+-//		err |= vfp_restore_state(&sf->aux.vfp);
++	if (err == 0)
++		err |= restore_vfp_context(&aux->vfp);
+ #endif
+ 
+ 	return err;
+@@ -369,8 +430,8 @@ setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set)
+ 		err |= preserve_iwmmxt_context(&aux->iwmmxt);
+ #endif
+ #ifdef CONFIG_VFP
+-//	if (err == 0)
+-//		err |= vfp_save_state(&sf->aux.vfp);
++	if (err == 0)
++		err |= preserve_vfp_context(&aux->vfp);
+ #endif
+ 	__put_user_error(0, &aux->end_magic, err);
+