rename packages/ to recipes/ per earlier agreement

See links below for more details:
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816

Signed-off-by: Denys Dmytriyenko <denis@denix.org>
Acked-by: Mike Westerhof <mwester@dls.net>
Acked-by: Philip Balister <philip@balister.org>
Acked-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Marcin Juszkiewicz <hrw@openembedded.org>
Acked-by: Koen Kooi <koen@openembedded.org>
Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>

58 files changed, 129586 insertions, 0 deletions

diff --git a/recipes/linux/linux-omap-2.6.28/0001-ASoC-Add-support-for-OMAP3-EVM.patch b/recipes/linux/linux-omap-2.6.28/0001-ASoC-Add-support-for-OMAP3-EVM.patch
new file mode 100644
index 0000000000..a76e96e444
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0001-ASoC-Add-support-for-OMAP3-EVM.patch
@@ -0,0 +1,206 @@
+From c1dad0b6b434300ae64c902d11611c54c513ea10 Mon Sep 17 00:00:00 2001
+From: Anuj Aggarwal <anuj.aggarwal@ti.com>
+Date: Fri, 21 Nov 2008 17:41:03 +0530
+Subject: [PATCH] ASoC: Add support for OMAP3 EVM
+
+This patch adds ALSA SoC support for OMAP3 EVM using TWL4030 audio codec.
+
+Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com>
+---
+ sound/soc/omap/Kconfig    |    8 +++
+ sound/soc/omap/Makefile   |    3 +-
+ sound/soc/omap/omap3evm.c |  147 +++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 157 insertions(+), 1 deletions(-)
+ create mode 100644 sound/soc/omap/omap3evm.c
+
+diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
+index 0daeee4..deb6ba9 100644
+--- a/sound/soc/omap/Kconfig
++++ b/sound/soc/omap/Kconfig
+@@ -22,6 +22,14 @@ config SND_OMAP_SOC_OMAP3_BEAGLE
+ 	help
+ 	  Say Y if you want to add support for SoC audio on the Beagleboard.
+ 
++config SND_OMAP_SOC_OMAP3EVM
++        tristate "SoC Audio support for OMAP3EVM board"
++        depends on SND_OMAP_SOC && MACH_OMAP3EVM
++        select SND_OMAP_SOC_MCBSP
++        select SND_SOC_TWL4030
++        help
++          Say Y if you want to add support for SoC audio on the omap3evm board.
++
+ config SND_OMAP_SOC_OSK5912
+ 	tristate "SoC Audio support for omap osk5912"
+ 	depends on SND_OMAP_SOC && MACH_OMAP_OSK
+diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
+index 4bae404..ef31c25 100644
+--- a/sound/soc/omap/Makefile
++++ b/sound/soc/omap/Makefile
+@@ -10,9 +10,10 @@ snd-soc-n810-objs := n810.o
+ snd-soc-omap3beagle-objs := omap3beagle.o
+ snd-soc-osk5912-objs := osk5912.o
+ snd-soc-overo-objs := overo.o
++snd-soc-omap3evm-objs := omap3evm.o
+ 
+ obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o
+ obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
+ obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o
+ obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o
+-
++obj-$(CONFIG_MACH_OMAP3EVM) += snd-soc-omap3evm.o
+diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
+new file mode 100644
+index 0000000..570af55
+--- /dev/null
++++ b/sound/soc/omap/omap3evm.c
+@@ -0,0 +1,147 @@
++/*
++ * omap3evm.c  -- ALSA SoC support for OMAP3 EVM
++ *
++ * Author: Anuj Aggarwal <anuj.aggarwal@ti.com>
++ *
++ * Based on sound/soc/omap/beagle.c by Steve Sakoman
++ *
++ * Copyright (C) 2008 Texas Instruments, Incorporated
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
++ * whether express or implied; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <mach/hardware.h>
++#include <mach/gpio.h>
++#include <mach/mcbsp.h>
++
++#include "omap-mcbsp.h"
++#include "omap-pcm.h"
++#include "../codecs/twl4030.h"
++
++static int omap3evm_hw_params(struct snd_pcm_substream *substream,
++	struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
++	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
++	int ret;
++
++	/* Set codec DAI configuration */
++	ret = snd_soc_dai_set_fmt(codec_dai,
++				  SND_SOC_DAIFMT_I2S |
++				  SND_SOC_DAIFMT_NB_NF |
++				  SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0) {
++		printk(KERN_ERR "can't set codec DAI configuration\n");
++		return ret;
++	}
++
++	/* Set cpu DAI configuration */
++	ret = snd_soc_dai_set_fmt(cpu_dai,
++				  SND_SOC_DAIFMT_I2S |
++				  SND_SOC_DAIFMT_NB_NF |
++				  SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0) {
++		printk(KERN_ERR "can't set cpu DAI configuration\n");
++		return ret;
++	}
++
++	/* Set the codec system clock for DAC and ADC */
++	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
++				     SND_SOC_CLOCK_IN);
++	if (ret < 0) {
++		printk(KERN_ERR "can't set codec system clock\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static struct snd_soc_ops omap3evm_ops = {
++	.hw_params = omap3evm_hw_params,
++};
++
++/* Digital audio interface glue - connects codec <--> CPU */
++static struct snd_soc_dai_link omap3evm_dai = {
++	.name = "TWL4030",
++	.stream_name = "TWL4030",
++	.cpu_dai = &omap_mcbsp_dai[0],
++	.codec_dai = &twl4030_dai,
++	.ops = &omap3evm_ops,
++};
++
++/* Audio machine driver */
++static struct snd_soc_machine snd_soc_machine_omap3evm = {
++	.name = "omap3evm",
++	.dai_link = &omap3evm_dai,
++	.num_links = 1,
++};
++
++/* Audio subsystem */
++static struct snd_soc_device omap3evm_snd_devdata = {
++	.machine = &snd_soc_machine_omap3evm,
++	.platform = &omap_soc_platform,
++	.codec_dev = &soc_codec_dev_twl4030,
++};
++
++static struct platform_device *omap3evm_snd_device;
++
++static int __init omap3evm_soc_init(void)
++{
++	int ret;
++
++	if (!machine_is_omap3evm()) {
++		pr_debug("Not OMAP3 EVM!\n");
++		return -ENODEV;
++	}
++	pr_info("OMAP3 EVM SoC init\n");
++
++	omap3evm_snd_device = platform_device_alloc("soc-audio", -1);
++	if (!omap3evm_snd_device) {
++		printk(KERN_ERR "Platform device allocation failed\n");
++		return -ENOMEM;
++	}
++
++	platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata);
++	omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev;
++	*(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */
++
++	ret = platform_device_add(omap3evm_snd_device);
++	if (ret)
++		goto err1;
++
++	return 0;
++
++err1:
++	printk(KERN_ERR "Unable to add platform device\n");
++	platform_device_put(omap3evm_snd_device);
++
++	return ret;
++}
++
++static void __exit omap3evm_soc_exit(void)
++{
++	platform_device_unregister(omap3evm_snd_device);
++}
++
++module_init(omap3evm_soc_init);
++module_exit(omap3evm_soc_exit);
++
++MODULE_AUTHOR("Anuj Aggarwal <anuj.aggarwal@ti.com>");
++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM");
++MODULE_LICENSE("GPL");
+-- 
+1.5.6.5
+
diff --git a/recipes/linux/linux-omap-2.6.28/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch b/recipes/linux/linux-omap-2.6.28/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch
new file mode 100644
index 0000000000..fda5191421
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch
@@ -0,0 +1,10365 @@
+From 3128e95ff7e6a1bed47cc5c64a138cc3bbab492a Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 7 Jan 2009 14:30:09 +0200
+Subject: [PATCH] DSS: New display subsystem driver for OMAP2/3
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ Documentation/arm/OMAP/DSS                |  266 +++
+ arch/arm/plat-omap/Kconfig                |    2 +
+ arch/arm/plat-omap/Makefile               |    2 +
+ arch/arm/plat-omap/dss/Kconfig            |   69 +
+ arch/arm/plat-omap/dss/Makefile           |    6 +
+ arch/arm/plat-omap/dss/dispc.c            | 2113 +++++++++++++++++++
+ arch/arm/plat-omap/dss/display.c          |  787 +++++++
+ arch/arm/plat-omap/dss/dpi.c              |  344 ++++
+ arch/arm/plat-omap/dss/dsi.c              | 3187 +++++++++++++++++++++++++++++
+ arch/arm/plat-omap/dss/dss.c              |  774 +++++++
+ arch/arm/plat-omap/dss/dss.h              |  274 +++
+ arch/arm/plat-omap/dss/rfbi.c             | 1262 ++++++++++++
+ arch/arm/plat-omap/dss/sdi.c              |  174 ++
+ arch/arm/plat-omap/dss/venc.c             |  506 +++++
+ arch/arm/plat-omap/include/mach/display.h |  462 +++++
+ 15 files changed, 10228 insertions(+), 0 deletions(-)
+ create mode 100644 Documentation/arm/OMAP/DSS
+ create mode 100644 arch/arm/plat-omap/dss/Kconfig
+ create mode 100644 arch/arm/plat-omap/dss/Makefile
+ create mode 100644 arch/arm/plat-omap/dss/dispc.c
+ create mode 100644 arch/arm/plat-omap/dss/display.c
+ create mode 100644 arch/arm/plat-omap/dss/dpi.c
+ create mode 100644 arch/arm/plat-omap/dss/dsi.c
+ create mode 100644 arch/arm/plat-omap/dss/dss.c
+ create mode 100644 arch/arm/plat-omap/dss/dss.h
+ create mode 100644 arch/arm/plat-omap/dss/rfbi.c
+ create mode 100644 arch/arm/plat-omap/dss/sdi.c
+ create mode 100644 arch/arm/plat-omap/dss/venc.c
+ create mode 100644 arch/arm/plat-omap/include/mach/display.h
+
+diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
+new file mode 100644
+index 0000000..a5e608c
+--- /dev/null
++++ b/Documentation/arm/OMAP/DSS
+@@ -0,0 +1,266 @@
++OMAP2/3 Display Subsystem
++-------------------------
++
++This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
++(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
++TV-out and multiple display support.
++
++The DSS2 driver (omap-dss module) is in arch/arm/plat-omap/dss/, and the FB,
++panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
++currently side by side, you can choose which one to use.
++
++Features
++--------
++
++Working and tested features include:
++
++- MIPI DPI (parallel) output
++- MIPI DSI output in command mode
++- MIPI DBI (RFBI) output (not tested for a while, might've gotten broken)
++- SDI output
++- TV output
++- All pieces can be compiled as a module or inside kernel
++- Use DISPC to update any of the outputs
++- Use CPU to update RFBI or DSI output
++- OMAP DISPC planes
++- RGB16, RGB24 packed, RGB24 unpacked
++- YUV2, UYVY
++- Scaling
++- Adjusting DSS FCK to find a good pixel clock
++- Use DSI DPLL to create DSS FCK
++
++omap-dss driver
++------------
++
++The DSS driver does not itself have any support for Linux framebuffer, V4L or
++such like the current ones, but it has an internal kernel API that upper level
++drivers can use.
++
++The DSS driver models OMAP's overlays, overlay managers and displays in a
++flexible way to enable non-common multi-display configuration. In addition to
++modelling the hardware overlays, omap-dss supports virtual overlays and overlay
++managers. These can be used when updating a display with CPU or system DMA.
++
++Panel and controller drivers
++----------------------------
++
++The drivers implement panel or controller specific functionality and are not
++visible to users except through omapfb driver.  They register themselves to the
++DSS driver.
++
++omapfb driver
++-------------
++
++The omapfb driver implements arbitrary number of standard linux framebuffers.
++These framebuffers can be routed flexibly to any overlays, thus allowing very
++dynamic display architecture.
++
++The driver exports some omapfb specific ioctls, which are compatible with the
++ioctls in the old driver.
++
++The rest of the non standard features are exported via sysfs. Whether the final
++implementation will use sysfs, or ioctls, is still open.
++
++V4L2 drivers
++------------
++
++Currently there are no V4L2 display drivers planned, but it is possible to
++implement such either to omapfb driver, or as a separate one. From omap-dss
++point of view the V4L2 drivers should be similar to framebuffer driver.
++
++Architecture
++--------------------
++
++Some clarification what the different components do:
++
++    - Framebuffer is a memory area inside OMAP's SDRAM that contains the pixel
++      data for the image. Framebuffer has width and height and color depth.
++    - Overlay defines where the pixels are read from and where they go on the
++      screen. The overlay may be smaller than framebuffer, thus displaying only
++      part of the framebuffer. The position of the overlay may be changed if
++      the overlay is smaller than the display.
++    - Overlay manager combines the overlays in to one image and feeds them to
++      display.
++    - Display is the actual physical display device.
++
++A framebuffer can be connected to multiple overlays to show the same pixel data
++on all of the overlays. Note that in this case the overlay input sizes must be
++the same, but, in case of video overlays, the output size can be different. Any
++framebuffer can be connected to any overlay.
++
++An overlay can be connected to one overlay manager. Also DISPC overlays can be
++connected only to DISPC overlay managers, and virtual overlays can be only
++connected to virtual overlays.
++
++An overlay manager can be connected to one display. There are certain
++restrictions which kinds of displays an overlay manager can be connected:
++
++    - DISPC TV overlay manager can be only connected to TV display.
++    - Virtual overlay managers can only be connected to DBI or DSI displays.
++    - DISPC LCD overlay manager can be connected to all displays, except TV
++      display.
++
++Sysfs
++-----
++The sysfs interface is a hack, but works for testing. I don't think sysfs
++interface is the best for this in the final version, but I don't quite know
++what would be the best interfaces for these things.
++
++In /sys/devices/platform/omapfb we have four files: framebuffers,
++overlays, managers and displays. You can read them so see the current
++setup, and change them by writing to it in the form of
++"<item-id> <opt1>:<val1> <opt2>:<val2>..."
++
++"framebuffers" lists all framebuffers. Its format is:
++	<fb number>
++	p:<physical address, read only>
++	v:<virtual address, read only>
++	s:<size, read only>
++	t:<target overlay>
++
++"overlays" lists all overlays. Its format is:
++	<overlay name>
++	t:<target manager>
++	x:<xpos>
++	y:<ypos>
++	iw:<input width, read only>
++	ih:<input height, read only>
++	w:<output width>
++	h:<output height>
++	e:<enabled>
++
++"managers" lists all overlay managers. Its format is:
++	<manager name>
++	t:<target display>
++
++"displays" lists all displays. Its format is:
++	<display name>
++	e:<enabled>
++	u:<update mode>
++	t:<tear sync on/off>
++	h:<xres/hfp/hbp/hsw>
++	v:<yres/vfp/vbp/vsw>
++	p:<pix clock, in kHz>
++	m:<mode str, as in drivers/video/modedb.c:fb_find_mode>
++
++There is also a debug sysfs file at /sys/devices/platform/omap-dss/clk which
++shows how DSS has configured the clocks.
++
++Examples
++--------
++
++In the example scripts "omapfb" is a symlink to /sys/devices/platform/omapfb/.
++
++Default setup on OMAP3 SDP
++--------------------------
++
++Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
++and TV-out are not in use. The columns from left to right are:
++framebuffers, overlays, overlay managers, displays. Framebuffers are
++handled by omapfb, and the rest by the DSS.
++
++FB0 --- GFX  -\            DVI
++FB1 --- VID1 --+- LCD ---- LCD
++FB2 --- VID2 -/   TV ----- TV
++
++Switch from LCD to DVI
++----------------------
++
++dviline=`cat omapfb/displays |grep dvi`
++w=`echo $dviline | cut -d " " -f 5 | cut -d ":" -f 2 | cut -d "/" -f 1`
++h=`echo $dviline | cut -d " " -f 6 | cut -d ":" -f 2 | cut -d "/" -f 1`
++
++echo "lcd e:0" > omapfb/displays
++echo "lcd t:none" > omapfb/managers
++fbset -fb /dev/fb0 -xres $w -yres $h
++# at this point you have to switch the dvi/lcd dip-switch from the omap board
++echo "lcd t:dvi" > omapfb/managers
++echo "dvi e:1" > omapfb/displays
++
++After this the configuration looks like:
++
++FB0 --- GFX  -\         -- DVI
++FB1 --- VID1 --+- LCD -/   LCD
++FB2 --- VID2 -/   TV ----- TV
++
++Clone GFX overlay to LCD and TV
++-------------------------------
++
++tvline=`cat /sys/devices/platform/omapfb/displays |grep tv`
++w=`echo $tvline | cut -d " " -f 5 | cut -d ":" -f 2 | cut -d "/" -f 1`
++h=`echo $tvline | cut -d " " -f 6 | cut -d ":" -f 2 | cut -d "/" -f 1`
++
++echo "1 t:none" > omapfb/framebuffers
++echo "0 t:gfx,vid1" > omapfb/framebuffers
++echo "gfx e:1" > omapfb/overlays
++echo "vid1 t:tv w:$w h:$h e:1" > omapfb/overlays
++echo "tv e:1" > omapfb/displays
++
++After this the configuration looks like (only relevant parts shown):
++
++FB0 +-- GFX  ---- LCD ---- LCD
++     \- VID1 ---- TV  ---- TV
++
++Misc notes
++----------
++
++OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator. If
++that fails, it will fall back to dma_alloc_writecombine().
++
++Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
++of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
++
++Arguments
++---------
++
++vram
++	- Amount of total VRAM to preallocate. For example, "10M".
++
++omapfb.video_mode
++	- Default video mode for default display. For example,
++	  "800x400MR-24@60".  See drivers/video/modedb.c
++
++omapfb.vram
++	- VRAM allocated for each framebuffer. Normally omapfb allocates vram
++	  depending on the display size. With this you can manually allocate
++	  more. For example "4M,3M" allocates 4M for fb0, 3M for fb1.
++
++omapfb.debug
++	- Enable debug printing. You have to have OMAPFB debug support enabled
++	  in kernel config.
++
++omap-dss.def_disp
++	- Name of default display, to which all overlays will be connected.
++	  Common examples are "lcd" or "tv".
++
++omap-dss.debug
++	- Enable debug printing. You have to have DSS debug support enabled in
++	  kernel config.
++
++TODO
++----
++
++DSS locking
++
++Error checking
++- Lots of checks are missing or implemented just as BUG()
++
++Rotate (external FB)
++Rotate (VRFB)
++Rotate (SMS)
++
++System DMA update for DSI
++- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
++  to skip the empty byte?)
++
++Power management
++- Context saving
++
++Resolution change
++- The x/y res of the framebuffer are not display resolutions, but the size
++  of the overlay.
++- The display resolution affects all planes on the display.
++
++OMAP1 support
++- Not sure if needed
++
+diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
+index 2465aea..cd7d9e2 100644
+--- a/arch/arm/plat-omap/Kconfig
++++ b/arch/arm/plat-omap/Kconfig
+@@ -245,6 +245,8 @@ config OMAP_SERIAL_WAKE
+ 	  to data on the serial RX line. This allows you to wake the
+ 	  system from serial console.
+ 
++source "arch/arm/plat-omap/dss/Kconfig"
++
+ endmenu
+ 
+ endif
+diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
+index 1259846..2740497 100644
+--- a/arch/arm/plat-omap/Makefile
++++ b/arch/arm/plat-omap/Makefile
+@@ -29,3 +29,5 @@ obj-$(CONFIG_OMAP_MMU_FWK) += mmu.o
+ # OMAP mailbox framework
+ obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
+ 
++# OMAP2/3 Display Subsystem
++obj-y += dss/
+diff --git a/arch/arm/plat-omap/dss/Kconfig b/arch/arm/plat-omap/dss/Kconfig
+new file mode 100644
+index 0000000..6b342df
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/Kconfig
+@@ -0,0 +1,69 @@
++config OMAP2_DSS
++        tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
++        depends on ARCH_OMAP2 || ARCH_OMAP3
++        help
++          OMAP2/3 Display Subsystem support.
++
++if OMAP2_DSS
++
++config OMAP2_DSS_DEBUG_SUPPORT
++        bool "Debug support"
++	default y
++	help
++	  This enables debug messages. You need to enable printing
++	  with 'debug' module parameter.
++
++config OMAP2_DSS_RFBI
++	bool "RFBI support"
++        default y
++
++config OMAP2_DSS_VENC
++	bool "VENC support"
++        default y
++
++if ARCH_OMAP3
++
++config OMAP2_DSS_SDI
++	bool "SDI support"
++        default y
++
++config OMAP2_DSS_DSI
++	bool "DSI support"
++        default y
++
++endif
++
++config OMAP2_DSS_USE_DSI_PLL
++	bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
++	default n
++	depends on OMAP2_DSS_DSI
++	help
++	  Use DSI PLL to generate pixel clock.
++	  Currently only for DPI output.
++
++config OMAP2_DSS_FAKE_VSYNC
++	bool "Fake VSYNC irq from manual update displays"
++	default n
++	help
++	  If this is selected, DSI will fake a DISPC VSYNC interrupt
++	  when DSI has sent a frame.
++
++config OMAP2_DSS_MIN_FCK_PER_PCK
++	int "Minimum FCK/PCK ratio (for scaling)"
++	range 0 32
++	default 0
++	help
++	  This can be used to adjust the minimum FCK/PCK ratio.
++
++	  With this you can make sure that DISPC FCK is at least
++	  n x PCK. Video plane scaling requires higher FCK than
++	  normally.
++
++	  If this is set to 0, there's no extra constraint on the
++	  DISPC FCK. However, the FCK will at minimum be
++	  2xPCK (if active matrix) or 3xPCK (if passive matrix).
++
++	  Max FCK is 173MHz, so this doesn't work if your PCK
++	  is very high.
++
++endif
+diff --git a/arch/arm/plat-omap/dss/Makefile b/arch/arm/plat-omap/dss/Makefile
+new file mode 100644
+index 0000000..e98c6c1
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/Makefile
+@@ -0,0 +1,6 @@
++obj-$(CONFIG_OMAP2_DSS) += omap-dss.o
++omap-dss-y := dss.o display.o dispc.o dpi.o
++omap-dss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
++omap-dss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
++omap-dss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
++omap-dss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
+diff --git a/arch/arm/plat-omap/dss/dispc.c b/arch/arm/plat-omap/dss/dispc.c
+new file mode 100644
+index 0000000..20caa48
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/dispc.c
+@@ -0,0 +1,2113 @@
++/*
++ * linux/arch/arm/plat-omap/dss/dispc.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DISPC"
++
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/jiffies.h>
++
++#include <mach/sram.h>
++#include <mach/board.h>
++#include <mach/clock.h>
++
++#include <mach/display.h>
++
++#include "dss.h"
++
++/* DISPC */
++#define DISPC_BASE			0x48050400
++
++#define DISPC_SZ_REGS			SZ_1K
++
++struct dispc_reg { u16 idx; };
++
++#define DISPC_REG(idx)			((const struct dispc_reg) { idx })
++
++/* DISPC common */
++#define DISPC_REVISION			DISPC_REG(0x0000)
++#define DISPC_SYSCONFIG			DISPC_REG(0x0010)
++#define DISPC_SYSSTATUS			DISPC_REG(0x0014)
++#define DISPC_IRQSTATUS			DISPC_REG(0x0018)
++#define DISPC_IRQENABLE			DISPC_REG(0x001C)
++#define DISPC_CONTROL			DISPC_REG(0x0040)
++#define DISPC_CONFIG			DISPC_REG(0x0044)
++#define DISPC_CAPABLE			DISPC_REG(0x0048)
++#define DISPC_DEFAULT_COLOR0		DISPC_REG(0x004C)
++#define DISPC_DEFAULT_COLOR1		DISPC_REG(0x0050)
++#define DISPC_TRANS_COLOR0		DISPC_REG(0x0054)
++#define DISPC_TRANS_COLOR1		DISPC_REG(0x0058)
++#define DISPC_LINE_STATUS		DISPC_REG(0x005C)
++#define DISPC_LINE_NUMBER		DISPC_REG(0x0060)
++#define DISPC_TIMING_H			DISPC_REG(0x0064)
++#define DISPC_TIMING_V			DISPC_REG(0x0068)
++#define DISPC_POL_FREQ			DISPC_REG(0x006C)
++#define DISPC_DIVISOR			DISPC_REG(0x0070)
++#define DISPC_GLOBAL_ALPHA		DISPC_REG(0x0074)
++#define DISPC_SIZE_DIG			DISPC_REG(0x0078)
++#define DISPC_SIZE_LCD			DISPC_REG(0x007C)
++
++/* DISPC GFX plane */
++#define DISPC_GFX_BA0			DISPC_REG(0x0080)
++#define DISPC_GFX_BA1			DISPC_REG(0x0084)
++#define DISPC_GFX_POSITION		DISPC_REG(0x0088)
++#define DISPC_GFX_SIZE			DISPC_REG(0x008C)
++#define DISPC_GFX_ATTRIBUTES		DISPC_REG(0x00A0)
++#define DISPC_GFX_FIFO_THRESHOLD	DISPC_REG(0x00A4)
++#define DISPC_GFX_FIFO_SIZE_STATUS	DISPC_REG(0x00A8)
++#define DISPC_GFX_ROW_INC		DISPC_REG(0x00AC)
++#define DISPC_GFX_PIXEL_INC		DISPC_REG(0x00B0)
++#define DISPC_GFX_WINDOW_SKIP		DISPC_REG(0x00B4)
++#define DISPC_GFX_TABLE_BA		DISPC_REG(0x00B8)
++
++#define DISPC_DATA_CYCLE1		DISPC_REG(0x01D4)
++#define DISPC_DATA_CYCLE2		DISPC_REG(0x01D8)
++#define DISPC_DATA_CYCLE3		DISPC_REG(0x01DC)
++
++#define DISPC_CPR_COEF_R		DISPC_REG(0x0220)
++#define DISPC_CPR_COEF_G		DISPC_REG(0x0224)
++#define DISPC_CPR_COEF_B		DISPC_REG(0x0228)
++
++#define DISPC_GFX_PRELOAD		DISPC_REG(0x022C)
++
++/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
++#define DISPC_VID_REG(n, idx)		DISPC_REG(0x00BC + (n)*0x90 + idx)
++
++#define DISPC_VID_BA0(n)		DISPC_VID_REG(n, 0x0000)
++#define DISPC_VID_BA1(n)		DISPC_VID_REG(n, 0x0004)
++#define DISPC_VID_POSITION(n)		DISPC_VID_REG(n, 0x0008)
++#define DISPC_VID_SIZE(n)		DISPC_VID_REG(n, 0x000C)
++#define DISPC_VID_ATTRIBUTES(n)		DISPC_VID_REG(n, 0x0010)
++#define DISPC_VID_FIFO_THRESHOLD(n)	DISPC_VID_REG(n, 0x0014)
++#define DISPC_VID_FIFO_SIZE_STATUS(n)	DISPC_VID_REG(n, 0x0018)
++#define DISPC_VID_ROW_INC(n)		DISPC_VID_REG(n, 0x001C)
++#define DISPC_VID_PIXEL_INC(n)		DISPC_VID_REG(n, 0x0020)
++#define DISPC_VID_FIR(n)		DISPC_VID_REG(n, 0x0024)
++#define DISPC_VID_PICTURE_SIZE(n)	DISPC_VID_REG(n, 0x0028)
++#define DISPC_VID_ACCU0(n)		DISPC_VID_REG(n, 0x002C)
++#define DISPC_VID_ACCU1(n)		DISPC_VID_REG(n, 0x0030)
++
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_H(n, i)	DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_HV(n, i)	DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
++/* coef index i = {0, 1, 2, 3, 4} */
++#define DISPC_VID_CONV_COEF(n, i)	DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_V(n, i)	DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
++
++#define DISPC_VID_PRELOAD(n)		DISPC_REG(0x230 + (n)*0x04)
++
++
++#define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
++					 DISPC_IRQ_OCP_ERR | \
++					 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
++					 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
++					 DISPC_IRQ_SYNC_LOST | \
++					 DISPC_IRQ_SYNC_LOST_DIGIT)
++
++#define DISPC_MAX_NR_ISRS		8
++
++static struct {
++	omap_dispc_isr_t	isr;
++	void			*arg;
++	u32			mask;
++} registered_isr[DISPC_MAX_NR_ISRS];
++
++#define REG_GET(idx, start, end) \
++	FLD_GET(dispc_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end)				\
++	dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
++
++static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
++	DISPC_VID_ATTRIBUTES(0),
++	DISPC_VID_ATTRIBUTES(1) };
++
++static struct {
++	void __iomem    *base;
++
++	struct clk	*dpll4_m4_ck;
++
++	spinlock_t	irq_lock;
++
++	unsigned long	cache_req_pck;
++	unsigned long	cache_prate;
++	struct dispc_clock_info cache_cinfo;
++
++	u32		ctx[DISPC_SZ_REGS / sizeof(u32)];
++} dispc;
++
++static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
++{
++	__raw_writel(val, dispc.base + idx.idx);
++}
++
++static inline u32 dispc_read_reg(const struct dispc_reg idx)
++{
++	return __raw_readl(dispc.base + idx.idx);
++}
++
++#define SR(reg) \
++	dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
++#define RR(reg) \
++	dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
++
++void dispc_save_context(void)
++{
++	if (cpu_is_omap24xx())
++		return;
++
++	SR(SYSCONFIG);
++	SR(IRQENABLE);
++	SR(CONTROL);
++	SR(CONFIG);
++	SR(DEFAULT_COLOR0);
++	SR(DEFAULT_COLOR1);
++	SR(TRANS_COLOR0);
++	SR(TRANS_COLOR1);
++	SR(LINE_NUMBER);
++	SR(TIMING_H);
++	SR(TIMING_V);
++	SR(POL_FREQ);
++	SR(DIVISOR);
++	SR(GLOBAL_ALPHA);
++	SR(SIZE_DIG);
++	SR(SIZE_LCD);
++
++	SR(GFX_BA0);
++	SR(GFX_BA1);
++	SR(GFX_POSITION);
++	SR(GFX_SIZE);
++	SR(GFX_ATTRIBUTES);
++	SR(GFX_FIFO_THRESHOLD);
++	SR(GFX_ROW_INC);
++	SR(GFX_PIXEL_INC);
++	SR(GFX_WINDOW_SKIP);
++	SR(GFX_TABLE_BA);
++
++	SR(DATA_CYCLE1);
++	SR(DATA_CYCLE2);
++	SR(DATA_CYCLE3);
++
++	SR(CPR_COEF_R);
++	SR(CPR_COEF_G);
++	SR(CPR_COEF_B);
++
++	SR(GFX_PRELOAD);
++
++	/* VID1 */
++	SR(VID_BA0(0));
++	SR(VID_BA1(0));
++	SR(VID_POSITION(0));
++	SR(VID_SIZE(0));
++	SR(VID_ATTRIBUTES(0));
++	SR(VID_FIFO_THRESHOLD(0));
++	SR(VID_ROW_INC(0));
++	SR(VID_PIXEL_INC(0));
++	SR(VID_FIR(0));
++	SR(VID_PICTURE_SIZE(0));
++	SR(VID_ACCU0(0));
++	SR(VID_ACCU1(0));
++
++	SR(VID_FIR_COEF_H(0, 0));
++	SR(VID_FIR_COEF_H(0, 1));
++	SR(VID_FIR_COEF_H(0, 2));
++	SR(VID_FIR_COEF_H(0, 3));
++	SR(VID_FIR_COEF_H(0, 4));
++	SR(VID_FIR_COEF_H(0, 5));
++	SR(VID_FIR_COEF_H(0, 6));
++	SR(VID_FIR_COEF_H(0, 7));
++
++	SR(VID_FIR_COEF_HV(0, 0));
++	SR(VID_FIR_COEF_HV(0, 1));
++	SR(VID_FIR_COEF_HV(0, 2));
++	SR(VID_FIR_COEF_HV(0, 3));
++	SR(VID_FIR_COEF_HV(0, 4));
++	SR(VID_FIR_COEF_HV(0, 5));
++	SR(VID_FIR_COEF_HV(0, 6));
++	SR(VID_FIR_COEF_HV(0, 7));
++
++	SR(VID_CONV_COEF(0, 0));
++	SR(VID_CONV_COEF(0, 1));
++	SR(VID_CONV_COEF(0, 2));
++	SR(VID_CONV_COEF(0, 3));
++	SR(VID_CONV_COEF(0, 4));
++
++	SR(VID_FIR_COEF_V(0, 0));
++	SR(VID_FIR_COEF_V(0, 1));
++	SR(VID_FIR_COEF_V(0, 2));
++	SR(VID_FIR_COEF_V(0, 3));
++	SR(VID_FIR_COEF_V(0, 4));
++	SR(VID_FIR_COEF_V(0, 5));
++	SR(VID_FIR_COEF_V(0, 6));
++	SR(VID_FIR_COEF_V(0, 7));
++
++	SR(VID_PRELOAD(0));
++
++	/* VID2 */
++	SR(VID_BA0(1));
++	SR(VID_BA1(1));
++	SR(VID_POSITION(1));
++	SR(VID_SIZE(1));
++	SR(VID_ATTRIBUTES(1));
++	SR(VID_FIFO_THRESHOLD(1));
++	SR(VID_ROW_INC(1));
++	SR(VID_PIXEL_INC(1));
++	SR(VID_FIR(1));
++	SR(VID_PICTURE_SIZE(1));
++	SR(VID_ACCU0(1));
++	SR(VID_ACCU1(1));
++
++	SR(VID_FIR_COEF_H(1, 0));
++	SR(VID_FIR_COEF_H(1, 1));
++	SR(VID_FIR_COEF_H(1, 2));
++	SR(VID_FIR_COEF_H(1, 3));
++	SR(VID_FIR_COEF_H(1, 4));
++	SR(VID_FIR_COEF_H(1, 5));
++	SR(VID_FIR_COEF_H(1, 6));
++	SR(VID_FIR_COEF_H(1, 7));
++
++	SR(VID_FIR_COEF_HV(1, 0));
++	SR(VID_FIR_COEF_HV(1, 1));
++	SR(VID_FIR_COEF_HV(1, 2));
++	SR(VID_FIR_COEF_HV(1, 3));
++	SR(VID_FIR_COEF_HV(1, 4));
++	SR(VID_FIR_COEF_HV(1, 5));
++	SR(VID_FIR_COEF_HV(1, 6));
++	SR(VID_FIR_COEF_HV(1, 7));
++
++	SR(VID_CONV_COEF(1, 0));
++	SR(VID_CONV_COEF(1, 1));
++	SR(VID_CONV_COEF(1, 2));
++	SR(VID_CONV_COEF(1, 3));
++	SR(VID_CONV_COEF(1, 4));
++
++	SR(VID_FIR_COEF_V(1, 0));
++	SR(VID_FIR_COEF_V(1, 1));
++	SR(VID_FIR_COEF_V(1, 2));
++	SR(VID_FIR_COEF_V(1, 3));
++	SR(VID_FIR_COEF_V(1, 4));
++	SR(VID_FIR_COEF_V(1, 5));
++	SR(VID_FIR_COEF_V(1, 6));
++	SR(VID_FIR_COEF_V(1, 7));
++
++	SR(VID_PRELOAD(1));
++}
++
++void dispc_restore_context(void)
++{
++	RR(SYSCONFIG);
++	RR(IRQENABLE);
++	/*RR(CONTROL);*/
++	RR(CONFIG);
++	RR(DEFAULT_COLOR0);
++	RR(DEFAULT_COLOR1);
++	RR(TRANS_COLOR0);
++	RR(TRANS_COLOR1);
++	RR(LINE_NUMBER);
++	RR(TIMING_H);
++	RR(TIMING_V);
++	RR(POL_FREQ);
++	RR(DIVISOR);
++	RR(GLOBAL_ALPHA);
++	RR(SIZE_DIG);
++	RR(SIZE_LCD);
++
++	RR(GFX_BA0);
++	RR(GFX_BA1);
++	RR(GFX_POSITION);
++	RR(GFX_SIZE);
++	RR(GFX_ATTRIBUTES);
++	RR(GFX_FIFO_THRESHOLD);
++	RR(GFX_ROW_INC);
++	RR(GFX_PIXEL_INC);
++	RR(GFX_WINDOW_SKIP);
++	RR(GFX_TABLE_BA);
++
++	RR(DATA_CYCLE1);
++	RR(DATA_CYCLE2);
++	RR(DATA_CYCLE3);
++
++	RR(CPR_COEF_R);
++	RR(CPR_COEF_G);
++	RR(CPR_COEF_B);
++
++	RR(GFX_PRELOAD);
++
++	/* VID1 */
++	RR(VID_BA0(0));
++	RR(VID_BA1(0));
++	RR(VID_POSITION(0));
++	RR(VID_SIZE(0));
++	RR(VID_ATTRIBUTES(0));
++	RR(VID_FIFO_THRESHOLD(0));
++	RR(VID_ROW_INC(0));
++	RR(VID_PIXEL_INC(0));
++	RR(VID_FIR(0));
++	RR(VID_PICTURE_SIZE(0));
++	RR(VID_ACCU0(0));
++	RR(VID_ACCU1(0));
++
++	RR(VID_FIR_COEF_H(0, 0));
++	RR(VID_FIR_COEF_H(0, 1));
++	RR(VID_FIR_COEF_H(0, 2));
++	RR(VID_FIR_COEF_H(0, 3));
++	RR(VID_FIR_COEF_H(0, 4));
++	RR(VID_FIR_COEF_H(0, 5));
++	RR(VID_FIR_COEF_H(0, 6));
++	RR(VID_FIR_COEF_H(0, 7));
++
++	RR(VID_FIR_COEF_HV(0, 0));
++	RR(VID_FIR_COEF_HV(0, 1));
++	RR(VID_FIR_COEF_HV(0, 2));
++	RR(VID_FIR_COEF_HV(0, 3));
++	RR(VID_FIR_COEF_HV(0, 4));
++	RR(VID_FIR_COEF_HV(0, 5));
++	RR(VID_FIR_COEF_HV(0, 6));
++	RR(VID_FIR_COEF_HV(0, 7));
++
++	RR(VID_CONV_COEF(0, 0));
++	RR(VID_CONV_COEF(0, 1));
++	RR(VID_CONV_COEF(0, 2));
++	RR(VID_CONV_COEF(0, 3));
++	RR(VID_CONV_COEF(0, 4));
++
++	RR(VID_FIR_COEF_V(0, 0));
++	RR(VID_FIR_COEF_V(0, 1));
++	RR(VID_FIR_COEF_V(0, 2));
++	RR(VID_FIR_COEF_V(0, 3));
++	RR(VID_FIR_COEF_V(0, 4));
++	RR(VID_FIR_COEF_V(0, 5));
++	RR(VID_FIR_COEF_V(0, 6));
++	RR(VID_FIR_COEF_V(0, 7));
++
++	RR(VID_PRELOAD(0));
++
++	/* VID2 */
++	RR(VID_BA0(1));
++	RR(VID_BA1(1));
++	RR(VID_POSITION(1));
++	RR(VID_SIZE(1));
++	RR(VID_ATTRIBUTES(1));
++	RR(VID_FIFO_THRESHOLD(1));
++	RR(VID_ROW_INC(1));
++	RR(VID_PIXEL_INC(1));
++	RR(VID_FIR(1));
++	RR(VID_PICTURE_SIZE(1));
++	RR(VID_ACCU0(1));
++	RR(VID_ACCU1(1));
++
++	RR(VID_FIR_COEF_H(1, 0));
++	RR(VID_FIR_COEF_H(1, 1));
++	RR(VID_FIR_COEF_H(1, 2));
++	RR(VID_FIR_COEF_H(1, 3));
++	RR(VID_FIR_COEF_H(1, 4));
++	RR(VID_FIR_COEF_H(1, 5));
++	RR(VID_FIR_COEF_H(1, 6));
++	RR(VID_FIR_COEF_H(1, 7));
++
++	RR(VID_FIR_COEF_HV(1, 0));
++	RR(VID_FIR_COEF_HV(1, 1));
++	RR(VID_FIR_COEF_HV(1, 2));
++	RR(VID_FIR_COEF_HV(1, 3));
++	RR(VID_FIR_COEF_HV(1, 4));
++	RR(VID_FIR_COEF_HV(1, 5));
++	RR(VID_FIR_COEF_HV(1, 6));
++	RR(VID_FIR_COEF_HV(1, 7));
++
++	RR(VID_CONV_COEF(1, 0));
++	RR(VID_CONV_COEF(1, 1));
++	RR(VID_CONV_COEF(1, 2));
++	RR(VID_CONV_COEF(1, 3));
++	RR(VID_CONV_COEF(1, 4));
++
++	RR(VID_FIR_COEF_V(1, 0));
++	RR(VID_FIR_COEF_V(1, 1));
++	RR(VID_FIR_COEF_V(1, 2));
++	RR(VID_FIR_COEF_V(1, 3));
++	RR(VID_FIR_COEF_V(1, 4));
++	RR(VID_FIR_COEF_V(1, 5));
++	RR(VID_FIR_COEF_V(1, 6));
++	RR(VID_FIR_COEF_V(1, 7));
++
++	RR(VID_PRELOAD(1));
++
++	/* enable last, because LCD & DIGIT enable are here */
++	RR(CONTROL);
++}
++
++#undef SR
++#undef RR
++
++static inline void enable_clocks(int enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	else
++		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++void dispc_go(enum omap_channel channel)
++{
++	int bit;
++	unsigned long tmo;
++
++	enable_clocks(1);
++
++	if (channel == OMAP_DSS_CHANNEL_LCD)
++		bit = 0; /* LCDENABLE */
++	else
++		bit = 1; /* DIGITALENABLE */
++
++	/* if the channel is not enabled, we don't need GO */
++	if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
++		goto end;
++
++	if (channel == OMAP_DSS_CHANNEL_LCD)
++		bit = 5; /* GOLCD */
++	else
++		bit = 6; /* GODIGIT */
++
++	tmo = jiffies + msecs_to_jiffies(200);
++	while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
++		if (time_after(jiffies, tmo)) {
++			DSSERR("timeout waiting GO flag\n");
++			goto end;
++		}
++		cpu_relax();
++	}
++
++	DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
++
++	REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
++end:
++	enable_clocks(0);
++}
++
++static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
++{
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
++}
++
++static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
++{
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
++}
++
++
++static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
++		int vscaleup)
++{
++	/* Coefficients for horizontal up-sampling */
++	const u32 coef_hup[8] = {
++		0x00800000,
++		0x0D7CF800,
++		0x1E70F5FF,
++		0x335FF5FE,
++		0xF74949F7,
++		0xF55F33FB,
++		0xF5701EFE,
++		0xF87C0DFF,
++	};
++
++	/* Coefficients for horizontal down-sampling */
++	const u32 coef_hdown[8] = {
++		0x24382400,
++		0x28371FFE,
++		0x2C361BFB,
++		0x303516F9,
++		0x11343311,
++		0x1635300C,
++		0x1B362C08,
++		0x1F372804,
++	};
++
++	/* Coefficients for horizontal and vertical up-sampling */
++	const u32 coef_hvup[8] = {
++		0x00800000,
++		0x037B02FF,
++		0x0C6F05FE,
++		0x205907FB,
++		0x00404000,
++		0x075920FE,
++		0x056F0CFF,
++		0x027B0300,
++	};
++
++	/* Coefficients for horizontal and vertical down-sampling */
++	const u32 coef_hvdown[8] = {
++		0x24382400,
++		0x28391F04,
++		0x2D381B08,
++		0x3237170C,
++		0x123737F7,
++		0x173732F9,
++		0x1B382DFB,
++		0x1F3928FE,
++	};
++
++	const u32 *h_coef;
++	const u32 *hv_coef;
++	const u32 *hv_coef_mod;
++	int i;
++
++	if (hscaleup)
++		h_coef = coef_hup;
++	else
++		h_coef = coef_hdown;
++
++	if (vscaleup) {
++		hv_coef = coef_hvup;
++
++		if (hscaleup)
++			hv_coef_mod = NULL;
++		else
++			hv_coef_mod = coef_hvdown;
++	} else {
++		hv_coef = coef_hvdown;
++
++		if (hscaleup)
++			hv_coef_mod = coef_hvup;
++		else
++			hv_coef_mod = NULL;
++	}
++
++	for (i = 0; i < 8; i++) {
++		u32 h, hv;
++
++		h = h_coef[i];
++
++		hv = hv_coef[i];
++
++		if (hv_coef_mod) {
++			hv &= 0xffffff00;
++			hv |= (hv_coef_mod[i] & 0xff);
++		}
++
++		_dispc_write_firh_reg(plane, i, h);
++		_dispc_write_firhv_reg(plane, i, hv);
++	}
++}
++
++static void _dispc_setup_color_conv_coef(void)
++{
++	const struct color_conv_coef {
++		int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
++		int  full_range;
++	}  ctbl_bt601_5 = {
++		298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
++	};
++
++	const struct color_conv_coef *ct;
++
++#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
++
++	ct = &ctbl_bt601_5;
++
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,	 ct->rcb));
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
++	dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
++
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,	 ct->rcb));
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
++	dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
++
++#undef CVAL
++
++	REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
++	REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
++}
++
++
++static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
++{
++	const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
++		DISPC_VID_BA0(0),
++		DISPC_VID_BA0(1) };
++
++	dispc_write_reg(ba0_reg[plane], paddr);
++}
++
++static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
++{
++	const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
++				      DISPC_VID_BA1(0),
++				      DISPC_VID_BA1(1) };
++
++	dispc_write_reg(ba1_reg[plane], paddr);
++}
++
++static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
++{
++	const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
++				      DISPC_VID_POSITION(0),
++				      DISPC_VID_POSITION(1) };
++
++	u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
++	dispc_write_reg(pos_reg[plane], val);
++}
++
++static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
++{
++	const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
++				      DISPC_VID_PICTURE_SIZE(0),
++				      DISPC_VID_PICTURE_SIZE(1) };
++	u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++	dispc_write_reg(siz_reg[plane], val);
++}
++
++static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
++{
++	u32 val;
++	const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
++				      DISPC_VID_SIZE(1) };
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++	dispc_write_reg(vsi_reg[plane-1], val);
++}
++
++static void _dispc_set_row_inc(enum omap_plane plane, int inc)
++{
++	const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
++				     DISPC_VID_ROW_INC(0),
++				     DISPC_VID_ROW_INC(1) };
++
++	dispc_write_reg(ri_reg[plane], inc);
++}
++
++static void _dispc_set_color_mode(enum omap_plane plane,
++		enum omap_color_mode color_mode)
++{
++	u32 m = 0;
++
++	switch (color_mode) {
++	case OMAP_DSS_COLOR_CLUT1:
++		m = 0x0; break;
++	case OMAP_DSS_COLOR_CLUT2:
++		m = 0x1; break;
++	case OMAP_DSS_COLOR_CLUT4:
++		m = 0x2; break;
++	case OMAP_DSS_COLOR_CLUT8:
++		m = 0x3; break;
++	case OMAP_DSS_COLOR_RGB12U:
++		m = 0x4; break;
++	case OMAP_DSS_COLOR_ARGB16:
++		m = 0x5; break;
++	case OMAP_DSS_COLOR_RGB16:
++		m = 0x6; break;
++	case OMAP_DSS_COLOR_RGB24U:
++		m = 0x8; break;
++	case OMAP_DSS_COLOR_RGB24P:
++		m = 0x9; break;
++	case OMAP_DSS_COLOR_YUV2:
++		m = 0xa; break;
++	case OMAP_DSS_COLOR_UYVY:
++		m = 0xb; break;
++	case OMAP_DSS_COLOR_ARGB32:
++		m = 0xc; break;
++	case OMAP_DSS_COLOR_RGBA32:
++		m = 0xd; break;
++	case OMAP_DSS_COLOR_RGBX32:
++		m = 0xe; break;
++	default:
++		BUG(); break;
++	}
++
++	REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
++}
++
++static void _dispc_set_channel_out(enum omap_plane plane,
++		enum omap_channel channel)
++{
++	int shift;
++	u32 val;
++
++	switch (plane) {
++	case OMAP_DSS_GFX:
++		shift = 8;
++		break;
++	case OMAP_DSS_VIDEO1:
++	case OMAP_DSS_VIDEO2:
++		shift = 16;
++		break;
++	default:
++		BUG();
++		return;
++	}
++
++	val = dispc_read_reg(dispc_reg_att[plane]);
++	val = FLD_MOD(val, channel, shift, shift);
++	dispc_write_reg(dispc_reg_att[plane], val);
++}
++
++void dispc_set_burst_size(enum omap_plane plane,
++		enum omap_burst_size burst_size)
++{
++	int shift;
++	u32 val;
++
++	enable_clocks(1);
++
++	switch (plane) {
++	case OMAP_DSS_GFX:
++		shift = 6;
++		break;
++	case OMAP_DSS_VIDEO1:
++	case OMAP_DSS_VIDEO2:
++		shift = 14;
++		break;
++	default:
++		BUG();
++		return;
++	}
++
++	val = dispc_read_reg(dispc_reg_att[plane]);
++	val = FLD_MOD(val, burst_size, shift+1, shift);
++	dispc_write_reg(dispc_reg_att[plane], val);
++
++	enable_clocks(0);
++}
++
++static void _dispc_set_vid_color_conv(enum omap_plane plane, int enable)
++{
++	u32 val;
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = dispc_read_reg(dispc_reg_att[plane]);
++	val = FLD_MOD(val, enable, 9, 9);
++	dispc_write_reg(dispc_reg_att[plane], val);
++}
++
++void dispc_set_lcd_size(int width, int height)
++{
++	u32 val;
++	BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
++	val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++	enable_clocks(1);
++	dispc_write_reg(DISPC_SIZE_LCD, val);
++	enable_clocks(0);
++}
++
++void dispc_set_digit_size(int width, int height)
++{
++	u32 val;
++	BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
++	val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++	enable_clocks(1);
++	dispc_write_reg(DISPC_SIZE_DIG, val);
++	enable_clocks(0);
++}
++
++u32 dispc_get_plane_fifo_size(enum omap_plane plane)
++{
++	const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
++				      DISPC_VID_FIFO_SIZE_STATUS(0),
++				      DISPC_VID_FIFO_SIZE_STATUS(1) };
++	u32 size;
++
++	enable_clocks(1);
++
++	if (cpu_is_omap24xx())
++		size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
++	else if (cpu_is_omap34xx())
++		size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
++	else
++		BUG();
++
++	enable_clocks(0);
++
++	return size;
++}
++
++void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
++{
++	const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
++				       DISPC_VID_FIFO_THRESHOLD(0),
++				       DISPC_VID_FIFO_THRESHOLD(1) };
++	const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
++				      DISPC_VID_FIFO_SIZE_STATUS(0),
++				      DISPC_VID_FIFO_SIZE_STATUS(1) };
++	u32 size;
++
++	enable_clocks(1);
++
++	if (cpu_is_omap24xx())
++		size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
++	else if (cpu_is_omap34xx())
++		size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
++	else
++		BUG();
++
++	BUG_ON(low > size || high > size);
++
++	DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
++			plane, size,
++			REG_GET(ftrs_reg[plane], 11, 0),
++			REG_GET(ftrs_reg[plane], 27, 16),
++			low, high);
++
++	if (cpu_is_omap24xx())
++		dispc_write_reg(ftrs_reg[plane],
++				FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
++	else
++		dispc_write_reg(ftrs_reg[plane],
++				FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
++
++	enable_clocks(0);
++}
++
++static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
++{
++	u32 val;
++	const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
++				      DISPC_VID_FIR(1) };
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
++	dispc_write_reg(fir_reg[plane-1], val);
++}
++
++static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
++{
++	u32 val;
++	const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
++				      DISPC_VID_ACCU0(1) };
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
++	dispc_write_reg(ac0_reg[plane-1], val);
++}
++
++static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
++{
++	u32 val;
++	const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
++				      DISPC_VID_ACCU1(1) };
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
++	dispc_write_reg(ac1_reg[plane-1], val);
++}
++
++
++static void _dispc_set_scaling(enum omap_plane plane,
++			       int orig_width, int orig_height,
++			       int out_width, int out_height,
++			       int ilace)
++{
++	int fir_hinc;
++	int fir_vinc;
++	int hscaleup, vscaleup;
++	int fieldmode = 0;
++	int accu0 = 0;
++	int accu1 = 0;
++	u32 l;
++
++	BUG_ON(plane == OMAP_DSS_GFX);
++
++	hscaleup = orig_width <= out_width;
++	vscaleup = orig_height <= out_height;
++
++	_dispc_set_scale_coef(plane, hscaleup, vscaleup);
++
++	if (!orig_width || orig_width == out_width)
++		fir_hinc = 0;
++	else
++		fir_hinc = 1024 * orig_width / out_width;
++
++	if (!orig_height || orig_height == out_height)
++		fir_vinc = 0;
++	else
++		fir_vinc = 1024 * orig_height / out_height;
++
++	_dispc_set_fir(plane, fir_hinc, fir_vinc);
++
++	l = dispc_read_reg(dispc_reg_att[plane]);
++	l &= ~(0x0f << 5);
++
++	l |= fir_hinc ? (1 << 5) : 0;
++	l |= fir_vinc ? (1 << 6) : 0;
++
++	l |= hscaleup ? 0 : (1 << 7);
++	l |= vscaleup ? 0 : (1 << 8);
++
++	dispc_write_reg(dispc_reg_att[plane], l);
++
++	if (ilace) {
++		if (fieldmode) {
++			accu0 = fir_vinc / 2;
++			accu1 = 0;
++		} else {
++			accu0 = 0;
++			accu1 = fir_vinc / 2;
++			if (accu1 >= 1024/2) {
++				accu0 = 1024/2;
++				accu1 -= accu0;
++			}
++		}
++	}
++
++	_dispc_set_vid_accu0(plane, 0, accu0);
++	_dispc_set_vid_accu1(plane, 0, accu1);
++}
++
++static int _dispc_setup_plane(enum omap_plane plane,
++		enum omap_channel channel_out,
++		u32 paddr, int screen_width,
++		int pos_x, int pos_y,
++		int width, int height,
++		int out_width, int out_height,
++		enum omap_color_mode color_mode,
++		int ilace)
++{
++	int fieldmode = 0;
++	int bpp;
++	int cconv;
++	int scaling = 0;
++
++	if (plane == OMAP_DSS_GFX) {
++		if (width != out_width || height != out_height)
++			return -EINVAL;
++	} else {
++		/* video plane */
++		if (width != out_width || height != out_height)
++			scaling = 1;
++
++		if (out_width < width/2 ||
++		   out_width > width*8)
++			return -EINVAL;
++
++		if (out_height < height/2 ||
++		   out_height > height*8)
++			return -EINVAL;
++	}
++
++
++	switch (color_mode) {
++	case OMAP_DSS_COLOR_RGB16:
++		bpp = 16;
++		cconv = 0;
++		break;
++
++	case OMAP_DSS_COLOR_RGB24P:
++		bpp = 24;
++		cconv = 0;
++		break;
++
++	case OMAP_DSS_COLOR_RGB24U:
++		bpp = 32;
++		cconv = 0;
++		break;
++
++	case OMAP_DSS_COLOR_YUV2:
++	case OMAP_DSS_COLOR_UYVY:
++		BUG_ON(plane == OMAP_DSS_GFX);
++		bpp = 16;
++		cconv = 1;
++		break;
++
++	default:
++		BUG();
++		return 1;
++	}
++
++	if (ilace) {
++		if (height == out_height || height > out_height)
++			fieldmode = 1;
++	}
++
++	if (fieldmode)
++		height /= 2;
++
++	if (ilace)
++		out_height /= 2;
++
++	if (plane != OMAP_DSS_GFX)
++		_dispc_set_scaling(plane, width, height,
++				   out_width, out_height,
++				   ilace);
++
++	/* attributes */
++	_dispc_set_channel_out(plane, channel_out);
++	_dispc_set_color_mode(plane, color_mode);
++	if (plane != OMAP_DSS_GFX)
++		_dispc_set_vid_color_conv(plane, cconv);
++
++	/* */
++
++	_dispc_set_plane_ba0(plane, paddr);
++
++	if (fieldmode)
++		_dispc_set_plane_ba1(plane, paddr + screen_width * bpp/8);
++	else
++		_dispc_set_plane_ba1(plane, paddr);
++
++
++	_dispc_set_plane_pos(plane, pos_x, pos_y);
++
++	_dispc_set_pic_size(plane, width, height);
++
++	if (plane != OMAP_DSS_GFX)
++		_dispc_set_vid_size(plane, out_width, out_height);
++
++	_dispc_set_row_inc(plane,
++			   (screen_width - width) * bpp / 8 +
++			   (fieldmode ? screen_width * bpp / 8 : 0) +
++			   1);
++
++	return 0;
++}
++
++static void _dispc_enable_plane(enum omap_plane plane, int enable)
++{
++	REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
++}
++
++
++void dispc_enable_lcd_out(int enable)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
++	enable_clocks(0);
++}
++
++void dispc_enable_digit_out(int enable)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
++	enable_clocks(0);
++}
++
++void dispc_lcd_enable_signal_polarity(int act_high)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
++	enable_clocks(0);
++}
++
++void dispc_lcd_enable_signal(int enable)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
++	enable_clocks(0);
++}
++
++void dispc_pck_free_enable(int enable)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
++	enable_clocks(0);
++}
++
++void dispc_enable_fifohandcheck(int enable)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
++	enable_clocks(0);
++}
++
++
++void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
++{
++	int mode;
++
++	switch (type) {
++	case OMAP_DSS_LCD_DISPLAY_STN:
++		mode = 0;
++		break;
++
++	case OMAP_DSS_LCD_DISPLAY_TFT:
++		mode = 1;
++		break;
++
++	default:
++		BUG();
++		return;
++	}
++
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
++	enable_clocks(0);
++}
++
++void dispc_set_loadmode(enum omap_dss_load_mode mode)
++{
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
++	enable_clocks(0);
++}
++
++
++void omap_dispc_set_default_color(enum omap_channel channel, u32 color)
++{
++	const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
++				DISPC_DEFAULT_COLOR1 };
++
++	enable_clocks(1);
++	dispc_write_reg(def_reg[channel], color);
++	enable_clocks(0);
++}
++
++void omap_dispc_set_trans_key(enum omap_channel ch,
++		enum omap_dss_color_key_type type,
++		u32 trans_key)
++{
++	const struct dispc_reg tr_reg[] = {
++		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
++
++	enable_clocks(1);
++	if (ch == OMAP_DSS_CHANNEL_LCD)
++		REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
++	else /* OMAP_DSS_CHANNEL_DIGIT */
++		REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
++
++	dispc_write_reg(tr_reg[ch], trans_key);
++	enable_clocks(0);
++}
++
++void omap_dispc_enable_trans_key(enum omap_channel ch, int enable)
++{
++	enable_clocks(1);
++	if (ch == OMAP_DSS_CHANNEL_LCD)
++		REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
++	else /* OMAP_DSS_CHANNEL_DIGIT */
++		REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
++	enable_clocks(0);
++}
++
++void dispc_set_tft_data_lines(int data_lines)
++{
++	int code;
++
++	switch (data_lines) {
++	case 12:
++		code = 0;
++		break;
++	case 16:
++		code = 1;
++		break;
++	case 18:
++		code = 2;
++		break;
++	case 24:
++		code = 3;
++		break;
++	default:
++		BUG();
++		return;
++	}
++
++	enable_clocks(1);
++	REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
++	enable_clocks(0);
++}
++
++void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
++{
++	u32 l;
++	int stallmode;
++	int gpout0 = 1;
++	int gpout1;
++
++	switch (mode) {
++	case OMAP_DSS_PARALLELMODE_BYPASS:
++		stallmode = 0;
++		gpout1 = 1;
++		break;
++
++	case OMAP_DSS_PARALLELMODE_RFBI:
++		stallmode = 1;
++		gpout1 = 0;
++		break;
++
++	case OMAP_DSS_PARALLELMODE_DSI:
++		stallmode = 1;
++		gpout1 = 1;
++		break;
++
++	default:
++		BUG();
++		return;
++	}
++
++	enable_clocks(1);
++
++	l = dispc_read_reg(DISPC_CONTROL);
++
++	l = FLD_MOD(l, stallmode, 11, 11);
++	l = FLD_MOD(l, gpout0, 15, 15);
++	l = FLD_MOD(l, gpout1, 16, 16);
++
++	dispc_write_reg(DISPC_CONTROL, l);
++
++	enable_clocks(0);
++}
++
++static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
++				   int vsw, int vfp, int vbp)
++{
++	u32 timing_h, timing_v;
++
++	BUG_ON(hsw < 1 || hsw > 64);
++	BUG_ON(hfp < 1 || hfp > 256);
++	BUG_ON(hbp < 1 || hbp > 256);
++
++	BUG_ON(vsw < 1 || vsw > 64);
++	BUG_ON(vfp < 0 || vfp > 255);
++	BUG_ON(vbp < 0 || vbp > 255);
++
++	timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
++		FLD_VAL(hbp-1, 27, 20);
++
++	timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
++		FLD_VAL(vbp, 27, 20);
++
++	enable_clocks(1);
++	dispc_write_reg(DISPC_TIMING_H, timing_h);
++	dispc_write_reg(DISPC_TIMING_V, timing_v);
++	enable_clocks(0);
++}
++
++/* change name to mode? */
++void dispc_set_lcd_timings(struct omap_video_timings *timings)
++{
++	unsigned xtot, ytot;
++	unsigned long ht, vt;
++
++	_dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
++			timings->vsw, timings->vfp, timings->vbp);
++
++	dispc_set_lcd_size(timings->x_res, timings->y_res);
++
++	xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
++	ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
++
++	ht = (timings->pixel_clock * 1000) / xtot;
++	vt = (timings->pixel_clock * 1000) / xtot / ytot;
++
++	DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
++	DSSDBG("pck %u\n", timings->pixel_clock);
++	DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
++			timings->hsw, timings->hfp, timings->hbp,
++			timings->vsw, timings->vfp, timings->vbp);
++
++	DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
++}
++
++void dispc_set_lcd_divisor(int lck_div, int pck_div)
++{
++	BUG_ON(lck_div < 1);
++	BUG_ON(pck_div < 2);
++
++	enable_clocks(1);
++	dispc_write_reg(DISPC_DIVISOR,
++			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
++	enable_clocks(0);
++}
++
++static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
++{
++	u32 l;
++	l = dispc_read_reg(DISPC_DIVISOR);
++	*lck_div = FLD_GET(l, 23, 16);
++	*pck_div = FLD_GET(l, 7, 0);
++}
++
++unsigned long dispc_fclk_rate(void)
++{
++	unsigned long r = 0;
++
++	if (dss_get_dispc_clk_source() == 0)
++		r = dss_clk_get_rate(DSS_CLK_FCK1);
++	else
++#ifdef CONFIG_OMAP2_DSS_DSI
++		r = dsi_get_dsi1_pll_rate();
++#else
++	BUG();
++#endif
++	return r;
++}
++
++unsigned long dispc_pclk_rate(void)
++{
++	int lcd, pcd;
++	unsigned long r;
++	u32 l;
++
++	l = dispc_read_reg(DISPC_DIVISOR);
++
++	lcd = FLD_GET(l, 23, 16);
++	pcd = FLD_GET(l, 7, 0);
++
++	r = dispc_fclk_rate();
++
++	return r / lcd / pcd;
++}
++
++ssize_t dispc_print_clocks(char *buf, ssize_t size)
++{
++	ssize_t l = 0;
++	int lcd, pcd;
++
++	enable_clocks(1);
++
++	dispc_get_lcd_divisor(&lcd, &pcd);
++
++	l += snprintf(buf + l, size - l, "- dispc -\n");
++
++	l += snprintf(buf + l, size - l, "dispc fclk source = %s\n",
++			dss_get_dispc_clk_source() == 0 ?
++			"dss1_alwon_fclk" : "dsi1_pll_fclk");
++
++	l += snprintf(buf + l, size - l,
++			"pixel clk = %lu / %d / %d = %lu\n",
++			dispc_fclk_rate(),
++			lcd, pcd,
++			dispc_pclk_rate());
++
++	enable_clocks(0);
++
++	return l;
++}
++
++static void _dispc_set_pol_freq(int onoff, int rf, int ieo, int ipc,
++				int ihs, int ivs, int acbi, int acb)
++{
++	u32 l = 0;
++
++	DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
++			onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
++
++	l |= FLD_VAL(onoff, 17, 17);
++	l |= FLD_VAL(rf, 16, 16);
++	l |= FLD_VAL(ieo, 15, 15);
++	l |= FLD_VAL(ipc, 14, 14);
++	l |= FLD_VAL(ihs, 13, 13);
++	l |= FLD_VAL(ivs, 12, 12);
++	l |= FLD_VAL(acbi, 11, 8);
++	l |= FLD_VAL(acb, 7, 0);
++
++	enable_clocks(1);
++	dispc_write_reg(DISPC_POL_FREQ, l);
++	enable_clocks(0);
++}
++
++void dispc_set_pol_freq(struct omap_panel *panel)
++{
++	_dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
++				 (panel->config & OMAP_DSS_LCD_RF) != 0,
++				 (panel->config & OMAP_DSS_LCD_IEO) != 0,
++				 (panel->config & OMAP_DSS_LCD_IPC) != 0,
++				 (panel->config & OMAP_DSS_LCD_IHS) != 0,
++				 (panel->config & OMAP_DSS_LCD_IVS) != 0,
++				 panel->acbi, panel->acb);
++}
++
++void find_lck_pck_divs(int is_tft, unsigned long req_pck, unsigned long fck,
++		int *lck_div, int *pck_div)
++{
++	int pcd_min = is_tft ? 2 : 3;
++	unsigned long best_pck;
++	int best_ld, cur_ld;
++	int best_pd, cur_pd;
++
++	best_pck = 0;
++	best_ld = 0;
++	best_pd = 0;
++
++	for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
++		unsigned long lck = fck / cur_ld;
++
++		for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
++			unsigned long pck = lck / cur_pd;
++			long old_delta = abs(best_pck - req_pck);
++			long new_delta = abs(pck - req_pck);
++
++			if (best_pck == 0 || new_delta < old_delta) {
++				best_pck = pck;
++				best_ld = cur_ld;
++				best_pd = cur_pd;
++
++				if (pck == req_pck)
++					goto found;
++			}
++
++			if (pck < req_pck)
++				break;
++		}
++
++		if (lck / pcd_min < req_pck)
++			break;
++	}
++
++found:
++	*lck_div = best_ld;
++	*pck_div = best_pd;
++}
++
++int dispc_calc_clock_div(int is_tft, unsigned long req_pck,
++		struct dispc_clock_info *cinfo)
++{
++	unsigned long prate;
++	struct dispc_clock_info cur, best;
++	int match = 0;
++	int min_fck_per_pck;
++
++	if (cpu_is_omap34xx())
++		prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++	else
++		prate = 0;
++
++	if (req_pck == dispc.cache_req_pck &&
++			((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
++			 dispc.cache_cinfo.fck == dss_clk_get_rate(DSS_CLK_FCK1))) {
++		DSSDBG("dispc clock info found from cache.\n");
++		*cinfo = dispc.cache_cinfo;
++		return 0;
++	}
++
++	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++	if (min_fck_per_pck &&
++		req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++		DSSERR("Requested pixel clock not possible with the current "
++				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++				"the constraint off.\n");
++		min_fck_per_pck = 0;
++	}
++
++retry:
++	memset(&cur, 0, sizeof(cur));
++	memset(&best, 0, sizeof(best));
++
++	if (cpu_is_omap24xx()) {
++		/* XXX can we change the clock on omap2? */
++		cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
++		cur.fck_div = 1;
++
++		match = 1;
++
++		find_lck_pck_divs(is_tft, req_pck, cur.fck,
++				&cur.lck_div, &cur.pck_div);
++
++		cur.lck = cur.fck / cur.lck_div;
++		cur.pck = cur.lck / cur.pck_div;
++
++		best = cur;
++
++		goto found;
++	} else if (cpu_is_omap34xx()) {
++		for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
++			cur.fck = prate / cur.fck_div * 2;
++
++			if (cur.fck > DISPC_MAX_FCK)
++				continue;
++
++			if (min_fck_per_pck &&
++					cur.fck < req_pck * min_fck_per_pck)
++				continue;
++
++			match = 1;
++
++			find_lck_pck_divs(is_tft, req_pck, cur.fck,
++					&cur.lck_div, &cur.pck_div);
++
++			cur.lck = cur.fck / cur.lck_div;
++			cur.pck = cur.lck / cur.pck_div;
++
++			if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
++				best = cur;
++
++				if (cur.pck == req_pck)
++					goto found;
++			}
++		}
++	} else {
++		BUG();
++	}
++
++found:
++	if (!match) {
++		if (min_fck_per_pck) {
++			DSSERR("Could not find suitable clock settings.\n"
++					"Turning FCK/PCK constraint off and"
++					"trying again.\n");
++			min_fck_per_pck = 0;
++			goto retry;
++		}
++
++		DSSERR("Could not find suitable clock settings.\n");
++
++		return -EINVAL;
++	}
++
++	if (cinfo)
++		*cinfo = best;
++
++	dispc.cache_req_pck = req_pck;
++	dispc.cache_prate = prate;
++	dispc.cache_cinfo = best;
++
++	return 0;
++}
++
++int dispc_set_clock_div(struct dispc_clock_info *cinfo)
++{
++	unsigned long prate;
++	int r;
++
++	if (cpu_is_omap34xx()) {
++		prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++		DSSDBG("dpll4_m4 = %ld\n", prate);
++	}
++
++	DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
++	DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
++	DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
++
++	if (cpu_is_omap34xx()) {
++		r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
++		if (r)
++			return r;
++	}
++
++	dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
++
++	return 0;
++}
++
++int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
++{
++	int i;
++	int ret = -EBUSY;
++	unsigned long flags;
++	u32 new_mask = 0;
++
++	if (isr == NULL)
++		return -EINVAL;
++
++	spin_lock_irqsave(&dispc.irq_lock, flags);
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		if (registered_isr[i].isr == isr) {
++			ret = -EINVAL;
++			break;
++		}
++
++		if (registered_isr[i].isr != NULL)
++			continue;
++
++		registered_isr[i].isr = isr;
++		registered_isr[i].arg = arg;
++		registered_isr[i].mask = mask;
++
++		enable_clocks(1);
++		new_mask = dispc_read_reg(DISPC_IRQENABLE);
++		new_mask |= mask;
++		dispc_write_reg(DISPC_IRQENABLE, new_mask);
++		enable_clocks(0);
++
++		ret = 0;
++		break;
++	}
++
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++	return ret;
++}
++EXPORT_SYMBOL(omap_dispc_register_isr);
++
++int omap_dispc_unregister_isr(omap_dispc_isr_t isr)
++{
++	int i, j;
++	unsigned long flags;
++	u32 new_mask = DISPC_IRQ_MASK_ERROR;
++	int ret = -EINVAL;
++
++	spin_lock_irqsave(&dispc.irq_lock, flags);
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		if (registered_isr[i].isr != isr)
++			continue;
++
++		registered_isr[i].isr = NULL;
++		registered_isr[i].arg = NULL;
++		registered_isr[i].mask = 0;
++
++		for (j = 0; j < DISPC_MAX_NR_ISRS; j++)
++			new_mask |= registered_isr[j].mask;
++
++		enable_clocks(1);
++		dispc_write_reg(DISPC_IRQENABLE, new_mask);
++		enable_clocks(0);
++
++		ret = 0;
++		break;
++	}
++
++	spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++	return ret;
++}
++EXPORT_SYMBOL(omap_dispc_unregister_isr);
++
++#ifdef DEBUG
++static void print_irq_status(u32 status)
++{
++	if ((status & DISPC_IRQ_MASK_ERROR) == 0)
++		return;
++
++	printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++	if (status & DISPC_IRQ_##x) \
++		printk(#x " ");
++	PIS(GFX_FIFO_UNDERFLOW);
++	PIS(OCP_ERR);
++	PIS(VID1_FIFO_UNDERFLOW);
++	PIS(VID2_FIFO_UNDERFLOW);
++	PIS(SYNC_LOST);
++	PIS(SYNC_LOST_DIGIT);
++#undef PIS
++
++	printk("\n");
++}
++#endif
++
++/* Called from dss.c. Note that we don't touch clocks here,
++ * but we presume they are on because we got an IRQ. However,
++ * an irq handler may turn the clocks off, so we may not have
++ * clock later in the function. */
++void dispc_irq_handler(void)
++{
++	int i;
++	u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
++	static int errors;
++	u32 handledirqs = 0;
++
++#ifdef DEBUG
++	if (dss_debug)
++		print_irq_status(irqstatus);
++#endif
++	/* Ack the interrupt. Do it here before clocks are possibly turned
++	 * off */
++	dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		if (!registered_isr[i].isr)
++			continue;
++		if (registered_isr[i].mask & irqstatus) {
++			registered_isr[i].isr(registered_isr[i].arg,
++					      irqstatus);
++			handledirqs |= registered_isr[i].mask;
++		}
++	}
++
++	if (irqstatus & ~handledirqs & DISPC_IRQ_MASK_ERROR) {
++		if (printk_ratelimit()) {
++			DSSERR("dispc irq error status %04x\n",
++			       irqstatus);
++		}
++		if (errors++ > 100) {
++			DSSERR("Excessive DISPC errors\n"
++					"Turning off lcd and digit\n");
++			dispc_enable_lcd_out(0);
++			dispc_enable_digit_out(0);
++		}
++	}
++
++}
++
++#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
++void dispc_fake_vsync_irq(void)
++{
++	u32 irqstatus = DISPC_IRQ_VSYNC;
++	int i;
++
++	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++		if (!registered_isr[i].isr)
++			continue;
++		if (registered_isr[i].mask & irqstatus)
++			registered_isr[i].isr(registered_isr[i].arg,
++					      irqstatus);
++	}
++}
++#endif
++
++static void _omap_dispc_initialize_irq(void)
++{
++	memset(registered_isr, 0, sizeof(registered_isr));
++
++	/* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
++	 * so clear it */
++	dispc_write_reg(DISPC_IRQSTATUS,
++			dispc_read_reg(DISPC_IRQSTATUS));
++
++	/* We'll handle these always */
++	dispc_write_reg(DISPC_IRQENABLE, DISPC_IRQ_MASK_ERROR);
++}
++
++static void _omap_dispc_initial_config(void)
++{
++	u32 l;
++
++	l = dispc_read_reg(DISPC_SYSCONFIG);
++	l = FLD_MOD(l, 2, 13, 12);	/* MIDLEMODE: smart standby */
++	l = FLD_MOD(l, 2, 4, 3);	/* SIDLEMODE: smart idle */
++	l = FLD_MOD(l, 1, 2, 2);	/* ENWAKEUP */
++	l = FLD_MOD(l, 1, 0, 0);	/* AUTOIDLE */
++	dispc_write_reg(DISPC_SYSCONFIG, l);
++
++	/* FUNCGATED */
++	REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
++
++	/* L3 firewall setting: enable access to OCM RAM */
++	__raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
++
++	_dispc_setup_color_conv_coef();
++
++	dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
++
++	/* Set logic clock to fck, pixel clock to fck/2 for now */
++	dispc_set_lcd_divisor(1, 2);
++}
++
++int dispc_init(void)
++{
++	u32 rev;
++
++	spin_lock_init(&dispc.irq_lock);
++
++	dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
++	if (!dispc.base) {
++		DSSERR("can't ioremap DISPC\n");
++		return -ENOMEM;
++	}
++
++	if (cpu_is_omap34xx()) {
++		dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
++		if (IS_ERR(dispc.dpll4_m4_ck)) {
++			DSSERR("Failed to get dpll4_m4_ck\n");
++			return -ENODEV;
++		}
++	}
++
++	enable_clocks(1);
++
++	_omap_dispc_initial_config();
++
++	_omap_dispc_initialize_irq();
++
++	dispc_save_context();
++
++	rev = dispc_read_reg(DISPC_REVISION);
++	printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
++	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++	enable_clocks(0);
++
++	return 0;
++}
++
++void dispc_exit(void)
++{
++	if (cpu_is_omap34xx())
++		clk_put(dispc.dpll4_m4_ck);
++	iounmap(dispc.base);
++}
++
++int dispc_enable_plane(enum omap_plane plane, int enable)
++{
++	DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
++
++	enable_clocks(1);
++	_dispc_enable_plane(plane, enable);
++	enable_clocks(0);
++
++	return 0;
++}
++
++int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
++		       u32 paddr, int screen_width,
++		       int pos_x, int pos_y,
++		       int width, int height,
++		       int out_width, int out_height,
++		       enum omap_color_mode color_mode,
++		       int ilace)
++{
++	int r = 0;
++
++	DSSDBG("dispc_setup_plane %d, %x, sw %d, %d,%d, %dx%d -> "
++	       "%dx%d, (ilace %d)\n",
++	       plane, paddr, screen_width, pos_x, pos_y,
++	       width, height,
++	       out_width, out_height,
++	       ilace);
++
++	enable_clocks(1);
++
++	r = _dispc_setup_plane(plane, channel_out,
++			   paddr, screen_width,
++			   pos_x, pos_y,
++			   width, height,
++			   out_width, out_height,
++			   color_mode, ilace);
++
++	enable_clocks(0);
++
++	return r;
++}
++
++static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
++				 int x2, int y2, int w2, int h2)
++{
++	if (x1 >= (x2+w2))
++		return 0;
++
++	if ((x1+w1) <= x2)
++		return 0;
++
++	if (y1 >= (y2+h2))
++		return 0;
++
++	if ((y1+h1) <= y2)
++		return 0;
++
++	return 1;
++}
++
++static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
++{
++	if (pi->width != pi->out_width)
++		return 1;
++
++	if (pi->height != pi->out_height)
++		return 1;
++
++	return 0;
++}
++
++/* returns the area that needs updating */
++void dispc_setup_partial_planes(struct omap_display *display,
++				    int *xi, int *yi, int *wi, int *hi)
++{
++	struct omap_overlay_manager *mgr;
++	int i;
++
++	int x, y, w, h;
++
++	x = *xi;
++	y = *yi;
++	w = *wi;
++	h = *hi;
++
++	DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
++		*xi, *yi, *wi, *hi);
++
++
++	mgr = display->manager;
++
++	if (!mgr) {
++		DSSDBG("no manager\n");
++		return;
++	}
++
++	for (i = 0; i < mgr->num_overlays; i++) {
++		struct omap_overlay *ovl;
++		struct omap_overlay_info *pi;
++		ovl = &mgr->overlays[i];
++
++		if (ovl->manager != mgr)
++			continue;
++
++		if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
++			continue;
++
++		pi = &ovl->info;
++
++		if (!pi->enabled)
++			continue;
++		/*
++		 * If the plane is intersecting and scaled, we
++		 * enlarge the update region to accomodate the
++		 * whole area
++		 */
++
++		if (dispc_is_intersecting(x, y, w, h,
++					  pi->pos_x, pi->pos_y,
++					  pi->out_width, pi->out_height)) {
++			if (dispc_is_overlay_scaled(pi)) {
++
++				int x1, y1, x2, y2;
++
++				if (x > pi->pos_x)
++					x1 = pi->pos_x;
++				else
++					x1 = x;
++
++				if (y > pi->pos_y)
++					y1 = pi->pos_y;
++				else
++					y1 = y;
++
++				if ((x + w) < (pi->pos_x + pi->out_width))
++					x2 = pi->pos_x + pi->out_width;
++				else
++					x2 = x + w;
++
++				if ((y + h) < (pi->pos_y + pi->out_height))
++					y2 = pi->pos_y + pi->out_height;
++				else
++					y2 = y + h;
++
++				x = x1;
++				y = y1;
++				w = x2 - x1;
++				h = y2 - y1;
++
++				DSSDBG("Update area after enlarge due to "
++					"scaling %d, %d %dx%d\n",
++					x, y, w, h);
++			}
++		}
++	}
++
++	for (i = 0; i < mgr->num_overlays; i++) {
++		struct omap_overlay *ovl = &mgr->overlays[i];
++		struct omap_overlay_info *pi = &ovl->info;
++
++		int px = pi->pos_x;
++		int py = pi->pos_y;
++		int pw = pi->width;
++		int ph = pi->height;
++		int pow = pi->out_width;
++		int poh = pi->out_height;
++		u32 pa = pi->paddr;
++		int psw = pi->screen_width;
++		int bpp;
++
++		if (ovl->manager != mgr)
++			continue;
++
++		/*
++		 * If plane is not enabled or the update region
++		 * does not intersect with the plane in question,
++		 * we really disable the plane from hardware
++		 */
++
++		if (!pi->enabled ||
++		    !dispc_is_intersecting(x, y, w, h,
++					   px, py, pow, poh)) {
++			dispc_enable_plane(ovl->id, 0);
++			continue;
++		}
++
++		switch (pi->color_mode) {
++		case OMAP_DSS_COLOR_RGB16:
++			bpp = 16;
++			break;
++
++		case OMAP_DSS_COLOR_RGB24P:
++			bpp = 24;
++			break;
++
++		case OMAP_DSS_COLOR_RGB24U:
++			bpp = 32;
++			break;
++
++		case OMAP_DSS_COLOR_YUV2:
++		case OMAP_DSS_COLOR_UYVY:
++			bpp = 16;
++			break;
++
++		default:
++			BUG();
++			return;
++		}
++
++		if (x > pi->pos_x) {
++			px = 0;
++			pw -= (x - pi->pos_x);
++			pa += (x - pi->pos_x) * bpp / 8;
++		} else {
++			px = pi->pos_x - x;
++		}
++
++		if (y > pi->pos_y) {
++			py = 0;
++			ph -= (y - pi->pos_y);
++			pa += (y - pi->pos_y) * psw * bpp / 8;
++		} else {
++			py = pi->pos_y - y;
++		}
++
++		if (w < (px+pw))
++			pw -= (px+pw) - (w);
++
++		if (h < (py+ph))
++			ph -= (py+ph) - (h);
++
++		/* Can't scale the GFX plane */
++		if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
++				dispc_is_overlay_scaled(pi) == 0) {
++			pow = pw;
++			poh = ph;
++		}
++
++		DSSDBG("calc  plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
++				ovl->id, pa, psw, px, py, pw, ph, pow, poh);
++
++		dispc_setup_plane(ovl->id, mgr->id,
++				pa, psw,
++				px, py,
++				pw, ph,
++				pow, poh,
++				pi->color_mode, 0);
++
++		dispc_enable_plane(ovl->id, 1);
++	}
++
++	*xi = x;
++	*yi = y;
++	*wi = w;
++	*hi = h;
++
++}
++
+diff --git a/arch/arm/plat-omap/dss/display.c b/arch/arm/plat-omap/dss/display.c
+new file mode 100644
+index 0000000..e3ff778
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/display.c
+@@ -0,0 +1,787 @@
++/*
++ * linux/arch/arm/plat-omap/dss/display.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DISPLAY"
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/sysfs.h>
++#include <linux/clk.h>
++
++#include <mach/display.h>
++#include <mach/clock.h>
++#include "dss.h"
++
++#define DSS_MAX_DISPLAYS                8
++
++static int num_displays;
++static struct omap_display displays[DSS_MAX_DISPLAYS];
++
++static ssize_t show_clk(struct device *dev, struct device_attribute *attr,
++		char *buf)
++{
++	ssize_t l, size = PAGE_SIZE;
++
++	l = 0;
++
++	l += dss_print_clocks(buf + l, size - l);
++
++	l += dispc_print_clocks(buf + l, size - l);
++#ifdef CONFIG_OMAP2_DSS_DSI
++	l += dsi_print_clocks(buf + l, size - l);
++#endif
++	return l;
++}
++
++static DEVICE_ATTR(clk, S_IRUGO, show_clk, NULL);
++
++int initialize_sysfs(struct device *dev)
++{
++	int r;
++
++	r = device_create_file(dev, &dev_attr_clk);
++	if (r)
++		DSSERR("failed to create sysfs clk file\n");
++
++	return r;
++}
++
++void uninitialize_sysfs(struct device *dev)
++{
++	device_remove_file(dev, &dev_attr_clk);
++}
++
++void initialize_displays(struct omap_dss_platform_data *pdata)
++{
++	int i;
++
++	num_displays = 0;
++
++	BUG_ON(pdata->num_displays > DSS_MAX_DISPLAYS);
++
++	for (i = 0; i < pdata->num_displays; ++i) {
++		struct omap_display *display = &displays[i];
++
++		/*atomic_set(&display->ref_count, 0);*/
++		display->ref_count = 0;
++
++		display->hw_config = *pdata->displays[i];
++		display->type = pdata->displays[i]->type;
++		display->name = pdata->displays[i]->name;
++
++		switch (display->type) {
++
++		case OMAP_DISPLAY_TYPE_DPI:
++			dpi_init_display(display);
++			break;
++#ifdef CONFIG_OMAP2_DSS_RFBI
++		case OMAP_DISPLAY_TYPE_DBI:
++			rfbi_init_display(display);
++			break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_VENC
++		case OMAP_DISPLAY_TYPE_VENC:
++			venc_init_display(display);
++			break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++		case OMAP_DISPLAY_TYPE_SDI:
++			sdi_init_display(display);
++			break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++		case OMAP_DISPLAY_TYPE_DSI:
++			dsi_init_display(display);
++			break;
++#endif
++
++		default:
++			DSSERR("Support for display '%s' not compiled in.\n",
++					display->name);
++			continue;
++		}
++
++		num_displays++;
++	}
++}
++
++static int check_overlay(struct omap_overlay *ovl,
++		struct omap_display *display)
++{
++	struct omap_overlay_info *info;
++	int outw, outh;
++
++	if (!display)
++		return 0;
++
++	if (!ovl->info.enabled)
++		return 0;
++
++	info = &ovl->info;
++
++	if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
++		outw = info->width;
++		outh = info->height;
++	} else {
++		if (info->out_width == 0)
++			outw = info->width;
++		else
++			outw = info->out_width;
++
++		if (info->out_height == 0)
++			outh = info->height;
++		else
++			outh = info->out_height;
++	}
++
++	if (display->panel->timings.x_res < info->pos_x + outw)
++		return -EINVAL;
++
++	if (display->panel->timings.y_res < info->pos_y + outh)
++		return -EINVAL;
++
++	return 0;
++}
++
++
++static int omap_dss_set_manager(struct omap_overlay *ovl,
++		struct omap_overlay_manager *mgr)
++{
++	int r;
++
++	if (ovl->manager) {
++		DSSERR("overlay '%s' already has a manager '%s'\n",
++				ovl->name, ovl->manager->name);
++	}
++
++	r = check_overlay(ovl, mgr->display);
++	if (r)
++		return r;
++
++	ovl->manager = mgr;
++
++	return 0;
++}
++
++static int omap_dss_unset_manager(struct omap_overlay *ovl)
++{
++	if (!ovl->manager) {
++		DSSERR("failed to detach overlay: manager not set\n");
++		return -EINVAL;
++	}
++
++	ovl->manager = NULL;
++
++	return 0;
++}
++
++static int omap_dss_set_display(struct omap_overlay_manager *mgr,
++		struct omap_display *display)
++{
++	int i;
++	int r;
++
++	if (display->manager) {
++		DSSERR("display '%s' already has a manager '%s'\n",
++			       display->name, display->manager->name);
++		return -EINVAL;
++	}
++
++	if ((mgr->supported_displays & display->type) == 0) {
++		DSSERR("display '%s' does not support manager '%s'\n",
++			       display->name, mgr->name);
++		return -EINVAL;
++	}
++
++	for (i = 0; i < mgr->num_overlays; i++) {
++		struct omap_overlay *ovl = &mgr->overlays[i];
++
++		if (ovl->manager != mgr || !ovl->info.enabled)
++			continue;
++
++		r = check_overlay(ovl, display);
++		if (r)
++			return r;
++	}
++
++	display->manager = mgr;
++	mgr->display = display;
++
++	return 0;
++}
++
++static int omap_dss_unset_display(struct omap_overlay_manager *mgr)
++{
++	if (!mgr->display) {
++		DSSERR("failed to unset display, display not set.\n");
++		return -EINVAL;
++	}
++
++	mgr->display->manager = NULL;
++	mgr->display = NULL;
++
++	return 0;
++}
++
++static int omap_dss_setup_overlay_input(struct omap_overlay *ovl,
++		u32 paddr, void *vaddr, int screen_width,
++		int width, int height,
++		enum omap_color_mode color_mode)
++{
++	int r;
++	struct omap_overlay_info old_info;
++
++	if ((ovl->supported_modes & color_mode) == 0) {
++		DSSERR("overlay doesn't support mode %d\n", color_mode);
++		return -EINVAL;
++	}
++
++	old_info = ovl->info;
++
++	ovl->info.paddr = paddr;
++	ovl->info.vaddr = vaddr;
++	ovl->info.screen_width = screen_width;
++
++	ovl->info.width = width;
++	ovl->info.height = height;
++	ovl->info.color_mode = color_mode;
++
++	if (ovl->manager) {
++		r = check_overlay(ovl, ovl->manager->display);
++		if (r) {
++			ovl->info = old_info;
++			return r;
++		}
++	}
++
++	return 0;
++}
++
++static int omap_dss_setup_overlay_output(struct omap_overlay *ovl,
++		int pos_x, int pos_y,
++		int out_width, int out_height)
++{
++	int r;
++	struct omap_overlay_info old_info;
++
++	old_info = ovl->info;
++
++	ovl->info.pos_x = pos_x;
++	ovl->info.pos_y = pos_y;
++	ovl->info.out_width = out_width;
++	ovl->info.out_height = out_height;
++
++	if (ovl->manager) {
++		r = check_overlay(ovl, ovl->manager->display);
++		if (r) {
++			ovl->info = old_info;
++			return r;
++		}
++	}
++
++	return 0;
++}
++
++static int omap_dss_enable_overlay(struct omap_overlay *ovl, int enable)
++{
++	struct omap_overlay_info old_info;
++	int r;
++
++	old_info = ovl->info;
++
++	ovl->info.enabled = enable ? 1 : 0;
++
++	if (ovl->manager) {
++		r = check_overlay(ovl, ovl->manager->display);
++		if (r) {
++			ovl->info = old_info;
++			return r;
++		}
++	}
++
++	return 0;
++}
++
++
++static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
++{
++	int i;
++	int r = 0;
++
++	DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
++
++	if (!mgr->display) {
++		DSSDBG("no display, aborting apply\n");
++		return 0;
++	}
++
++	/* on a manual update display update() handles configuring
++	 * planes */
++	if (mgr->display->get_update_mode) {
++		enum omap_dss_update_mode mode;
++		mode = mgr->display->get_update_mode(mgr->display);
++		if (mode == OMAP_DSS_UPDATE_MANUAL)
++			return 0;
++	}
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	for (i = 0; i < mgr->num_overlays; i++) {
++		int ilace = 0;
++		int outw, outh;
++
++		struct omap_overlay *ovl = &mgr->overlays[i];
++
++		if (!ovl->manager) {
++			dispc_enable_plane(ovl->id, 0);
++			continue;
++		}
++
++		if (ovl->manager != mgr)
++			continue;
++
++		if (!ovl->info.enabled) {
++			dispc_enable_plane(ovl->id, 0);
++			continue;
++		}
++
++		if (mgr->display->type == OMAP_DISPLAY_TYPE_VENC)
++			ilace = 1;
++
++		if (ovl->info.out_width == 0)
++			outw = ovl->info.width;
++		else
++			outw = ovl->info.out_width;
++
++		if (ovl->info.out_height == 0)
++			outh = ovl->info.height;
++		else
++			outh = ovl->info.out_height;
++
++		r = dispc_setup_plane(ovl->id, ovl->manager->id,
++				ovl->info.paddr,
++				ovl->info.screen_width,
++				ovl->info.pos_x,
++				ovl->info.pos_y,
++				ovl->info.width,
++				ovl->info.height,
++				outw,
++				outh,
++				ovl->info.color_mode,
++				ilace);
++
++		if (r) {
++			DSSERR("dispc_setup_plane failed\n");
++			goto exit;
++		}
++
++		dispc_enable_plane(ovl->id, 1);
++	}
++
++	dispc_go(mgr->id);
++
++exit:
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	return r;
++}
++
++static struct omap_overlay dispc_overlays[] = {
++	{
++		.name = "gfx",
++		.id = OMAP_DSS_GFX,
++		.set_manager = &omap_dss_set_manager,
++		.unset_manager = &omap_dss_unset_manager,
++		.setup_input = &omap_dss_setup_overlay_input,
++		.setup_output = &omap_dss_setup_overlay_output,
++		.enable = &omap_dss_enable_overlay,
++		.supported_modes = OMAP_DSS_COLOR_GFX_OMAP3,
++	},
++	{
++		.name = "vid1",
++		.id = OMAP_DSS_VIDEO1,
++		.set_manager = &omap_dss_set_manager,
++		.unset_manager = &omap_dss_unset_manager,
++		.setup_input = &omap_dss_setup_overlay_input,
++		.setup_output = &omap_dss_setup_overlay_output,
++		.enable = &omap_dss_enable_overlay,
++		.supported_modes = OMAP_DSS_COLOR_VID_OMAP3,
++		.caps = OMAP_DSS_OVL_CAP_SCALE,
++	},
++	{
++		.name = "vid2",
++		.id = OMAP_DSS_VIDEO2,
++		.set_manager = &omap_dss_set_manager,
++		.unset_manager = &omap_dss_unset_manager,
++		.setup_input = &omap_dss_setup_overlay_input,
++		.setup_output = &omap_dss_setup_overlay_output,
++		.enable = &omap_dss_enable_overlay,
++		.supported_modes = OMAP_DSS_COLOR_VID_OMAP3,
++		.caps = OMAP_DSS_OVL_CAP_SCALE,
++	},
++};
++
++static struct omap_overlay_manager dispc_overlay_managers[] =
++{
++	[OMAP_DSS_OVL_MGR_LCD] = {
++		.name = "lcd",
++		.id = OMAP_DSS_CHANNEL_LCD,
++		.num_overlays = 3,
++		.overlays = dispc_overlays,
++		.set_display = &omap_dss_set_display,
++		.unset_display = &omap_dss_unset_display,
++		.apply = &omap_dss_mgr_apply,
++		.caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
++		.supported_displays =
++			OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
++			OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
++	},
++	[OMAP_DSS_OVL_MGR_TV] = {
++		.name = "tv",
++		.id = OMAP_DSS_CHANNEL_DIGIT,
++		.num_overlays = 3,
++		.overlays = dispc_overlays,
++		.set_display = &omap_dss_set_display,
++		.unset_display = &omap_dss_unset_display,
++		.apply = &omap_dss_mgr_apply,
++		.caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
++		.supported_displays = OMAP_DISPLAY_TYPE_VENC,
++	},
++};
++
++static int num_overlays = 3;
++
++static struct omap_overlay *omap_dss_overlays[10] = {
++	&dispc_overlays[0],
++	&dispc_overlays[1],
++	&dispc_overlays[2],
++};
++
++static int num_overlay_managers = 2;
++
++static struct omap_overlay_manager *omap_dss_overlay_managers[10] = {
++	&dispc_overlay_managers[0],
++	&dispc_overlay_managers[1],
++};
++
++
++static void omap_dss_add_overlay(struct omap_overlay *overlay)
++{
++	int i = num_overlays++;
++
++	omap_dss_overlays[i] = overlay;
++}
++
++static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
++{
++	int i = num_overlay_managers++;
++	omap_dss_overlay_managers[i] = manager;
++}
++
++int omap_dss_get_num_overlays(void)
++{
++	return num_overlays;
++}
++EXPORT_SYMBOL(omap_dss_get_num_overlays);
++
++struct omap_overlay *omap_dss_get_overlay(int num)
++{
++	BUG_ON(num >= num_overlays);
++	return omap_dss_overlays[num];
++}
++EXPORT_SYMBOL(omap_dss_get_overlay);
++
++int omap_dss_get_num_overlay_managers(void)
++{
++	return num_overlay_managers;
++}
++EXPORT_SYMBOL(omap_dss_get_num_overlay_managers);
++
++struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
++{
++	BUG_ON(num >= num_overlay_managers);
++	return omap_dss_overlay_managers[num];
++}
++EXPORT_SYMBOL(omap_dss_get_overlay_manager);
++
++static int ovl_mgr_apply_l4(struct omap_overlay_manager *mgr)
++{
++	DSSDBG("omap_dss_mgr_apply_l4(%s)\n", mgr->name);
++
++	return 0;
++}
++
++void initialize_overlays(const char *def_disp_name)
++{
++	int i;
++	struct omap_overlay_manager *lcd_mgr;
++	struct omap_overlay_manager *tv_mgr;
++	struct omap_overlay_manager *def_mgr = NULL;
++
++	lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
++	tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
++
++	if (def_disp_name) {
++		for (i = 0; i < num_displays; i++) {
++			struct omap_display *display = &displays[i];
++
++			if (strcmp(display->name, def_disp_name) == 0) {
++				if (display->type != OMAP_DISPLAY_TYPE_VENC) {
++					omap_dss_set_display(lcd_mgr, display);
++					def_mgr = lcd_mgr;
++				} else {
++					omap_dss_set_display(tv_mgr, display);
++					def_mgr = tv_mgr;
++				}
++
++				break;
++			}
++		}
++
++		if (!def_mgr)
++			DSSWARN("default display %s not found\n",
++					def_disp_name);
++	}
++
++	if (def_mgr != lcd_mgr) {
++		/* connect lcd manager to first non-VENC display found */
++		for (i = 0; i < num_displays; i++) {
++			struct omap_display *display = &displays[i];
++			if (display->type != OMAP_DISPLAY_TYPE_VENC) {
++				omap_dss_set_display(lcd_mgr, display);
++
++				if (!def_mgr)
++					def_mgr = lcd_mgr;
++
++				break;
++			}
++		}
++	}
++
++	if (def_mgr != tv_mgr) {
++		/* connect tv manager to first VENC display found */
++		for (i = 0; i < num_displays; i++) {
++			struct omap_display *display = &displays[i];
++			if (display->type == OMAP_DISPLAY_TYPE_VENC) {
++				omap_dss_set_display(tv_mgr, display);
++
++				if (!def_mgr)
++					def_mgr = tv_mgr;
++
++				break;
++			}
++		}
++	}
++
++	/* connect all dispc overlays to def_mgr */
++	if (def_mgr) {
++		for (i = 0; i < 3; i++) {
++			struct omap_overlay *ovl;
++			ovl = omap_dss_get_overlay(i);
++			omap_dss_set_manager(ovl, def_mgr);
++		}
++	}
++
++	/* setup L4 overlay as an example */
++	{
++		static struct omap_overlay ovl = {
++			.name = "l4-ovl",
++			.supported_modes = OMAP_DSS_COLOR_RGB24U,
++			.set_manager = &omap_dss_set_manager,
++			.unset_manager = &omap_dss_unset_manager,
++			.setup_input = &omap_dss_setup_overlay_input,
++			.setup_output = &omap_dss_setup_overlay_output,
++			.enable = &omap_dss_enable_overlay,
++		};
++
++		static struct omap_overlay_manager mgr = {
++			.name = "l4",
++			.num_overlays = 1,
++			.overlays = &ovl,
++			.set_display = &omap_dss_set_display,
++			.unset_display = &omap_dss_unset_display,
++			.apply = &ovl_mgr_apply_l4,
++			.supported_displays =
++				OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
++		};
++
++		omap_dss_add_overlay(&ovl);
++		omap_dss_add_overlay_manager(&mgr);
++		omap_dss_set_manager(&ovl, &mgr);
++	}
++
++}
++
++
++int omap_dss_get_num_displays(void)
++{
++	return num_displays;
++}
++EXPORT_SYMBOL(omap_dss_get_num_displays);
++
++struct omap_display *omap_dss_get_display(int no)
++{
++	struct omap_display *display;
++
++	if (no >= num_displays)
++		return NULL;
++
++	display = &displays[no];
++
++	switch (display->type) {
++	case OMAP_DISPLAY_TYPE_VENC:
++		break;
++
++	case OMAP_DISPLAY_TYPE_DPI:
++	case OMAP_DISPLAY_TYPE_SDI:
++		if (display->panel == NULL)
++			return NULL;
++		break;
++
++	case OMAP_DISPLAY_TYPE_DBI:
++	case OMAP_DISPLAY_TYPE_DSI:
++		if (display->panel == NULL || display->ctrl == NULL)
++			return NULL;
++		break;
++
++	default:
++		return NULL;
++	}
++
++	if (display->panel) {
++		if (!try_module_get(display->panel->owner))
++			goto err0;
++
++		if (display->panel->init)
++			if (display->panel->init(display) != 0)
++				goto err1;
++	}
++
++	if (display->ctrl) {
++		if (!try_module_get(display->ctrl->owner))
++			goto err2;
++
++		if (display->ctrl->init)
++			if (display->ctrl->init(display) != 0)
++				goto err3;
++	}
++
++	display->ref_count++;
++	/*
++	if (atomic_cmpxchg(&display->ref_count, 0, 1) != 0)
++		return 0;
++*/
++
++	return display;
++err3:
++	if (display->ctrl)
++		module_put(display->ctrl->owner);
++err2:
++	if (display->panel && display->panel->init)
++		display->panel->cleanup(display);
++err1:
++	if (display->panel)
++		module_put(display->panel->owner);
++err0:
++	return NULL;
++}
++EXPORT_SYMBOL(omap_dss_get_display);
++
++void omap_dss_put_display(struct omap_display *display)
++{
++	if (--display->ref_count > 0)
++		return;
++/*
++	if (atomic_cmpxchg(&display->ref_count, 1, 0) != 1)
++		return;
++*/
++	if (display->ctrl) {
++		if (display->ctrl->cleanup)
++			display->ctrl->cleanup(display);
++		module_put(display->ctrl->owner);
++	}
++
++	if (display->panel) {
++		if (display->panel->cleanup)
++			display->panel->cleanup(display);
++		module_put(display->panel->owner);
++	}
++}
++EXPORT_SYMBOL(omap_dss_put_display);
++
++void omap_dss_register_ctrl(struct omap_ctrl *ctrl)
++{
++	int i;
++
++	for (i = 0; i < num_displays; i++) {
++		struct omap_display *display = &displays[i];
++		if (display->hw_config.ctrl_name &&
++		    strcmp(display->hw_config.ctrl_name, ctrl->name) == 0) {
++			display->ctrl = ctrl;
++			DSSDBG("ctrl '%s' registered\n", ctrl->name);
++		}
++	}
++}
++EXPORT_SYMBOL(omap_dss_register_ctrl);
++
++void omap_dss_register_panel(struct omap_panel *panel)
++{
++	int i;
++
++	for (i = 0; i < num_displays; i++) {
++		struct omap_display *display = &displays[i];
++		if (display->hw_config.panel_name &&
++		    strcmp(display->hw_config.panel_name, panel->name) == 0) {
++			display->panel = panel;
++			DSSDBG("panel '%s' registered\n", panel->name);
++		}
++	}
++}
++EXPORT_SYMBOL(omap_dss_register_panel);
++
++void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl)
++{
++	int i;
++
++	for (i = 0; i < num_displays; i++) {
++		struct omap_display *display = &displays[i];
++		if (display->hw_config.ctrl_name &&
++		    strcmp(display->hw_config.ctrl_name, ctrl->name) == 0)
++			display->ctrl = NULL;
++	}
++}
++EXPORT_SYMBOL(omap_dss_unregister_ctrl);
++
++void omap_dss_unregister_panel(struct omap_panel *panel)
++{
++	int i;
++
++	for (i = 0; i < num_displays; i++) {
++		struct omap_display *display = &displays[i];
++		if (display->hw_config.panel_name &&
++		    strcmp(display->hw_config.panel_name, panel->name) == 0)
++			display->panel = NULL;
++	}
++}
++EXPORT_SYMBOL(omap_dss_unregister_panel);
+diff --git a/arch/arm/plat-omap/dss/dpi.c b/arch/arm/plat-omap/dss/dpi.c
+new file mode 100644
+index 0000000..2dd8a3b
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/dpi.c
+@@ -0,0 +1,344 @@
++/*
++ * linux/arch/arm/plat-omap/dss/dpi.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++
++static struct {
++	int update_enabled;
++} dpi;
++
++static void dpi_set_mode(struct omap_display *display)
++{
++	struct omap_panel *panel = display->panel;
++	int lck_div, pck_div;
++	unsigned long fck;
++	unsigned long pck;
++	int is_tft;
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	dispc_set_pol_freq(panel);
++
++	is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	{
++		struct dsi_clock_info cinfo;
++		dsi_pll_calc_pck(is_tft,
++				display->panel->timings.pixel_clock * 1000,
++				&cinfo);
++
++		dsi_pll_program(&cinfo);
++
++		dss_select_clk_source(0, 1);
++
++		dispc_set_lcd_divisor(cinfo.lck_div, cinfo.pck_div);
++
++		fck = cinfo.dispc_fck;
++		lck_div = cinfo.lck_div;
++		pck_div = cinfo.pck_div;
++	}
++#else
++	{
++		struct dispc_clock_info cinfo;
++		dispc_calc_clock_div(is_tft, panel->timings.pixel_clock * 1000,
++				&cinfo);
++
++		if (dispc_set_clock_div(&cinfo)) {
++			DSSERR("Failed to set DSS clocks\n");
++			dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++			return;
++		}
++
++		fck = cinfo.fck;
++		lck_div = cinfo.lck_div;
++		pck_div = cinfo.pck_div;
++	}
++#endif
++
++	pck = fck / lck_div / pck_div / 1000;
++
++	if (pck != panel->timings.pixel_clock) {
++		DSSWARN("Could not find exact pixel clock. "
++				"Requested %d kHz, got %lu kHz\n",
++				panel->timings.pixel_clock, pck);
++
++		panel->timings.pixel_clock = pck;
++	}
++
++	dispc_set_lcd_timings(&panel->timings);
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++
++static int dpi_display_enable(struct omap_display *display)
++{
++	struct omap_panel *panel = display->panel;
++	int r;
++	int is_tft;
++	unsigned high, low, burst;
++
++	if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++		DSSERR("display already enabled\n");
++		return -EINVAL;
++	}
++
++	r = panel->enable(display);
++	if (r)
++		return r;
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	dss_clk_enable(DSS_CLK_FCK2);
++	r = dsi_pll_init(0, 1);
++	if (r)
++		return r;
++#endif
++	is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
++	dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
++			OMAP_DSS_LCD_DISPLAY_STN);
++	dispc_set_tft_data_lines(display->hw_config.u.dpi.data_lines);
++
++	dispc_set_burst_size(OMAP_DSS_GFX, OMAP_DSS_BURST_16x32);
++	dispc_set_burst_size(OMAP_DSS_VIDEO1, OMAP_DSS_BURST_16x32);
++	dispc_set_burst_size(OMAP_DSS_VIDEO2, OMAP_DSS_BURST_16x32);
++
++	burst = 16 * 32 / 8;
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_GFX) - burst;
++	low = dispc_get_plane_fifo_size(OMAP_DSS_GFX) / 4;
++	dispc_setup_plane_fifo(OMAP_DSS_GFX, low, high);
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO1) - burst;
++	low = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO1) / 4;
++	dispc_setup_plane_fifo(OMAP_DSS_VIDEO1, low, high);
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO2) - burst;
++	low = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO2) / 4;
++	dispc_setup_plane_fifo(OMAP_DSS_VIDEO2, low, high);
++
++	dpi_set_mode(display);
++
++	mdelay(2);
++
++	dispc_enable_lcd_out(1);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	return 0;
++}
++
++static int dpi_display_resume(struct omap_display *display);
++
++static void dpi_display_disable(struct omap_display *display)
++{
++	if (display->state == OMAP_DSS_DISPLAY_DISABLED)
++		return;
++
++	if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
++		dpi_display_resume(display);
++
++	display->panel->disable(display);
++	dispc_enable_lcd_out(0);
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	dss_select_clk_source(0, 0);
++	dsi_pll_uninit();
++	dss_clk_disable(DSS_CLK_FCK2);
++#endif
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++}
++
++static int dpi_display_suspend(struct omap_display *display)
++{
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return -EINVAL;
++
++	if (display->panel->suspend)
++		display->panel->suspend(display);
++
++	dispc_enable_lcd_out(0);
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	display->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++	return 0;
++}
++
++static int dpi_display_resume(struct omap_display *display)
++{
++	if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
++		return -EINVAL;
++
++	dispc_enable_lcd_out(1);
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	if (display->panel->resume)
++		display->panel->resume(display);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	return 0;
++}
++
++static void dpi_set_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	DSSDBG("dpi_set_timings\n");
++	display->panel->timings = *timings;
++	if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
++		dpi_set_mode(display);
++		dispc_go(OMAP_DSS_CHANNEL_LCD);
++	}
++}
++
++static int dpi_check_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	int is_tft;
++	int r;
++	int lck_div, pck_div;
++	unsigned long fck;
++	unsigned long pck;
++
++	if (timings->hsw < 1 || timings->hsw > 64 ||
++		timings->hfp < 1 || timings->hfp > 256 ||
++		timings->hbp < 1 || timings->hbp > 256) {
++		return -EINVAL;
++	}
++
++	if (timings->vsw < 1 || timings->vsw > 64 ||
++		timings->vfp > 256 || timings->vbp > 256) {
++		return -EINVAL;
++	}
++
++	if (timings->pixel_clock == 0)
++		return -EINVAL;
++
++	is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++	{
++		struct dsi_clock_info cinfo;
++		r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
++				&cinfo);
++
++		if (r)
++			return r;
++
++		fck = cinfo.dispc_fck;
++		lck_div = cinfo.lck_div;
++		pck_div = cinfo.pck_div;
++	}
++#else
++	{
++		struct dispc_clock_info cinfo;
++		r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
++				&cinfo);
++
++		if (r)
++			return r;
++
++		fck = cinfo.fck;
++		lck_div = cinfo.lck_div;
++		pck_div = cinfo.pck_div;
++	}
++#endif
++
++	pck = fck / lck_div / pck_div / 1000;
++
++	timings->pixel_clock = pck;
++
++	return 0;
++}
++
++static void dpi_get_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	*timings = display->panel->timings;
++}
++
++static int dpi_display_set_update_mode(struct omap_display *display,
++		enum omap_dss_update_mode mode)
++{
++	if (mode == OMAP_DSS_UPDATE_MANUAL)
++		return -EINVAL;
++
++	if (mode == OMAP_DSS_UPDATE_DISABLED) {
++		dispc_enable_lcd_out(0);
++		dpi.update_enabled = 0;
++	} else {
++		dispc_enable_lcd_out(1);
++		dpi.update_enabled = 1;
++	}
++
++	return 0;
++}
++
++static enum omap_dss_update_mode dpi_display_get_update_mode(
++		struct omap_display *display)
++{
++	return dpi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
++		OMAP_DSS_UPDATE_DISABLED;
++}
++
++void dpi_init_display(struct omap_display *display)
++{
++	DSSDBG("DPI init_display\n");
++
++	display->enable = dpi_display_enable;
++	display->disable = dpi_display_disable;
++	display->suspend = dpi_display_suspend;
++	display->resume = dpi_display_resume;
++	display->set_timings = dpi_set_timings;
++	display->check_timings = dpi_check_timings;
++	display->get_timings = dpi_get_timings;
++	display->set_update_mode = dpi_display_set_update_mode;
++	display->get_update_mode = dpi_display_get_update_mode;
++}
++
++int dpi_init(void)
++{
++	return 0;
++}
++
++void dpi_exit(void)
++{
++}
++
+diff --git a/arch/arm/plat-omap/dss/dsi.c b/arch/arm/plat-omap/dss/dsi.c
+new file mode 100644
+index 0000000..e279571
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/dsi.c
+@@ -0,0 +1,3187 @@
++/*
++ * linux/arch/arm/plat-omap/dss/dsi.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DSI"
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++#include <linux/mutex.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include <mach/clock.h>
++
++#include "dss.h"
++
++/*#define VERBOSE*/
++/*#define VERBOSE_IRQ*/
++/*#define MEASURE_PERF*/
++
++#define DSI_BASE		0x4804FC00
++
++struct dsi_reg { u16 idx; };
++
++#define DSI_REG(idx)		((const struct dsi_reg) { idx })
++
++#define DSI_SZ_REGS		SZ_1K
++/* DSI Protocol Engine */
++
++#define DSI_REVISION			DSI_REG(0x0000)
++#define DSI_SYSCONFIG			DSI_REG(0x0010)
++#define DSI_SYSSTATUS			DSI_REG(0x0014)
++#define DSI_IRQSTATUS			DSI_REG(0x0018)
++#define DSI_IRQENABLE			DSI_REG(0x001C)
++#define DSI_CTRL			DSI_REG(0x0040)
++#define DSI_COMPLEXIO_CFG1		DSI_REG(0x0048)
++#define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(0x004C)
++#define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(0x0050)
++#define DSI_CLK_CTRL			DSI_REG(0x0054)
++#define DSI_TIMING1			DSI_REG(0x0058)
++#define DSI_TIMING2			DSI_REG(0x005C)
++#define DSI_VM_TIMING1			DSI_REG(0x0060)
++#define DSI_VM_TIMING2			DSI_REG(0x0064)
++#define DSI_VM_TIMING3			DSI_REG(0x0068)
++#define DSI_CLK_TIMING			DSI_REG(0x006C)
++#define DSI_TX_FIFO_VC_SIZE		DSI_REG(0x0070)
++#define DSI_RX_FIFO_VC_SIZE		DSI_REG(0x0074)
++#define DSI_COMPLEXIO_CFG2		DSI_REG(0x0078)
++#define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(0x007C)
++#define DSI_VM_TIMING4			DSI_REG(0x0080)
++#define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(0x0084)
++#define DSI_VM_TIMING5			DSI_REG(0x0088)
++#define DSI_VM_TIMING6			DSI_REG(0x008C)
++#define DSI_VM_TIMING7			DSI_REG(0x0090)
++#define DSI_STOPCLK_TIMING		DSI_REG(0x0094)
++#define DSI_VC_CTRL(n)			DSI_REG(0x0100 + (n * 0x20))
++#define DSI_VC_TE(n)			DSI_REG(0x0104 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(0x0108 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(0x010C + (n * 0x20))
++#define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(0x0110 + (n * 0x20))
++#define DSI_VC_IRQSTATUS(n)		DSI_REG(0x0118 + (n * 0x20))
++#define DSI_VC_IRQENABLE(n)		DSI_REG(0x011C + (n * 0x20))
++
++/* DSIPHY_SCP */
++
++#define DSI_DSIPHY_CFG0			DSI_REG(0x200 + 0x0000)
++#define DSI_DSIPHY_CFG1			DSI_REG(0x200 + 0x0004)
++#define DSI_DSIPHY_CFG2			DSI_REG(0x200 + 0x0008)
++#define DSI_DSIPHY_CFG5			DSI_REG(0x200 + 0x0014)
++
++/* DSI_PLL_CTRL_SCP */
++
++#define DSI_PLL_CONTROL			DSI_REG(0x300 + 0x0000)
++#define DSI_PLL_STATUS			DSI_REG(0x300 + 0x0004)
++#define DSI_PLL_GO			DSI_REG(0x300 + 0x0008)
++#define DSI_PLL_CONFIGURATION1		DSI_REG(0x300 + 0x000C)
++#define DSI_PLL_CONFIGURATION2		DSI_REG(0x300 + 0x0010)
++
++#define REG_GET(idx, start, end) \
++	FLD_GET(dsi_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++	dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
++
++/* Global interrupts */
++#define DSI_IRQ_VC0		(1 << 0)
++#define DSI_IRQ_VC1		(1 << 1)
++#define DSI_IRQ_VC2		(1 << 2)
++#define DSI_IRQ_VC3		(1 << 3)
++#define DSI_IRQ_WAKEUP		(1 << 4)
++#define DSI_IRQ_RESYNC		(1 << 5)
++#define DSI_IRQ_PLL_LOCK	(1 << 7)
++#define DSI_IRQ_PLL_UNLOCK	(1 << 8)
++#define DSI_IRQ_PLL_RECALL	(1 << 9)
++#define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
++#define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
++#define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
++#define DSI_IRQ_TE_TRIGGER	(1 << 16)
++#define DSI_IRQ_ACK_TRIGGER	(1 << 17)
++#define DSI_IRQ_SYNC_LOST	(1 << 18)
++#define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
++#define DSI_IRQ_TA_TIMEOUT	(1 << 20)
++#define DSI_IRQ_ERROR_MASK \
++	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
++	DSI_IRQ_TA_TIMEOUT)
++#define DSI_IRQ_CHANNEL_MASK	0xf
++
++/* Virtual channel interrupts */
++#define DSI_VC_IRQ_CS		(1 << 0)
++#define DSI_VC_IRQ_ECC_CORR	(1 << 1)
++#define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
++#define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
++#define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
++#define DSI_VC_IRQ_BTA		(1 << 5)
++#define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
++#define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
++#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
++#define DSI_VC_IRQ_ERROR_MASK \
++	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
++	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
++	DSI_VC_IRQ_FIFO_TX_UDF)
++
++/* ComplexIO interrupts */
++#define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
++#define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
++#define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
++#define DSI_CIO_IRQ_ERRESC1		(1 << 5)
++#define DSI_CIO_IRQ_ERRESC2		(1 << 6)
++#define DSI_CIO_IRQ_ERRESC3		(1 << 7)
++#define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
++#define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
++#define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
++#define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
++#define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
++#define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
++
++#define DSI_DT_DCS_SHORT_WRITE_0	0x05
++#define DSI_DT_DCS_SHORT_WRITE_1	0x15
++#define DSI_DT_DCS_READ			0x06
++#define DSI_DT_SET_MAX_RET_PKG_SIZE	0x37
++#define DSI_DT_NULL_PACKET		0x09
++#define DSI_DT_DCS_LONG_WRITE		0x39
++
++#define DSI_DT_RX_ACK_WITH_ERR		0x02
++#define DSI_DT_RX_DCS_LONG_READ		0x1c
++#define DSI_DT_RX_SHORT_READ_1		0x21
++#define DSI_DT_RX_SHORT_READ_2		0x22
++
++#define FINT_MAX 2100000
++#define FINT_MIN 750000
++#define REGN_MAX (1 << 7)
++#define REGM_MAX ((1 << 11) - 1)
++#define REGM3_MAX (1 << 4)
++#define REGM4_MAX (1 << 4)
++
++enum fifo_size {
++	DSI_FIFO_SIZE_0		= 0,
++	DSI_FIFO_SIZE_32	= 1,
++	DSI_FIFO_SIZE_64	= 2,
++	DSI_FIFO_SIZE_96	= 3,
++	DSI_FIFO_SIZE_128	= 4,
++};
++
++static struct
++{
++	void __iomem	*base;
++
++	unsigned long	dsi1_pll_fclk;	/* Hz */
++	unsigned long	dsi2_pll_fclk;	/* Hz */
++	unsigned long	dsiphy;		/* Hz */
++	unsigned long	ddr_clk;	/* Hz */
++
++	u32		ctx[DSI_SZ_REGS / sizeof(u32)];
++
++	struct {
++		enum fifo_size	fifo_size;
++		int dest_per;	/* destination peripheral 0-3 */
++	} vc[4];
++
++	struct mutex lock;
++
++	unsigned pll_locked;
++
++	struct completion bta_completion;
++
++	spinlock_t update_lock;
++	int update_ongoing;
++	int update_syncers;
++	struct completion update_completion;
++	struct delayed_work framedone_work;
++
++	enum omap_dss_update_mode user_update_mode; /* what the user wants */
++	enum omap_dss_update_mode update_mode; /* current mode */
++	int use_te;
++	int framedone_scheduled; /* helps to catch strange framedone bugs */
++
++	struct {
++		struct omap_display *display;
++		int x, y, w, h;
++		int bytespp;
++	} update_region;
++
++	unsigned long cache_req_pck;
++	unsigned long cache_clk_freq;
++	struct dsi_clock_info cache_cinfo;
++
++#ifdef MEASURE_PERF
++	ktime_t perf_setup_time;
++	ktime_t perf_start_time;
++	int perf_measure_frames;
++#endif
++} dsi;
++
++static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
++{
++	__raw_writel(val, dsi.base + idx.idx);
++}
++
++static inline u32 dsi_read_reg(const struct dsi_reg idx)
++{
++	return __raw_readl(dsi.base + idx.idx);
++}
++
++
++#define SR(reg) \
++	dsi.ctx[(DSI_##reg).idx / sizeof(u32)] = dsi_read_reg(DSI_##reg)
++#define RR(reg) \
++	dsi_write_reg(DSI_##reg, dsi.ctx[(DSI_##reg).idx / sizeof(u32)])
++
++void dsi_save_context(void)
++{
++	SR(SYSCONFIG);
++	SR(IRQENABLE);
++	SR(CTRL);
++	SR(COMPLEXIO_CFG1);
++	SR(COMPLEXIO_IRQ_ENABLE);
++	SR(CLK_CTRL);
++	SR(TIMING1);
++	SR(TIMING2);
++	SR(VM_TIMING1);
++	SR(VM_TIMING2);
++	SR(VM_TIMING3);
++	SR(CLK_TIMING);
++	SR(TX_FIFO_VC_SIZE);
++	SR(RX_FIFO_VC_SIZE);
++	SR(COMPLEXIO_CFG2);
++	SR(VM_TIMING4);
++	SR(VM_TIMING5);
++	SR(VM_TIMING6);
++	SR(VM_TIMING7);
++	SR(STOPCLK_TIMING);
++
++	SR(VC_CTRL(0));
++	SR(VC_TE(0));
++	SR(VC_IRQENABLE(0));
++
++	SR(VC_CTRL(1));
++	SR(VC_TE(1));
++	SR(VC_IRQENABLE(1));
++
++	SR(VC_CTRL(2));
++	SR(VC_TE(2));
++	SR(VC_IRQENABLE(2));
++
++	SR(VC_CTRL(3));
++	SR(VC_TE(3));
++	SR(VC_IRQENABLE(3));
++
++	SR(DSIPHY_CFG0);
++	SR(DSIPHY_CFG1);
++	SR(DSIPHY_CFG2);
++	SR(DSIPHY_CFG5);
++
++	SR(PLL_CONTROL);
++	SR(PLL_CONFIGURATION1);
++	SR(PLL_CONFIGURATION2);
++}
++
++void dsi_restore_context(void)
++{
++	RR(SYSCONFIG);
++	RR(IRQENABLE);
++	RR(CTRL);
++	RR(COMPLEXIO_CFG1);
++	RR(COMPLEXIO_IRQ_ENABLE);
++	RR(CLK_CTRL);
++	RR(TIMING1);
++	RR(TIMING2);
++	RR(VM_TIMING1);
++	RR(VM_TIMING2);
++	RR(VM_TIMING3);
++	RR(CLK_TIMING);
++	RR(TX_FIFO_VC_SIZE);
++	RR(RX_FIFO_VC_SIZE);
++	RR(COMPLEXIO_CFG2);
++	RR(VM_TIMING4);
++	RR(VM_TIMING5);
++	RR(VM_TIMING6);
++	RR(VM_TIMING7);
++	RR(STOPCLK_TIMING);
++
++	RR(VC_CTRL(0));
++	RR(VC_IRQENABLE(0));
++
++	RR(VC_CTRL(1));
++	RR(VC_IRQENABLE(1));
++
++	RR(VC_CTRL(2));
++	RR(VC_IRQENABLE(2));
++
++	RR(VC_CTRL(3));
++	RR(VC_IRQENABLE(3));
++
++	RR(DSIPHY_CFG0);
++	RR(DSIPHY_CFG1);
++	RR(DSIPHY_CFG2);
++	RR(DSIPHY_CFG5);
++
++	RR(PLL_CONTROL);
++	RR(PLL_CONFIGURATION1);
++	RR(PLL_CONFIGURATION2);
++}
++
++#undef SR
++#undef RR
++
++static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
++		int value)
++{
++	int t = 100000;
++
++	while (REG_GET(idx, bitnum, bitnum) != value) {
++		if (--t == 0)
++			return !value;
++	}
++
++	return value;
++}
++
++
++#ifdef MEASURE_PERF
++static void perf_mark_setup(void)
++{
++	dsi.perf_setup_time = ktime_get();
++}
++
++static void perf_mark_start(void)
++{
++	dsi.perf_start_time = ktime_get();
++}
++
++static void perf_show(const char *name)
++{
++	ktime_t t, setup_time, trans_time;
++	u32 total_bytes;
++	u32 setup_us, trans_us, total_us;
++	const int numframes = 100;
++	static u32 s_trans_us, s_min_us = 0xffffffff, s_max_us;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
++		return;
++
++	t = ktime_get();
++
++	setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
++	setup_us = (u32)ktime_to_us(setup_time);
++	if (setup_us == 0)
++		setup_us = 1;
++
++	trans_time = ktime_sub(t, dsi.perf_start_time);
++	trans_us = (u32)ktime_to_us(trans_time);
++	if (trans_us == 0)
++		trans_us = 1;
++
++	total_us = setup_us + trans_us;
++
++	total_bytes = dsi.update_region.w *
++		dsi.update_region.h *
++		dsi.update_region.bytespp;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++		dsi.perf_measure_frames++;
++
++		if (trans_us < s_min_us)
++			s_min_us = trans_us;
++
++		if (trans_us > s_max_us)
++			s_max_us = trans_us;
++
++		s_trans_us += trans_us;
++
++		if (dsi.perf_measure_frames < numframes)
++			return;
++
++		DSSINFO("%s update: %d frames in %u us (min/max %u/%u), "
++				"%u fps\n",
++				name, numframes,
++				s_trans_us,
++				s_min_us,
++				s_max_us,
++				1000*1000 / (s_trans_us / numframes));
++
++		dsi.perf_measure_frames = 0;
++		s_trans_us = 0;
++		s_min_us = 0xffffffff;
++		s_max_us = 0;
++	} else {
++		DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
++				"%u kbytes/sec\n",
++				name,
++				setup_us,
++				trans_us,
++				total_us,
++				1000*1000 / total_us,
++				total_bytes,
++				total_bytes * 1000 / total_us);
++	}
++}
++#else
++#define perf_mark_setup()
++#define perf_mark_start()
++#define perf_show(x)
++#endif
++
++
++
++
++static void print_irq_status(u32 status)
++{
++#ifndef VERBOSE_IRQ
++	if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
++		return;
++#endif
++	printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++	if (status & DSI_IRQ_##x) \
++		printk(#x " ");
++#ifdef VERBOSE_IRQ
++	PIS(VC0);
++	PIS(VC1);
++	PIS(VC2);
++	PIS(VC3);
++#endif
++	PIS(WAKEUP);
++	PIS(RESYNC);
++	PIS(PLL_LOCK);
++	PIS(PLL_UNLOCK);
++	PIS(PLL_RECALL);
++	PIS(COMPLEXIO_ERR);
++	PIS(HS_TX_TIMEOUT);
++	PIS(LP_RX_TIMEOUT);
++	PIS(TE_TRIGGER);
++	PIS(ACK_TRIGGER);
++	PIS(SYNC_LOST);
++	PIS(LDO_POWER_GOOD);
++	PIS(TA_TIMEOUT);
++#undef PIS
++
++	printk("\n");
++}
++
++static void print_irq_status_vc(int channel, u32 status)
++{
++#ifndef VERBOSE_IRQ
++	if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
++		return;
++#endif
++	printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
++
++#define PIS(x) \
++	if (status & DSI_VC_IRQ_##x) \
++		printk(#x " ");
++	PIS(CS);
++	PIS(ECC_CORR);
++#ifdef VERBOSE_IRQ
++	PIS(PACKET_SENT);
++#endif
++	PIS(FIFO_TX_OVF);
++	PIS(FIFO_RX_OVF);
++	PIS(BTA);
++	PIS(ECC_NO_CORR);
++	PIS(FIFO_TX_UDF);
++	PIS(PP_BUSY_CHANGE);
++#undef PIS
++	printk("\n");
++}
++
++static void print_irq_status_cio(u32 status)
++{
++	printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
++
++#define PIS(x) \
++	if (status & DSI_CIO_IRQ_##x) \
++		printk(#x " ");
++	PIS(ERRSYNCESC1);
++	PIS(ERRSYNCESC2);
++	PIS(ERRSYNCESC3);
++	PIS(ERRESC1);
++	PIS(ERRESC2);
++	PIS(ERRESC3);
++	PIS(ERRCONTROL1);
++	PIS(ERRCONTROL2);
++	PIS(ERRCONTROL3);
++	PIS(STATEULPS1);
++	PIS(STATEULPS2);
++	PIS(STATEULPS3);
++	PIS(ERRCONTENTIONLP0_1);
++	PIS(ERRCONTENTIONLP1_1);
++	PIS(ERRCONTENTIONLP0_2);
++	PIS(ERRCONTENTIONLP1_2);
++	PIS(ERRCONTENTIONLP0_3);
++	PIS(ERRCONTENTIONLP1_3);
++	PIS(ULPSACTIVENOT_ALL0);
++	PIS(ULPSACTIVENOT_ALL1);
++#undef PIS
++
++	printk("\n");
++}
++
++static int debug_irq;
++
++/* called from dss */
++void dsi_irq_handler(void)
++{
++	u32 irqstatus, vcstatus, ciostatus;
++	int i;
++
++	irqstatus = dsi_read_reg(DSI_IRQSTATUS);
++
++	if (irqstatus & DSI_IRQ_ERROR_MASK) {
++		DSSERR("DSI error, irqstatus %x\n", irqstatus);
++		print_irq_status(irqstatus);
++	} else if (debug_irq) {
++		print_irq_status(irqstatus);
++	}
++
++	for (i = 0; i < 4; ++i) {
++		if ((irqstatus & (1<<i)) == 0)
++			continue;
++
++		vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++
++		if (vcstatus & DSI_VC_IRQ_BTA)
++			complete(&dsi.bta_completion);
++
++		if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
++			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
++				       i, vcstatus);
++			print_irq_status_vc(i, vcstatus);
++		} else if (debug_irq) {
++			print_irq_status_vc(i, vcstatus);
++		}
++
++		dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
++	}
++
++	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
++		ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++
++		dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
++
++		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
++		print_irq_status_cio(ciostatus);
++	}
++
++	dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
++}
++
++
++static void _dsi_initialize_irq(void)
++{
++	u32 l;
++	int i;
++
++	/* disable all interrupts */
++	dsi_write_reg(DSI_IRQENABLE, 0);
++	for (i = 0; i < 4; ++i)
++		dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
++	dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
++
++	/* clear interrupt status */
++	l = dsi_read_reg(DSI_IRQSTATUS);
++	dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
++
++	for (i = 0; i < 4; ++i) {
++		l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++		dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
++	}
++
++	l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++	dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
++
++	/* enable error irqs */
++	l = DSI_IRQ_ERROR_MASK;
++	dsi_write_reg(DSI_IRQENABLE, l);
++
++	l = DSI_VC_IRQ_ERROR_MASK;
++	for (i = 0; i < 4; ++i)
++		dsi_write_reg(DSI_VC_IRQENABLE(i), l);
++
++	/* XXX zonda responds incorrectly, causing control error:
++	   Exit from LP-ESC mode to LP11 uses wrong transition states on the
++	   data lines LP0 and LN0. */
++	dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
++			-1 & (~DSI_CIO_IRQ_ERRCONTROL2));
++}
++
++static void dsi_vc_enable_bta_irq(int channel)
++{
++	u32 l;
++
++	l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++	l |= DSI_VC_IRQ_BTA;
++	dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++static void dsi_vc_disable_bta_irq(int channel)
++{
++	u32 l;
++
++	l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++	l &= ~DSI_VC_IRQ_BTA;
++	dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++/* DSI func clock. this could also be DSI2_PLL_FCLK */
++static inline void enable_clocks(int enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	else
++		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++/* source clock for DSI PLL. this could also be PCLKFREE */
++static inline void dsi_enable_pll_clock(int enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_FCK2);
++	else
++		dss_clk_disable(DSS_CLK_FCK2);
++
++	if (enable && dsi.pll_locked) {
++		if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
++			DSSERR("cannot lock PLL when enabling clocks\n");
++	}
++}
++
++#ifdef DEBUG
++static void _dsi_print_reset_status(void)
++{
++	u32 l;
++
++	if (!dss_debug)
++		return;
++
++	/* A dummy read using the SCP interface to any DSIPHY register is
++	 * required after DSIPHY reset to complete the reset of the DSI complex
++	 * I/O. */
++	l = dsi_read_reg(DSI_DSIPHY_CFG5);
++
++	printk(KERN_DEBUG "DSI resets: ");
++
++	l = dsi_read_reg(DSI_PLL_STATUS);
++	printk("PLL (%d) ", FLD_GET(l, 0, 0));
++
++	l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++	printk("CIO (%d) ", FLD_GET(l, 29, 29));
++
++	l = dsi_read_reg(DSI_DSIPHY_CFG5);
++	printk("PHY (%x, %d, %d, %d)\n",
++			FLD_GET(l, 28, 26),
++			FLD_GET(l, 29, 29),
++			FLD_GET(l, 30, 30),
++			FLD_GET(l, 31, 31));
++}
++#else
++#define _dsi_print_reset_status()
++#endif
++
++static inline int dsi_if_enable(int enable)
++{
++	DSSDBG("dsi_if_enable(%d)\n", enable);
++
++	enable = enable ? 1 : 0;
++	REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
++
++	if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
++			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
++			return -EIO;
++	}
++
++	return 0;
++}
++
++static unsigned long dsi_fclk_rate(void)
++{
++	unsigned long r;
++
++	if (dss_get_dsi_clk_source() == 0) {
++		/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
++		r = dss_clk_get_rate(DSS_CLK_FCK1);
++	} else {
++		/* DSI FCLK source is DSI2_PLL_FCLK */
++		r = dsi.dsi2_pll_fclk;
++	}
++
++	return r;
++}
++
++static int dsi_set_lp_clk_divisor(void)
++{
++	int n;
++	unsigned long dsi_fclk;
++	unsigned long mhz;
++
++	/* LP_CLK_DIVISOR, DSI fclk/n, should be 20MHz - 32kHz */
++
++	dsi_fclk = dsi_fclk_rate();
++
++	for (n = 1; n < (1 << 13) - 1; ++n) {
++		mhz = dsi_fclk / n;
++		if (mhz <= 20*1000*1000)
++			break;
++	}
++
++	if (n == (1 << 13) - 1) {
++		DSSERR("Failed to find LP_CLK_DIVISOR\n");
++		return -EINVAL;
++	}
++
++	DSSDBG("LP_CLK_DIV %d, LP_CLK %ld\n", n, mhz);
++
++	REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0);	/* LP_CLK_DIVISOR */
++	if (dsi_fclk > 30*1000*1000)
++		REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
++
++	return 0;
++}
++
++
++enum dsi_pll_power_state {
++	DSI_PLL_POWER_OFF	= 0x0,
++	DSI_PLL_POWER_ON_HSCLK	= 0x1,
++	DSI_PLL_POWER_ON_ALL	= 0x2,
++	DSI_PLL_POWER_ON_DIV	= 0x3,
++};
++
++static int dsi_pll_power(enum dsi_pll_power_state state)
++{
++	int t = 0;
++
++	REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30);	/* PLL_PWR_CMD */
++
++	/* PLL_PWR_STATUS */
++	while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
++		udelay(1);
++		if (t++ > 1000) {
++			DSSERR("Failed to set DSI PLL power mode to %d\n",
++					state);
++			return -ENODEV;
++		}
++	}
++
++	return 0;
++}
++
++int dsi_pll_calc_pck(int is_tft, unsigned long req_pck,
++		struct dsi_clock_info *cinfo)
++{
++	struct dsi_clock_info cur, best;
++	int min_fck_per_pck;
++	int match = 0;
++
++	if (req_pck == dsi.cache_req_pck &&
++			dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
++		DSSDBG("DSI clock info found from cache\n");
++		*cinfo = dsi.cache_cinfo;
++		return 0;
++	}
++
++	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++	if (min_fck_per_pck &&
++		req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++		DSSERR("Requested pixel clock not possible with the current "
++				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++				"the constraint off.\n");
++		min_fck_per_pck = 0;
++	}
++
++	DSSDBG("dsi_pll_calc\n");
++
++retry:
++	memset(&best, 0, sizeof(best));
++
++	memset(&cur, 0, sizeof(cur));
++	cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
++	cur.use_dss2_fck = 1;
++	cur.highfreq = 0;
++
++	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++	for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++		if (cur.highfreq == 0)
++			cur.fint = cur.clkin / cur.regn;
++		else
++			cur.fint = cur.clkin / (2 * cur.regn);
++
++		if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++			continue;
++
++		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++		for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++			unsigned long a, b;
++
++			a = 2 * cur.regm * (cur.clkin/1000);
++			b = cur.regn * (cur.highfreq + 1);
++			cur.dsiphy = a / b * 1000;
++
++			if (cur.dsiphy > 1800 * 1000 * 1000)
++				break;
++
++			/* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3  < 173MHz */
++			for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
++					++cur.regm3) {
++				cur.dispc_fck = cur.dsiphy / cur.regm3;
++
++				/* this will narrow down the search a bit,
++				 * but still give pixclocks below what was
++				 * requested */
++				if (cur.dispc_fck  < req_pck)
++					break;
++
++				if (cur.dispc_fck > DISPC_MAX_FCK)
++					continue;
++
++				if (min_fck_per_pck &&
++					cur.dispc_fck <
++						req_pck * min_fck_per_pck)
++					continue;
++
++				match = 1;
++
++				find_lck_pck_divs(is_tft, req_pck,
++						cur.dispc_fck,
++						&cur.lck_div,
++						&cur.pck_div);
++
++				cur.lck = cur.dispc_fck / cur.lck_div;
++				cur.pck = cur.lck / cur.pck_div;
++
++				if (abs(cur.pck - req_pck) <
++						abs(best.pck - req_pck)) {
++					best = cur;
++
++					if (cur.pck == req_pck)
++						goto found;
++				}
++			}
++		}
++	}
++found:
++	if (!match) {
++		if (min_fck_per_pck) {
++			DSSERR("Could not find suitable clock settings.\n"
++					"Turning FCK/PCK constraint off and"
++					"trying again.\n");
++			min_fck_per_pck = 0;
++			goto retry;
++		}
++
++		DSSERR("Could not find suitable clock settings.\n");
++
++		return -EINVAL;
++	}
++
++	/* DSI2_PLL_FCLK(MHz) = DSIPHY(MHz) / regm4  < 173MHz */
++	/* hardcoded 48MHz for now. what should it be? */
++	best.regm4 = best.dsiphy / 48000000;
++	if (best.regm4 > REGM4_MAX)
++		best.regm4 = REGM4_MAX;
++	best.dsi_fck = best.dsiphy / best.regm4;
++
++	if (cinfo)
++		*cinfo = best;
++
++	dsi.cache_req_pck = req_pck;
++	dsi.cache_clk_freq = 0;
++	dsi.cache_cinfo = best;
++
++	return 0;
++}
++
++static int dsi_pll_calc_ddrfreq(unsigned long clk_freq,
++		struct dsi_clock_info *cinfo)
++{
++	struct dsi_clock_info cur, best;
++	const int use_dss2_fck = 1;
++	unsigned long datafreq;
++
++	DSSDBG("dsi_pll_calc_ddrfreq\n");
++
++	if (clk_freq == dsi.cache_clk_freq &&
++			dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
++		DSSDBG("DSI clock info found from cache\n");
++		*cinfo = dsi.cache_cinfo;
++		return 0;
++	}
++
++	datafreq = clk_freq * 4;
++
++	memset(&best, 0, sizeof(best));
++
++	memset(&cur, 0, sizeof(cur));
++	cur.use_dss2_fck = use_dss2_fck;
++	if (use_dss2_fck) {
++		cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
++		cur.highfreq = 0;
++	} else {
++		cur.clkin = dispc_pclk_rate();
++		if (cur.clkin < 32000000)
++			cur.highfreq = 0;
++		else
++			cur.highfreq = 1;
++	}
++
++	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++	for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++		if (cur.highfreq == 0)
++			cur.fint = cur.clkin / cur.regn;
++		else
++			cur.fint = cur.clkin / (2 * cur.regn);
++
++		if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++			continue;
++
++		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++		for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++			unsigned long a, b;
++
++			a = 2 * cur.regm * (cur.clkin/1000);
++			b = cur.regn * (cur.highfreq + 1);
++			cur.dsiphy = a / b * 1000;
++
++			if (cur.dsiphy > 1800 * 1000 * 1000)
++				break;
++
++			if (abs(cur.dsiphy - datafreq) <
++					abs(best.dsiphy - datafreq)) {
++				best = cur;
++				/* DSSDBG("best %ld\n", best.dsiphy); */
++			}
++
++			if (cur.dsiphy == datafreq)
++				goto found;
++		}
++	}
++found:
++	/* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3  < 173MHz */
++	/* hardcoded 48MHz for now. what should it be? */
++	best.regm3 = best.dsiphy / (48000000);
++	if (best.regm3 > REGM3_MAX)
++		best.regm3 = REGM3_MAX;
++	best.dispc_fck = best.dsiphy / best.regm3;
++
++	/* DSI2_PLL_FCLK(MHz) = DSIPHY(MHz) / regm4  < 173MHz */
++	/* hardcoded 48MHz for now. what should it be? */
++	best.regm4 = best.dsiphy / (48000000);
++	if (best.regm4 > REGM4_MAX)
++		best.regm4 = REGM4_MAX;
++	best.dsi_fck = best.dsiphy / best.regm4;
++
++	if (cinfo)
++		*cinfo = best;
++
++	dsi.cache_clk_freq = clk_freq;
++	dsi.cache_req_pck = 0;
++	dsi.cache_cinfo = best;
++
++	return 0;
++}
++
++int dsi_pll_program(struct dsi_clock_info *cinfo)
++{
++	int r = 0;
++	u32 l;
++
++	DSSDBG("dsi_pll_program\n");
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	dsi.dsiphy = cinfo->dsiphy;
++	dsi.ddr_clk = dsi.dsiphy / 4;
++	dsi.dsi1_pll_fclk = cinfo->dispc_fck;
++	dsi.dsi2_pll_fclk = cinfo->dsi_fck;
++
++	DSSDBG("DSI Fint %ld\n", cinfo->fint);
++
++	DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
++			cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
++			cinfo->clkin,
++			cinfo->highfreq);
++
++	/* DSIPHY == CLKIN4DDR */
++	DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
++			cinfo->regm,
++			cinfo->regn,
++			cinfo->clkin,
++			cinfo->highfreq + 1,
++			cinfo->dsiphy);
++
++	DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
++			dsi.dsiphy / 1000 / 1000 / 2);
++
++	DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
++
++	DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
++			cinfo->regm3, cinfo->dispc_fck);
++	DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
++			cinfo->regm4, cinfo->dsi_fck);
++
++	REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
++
++	l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
++	l = FLD_MOD(l, 1, 0, 0);		/* DSI_PLL_STOPMODE */
++	l = FLD_MOD(l, cinfo->regn - 1, 7, 1);	/* DSI_PLL_REGN */
++	l = FLD_MOD(l, cinfo->regm, 18, 8);	/* DSI_PLL_REGM */
++	l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19);	/* DSI_CLOCK_DIV */
++	l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23);	/* DSIPROTO_CLOCK_DIV */
++	dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
++
++	l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++	l = FLD_MOD(l, 7, 4, 1);		/* DSI_PLL_FREQSEL */
++	/* DSI_PLL_CLKSEL */
++	l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
++	l = FLD_MOD(l, cinfo->highfreq, 12, 12);	/* DSI_PLL_HIGHFREQ */
++	l = FLD_MOD(l, 1, 13, 13);		/* DSI_PLL_REFEN */
++	l = FLD_MOD(l, 0, 14, 14);		/* DSIPHY_CLKINEN */
++	l = FLD_MOD(l, 1, 20, 20);		/* DSI_HSDIVBYPASS */
++	dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++	REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
++
++	if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
++		DSSERR("dsi pll go bit not going down.\n");
++		r = -EIO;
++		goto err;
++	}
++
++	if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
++		DSSERR("cannot lock PLL\n");
++		r = -EIO;
++		goto err;
++	}
++
++	dsi.pll_locked = 1;
++
++	l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++	l = FLD_MOD(l, 0, 0, 0);	/* DSI_PLL_IDLE */
++	l = FLD_MOD(l, 0, 5, 5);	/* DSI_PLL_PLLLPMODE */
++	l = FLD_MOD(l, 0, 6, 6);	/* DSI_PLL_LOWCURRSTBY */
++	l = FLD_MOD(l, 0, 7, 7);	/* DSI_PLL_TIGHTPHASELOCK */
++	l = FLD_MOD(l, 0, 8, 8);	/* DSI_PLL_DRIFTGUARDEN */
++	l = FLD_MOD(l, 0, 10, 9);	/* DSI_PLL_LOCKSEL */
++	l = FLD_MOD(l, 1, 13, 13);	/* DSI_PLL_REFEN */
++	l = FLD_MOD(l, 1, 14, 14);	/* DSIPHY_CLKINEN */
++	l = FLD_MOD(l, 0, 15, 15);	/* DSI_BYPASSEN */
++	l = FLD_MOD(l, 1, 16, 16);	/* DSS_CLOCK_EN */
++	l = FLD_MOD(l, 0, 17, 17);	/* DSS_CLOCK_PWDN */
++	l = FLD_MOD(l, 1, 18, 18);	/* DSI_PROTO_CLOCK_EN */
++	l = FLD_MOD(l, 0, 19, 19);	/* DSI_PROTO_CLOCK_PWDN */
++	l = FLD_MOD(l, 0, 20, 20);	/* DSI_HSDIVBYPASS */
++	dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++	DSSDBG("PLL config done\n");
++err:
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++
++	return r;
++}
++
++int dsi_pll_init(int enable_hsclk, int enable_hsdiv)
++{
++	int r = 0;
++	enum dsi_pll_power_state pwstate;
++	struct dispc_clock_info cinfo;
++
++	DSSDBG("PLL init\n");
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	/* configure dispc fck and pixel clock to something sane */
++	r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
++	if (r)
++		return r;
++
++	r = dispc_set_clock_div(&cinfo);
++	if (r) {
++		DSSERR("Failed to set basic clocks\n");
++		return r;
++	}
++
++	/* PLL does not come out of reset without this... */
++	dispc_pck_free_enable(1);
++
++	if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
++		DSSERR("PLL not coming out of reset.\n");
++		r = -ENODEV;
++		goto err;
++	}
++
++	/* ... but if left on, we get problems when planes do not
++	 * fill the whole display. No idea about this XXX */
++	dispc_pck_free_enable(0);
++
++	if (enable_hsclk && enable_hsdiv)
++		pwstate = DSI_PLL_POWER_ON_ALL;
++	else if (enable_hsclk)
++		pwstate = DSI_PLL_POWER_ON_HSCLK;
++	else if (enable_hsdiv)
++		pwstate = DSI_PLL_POWER_ON_DIV;
++	else
++		pwstate = DSI_PLL_POWER_OFF;
++
++	r = dsi_pll_power(pwstate);
++
++	if (r)
++		goto err;
++
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++
++	DSSDBG("PLL init done\n");
++
++	return 0;
++err:
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++	return r;
++}
++
++void dsi_pll_uninit(void)
++{
++	dsi.pll_locked = 0;
++	dsi_pll_power(DSI_PLL_POWER_OFF);
++	DSSDBG("PLL uninit done\n");
++}
++
++unsigned long dsi_get_dsi1_pll_rate(void)
++{
++	return dsi.dsi1_pll_fclk;
++}
++
++unsigned long dsi_get_dsi2_pll_rate(void)
++{
++	return dsi.dsi2_pll_fclk;
++}
++
++ssize_t dsi_print_clocks(char *buf, ssize_t size)
++{
++	ssize_t l = 0;
++	int clksel;
++
++	enable_clocks(1);
++
++	clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
++
++	l += snprintf(buf + l, size - l, "- dsi -\n");
++
++	l += snprintf(buf + l, size - l, "dsi fclk source = %s\n",
++			dss_get_dsi_clk_source() == 0 ?
++			"dss1_alwon_fclk" : "dsi2_pll_fclk");
++
++	l += snprintf(buf + l, size - l, "dsi pll source = %s\n",
++			clksel == 0 ?
++			"dss2_alwon_fclk" : "pclkfree");
++
++	l += snprintf(buf + l, size - l,
++			"DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
++			dsi.dsiphy, dsi.ddr_clk);
++
++	l += snprintf(buf + l, size - l,
++			"dsi1_pll_fck\t%lu (%s)\n"
++			"dsi2_pll_fck\t%lu (%s)\n",
++			dsi.dsi1_pll_fclk,
++			dss_get_dispc_clk_source() == 0 ? "off" : "on",
++			dsi.dsi2_pll_fclk,
++			dss_get_dsi_clk_source() == 0 ? "off" : "on");
++
++	enable_clocks(0);
++
++	return l;
++}
++
++
++enum dsi_complexio_power_state {
++	DSI_COMPLEXIO_POWER_OFF		= 0x0,
++	DSI_COMPLEXIO_POWER_ON		= 0x1,
++	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
++};
++
++static int dsi_complexio_power(enum dsi_complexio_power_state state)
++{
++	int t = 0;
++
++	/* PWR_CMD */
++	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
++
++	/* PWR_STATUS */
++	while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
++		udelay(1);
++		if (t++ > 1000) {
++			DSSERR("failed to set complexio power state to "
++					"%d\n", state);
++			return -ENODEV;
++		}
++	}
++
++	return 0;
++}
++
++static void dsi_complexio_config(struct omap_display *display)
++{
++	u32 r;
++
++	int clk_lane   = display->hw_config.u.dsi.clk_lane;
++	int data1_lane = display->hw_config.u.dsi.data1_lane;
++	int data2_lane = display->hw_config.u.dsi.data2_lane;
++	int clk_pol    = display->hw_config.u.dsi.clk_pol;
++	int data1_pol  = display->hw_config.u.dsi.data1_pol;
++	int data2_pol  = display->hw_config.u.dsi.data2_pol;
++
++	r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++	r = FLD_MOD(r, clk_lane, 2, 0);
++	r = FLD_MOD(r, clk_pol, 3, 3);
++	r = FLD_MOD(r, data1_lane, 6, 4);
++	r = FLD_MOD(r, data1_pol, 7, 7);
++	r = FLD_MOD(r, data2_lane, 10, 8);
++	r = FLD_MOD(r, data2_pol, 11, 11);
++	dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
++
++	/* The configuration of the DSI complex I/O (number of data lanes,
++	   position, differential order) should not be changed while
++	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
++	   the hardware to take into account a new configuration of the complex
++	   I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
++	   follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
++	   then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
++	   DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
++	   DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
++	   DSI complex I/O configuration is unknown. */
++
++	/*
++	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++	REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
++	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
++	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++	*/
++}
++
++static inline int ns2ddr(int ns)
++{
++	/* convert time in ns to ddr ticks, rounding up */
++	return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
++}
++
++static void dsi_complexio_timings(void)
++{
++	u32 r;
++	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
++	u32 tlpx_half, tclk_trail, tclk_zero;
++	u32 tclk_prepare;
++
++	/* calculate timings */
++
++	/* 1 * DDR_CLK = 2 * UI */
++
++	/* min 40ns + 4*UI	max 85ns + 6*UI */
++	ths_prepare = ns2ddr(59) + 2;
++
++	/* min 145ns + 10*UI */
++	ths_prepare_ths_zero = ns2ddr(145) + 5;
++
++	/* min max(8*UI, 60ns+4*UI) */
++	ths_trail = max(4, ns2ddr(60) + 2);
++
++	/* min 100ns */
++	ths_exit = ns2ddr(100);
++
++	/* tlpx min 50n */
++	tlpx_half = ns2ddr(25);
++
++	/* min 60ns */
++	tclk_trail = ns2ddr(60);
++
++	/* min 38ns, max 95ns */
++	tclk_prepare = ns2ddr(38);
++
++	/* min tclk-prepare + tclk-zero = 300ns */
++	tclk_zero = ns2ddr(300 - 38);
++
++#ifdef VERBOSE
++	DSSDBG("ths_prepare %d, ths_prepare_ths_zero %d\n",
++		ths_prepare, ths_prepare_ths_zero);
++	DSSDBG("ths_trail %d, ths_exit %d\n", ths_trail, ths_exit);
++
++
++	DSSDBG("tlpx_half %d, tclk_trail %d, tclk_zero %d\n", tlpx_half,
++			tclk_trail, tclk_zero);
++	DSSDBG("tclk_prepare %d\n", tclk_prepare);
++#endif
++
++	/* program timings */
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG0);
++	r = FLD_MOD(r, ths_prepare, 31, 24);
++	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
++	r = FLD_MOD(r, ths_trail, 15, 8);
++	r = FLD_MOD(r, ths_exit, 7, 0);
++	dsi_write_reg(DSI_DSIPHY_CFG0, r);
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG1);
++	r = FLD_MOD(r, tlpx_half, 22, 16);
++	r = FLD_MOD(r, tclk_trail, 15, 8);
++	r = FLD_MOD(r, tclk_zero, 7, 0);
++	dsi_write_reg(DSI_DSIPHY_CFG1, r);
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG2);
++	r = FLD_MOD(r, tclk_prepare, 7, 0);
++	dsi_write_reg(DSI_DSIPHY_CFG2, r);
++}
++
++
++static int dsi_complexio_init(struct omap_display *display)
++{
++	int r = 0;
++
++	DSSDBG("dsi_complexio_init\n");
++
++	/* CIO_CLK_ICG, enable L3 clk to CIO */
++	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
++
++	/* A dummy read using the SCP interface to any DSIPHY register is
++	 * required after DSIPHY reset to complete the reset of the DSI complex
++	 * I/O. */
++	dsi_read_reg(DSI_DSIPHY_CFG5);
++
++	if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
++		DSSERR("ComplexIO PHY not coming out of reset.\n");
++		r = -ENODEV;
++		goto err;
++	}
++
++	dsi_complexio_config(display);
++
++	r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
++
++	if (r)
++		goto err;
++
++	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
++		DSSERR("ComplexIO not coming out of reset.\n");
++		r = -ENODEV;
++		goto err;
++	}
++
++	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
++		DSSERR("ComplexIO LDO power down.\n");
++		r = -ENODEV;
++		goto err;
++	}
++
++	dsi_complexio_timings();
++
++	/*
++	   The configuration of the DSI complex I/O (number of data lanes,
++	   position, differential order) should not be changed while
++	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
++	   hardware to recognize a new configuration of the complex I/O (done
++	   in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
++	   this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
++	   reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
++	   LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
++	   bit to 1. If the sequence is not followed, the DSi complex I/O
++	   configuration is undetermined.
++	   */
++	dsi_if_enable(1);
++	dsi_if_enable(0);
++	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
++	dsi_if_enable(1);
++	dsi_if_enable(0);
++
++	DSSDBG("CIO init done\n");
++err:
++	return r;
++}
++
++static void dsi_complexio_uninit(void)
++{
++	dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
++}
++
++
++
++static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
++		enum fifo_size size3, enum fifo_size size4)
++{
++	u32 r = 0;
++	int add = 0;
++	int i;
++
++	dsi.vc[0].fifo_size = size1;
++	dsi.vc[1].fifo_size = size2;
++	dsi.vc[2].fifo_size = size3;
++	dsi.vc[3].fifo_size = size4;
++
++	for (i = 0; i < 4; i++) {
++		u8 v;
++		int size = dsi.vc[i].fifo_size;
++
++		if (add + size > 4) {
++			DSSERR("Illegal FIFO configuration\n");
++			BUG();
++		}
++
++		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++		r |= v << (8 * i);
++		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
++		add += size;
++	}
++
++	dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
++}
++
++static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
++		enum fifo_size size3, enum fifo_size size4)
++{
++	u32 r = 0;
++	int add = 0;
++	int i;
++
++	dsi.vc[0].fifo_size = size1;
++	dsi.vc[1].fifo_size = size2;
++	dsi.vc[2].fifo_size = size3;
++	dsi.vc[3].fifo_size = size4;
++
++	for (i = 0; i < 4; i++) {
++		u8 v;
++		int size = dsi.vc[i].fifo_size;
++
++		if (add + size > 4) {
++			DSSERR("Illegal FIFO configuration\n");
++			BUG();
++		}
++
++		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++		r |= v << (8 * i);
++		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
++		add += size;
++	}
++
++	dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
++}
++
++static int dsi_force_tx_stop_mode_io(void)
++{
++	u32 r;
++
++	r = dsi_read_reg(DSI_TIMING1);
++	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
++	dsi_write_reg(DSI_TIMING1, r);
++
++	if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
++		DSSERR("TX_STOP bit not going down\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static void dsi_vc_print_status(int channel)
++{
++	u32 r;
++
++	r = dsi_read_reg(DSI_VC_CTRL(channel));
++	DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
++			"TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
++			channel,
++			FLD_GET(r, 5, 5),
++			FLD_GET(r, 6, 6),
++			FLD_GET(r, 15, 15),
++			FLD_GET(r, 16, 16),
++			FLD_GET(r, 20, 20));
++
++	r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
++	DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
++}
++
++static void dsi_vc_config(int channel)
++{
++	u32 r;
++
++	DSSDBG("dsi_vc_config %d\n", channel);
++
++	r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
++	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
++	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
++
++	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++	dsi_write_reg(DSI_VC_CTRL(channel), r);
++}
++
++static void dsi_vc_config_vp(int channel)
++{
++	u32 r;
++
++	DSSDBG("dsi_vc_config_vp\n");
++
++	r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++	r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
++	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
++	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++	r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
++
++	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++	dsi_write_reg(DSI_VC_CTRL(channel), r);
++}
++
++
++static int dsi_vc_enable(int channel, int enable)
++{
++	DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable);
++
++	enable = enable ? 1 : 0;
++
++	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
++
++	if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
++			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
++			return -EIO;
++	}
++
++	return 0;
++}
++
++static void dsi_vc_enable_hs(int channel, int enable)
++{
++	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
++
++	dsi_vc_enable(channel, 0);
++	dsi_if_enable(0);
++
++	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
++
++	dsi_vc_enable(channel, 1);
++	dsi_if_enable(1);
++
++	dsi_force_tx_stop_mode_io();
++}
++
++static void dsi_vc_flush_long_data(int channel)
++{
++	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++		u32 val;
++		val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
++				(val >> 0) & 0xff,
++				(val >> 8) & 0xff,
++				(val >> 16) & 0xff,
++				(val >> 24) & 0xff);
++	}
++}
++
++static u16 dsi_vc_flush_receive_data(int channel)
++{
++	/* RX_FIFO_NOT_EMPTY */
++	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++		u32 val;
++		u8 dt;
++		val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++		DSSDBG("\trawval %#08x\n", val);
++		dt = FLD_GET(val, 7, 0);
++		if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++			u16 err = FLD_GET(val, 23, 8);
++			DSSERR("\tACK with ERROR: %#x\n", err);
++			if (err & (1 << 9))
++				DSSERR("\t\tECC multibit\n");
++			if (err & (1 << 11))
++				DSSERR("\t\tData type not recognized\n");
++			if (err & (1 << 12))
++				DSSERR("\t\tInvalid VC ID\n");
++
++		} else if (dt == DSI_DT_RX_SHORT_READ_1) {
++			DSSDBG("\tDCS short response, 1 byte: %#x\n",
++					FLD_GET(val, 23, 8));
++			return FLD_GET(val, 23, 8);
++		} else if (dt == DSI_DT_RX_SHORT_READ_2) {
++			DSSDBG("\tDCS short response, 2 byte: %#x\n",
++					FLD_GET(val, 23, 8));
++			return FLD_GET(val, 23, 8);
++		} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++			DSSDBG("\tDCS long response, len %d\n",
++					FLD_GET(val, 23, 8));
++			dsi_vc_flush_long_data(channel);
++		} else {
++			DSSERR("\tunknown datatype\n");
++		}
++	}
++	return 0;
++}
++
++static int dsi_vc_send_bta(int channel)
++{
++	unsigned long tmo;
++
++	/*DSSDBG("dsi_vc_send_bta_sync %d\n", channel); */
++
++	if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {	/* RX_FIFO_NOT_EMPTY */
++		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
++		dsi_vc_flush_receive_data(channel);
++	}
++
++	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
++
++	tmo = jiffies + msecs_to_jiffies(10);
++	while (REG_GET(DSI_VC_CTRL(channel), 6, 6) == 1) {
++		if (time_after(jiffies, tmo)) {
++			DSSERR("Failed to send BTA\n");
++			return -EIO;
++		}
++	}
++
++	return 0;
++}
++
++static int dsi_vc_send_bta_sync(int channel)
++{
++	int r = 0;
++
++	init_completion(&dsi.bta_completion);
++
++	dsi_vc_enable_bta_irq(channel);
++
++	r = dsi_vc_send_bta(channel);
++	if (r)
++		goto err;
++
++	if (wait_for_completion_timeout(&dsi.bta_completion,
++				msecs_to_jiffies(500)) == 0) {
++		DSSERR("Failed to receive BTA\n");
++		r = -EIO;
++		goto err;
++	}
++err:
++	dsi_vc_disable_bta_irq(channel);
++
++	return r;
++}
++
++static inline void dsi_vc_write_long_header(int channel, u8 data_type,
++		u16 len, u8 ecc)
++{
++	u32 val;
++	u8 data_id;
++
++	/*data_id = data_type | channel << 6; */
++	data_id = data_type | dsi.vc[channel].dest_per << 6;
++
++	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
++		FLD_VAL(ecc, 31, 24);
++
++	dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
++}
++
++static inline void dsi_vc_write_long_payload(int channel,
++		u8 b1, u8 b2, u8 b3, u8 b4)
++{
++	u32 val;
++
++	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
++
++/*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
++			b1, b2, b3, b4, val); */
++
++	dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
++}
++
++static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
++		u8 ecc)
++{
++	/*u32 val; */
++	int i;
++	u8 *p;
++	int r = 0;
++	u8 b1, b2, b3, b4;
++
++	/*DSSDBG("dsi_vc_send_long, %d bytes\n", len); */
++
++	/* len + header */
++	if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
++		DSSERR("unable to send long packet: packet too long.\n");
++		return -EINVAL;
++	}
++
++	dsi_vc_write_long_header(channel, data_type, len, ecc);
++
++	/*dsi_vc_print_status(0); */
++
++	p = data;
++	for (i = 0; i < len >> 2; i++) {
++		/*DSSDBG("\tsending full packet %d\n", i); */
++		/*dsi_vc_print_status(0); */
++
++		b1 = *p++;
++		b2 = *p++;
++		b3 = *p++;
++		b4 = *p++;
++
++		dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
++	}
++
++	i = len % 4;
++	if (i) {
++		b1 = 0; b2 = 0; b3 = 0;
++
++		/*DSSDBG("\tsending remainder bytes %d\n", i); */
++
++		switch (i) {
++		case 3:
++			b1 = *p++;
++			b2 = *p++;
++			b3 = *p++;
++			break;
++		case 2:
++			b1 = *p++;
++			b2 = *p++;
++			break;
++		case 1:
++			b1 = *p++;
++			break;
++		}
++
++		dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
++	}
++
++	return r;
++}
++
++static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
++{
++	u32 r;
++	u8 data_id;
++/*
++	DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
++			channel,
++			data_type, data & 0xff, (data >> 8) & 0xff);
++*/
++	if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
++		DSSERR("ERROR FIFO FULL, aborting transfer\n");
++		return -EINVAL;
++	}
++
++	data_id = data_type | channel << 6;
++
++	r = (data_id << 0) | (data << 8) | (ecc << 24);
++
++	dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
++
++	return 0;
++}
++
++int dsi_vc_send_null(int channel)
++{
++	u8 nullpkg[] = {0, 0, 0, 0};
++	return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
++}
++EXPORT_SYMBOL(dsi_vc_send_null);
++
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
++{
++	int r;
++
++	BUG_ON(len == 0);
++
++	if (len == 1) {
++		r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
++				data[0], 0);
++	} else if (len == 2) {
++		r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
++				data[0] | (data[1] << 8), 0);
++	} else {
++		/* 0x39 = DCS Long Write */
++		r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
++				data, len, 0);
++	}
++
++	return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
++
++int dsi_vc_dcs_write(int channel, u8 *data, int len)
++{
++	int r;
++
++	r = dsi_vc_dcs_write_nosync(channel, data, len);
++	if (r)
++		return r;
++
++	/* Some devices need time to process the msg in low power mode.
++	   This also makes the write synchronous, and checks that
++	   the peripheral is still alive */
++	r = dsi_vc_send_bta_sync(channel);
++
++	return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write);
++
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
++{
++	u32 val;
++	u8 dt;
++	int debug = 0;
++
++	if (debug)
++		DSSDBG("dsi_vc_dcs_read\n");
++
++	dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
++
++	dsi_vc_send_bta_sync(channel);
++
++	val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++	if (debug)
++		DSSDBG("\trawval %#08x\n", val);
++	dt = FLD_GET(val, 7, 0);
++	if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++		u16 err = FLD_GET(val, 23, 8);
++		DSSERR("\tACK with ERROR: %#x\n", err);
++		if (err & (1 << 9))
++			DSSERR("\t\tECC multibit\n");
++		if (err & (1 << 11))
++			DSSERR("\t\tData type not recognized\n");
++		if (err & (1 << 12))
++			DSSERR("\t\tInvalid VC ID\n");
++		return -1;
++
++	} else if (dt == DSI_DT_RX_SHORT_READ_1) {
++		u8 data = FLD_GET(val, 15, 8);
++		if (debug)
++			DSSDBG("\tDCS short response, 1 byte: %#x\n", data);
++
++		if (buflen < 1)
++			return -1;
++
++		buf[0] = data;
++
++		return 1;
++	} else if (dt == DSI_DT_RX_SHORT_READ_2) {
++		u16 data = FLD_GET(val, 23, 8);
++		if (debug)
++			DSSDBG("\tDCS short response, 2 byte: %#x\n", data);
++
++		if (buflen < 2)
++			return -1;
++
++		buf[0] = data & 0xff;
++		buf[1] = (data >> 8) & 0xff;
++
++		return 2;
++	} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++		int x;
++		int len = FLD_GET(val, 23, 8);
++		if (debug)
++			DSSDBG("\tDCS long response, len %d\n", len);
++
++		if (len > buflen)
++			return -1;
++
++		x = 0;
++		while (x < len) {
++			val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++			if (debug)
++				DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 "
++						"%#02x\n",
++						(val >> 0) & 0xff,
++						(val >> 8) & 0xff,
++						(val >> 16) & 0xff,
++						(val >> 24) & 0xff);
++
++			if (x < len)
++				buf[x++] = (val >> 0) & 0xff;
++			if (x < len)
++				buf[x++] = (val >> 8) & 0xff;
++			if (x < len)
++				buf[x++] = (val >> 16) & 0xff;
++			if (x < len)
++				buf[x++] = (val >> 24) & 0xff;
++		}
++
++		return len;
++	} else {
++		DSSERR("\tunknown datatype\n");
++		return -1;
++	}
++}
++EXPORT_SYMBOL(dsi_vc_dcs_read);
++
++
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
++{
++	return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
++			len, 0);
++}
++EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
++
++
++static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
++{
++	u32 r;
++	unsigned long fck;
++	int ticks;
++
++	/* ticks in DSI_FCK */
++
++	fck = dsi_fclk_rate();
++	ticks = (fck / 1000 / 1000) * ns / 1000;
++
++	if (ticks > 0x1fff) {
++		DSSERR("LP_TX_TO too high\n");
++		return -EINVAL;
++	}
++
++	r = dsi_read_reg(DSI_TIMING2);
++	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
++	r = FLD_MOD(r, x16, 14, 14);	/* LP_RX_TO_X16 */
++	r = FLD_MOD(r, x4, 13, 13);	/* LP_RX_TO_X4 */
++	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
++	dsi_write_reg(DSI_TIMING2, r);
++
++	DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
++			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++			(fck / 1000 / 1000),
++			ticks);
++
++	return 0;
++}
++
++static int dsi_set_ta_timeout(int ns, int x8, int x16)
++{
++	u32 r;
++	unsigned long fck;
++	int ticks;
++
++	/* ticks in DSI_FCK */
++
++	fck = dsi_fclk_rate();
++	ticks = (fck / 1000 / 1000) * ns / 1000;
++
++	if (ticks > 0x1fff) {
++		DSSERR("TA_TO too high\n");
++		return -EINVAL;
++	}
++
++	r = dsi_read_reg(DSI_TIMING1);
++	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
++	r = FLD_MOD(r, x16, 30, 30);	/* TA_TO_X16 */
++	r = FLD_MOD(r, x8, 29, 29);	/* TA_TO_X8 */
++	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
++	dsi_write_reg(DSI_TIMING1, r);
++
++	DSSDBG("TA_TO %ld ns (%#x ticks)\n",
++			(ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
++			(fck / 1000 / 1000),
++			ticks);
++
++	return 0;
++}
++
++static int dsi_set_stop_state_counter(int ns, int x4, int x16)
++{
++	u32 r;
++	unsigned long fck;
++	int ticks;
++
++	/* ticks in DSI_FCK */
++
++	fck = dsi_fclk_rate();
++	ticks = (fck / 1000 / 1000) * ns / 1000;
++
++	if (ticks > 0x1fff) {
++		DSSERR("STOP_STATE_COUNTER_IO too high\n");
++		return -EINVAL;
++	}
++
++	r = dsi_read_reg(DSI_TIMING1);
++	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
++	r = FLD_MOD(r, x16, 14, 14);	/* STOP_STATE_X16_IO */
++	r = FLD_MOD(r, x4, 13, 13);	/* STOP_STATE_X4_IO */
++	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
++	dsi_write_reg(DSI_TIMING1, r);
++
++	DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
++			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++			(fck / 1000 / 1000),
++			ticks);
++
++	return 0;
++}
++
++static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
++{
++	u32 r;
++	unsigned long fck;
++	int ticks;
++
++	/* ticks in TxByteClkHS */
++
++	fck = dsi.ddr_clk / 4;
++	ticks = (fck / 1000 / 1000) * ns / 1000;
++
++	if (ticks > 0x1fff) {
++		DSSERR("HS_TX_TO too high\n");
++		return -EINVAL;
++	}
++
++	r = dsi_read_reg(DSI_TIMING2);
++	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
++	r = FLD_MOD(r, x16, 30, 30);	/* HS_TX_TO_X16 */
++	r = FLD_MOD(r, x4, 29, 29);	/* HS_TX_TO_X8 (4 really) */
++	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
++	dsi_write_reg(DSI_TIMING2, r);
++
++	DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
++			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++			(fck / 1000 / 1000),
++			ticks);
++
++	return 0;
++}
++static int dsi_proto_config(struct omap_display *display)
++{
++	u32 r;
++	int buswidth = 0;
++
++	dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
++			DSI_FIFO_SIZE_0,
++			DSI_FIFO_SIZE_0,
++			DSI_FIFO_SIZE_0);
++
++	dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
++			DSI_FIFO_SIZE_0,
++			DSI_FIFO_SIZE_0,
++			DSI_FIFO_SIZE_0);
++
++	/* XXX what values for the timeouts? */
++	dsi_set_stop_state_counter(1000, 0, 0);
++
++	dsi_set_ta_timeout(50000, 1, 1);
++
++	/* 3000ns * 16 */
++	dsi_set_lp_rx_timeout(3000, 0, 1);
++
++	/* 10000ns * 4 */
++	dsi_set_hs_tx_timeout(10000, 1, 0);
++
++	switch (display->ctrl->pixel_size) {
++	case 16:
++		buswidth = 0;
++		break;
++	case 18:
++		buswidth = 1;
++		break;
++	case 24:
++		buswidth = 2;
++		break;
++	default:
++		BUG();
++	}
++
++	r = dsi_read_reg(DSI_CTRL);
++	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
++	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
++	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
++	/* XXX what should the ratio be */
++	r = FLD_MOD(r, 0, 4, 4);	/* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
++	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
++	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
++	r = FLD_MOD(r, 2, 13, 12);	/* LINE_BUFFER, 2 lines */
++	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
++	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
++	r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
++	r = FLD_MOD(r, 0, 25, 25);	/* DCS_CMD_CODE, 1=start, 0=continue */
++
++	dsi_write_reg(DSI_CTRL, r);
++
++	/* we configure vc0 for L4 communication, and
++	 * vc1 for dispc */
++	dsi_vc_config(0);
++	dsi_vc_config_vp(1);
++
++	/* set all vc targets to peripheral 0 */
++	dsi.vc[0].dest_per = 0;
++	dsi.vc[1].dest_per = 0;
++	dsi.vc[2].dest_per = 0;
++	dsi.vc[3].dest_per = 0;
++
++	return 0;
++}
++
++static void dsi_proto_timings(void)
++{
++	int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
++	int tclk_pre, tclk_post;
++	int ddr_clk_pre, ddr_clk_post;
++	u32 r;
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG1);
++	tlpx_half = FLD_GET(r, 22, 16);
++	tclk_trail = FLD_GET(r, 15, 8);
++	tclk_zero = FLD_GET(r, 7, 0);
++
++	r = dsi_read_reg(DSI_DSIPHY_CFG2);
++	tclk_prepare = FLD_GET(r, 7, 0);
++
++	/* min 8*UI */
++	tclk_pre = 20;
++	/* min 60ns + 52*UI */
++	tclk_post = ns2ddr(60) + 26;
++
++	ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
++	ddr_clk_post = (tclk_post + tclk_trail) / 4;
++
++	r = dsi_read_reg(DSI_CLK_TIMING);
++	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
++	r = FLD_MOD(r, ddr_clk_post, 7, 0);
++	dsi_write_reg(DSI_CLK_TIMING, r);
++
++#ifdef VERBOSE
++	DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
++			ddr_clk_pre,
++			ddr_clk_post);
++#endif
++}
++
++
++#define DSI_DECL_VARS \
++	int __dsi_cb = 0; u32 __dsi_cv = 0;
++
++#define DSI_FLUSH(ch) \
++	if (__dsi_cb > 0) { \
++		/*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
++		dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
++		__dsi_cb = __dsi_cv = 0; \
++	}
++
++#define DSI_PUSH(ch, data) \
++	do { \
++		__dsi_cv |= (data) << (__dsi_cb * 8); \
++		/*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
++		if (++__dsi_cb > 3) \
++			DSI_FLUSH(ch); \
++	} while (0)
++
++static int dsi_update_screen_l4(struct omap_display *display,
++			int x, int y, int w, int h)
++{
++	/* Note: supports only 24bit colors in 32bit container */
++	int first = 1;
++	int fifo_stalls = 0;
++	int max_dsi_packet_size;
++	int max_data_per_packet;
++	int max_pixels_per_packet;
++	int pixels_left;
++	int bytespp = 3;
++	int scr_width;
++	u32 *data;
++	int start_offset;
++	int horiz_inc;
++	int current_x;
++	struct omap_overlay *ovl;
++
++	debug_irq = 0;
++
++	DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
++			x, y, w, h);
++
++	ovl = &display->manager->overlays[0];
++
++	if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
++		return -EINVAL;
++
++	if (display->ctrl->pixel_size != 24)
++		return -EINVAL;
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	scr_width = ovl->info.screen_width;
++	data = ovl->info.vaddr;
++
++	start_offset = scr_width * y + x;
++	horiz_inc = scr_width - w;
++	current_x = x;
++
++	/* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
++	 * in fifo */
++
++	/* When using CPU, max long packet size is TX buffer size */
++	max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
++
++	/* we seem to get better perf if we divide the tx fifo to half,
++	   and while the other half is being sent, we fill the other half
++	   max_dsi_packet_size /= 2; */
++
++	max_data_per_packet = max_dsi_packet_size - 4 - 1;
++
++	max_pixels_per_packet = max_data_per_packet / bytespp;
++
++	DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
++
++	display->ctrl->setup_update(display, x, y, w, h);
++
++	pixels_left = w * h;
++
++	DSSDBG("total pixels %d\n", pixels_left);
++
++	data += start_offset;
++
++	dsi.update_region.x = x;
++	dsi.update_region.y = y;
++	dsi.update_region.w = w;
++	dsi.update_region.h = h;
++	dsi.update_region.bytespp = bytespp;
++
++	perf_mark_start();
++
++	while (pixels_left > 0) {
++		/* 0x2c = write_memory_start */
++		/* 0x3c = write_memory_continue */
++		u8 dcs_cmd = first ? 0x2c : 0x3c;
++		int pixels;
++		DSI_DECL_VARS;
++		first = 0;
++
++#if 1
++		/* using fifo not empty */
++		/* TX_FIFO_NOT_EMPTY */
++		while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
++			udelay(1);
++			fifo_stalls++;
++			if (fifo_stalls > 0xfffff) {
++				DSSERR("fifo stalls overflow, pixels left %d\n",
++						pixels_left);
++				dsi_if_enable(0);
++				enable_clocks(0);
++				return -EIO;
++			}
++		}
++#elif 1
++		/* using fifo emptiness */
++		while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
++				max_dsi_packet_size) {
++			fifo_stalls++;
++			if (fifo_stalls > 0xfffff) {
++				DSSERR("fifo stalls overflow, pixels left %d\n",
++					       pixels_left);
++				dsi_if_enable(0);
++				enable_clocks(0);
++				return -EIO;
++			}
++		}
++#else
++		while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
++			fifo_stalls++;
++			if (fifo_stalls > 0xfffff) {
++				DSSERR("fifo stalls overflow, pixels left %d\n",
++					       pixels_left);
++				dsi_if_enable(0);
++				enable_clocks(0);
++				return -EIO;
++			}
++		}
++#endif
++		pixels = min(max_pixels_per_packet, pixels_left);
++
++		pixels_left -= pixels;
++
++		dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
++				1 + pixels * bytespp, 0);
++
++		DSI_PUSH(0, dcs_cmd);
++
++		while (pixels-- > 0) {
++			u32 pix = *data++;
++
++			DSI_PUSH(0, (pix >> 16) & 0xff);
++			DSI_PUSH(0, (pix >> 8) & 0xff);
++			DSI_PUSH(0, (pix >> 0) & 0xff);
++
++			current_x++;
++			if (current_x == x+w) {
++				current_x = x;
++				data += horiz_inc;
++			}
++		}
++
++		DSI_FLUSH(0);
++	}
++
++	perf_show("L4");
++
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++
++	return 0;
++}
++
++#if 0
++static void dsi_clear_screen_l4(struct omap_display *display,
++			int x, int y, int w, int h)
++{
++	int first = 1;
++	int fifo_stalls = 0;
++	int max_dsi_packet_size;
++	int max_data_per_packet;
++	int max_pixels_per_packet;
++	int pixels_left;
++	int bytespp = 3;
++	int pixnum;
++
++	debug_irq = 0;
++
++	DSSDBG("dsi_clear_screen_l4 (%d,%d %dx%d)\n",
++			x, y, w, h);
++
++	if (display->ctrl->bpp != 24)
++		return -EINVAL;
++
++	/* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp)
++	 * bytes in fifo */
++
++	/* When using CPU, max long packet size is TX buffer size */
++	max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
++
++	max_data_per_packet = max_dsi_packet_size - 4 - 1;
++
++	max_pixels_per_packet = max_data_per_packet / bytespp;
++
++	enable_clocks(1);
++
++	display->ctrl->setup_update(display, x, y, w, h);
++
++	pixels_left = w * h;
++
++	dsi.update_region.x = x;
++	dsi.update_region.y = y;
++	dsi.update_region.w = w;
++	dsi.update_region.h = h;
++	dsi.update_region.bytespp = bytespp;
++
++	start_measuring();
++
++	pixnum = 0;
++
++	while (pixels_left > 0) {
++		/* 0x2c = write_memory_start */
++		/* 0x3c = write_memory_continue */
++		u8 dcs_cmd = first ? 0x2c : 0x3c;
++		int pixels;
++		DSI_DECL_VARS;
++		first = 0;
++
++		/* TX_FIFO_NOT_EMPTY */
++		while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
++			fifo_stalls++;
++			if (fifo_stalls > 0xfffff) {
++				DSSERR("fifo stalls overflow\n");
++				dsi_if_enable(0);
++				enable_clocks(0);
++				return;
++			}
++		}
++
++		pixels = min(max_pixels_per_packet, pixels_left);
++
++		pixels_left -= pixels;
++
++		dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
++				1 + pixels * bytespp, 0);
++
++		DSI_PUSH(0, dcs_cmd);
++
++		while (pixels-- > 0) {
++			u32 pix;
++
++			pix = 0x000000;
++
++			DSI_PUSH(0, (pix >> 16) & 0xff);
++			DSI_PUSH(0, (pix >> 8) & 0xff);
++			DSI_PUSH(0, (pix >> 0) & 0xff);
++		}
++
++		DSI_FLUSH(0);
++	}
++
++	enable_clocks(0);
++
++	end_measuring("L4 CLEAR");
++}
++#endif
++
++static int dsi_wait_for_framedone(int stop_update)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&dsi.update_lock, flags);
++	if (dsi.update_ongoing) {
++		long wait = msecs_to_jiffies(1000);
++		dsi.update_syncers++;
++		if (stop_update)
++			dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
++		spin_unlock_irqrestore(&dsi.update_lock, flags);
++		wait = wait_for_completion_timeout(&dsi.update_completion,
++				wait);
++		if (wait == 0) {
++			DSSERR("timeout waiting sync\n");
++			return -ETIME;
++		}
++	} else {
++		spin_unlock_irqrestore(&dsi.update_lock, flags);
++	}
++
++	return 0;
++}
++
++static void dsi_setup_update_dispc(struct omap_display *display,
++			int x, int y, int w, int h)
++{
++	int bytespp = 3;
++
++	DSSDBG("dsi_setup_update_dispc(%d,%d %dx%d)\n",
++			x, y, w, h);
++
++	dsi.update_region.display = display;
++	dsi.update_region.x = x;
++	dsi.update_region.y = y;
++	dsi.update_region.w = w;
++	dsi.update_region.h = h;
++	dsi.update_region.bytespp = bytespp;
++
++	enable_clocks(1);
++
++	dispc_setup_partial_planes(display, &x, &y, &w, &h);
++
++	dispc_set_lcd_size(w, h);
++
++	enable_clocks(0);
++}
++
++static void dsi_update_screen_dispc(struct omap_display *display)
++{
++	int bytespp = 3;
++	int total_len;
++	int line_packet_len;
++	int x, y, w, h;
++	u32 l;
++
++	x = dsi.update_region.x;
++	y = dsi.update_region.y;
++	w = dsi.update_region.w;
++	h = dsi.update_region.h;
++
++	if (dsi.user_update_mode != OMAP_DSS_UPDATE_AUTO)
++		DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
++				x, y, w, h);
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	/* TODO: one packet could be longer, I think? Max is the line buffer */
++	line_packet_len = w * bytespp + 1;	/* 1 byte for DCS cmd */
++	total_len = line_packet_len * h;
++
++	display->ctrl->setup_update(display, x, y, w, h);
++
++	if (0)
++		dsi_vc_print_status(1);
++
++	perf_mark_start();
++
++	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
++	dsi_write_reg(DSI_VC_TE(1), l);
++
++	dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
++
++	if (dsi.use_te)
++		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
++	else
++		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
++	dsi_write_reg(DSI_VC_TE(1), l);
++
++	dispc_enable_lcd_out(1);
++
++	if (dsi.use_te)
++		dsi_vc_send_bta(1);
++}
++
++static void framedone_callback(void *data, u32 mask)
++{
++	if (dsi.framedone_scheduled) {
++		DSSERR("Framedone already scheduled. Bogus FRAMEDONE IRQ?\n");
++		return;
++	}
++
++	dsi.framedone_scheduled = 1;
++
++	/* We get FRAMEDONE when DISPC has finished sending pixels and turns
++	 * itself off. However, DSI still has the pixels in its buffers, and
++	 * is sending the data. Thus we have to wait until we can do a new
++	 * transfer or turn the clocks off. We do that in a separate work
++	 * func. */
++	/* XXX When using auto update and delay value 0, the kernel seems to be
++	 * very relaxed about when to call our callback. It may take a second.
++	 * Thus we use a delay of 1 */
++	if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++		schedule_delayed_work(&dsi.framedone_work, 1);
++	else
++		schedule_delayed_work(&dsi.framedone_work, 0);
++}
++
++static void framedone_worker(struct work_struct *work)
++{
++	unsigned long flags;
++	u32 l;
++	unsigned long tmo;
++	int i = 0;
++
++	l = REG_GET(DSI_VC_TE(1), 23, 0); /* TE_SIZE */
++
++	/* There shouldn't be much stuff in DSI buffers, if any, so we'll
++	 * just busyloop */
++	if (l > 0) {
++		tmo = jiffies + msecs_to_jiffies(50);
++		while (REG_GET(DSI_VC_TE(1), 23, 0) > 0) { /* TE_SIZE */
++			i++;
++			if (time_after(jiffies, tmo)) {
++				DSSERR("timeout waiting TE_SIZE to zero\n");
++				break;
++			}
++			cpu_relax();
++		}
++	}
++
++	if (REG_GET(DSI_VC_TE(1), 30, 30))
++		DSSERR("TE_EN not zero\n");
++
++	if (REG_GET(DSI_VC_TE(1), 31, 31))
++		DSSERR("TE_START not zero\n");
++
++	spin_lock_irqsave(&dsi.update_lock, flags);
++	if (dsi.update_ongoing == 0) {
++		spin_unlock_irqrestore(&dsi.update_lock, flags);
++		DSSERR("framedone irq without update request\n");
++		return;
++	}
++	spin_unlock_irqrestore(&dsi.update_lock, flags);
++
++	perf_show("DISPC");
++
++	if (dsi.user_update_mode != OMAP_DSS_UPDATE_AUTO)
++		DSSDBG("FRAMEDONE\n");
++
++#if 0
++	if (l)
++		DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
++#else
++	if (l > 1024*3)
++		DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
++#endif
++
++#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
++	dispc_fake_vsync_irq();
++#endif
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++
++	dsi.framedone_scheduled = 0;
++
++	spin_lock_irqsave(&dsi.update_lock, flags);
++
++	if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
++		dsi.update_ongoing = 0;
++
++	while (dsi.update_syncers > 0) {
++		complete(&dsi.update_completion);
++		--dsi.update_syncers;
++	}
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++		spin_unlock_irqrestore(&dsi.update_lock, flags);
++		dsi_update_screen_dispc(dsi.update_region.display);
++	} else {
++		spin_unlock_irqrestore(&dsi.update_lock, flags);
++	}
++}
++
++static void dsi_start_auto_update(struct omap_display *display)
++{
++	unsigned long flags;
++	int bytespp = 3;
++
++	DSSDBG("starting auto update\n");
++
++	dsi.update_region.display = display;
++	dsi.update_region.x = 0;
++	dsi.update_region.y = 0;
++	dsi.update_region.w = display->panel->timings.x_res;
++	dsi.update_region.h = display->panel->timings.y_res;
++	dsi.update_region.bytespp = bytespp;
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	dispc_set_lcd_size(display->panel->timings.x_res,
++			display->panel->timings.y_res);
++
++	spin_lock_irqsave(&dsi.update_lock, flags);
++	dsi.update_ongoing = 1;
++	spin_unlock_irqrestore(&dsi.update_lock, flags);
++	dsi_update_screen_dispc(display);
++}
++
++static void dsi_stop_auto_update(void)
++{
++	DSSDBG("waiting for display to finish.\n");
++	dsi_wait_for_framedone(1);
++	DSSDBG("done waiting\n");
++
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++}
++
++static int dsi_set_update_mode(struct omap_display *display,
++		enum omap_dss_update_mode mode)
++{
++	if (mode == dsi.update_mode)
++		return 0;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++		dsi_stop_auto_update();
++	else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
++		dsi_wait_for_framedone(0);
++
++	dsi.update_mode = mode;
++
++	if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++		dsi_start_auto_update(display);
++
++	return 0;
++}
++
++/* Display funcs */
++
++static int dsi_display_enable(struct omap_display *display)
++{
++	int r = 0;
++	struct dsi_clock_info cinfo;
++	u32 low, high;
++
++	DSSDBG("dsi_display_enable\n");
++
++	mutex_lock(&dsi.lock);
++
++	if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++		DSSERR("display already enabled\n");
++		r = -EINVAL;
++		goto err0;
++	}
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	r = omap_dispc_register_isr(framedone_callback, NULL,
++			DISPC_IRQ_FRAMEDONE);
++	if (r) {
++		DSSERR("can't get FRAMEDONE irq\n");
++		goto err1;
++	}
++
++	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++
++	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
++	dispc_enable_fifohandcheck(1);
++
++	dispc_set_burst_size(OMAP_DSS_GFX, OMAP_DSS_BURST_16x32);
++	dispc_set_burst_size(OMAP_DSS_VIDEO1, OMAP_DSS_BURST_16x32);
++	dispc_set_burst_size(OMAP_DSS_VIDEO2, OMAP_DSS_BURST_16x32);
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_GFX) - (16*32/8);
++	low = 0;
++	dispc_setup_plane_fifo(OMAP_DSS_GFX, low, high);
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO1) - (16*32/8);
++	low = 0;
++	dispc_setup_plane_fifo(OMAP_DSS_VIDEO1, low, high);
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO2) - (16*32/8);
++	low = 0;
++	dispc_setup_plane_fifo(OMAP_DSS_VIDEO2, low, high);
++
++	dispc_set_tft_data_lines(display->ctrl->pixel_size);
++
++	{
++		struct omap_video_timings timings = {
++			.hsw		= 1,
++			.hfp		= 1,
++			.hbp		= 1,
++			.vsw		= 1,
++			.vfp		= 0,
++			.vbp		= 0,
++		};
++
++		dispc_set_lcd_timings(&timings);
++	}
++
++	_dsi_print_reset_status();
++
++	r = dsi_pll_init(1, 0);
++	if (r)
++		goto err2;
++
++	r = dsi_pll_calc_ddrfreq(display->hw_config.u.dsi.ddr_clk_hz, &cinfo);
++	if (r)
++		goto err3;
++
++	r = dsi_pll_program(&cinfo);
++	if (r)
++		goto err3;
++
++	DSSDBG("PLL OK\n");
++
++	r = dsi_complexio_init(display);
++	if (r)
++		goto err3;
++
++	_dsi_print_reset_status();
++
++	dsi_proto_timings();
++	dsi_set_lp_clk_divisor();
++
++	if (1)
++		_dsi_print_reset_status();
++
++	r = dsi_proto_config(display);
++	if (r)
++		goto err4;
++
++	/* enable interface */
++	dsi_vc_enable(0, 1);
++	dsi_vc_enable(1, 1);
++	dsi_if_enable(1);
++	dsi_force_tx_stop_mode_io();
++
++
++	if (display->ctrl && display->ctrl->enable) {
++		r = display->ctrl->enable(display);
++		if (r)
++			goto err5;
++	}
++
++	if (display->panel && display->panel->enable) {
++		r = display->panel->enable(display);
++		if (r)
++			goto err6;
++	}
++
++	if (dsi.use_te) {
++		r = display->ctrl->enable_te(display, 1);
++		if (r)
++			goto err7;
++	}
++
++	/* enable high-speed after initial config */
++	dsi_vc_enable_hs(0, 1);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	dsi_set_update_mode(display, dsi.user_update_mode);
++
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++	mutex_unlock(&dsi.lock);
++
++	return 0;
++err7:
++	if (display->panel && display->panel->disable)
++		display->panel->disable(display);
++err6:
++	if (display->ctrl && display->ctrl->disable)
++		display->ctrl->disable(display);
++err5:
++	dsi_if_enable(0);
++err4:
++	dsi_complexio_uninit();
++err3:
++	dsi_pll_uninit();
++err2:
++	omap_dispc_unregister_isr(framedone_callback);
++err1:
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++err0:
++	mutex_unlock(&dsi.lock);
++	DSSDBG("dsi_display_enable FAILED\n");
++	return r;
++}
++
++static void dsi_display_disable(struct omap_display *display)
++{
++	DSSDBG("dsi_display_disable\n");
++
++	mutex_lock(&dsi.lock);
++
++	if (display->state == OMAP_DSS_DISPLAY_DISABLED)
++		goto end;
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	dsi_set_update_mode(display, OMAP_DSS_UPDATE_DISABLED);
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++
++	omap_dispc_unregister_isr(framedone_callback);
++
++	if (display->panel && display->panel->disable)
++		display->panel->disable(display);
++	if (display->ctrl && display->ctrl->disable)
++		display->ctrl->disable(display);
++
++	dsi_complexio_uninit();
++	dsi_pll_uninit();
++
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++end:
++	mutex_unlock(&dsi.lock);
++}
++
++static int dsi_display_suspend(struct omap_display *display)
++{
++	if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++		return -EINVAL;
++
++	if (display->panel->suspend)
++		display->panel->suspend(display);
++
++	if (display->ctrl->suspend)
++		display->ctrl->suspend(display);
++
++	display->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++	return 0;
++}
++
++static int dsi_display_resume(struct omap_display *display)
++{
++	if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
++		return -EINVAL;
++
++	if (display->panel->resume)
++		display->panel->resume(display);
++
++	if (display->ctrl->resume)
++		display->ctrl->resume(display);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	return 0;
++}
++
++static int dsi_display_update(struct omap_display *display,
++			int x, int y, int w, int h)
++{
++	unsigned long flags;
++	int r = 0;
++
++	DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
++
++	if (w == 0 || h == 0)
++		return 0;
++
++	mutex_lock(&dsi.lock);
++
++	if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
++		goto end; /* XXX return error? */
++
++	spin_lock_irqsave(&dsi.update_lock, flags);
++
++	if (dsi.update_ongoing) {
++		spin_unlock_irqrestore(&dsi.update_lock, flags);
++		DSSERR("DSI is busy\n");
++		r = -EBUSY;
++		goto end;
++	}
++
++	perf_mark_setup();
++
++	dsi.update_ongoing = 1;
++
++	if (dsi.update_syncers > 0)
++		DSSERR("someone waiting for sync, and no update ongoing\n");
++
++	spin_unlock_irqrestore(&dsi.update_lock, flags);
++
++	if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++		dsi_setup_update_dispc(display, x, y, w, h);
++		dsi_update_screen_dispc(display);
++	} else {
++		r = dsi_update_screen_l4(display, x, y, w, h);
++		if (r)
++			goto end;
++
++		spin_lock_irqsave(&dsi.update_lock, flags);
++		dsi.update_ongoing = 0;
++		while (dsi.update_syncers > 0) {
++			complete(&dsi.update_completion);
++			--dsi.update_syncers;
++		}
++		spin_unlock_irqrestore(&dsi.update_lock, flags);
++	}
++
++end:
++	mutex_unlock(&dsi.lock);
++	return r;
++}
++
++static int dsi_display_sync(struct omap_display *display)
++{
++	int r = 0;
++
++	DSSDBG("dsi_display_sync\n");
++
++	mutex_lock(&dsi.lock);
++
++	if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
++		goto end;
++
++	r = dsi_wait_for_framedone(0);
++
++end:
++	mutex_unlock(&dsi.lock);
++	return r;
++}
++
++static int dsi_display_set_update_mode(struct omap_display *display,
++		enum omap_dss_update_mode mode)
++{
++	int r;
++
++	DSSDBG("dsi_display_set_update_mode\n");
++
++	mutex_lock(&dsi.lock);
++
++	r = dsi_set_update_mode(display, mode);
++	dsi.user_update_mode = mode;
++
++	mutex_unlock(&dsi.lock);
++
++	return r;
++}
++
++static enum omap_dss_update_mode dsi_display_get_update_mode(
++		struct omap_display *display)
++{
++	return dsi.user_update_mode;
++}
++
++static int dsi_display_enable_te(struct omap_display *display, int enable)
++{
++	DSSDBG("dsi_display_enable_te\n");
++
++	mutex_lock(&dsi.lock);
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	dsi_set_update_mode(display, OMAP_DSS_UPDATE_DISABLED);
++
++	dsi.use_te = enable;
++	display->ctrl->enable_te(display, enable);
++	if (enable) {
++		/* disable LP_RX_TO, so that we can receive TE.
++		 * Time to wait for TE is longer than the timer allows */
++		REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
++	} else {
++		REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
++	}
++
++	/* restore the old update mode */
++	dsi_set_update_mode(display, dsi.user_update_mode);
++
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++
++	mutex_unlock(&dsi.lock);
++
++	return 0;
++}
++
++static int dsi_display_get_te(struct omap_display *display)
++{
++	return dsi.use_te;
++}
++
++static int dsi_display_run_test(struct omap_display *display, int test_num)
++{
++	int r = 0;
++
++	DSSDBG("dsi_display_run_test %d\n", test_num);
++
++	mutex_lock(&dsi.lock);
++
++	enable_clocks(1);
++	dsi_enable_pll_clock(1);
++
++	dsi_set_update_mode(display, OMAP_DSS_UPDATE_DISABLED);
++
++	/* run test first in low speed mode */
++	dsi_vc_enable_hs(0, 0);
++
++	if (display->ctrl->run_test) {
++		r = display->ctrl->run_test(display, test_num);
++		if (r)
++			goto fail;
++	}
++
++	if (display->panel->run_test) {
++		r = display->panel->run_test(display, test_num);
++		if (r)
++			goto fail;
++	}
++
++	/* then in high speed */
++	dsi_vc_enable_hs(0, 1);
++
++	if (display->ctrl->run_test) {
++		r = display->ctrl->run_test(display, test_num);
++		if (r)
++			goto fail;
++	}
++
++	if (display->panel->run_test)
++		r = display->panel->run_test(display, test_num);
++
++fail:
++	dsi_vc_enable_hs(0, 1);
++
++	/* restore the old update mode */
++	dsi_set_update_mode(display, dsi.user_update_mode);
++
++	enable_clocks(0);
++	dsi_enable_pll_clock(0);
++
++	mutex_unlock(&dsi.lock);
++
++	return r;
++}
++
++void dsi_init_display(struct omap_display *display)
++{
++	DSSDBG("DSI init\n");
++
++	display->enable = dsi_display_enable;
++	display->disable = dsi_display_disable;
++	display->suspend = dsi_display_suspend;
++	display->resume = dsi_display_resume;
++	display->update = dsi_display_update;
++	display->sync = dsi_display_sync;
++	display->set_update_mode = dsi_display_set_update_mode;
++	display->get_update_mode = dsi_display_get_update_mode;
++	display->enable_te = dsi_display_enable_te;
++	display->get_te = dsi_display_get_te;
++	display->run_test = dsi_display_run_test;
++
++	display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++}
++
++int dsi_init(void)
++{
++	u32 rev;
++
++	init_completion(&dsi.bta_completion);
++	INIT_DELAYED_WORK(&dsi.framedone_work, framedone_worker);
++
++	init_completion(&dsi.update_completion);
++	spin_lock_init(&dsi.update_lock);
++	dsi.update_ongoing = 0;
++	dsi.update_syncers = 0;
++
++	mutex_init(&dsi.lock);
++
++	dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
++	if (!dsi.base) {
++		DSSERR("can't ioremap DSI\n");
++		return -ENOMEM;
++	}
++
++	enable_clocks(1);
++
++	/* Autoidle */
++	REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
++
++	/* ENWAKEUP */
++	REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
++
++	/* SIDLEMODE smart-idle */
++	REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
++
++	_dsi_initialize_irq();
++
++	rev = dsi_read_reg(DSI_REVISION);
++	printk(KERN_INFO "OMAP DSI rev %d.%d\n",
++	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++	enable_clocks(0);
++
++	return 0;
++}
++
++void dsi_exit(void)
++{
++	iounmap(dsi.base);
++
++	DSSDBG("omap_dsi_exit\n");
++}
++
+diff --git a/arch/arm/plat-omap/dss/dss.c b/arch/arm/plat-omap/dss/dss.c
+new file mode 100644
+index 0000000..4a403c1
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/dss.c
+@@ -0,0 +1,774 @@
++/*
++ * linux/arch/arm/plat-omap/dss/dss.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DSS"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++
++#include <mach/display.h>
++#include <mach/clock.h>
++#include "dss.h"
++
++#define DSS_BASE			0x48050000
++
++#define DSS_SZ_REGS			SZ_512
++
++struct dss_reg {
++	u16 idx;
++};
++
++#define DSS_REG(idx)			((const struct dss_reg) { idx })
++
++#define DSS_REVISION			DSS_REG(0x0000)
++#define DSS_SYSCONFIG			DSS_REG(0x0010)
++#define DSS_SYSSTATUS			DSS_REG(0x0014)
++#define DSS_IRQSTATUS			DSS_REG(0x0018)
++#define DSS_CONTROL			DSS_REG(0x0040)
++#define DSS_SDI_CONTROL			DSS_REG(0x0044)
++#define DSS_PLL_CONTROL			DSS_REG(0x0048)
++#define DSS_SDI_STATUS			DSS_REG(0x005C)
++
++#define REG_GET(idx, start, end) \
++	FLD_GET(dss_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++	dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
++
++static struct {
++	void __iomem    *base;
++
++	struct clk      *dss_ick;
++	struct clk	*dss1_fck;
++	struct clk	*dss2_fck;
++	struct clk      *dss_54m_fck;
++	struct clk	*dss_96m_fck;
++
++	unsigned	num_clks_enabled;
++	struct platform_device *pdev;
++	unsigned	ctx_id;
++	u32		ctx[DSS_SZ_REGS / sizeof(u32)];
++} dss;
++
++static void dss_clk_enable_all_no_ctx(void);
++static void dss_clk_disable_all_no_ctx(void);
++static void dss_clk_enable_no_ctx(enum dss_clock clks);
++static void dss_clk_disable_no_ctx(enum dss_clock clks);
++static int _omap_dss_wait_reset(void);
++
++static char *def_disp_name;
++module_param_named(def_disp, def_disp_name, charp, 0);
++MODULE_PARM_DESC(def_disp_name, "default display name");
++
++#ifdef DEBUG
++unsigned int dss_debug;
++module_param_named(debug, dss_debug, bool, 0644);
++#endif
++
++static inline void dss_write_reg(const struct dss_reg idx, u32 val)
++{
++	__raw_writel(val, dss.base + idx.idx);
++}
++
++static inline u32 dss_read_reg(const struct dss_reg idx)
++{
++	return __raw_readl(dss.base + idx.idx);
++}
++
++#define SR(reg) \
++	dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
++#define RR(reg) \
++	dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
++
++static void dss_save_context(void)
++{
++	if (cpu_is_omap24xx())
++		return;
++
++	SR(SYSCONFIG);
++	SR(CONTROL);
++	SR(SDI_CONTROL);
++	SR(PLL_CONTROL);
++}
++
++static void dss_restore_context(void)
++{
++	RR(SYSCONFIG);
++	RR(CONTROL);
++	RR(SDI_CONTROL);
++	RR(PLL_CONTROL);
++}
++
++#undef SR
++#undef RR
++
++static unsigned dss_get_ctx_id(void)
++{
++	struct omap_dss_platform_data *pdata = dss.pdev->dev.platform_data;
++
++	if (!pdata->get_last_off_on_transaction_id)
++		return 0;
++
++	return pdata->get_last_off_on_transaction_id(&dss.pdev->dev);
++}
++
++static void save_all_ctx(void)
++{
++	DSSDBG("save context\n");
++
++	dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	dss_save_context();
++	dispc_save_context();
++#ifdef CONFIG_OMAP2_DSS_DSI
++	dsi_save_context();
++#endif
++
++	dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++static void restore_all_ctx(void)
++{
++	DSSDBG("restore context\n");
++
++	dss_clk_enable_all_no_ctx();
++
++	if (_omap_dss_wait_reset())
++		DSSERR("DSS not coming out of reset after sleep\n");
++
++	dss_restore_context();
++	dispc_restore_context();
++#ifdef CONFIG_OMAP2_DSS_DSI
++	dsi_restore_context();
++#endif
++
++	dss_clk_disable_all_no_ctx();
++}
++
++void dss_sdi_init(int datapairs)
++{
++	u32 l;
++
++	BUG_ON(datapairs > 3 || datapairs < 1);
++
++	l = dss_read_reg(DSS_SDI_CONTROL);
++	l = FLD_MOD(l, 0xf, 19, 15);		/* SDI_PDIV */
++	l = FLD_MOD(l, datapairs-1, 3, 2);	/* SDI_PRSEL */
++	l = FLD_MOD(l, 2, 1, 0);		/* SDI_BWSEL */
++	dss_write_reg(DSS_SDI_CONTROL, l);
++
++	l = dss_read_reg(DSS_PLL_CONTROL);
++	l = FLD_MOD(l, 0x7, 25, 22);	/* SDI_PLL_FREQSEL */
++	l = FLD_MOD(l, 0xb, 16, 11);	/* SDI_PLL_REGN */
++	l = FLD_MOD(l, 0xb4, 10, 1);	/* SDI_PLL_REGM */
++	dss_write_reg(DSS_PLL_CONTROL, l);
++
++	/* Reset SDI PLL */
++	REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
++	udelay(1);	/* wait 2x PCLK */
++
++	/* Lock SDI PLL */
++	REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
++
++	/* Waiting for PLL lock request to complete */
++	while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6))
++		;
++
++	/* Clearing PLL_GO bit */
++	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
++
++	/* Waiting for PLL to lock */
++	while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5)))
++		;
++
++	dispc_lcd_enable_signal(1);
++
++	/* Waiting for SDI reset to complete */
++	while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5)))
++		;
++}
++
++ssize_t dss_print_clocks(char *buf, ssize_t size)
++{
++	ssize_t l = 0;
++	int i;
++	struct clk *clocks[5] = {
++		dss.dss_ick,
++		dss.dss1_fck,
++		dss.dss2_fck,
++		dss.dss_54m_fck,
++		dss.dss_96m_fck
++	};
++
++	l += snprintf(buf + l, size - l, "- dss -\n");
++
++	l += snprintf(buf + l, size - l, "internal clk count\t%u\n",
++			dss.num_clks_enabled);
++
++	for (i = 0; i < 5; i++) {
++		if (!clocks[i])
++			continue;
++		l += snprintf(buf + l, size - l, "%-15s\t%lu\t%d\n",
++				clocks[i]->name,
++				clk_get_rate(clocks[i]),
++				clk_get_usecount(clocks[i]));
++	}
++
++	return l;
++}
++
++static int get_dss_clocks(void)
++{
++	const struct {
++		struct clk **clock;
++		char *omap2_name;
++		char *omap3_name;
++	} clocks[5] = {
++		{ &dss.dss_ick, "dss_ick", "dss_ick" },	/* L3 & L4 ick */
++		{ &dss.dss1_fck, "dss1_fck", "dss1_alwon_fck" },
++		{ &dss.dss2_fck, "dss2_fck", "dss2_alwon_fck" },
++		{ &dss.dss_54m_fck, "dss_54m_fck", "dss_tv_fck" },
++		{ &dss.dss_96m_fck, NULL, "dss_96m_fck" },
++	};
++
++	int r = 0;
++	int i;
++	const int num_clocks = 5;
++
++	for (i = 0; i < num_clocks; i++)
++		*clocks[i].clock = NULL;
++
++	for (i = 0; i < num_clocks; i++) {
++		struct clk *clk;
++		const char *clk_name;
++
++		clk_name = cpu_is_omap34xx() ? clocks[i].omap3_name
++			: clocks[i].omap2_name;
++
++		if (!clk_name)
++			continue;
++
++		clk = clk_get(NULL, clk_name);
++
++		if (IS_ERR(clk)) {
++			DSSERR("can't get clock %s", clk_name);
++			r = PTR_ERR(clk);
++			goto err;
++		}
++
++		DSSDBG("clk %s, rate %ld\n",
++				clk_name, clk_get_rate(clk));
++
++		*clocks[i].clock = clk;
++	}
++
++	return 0;
++
++err:
++	for (i = 0; i < num_clocks; i++) {
++		if (!IS_ERR(*clocks[i].clock))
++			clk_put(*clocks[i].clock);
++	}
++
++	return r;
++}
++
++static void put_dss_clocks(void)
++{
++	if (dss.dss_96m_fck)
++		clk_put(dss.dss_96m_fck);
++	clk_put(dss.dss_54m_fck);
++	clk_put(dss.dss1_fck);
++	clk_put(dss.dss2_fck);
++	clk_put(dss.dss_ick);
++}
++
++unsigned long dss_clk_get_rate(enum dss_clock clk)
++{
++	switch (clk) {
++	case DSS_CLK_ICK:
++		return clk_get_rate(dss.dss_ick);
++	case DSS_CLK_FCK1:
++		return clk_get_rate(dss.dss1_fck);
++	case DSS_CLK_FCK2:
++		return clk_get_rate(dss.dss2_fck);
++	case DSS_CLK_54M:
++		return clk_get_rate(dss.dss_54m_fck);
++	case DSS_CLK_96M:
++		return clk_get_rate(dss.dss_96m_fck);
++	}
++
++	BUG();
++	return 0;
++}
++
++static unsigned count_clk_bits(enum dss_clock clks)
++{
++	unsigned num_clks = 0;
++
++	if (clks & DSS_CLK_ICK)
++		++num_clks;
++	if (clks & DSS_CLK_FCK1)
++		++num_clks;
++	if (clks & DSS_CLK_FCK2)
++		++num_clks;
++	if (clks & DSS_CLK_54M)
++		++num_clks;
++	if (clks & DSS_CLK_96M)
++		++num_clks;
++
++	return num_clks;
++}
++
++static void dss_clk_enable_no_ctx(enum dss_clock clks)
++{
++	unsigned num_clks = count_clk_bits(clks);
++
++	if (clks & DSS_CLK_ICK)
++		clk_enable(dss.dss_ick);
++	if (clks & DSS_CLK_FCK1)
++		clk_enable(dss.dss1_fck);
++	if (clks & DSS_CLK_FCK2)
++		clk_enable(dss.dss2_fck);
++	if (clks & DSS_CLK_54M)
++		clk_enable(dss.dss_54m_fck);
++	if (clks & DSS_CLK_96M)
++		clk_enable(dss.dss_96m_fck);
++
++	dss.num_clks_enabled += num_clks;
++}
++
++void dss_clk_enable(enum dss_clock clks)
++{
++	dss_clk_enable_no_ctx(clks);
++
++	if (cpu_is_omap34xx()) {
++		int id = dss_get_ctx_id();
++
++		if (id != dss.ctx_id) {
++			DSSDBG("ctx id %u -> id %u\n",
++					dss.ctx_id, id);
++			restore_all_ctx();
++			dss.ctx_id = id;
++		}
++	}
++}
++
++static void dss_clk_disable_no_ctx(enum dss_clock clks)
++{
++	unsigned num_clks = count_clk_bits(clks);
++
++	if (clks & DSS_CLK_ICK)
++		clk_disable(dss.dss_ick);
++	if (clks & DSS_CLK_FCK1)
++		clk_disable(dss.dss1_fck);
++	if (clks & DSS_CLK_FCK2)
++		clk_disable(dss.dss2_fck);
++	if (clks & DSS_CLK_54M)
++		clk_disable(dss.dss_54m_fck);
++	if (clks & DSS_CLK_96M)
++		clk_disable(dss.dss_96m_fck);
++
++	dss.num_clks_enabled -= num_clks;
++}
++
++void dss_clk_disable(enum dss_clock clks)
++{
++	if (cpu_is_omap34xx()) {
++		unsigned num_clks = count_clk_bits(clks);
++
++		BUG_ON(dss.num_clks_enabled < num_clks);
++
++		if (dss.num_clks_enabled == num_clks)
++			save_all_ctx();
++	}
++
++	dss_clk_disable_no_ctx(clks);
++}
++
++static void dss_clk_enable_all_no_ctx(void)
++{
++	enum dss_clock clks;
++
++	clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++	if (cpu_is_omap34xx())
++		clks |= DSS_CLK_96M;
++	dss_clk_enable_no_ctx(clks);
++}
++
++static void dss_clk_disable_all_no_ctx(void)
++{
++	enum dss_clock clks;
++
++	clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++	if (cpu_is_omap34xx())
++		clks |= DSS_CLK_96M;
++	dss_clk_disable_no_ctx(clks);
++}
++
++static void dss_clk_disable_all(void)
++{
++	enum dss_clock clks;
++
++	clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++	if (cpu_is_omap34xx())
++		clks |= DSS_CLK_96M;
++	dss_clk_disable(clks);
++}
++
++void dss_select_clk_source(int dsi, int dispc)
++{
++	u32 r;
++	r = dss_read_reg(DSS_CONTROL);
++	r = FLD_MOD(r, dsi, 1, 1);	/* DSI_CLK_SWITCH */
++	r = FLD_MOD(r, dispc, 0, 0);	/* DISPC_CLK_SWITCH */
++	dss_write_reg(DSS_CONTROL, r);
++}
++
++int dss_get_dsi_clk_source(void)
++{
++	return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1);
++}
++
++int dss_get_dispc_clk_source(void)
++{
++	return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0);
++}
++
++static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
++{
++	dispc_irq_handler();
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
++{
++	u32 irqstatus;
++
++	irqstatus = dss_read_reg(DSS_IRQSTATUS);
++
++	if (irqstatus & (1<<0))	/* DISPC_IRQ */
++		dispc_irq_handler();
++#ifdef CONFIG_OMAP2_DSS_DSI
++	if (irqstatus & (1<<1))	/* DSI_IRQ */
++		dsi_irq_handler();
++#endif
++
++	return IRQ_HANDLED;
++}
++
++static int _omap_dss_wait_reset(void)
++{
++	unsigned timeout = 1000;
++
++	while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
++		udelay(1);
++		if (!--timeout) {
++			DSSERR("soft reset failed\n");
++			return -ENODEV;
++		}
++	}
++
++	return 0;
++}
++
++static int _omap_dss_reset(void)
++{
++	/* Soft reset */
++	REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
++	return _omap_dss_wait_reset();
++}
++
++void dss_set_venc_output(enum omap_dss_venc_type type)
++{
++	int l = 0;
++
++	if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
++		l = 0;
++	else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
++		l = 1;
++	else
++		BUG();
++
++	/* venc out selection. 0 = comp, 1 = svideo */
++	REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
++}
++
++void dss_set_dac_pwrdn_bgz(int enable)
++{
++	REG_FLD_MOD(DSS_CONTROL, enable, 5, 5);	/* DAC Power-Down Control */
++}
++
++int dss_init(void)
++{
++	int r;
++	u32 rev;
++
++	dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
++	if (!dss.base) {
++		DSSERR("can't ioremap DSS\n");
++		r = -ENOMEM;
++		goto fail0;
++	}
++
++	/* We need to wait here a bit, otherwise we sometimes start to get
++	 * synclost errors. I believe we could wait for one framedone or
++	 * perhaps vsync interrupt, but, because dispc is not initialized yet,
++	 * we don't have access to the irq register.
++	 */
++	msleep(400);
++
++	_omap_dss_reset();
++
++	/* autoidle */
++	REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
++
++	/* Select DPLL */
++	REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++	REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);	/* venc dac demen */
++	REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);	/* venc clock 4x enable */
++	REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */
++#endif
++
++	r = request_irq(INT_24XX_DSS_IRQ,
++			cpu_is_omap24xx()
++			? dss_irq_handler_omap2
++			: dss_irq_handler_omap3,
++			0, "OMAP DSS", NULL);
++
++	if (r < 0) {
++		DSSERR("omap2 dss: request_irq failed\n");
++		goto fail1;
++	}
++
++	dss_save_context();
++
++	rev = dss_read_reg(DSS_REVISION);
++	printk(KERN_INFO "OMAP DSS rev %d.%d\n",
++			FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++	return 0;
++
++fail1:
++	iounmap(dss.base);
++fail0:
++	return r;
++}
++
++void dss_exit(void)
++{
++	int c;
++
++	free_irq(INT_24XX_DSS_IRQ, NULL);
++
++	/* these should be removed at some point */
++	c = clk_get_usecount(dss.dss_ick);
++	if (c > 0) {
++		DSSERR("warning: dss_ick usecount %d, disabling\n", c);
++		while (c-- > 0)
++			clk_disable(dss.dss_ick);
++	}
++
++	c = clk_get_usecount(dss.dss1_fck);
++	if (c > 0) {
++		DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
++		while (c-- > 0)
++			clk_disable(dss.dss1_fck);
++	}
++
++	c = clk_get_usecount(dss.dss2_fck);
++	if (c > 0) {
++		DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
++		while (c-- > 0)
++			clk_disable(dss.dss2_fck);
++	}
++
++	c = clk_get_usecount(dss.dss_54m_fck);
++	if (c > 0) {
++		DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
++		while (c-- > 0)
++			clk_disable(dss.dss_54m_fck);
++	}
++
++	if (dss.dss_96m_fck) {
++		c = clk_get_usecount(dss.dss_96m_fck);
++		if (c > 0) {
++			DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
++					c);
++			while (c-- > 0)
++				clk_disable(dss.dss_96m_fck);
++		}
++	}
++
++	put_dss_clocks();
++
++	iounmap(dss.base);
++}
++
++
++
++static int omap_dss_probe(struct platform_device *pdev)
++{
++	struct omap_dss_platform_data *pdata = pdev->dev.platform_data;
++
++	int r;
++
++	dss.pdev = pdev;
++
++	r = get_dss_clocks();
++	if (r)
++		goto fail0;
++
++	dss_clk_enable_all_no_ctx();
++
++	dss.ctx_id = dss_get_ctx_id();
++	DSSDBG("initial ctx id %u\n", dss.ctx_id);
++
++	r = dss_init();
++	if (r) {
++		DSSERR("Failed to initialize DSS\n");
++		goto fail0;
++	}
++
++#ifdef CONFIG_OMAP2_DSS_RFBI
++	r = rfbi_init();
++	if (r) {
++		DSSERR("Failed to initialize rfbi\n");
++		goto fail0;
++	}
++#endif
++
++	r = dpi_init();
++	if (r) {
++		DSSERR("Failed to initialize dpi\n");
++		goto fail0;
++	}
++
++	r = dispc_init();
++	if (r) {
++		DSSERR("Failed to initialize dispc\n");
++		goto fail0;
++	}
++#ifdef CONFIG_OMAP2_DSS_VENC
++	r = venc_init();
++	if (r) {
++		DSSERR("Failed to initialize venc\n");
++		goto fail0;
++	}
++#endif
++	if (cpu_is_omap34xx()) {
++#ifdef CONFIG_OMAP2_DSS_SDI
++		r = sdi_init();
++		if (r) {
++			DSSERR("Failed to initialize SDI\n");
++			goto fail0;
++		}
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++		r = dsi_init();
++		if (r) {
++			DSSERR("Failed to initialize DSI\n");
++			goto fail0;
++		}
++#endif
++	}
++
++	initialize_displays(pdata);
++
++	r = initialize_sysfs(&pdev->dev);
++	if (r)
++		goto fail0;
++
++	initialize_overlays(def_disp_name);
++
++	dss_clk_disable_all();
++
++	return 0;
++
++	/* XXX fail correctly */
++fail0:
++	return r;
++}
++
++static int omap_dss_remove(struct platform_device *pdev)
++{
++	uninitialize_sysfs(&pdev->dev);
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++	venc_exit();
++#endif
++	dispc_exit();
++	dpi_exit();
++#ifdef CONFIG_OMAP2_DSS_RFBI
++	rfbi_exit();
++#endif
++	if (cpu_is_omap34xx()) {
++#ifdef CONFIG_OMAP2_DSS_DSI
++		dsi_exit();
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++		sdi_exit();
++#endif
++	}
++
++	dss_exit();
++
++	return 0;
++}
++
++
++static struct platform_driver omap_dss_driver = {
++	.probe          = omap_dss_probe,
++	.remove         = omap_dss_remove,
++	.driver         = {
++		.name   = "omap-dss",
++		.owner  = THIS_MODULE,
++	},
++};
++
++static int __init omap_dss_init(void)
++{
++	return platform_driver_register(&omap_dss_driver);
++}
++
++static void __exit omap_dss_exit(void)
++{
++	platform_driver_unregister(&omap_dss_driver);
++}
++
++subsys_initcall(omap_dss_init);
++module_exit(omap_dss_exit);
++
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/arch/arm/plat-omap/dss/dss.h b/arch/arm/plat-omap/dss/dss.h
+new file mode 100644
+index 0000000..da628a7
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/dss.h
+@@ -0,0 +1,274 @@
++/*
++ * linux/arch/arm/plat-omap/dss/dss.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __OMAP2_DSS_H
++#define __OMAP2_DSS_H
++
++#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
++#define DEBUG
++#endif
++
++#ifdef DEBUG
++extern unsigned int dss_debug;
++#ifdef DSS_SUBSYS_NAME
++#define DSSDBG(format, ...) \
++	if (dss_debug) \
++		printk(KERN_DEBUG "omap-dss " DSS_SUBSYS_NAME ": " format, \
++		## __VA_ARGS__)
++#else
++#define DSSDBG(format, ...) \
++	if (dss_debug) \
++		printk(KERN_DEBUG "omap-dss: " format, ## __VA_ARGS__)
++#endif
++#else
++#define DSSDBG(format, ...)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSERR(format, ...) \
++	printk(KERN_ERR "omap-dss " DSS_SUBSYS_NAME " error: " format, \
++	## __VA_ARGS__)
++#else
++#define DSSERR(format, ...) \
++	printk(KERN_ERR "omap-dss error: " format, ## __VA_ARGS__)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSINFO(format, ...) \
++	printk(KERN_INFO "omap-dss " DSS_SUBSYS_NAME ": " format, \
++	## __VA_ARGS__)
++#else
++#define DSSINFO(format, ...) \
++	printk(KERN_INFO "omap-dss: " format, ## __VA_ARGS__)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSWARN(format, ...) \
++	printk(KERN_WARNING "omap-dss " DSS_SUBSYS_NAME ": " format, \
++	## __VA_ARGS__)
++#else
++#define DSSWARN(format, ...) \
++	printk(KERN_WARNING "omap-dss: " format, ## __VA_ARGS__)
++#endif
++
++/* OMAP TRM gives bitfields as start:end, where start is the higher bit
++   number. For example 7:0 */
++#define FLD_MASK(start, end)	(((1 << (start - end + 1)) - 1) << (end))
++#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end))
++#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
++#define FLD_MOD(orig, val, start, end) \
++	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
++
++#define DISPC_MAX_FCK 173000000
++
++enum omap_burst_size {
++	OMAP_DSS_BURST_4x32 = 0,
++	OMAP_DSS_BURST_8x32 = 1,
++	OMAP_DSS_BURST_16x32 = 2,
++};
++
++enum omap_parallel_interface_mode {
++	OMAP_DSS_PARALLELMODE_BYPASS,		/* MIPI DPI */
++	OMAP_DSS_PARALLELMODE_RFBI,		/* MIPI DBI */
++	OMAP_DSS_PARALLELMODE_DSI,
++};
++
++enum dss_clock {
++	DSS_CLK_ICK	= 1 << 0,
++	DSS_CLK_FCK1	= 1 << 1,
++	DSS_CLK_FCK2	= 1 << 2,
++	DSS_CLK_54M	= 1 << 3,
++	DSS_CLK_96M	= 1 << 4,
++};
++
++struct dispc_clock_info {
++	/* rates that we get with dividers below */
++	unsigned long fck;
++	unsigned long lck;
++	unsigned long pck;
++
++	/* dividers */
++	int fck_div;
++	int lck_div;
++	int pck_div;
++};
++
++struct dsi_clock_info {
++	/* rates that we get with dividers below */
++	unsigned long fint;
++	unsigned long dsiphy;
++	unsigned long clkin;	/* input clk for DSI PLL */
++	unsigned long dispc_fck;	/* output clk, DSI1_PLL_FCLK */
++	unsigned long dsi_fck;	/* output clk, DSI2_PLL_FCLK */
++	unsigned long lck;
++	unsigned long pck;
++
++	/* dividers */
++	int regn;
++	int regm;
++	int regm3;
++	int regm4;
++
++	int lck_div;
++	int pck_div;
++
++	int highfreq;
++	int use_dss2_fck;
++};
++
++int initialize_sysfs(struct device *dev);
++void uninitialize_sysfs(struct device *dev);
++void initialize_displays(struct omap_dss_platform_data *pdata);
++void initialize_overlays(const char *def_disp_name);
++
++/* DSS */
++int dss_init(void);
++void dss_exit(void);
++
++void dss_clk_enable(enum dss_clock clks);
++void dss_clk_disable(enum dss_clock clks);
++
++void dss_sdi_init(int datapairs);
++void dss_select_clk_source(int dsi, int dispc);
++int dss_get_dsi_clk_source(void);
++int dss_get_dispc_clk_source(void);
++void dss_set_venc_output(enum omap_dss_venc_type type);
++void dss_set_dac_pwrdn_bgz(int enable);
++unsigned long dss_clk_get_rate(enum dss_clock clk);
++ssize_t dss_print_clocks(char *buf, ssize_t size);
++
++/* SDI */
++int sdi_init(void);
++void sdi_exit(void);
++void sdi_init_display(struct omap_display *display);
++
++
++/* DSI */
++int dsi_init(void);
++void dsi_exit(void);
++
++void dsi_save_context(void);
++void dsi_restore_context(void);
++
++void dsi_init_display(struct omap_display *display);
++void dsi_irq_handler(void);
++unsigned long dsi_get_dsi1_pll_rate(void);
++unsigned long dsi_get_dsi2_pll_rate(void);
++int dsi_pll_calc_pck(int is_tft, unsigned long req_pck,
++		struct dsi_clock_info *cinfo);
++int dsi_pll_program(struct dsi_clock_info *cinfo);
++int dsi_pll_init(int enable_hsclk, int enable_hsdiv);
++void dsi_pll_uninit(void);
++ssize_t dsi_print_clocks(char *buf, ssize_t size);
++
++/* DPI */
++int dpi_init(void);
++void dpi_exit(void);
++void dpi_init_display(struct omap_display *display);
++
++/* DISPC */
++int dispc_init(void);
++void dispc_exit(void);
++void dispc_irq_handler(void);
++void dispc_fake_vsync_irq(void);
++
++void dispc_save_context(void);
++void dispc_restore_context(void);
++
++void dispc_lcd_enable_signal_polarity(int act_high);
++void dispc_lcd_enable_signal(int enable);
++void dispc_pck_free_enable(int enable);
++void dispc_enable_fifohandcheck(int enable);
++
++void dispc_set_lcd_size(int width, int height);
++void dispc_set_digit_size(int width, int height);
++u32 dispc_get_plane_fifo_size(enum omap_plane plane);
++void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
++void dispc_set_burst_size(enum omap_plane plane,
++		enum omap_burst_size burst_size);
++
++void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
++void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
++void dispc_set_plane_pos(enum omap_plane plane, int x, int y);
++void dispc_set_plane_size(enum omap_plane plane, int width, int height);
++void dispc_set_row_inc(enum omap_plane plane, int inc);
++
++int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
++		      u32 paddr, int screen_width,
++		      int pos_x, int pos_y,
++		      int width, int height,
++		      int out_width, int out_height,
++		      enum omap_color_mode color_mode,
++		      int ilace);
++
++void dispc_go(enum omap_channel channel);
++void dispc_enable_lcd_out(int enable);
++void dispc_enable_digit_out(int enable);
++int dispc_enable_plane(enum omap_plane plane, int enable);
++
++void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
++void dispc_set_tft_data_lines(int data_lines);
++void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
++void dispc_set_loadmode(enum omap_dss_load_mode mode);
++
++void dispc_set_default_color(enum omap_channel channel, u32 color);
++void dispc_set_trans_key(enum omap_channel ch,
++		enum omap_dss_color_key_type type,
++		u32 trans_key);
++void dispc_enable_trans_key(enum omap_channel ch, int enable);
++
++void dispc_set_lcd_timings(struct omap_video_timings *timings);
++unsigned long dispc_fclk_rate(void);
++unsigned long dispc_pclk_rate(void);
++void dispc_set_pol_freq(struct omap_panel *panel);
++void find_lck_pck_divs(int is_tft, unsigned long req_pck, unsigned long fck,
++		int *lck_div, int *pck_div);
++int dispc_calc_clock_div(int is_tft, unsigned long req_pck,
++		struct dispc_clock_info *cinfo);
++int dispc_set_clock_div(struct dispc_clock_info *cinfo);
++void dispc_set_lcd_divisor(int lck_div, int pck_div);
++
++void dispc_setup_partial_planes(struct omap_display *display,
++				int *x, int *y, int *w, int *h);
++void dispc_draw_partial_planes(struct omap_display *display);
++
++
++ssize_t dispc_print_clocks(char *buf, ssize_t size);
++
++/* VENC */
++int venc_init(void);
++void venc_exit(void);
++void venc_init_display(struct omap_display *display);
++
++/* RFBI */
++int rfbi_init(void);
++void rfbi_exit(void);
++
++int rfbi_configure(int rfbi_module, int bpp, int lines);
++void rfbi_enable_rfbi(int enable);
++void rfbi_transfer_area(int width, int height,
++			     void (callback)(void *data), void *data);
++void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
++unsigned long rfbi_get_max_tx_rate(void);
++void rfbi_init_display(struct omap_display *display);
++
++#endif
+diff --git a/arch/arm/plat-omap/dss/rfbi.c b/arch/arm/plat-omap/dss/rfbi.c
+new file mode 100644
+index 0000000..b4b65e6
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/rfbi.c
+@@ -0,0 +1,1262 @@
++/*
++ * linux/arch/arm/plat-omap/dss/rfbi.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "RFBI"
++
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <linux/kfifo.h>
++#include <linux/ktime.h>
++#include <linux/hrtimer.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++/*#define MEASURE_PERF*/
++
++#define RFBI_BASE               0x48050800
++
++struct rfbi_reg { u16 idx; };
++
++#define RFBI_REG(idx)		((const struct rfbi_reg) { idx })
++
++#define RFBI_REVISION		RFBI_REG(0x0000)
++#define RFBI_SYSCONFIG		RFBI_REG(0x0010)
++#define RFBI_SYSSTATUS		RFBI_REG(0x0014)
++#define RFBI_CONTROL		RFBI_REG(0x0040)
++#define RFBI_PIXEL_CNT		RFBI_REG(0x0044)
++#define RFBI_LINE_NUMBER	RFBI_REG(0x0048)
++#define RFBI_CMD		RFBI_REG(0x004c)
++#define RFBI_PARAM		RFBI_REG(0x0050)
++#define RFBI_DATA		RFBI_REG(0x0054)
++#define RFBI_READ		RFBI_REG(0x0058)
++#define RFBI_STATUS		RFBI_REG(0x005c)
++
++#define RFBI_CONFIG(n)		RFBI_REG(0x0060 + (n)*0x18)
++#define RFBI_ONOFF_TIME(n)	RFBI_REG(0x0064 + (n)*0x18)
++#define RFBI_CYCLE_TIME(n)	RFBI_REG(0x0068 + (n)*0x18)
++#define RFBI_DATA_CYCLE1(n)	RFBI_REG(0x006c + (n)*0x18)
++#define RFBI_DATA_CYCLE2(n)	RFBI_REG(0x0070 + (n)*0x18)
++#define RFBI_DATA_CYCLE3(n)	RFBI_REG(0x0074 + (n)*0x18)
++
++#define RFBI_VSYNC_WIDTH	RFBI_REG(0x0090)
++#define RFBI_HSYNC_WIDTH	RFBI_REG(0x0094)
++
++#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param))
++
++#define REG_FLD_MOD(idx, val, start, end) \
++	rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
++
++/* To work around an RFBI transfer rate limitation */
++#define OMAP_RFBI_RATE_LIMIT    1
++
++enum omap_rfbi_cycleformat {
++	OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
++	OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
++	OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
++	OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
++};
++
++enum omap_rfbi_datatype {
++	OMAP_DSS_RFBI_DATATYPE_12 = 0,
++	OMAP_DSS_RFBI_DATATYPE_16 = 1,
++	OMAP_DSS_RFBI_DATATYPE_18 = 2,
++	OMAP_DSS_RFBI_DATATYPE_24 = 3,
++};
++
++enum omap_rfbi_parallelmode {
++	OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
++	OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
++	OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
++	OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
++};
++
++enum update_cmd {
++	RFBI_CMD_UPDATE = 0,
++	RFBI_CMD_SYNC   = 1,
++};
++
++static int rfbi_convert_timings(struct rfbi_timings *t);
++static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
++static void process_cmd_fifo(void);
++
++static struct {
++	void __iomem	*base;
++
++	unsigned long	l4_khz;
++
++	enum omap_rfbi_datatype datatype;
++	enum omap_rfbi_parallelmode parallelmode;
++
++	enum omap_rfbi_te_mode te_mode;
++	int te_enabled;
++
++	void (*framedone_callback)(void *data);
++	void *framedone_callback_data;
++
++	struct omap_display *display[2];
++
++	struct kfifo      *cmd_fifo;
++	spinlock_t        cmd_lock;
++	struct completion cmd_done;
++	atomic_t          cmd_fifo_full;
++	atomic_t          cmd_pending;
++#ifdef MEASURE_PERF
++	unsigned perf_bytes;
++	ktime_t perf_setup_time;
++	ktime_t perf_start_time;
++#endif
++} rfbi;
++
++struct update_region {
++	u16	x;
++	u16     y;
++	u16     w;
++	u16     h;
++};
++
++struct update_param {
++	u8 rfbi_module;
++	u8 cmd;
++
++	union {
++		struct update_region r;
++		struct completion *sync;
++	} par;
++};
++
++static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
++{
++	__raw_writel(val, rfbi.base + idx.idx);
++}
++
++static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
++{
++	return __raw_readl(rfbi.base + idx.idx);
++}
++
++static void rfbi_enable_clocks(int enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++	else
++		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++void omap_rfbi_write_command(const void *buf, u32 len)
++{
++	rfbi_enable_clocks(1);
++	switch (rfbi.parallelmode) {
++	case OMAP_DSS_RFBI_PARALLELMODE_8:
++	{
++		const u8 *b = buf;
++		for (; len; len--)
++			rfbi_write_reg(RFBI_CMD, *b++);
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_16:
++	{
++		const u16 *w = buf;
++		BUG_ON(len & 1);
++		for (; len; len -= 2)
++			rfbi_write_reg(RFBI_CMD, *w++);
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_9:
++	case OMAP_DSS_RFBI_PARALLELMODE_12:
++	default:
++		BUG();
++	}
++	rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_command);
++
++void omap_rfbi_read_data(void *buf, u32 len)
++{
++	rfbi_enable_clocks(1);
++	switch (rfbi.parallelmode) {
++	case OMAP_DSS_RFBI_PARALLELMODE_8:
++	{
++		u8 *b = buf;
++		for (; len; len--) {
++			rfbi_write_reg(RFBI_READ, 0);
++			*b++ = rfbi_read_reg(RFBI_READ);
++		}
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_16:
++	{
++		u16 *w = buf;
++		BUG_ON(len & ~1);
++		for (; len; len -= 2) {
++			rfbi_write_reg(RFBI_READ, 0);
++			*w++ = rfbi_read_reg(RFBI_READ);
++		}
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_9:
++	case OMAP_DSS_RFBI_PARALLELMODE_12:
++	default:
++		BUG();
++	}
++	rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_read_data);
++
++void omap_rfbi_write_data(const void *buf, u32 len)
++{
++	rfbi_enable_clocks(1);
++	switch (rfbi.parallelmode) {
++	case OMAP_DSS_RFBI_PARALLELMODE_8:
++	{
++		const u8 *b = buf;
++		for (; len; len--)
++			rfbi_write_reg(RFBI_PARAM, *b++);
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_16:
++	{
++		const u16 *w = buf;
++		BUG_ON(len & 1);
++		for (; len; len -= 2)
++			rfbi_write_reg(RFBI_PARAM, *w++);
++		break;
++	}
++
++	case OMAP_DSS_RFBI_PARALLELMODE_9:
++	case OMAP_DSS_RFBI_PARALLELMODE_12:
++	default:
++		BUG();
++
++	}
++	rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_data);
++
++void omap_rfbi_write_pixels(const void *buf, int scr_width, int x, int y,
++			    int w, int h)
++{
++	int start_offset = scr_width * y + x;
++	int horiz_offset = scr_width - w;
++	int i;
++
++	rfbi_enable_clocks(1);
++
++	if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
++	   rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
++		const u16 *pd = buf;
++		pd += start_offset;
++
++		for (; h; --h) {
++			for (i = 0; i < w; ++i) {
++				const u8 *b = (const u8 *)pd;
++				rfbi_write_reg(RFBI_PARAM, *(b+1));
++				rfbi_write_reg(RFBI_PARAM, *(b+0));
++				++pd;
++			}
++			pd += horiz_offset;
++		}
++	} else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
++	   rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
++		const u32 *pd = buf;
++		pd += start_offset;
++
++		for (; h; --h) {
++			for (i = 0; i < w; ++i) {
++				const u8 *b = (const u8 *)pd;
++				rfbi_write_reg(RFBI_PARAM, *(b+2));
++				rfbi_write_reg(RFBI_PARAM, *(b+1));
++				rfbi_write_reg(RFBI_PARAM, *(b+0));
++				++pd;
++			}
++			pd += horiz_offset;
++		}
++	} else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
++	   rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
++		const u16 *pd = buf;
++		pd += start_offset;
++
++		for (; h; --h) {
++			for (i = 0; i < w; ++i) {
++				rfbi_write_reg(RFBI_PARAM, *pd);
++				++pd;
++			}
++			pd += horiz_offset;
++		}
++	} else {
++		BUG();
++	}
++
++	rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_pixels);
++
++#ifdef MEASURE_PERF
++static void perf_mark_setup(void)
++{
++	rfbi.perf_setup_time = ktime_get();
++}
++
++static void perf_mark_start(void)
++{
++	rfbi.perf_start_time = ktime_get();
++}
++
++static void perf_show(const char *name)
++{
++	ktime_t t, setup_time, trans_time;
++	u32 total_bytes;
++	u32 setup_us, trans_us, total_us;
++
++	t = ktime_get();
++
++	setup_time = ktime_sub(rfbi.perf_start_time, rfbi.perf_setup_time);
++	setup_us = (u32)ktime_to_us(setup_time);
++	if (setup_us == 0)
++		setup_us = 1;
++
++	trans_time = ktime_sub(t, rfbi.perf_start_time);
++	trans_us = (u32)ktime_to_us(trans_time);
++	if (trans_us == 0)
++		trans_us = 1;
++
++	total_us = setup_us + trans_us;
++
++	total_bytes = rfbi.perf_bytes;
++
++	DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
++			"%u kbytes/sec\n",
++			name,
++			setup_us,
++			trans_us,
++			total_us,
++			1000*1000 / total_us,
++			total_bytes,
++			total_bytes * 1000 / total_us);
++}
++#else
++#define perf_mark_setup()
++#define perf_mark_start()
++#define perf_show(x)
++#endif
++
++void rfbi_transfer_area(int width, int height,
++			     void (callback)(void *data), void *data)
++{
++	u32 l;
++
++	/*BUG_ON(callback == 0);*/
++	BUG_ON(rfbi.framedone_callback != NULL);
++
++	DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
++
++	dispc_set_lcd_size(width, height);
++
++	dispc_enable_lcd_out(1);
++
++	rfbi.framedone_callback = callback;
++	rfbi.framedone_callback_data = data;
++
++	rfbi_enable_clocks(1);
++
++	rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
++
++	l = rfbi_read_reg(RFBI_CONTROL);
++	l = FLD_MOD(l, 1, 0, 0); /* enable */
++	if (!rfbi.te_enabled)
++		l = FLD_MOD(l, 1, 4, 4); /* ITE */
++
++	perf_mark_start();
++
++	rfbi_write_reg(RFBI_CONTROL, l);
++}
++
++static void framedone_callback(void *data, u32 mask)
++{
++	void (*callback)(void *data);
++
++	DSSDBG("FRAMEDONE\n");
++
++	perf_show("DISPC");
++
++	REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
++
++	rfbi_enable_clocks(0);
++
++	callback = rfbi.framedone_callback;
++	rfbi.framedone_callback = NULL;
++
++	/*callback(rfbi.framedone_callback_data);*/
++
++	atomic_set(&rfbi.cmd_pending, 0);
++
++	process_cmd_fifo();
++}
++
++#if 1 /* VERBOSE */
++static void rfbi_print_timings(void)
++{
++	u32 l;
++	u32 time;
++
++	l = rfbi_read_reg(RFBI_CONFIG(0));
++	time = 1000000000 / rfbi.l4_khz;
++	if (l & (1 << 4))
++		time *= 2;
++
++	DSSDBG("Tick time %u ps\n", time);
++	l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
++	DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
++		"REONTIME %d, REOFFTIME %d\n",
++		l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
++		(l >> 20) & 0x0f, (l >> 24) & 0x3f);
++
++	l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
++	DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
++		"ACCESSTIME %d\n",
++		(l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
++		(l >> 22) & 0x3f);
++}
++#else
++static void rfbi_print_timings(void) {}
++#endif
++
++
++
++
++static u32 extif_clk_period;
++
++static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
++{
++	int bus_tick = extif_clk_period * div;
++	return (ps + bus_tick - 1) / bus_tick * bus_tick;
++}
++
++static int calc_reg_timing(struct rfbi_timings *t, int div)
++{
++	t->clk_div = div;
++
++	t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
++
++	t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
++	t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
++	t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
++
++	t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
++	t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
++	t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
++
++	t->access_time = round_to_extif_ticks(t->access_time, div);
++	t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
++	t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
++
++	DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
++	       t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
++	DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
++	       t->we_on_time, t->we_off_time, t->re_cycle_time,
++	       t->we_cycle_time);
++	DSSDBG("[reg]rdaccess %d cspulse %d\n",
++	       t->access_time, t->cs_pulse_width);
++
++	return rfbi_convert_timings(t);
++}
++
++static int calc_extif_timings(struct rfbi_timings *t)
++{
++	u32 max_clk_div;
++	int div;
++
++	rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
++	for (div = 1; div <= max_clk_div; div++) {
++		if (calc_reg_timing(t, div) == 0)
++			break;
++	}
++
++	if (div <= max_clk_div)
++		return 0;
++
++	DSSERR("can't setup timings\n");
++	return -1;
++}
++
++
++void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
++{
++	int r;
++
++	if (!t->converted) {
++		r = calc_extif_timings(t);
++		if (r < 0)
++			DSSERR("Failed to calc timings\n");
++	}
++
++	BUG_ON(!t->converted);
++
++	rfbi_enable_clocks(1);
++	rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
++	rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
++
++	/* TIMEGRANULARITY */
++	REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
++		    (t->tim[2] ? 1 : 0), 4, 4);
++
++	rfbi_print_timings();
++	rfbi_enable_clocks(0);
++}
++
++static int ps_to_rfbi_ticks(int time, int div)
++{
++	unsigned long tick_ps;
++	int ret;
++
++	/* Calculate in picosecs to yield more exact results */
++	tick_ps = 1000000000 / (rfbi.l4_khz) * div;
++
++	ret = (time + tick_ps - 1) / tick_ps;
++
++	return ret;
++}
++
++#ifdef OMAP_RFBI_RATE_LIMIT
++unsigned long rfbi_get_max_tx_rate(void)
++{
++	unsigned long   l4_rate, dss1_rate;
++	int             min_l4_ticks = 0;
++	int             i;
++
++	/* According to TI this can't be calculated so make the
++	 * adjustments for a couple of known frequencies and warn for
++	 * others.
++	 */
++	static const struct {
++		unsigned long l4_clk;           /* HZ */
++		unsigned long dss1_clk;         /* HZ */
++		unsigned long min_l4_ticks;
++	} ftab[] = {
++		{ 55,   132,    7, },           /* 7.86 MPix/s */
++		{ 110,  110,    12, },          /* 9.16 MPix/s */
++		{ 110,  132,    10, },          /* 11   Mpix/s */
++		{ 120,  120,    10, },          /* 12   Mpix/s */
++		{ 133,  133,    10, },          /* 13.3 Mpix/s */
++	};
++
++	l4_rate = rfbi.l4_khz / 1000;
++	dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
++
++	for (i = 0; i < ARRAY_SIZE(ftab); i++) {
++		/* Use a window instead of an exact match, to account
++		 * for different DPLL multiplier / divider pairs.
++		 */
++		if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
++		    abs(ftab[i].dss1_clk - dss1_rate) < 3) {
++			min_l4_ticks = ftab[i].min_l4_ticks;
++			break;
++		}
++	}
++	if (i == ARRAY_SIZE(ftab)) {
++		/* Can't be sure, return anyway the maximum not
++		 * rate-limited. This might cause a problem only for the
++		 * tearing synchronisation.
++		 */
++		DSSERR("can't determine maximum RFBI transfer rate\n");
++		return rfbi.l4_khz * 1000;
++	}
++	return rfbi.l4_khz * 1000 / min_l4_ticks;
++}
++#else
++int rfbi_get_max_tx_rate(void)
++{
++	return rfbi.l4_khz * 1000;
++}
++#endif
++
++static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
++{
++	*clk_period = 1000000000 / rfbi.l4_khz;
++	*max_clk_div = 2;
++}
++
++static int rfbi_convert_timings(struct rfbi_timings *t)
++{
++	u32 l;
++	int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
++	int actim, recyc, wecyc;
++	int div = t->clk_div;
++
++	if (div <= 0 || div > 2)
++		return -1;
++
++	/* Make sure that after conversion it still holds that:
++	 * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
++	 * csoff > cson, csoff >= max(weoff, reoff), actim > reon
++	 */
++	weon = ps_to_rfbi_ticks(t->we_on_time, div);
++	weoff = ps_to_rfbi_ticks(t->we_off_time, div);
++	if (weoff <= weon)
++		weoff = weon + 1;
++	if (weon > 0x0f)
++		return -1;
++	if (weoff > 0x3f)
++		return -1;
++
++	reon = ps_to_rfbi_ticks(t->re_on_time, div);
++	reoff = ps_to_rfbi_ticks(t->re_off_time, div);
++	if (reoff <= reon)
++		reoff = reon + 1;
++	if (reon > 0x0f)
++		return -1;
++	if (reoff > 0x3f)
++		return -1;
++
++	cson = ps_to_rfbi_ticks(t->cs_on_time, div);
++	csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
++	if (csoff <= cson)
++		csoff = cson + 1;
++	if (csoff < max(weoff, reoff))
++		csoff = max(weoff, reoff);
++	if (cson > 0x0f)
++		return -1;
++	if (csoff > 0x3f)
++		return -1;
++
++	l =  cson;
++	l |= csoff << 4;
++	l |= weon  << 10;
++	l |= weoff << 14;
++	l |= reon  << 20;
++	l |= reoff << 24;
++
++	t->tim[0] = l;
++
++	actim = ps_to_rfbi_ticks(t->access_time, div);
++	if (actim <= reon)
++		actim = reon + 1;
++	if (actim > 0x3f)
++		return -1;
++
++	wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
++	if (wecyc < weoff)
++		wecyc = weoff;
++	if (wecyc > 0x3f)
++		return -1;
++
++	recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
++	if (recyc < reoff)
++		recyc = reoff;
++	if (recyc > 0x3f)
++		return -1;
++
++	cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
++	if (cs_pulse > 0x3f)
++		return -1;
++
++	l =  wecyc;
++	l |= recyc    << 6;
++	l |= cs_pulse << 12;
++	l |= actim    << 22;
++
++	t->tim[1] = l;
++
++	t->tim[2] = div - 1;
++
++	t->converted = 1;
++
++	return 0;
++}
++
++/* xxx FIX module selection missing */
++int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
++			     unsigned hs_pulse_time, unsigned vs_pulse_time,
++			     int hs_pol_inv, int vs_pol_inv, int extif_div)
++{
++	int hs, vs;
++	int min;
++	u32 l;
++
++	hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
++	vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
++	if (hs < 2)
++		return -EDOM;
++	if (mode == OMAP_DSS_RFBI_TE_MODE_2)
++		min = 2;
++	else /* OMAP_DSS_RFBI_TE_MODE_1 */
++		min = 4;
++	if (vs < min)
++		return -EDOM;
++	if (vs == hs)
++		return -EINVAL;
++	rfbi.te_mode = mode;
++	DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
++		mode, hs, vs, hs_pol_inv, vs_pol_inv);
++
++	rfbi_enable_clocks(1);
++	rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
++	rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
++
++	l = rfbi_read_reg(RFBI_CONFIG(0));
++	if (hs_pol_inv)
++		l &= ~(1 << 21);
++	else
++		l |= 1 << 21;
++	if (vs_pol_inv)
++		l &= ~(1 << 20);
++	else
++		l |= 1 << 20;
++	rfbi_enable_clocks(0);
++
++	return 0;
++}
++EXPORT_SYMBOL(omap_rfbi_setup_te);
++
++/* xxx FIX module selection missing */
++int omap_rfbi_enable_te(int enable, unsigned line)
++{
++	u32 l;
++
++	DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
++	if (line > (1 << 11) - 1)
++		return -EINVAL;
++
++	rfbi_enable_clocks(1);
++	l = rfbi_read_reg(RFBI_CONFIG(0));
++	l &= ~(0x3 << 2);
++	if (enable) {
++		rfbi.te_enabled = 1;
++		l |= rfbi.te_mode << 2;
++	} else
++		rfbi.te_enabled = 0;
++	rfbi_write_reg(RFBI_CONFIG(0), l);
++	rfbi_write_reg(RFBI_LINE_NUMBER, line);
++	rfbi_enable_clocks(0);
++
++	return 0;
++}
++EXPORT_SYMBOL(omap_rfbi_enable_te);
++
++#if 0
++static void rfbi_enable_config(int enable1, int enable2)
++{
++	u32 l;
++	int cs = 0;
++
++	if (enable1)
++		cs |= 1<<0;
++	if (enable2)
++		cs |= 1<<1;
++
++	rfbi_enable_clocks(1);
++
++	l = rfbi_read_reg(RFBI_CONTROL);
++
++	l = FLD_MOD(l, cs, 3, 2);
++	l = FLD_MOD(l, 0, 1, 1);
++
++	rfbi_write_reg(RFBI_CONTROL, l);
++
++
++	l = rfbi_read_reg(RFBI_CONFIG(0));
++	l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
++	/*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
++	/*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
++
++	l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
++	l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
++	l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
++
++	l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
++	rfbi_write_reg(RFBI_CONFIG(0), l);
++
++	rfbi_enable_clocks(0);
++}
++#endif
++
++int rfbi_configure(int rfbi_module, int bpp, int lines)
++{
++	u32 l;
++	int cycle1 = 0, cycle2 = 0, cycle3 = 0;
++	enum omap_rfbi_cycleformat cycleformat;
++	enum omap_rfbi_datatype datatype;
++	enum omap_rfbi_parallelmode parallelmode;
++
++	switch (bpp) {
++	case 12:
++		datatype = OMAP_DSS_RFBI_DATATYPE_12;
++		break;
++	case 16:
++		datatype = OMAP_DSS_RFBI_DATATYPE_16;
++		break;
++	case 18:
++		datatype = OMAP_DSS_RFBI_DATATYPE_18;
++		break;
++	case 24:
++		datatype = OMAP_DSS_RFBI_DATATYPE_24;
++		break;
++	default:
++		BUG();
++		return 1;
++	}
++	rfbi.datatype = datatype;
++
++	switch (lines) {
++	case 8:
++		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
++		break;
++	case 9:
++		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
++		break;
++	case 12:
++		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
++		break;
++	case 16:
++		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
++		break;
++	default:
++		BUG();
++		return 1;
++	}
++	rfbi.parallelmode = parallelmode;
++
++	if ((bpp % lines) == 0) {
++		switch (bpp / lines) {
++		case 1:
++			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
++			break;
++		case 2:
++			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
++			break;
++		case 3:
++			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
++			break;
++		default:
++			BUG();
++			return 1;
++		}
++	} else if ((2 * bpp % lines) == 0) {
++		if ((2 * bpp / lines) == 3)
++			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
++		else {
++			BUG();
++			return 1;
++		}
++	} else {
++		BUG();
++		return 1;
++	}
++
++	switch (cycleformat) {
++	case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
++		cycle1 = lines;
++		break;
++
++	case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
++		cycle1 = lines;
++		cycle2 = lines;
++		break;
++
++	case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
++		cycle1 = lines;
++		cycle2 = lines;
++		cycle3 = lines;
++		break;
++
++	case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
++		cycle1 = lines;
++		cycle2 = (lines / 2) | ((lines / 2) << 16);
++		cycle3 = (lines << 16);
++		break;
++	}
++
++	rfbi_enable_clocks(1);
++
++	REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
++
++	l = 0;
++	l |= FLD_VAL(parallelmode, 1, 0);
++	l |= FLD_VAL(0, 3, 2);		/* TRIGGERMODE: ITE */
++	l |= FLD_VAL(0, 4, 4);		/* TIMEGRANULARITY */
++	l |= FLD_VAL(datatype, 6, 5);
++	/* l |= FLD_VAL(2, 8, 7); */	/* L4FORMAT, 2pix/L4 */
++	l |= FLD_VAL(0, 8, 7);	/* L4FORMAT, 1pix/L4 */
++	l |= FLD_VAL(cycleformat, 10, 9);
++	l |= FLD_VAL(0, 12, 11);	/* UNUSEDBITS */
++	l |= FLD_VAL(0, 16, 16);	/* A0POLARITY */
++	l |= FLD_VAL(0, 17, 17);	/* REPOLARITY */
++	l |= FLD_VAL(0, 18, 18);	/* WEPOLARITY */
++	l |= FLD_VAL(0, 19, 19);	/* CSPOLARITY */
++	l |= FLD_VAL(1, 20, 20);	/* TE_VSYNC_POLARITY */
++	l |= FLD_VAL(1, 21, 21);	/* HSYNCPOLARITY */
++	rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
++
++	rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
++	rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
++	rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
++
++
++	l = rfbi_read_reg(RFBI_CONTROL);
++	l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
++	l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
++	rfbi_write_reg(RFBI_CONTROL, l);
++
++
++	DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
++	       bpp, lines, cycle1, cycle2, cycle3);
++
++	rfbi_enable_clocks(0);
++
++	return 0;
++}
++EXPORT_SYMBOL(rfbi_configure);
++
++static int rfbi_find_display(struct omap_display *disp)
++{
++	if (disp == rfbi.display[0])
++		return 0;
++
++	if (disp == rfbi.display[1])
++		return 1;
++
++	BUG();
++	return -1;
++}
++
++
++static void signal_fifo_waiters(void)
++{
++	if (atomic_read(&rfbi.cmd_fifo_full) > 0) {
++		/* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */
++		complete(&rfbi.cmd_done);
++		atomic_dec(&rfbi.cmd_fifo_full);
++	}
++}
++
++/* returns 1 for async op, and 0 for sync op */
++static int do_update(struct omap_display *display, struct update_region *upd)
++{
++	int x = upd->x;
++	int y = upd->y;
++	int w = upd->w;
++	int h = upd->h;
++
++	perf_mark_setup();
++
++	if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++		/*display->ctrl->enable_te(display, 1); */
++		dispc_setup_partial_planes(display, &x, &y, &w, &h);
++	}
++
++#ifdef MEASURE_PERF
++	rfbi.perf_bytes = w * h * 2; /* XXX always 16bit */
++#endif
++
++	display->ctrl->setup_update(display, x, y, w, h);
++
++	if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++		rfbi_transfer_area(w, h, NULL, NULL);
++		return 1;
++	} else {
++		struct omap_overlay *ovl;
++		void *addr;
++		int scr_width;
++
++		ovl = &display->manager->overlays[0];
++		scr_width = ovl->info.screen_width;
++		addr = ovl->info.vaddr;
++
++		omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
++
++		perf_show("L4");
++
++		return 0;
++	}
++}
++
++static void process_cmd_fifo(void)
++{
++	int len;
++	struct update_param p;
++	struct omap_display *display;
++	unsigned long flags;
++
++	if (atomic_inc_return(&rfbi.cmd_pending) != 1)
++		return;
++
++	while (true) {
++		spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
++
++		len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p,
++				  sizeof(struct update_param));
++		if (len == 0) {
++			DSSDBG("nothing more in fifo\n");
++			atomic_set(&rfbi.cmd_pending, 0);
++			spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++			break;
++		}
++
++		/* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/
++
++		spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++
++		BUG_ON(len != sizeof(struct update_param));
++		BUG_ON(p.rfbi_module > 1);
++
++		display = rfbi.display[p.rfbi_module];
++
++		if (p.cmd == RFBI_CMD_UPDATE) {
++			if (do_update(display, &p.par.r))
++				break; /* async op */
++		} else if (p.cmd == RFBI_CMD_SYNC) {
++			DSSDBG("Signaling SYNC done!\n");
++			complete(p.par.sync);
++		} else
++			BUG();
++	}
++
++	signal_fifo_waiters();
++}
++
++static void rfbi_push_cmd(struct update_param *p)
++{
++	int ret;
++
++	while (1) {
++		unsigned long flags;
++		int available;
++
++		spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
++		available = RFBI_CMD_FIFO_LEN_BYTES -
++			__kfifo_len(rfbi.cmd_fifo);
++
++/*		DSSDBG("%d bytes left in fifo\n", available); */
++		if (available < sizeof(struct update_param)) {
++			DSSDBG("Going to wait because FIFO FULL..\n");
++			spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++			atomic_inc(&rfbi.cmd_fifo_full);
++			wait_for_completion(&rfbi.cmd_done);
++			/*DSSDBG("Woke up because fifo not full anymore\n");*/
++			continue;
++		}
++
++		ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p,
++				  sizeof(struct update_param));
++/*		DSSDBG("pushed %d bytes\n", ret);*/
++
++		spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++
++		BUG_ON(ret != sizeof(struct update_param));
++
++		break;
++	}
++}
++
++static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h)
++{
++	struct update_param p;
++
++	p.rfbi_module = rfbi_module;
++	p.cmd = RFBI_CMD_UPDATE;
++
++	p.par.r.x = x;
++	p.par.r.y = y;
++	p.par.r.w = w;
++	p.par.r.h = h;
++
++	DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h);
++
++	rfbi_push_cmd(&p);
++
++	process_cmd_fifo();
++}
++
++static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp)
++{
++	struct update_param p;
++
++	p.rfbi_module = rfbi_module;
++	p.cmd = RFBI_CMD_SYNC;
++	p.par.sync = sync_comp;
++
++	rfbi_push_cmd(&p);
++
++	DSSDBG("RFBI sync pushed to cmd fifo\n");
++
++	process_cmd_fifo();
++}
++
++int rfbi_init(void)
++{
++	u32 rev;
++	u32 l;
++
++	spin_lock_init(&rfbi.cmd_lock);
++	rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL,
++				    &rfbi.cmd_lock);
++	if (IS_ERR(rfbi.cmd_fifo))
++		return -ENOMEM;
++
++	init_completion(&rfbi.cmd_done);
++	atomic_set(&rfbi.cmd_fifo_full, 0);
++	atomic_set(&rfbi.cmd_pending, 0);
++
++	rfbi.base = ioremap(RFBI_BASE, SZ_256);
++	if (!rfbi.base) {
++		DSSERR("can't ioremap RFBI\n");
++		return -ENOMEM;
++	}
++
++	rfbi_enable_clocks(1);
++
++	msleep(10);
++
++	rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
++
++	/* Enable autoidle and smart-idle */
++	l = rfbi_read_reg(RFBI_SYSCONFIG);
++	l |= (1 << 0) | (2 << 3);
++	rfbi_write_reg(RFBI_SYSCONFIG, l);
++
++	rev = rfbi_read_reg(RFBI_REVISION);
++	printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
++	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++	rfbi_enable_clocks(0);
++
++	return 0;
++}
++
++void rfbi_exit(void)
++{
++	DSSDBG("rfbi_exit\n");
++
++	kfifo_free(rfbi.cmd_fifo);
++
++	iounmap(rfbi.base);
++}
++
++/* struct omap_display support */
++static int rfbi_display_update(struct omap_display *display,
++			int x, int y, int w, int h)
++{
++	int rfbi_module;
++
++	if (w == 0 || h == 0)
++		return 0;
++
++	rfbi_module = rfbi_find_display(display);
++
++	rfbi_push_update(rfbi_module, x, y, w, h);
++
++	return 0;
++}
++
++static int rfbi_display_sync(struct omap_display *display)
++{
++	struct completion sync_comp;
++	int rfbi_module;
++
++	rfbi_module = rfbi_find_display(display);
++
++	init_completion(&sync_comp);
++	rfbi_push_sync(rfbi_module, &sync_comp);
++	DSSDBG("Waiting for SYNC to happen...\n");
++	wait_for_completion(&sync_comp);
++	DSSDBG("Released from SYNC\n");
++	return 0;
++}
++
++static int rfbi_display_enable_te(struct omap_display *display, int enable)
++{
++	display->ctrl->enable_te(display, enable);
++	return 0;
++}
++
++static int rfbi_display_enable(struct omap_display *display)
++{
++	int r;
++
++	BUG_ON(display->panel == NULL || display->ctrl == NULL);
++
++	r = omap_dispc_register_isr(framedone_callback, NULL,
++			DISPC_IRQ_FRAMEDONE);
++	if (r) {
++		DSSERR("can't get FRAMEDONE irq\n");
++		return r;
++	}
++
++	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++
++	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
++
++	dispc_set_tft_data_lines(display->ctrl->pixel_size);
++
++	rfbi_configure(display->hw_config.u.rfbi.channel,
++			       display->ctrl->pixel_size,
++			       display->hw_config.u.rfbi.data_lines);
++
++	rfbi_set_timings(display->hw_config.u.rfbi.channel,
++			 &display->ctrl->timings);
++
++
++	if (display->ctrl && display->ctrl->enable) {
++		r = display->ctrl->enable(display);
++		if (r)
++			goto err;
++	}
++
++	if (display->panel && display->panel->enable) {
++		r = display->panel->enable(display);
++		if (r)
++			goto err;
++	}
++
++	return 0;
++err:
++	return -ENODEV;
++}
++
++static void rfbi_display_disable(struct omap_display *display)
++{
++	display->ctrl->disable(display);
++	omap_dispc_unregister_isr(framedone_callback);
++}
++
++void rfbi_init_display(struct omap_display *display)
++{
++	display->enable = rfbi_display_enable;
++	display->disable = rfbi_display_disable;
++	display->update = rfbi_display_update;
++	display->sync = rfbi_display_sync;
++	display->enable_te = rfbi_display_enable_te;
++
++	rfbi.display[display->hw_config.u.rfbi.channel] = display;
++
++	display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++}
+diff --git a/arch/arm/plat-omap/dss/sdi.c b/arch/arm/plat-omap/dss/sdi.c
+new file mode 100644
+index 0000000..02d549b
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/sdi.c
+@@ -0,0 +1,174 @@
++/*
++ * linux/arch/arm/plat-omap/dss/sdi.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "SDI"
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++
++static struct {
++	int update_enabled;
++} sdi;
++
++static int sdi_display_enable(struct omap_display *display)
++{
++	struct dispc_clock_info cinfo;
++	int lck_div, pck_div;
++	unsigned long fck;
++	struct omap_panel *panel = display->panel;
++	unsigned high, low, burst;
++	unsigned long pck;
++
++	if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++		DSSERR("display already enabled\n");
++		return -EINVAL;
++	}
++
++	panel->enable(display);
++
++	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
++
++	dispc_set_burst_size(OMAP_DSS_GFX, OMAP_DSS_BURST_16x32);
++	dispc_set_burst_size(OMAP_DSS_VIDEO1, OMAP_DSS_BURST_16x32);
++	dispc_set_burst_size(OMAP_DSS_VIDEO2, OMAP_DSS_BURST_16x32);
++
++	burst = 16 * 32 / 8;
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_GFX) - burst;
++	low = dispc_get_plane_fifo_size(OMAP_DSS_GFX) / 4 * 3;
++	dispc_setup_plane_fifo(OMAP_DSS_GFX, low, high);
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO1) - burst;
++	low = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO1) / 4 * 3;
++	dispc_setup_plane_fifo(OMAP_DSS_VIDEO1, low, high);
++
++	high = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO2) - burst;
++	low = dispc_get_plane_fifo_size(OMAP_DSS_VIDEO2) / 4 * 3;
++	dispc_setup_plane_fifo(OMAP_DSS_VIDEO2, low, high);
++
++	/* 15.5.9.1.2 */
++	panel->config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
++
++	dispc_set_pol_freq(panel);
++
++	dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000,
++			&cinfo);
++
++	if (dispc_set_clock_div(&cinfo)) {
++		DSSERR("Failed to set DSS clocks\n");
++		return -EINVAL;
++	}
++
++	fck = cinfo.fck;
++	lck_div = cinfo.lck_div;
++	pck_div = cinfo.pck_div;
++
++	pck = fck / lck_div / pck_div / 1000;
++
++	if (pck != panel->timings.pixel_clock) {
++		DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
++				"got %lu kHz\n",
++				panel->timings.pixel_clock, pck);
++
++		panel->timings.pixel_clock = pck;
++	}
++
++	dispc_set_lcd_timings(&panel->timings);
++
++	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++	dispc_set_tft_data_lines(24);
++	dispc_lcd_enable_signal_polarity(1);
++	dispc_pck_free_enable(1);
++
++	dss_sdi_init(display->hw_config.u.sdi.datapairs);
++
++	mdelay(2);
++
++	dispc_enable_lcd_out(1);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	return 0;
++}
++
++static void sdi_display_disable(struct omap_display *display)
++{
++	if (display->state == OMAP_DSS_DISPLAY_DISABLED)
++		return;
++
++	display->panel->disable(display);
++	dispc_enable_lcd_out(0);
++
++	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++}
++
++static int sdi_display_set_update_mode(struct omap_display *display,
++		enum omap_dss_update_mode mode)
++{
++	if (mode == OMAP_DSS_UPDATE_MANUAL)
++		return -EINVAL;
++
++	if (mode == OMAP_DSS_UPDATE_DISABLED) {
++		dispc_enable_lcd_out(0);
++		sdi.update_enabled = 0;
++	} else {
++		dispc_enable_lcd_out(1);
++		sdi.update_enabled = 1;
++	}
++
++	return 0;
++}
++
++static enum omap_dss_update_mode sdi_display_get_update_mode(
++		struct omap_display *display)
++{
++	return sdi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
++		OMAP_DSS_UPDATE_DISABLED;
++}
++
++
++void sdi_init_display(struct omap_display *display)
++{
++	DSSDBG("SDI init\n");
++
++	display->enable = sdi_display_enable;
++	display->disable = sdi_display_disable;
++	display->set_update_mode = sdi_display_set_update_mode;
++	display->get_update_mode = sdi_display_get_update_mode;
++}
++
++int sdi_init(void)
++{
++	return 0;
++}
++
++void sdi_exit(void)
++{
++}
+diff --git a/arch/arm/plat-omap/dss/venc.c b/arch/arm/plat-omap/dss/venc.c
+new file mode 100644
+index 0000000..81319e4
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/venc.c
+@@ -0,0 +1,506 @@
++/*
++ * linux/arch/arm/plat-omap/dss/venc.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * VENC settings from TI's DSS driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "VENC"
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/mutex.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++#include <mach/cpu.h>
++
++#include "dss.h"
++
++#define VENC_BASE	0x48050C00
++
++/* Venc registers */
++#define VENC_REV_ID				0x00
++#define VENC_STATUS				0x04
++#define VENC_F_CONTROL				0x08
++#define VENC_VIDOUT_CTRL			0x10
++#define VENC_SYNC_CTRL				0x14
++#define VENC_LLEN				0x1C
++#define VENC_FLENS				0x20
++#define VENC_HFLTR_CTRL				0x24
++#define VENC_CC_CARR_WSS_CARR			0x28
++#define VENC_C_PHASE				0x2C
++#define VENC_GAIN_U				0x30
++#define VENC_GAIN_V				0x34
++#define VENC_GAIN_Y				0x38
++#define VENC_BLACK_LEVEL			0x3C
++#define VENC_BLANK_LEVEL			0x40
++#define VENC_X_COLOR				0x44
++#define VENC_M_CONTROL				0x48
++#define VENC_BSTAMP_WSS_DATA			0x4C
++#define VENC_S_CARR				0x50
++#define VENC_LINE21				0x54
++#define VENC_LN_SEL				0x58
++#define VENC_L21__WC_CTL			0x5C
++#define VENC_HTRIGGER_VTRIGGER			0x60
++#define VENC_SAVID__EAVID			0x64
++#define VENC_FLEN__FAL				0x68
++#define VENC_LAL__PHASE_RESET			0x6C
++#define VENC_HS_INT_START_STOP_X		0x70
++#define VENC_HS_EXT_START_STOP_X		0x74
++#define VENC_VS_INT_START_X			0x78
++#define VENC_VS_INT_STOP_X__VS_INT_START_Y	0x7C
++#define VENC_VS_INT_STOP_Y__VS_EXT_START_X	0x80
++#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y	0x84
++#define VENC_VS_EXT_STOP_Y			0x88
++#define VENC_AVID_START_STOP_X			0x90
++#define VENC_AVID_START_STOP_Y			0x94
++#define VENC_FID_INT_START_X__FID_INT_START_Y	0xA0
++#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X	0xA4
++#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y	0xA8
++#define VENC_TVDETGP_INT_START_STOP_X		0xB0
++#define VENC_TVDETGP_INT_START_STOP_Y		0xB4
++#define VENC_GEN_CTRL				0xB8
++#define VENC_OUTPUT_CONTROL			0xC4
++#define VENC_DAC_B__DAC_C			0xC8
++
++struct venc_config {
++	u32 f_control;
++	u32 vidout_ctrl;
++	u32 sync_ctrl;
++	u32 llen;
++	u32 flens;
++	u32 hfltr_ctrl;
++	u32 cc_carr_wss_carr;
++	u32 c_phase;
++	u32 gain_u;
++	u32 gain_v;
++	u32 gain_y;
++	u32 black_level;
++	u32 blank_level;
++	u32 x_color;
++	u32 m_control;
++	u32 bstamp_wss_data;
++	u32 s_carr;
++	u32 line21;
++	u32 ln_sel;
++	u32 l21__wc_ctl;
++	u32 htrigger_vtrigger;
++	u32 savid__eavid;
++	u32 flen__fal;
++	u32 lal__phase_reset;
++	u32 hs_int_start_stop_x;
++	u32 hs_ext_start_stop_x;
++	u32 vs_int_start_x;
++	u32 vs_int_stop_x__vs_int_start_y;
++	u32 vs_int_stop_y__vs_ext_start_x;
++	u32 vs_ext_stop_x__vs_ext_start_y;
++	u32 vs_ext_stop_y;
++	u32 avid_start_stop_x;
++	u32 avid_start_stop_y;
++	u32 fid_int_start_x__fid_int_start_y;
++	u32 fid_int_offset_y__fid_ext_start_x;
++	u32 fid_ext_start_y__fid_ext_offset_y;
++	u32 tvdetgp_int_start_stop_x;
++	u32 tvdetgp_int_start_stop_y;
++	u32 gen_ctrl;
++
++	int width;
++	int height;
++};
++
++/* from TRM */
++static const struct venc_config venc_config_pal_trm = {
++	.f_control				= 0,
++	.vidout_ctrl				= 1,
++	.sync_ctrl				= 0x40,
++	.llen					= 0x35F, /* 863 */
++	.flens					= 0x270, /* 624 */
++	.hfltr_ctrl				= 0,
++	.cc_carr_wss_carr			= 0x2F7225ED,
++	.c_phase				= 0,
++	.gain_u					= 0x111,
++	.gain_v					= 0x181,
++	.gain_y					= 0x140,
++	.black_level				= 0x3B,
++	.blank_level				= 0x3B,
++	.x_color				= 0x7,
++	.m_control				= 0x2,
++	.bstamp_wss_data			= 0x3F,
++	.s_carr					= 0x2A098ACB,
++	.line21					= 0,
++	.ln_sel					= 0x01290015,
++	.l21__wc_ctl				= 0x0000F603,
++	.htrigger_vtrigger			= 0,
++
++	.savid__eavid				= 0x06A70108,
++	.flen__fal				= 0x00180270,
++	.lal__phase_reset			= 0x00180270,
++	.hs_int_start_stop_x			= 0x00880358,
++	.hs_ext_start_stop_x			= 0x000F035F,
++	.vs_int_start_x				= 0x01A70000,
++	.vs_int_stop_x__vs_int_start_y		= 0x000001A7,
++	.vs_int_stop_y__vs_ext_start_x		= 0x01AF0000,
++	.vs_ext_stop_x__vs_ext_start_y		= 0x000101AF,
++	.vs_ext_stop_y				= 0x00000025,
++	.avid_start_stop_x			= 0x03530083,
++	.avid_start_stop_y			= 0x026C002E,
++	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
++	.fid_int_offset_y__fid_ext_start_x	= 0x002E0138,
++	.fid_ext_start_y__fid_ext_offset_y	= 0x01380001,
++
++	.tvdetgp_int_start_stop_x		= 0x00140001,
++	.tvdetgp_int_start_stop_y		= 0x00010001,
++	.gen_ctrl				= 0x00FF0000,
++
++	.width = 720,
++	.height = 574, /* for some reason, this isn't 576 */
++};
++
++/* from TRM */
++static const struct venc_config venc_config_ntsc_trm = {
++	.f_control				= 0,
++	.vidout_ctrl				= 1,
++	.sync_ctrl				= 0x8040,
++	.llen					= 0x359,
++	.flens					= 0x20C,
++	.hfltr_ctrl				= 0,
++	.cc_carr_wss_carr			= 0x043F2631,
++	.c_phase				= 0,
++	.gain_u					= 0x102,
++	.gain_v					= 0x16C,
++	.gain_y					= 0x12F,
++	.black_level				= 0x43,
++	.blank_level				= 0x38,
++	.x_color				= 0x7,
++	.m_control				= 0x1,
++	.bstamp_wss_data			= 0x38,
++	.s_carr					= 0x21F07C1F,
++	.line21					= 0,
++	.ln_sel					= 0x01310011,
++	.l21__wc_ctl				= 0x0000F003,
++	.htrigger_vtrigger			= 0,
++
++	.savid__eavid				= 0x069300F4,
++	.flen__fal				= 0x0016020C,
++	.lal__phase_reset			= 0x00060107,
++	.hs_int_start_stop_x			= 0x008E0350,
++	.hs_ext_start_stop_x			= 0x000F0359,
++	.vs_int_start_x				= 0x01A00000,
++	.vs_int_stop_x__vs_int_start_y		= 0x020701A0,
++	.vs_int_stop_y__vs_ext_start_x		= 0x01AC0024,
++	.vs_ext_stop_x__vs_ext_start_y		= 0x020D01AC,
++	.vs_ext_stop_y				= 0x00000006,
++	.avid_start_stop_x			= 0x03480078,
++	.avid_start_stop_y			= 0x02060024,
++	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
++	.fid_int_offset_y__fid_ext_start_x	= 0x01AC0106,
++	.fid_ext_start_y__fid_ext_offset_y	= 0x01060006,
++
++	.tvdetgp_int_start_stop_x		= 0x00140001,
++	.tvdetgp_int_start_stop_y		= 0x00010001,
++	.gen_ctrl				= 0x00F90000,
++
++	.width = 720,
++	.height = 482,
++};
++
++static const struct venc_config venc_config_pal_bdghi = {
++	.f_control				= 0,
++	.vidout_ctrl				= 0,
++	.sync_ctrl				= 0,
++	.hfltr_ctrl				= 0,
++	.x_color				= 0,
++	.line21					= 0,
++	.ln_sel					= 21,
++	.htrigger_vtrigger			= 0,
++	.tvdetgp_int_start_stop_x		= 0x00140001,
++	.tvdetgp_int_start_stop_y		= 0x00010001,
++	.gen_ctrl				= 0x00FB0000,
++
++	.llen					= 864-1,
++	.flens					= 625-1,
++	.cc_carr_wss_carr			= 0x2F7625ED,
++	.c_phase				= 0xDF,
++	.gain_u					= 0x111,
++	.gain_v					= 0x181,
++	.gain_y					= 0x140,
++	.black_level				= 0x3e,
++	.blank_level				= 0x3e,
++	.m_control				= 0<<2 | 1<<1,
++	.bstamp_wss_data			= 0x42,
++	.s_carr					= 0x2a098acb,
++	.l21__wc_ctl				= 0<<13 | 0x16<<8 | 0<<0,
++	.savid__eavid				= 0x06A70108,
++	.flen__fal				= 23<<16 | 624<<0,
++	.lal__phase_reset			= 2<<17 | 310<<0,
++	.hs_int_start_stop_x			= 0x00920358,
++	.hs_ext_start_stop_x			= 0x000F035F,
++	.vs_int_start_x				= 0x1a7<<16,
++	.vs_int_stop_x__vs_int_start_y		= 0x000601A7,
++	.vs_int_stop_y__vs_ext_start_x		= 0x01AF0036,
++	.vs_ext_stop_x__vs_ext_start_y		= 0x27101af,
++	.vs_ext_stop_y				= 0x05,
++	.avid_start_stop_x			= 0x03530082,
++	.avid_start_stop_y			= 0x0270002E,
++	.fid_int_start_x__fid_int_start_y	= 0x0005008A,
++	.fid_int_offset_y__fid_ext_start_x	= 0x002E0138,
++	.fid_ext_start_y__fid_ext_offset_y	= 0x01380005,
++
++	.width = 720,
++	.height = 576,
++};
++
++static struct {
++	void __iomem *base;
++	const struct venc_config *config;
++	struct mutex venc_lock;
++} venc;
++
++static struct omap_panel venc_panel = {
++	.name = "tv-out",
++	.bpp = 24,
++};
++
++static inline void venc_write_reg(int idx, u32 val)
++{
++	__raw_writel(val, venc.base + idx);
++}
++
++static inline u32 venc_read_reg(int idx)
++{
++	u32 l = __raw_readl(venc.base + idx);
++	return l;
++}
++
++static void venc_write_config(const struct venc_config *config)
++{
++	DSSDBG("write venc conf\n");
++
++	venc_write_reg(VENC_LLEN, config->llen);
++	venc_write_reg(VENC_FLENS, config->flens);
++	venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
++	venc_write_reg(VENC_C_PHASE, config->c_phase);
++	venc_write_reg(VENC_GAIN_U, config->gain_u);
++	venc_write_reg(VENC_GAIN_V, config->gain_v);
++	venc_write_reg(VENC_GAIN_Y, config->gain_y);
++	venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
++	venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
++	venc_write_reg(VENC_M_CONTROL, config->m_control);
++	venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
++	venc_write_reg(VENC_S_CARR, config->s_carr);
++	venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
++	venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
++	venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
++	venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
++	venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
++	venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
++	venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
++	venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
++		       config->vs_int_stop_x__vs_int_start_y);
++	venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
++		       config->vs_int_stop_y__vs_ext_start_x);
++	venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
++		       config->vs_ext_stop_x__vs_ext_start_y);
++	venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
++	venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
++	venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
++	venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
++		       config->fid_int_start_x__fid_int_start_y);
++	venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
++		       config->fid_int_offset_y__fid_ext_start_x);
++	venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
++		       config->fid_ext_start_y__fid_ext_offset_y);
++
++	venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
++	venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
++	venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
++	venc_write_reg(VENC_X_COLOR, config->x_color);
++	venc_write_reg(VENC_LINE21, config->line21);
++	venc_write_reg(VENC_LN_SEL, config->ln_sel);
++	venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
++	venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
++		       config->tvdetgp_int_start_stop_x);
++	venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
++		       config->tvdetgp_int_start_stop_y);
++	venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
++	venc_write_reg(VENC_F_CONTROL, config->f_control);
++	venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
++}
++
++static void venc_reset(void)
++{
++	int t = 1000;
++
++	venc_write_reg(VENC_F_CONTROL, venc_read_reg(VENC_F_CONTROL) | (1<<8));
++	while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
++		if (--t == 0) {
++			DSSERR("Failed to reset venc\n");
++			return;
++		}
++	}
++}
++
++static void venc_enable_clocks(int enable)
++{
++	if (enable)
++		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
++				DSS_CLK_96M);
++	else
++		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
++				DSS_CLK_96M);
++}
++
++int venc_init(void)
++{
++	u8 rev_id;
++	int use_pal = 1; /* XXX */
++
++	mutex_init(&venc.venc_lock);
++
++	if (use_pal)
++		venc.config = &venc_config_pal_trm;
++	else
++		venc.config = &venc_config_ntsc_trm;
++
++	venc_panel.timings.x_res = venc.config->width;
++	venc_panel.timings.y_res = venc.config->height;
++
++	venc.base = ioremap(VENC_BASE, SZ_1K);
++	if (!venc.base) {
++		DSSERR("can't ioremap VENC\n");
++		return -ENOMEM;
++	}
++
++	/* enable clocks */
++	venc_enable_clocks(1);
++
++	/* configure venc */
++	venc_reset();
++	venc_write_config(venc.config);
++
++	rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
++	printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
++
++	venc_enable_clocks(0);
++
++	return 0;
++}
++
++void venc_exit(void)
++{
++	iounmap(venc.base);
++}
++
++static void venc_sync_lost_handler(void *arg, u32 mask)
++{
++	/* we just catch SYNC_LOST_DIGIT here so that
++	 * dispc doesn't take it as an error */
++}
++
++static int venc_enable_display(struct omap_display *display)
++{
++	DSSDBG("venc_enable_display\n");
++
++	mutex_lock(&venc.venc_lock);
++
++	if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++		mutex_unlock(&venc.venc_lock);
++		return -EINVAL;
++	}
++
++	venc_enable_clocks(1);
++
++	dss_set_venc_output(display->hw_config.u.venc.type);
++	dss_set_dac_pwrdn_bgz(1);
++
++	if (display->hw_config.u.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) {
++		if (cpu_is_omap24xx())
++			venc_write_reg(VENC_OUTPUT_CONTROL, 0x2);
++		else
++			venc_write_reg(VENC_OUTPUT_CONTROL, 0xa);
++	} else { /* S-Video */
++		venc_write_reg(VENC_OUTPUT_CONTROL, 0xd);
++	}
++
++	venc_write_config(venc.config);
++
++	dispc_set_digit_size(venc.config->width, venc.config->height/2);
++
++	if (display->hw_config.panel_enable)
++		display->hw_config.panel_enable(display);
++
++	dispc_go(OMAP_DSS_CHANNEL_DIGIT);
++
++	omap_dispc_register_isr(venc_sync_lost_handler, NULL,
++			DISPC_IRQ_SYNC_LOST_DIGIT);
++
++	dispc_enable_digit_out(1);
++
++	mdelay(20);
++
++	omap_dispc_unregister_isr(venc_sync_lost_handler);
++
++	display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++	mutex_unlock(&venc.venc_lock);
++
++	return 0;
++}
++
++static void venc_disable_display(struct omap_display *display)
++{
++	DSSDBG("venc_disable_display\n");
++
++	mutex_lock(&venc.venc_lock);
++
++	if (display->state == OMAP_DSS_DISPLAY_DISABLED) {
++		mutex_unlock(&venc.venc_lock);
++		return;
++	}
++
++	venc_write_reg(VENC_OUTPUT_CONTROL, 0);
++	dss_set_dac_pwrdn_bgz(0);
++
++	dispc_enable_digit_out(0);
++
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++
++	venc_enable_clocks(0);
++
++	display->state = OMAP_DSS_DISPLAY_DISABLED;
++
++	mutex_unlock(&venc.venc_lock);
++}
++
++static void venc_get_timings(struct omap_display *display,
++			struct omap_video_timings *timings)
++{
++	*timings = venc_panel.timings;
++}
++
++void venc_init_display(struct omap_display *display)
++{
++	display->panel = &venc_panel;
++	display->enable = venc_enable_display;
++	display->disable = venc_disable_display;
++	display->get_timings = venc_get_timings;
++}
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+new file mode 100644
+index 0000000..49ab00a
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -0,0 +1,462 @@
++/*
++ * linux/include/asm-arm/arch-omap/display.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __ASM_ARCH_OMAP_DISPLAY_H
++#define __ASM_ARCH_OMAP_DISPLAY_H
++
++#include <asm/atomic.h>
++
++#define DISPC_IRQ_FRAMEDONE		(1 << 0)
++#define DISPC_IRQ_VSYNC			(1 << 1)
++#define DISPC_IRQ_EVSYNC_EVEN		(1 << 2)
++#define DISPC_IRQ_EVSYNC_ODD		(1 << 3)
++#define DISPC_IRQ_ACBIAS_COUNT_STAT	(1 << 4)
++#define DISPC_IRQ_PROG_LINE_NUM		(1 << 5)
++#define DISPC_IRQ_GFX_FIFO_UNDERFLOW	(1 << 6)
++#define DISPC_IRQ_GFX_END_WIN		(1 << 7)
++#define DISPC_IRQ_PAL_GAMMA_MASK	(1 << 8)
++#define DISPC_IRQ_OCP_ERR		(1 << 9)
++#define DISPC_IRQ_VID1_FIFO_UNDERFLOW	(1 << 10)
++#define DISPC_IRQ_VID1_END_WIN		(1 << 11)
++#define DISPC_IRQ_VID2_FIFO_UNDERFLOW	(1 << 12)
++#define DISPC_IRQ_VID2_END_WIN		(1 << 13)
++#define DISPC_IRQ_SYNC_LOST		(1 << 14)
++#define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
++
++enum omap_display_type {
++	OMAP_DISPLAY_TYPE_NONE		= 0,
++	OMAP_DISPLAY_TYPE_DPI		= 1 << 0,
++	OMAP_DISPLAY_TYPE_DBI		= 1 << 1,
++	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
++	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
++	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
++};
++
++enum omap_plane {
++	OMAP_DSS_GFX	= 0,
++	OMAP_DSS_VIDEO1	= 1,
++	OMAP_DSS_VIDEO2	= 2
++};
++
++enum omap_channel {
++	OMAP_DSS_CHANNEL_LCD	= 0,
++	OMAP_DSS_CHANNEL_DIGIT	= 1,
++};
++
++enum omap_color_mode {
++	OMAP_DSS_COLOR_CLUT1	= 1 << 0,  /* BITMAP 1 */
++	OMAP_DSS_COLOR_CLUT2	= 1 << 1,  /* BITMAP 2 */
++	OMAP_DSS_COLOR_CLUT4	= 1 << 2,  /* BITMAP 4 */
++	OMAP_DSS_COLOR_CLUT8	= 1 << 3,  /* BITMAP 8 */
++	OMAP_DSS_COLOR_RGB12U	= 1 << 4,  /* RGB12, 16-bit container */
++	OMAP_DSS_COLOR_ARGB16	= 1 << 5,  /* ARGB16 */
++	OMAP_DSS_COLOR_RGB16	= 1 << 6,  /* RGB16 */
++	OMAP_DSS_COLOR_RGB24U	= 1 << 7,  /* RGB24, 32-bit container */
++	OMAP_DSS_COLOR_RGB24P	= 1 << 8,  /* RGB24, 24-bit container */
++	OMAP_DSS_COLOR_YUV2	= 1 << 9,  /* YUV2 4:2:2 co-sited */
++	OMAP_DSS_COLOR_UYVY	= 1 << 10, /* UYVY 4:2:2 co-sited */
++	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
++	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
++	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
++
++	OMAP_DSS_COLOR_GFX_OMAP3 =
++		OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
++		OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
++		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
++		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
++		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
++		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
++
++	OMAP_DSS_COLOR_VID_OMAP3 =
++		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
++		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
++		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
++		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
++		OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
++};
++
++enum omap_lcd_display_type {
++	OMAP_DSS_LCD_DISPLAY_STN,
++	OMAP_DSS_LCD_DISPLAY_TFT,
++};
++
++enum omap_dss_load_mode {
++	OMAP_DSS_LOAD_CLUT_AND_FRAME	= 0,
++	OMAP_DSS_LOAD_CLUT_ONLY		= 1,
++	OMAP_DSS_LOAD_FRAME_ONLY	= 2,
++	OMAP_DSS_LOAD_CLUT_ONCE_FRAME	= 3,
++};
++
++enum omap_dss_color_key_type {
++	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
++	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
++};
++
++enum omap_rfbi_te_mode {
++	OMAP_DSS_RFBI_TE_MODE_1 = 1,
++	OMAP_DSS_RFBI_TE_MODE_2 = 2,
++};
++
++enum omap_panel_config {
++	OMAP_DSS_LCD_IVS		= 1<<0,
++	OMAP_DSS_LCD_IHS		= 1<<1,
++	OMAP_DSS_LCD_IPC		= 1<<2,
++	OMAP_DSS_LCD_IEO		= 1<<3,
++	OMAP_DSS_LCD_RF			= 1<<4,
++	OMAP_DSS_LCD_ONOFF		= 1<<5,
++
++	OMAP_DSS_LCD_TFT		= 1<<20,
++};
++
++enum omap_dss_venc_type {
++	OMAP_DSS_VENC_TYPE_COMPOSITE,
++	OMAP_DSS_VENC_TYPE_SVIDEO,
++};
++
++struct omap_display;
++struct omap_panel;
++struct omap_ctrl;
++
++/* RFBI */
++
++struct rfbi_timings {
++	int cs_on_time;
++	int cs_off_time;
++	int we_on_time;
++	int we_off_time;
++	int re_on_time;
++	int re_off_time;
++	int we_cycle_time;
++	int re_cycle_time;
++	int cs_pulse_width;
++	int access_time;
++
++	int clk_div;
++
++	u32 tim[5];             /* set by rfbi_convert_timings() */
++
++	int converted;
++};
++
++void omap_rfbi_write_command(const void *buf, u32 len);
++void omap_rfbi_read_data(void *buf, u32 len);
++void omap_rfbi_write_data(const void *buf, u32 len);
++void omap_rfbi_write_pixels(const void *buf, int scr_width, int x, int y,
++			    int w, int h);
++int omap_rfbi_enable_te(int enable, unsigned line);
++int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
++			     unsigned hs_pulse_time, unsigned vs_pulse_time,
++			     int hs_pol_inv, int vs_pol_inv, int extif_div);
++
++/* DSI */
++int dsi_vc_dcs_write(int channel, u8 *data, int len);
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
++int dsi_vc_send_null(int channel);
++
++/* Board specific data */
++struct omap_display_data {
++	enum omap_display_type type;
++
++	union {
++		struct {
++			int data_lines;
++		} dpi;
++
++		struct {
++			int channel;
++			int data_lines;
++		} rfbi;
++
++		struct {
++			int datapairs;
++		} sdi;
++
++		struct {
++			int clk_lane;
++			int clk_pol;
++			int data1_lane;
++			int data1_pol;
++			int data2_lane;
++			int data2_pol;
++			unsigned long ddr_clk_hz;
++		} dsi;
++
++		struct {
++			enum omap_dss_venc_type type;
++		} venc;
++	} u;
++
++	int panel_reset_gpio;
++	int ctrl_reset_gpio;
++
++	const char *name;		/* for debug */
++	const char *ctrl_name;
++	const char *panel_name;
++
++	void *priv;
++
++	/* platform specific enable/disable */
++	int (*panel_enable)(struct omap_display *display);
++	void (*panel_disable)(struct omap_display *display);
++	int (*ctrl_enable)(struct omap_display *display);
++	void (*ctrl_disable)(struct omap_display *display);
++	int (*set_backlight)(struct omap_display *display,
++			int level);
++};
++
++struct device;
++
++/* Board specific data */
++struct omap_dss_platform_data {
++	unsigned (*get_last_off_on_transaction_id)(struct device *dev);
++	int num_displays;
++	struct omap_display_data *displays[];
++};
++
++struct omap_ctrl {
++	struct module *owner;
++
++	const char *name;
++
++	int (*init)(struct omap_display *display);
++	void (*cleanup)(struct omap_display *display);
++	int (*enable)(struct omap_display *display);
++	void (*disable)(struct omap_display *display);
++	int (*suspend)(struct omap_display *display);
++	int (*resume)(struct omap_display *display);
++	void (*setup_update)(struct omap_display *display,
++			     int x, int y, int w, int h);
++
++	int (*enable_te)(struct omap_display *display, int enable);
++
++	int (*rotate)(struct omap_display *display, int rotate);
++	int (*mirror)(struct omap_display *display, int enable);
++
++	int (*run_test)(struct omap_display *display, int test);
++
++	int pixel_size;
++
++	struct rfbi_timings timings;
++
++	void *priv;
++};
++
++struct omap_video_timings {
++	/* Unit: pixels */
++	u16 x_res;
++	/* Unit: pixels */
++	u16 y_res;
++	/* Unit: KHz */
++	u32 pixel_clock;
++	/* Unit: pixel clocks */
++	u16 hsw;	/* Horizontal synchronization pulse width */
++	/* Unit: pixel clocks */
++	u16 hfp;	/* Horizontal front porch */
++	/* Unit: pixel clocks */
++	u16 hbp;	/* Horizontal back porch */
++	/* Unit: line clocks */
++	u16 vsw;	/* Vertical synchronization pulse width */
++	/* Unit: line clocks */
++	u16 vfp;	/* Vertical front porch */
++	/* Unit: line clocks */
++	u16 vbp;	/* Vertical back porch */
++
++};
++
++struct omap_panel {
++	struct module *owner;
++
++	const char *name;
++
++	int (*init)(struct omap_display *display);
++	void (*cleanup)(struct omap_display *display);
++	int (*remove)(struct omap_display *display);
++	int (*enable)(struct omap_display *display);
++	void (*disable)(struct omap_display *display);
++	int (*suspend)(struct omap_display *display);
++	int (*resume)(struct omap_display *display);
++	int (*run_test)(struct omap_display *display, int test);
++
++	struct omap_video_timings timings;
++
++	int acbi;	/* ac-bias pin transitions per interrupt */
++	/* Unit: line clocks */
++	int acb;	/* ac-bias pin frequency */
++
++	enum omap_panel_config config;
++
++	int bpp;
++
++	void *priv;
++};
++
++/* XXX perhaps this should be removed */
++enum omap_dss_overlay_managers {
++	OMAP_DSS_OVL_MGR_LCD,
++	OMAP_DSS_OVL_MGR_TV,
++};
++
++struct omap_overlay_manager;
++
++struct omap_overlay_info {
++	int enabled;
++	u32 paddr;
++	void *vaddr;
++	int screen_width;
++	int pos_x;
++	int pos_y;
++	int width;
++	int height;
++	int out_width;	/* if 0, out_width == width */
++	int out_height;	/* if 0, out_height == height */
++	enum omap_color_mode color_mode;
++};
++
++enum omap_overlay_caps {
++	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
++};
++
++struct omap_overlay {
++
++	const char *name;
++	int id;
++	struct omap_overlay_manager *manager;
++	enum omap_color_mode supported_modes;
++	struct omap_overlay_info info;
++	enum omap_overlay_caps caps;
++
++	int (*set_manager)(struct omap_overlay *ovl,
++		struct omap_overlay_manager *mgr);
++	int (*unset_manager)(struct omap_overlay *ovl);
++
++	int (*setup_input)(struct omap_overlay *ovl,
++			u32 paddr, void *vaddr,
++			int screen_width,
++			int width, int height,
++			enum omap_color_mode color_mode);
++	int (*setup_output)(struct omap_overlay *ovl,
++			int pos_x, int pos_y,
++			int out_width, int out_height);
++	int (*enable)(struct omap_overlay *ovl, int enable);
++};
++
++enum omap_overlay_manager_caps {
++	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
++};
++
++struct omap_overlay_manager {
++
++	const char *name;
++	int id;
++	enum omap_overlay_manager_caps caps;
++	struct omap_display *display;
++	int num_overlays;
++	struct omap_overlay *overlays;
++	enum omap_display_type supported_displays;
++
++	int (*set_display)(struct omap_overlay_manager *mgr,
++		struct omap_display *display);
++	int (*unset_display)(struct omap_overlay_manager *mgr);
++
++	int (*apply)(struct omap_overlay_manager *mgr);
++};
++
++enum omap_display_caps {
++	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
++};
++
++enum omap_dss_update_mode {
++	OMAP_DSS_UPDATE_DISABLED = 0,
++	OMAP_DSS_UPDATE_AUTO,
++	OMAP_DSS_UPDATE_MANUAL,
++};
++
++enum omap_dss_display_state {
++	OMAP_DSS_DISPLAY_DISABLED = 0,
++	OMAP_DSS_DISPLAY_ACTIVE,
++	OMAP_DSS_DISPLAY_SUSPENDED,
++};
++
++struct omap_display {
++	/*atomic_t ref_count;*/
++	int ref_count;
++
++	enum omap_display_type type;
++	const char *name;
++
++	enum omap_display_caps caps;
++
++	struct omap_overlay_manager *manager;
++
++	enum omap_dss_display_state state;
++
++	struct omap_display_data hw_config;	/* board specific data */
++	struct omap_ctrl *ctrl;			/* static common data */
++	struct omap_panel *panel;		/* static common data */
++
++	int (*enable)(struct omap_display *display);
++	void (*disable)(struct omap_display *display);
++
++	int (*suspend)(struct omap_display *display);
++	int (*resume)(struct omap_display *display);
++
++	int (*check_timings)(struct omap_display *display,
++			struct omap_video_timings *timings);
++	void (*set_timings)(struct omap_display *display,
++			struct omap_video_timings *timings);
++	void (*get_timings)(struct omap_display *display,
++			struct omap_video_timings *timings);
++	int (*update)(struct omap_display *display,
++			       int x, int y, int w, int h);
++	int (*sync)(struct omap_display *display);
++
++	int (*set_update_mode)(struct omap_display *display,
++			enum omap_dss_update_mode);
++	enum omap_dss_update_mode (*get_update_mode)
++		(struct omap_display *display);
++
++	int (*enable_te)(struct omap_display *display, int enable);
++	int (*get_te)(struct omap_display *display);
++
++	int (*run_test)(struct omap_display *display, int test);
++};
++
++int omap_dss_get_num_displays(void);
++struct omap_display *omap_dss_get_display(int no);
++void omap_dss_put_display(struct omap_display *display);
++
++void omap_dss_register_ctrl(struct omap_ctrl *ctrl);
++void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl);
++
++void omap_dss_register_panel(struct omap_panel *panel);
++void omap_dss_unregister_panel(struct omap_panel *panel);
++
++int omap_dss_get_num_overlay_managers(void);
++struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
++
++int omap_dss_get_num_overlays(void);
++struct omap_overlay *omap_dss_get_overlay(int num);
++
++typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
++int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
++int omap_dispc_unregister_isr(omap_dispc_isr_t isr);
++
++#endif
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0001-Implement-downsampling-with-debugs.patch b/recipes/linux/linux-omap-2.6.28/0001-Implement-downsampling-with-debugs.patch
new file mode 100644
index 0000000000..d3608df9cb
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0001-Implement-downsampling-with-debugs.patch
@@ -0,0 +1,138 @@
+From 1ef94095e9399a9a387b7b457b48f6c5de7013d8 Mon Sep 17 00:00:00 2001
+From: Tuomas Kulve <tuomas.kulve@movial.com>
+Date: Fri, 31 Oct 2008 14:23:57 +0200
+Subject: [PATCH] Implement downsampling (with debugs).
+
+---
+ drivers/video/omap/dispc.c |   75 +++++++++++++++++++++++++++++++++++++-------
+ 1 files changed, 63 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index 68bc887..3640dbe 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -18,6 +18,8 @@
+  * with this program; if not, write to the Free Software Foundation, Inc.,
+  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+  */
++#define DEBUG
++#define VERBOSE_DEBUG
+ #include <linux/kernel.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/mm.h>
+@@ -545,6 +547,17 @@ static void write_firhv_reg(int plane, int reg, u32 value)
+ 	dispc_write_reg(base + reg * 8,	value);
+ }
+ 
++static void write_firv_reg(int plane, int reg, u32 value)
++{
++	u32 base;
++
++	if (plane == 1)
++		base = 0x1E0;
++	else
++		base = 0x1E0 + 0x20;
++	dispc_write_reg(base + reg * 4,	value);
++}
++
+ static void set_upsampling_coef_table(int plane)
+ {
+ 	const u32 coef[][2] = {
+@@ -565,6 +578,27 @@ static void set_upsampling_coef_table(int plane)
+ 	}
+ }
+ 
++static void set_downsampling_coef_table(int plane)
++{
++	const u32 coef[][3] = {
++                { 0x24382400, 0x24382400, 0x00000000 },
++                { 0x28371FFE, 0x28391F04, 0x000004FE },
++                { 0x2C361BFB, 0x2D381B08, 0x000008FB },
++                { 0x303516F9, 0x3237170C, 0x00000CF9 },
++                { 0x11343311, 0x123737F7, 0x0000F711 },
++                { 0x1635300C, 0x173732F9, 0x0000F90C },
++                { 0x1B362C08, 0x1B382DFB, 0x0000FB08 },
++                { 0x1F372804, 0x1F3928FE, 0x0000FE04 },
++	};
++	int i;
++
++	for (i = 0; i < 8; i++) {
++		write_firh_reg(plane, i, coef[i][0]);
++		write_firhv_reg(plane, i, coef[i][1]);
++		write_firv_reg(plane, i, coef[i][2]);
++	}
++}
++
+ static int omap_dispc_set_scale(int plane,
+ 				int orig_width, int orig_height,
+ 				int out_width, int out_height)
+@@ -592,25 +626,47 @@ static int omap_dispc_set_scale(int plane,
+ 		if (orig_height > out_height ||
+ 		    orig_width * 8 < out_width ||
+ 		    orig_height * 8 < out_height) {
++                        dev_dbg(dispc.fbdev->dev, 
++                                "Max upsampling is 8x, "
++                                "tried: %dx%d -> %dx%d\n",
++                                orig_width, orig_height,
++                                out_width, out_height);
+ 			enable_lcd_clocks(0);
+ 			return -EINVAL;
+ 		}
+ 		set_upsampling_coef_table(plane);
+ 	} else if (orig_width > out_width) {
+-		/* Downsampling not yet supported
+-		*/
+-
+-		enable_lcd_clocks(0);
+-		return -EINVAL;
++		/*
++		 * Downsampling.
++		 * Currently you can only scale both dimensions in one way.
++		 */
++		if (orig_height < out_height ||
++		    orig_width > out_width * 4||
++		    orig_height > out_height * 4) {
++                        dev_dbg(dispc.fbdev->dev, 
++                                "Max downsampling is 4x, "
++                                "tried: %dx%d -> %dx%d\n",
++                                orig_width, orig_height,
++                                out_width, out_height);
++			enable_lcd_clocks(0);
++			return -EINVAL;
++		}
++		set_downsampling_coef_table(plane);
+ 	}
+ 	if (!orig_width || orig_width == out_width)
+ 		fir_hinc = 0;
+ 	else
+-		fir_hinc = 1024 * orig_width / out_width;
++		fir_hinc = 1024 * (orig_width -1)/ (out_width -1);
+ 	if (!orig_height || orig_height == out_height)
+ 		fir_vinc = 0;
+ 	else
+-		fir_vinc = 1024 * orig_height / out_height;
++		fir_vinc = 1024 * (orig_height-1) / (out_height -1 );
++
++	dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d "
++		"orig_height %d fir_hinc  %d fir_vinc %d\n",
++		out_width, out_height, orig_width, orig_height,
++		fir_hinc, fir_vinc);
++
+ 	dispc.fir_hinc[plane] = fir_hinc;
+ 	dispc.fir_vinc[plane] = fir_vinc;
+ 
+@@ -619,11 +675,6 @@ static int omap_dispc_set_scale(int plane,
+ 		    ((fir_vinc & 4095) << 16) |
+ 		    (fir_hinc & 4095));
+ 
+-	dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d "
+-		"orig_height %d fir_hinc  %d fir_vinc %d\n",
+-		out_width, out_height, orig_width, orig_height,
+-		fir_hinc, fir_vinc);
+-
+ 	MOD_REG_FLD(vs_reg[plane],
+ 		    FLD_MASK(16, 11) | FLD_MASK(0, 11),
+ 		    ((out_height - 1) << 16) | (out_width - 1));
+-- 
+1.5.6.5
+
diff --git a/recipes/linux/linux-omap-2.6.28/0001-Removed-resolution-check-that-prevents-scaling-when.patch b/recipes/linux/linux-omap-2.6.28/0001-Removed-resolution-check-that-prevents-scaling-when.patch
new file mode 100644
index 0000000000..636203ef32
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0001-Removed-resolution-check-that-prevents-scaling-when.patch
@@ -0,0 +1,26 @@
+From 3227bd5c412e7eb0d4370b2834e71723f6b4be48 Mon Sep 17 00:00:00 2001
+From: Tuomas Kulve <tuomas.kulve@movial.fi>
+Date: Mon, 27 Oct 2008 18:55:59 +0200
+Subject: [PATCH] Removed resolution check that prevents scaling when output resolution doesn't match the original resolution.
+
+---
+ drivers/video/omap/dispc.c |    3 ---
+ 1 files changed, 0 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index 0f0b2e5..1df0c1e 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -579,9 +579,6 @@ static int omap_dispc_set_scale(int plane,
+ 	if ((unsigned)plane > OMAPFB_PLANE_NUM)
+ 		return -ENODEV;
+ 
+-	if (out_width != orig_width || out_height != orig_height)
+-		return -EINVAL;
+-
+ 	enable_lcd_clocks(1);
+ 	if (orig_width < out_width) {
+ 		/*
+-- 
+1.5.6.5
+
diff --git a/recipes/linux/linux-omap-2.6.28/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch b/recipes/linux/linux-omap-2.6.28/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch
new file mode 100644
index 0000000000..d590f8ffb9
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch
@@ -0,0 +1,146 @@
+From f8f10f496bce396416d7156da876222c6ce8c341 Mon Sep 17 00:00:00 2001
+From: Steven Kipisz <skipisz@beagleboard.org>
+Date: Wed, 9 Jan 2009 12:01:11 -0600
+Subject: [PATCH-USB] Omap3 beagleboard: add support for EHCI in revision C1 boards
+
+Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   10 +---------
+ arch/arm/mach-omap2/usb-ehci.c          |    4 +---
+ drivers/usb/host/ehci-omap.c            |   26 ++++++++++++++++++++++++++
+ 3 files changed, 28 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index fe97bab..de81153 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -140,15 +140,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
+ 	 * power switch and overcurrent detect
+ 	 */
+ 
+-	gpio_request(gpio + 1, "EHCI_nOC");
+-	gpio_direction_input(gpio + 1);
+-
+-	/* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
+-	gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
+-	gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1);
+-
+-	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+-	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
++        /* TODO: This needs to be modified to not rely on u-boot */
+ 
+ 	return 0;
+ }
+diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
+index 489439d..2c6305b 100644
+--- a/arch/arm/mach-omap2/usb-ehci.c
++++ b/arch/arm/mach-omap2/usb-ehci.c
+@@ -152,9 +152,7 @@ static void setup_ehci_io_mux(void)
+ void __init usb_ehci_init(void)
+ {
+ #if     defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
+-	/* Setup Pin IO MUX for EHCI */
+-	if (cpu_is_omap34xx())
+-		setup_ehci_io_mux();
++	/* TODO: Setup Pin IO MUX for EHCI - moved this temporarily to U-boot */
+ 
+ 	if (platform_device_register(&ehci_device) < 0) {
+ 		printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
+
+diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
+index 1b3266c..8472996 100644
+--- a/drivers/usb/host/ehci-omap.c
++++ b/drivers/usb/host/ehci-omap.c
+@@ -48,16 +48,26 @@
+  *		to get the PHY state machine in working state
+  */
+ #define EXTERNAL_PHY_RESET
++#ifdef CONFIG_MACH_OMAP3_BEAGLE
++#define	EXT_PHY_RESET_GPIO_PORT2	(147)
++#else
+ #define	EXT_PHY_RESET_GPIO_PORT1	(57)
+ #define	EXT_PHY_RESET_GPIO_PORT2	(61)
++#endif
+ #define	EXT_PHY_RESET_DELAY		(10)
+ 
++#define PHY_STP_PULLUP_ENABLE           (0x10)
++#define PHY_STP_PULLUP_DISABLE          (0x90)
++
++
+ /* ISSUE2:
+  * USBHOST supports External charge pump PHYs only
+  * Use the VBUS from Port1 to power VBUS of Port2 externally
+  * So use Port2 as the working ULPI port
+  */
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ #define VBUS_INTERNAL_CHARGEPUMP_HACK
++#endif
+ 
+ #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
+ 
+@@ -225,14 +235,43 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 
+ #ifdef EXTERNAL_PHY_RESET
+ 	/* Refer: ISSUE1 */
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT1, "USB1 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT1, 0);
++#endif
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT2, "USB2 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT2, 0);
++	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 0);
+ 	/* Hold the PHY in RESET for enough time till DIR is high */
+ 	udelay(EXT_PHY_RESET_DELAY);
+ #endif
+ 
++        /*
++         * The PHY register 0x7 - Interface Control register is
++         * configured to disable the integrated STP pull-up resistor
++         * used for interface protection.
++	 *
++	 * May not need to be here.
++         */
++        omap_writel((0x7 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* interface reg */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (PHY_STP_PULLUP_DISABLE),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
++        /* Force PHY to HS */
++        omap_writel((0x4 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* function ctrl */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (0x40),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
+ 	/* Configure TLL for 60Mhz clk for ULPI */
+ 	ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
+ 	if (IS_ERR(ehci_clocks->usbtll_fck_clk))
+@@ -307,7 +346,9 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 	 * Hold the PHY in RESET for enough time till PHY is settled and ready
+ 	 */
+ 	udelay(EXT_PHY_RESET_DELAY);
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT1, 1);
++#endif
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 1);
+ #endif
+ 
+@@ -393,7 +434,9 @@ static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 
+ 
+ #ifdef EXTERNAL_PHY_RESET
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT1);
++#endif
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT2);
+ #endif
+
+--
+1.6.0.4.790.gaa14a 
diff --git a/recipes/linux/linux-omap-2.6.28/0001-board-omap3beagle-set-i2c-3-to-100kHz.patch b/recipes/linux/linux-omap-2.6.28/0001-board-omap3beagle-set-i2c-3-to-100kHz.patch
new file mode 100644
index 0000000000..d4a9716349
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0001-board-omap3beagle-set-i2c-3-to-100kHz.patch
@@ -0,0 +1,30 @@
+From 8364891aa9a99eac26e6069840c00489764d963f Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@beagleboard.org>
+Date: Thu, 15 Jan 2009 20:11:07 +0100
+Subject: [PATCH] board-omap3beagle: set i2c-3 to 100kHz
+
+Changing it do 100kHz is needed to make more devices works properly. Controlling the TI DLP Pico projector[1] doesn't work properly at 400kHz, 100kHz and lower work fine. EDID readout is unaffected by this change.
+
+[1] http://focus.ti.com/dlpdmd/docs/dlpdiscovery.tsp?sectionId=60&tabId=2234
+
+Signed-off-by: Koen Kooi <koen@beagleboard.org>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index fe97bab..f279404 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -227,7 +227,7 @@ static int __init omap3_beagle_i2c_init(void)
+ #ifdef CONFIG_I2C2_OMAP_BEAGLE
+ 	omap_register_i2c_bus(2, 400, NULL, 0);
+ #endif
+-	omap_register_i2c_bus(3, 400, NULL, 0);
++	omap_register_i2c_bus(3, 100, NULL, 0);
+ 	return 0;
+ }
+ 
+-- 
+1.5.6.5
+
diff --git a/recipes/linux/linux-omap-2.6.28/0002-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch b/recipes/linux/linux-omap-2.6.28/0002-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch
new file mode 100644
index 0000000000..0d9dba3311
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0002-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch
@@ -0,0 +1,3809 @@
+From 2167c1818af2d302d3934185b534ea4006c407c7 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 7 Jan 2009 14:30:18 +0200
+Subject: [PATCH] DSS: OMAPFB: fb driver for new display subsystem
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/plat-omap/Makefile              |    2 +-
+ arch/arm/plat-omap/fb-vram.c             |  646 +++++++++++++
+ arch/arm/plat-omap/fb.c                  |   22 +
+ arch/arm/plat-omap/include/mach/omapfb.h |   14 +
+ drivers/video/Kconfig                    |    1 +
+ drivers/video/Makefile                   |    1 +
+ drivers/video/omap/Kconfig               |    5 +-
+ drivers/video/omap2/Kconfig              |   42 +
+ drivers/video/omap2/Makefile             |    2 +
+ drivers/video/omap2/omapfb-ioctl.c       |  464 ++++++++++
+ drivers/video/omap2/omapfb-main.c        | 1441 ++++++++++++++++++++++++++++++
+ drivers/video/omap2/omapfb-sysfs.c       |  901 +++++++++++++++++++
+ drivers/video/omap2/omapfb.h             |  115 +++
+ 13 files changed, 3653 insertions(+), 3 deletions(-)
+ create mode 100644 arch/arm/plat-omap/fb-vram.c
+ create mode 100644 drivers/video/omap2/Kconfig
+ create mode 100644 drivers/video/omap2/Makefile
+ create mode 100644 drivers/video/omap2/omapfb-ioctl.c
+ create mode 100644 drivers/video/omap2/omapfb-main.c
+ create mode 100644 drivers/video/omap2/omapfb-sysfs.c
+ create mode 100644 drivers/video/omap2/omapfb.h
+
+diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
+index 2740497..7d602a6 100644
+--- a/arch/arm/plat-omap/Makefile
++++ b/arch/arm/plat-omap/Makefile
+@@ -4,7 +4,7 @@
+ 
+ # Common support
+ obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
+-	 usb.o fb.o io.o
++	 usb.o fb.o fb-vram.o io.o
+ obj-m :=
+ obj-n :=
+ obj-  :=
+diff --git a/arch/arm/plat-omap/fb-vram.c b/arch/arm/plat-omap/fb-vram.c
+new file mode 100644
+index 0000000..2994f8f
+--- /dev/null
++++ b/arch/arm/plat-omap/fb-vram.c
+@@ -0,0 +1,646 @@
++/*
++ * linux/arch/arm/plat-omap/fb-vram.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++//#define DEBUG
++
++#include <linux/vmalloc.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++#include <linux/dma-mapping.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/bootmem.h>
++
++#include <asm/setup.h>
++
++#include <mach/sram.h>
++#include <mach/omapfb.h>
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define OMAP2_SRAM_START		0x40200000
++/* Maximum size, in reality this is smaller if SRAM is partially locked. */
++#define OMAP2_SRAM_SIZE			0xa0000		/* 640k */
++
++#define REG_MAP_SIZE(_page_cnt)						\
++	((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
++#define REG_MAP_PTR(_rg, _page_nr)					\
++	(((_rg)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
++#define REG_MAP_MASK(_page_nr)						\
++	(1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
++
++#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
++
++/* postponed regions are used to temporarily store region information at boot
++ * time when we cannot yet allocate the region list */
++#define MAX_POSTPONED_REGIONS 10
++
++static int postponed_cnt __initdata;
++static struct {
++	unsigned long paddr;
++	size_t size;
++} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
++
++struct vram_alloc {
++	struct list_head list;
++	unsigned long paddr;
++	unsigned pages;
++};
++
++struct vram_region {
++	struct list_head list;
++	struct list_head alloc_list;
++	unsigned long	paddr;
++	void		*vaddr;
++	unsigned	pages;
++	unsigned	dma_alloced:1;
++};
++
++static DEFINE_MUTEX(region_mutex);
++static LIST_HEAD(region_list);
++
++static inline int region_mem_type(unsigned long paddr)
++{
++	if (paddr >= OMAP2_SRAM_START &&
++	    paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
++		return OMAPFB_MEMTYPE_SRAM;
++	else
++		return OMAPFB_MEMTYPE_SDRAM;
++}
++
++static struct vram_region *omap_vram_create_region(unsigned long paddr,
++		void *vaddr, unsigned pages)
++{
++	struct vram_region *rm;
++
++	rm = kzalloc(sizeof(*rm), GFP_KERNEL);
++
++	if (rm) {
++		INIT_LIST_HEAD(&rm->alloc_list);
++		rm->paddr = paddr;
++		rm->vaddr = vaddr;
++		rm->pages = pages;
++	}
++
++	return rm;
++}
++
++static void omap_vram_free_region(struct vram_region *vr)
++{
++	list_del(&vr->list);
++	kfree(vr);
++}
++
++static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr,
++		unsigned long paddr, unsigned pages)
++{
++	struct vram_alloc *va;
++	struct vram_alloc *new;
++
++	new = kzalloc(sizeof(*va), GFP_KERNEL);
++
++	if (!new)
++		return NULL;
++
++	new->paddr = paddr;
++	new->pages = pages;
++
++	list_for_each_entry(va, &vr->alloc_list, list) {
++		if (va->paddr > new->paddr)
++			break;
++	}
++
++	list_add_tail(&new->list, &va->list);
++
++	return new;
++}
++
++static void omap_vram_free_allocation(struct vram_alloc *va)
++{
++	list_del(&va->list);
++	kfree(va);
++}
++
++static __init int omap_vram_add_region_postponed(unsigned long paddr, size_t size)
++{
++	if (postponed_cnt == MAX_POSTPONED_REGIONS)
++		return -ENOMEM;
++
++	postponed_regions[postponed_cnt].paddr = paddr;
++	postponed_regions[postponed_cnt].size = size;
++
++	++postponed_cnt;
++
++	return 0;
++}
++
++/* add/remove_region can be exported if there's need to add/remove regions
++ * runtime */
++static int omap_vram_add_region(unsigned long paddr, size_t size)
++{
++	struct vram_region *rm;
++	void *vaddr;
++	unsigned pages;
++
++	DBG("adding region paddr %08lx size %d\n",
++			paddr, size);
++
++	size &= PAGE_MASK;
++	pages = size >> PAGE_SHIFT;
++
++	vaddr = ioremap_wc(paddr, size);
++	if (vaddr == NULL)
++		return -ENOMEM;
++
++	rm = omap_vram_create_region(paddr, vaddr, pages);
++	if (rm == NULL) {
++		iounmap(vaddr);
++		return -ENOMEM;
++	}
++
++	list_add(&rm->list, &region_list);
++
++	return 0;
++}
++
++#if 0
++int omap_vram_remove_region(unsigned long paddr)
++{
++	struct region *rm;
++	unsigned i;
++
++	DBG("remove region paddr %08lx\n", paddr);
++	list_for_each_entry(rm, &region_list, list)
++		if (rm->paddr != paddr)
++			continue;
++
++	if (rm->paddr != paddr)
++		return -EINVAL;
++
++	for (i = 0; i < rm->page_cnt; i++)
++		if (region_page_reserved(rm, i))
++			return -EBUSY;
++
++	iounmap(rm->vaddr);
++
++	list_del(&rm->list);
++
++	kfree(rm);
++
++	return 0;
++}
++#endif
++
++int omap_vram_free(unsigned long paddr, void *vaddr, size_t size)
++{
++	struct vram_region *rm;
++	struct vram_alloc *alloc;
++	unsigned start, end;
++
++	DBG("free mem paddr %08lx vaddr %p size %d\n",
++			paddr, vaddr, size);
++
++	size = PAGE_ALIGN(size);
++
++	mutex_lock(&region_mutex);
++
++	list_for_each_entry(rm, &region_list, list) {
++		list_for_each_entry(alloc, &rm->alloc_list, list) {
++			start = alloc->paddr;
++			end = alloc->paddr + (alloc->pages >> PAGE_SHIFT);
++
++			if (start >= paddr && end < paddr + size)
++				goto found;
++		}
++	}
++
++	mutex_unlock(&region_mutex);
++	return -EINVAL;
++
++found:
++	if (rm->dma_alloced) {
++		DBG("freeing dma-alloced\n");
++		dma_free_writecombine(NULL, size, vaddr, paddr);
++		omap_vram_free_allocation(alloc);
++		omap_vram_free_region(rm);
++	} else {
++		omap_vram_free_allocation(alloc);
++	}
++
++	mutex_unlock(&region_mutex);
++	return 0;
++}
++EXPORT_SYMBOL(omap_vram_free);
++
++#if 0
++void *omap_vram_reserve(unsigned long paddr, size_t size)
++{
++
++	struct region *rm;
++	unsigned start_page;
++	unsigned end_page;
++	unsigned i;
++	void *vaddr;
++
++	size = PAGE_ALIGN(size);
++
++	rm = region_find_region(paddr, size);
++
++	DBG("reserve mem paddr %08lx size %d\n",
++			paddr, size);
++
++	BUG_ON(rm == NULL);
++
++	start_page = (paddr - rm->paddr) >> PAGE_SHIFT;
++	end_page = start_page + (size >> PAGE_SHIFT);
++	for (i = start_page; i < end_page; i++)
++		region_reserve_page(rm, i);
++
++	vaddr = rm->vaddr + (start_page << PAGE_SHIFT);
++
++	return vaddr;
++}
++EXPORT_SYMBOL(omap_vram_reserve);
++#endif
++static void *_omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
++{
++	struct vram_region *rm;
++	struct vram_alloc *alloc;
++	void *vaddr;
++
++	list_for_each_entry(rm, &region_list, list) {
++		unsigned long start, end;
++
++		DBG("checking region %lx %d\n", rm->paddr, rm->pages);
++
++		if (region_mem_type(rm->paddr) != mtype)
++			continue;
++
++		start = rm->paddr;
++
++		list_for_each_entry(alloc, &rm->alloc_list, list) {
++			end = alloc->paddr;
++
++			if (end - start >= pages << PAGE_SHIFT)
++				goto found;
++
++			start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
++		}
++
++		end = rm->paddr + (rm->pages << PAGE_SHIFT);
++found:
++		if (end - start < pages << PAGE_SHIFT)
++			continue;
++
++		DBG("FOUND %lx, end %lx\n", start, end);
++
++		if (omap_vram_create_allocation(rm, start, pages) == NULL)
++			return NULL;
++
++		*paddr = start;
++		vaddr = rm->vaddr + (start - rm->paddr);
++
++		return vaddr;
++	}
++
++	return NULL;
++}
++
++static void *_omap_vram_alloc_dma(unsigned pages, unsigned long *paddr)
++{
++	struct vram_region *rm;
++	void *vaddr;
++
++	vaddr = dma_alloc_writecombine(NULL, pages << PAGE_SHIFT,
++			(dma_addr_t *)paddr, GFP_KERNEL);
++
++	if (vaddr == NULL)
++		return NULL;
++
++	rm = omap_vram_create_region(*paddr, vaddr, pages);
++	if (rm == NULL) {
++		dma_free_writecombine(NULL, pages << PAGE_SHIFT, vaddr,
++				(dma_addr_t)*paddr);
++		return NULL;
++	}
++
++	rm->dma_alloced = 1;
++
++	if (omap_vram_create_allocation(rm, *paddr, pages) == NULL) {
++		dma_free_writecombine(NULL, pages << PAGE_SHIFT, vaddr,
++				(dma_addr_t)*paddr);
++		kfree(rm);
++		return NULL;
++	}
++
++	list_add(&rm->list, &region_list);
++
++	return vaddr;
++}
++
++void *omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
++{
++	void *vaddr;
++	unsigned pages;
++
++	BUG_ON(mtype > OMAPFB_MEMTYPE_MAX || !size);
++
++	DBG("alloc mem type %d size %d\n", mtype, size);
++
++	size = PAGE_ALIGN(size);
++	pages = size >> PAGE_SHIFT;
++
++	mutex_lock(&region_mutex);
++
++	vaddr = _omap_vram_alloc(mtype, pages, paddr);
++
++	if (vaddr == NULL && mtype == OMAPFB_MEMTYPE_SDRAM) {
++		DBG("fallback to dma_alloc\n");
++
++		vaddr = _omap_vram_alloc_dma(pages, paddr);
++	}
++
++	mutex_unlock(&region_mutex);
++
++	return vaddr;
++}
++EXPORT_SYMBOL(omap_vram_alloc);
++
++#ifdef CONFIG_PROC_FS
++static void *r_next(struct seq_file *m, void *v, loff_t *pos)
++{
++	struct list_head *l = v;
++
++	(*pos)++;
++
++	if (list_is_last(l, &region_list))
++		return 0;
++
++	return l->next;
++}
++
++static void *r_start(struct seq_file *m, loff_t *pos)
++{
++	loff_t p = *pos;
++	struct list_head *l = &region_list;
++
++	mutex_lock(&region_mutex);
++
++	do {
++		l = l->next;
++		if (l == &region_list)
++			return NULL;
++	} while (p--);
++
++	return l;
++}
++
++static void r_stop(struct seq_file *m, void *v)
++{
++	mutex_unlock(&region_mutex);
++}
++
++static int r_show(struct seq_file *m, void *v)
++{
++	struct vram_region *vr;
++	struct vram_alloc *va;
++	unsigned size;
++
++	vr = list_entry(v, struct vram_region, list);
++
++	size = vr->pages << PAGE_SHIFT;
++	seq_printf(m, "%08lx-%08lx v:%p-%p (%d bytes) %s\n",
++			vr->paddr, vr->paddr + size,
++			vr->vaddr, vr->vaddr + size,
++			size,
++			vr->dma_alloced ? "dma_alloc" : "");
++
++	list_for_each_entry(va, &vr->alloc_list, list) {
++		size = va->pages << PAGE_SHIFT;
++		seq_printf(m, "    %08lx-%08lx (%d bytes)\n",
++				va->paddr, va->paddr + size,
++				size);
++	}
++
++
++
++	return 0;
++}
++
++static const struct seq_operations resource_op = {
++	.start	= r_start,
++	.next	= r_next,
++	.stop	= r_stop,
++	.show	= r_show,
++};
++
++static int vram_open(struct inode *inode, struct file *file)
++{
++	return seq_open(file, &resource_op);
++}
++
++static const struct file_operations proc_vram_operations = {
++	.open		= vram_open,
++	.read		= seq_read,
++	.llseek		= seq_lseek,
++	.release	= seq_release,
++};
++
++static int __init omap_vram_create_proc(void)
++{
++	proc_create("omap-vram", 0, NULL, &proc_vram_operations);
++
++	return 0;
++}
++#endif
++
++static __init int omap_vram_init(void)
++{
++	int i, r;
++
++	for (i = 0; i < postponed_cnt; i++)
++		omap_vram_add_region(postponed_regions[i].paddr,
++				postponed_regions[i].size);
++
++#ifdef CONFIG_PROC_FS
++	r = omap_vram_create_proc();
++	if (r)
++		return -ENOMEM;
++#endif
++
++	return 0;
++}
++
++arch_initcall(omap_vram_init);
++
++/* boottime vram alloc stuff */
++static u32 omapfb_sram_vram_start __initdata;
++static u32 omapfb_sram_vram_size __initdata;
++
++static u32 omapfb_sdram_vram_start __initdata;
++static u32 omapfb_sdram_vram_size __initdata;
++
++static u32 omapfb_def_sdram_vram_size __initdata;
++
++static void __init omapfb_early_vram(char **p)
++{
++	unsigned long size;
++	size  = memparse(*p, p);
++	omapfb_def_sdram_vram_size = size;
++}
++__early_param("vram=", omapfb_early_vram);
++
++/*
++ * Called from map_io. We need to call to this early enough so that we
++ * can reserve the fixed SDRAM regions before VM could get hold of them.
++ */
++void __init omapfb_reserve_sdram(void)
++{
++	struct bootmem_data	*bdata;
++	unsigned long		sdram_start, sdram_size;
++	unsigned long		reserved;
++	u32 paddr;
++	u32 size;
++
++	bdata = NODE_DATA(0)->bdata;
++	sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
++	sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
++	reserved = 0;
++
++	/* cmdline arg overrides the board file definition */
++	if (omapfb_def_sdram_vram_size) {
++		size = omapfb_def_sdram_vram_size;
++		paddr = 0;
++	} else {
++		size = omapfb_sdram_vram_size;
++		paddr = omapfb_sdram_vram_start;
++	}
++
++	if (size) {
++		if (paddr) {
++			if (paddr < sdram_start ||
++					paddr + size > sdram_start + sdram_size) {
++				printk(KERN_ERR "Illegal SDRAM region for VRAM\n");
++				return;
++			}
++
++			reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
++		} else {
++			if (size > sdram_size) {
++				printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
++				return;
++			}
++
++			paddr = virt_to_phys(alloc_bootmem(size));
++		}
++
++		reserved += size;
++		omap_vram_add_region_postponed(paddr, size);
++	}
++
++	if (reserved)
++		pr_info("Reserving %lu bytes SDRAM for VRAM\n", reserved);
++}
++
++/*
++ * Called at sram init time, before anything is pushed to the SRAM stack.
++ * Because of the stack scheme, we will allocate everything from the
++ * start of the lowest address region to the end of SRAM. This will also
++ * include padding for page alignment and possible holes between regions.
++ *
++ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
++ * this point, since the driver built as a module would have problem with
++ * freeing / reallocating the regions.
++ */
++unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
++				  unsigned long sram_vstart,
++				  unsigned long sram_size,
++				  unsigned long pstart_avail,
++				  unsigned long size_avail)
++{
++	unsigned long			pend_avail;
++	unsigned long			reserved;
++	u32 paddr;
++	u32 size;
++
++	paddr = omapfb_sram_vram_start;
++	size = omapfb_sram_vram_size;
++
++	reserved = 0;
++	pend_avail = pstart_avail + size_avail;
++
++
++	if (!paddr) {
++		/* Dynamic allocation */
++		if ((size_avail & PAGE_MASK) < size) {
++			printk(KERN_ERR "Not enough SRAM for VRAM\n");
++			return 0;
++		}
++		size_avail = (size_avail - size) & PAGE_MASK;
++		paddr = pstart_avail + size_avail;
++	}
++
++	if (paddr < sram_pstart ||
++			paddr + size > sram_pstart + sram_size) {
++		printk(KERN_ERR "Illegal SRAM region for VRAM\n");
++		return 0;
++	}
++
++	/* Reserve everything above the start of the region. */
++	if (pend_avail - paddr > reserved)
++		reserved = pend_avail - paddr;
++	size_avail = pend_avail - reserved - pstart_avail;
++
++	/*
++	 * We have a kernel mapping for this already, so the
++	 * driver won't have to make one.
++	 */
++	/* XXX do we need the vaddr? */
++	/* rg.vaddr = (void *)(sram_vstart + paddr - sram_pstart); */
++
++	omap_vram_add_region_postponed(paddr, size);
++
++	if (reserved)
++		pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
++
++	return reserved;
++}
++
++void __init omap2_set_sdram_vram(u32 size, u32 start)
++{
++	omapfb_sdram_vram_start = start;
++	omapfb_sdram_vram_size = size;
++}
++
++void __init omap2_set_sram_vram(u32 size, u32 start)
++{
++	omapfb_sram_vram_start = start;
++	omapfb_sram_vram_size = size;
++}
++
++#endif
++
+diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
+index 3746222..ee2cc6f 100644
+--- a/arch/arm/plat-omap/fb.c
++++ b/arch/arm/plat-omap/fb.c
+@@ -327,6 +327,28 @@ static inline int omap_init_fb(void)
+ 
+ arch_initcall(omap_init_fb);
+ 
++#elif defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
++
++static u64 omap_fb_dma_mask = ~(u32)0;
++
++static struct platform_device omap_fb_device = {
++	.name		= "omapfb",
++	.id		= -1,
++	.dev = {
++		.dma_mask		= &omap_fb_dma_mask,
++		.coherent_dma_mask	= ~(u32)0,
++		.platform_data		= NULL,
++	},
++	.num_resources = 0,
++};
++
++static inline int omap_init_fb(void)
++{
++	return platform_device_register(&omap_fb_device);
++}
++
++arch_initcall(omap_init_fb);
++
+ #else
+ 
+ void omapfb_reserve_sdram(void) {}
+diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
+index b226bdf..0800f92 100644
+--- a/arch/arm/plat-omap/include/mach/omapfb.h
++++ b/arch/arm/plat-omap/include/mach/omapfb.h
+@@ -90,6 +90,13 @@ enum omapfb_color_format {
+ 	OMAPFB_COLOR_CLUT_1BPP,
+ 	OMAPFB_COLOR_RGB444,
+ 	OMAPFB_COLOR_YUY422,
++
++	OMAPFB_COLOR_ARGB16,
++	OMAPFB_COLOR_RGB24U,	/* RGB24, 32-bit container */
++	OMAPFB_COLOR_RGB24P,	/* RGB24, 24-bit container */
++	OMAPFB_COLOR_ARGB32,
++	OMAPFB_COLOR_RGBA32,
++	OMAPFB_COLOR_RGBX32,
+ };
+ 
+ struct omapfb_update_window {
+@@ -393,6 +400,13 @@ extern int  omapfb_update_window_async(struct fb_info *fbi,
+ /* in arch/arm/plat-omap/fb.c */
+ extern void omapfb_set_ctrl_platform_data(void *pdata);
+ 
++/* in arch/arm/plat-omap/fb-vram */
++int omap_vram_free(unsigned long paddr, void *vaddr, size_t size);
++void *omap_vram_reserve(unsigned long paddr, size_t size);
++void *omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
++extern void omap2_set_sdram_vram(u32 size, u32 start);
++extern void omap2_set_sram_vram(u32 size, u32 start);
++
+ #endif /* __KERNEL__ */
+ 
+ #endif /* __OMAPFB_H */
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index 3f3ce13..689a3b1 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -2116,6 +2116,7 @@ config FB_PRE_INIT_FB
+ 	  the bootloader.
+ 
+ source "drivers/video/omap/Kconfig"
++source "drivers/video/omap2/Kconfig"
+ 
+ source "drivers/video/backlight/Kconfig"
+ source "drivers/video/display/Kconfig"
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index e39e33e..3d9d50e 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_SM501)            += sm501fb.o
+ obj-$(CONFIG_FB_XILINX)           += xilinxfb.o
+ obj-$(CONFIG_FB_SH_MOBILE_LCDC)	  += sh_mobile_lcdcfb.o
+ obj-$(CONFIG_FB_OMAP)             += omap/
++obj-$(CONFIG_OMAP2_DSS)           += omap2/
+ obj-$(CONFIG_XEN_FBDEV_FRONTEND)  += xen-fbfront.o
+ obj-$(CONFIG_FB_CARMINE)          += carminefb.o
+ obj-$(CONFIG_FB_MB862XX)	  += mb862xx/
+diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
+index c355b59..541fab3 100644
+--- a/drivers/video/omap/Kconfig
++++ b/drivers/video/omap/Kconfig
+@@ -1,6 +1,7 @@
+ config FB_OMAP
+ 	tristate "OMAP frame buffer support (EXPERIMENTAL)"
+-	depends on FB && ARCH_OMAP
++	depends on FB && ARCH_OMAP && (OMAP2_DSS = "n")
++
+ 	select FB_CFB_FILLRECT
+ 	select FB_CFB_COPYAREA
+ 	select FB_CFB_IMAGEBLIT
+@@ -80,7 +81,7 @@ config FB_OMAP_BOOTLOADER_INIT
+ 
+ config FB_OMAP_CONSISTENT_DMA_SIZE
+ 	int "Consistent DMA memory size (MB)"
+-	depends on FB_OMAP
++	depends on FB && ARCH_OMAP
+ 	range 1 14
+ 	default 2
+ 	help
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+new file mode 100644
+index 0000000..8be51a3
+--- /dev/null
++++ b/drivers/video/omap2/Kconfig
+@@ -0,0 +1,42 @@
++config FB_OMAP2
++        tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)"
++        depends on FB && OMAP2_DSS
++
++        select FB_CFB_FILLRECT
++        select FB_CFB_COPYAREA
++        select FB_CFB_IMAGEBLIT
++        help
++          Frame buffer driver for OMAP2/3 based boards.
++
++config FB_OMAP2_DEBUG
++	bool "Debug support for OMAP2/3 FB"
++	default y
++	depends on FB_OMAP2
++	help
++	  Support for debug output. You have to enable the actual printing
++	  with debug module parameter.
++
++config FB_OMAP2_FORCE_AUTO_UPDATE
++	bool "Force main display to automatic update mode"
++	depends on FB_OMAP2
++	help
++	  Forces main display to automatic update mode (if possible),
++	  and also enables tearsync (if possible). By default
++	  displays that support manual update are started in manual
++	  update mode.
++
++config FB_OMAP2_NUM_FBS
++	int "Number of framebuffers"
++	range 1 10
++	default 3
++	depends on FB_OMAP2
++	help
++	  Select the number of framebuffers created. OMAP2/3 has 3 overlays
++	  so normally this would be 3.
++
++menu "OMAP2/3 Display Device Drivers"
++        depends on OMAP2_DSS
++
++
++endmenu
++
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+new file mode 100644
+index 0000000..51c2e00
+--- /dev/null
++++ b/drivers/video/omap2/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_FB_OMAP2) += omapfb.o
++omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
+diff --git a/drivers/video/omap2/omapfb-ioctl.c b/drivers/video/omap2/omapfb-ioctl.c
+new file mode 100644
+index 0000000..1f0f044
+--- /dev/null
++++ b/drivers/video/omap2/omapfb-ioctl.c
+@@ -0,0 +1,464 @@
++/*
++ * linux/drivers/video/omap2/omapfb-ioctl.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/fb.h>
++#include <linux/device.h>
++#include <linux/uaccess.h>
++#include <linux/platform_device.h>
++#include <linux/mm.h>
++
++#include <mach/display.h>
++#include <mach/omapfb.h>
++
++#include "omapfb.h"
++
++static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	struct omap_overlay *ovl;
++	int r = 0;
++
++	DBG("omapfb_setup_plane\n");
++
++	omapfb_lock(fbdev);
++
++	if (ofbi->num_overlays != 1) {
++		r = -EINVAL;
++		goto out;
++	}
++
++	/* XXX uses only the first overlay */
++	ovl = ofbi->overlays[0];
++
++	if (pi->enabled && !ofbi->region.size) {
++		/*
++		 * This plane's memory was freed, can't enable it
++		 * until it's reallocated.
++		 */
++		r = -EINVAL;
++		goto out;
++	}
++
++	if (pi->enabled) {
++		r = omapfb_setup_overlay(fbi, ovl, pi->pos_x, pi->pos_y,
++				pi->out_width, pi->out_height);
++		if (r)
++			goto out;
++	}
++
++	r = omapfb_setup_overlay(fbi, ovl, pi->pos_x, pi->pos_y,
++			pi->out_width, pi->out_height);
++	if (r)
++		goto out;
++
++	ovl->enable(ovl, pi->enabled);
++
++	if (ovl->manager)
++		ovl->manager->apply(ovl->manager);
++
++	if (display) {
++		if (display->sync)
++			display->sync(display);
++
++		if (display->update)
++			display->update(display, 0, 0,
++					display->panel->timings.x_res,
++					display->panel->timings.y_res);
++	}
++
++out:
++	omapfb_unlock(fbdev);
++	if (r)
++		dev_err(fbdev->dev, "setup_plane failed\n");
++	return r;
++}
++
++static int omapfb_query_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++
++	omapfb_lock(fbdev);
++
++	if (ofbi->num_overlays != 1) {
++		memset(pi, 0, sizeof(*pi));
++	} else {
++		struct omap_overlay_info *ovli;
++		struct omap_overlay *ovl;
++
++		ovl = ofbi->overlays[0];
++		ovli = &ovl->info;
++
++		pi->pos_x = ovli->pos_x;
++		pi->pos_y = ovli->pos_y;
++		pi->enabled = ovli->enabled;
++		pi->channel_out = 0; /* xxx */
++		pi->mirror = 0;
++		pi->out_width = ovli->out_width;
++		pi->out_height = ovli->out_height;
++	}
++
++	omapfb_unlock(fbdev);
++
++	return 0;
++}
++
++static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omapfb_mem_region *rg;
++	struct omap_display *display = fb2display(fbi);
++	int r, i;
++	size_t size;
++
++	if (mi->type > OMAPFB_MEMTYPE_MAX)
++		return -EINVAL;
++
++	size = PAGE_ALIGN(mi->size);
++
++	rg = &ofbi->region;
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i]->info.enabled) {
++			r = -EBUSY;
++			goto out;
++		}
++	}
++
++	if (rg->size != size || rg->type != mi->type) {
++		struct fb_var_screeninfo new_var;
++		unsigned long old_size = rg->size;
++
++		if (display->sync)
++			display->sync(display);
++
++		r = omapfb_realloc_fbmem(fbdev, ofbi->id, size);
++		if (r)
++			goto out;
++
++		if (old_size != size) {
++			if (size) {
++				memcpy(&new_var, &fbi->var, sizeof(new_var));
++				r = check_fb_var(fbi, &new_var);
++				if (r < 0)
++					goto out;
++				memcpy(&fbi->var, &new_var, sizeof(fbi->var));
++				set_fb_fix(fbi);
++			} else {
++				/*
++				 * Set these explicitly to indicate that the
++				 * plane memory is dealloce'd, the other
++				 * screen parameters in var / fix are invalid.
++				 */
++				fbi->fix.smem_start = 0;
++				fbi->fix.smem_len = 0;
++			}
++		}
++	}
++
++	r = 0;
++out:
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omapfb_mem_region *rg;
++
++	rg = &ofbi->region;
++	memset(mi, 0, sizeof(*mi));
++
++	omapfb_lock(fbdev);
++	mi->size = rg->size;
++	mi->type = rg->type;
++	omapfb_unlock(fbdev);
++
++	return 0;
++}
++
++static int omapfb_update_window(struct fb_info *fbi,
++		u32 x, u32 y, u32 w, u32 h)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++
++	if (!display)
++		return 0;
++
++	if (w == 0 || h == 0)
++		return 0;
++
++	if (x + w > display->panel->timings.x_res ||
++			y + h > display->panel->timings.y_res)
++		return -EINVAL;
++
++	omapfb_lock(fbdev);
++	display->update(display, x, y, w, h);
++	omapfb_unlock(fbdev);
++
++	return 0;
++}
++
++static int omapfb_set_update_mode(struct fb_info *fbi,
++				   enum omapfb_update_mode mode)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	enum omap_dss_update_mode um;
++	int r;
++
++	if (!display || !display->set_update_mode)
++		return -EINVAL;
++
++	switch (mode) {
++	case OMAPFB_UPDATE_DISABLED:
++		um = OMAP_DSS_UPDATE_DISABLED;
++		break;
++
++	case OMAPFB_AUTO_UPDATE:
++		um = OMAP_DSS_UPDATE_AUTO;
++		break;
++
++	case OMAPFB_MANUAL_UPDATE:
++		um = OMAP_DSS_UPDATE_MANUAL;
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	omapfb_lock(fbdev);
++	r = display->set_update_mode(display, um);
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static int omapfb_get_update_mode(struct fb_info *fbi,
++		enum omapfb_update_mode *mode)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	enum omap_dss_update_mode m;
++
++	if (!display || !display->get_update_mode)
++		return -EINVAL;
++
++	omapfb_lock(fbdev);
++	m = display->get_update_mode(display);
++	omapfb_unlock(fbdev);
++
++	switch (m) {
++	case OMAP_DSS_UPDATE_DISABLED:
++		*mode = OMAPFB_UPDATE_DISABLED;
++		break;
++	case OMAP_DSS_UPDATE_AUTO:
++		*mode = OMAPFB_AUTO_UPDATE;
++		break;
++	case OMAP_DSS_UPDATE_MANUAL:
++		*mode = OMAPFB_MANUAL_UPDATE;
++		break;
++	default:
++		BUG();
++	}
++
++	return 0;
++}
++
++int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++
++	union {
++		struct omapfb_update_window_old	uwnd_o;
++		struct omapfb_update_window	uwnd;
++		struct omapfb_plane_info	plane_info;
++		struct omapfb_caps		caps;
++		struct omapfb_mem_info          mem_info;
++		enum omapfb_update_mode		update_mode;
++		int test_num;
++	} p;
++
++	int r = 0;
++
++	DBG("ioctl %x (%d)\n", cmd, cmd & 0xff);
++
++	switch (cmd) {
++	case OMAPFB_SYNC_GFX:
++		if (!display || !display->sync) {
++			r = -EINVAL;
++			break;
++		}
++
++		omapfb_lock(fbdev);
++		r = display->sync(display);
++		omapfb_unlock(fbdev);
++		break;
++
++	case OMAPFB_UPDATE_WINDOW_OLD:
++		if (!display || !display->update) {
++			r = -EINVAL;
++			break;
++		}
++
++		if (copy_from_user(&p.uwnd_o,
++					(void __user *)arg,
++					sizeof(p.uwnd_o))) {
++			r = -EFAULT;
++			break;
++		}
++
++		r = omapfb_update_window(fbi, p.uwnd_o.x, p.uwnd_o.y,
++				p.uwnd_o.width, p.uwnd_o.height);
++		break;
++
++	case OMAPFB_UPDATE_WINDOW:
++		if (!display || !display->update) {
++			r = -EINVAL;
++			break;
++		}
++
++		if (copy_from_user(&p.uwnd, (void __user *)arg,
++					sizeof(p.uwnd))) {
++			r = -EFAULT;
++			break;
++		}
++
++		r = omapfb_update_window(fbi, p.uwnd.x, p.uwnd.y,
++				p.uwnd.width, p.uwnd.height);
++		break;
++
++	case OMAPFB_SETUP_PLANE:
++		if (copy_from_user(&p.plane_info, (void __user *)arg,
++					sizeof(p.plane_info)))
++			r = -EFAULT;
++		else
++			r = omapfb_setup_plane(fbi, &p.plane_info);
++		break;
++
++	case OMAPFB_QUERY_PLANE:
++		r = omapfb_query_plane(fbi, &p.plane_info);
++		if (r < 0)
++			break;
++		if (copy_to_user((void __user *)arg, &p.plane_info,
++					sizeof(p.plane_info)))
++			r = -EFAULT;
++		break;
++
++	case OMAPFB_SETUP_MEM:
++		if (copy_from_user(&p.mem_info, (void __user *)arg,
++					sizeof(p.mem_info)))
++			r = -EFAULT;
++		else
++			r = omapfb_setup_mem(fbi, &p.mem_info);
++		break;
++
++	case OMAPFB_QUERY_MEM:
++		r = omapfb_query_mem(fbi, &p.mem_info);
++		if (r < 0)
++			break;
++		if (copy_to_user((void __user *)arg, &p.mem_info,
++					sizeof(p.mem_info)))
++			r = -EFAULT;
++		break;
++
++	case OMAPFB_GET_CAPS:
++		if (!display) {
++			r = -EINVAL;
++			break;
++		}
++
++		p.caps.ctrl = display->caps;
++
++		if (copy_to_user((void __user *)arg, &p.caps, sizeof(p.caps)))
++			r = -EFAULT;
++		break;
++
++	case OMAPFB_SET_UPDATE_MODE:
++		if (get_user(p.update_mode, (int __user *)arg))
++			r = -EFAULT;
++		else
++			r = omapfb_set_update_mode(fbi, p.update_mode);
++		break;
++
++	case OMAPFB_GET_UPDATE_MODE:
++		r = omapfb_get_update_mode(fbi, &p.update_mode);
++		if (r)
++			break;
++		if (put_user(p.update_mode,
++					(enum omapfb_update_mode __user *)arg))
++			r = -EFAULT;
++		break;
++
++	/* LCD and CTRL tests do the same thing for backward
++	 * compatibility */
++	case OMAPFB_LCD_TEST:
++		if (get_user(p.test_num, (int __user *)arg)) {
++			r = -EFAULT;
++			break;
++		}
++		if (!display || !display->run_test) {
++			r = -EINVAL;
++			break;
++		}
++
++		r = display->run_test(display, p.test_num);
++
++		break;
++
++	case OMAPFB_CTRL_TEST:
++		if (get_user(p.test_num, (int __user *)arg)) {
++			r = -EFAULT;
++			break;
++		}
++		if (!display || !display->run_test) {
++			r = -EINVAL;
++			break;
++		}
++
++		r = display->run_test(display, p.test_num);
++
++		break;
++
++	default:
++		DBG("ioctl unhandled\n");
++		r = -EINVAL;
++	}
++
++	return r;
++}
++
++
+diff --git a/drivers/video/omap2/omapfb-main.c b/drivers/video/omap2/omapfb-main.c
+new file mode 100644
+index 0000000..76bd416
+--- /dev/null
++++ b/drivers/video/omap2/omapfb-main.c
+@@ -0,0 +1,1441 @@
++/*
++ * linux/drivers/video/omap2/omapfb-main.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++
++#include <mach/display.h>
++#include <mach/omapfb.h>
++
++#include "omapfb.h"
++
++#define MODULE_NAME     "omapfb"
++
++static char *def_mode;
++static char *def_vram;
++
++#ifdef DEBUG
++unsigned int omapfb_debug;
++module_param_named(debug, omapfb_debug, bool, 0644);
++#endif
++
++#ifdef DEBUG
++static void fill_fb(void *addr, struct fb_info *fbi)
++{
++	struct fb_var_screeninfo *var = &fbi->var;
++
++	const short w = var->xres_virtual;
++	const short h = var->yres_virtual;
++
++	int y, x;
++	u8 *p = addr;
++
++	for (y = 0; y < h; y++) {
++		for (x = 0; x < w; x++) {
++			if (var->bits_per_pixel == 16) {
++				u16 *pw = (u16 *)p;
++
++				if (x < 20 && y < 20)
++					*pw = 0xffff;
++				else if (x == 20 || x == w - 20 ||
++						y == 20 || y == h - 20)
++					*pw = 0xffff;
++				else if (x == y || w - x == h - y)
++					*pw = ((1<<5)-1)<<11;
++				else if (w - x == y || x == h - y)
++					*pw = ((1<<6)-1)<<5;
++				else {
++					int t = x / (w/3);
++					if (t == 0)
++						*pw = y % 32;
++					else if (t == 1)
++						*pw = (y % 64) << 5;
++					else if (t == 2)
++						*pw = (y % 32) << 11;
++				}
++			} else if (var->bits_per_pixel == 24) {
++				u8 *pb = (u8 *)p;
++
++				int r = 0, g = 0, b = 0;
++
++				if (x < 20 && y < 20)
++					r = g = b = 0xff;
++				else if (x == 20 || x == w - 20 ||
++						y == 20 || y == h - 20)
++					r = g = b = 0xff;
++				else if (x == y || w - x == h - y)
++					r = 0xff;
++				else if (w - x == y || x == h - y)
++					g = 0xff;
++				else {
++					int q = x / (w / 3);
++					u8 base = 255 - (y % 256);
++					if (q == 0)
++						r = base;
++					else if (q == 1)
++						g = base;
++					else if (q == 2)
++						b = base;
++				}
++
++				pb[0] = b;
++				pb[1] = g;
++				pb[2] = r;
++
++			} else if (var->bits_per_pixel == 32) {
++				u32 *pd = (u32 *)p;
++
++				if (x < 20 && y < 20)
++					*pd = 0xffffff;
++				else if (x == 20 || x == w - 20 ||
++						y == 20 || y == h - 20)
++					*pd = 0xffffff;
++				else if (x == y || w - x == h - y)
++					*pd = 0xff0000;
++				else if (w - x == y || x == h - y)
++					*pd = 0x00ff00;
++				else {
++					u8 base = 255 - (y % 256);
++					*pd = base << ((x / (w/3)) << 3);
++				}
++			}
++
++			p += var->bits_per_pixel >> 3;
++		}
++	}
++}
++#endif
++
++static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var)
++{
++	switch (var->nonstd) {
++	case 0:
++		break;
++	case OMAPFB_COLOR_YUV422:
++		return OMAP_DSS_COLOR_UYVY;
++
++	case OMAPFB_COLOR_YUY422:
++		return OMAP_DSS_COLOR_YUV2;
++
++	case OMAPFB_COLOR_ARGB16:
++		return OMAP_DSS_COLOR_ARGB16;
++
++	case OMAPFB_COLOR_ARGB32:
++		return OMAP_DSS_COLOR_ARGB32;
++
++	case OMAPFB_COLOR_RGBA32:
++		return OMAP_DSS_COLOR_RGBA32;
++
++	case OMAPFB_COLOR_RGBX32:
++		return OMAP_DSS_COLOR_RGBX32;
++
++	default:
++		return -EINVAL;
++	}
++
++	switch (var->bits_per_pixel) {
++	case 1:
++		return OMAP_DSS_COLOR_CLUT1;
++	case 2:
++		return OMAP_DSS_COLOR_CLUT2;
++	case 4:
++		return OMAP_DSS_COLOR_CLUT4;
++	case 8:
++		return OMAP_DSS_COLOR_CLUT8;
++	case 12:
++		return OMAP_DSS_COLOR_RGB12U;
++	case 16:
++		return OMAP_DSS_COLOR_RGB16;
++	case 24:
++		return OMAP_DSS_COLOR_RGB24P;
++	case 32:
++		return OMAP_DSS_COLOR_RGB24U;
++	default:
++		return -EINVAL;
++	}
++
++	return -EINVAL;
++}
++
++void set_fb_fix(struct fb_info *fbi)
++{
++	struct fb_fix_screeninfo *fix = &fbi->fix;
++	struct fb_var_screeninfo *var = &fbi->var;
++	struct omapfb_mem_region *rg = &FB2OFB(fbi)->region;
++
++	DBG("set_fb_fix\n");
++
++	/* used by open/write in fbmem.c */
++	fbi->screen_base        = (char __iomem *)rg->vaddr;
++
++	/* used by mmap in fbmem.c */
++	fix->smem_start         = rg->paddr;
++	fix->smem_len           = rg->size;
++
++	fix->type = FB_TYPE_PACKED_PIXELS;
++
++	if (var->nonstd)
++		fix->visual = FB_VISUAL_PSEUDOCOLOR;
++	else {
++		switch (var->bits_per_pixel) {
++		case 32:
++		case 24:
++		case 16:
++		case 12:
++			fix->visual = FB_VISUAL_TRUECOLOR;
++			/* 12bpp is stored in 16 bits */
++			break;
++		case 1:
++		case 2:
++		case 4:
++		case 8:
++			fix->visual = FB_VISUAL_PSEUDOCOLOR;
++			break;
++		}
++	}
++
++	fix->accel = FB_ACCEL_NONE;
++	fix->line_length = (var->xres_virtual * var->bits_per_pixel) >> 3;
++
++	fix->xpanstep = 1;
++	fix->ypanstep = 1;
++}
++
++/* check new var and possibly modify it to be ok */
++int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omap_display *display = fb2display(fbi);
++	unsigned long max_frame_size;
++	unsigned long line_size;
++	int xres_min, xres_max;
++	int yres_min, yres_max;
++	enum omap_color_mode mode = 0;
++	struct omap_overlay *ovl;
++
++	DBG("check_fb_var %d\n", ofbi->id);
++
++	if (ofbi->region.size == 0) {
++		memset(var, 0, sizeof(*var));
++		return 0;
++	}
++
++	if (ofbi->num_overlays == 0) {
++		dev_err(ofbi->fbdev->dev, "no overlays, aborting\n");
++		return -EINVAL;
++	}
++
++	/* XXX: uses the first overlay */
++	ovl = ofbi->overlays[0];
++
++	/* if we are using non standard mode, fix the bpp first */
++	switch (var->nonstd) {
++	case 0:
++		break;
++	case OMAPFB_COLOR_YUV422:
++	case OMAPFB_COLOR_YUY422:
++	case OMAPFB_COLOR_ARGB16:
++		var->bits_per_pixel = 16;
++		break;
++	case OMAPFB_COLOR_ARGB32:
++	case OMAPFB_COLOR_RGBA32:
++	case OMAPFB_COLOR_RGBX32:
++		var->bits_per_pixel = 32;
++		break;
++	default:
++		DBG("invalid nonstd mode\n");
++		return -EINVAL;
++	}
++
++	mode = fb_mode_to_dss_mode(var);
++	if (mode < 0) {
++		DBG("cannot convert var to omap dss mode\n");
++		return -EINVAL;
++	}
++
++	if ((ovl->supported_modes & mode) == 0) {
++		DBG("invalid mode\n");
++		return -EINVAL;
++	}
++
++	xres_min = OMAPFB_PLANE_XRES_MIN;
++	xres_max = (display ? display->panel->timings.x_res : 2048) - ovl->info.pos_x;
++	yres_min = OMAPFB_PLANE_YRES_MIN;
++	yres_max = (display ? display->panel->timings.y_res : 2048) - ovl->info.pos_y;
++
++	if (var->xres < xres_min)
++		var->xres = xres_min;
++	if (var->yres < yres_min)
++		var->yres = yres_min;
++	if (var->xres_virtual < var->xres)
++		var->xres_virtual = var->xres;
++	if (var->yres_virtual < var->yres)
++		var->yres_virtual = var->yres;
++	max_frame_size = ofbi->region.size;
++	line_size = (var->xres_virtual * var->bits_per_pixel) >> 3;
++
++	if (line_size * var->yres_virtual > max_frame_size) {
++		/* Try to keep yres_virtual first */
++		line_size = max_frame_size / var->yres_virtual;
++		var->xres_virtual = line_size * 8 / var->bits_per_pixel;
++		if (var->xres_virtual < var->xres) {
++			/* Still doesn't fit. Shrink yres_virtual too */
++			var->xres_virtual = var->xres;
++			line_size = var->xres * var->bits_per_pixel / 8;
++			var->yres_virtual = max_frame_size / line_size;
++		}
++		/* Recheck this, as the virtual size changed. */
++		if (var->xres_virtual < var->xres)
++			var->xres = var->xres_virtual;
++		if (var->yres_virtual < var->yres)
++			var->yres = var->yres_virtual;
++		if (var->xres < xres_min || var->yres < yres_min) {
++			DBG("Cannot fit FB to memory\n");
++			return -EINVAL;
++		}
++	}
++	if (var->xres + var->xoffset > var->xres_virtual)
++		var->xoffset = var->xres_virtual - var->xres;
++	if (var->yres + var->yoffset > var->yres_virtual)
++		var->yoffset = var->yres_virtual - var->yres;
++
++	if (var->bits_per_pixel == 16) {
++		var->red.offset  = 11; var->red.length   = 5;
++		var->red.msb_right   = 0;
++		var->green.offset = 5;  var->green.length = 6;
++		var->green.msb_right = 0;
++		var->blue.offset = 0;  var->blue.length  = 5;
++		var->blue.msb_right  = 0;
++	} else if (var->bits_per_pixel == 24) {
++		var->red.offset  = 16; var->red.length   = 8;
++		var->red.msb_right   = 0;
++		var->green.offset = 8;  var->green.length = 8;
++		var->green.msb_right = 0;
++		var->blue.offset = 0;  var->blue.length  = 8;
++		var->blue.msb_right  = 0;
++		var->transp.offset = 0; var->transp.length = 0;
++	} else if (var->bits_per_pixel == 32) {
++		var->red.offset  = 16; var->red.length   = 8;
++		var->red.msb_right   = 0;
++		var->green.offset = 8;  var->green.length = 8;
++		var->green.msb_right = 0;
++		var->blue.offset = 0;  var->blue.length  = 8;
++		var->blue.msb_right  = 0;
++		var->transp.offset = 0; var->transp.length = 0;
++	} else {
++		DBG("failed to setup fb color mask\n");
++		return -EINVAL;
++	}
++
++	DBG("xres = %d, yres = %d, vxres = %d, vyres = %d\n",
++			var->xres, var->yres,
++			var->xres_virtual, var->yres_virtual);
++
++	var->height             = -1;
++	var->width              = -1;
++	var->grayscale          = 0;
++
++	if (display && display->get_timings) {
++		struct omap_video_timings timings;
++		display->get_timings(display, &timings);
++
++		/* pixclock in ps, the rest in pixclock */
++		var->pixclock = timings.pixel_clock != 0 ?
++			KHZ2PICOS(timings.pixel_clock) :
++			0;
++		var->left_margin = timings.hfp;
++		var->right_margin = timings.hbp;
++		var->upper_margin = timings.vfp;
++		var->lower_margin = timings.vbp;
++		var->hsync_len = timings.hsw;
++		var->vsync_len = timings.vsw;
++	} else {
++		var->pixclock = 0;
++		var->left_margin = 0;
++		var->right_margin = 0;
++		var->upper_margin = 0;
++		var->lower_margin = 0;
++		var->hsync_len = 0;
++		var->vsync_len = 0;
++	}
++
++	/* TODO: get these from panel->config */
++	var->vmode              = FB_VMODE_NONINTERLACED;
++	var->sync               = 0;
++
++	return 0;
++}
++
++/*
++ * ---------------------------------------------------------------------------
++ * fbdev framework callbacks
++ * ---------------------------------------------------------------------------
++ */
++static int omapfb_open(struct fb_info *fbi, int user)
++{
++	return 0;
++}
++
++static int omapfb_release(struct fb_info *fbi, int user)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++
++	DBG("Closing fb with plane index %d\n", ofbi->id);
++
++	omapfb_lock(fbdev);
++#if 1
++	if (display) {
++		/* XXX Is this really needed ? */
++		if (display->sync)
++			display->sync(display);
++
++		if (display->update)
++			display->update(display,
++					0, 0,
++					display->panel->timings.x_res,
++					display->panel->timings.y_res);
++	}
++#endif
++
++	if (display && display->sync)
++		display->sync(display);
++
++	omapfb_unlock(fbdev);
++
++	return 0;
++}
++
++/* setup overlay according to the fb */
++int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
++		int posx, int posy, int outw, int outh)
++{
++	int r = 0;
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct fb_var_screeninfo *var = &fbi->var;
++	enum omap_color_mode mode = 0;
++	int offset;
++	u32 data_start_p;
++	void *data_start_v;
++
++	DBG("setup_overlay %d\n", ofbi->id);
++
++	if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 &&
++			(outw != var->xres || outh != var->yres)) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	offset = ((var->yoffset * var->xres_virtual +
++				var->xoffset) * var->bits_per_pixel) >> 3;
++
++	data_start_p = ofbi->region.paddr + offset;
++	data_start_v = ofbi->region.vaddr + offset;
++
++	mode = fb_mode_to_dss_mode(var);
++
++	if (mode == -EINVAL) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	r = ovl->setup_input(ovl,
++			data_start_p, data_start_v,
++			var->xres_virtual,
++			var->xres, var->yres,
++			mode);
++
++	if (r)
++		goto err;
++
++	r = ovl->setup_output(ovl,
++			posx, posy,
++			outw, outh);
++
++	if (r)
++		goto err;
++
++	return 0;
++
++err:
++	DBG("setup_overlay failed\n");
++	return r;
++}
++
++/* apply var to the overlay */
++int omapfb_apply_changes(struct fb_info *fbi, int init)
++{
++	int r = 0;
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct fb_var_screeninfo *var = &fbi->var;
++	struct omap_overlay *ovl;
++	int posx, posy;
++	int outw, outh;
++	int i;
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		ovl = ofbi->overlays[i];
++
++		DBG("apply_changes, fb %d, ovl %d\n", ofbi->id, ovl->id);
++
++		if (ofbi->region.size == 0) {
++			/* the fb is not available. disable the overlay */
++			ovl->enable(ovl, 0);
++			if (!init && ovl->manager)
++				ovl->manager->apply(ovl->manager);
++			continue;
++		}
++
++		if (init || (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
++			outw = var->xres;
++			outh = var->yres;
++		} else {
++			outw = ovl->info.out_width;
++			outh = ovl->info.out_height;
++		}
++
++		if (init) {
++			posx = 0;
++			posy = 0;
++		} else {
++			posx = ovl->info.pos_x;
++			posy = ovl->info.pos_y;
++		}
++
++		r = omapfb_setup_overlay(fbi, ovl, posx, posy, outw, outh);
++		if (r)
++			goto err;
++
++		if (!init && ovl->manager)
++			ovl->manager->apply(ovl->manager);
++	}
++	return 0;
++err:
++	DBG("apply_changes failed\n");
++	return r;
++}
++
++/* checks var and eventually tweaks it to something supported,
++ * DO NOT MODIFY PAR */
++static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
++{
++	int r;
++
++	DBG("check_var(%d)\n", FB2OFB(fbi)->id);
++
++	r = check_fb_var(fbi, var);
++
++	return r;
++}
++
++/* set the video mode according to info->var */
++static int omapfb_set_par(struct fb_info *fbi)
++{
++	int r;
++
++	DBG("set_par(%d)\n", FB2OFB(fbi)->id);
++
++	set_fb_fix(fbi);
++	r = omapfb_apply_changes(fbi, 0);
++
++	return r;
++}
++
++static void omapfb_rotate(struct fb_info *fbi, int rotate)
++{
++	DBG("rotate(%d)\n", FB2OFB(fbi)->id);
++	return;
++}
++
++static int omapfb_pan_display(struct fb_var_screeninfo *var,
++		struct fb_info *fbi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	int r = 0;
++
++	DBG("pan_display(%d)\n", ofbi->id);
++
++	omapfb_lock(fbdev);
++
++	if (var->xoffset != fbi->var.xoffset ||
++	    var->yoffset != fbi->var.yoffset) {
++		struct fb_var_screeninfo new_var;
++
++		new_var = fbi->var;
++		new_var.xoffset = var->xoffset;
++		new_var.yoffset = var->yoffset;
++
++		r = check_fb_var(fbi, &new_var);
++
++		if (r == 0) {
++			fbi->var = new_var;
++			set_fb_fix(fbi);
++			r = omapfb_apply_changes(fbi, 0);
++		}
++	}
++
++	omapfb_unlock(fbdev);
++
++	return r;
++}
++
++static void mmap_user_open(struct vm_area_struct *vma)
++{
++	struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
++
++	atomic_inc(&ofbi->map_count);
++}
++
++static void mmap_user_close(struct vm_area_struct *vma)
++{
++	struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
++
++	atomic_dec(&ofbi->map_count);
++}
++
++static struct vm_operations_struct mmap_user_ops = {
++	.open = mmap_user_open,
++	.close = mmap_user_close,
++};
++
++static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb_mem_region *rg = &ofbi->region;
++	unsigned long off;
++	unsigned long start;
++	u32 len;
++
++	if (vma->vm_end - vma->vm_start == 0)
++		return 0;
++	if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
++		return -EINVAL;
++	off = vma->vm_pgoff << PAGE_SHIFT;
++
++	start = rg->paddr;
++	len = rg->size;
++	if (off >= len)
++		return -EINVAL;
++	if ((vma->vm_end - vma->vm_start + off) > len)
++		return -EINVAL;
++	off += start;
++	vma->vm_pgoff = off >> PAGE_SHIFT;
++	vma->vm_flags |= VM_IO | VM_RESERVED;
++	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++	vma->vm_ops = &mmap_user_ops;
++	vma->vm_private_data = ofbi;
++	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
++			     vma->vm_end - vma->vm_start, vma->vm_page_prot))
++		return -EAGAIN;
++	/* vm_ops.open won't be called for mmap itself. */
++	atomic_inc(&ofbi->map_count);
++	return 0;
++}
++
++/* Store a single color palette entry into a pseudo palette or the hardware
++ * palette if one is available. For now we support only 16bpp and thus store
++ * the entry only to the pseudo palette.
++ */
++static int _setcolreg(struct fb_info *fbi, u_int regno, u_int red, u_int green,
++		u_int blue, u_int transp, int update_hw_pal)
++{
++	/*struct omapfb_info *ofbi = FB2OFB(fbi);*/
++	/*struct omapfb2_device *fbdev = ofbi->fbdev;*/
++	struct fb_var_screeninfo *var = &fbi->var;
++	int r = 0;
++
++	enum omapfb_color_format mode = OMAPFB_COLOR_RGB24U; /* XXX */
++
++	/*switch (plane->color_mode) {*/
++	switch (mode) {
++	case OMAPFB_COLOR_YUV422:
++	case OMAPFB_COLOR_YUV420:
++	case OMAPFB_COLOR_YUY422:
++		r = -EINVAL;
++		break;
++	case OMAPFB_COLOR_CLUT_8BPP:
++	case OMAPFB_COLOR_CLUT_4BPP:
++	case OMAPFB_COLOR_CLUT_2BPP:
++	case OMAPFB_COLOR_CLUT_1BPP:
++		/*
++		   if (fbdev->ctrl->setcolreg)
++		   r = fbdev->ctrl->setcolreg(regno, red, green, blue,
++		   transp, update_hw_pal);
++		   */
++		/* Fallthrough */
++		r = -EINVAL;
++		break;
++	case OMAPFB_COLOR_RGB565:
++	case OMAPFB_COLOR_RGB444:
++	case OMAPFB_COLOR_RGB24P:
++	case OMAPFB_COLOR_RGB24U:
++		if (r != 0)
++			break;
++
++		if (regno < 0) {
++			r = -EINVAL;
++			break;
++		}
++
++		if (regno < 16) {
++			u16 pal;
++			pal = ((red >> (16 - var->red.length)) <<
++					var->red.offset) |
++				((green >> (16 - var->green.length)) <<
++				 var->green.offset) |
++				(blue >> (16 - var->blue.length));
++			((u32 *)(fbi->pseudo_palette))[regno] = pal;
++		}
++		break;
++	default:
++		BUG();
++	}
++	return r;
++}
++
++static int omapfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
++		u_int transp, struct fb_info *info)
++{
++	DBG("setcolreg\n");
++
++	return _setcolreg(info, regno, red, green, blue, transp, 1);
++}
++
++static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
++{
++	int count, index, r;
++	u16 *red, *green, *blue, *transp;
++	u16 trans = 0xffff;
++
++	DBG("setcmap\n");
++
++	red     = cmap->red;
++	green   = cmap->green;
++	blue    = cmap->blue;
++	transp  = cmap->transp;
++	index   = cmap->start;
++
++	for (count = 0; count < cmap->len; count++) {
++		if (transp)
++			trans = *transp++;
++		r = _setcolreg(info, index++, *red++, *green++, *blue++, trans,
++				count == cmap->len - 1);
++		if (r != 0)
++			return r;
++	}
++
++	return 0;
++}
++
++static int omapfb_blank(int blank, struct fb_info *fbi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	struct omap_display *display = fb2display(fbi);
++	int do_update = 0;
++	int r = 0;
++
++	omapfb_lock(fbdev);
++
++	switch (blank) {
++	case FB_BLANK_UNBLANK:
++		if (display->state != OMAP_DSS_DISPLAY_SUSPENDED) {
++			r = -EINVAL;
++			goto exit;
++		}
++
++		if (display->resume)
++			r = display->resume(display);
++
++		if (r == 0 && display->get_update_mode &&
++				display->get_update_mode(display) ==
++				OMAP_DSS_UPDATE_MANUAL)
++			do_update = 1;
++
++		break;
++
++	case FB_BLANK_POWERDOWN:
++		if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
++			r = -EINVAL;
++			goto exit;
++		}
++
++		if (display->suspend)
++			r = display->suspend(display);
++
++		break;
++
++	default:
++		r = -EINVAL;
++	}
++
++exit:
++	omapfb_unlock(fbdev);
++
++	if (r == 0 && do_update && display->update)
++		r = display->update(display,
++				0, 0,
++				display->panel->timings.x_res,
++				display->panel->timings.y_res);
++
++	return r;
++}
++
++static struct fb_ops omapfb_ops = {
++	.owner          = THIS_MODULE,
++	.fb_open        = omapfb_open,
++	.fb_release     = omapfb_release,
++	.fb_fillrect    = cfb_fillrect,
++	.fb_copyarea    = cfb_copyarea,
++	.fb_imageblit   = cfb_imageblit,
++	.fb_blank       = omapfb_blank,
++	.fb_ioctl       = omapfb_ioctl,
++	.fb_check_var   = omapfb_check_var,
++	.fb_set_par     = omapfb_set_par,
++	.fb_rotate      = omapfb_rotate,
++	.fb_pan_display = omapfb_pan_display,
++	.fb_mmap	= omapfb_mmap,
++	.fb_setcolreg	= omapfb_setcolreg,
++	.fb_setcmap	= omapfb_setcmap,
++};
++
++static void omapfb_free_fbmem(struct omapfb2_device *fbdev, int fbnum)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[fbnum]);
++	struct omapfb_mem_region *rg;
++
++	rg = &ofbi->region;
++
++	if (rg->paddr)
++		if (omap_vram_free(rg->paddr, rg->vaddr, rg->size))
++			dev_err(fbdev->dev, "VRAM FREE failed\n");
++
++	rg->vaddr = NULL;
++	rg->paddr = 0;
++	rg->alloc = 0;
++	rg->size = 0;
++}
++
++static int omapfb_free_all_fbmem(struct omapfb2_device *fbdev)
++{
++	int i;
++
++	DBG("free all fbmem\n");
++
++	for (i = 0; i < fbdev->num_fbs; i++)
++		omapfb_free_fbmem(fbdev, i);
++
++	return 0;
++}
++
++static int omapfb_alloc_fbmem(struct omapfb2_device *fbdev, int fbnum,
++		unsigned long size)
++{
++	struct omapfb_info *ofbi;
++	struct omapfb_mem_region *rg;
++	unsigned long paddr;
++	void *vaddr;
++
++	size = PAGE_ALIGN(size);
++
++	ofbi = FB2OFB(fbdev->fbs[fbnum]);
++	rg = &ofbi->region;
++	memset(rg, 0, sizeof(*rg));
++
++	DBG("allocating %lu bytes for fb %d\n",
++			size, ofbi->id);
++
++	vaddr = omap_vram_alloc(OMAPFB_MEMTYPE_SDRAM, size, &paddr);
++	DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
++
++	if (vaddr == NULL) {
++		dev_err(fbdev->dev,
++				"failed to allocate framebuffer\n");
++		return -ENOMEM;
++	}
++
++	rg->paddr = paddr;
++	rg->vaddr = vaddr;
++	rg->size = size;
++	rg->alloc = 1;
++
++	return 0;
++}
++
++int omapfb_realloc_fbmem(struct omapfb2_device *fbdev, int fbnum,
++		unsigned long size)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[fbnum]);
++	struct omapfb_mem_region *rg = &ofbi->region;
++	unsigned old_size = rg->size;
++	int r;
++
++	size = PAGE_ALIGN(size);
++
++	omapfb_free_fbmem(fbdev, fbnum);
++
++	if (size == 0)
++		return 0;
++
++	r = omapfb_alloc_fbmem(fbdev, fbnum, size);
++
++	if (r)
++		omapfb_alloc_fbmem(fbdev, fbnum, old_size);
++
++	return r;
++}
++
++/* allocate fbmem using display resolution as reference */
++static int omapfb_alloc_fbmem_display(struct omapfb2_device *fbdev, int fbnum,
++		unsigned long def_vram)
++{
++	struct omapfb_info *ofbi;
++	struct omap_display *display;
++	int bytespp;
++	unsigned long size;
++
++	ofbi = FB2OFB(fbdev->fbs[fbnum]);
++	display =  fb2display(fbdev->fbs[fbnum]);
++
++	if (!display)
++		return 0;
++
++	switch (display->panel->bpp) {
++	case 16:
++		bytespp = 2;
++		break;
++	case 24:
++	case 32:
++		bytespp = 4;
++		break;
++	default:
++		bytespp = 4;
++		break;
++	}
++
++	size = display->panel->timings.x_res * display->panel->timings.y_res *
++		bytespp;
++
++	if (def_vram > size)
++		size = def_vram;
++
++	return omapfb_alloc_fbmem(fbdev, fbnum, size);
++}
++
++static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
++{
++	int i, r;
++	unsigned long vrams[10];
++
++	memset(vrams, 0, sizeof(vrams));
++
++	if (def_vram) {
++		char *p = def_vram;
++		i = 0;
++
++		while (true) {
++			unsigned long size;
++
++			size = memparse(p, &p);
++
++			if (size == 0) {
++				dev_err(fbdev->dev, "illegal vram size\n");
++				break;
++			}
++
++			vrams[i++] = size;
++
++			if (*p != ',')
++				break;
++
++			p++;
++		}
++	}
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		r = omapfb_alloc_fbmem_display(fbdev, i, vrams[i]);
++
++		if (r)
++			return r;
++	}
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++		struct omapfb_mem_region *rg;
++		rg = &ofbi->region;
++
++		DBG("region%d phys %08x virt %p size=%lu\n",
++				i,
++				rg->paddr,
++				rg->vaddr,
++				rg->size);
++	}
++
++	return 0;
++}
++
++/* initialize fb_info, var, fix to something sane based on the display */
++static int fbinfo_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
++{
++	struct fb_var_screeninfo *var = &fbi->var;
++	struct fb_fix_screeninfo *fix = &fbi->fix;
++	struct omap_display *display = fb2display(fbi);
++	int r = 0;
++
++	fbi->fbops = &omapfb_ops;
++	fbi->flags = FBINFO_FLAG_DEFAULT;
++	fbi->pseudo_palette = fbdev->pseudo_palette;
++
++	strncpy(fix->id, MODULE_NAME, sizeof(fix->id));
++
++	var->nonstd = 0;
++
++	if (display) {
++		var->xres = display->panel->timings.x_res;
++		var->yres = display->panel->timings.y_res;
++		var->xres_virtual = var->xres;
++		var->yres_virtual = var->yres;
++		/*        var->rotate       = def_rotate; */
++
++		switch (display->panel->bpp) {
++		case 16:
++			var->bits_per_pixel = 16;
++			break;
++		case 18:
++			var->bits_per_pixel = 16;
++			break;
++		case 24:
++			var->bits_per_pixel = 32;
++			break;
++		default:
++			dev_err(fbdev->dev, "illegal display bpp\n");
++			return -EINVAL;
++		}
++	}
++
++	r = check_fb_var(fbi, var);
++	if (r)
++		goto err;
++
++	set_fb_fix(fbi);
++
++#ifdef DEBUG
++	if (omapfb_debug)
++		fill_fb(FB2OFB(fbi)->region.vaddr, fbi);
++#endif
++err:
++	return r;
++}
++
++static void fbinfo_cleanup(struct omapfb2_device *fbdev, struct fb_info *fbi)
++{
++	fb_dealloc_cmap(&fbi->cmap);
++}
++
++
++static void omapfb_free_resources(struct omapfb2_device *fbdev)
++{
++	int i;
++
++	DBG("free_resources\n");
++
++	if (fbdev == NULL)
++		return;
++
++	for (i = 0; i < fbdev->num_fbs; i++)
++		unregister_framebuffer(fbdev->fbs[i]);
++
++	/* free the reserved fbmem */
++	omapfb_free_all_fbmem(fbdev);
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		fbinfo_cleanup(fbdev, fbdev->fbs[i]);
++		framebuffer_release(fbdev->fbs[i]);
++	}
++
++	for (i = 0; i < fbdev->num_displays; i++) {
++		if (fbdev->displays[i]->state != OMAP_DSS_DISPLAY_DISABLED)
++			fbdev->displays[i]->disable(fbdev->displays[i]);
++
++		omap_dss_put_display(fbdev->displays[i]);
++	}
++
++	dev_set_drvdata(fbdev->dev, NULL);
++	kfree(fbdev);
++}
++
++static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
++{
++	int r, i;
++
++	fbdev->num_fbs = 0;
++
++	DBG("create %d framebuffers\n",	CONFIG_FB_OMAP2_NUM_FBS);
++
++	/* allocate fb_infos */
++	for (i = 0; i < CONFIG_FB_OMAP2_NUM_FBS; i++) {
++		struct fb_info *fbi;
++		struct omapfb_info *ofbi;
++
++		fbi = framebuffer_alloc(sizeof(struct omapfb_info),
++				fbdev->dev);
++
++		if (fbi == NULL) {
++			dev_err(fbdev->dev,
++				"unable to allocate memory for plane info\n");
++			return -ENOMEM;
++		}
++
++		fbdev->fbs[i] = fbi;
++
++		ofbi = FB2OFB(fbi);
++		ofbi->fbdev = fbdev;
++		ofbi->id = i;
++		fbdev->num_fbs++;
++	}
++
++	DBG("fb_infos allocated\n");
++
++	/* assign overlays for the fbs */
++	for (i = 0; i < min(fbdev->num_fbs, fbdev->num_overlays); i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++		ofbi->overlays[0] = fbdev->overlays[i];
++		ofbi->num_overlays = 1;
++	}
++
++	/* allocate fb memories */
++	r = omapfb_allocate_all_fbs(fbdev);
++	if (r) {
++		dev_err(fbdev->dev, "failed to allocate fbmem\n");
++		return r;
++	}
++
++	DBG("fbmems allocated\n");
++
++	/* setup fb_infos */
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		r = fbinfo_init(fbdev, fbdev->fbs[i]);
++		if (r) {
++			dev_err(fbdev->dev, "failed to setup fb_info\n");
++			return r;
++		}
++	}
++
++	DBG("fb_infos initialized\n");
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		r = register_framebuffer(fbdev->fbs[i]);
++		if (r != 0) {
++			dev_err(fbdev->dev,
++				"registering framebuffer %d failed\n", i);
++			return r;
++		}
++	}
++
++	DBG("framebuffers registered\n");
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		r = omapfb_apply_changes(fbdev->fbs[i], 1);
++		if (r)
++			dev_err(fbdev->dev, "failed to change mode\n");
++	}
++
++	/* Enable the first framebuffer that has overlay that is connected
++	 * to display. Usually this would be the GFX plane. */
++	r = 0;
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++		int t;
++
++		for (t = 0; t < ofbi->num_overlays; t++) {
++			struct omap_overlay *ovl = ofbi->overlays[t];
++			if (ovl->manager && ovl->manager->display) {
++				ovl->enable(ovl, 1);
++				r = 1;
++				break;
++			}
++		}
++
++		if (r)
++			break;
++	}
++
++	DBG("create_framebuffers done\n");
++
++	return 0;
++}
++
++int omapfb_mode_to_timings(const char *mode_str,
++		struct omap_video_timings *timings, unsigned *bpp)
++{
++	struct fb_info fbi;
++	struct fb_var_screeninfo var;
++	struct fb_ops fbops;
++	int r;
++
++	/* this is quite a hack, but I wanted to use the modedb and for
++	 * that we need fb_info and var, so we create dummy ones */
++
++	memset(&fbi, 0, sizeof(fbi));
++	memset(&var, 0, sizeof(var));
++	memset(&fbops, 0, sizeof(fbops));
++	fbi.fbops = &fbops;
++
++	r = fb_find_mode(&var, &fbi, mode_str, NULL, 0, NULL, 24);
++
++	if (r != 0) {
++		timings->pixel_clock = PICOS2KHZ(var.pixclock);
++		timings->hfp = var.left_margin;
++		timings->hbp = var.right_margin;
++		timings->vfp = var.upper_margin;
++		timings->vbp = var.lower_margin;
++		timings->hsw = var.hsync_len;
++		timings->vsw = var.vsync_len;
++		timings->x_res = var.xres;
++		timings->y_res = var.yres;
++
++		switch (var.bits_per_pixel) {
++		case 16:
++			*bpp = 16;
++			break;
++		case 24:
++		case 32:
++		default:
++			*bpp = 24;
++			break;
++		}
++
++		return 0;
++	} else {
++		return -EINVAL;
++	}
++}
++
++static int omapfb_probe(struct platform_device *pdev)
++{
++	struct omapfb2_device *fbdev = NULL;
++	int r = 0;
++	int i, t;
++	struct omap_overlay *ovl;
++	struct omap_display *def_display;
++
++	DBG("omapfb_probe\n");
++
++	if (pdev->num_resources != 0) {
++		dev_err(&pdev->dev, "probed for an unknown device\n");
++		r = -ENODEV;
++		goto err0;
++	}
++
++	fbdev = kzalloc(sizeof(struct omapfb2_device), GFP_KERNEL);
++	if (fbdev == NULL) {
++		r = -ENOMEM;
++		goto err0;
++	}
++
++	mutex_init(&fbdev->mtx);
++
++	fbdev->dev = &pdev->dev;
++	platform_set_drvdata(pdev, fbdev);
++
++	fbdev->num_displays = 0;
++	t = omap_dss_get_num_displays();
++	for (i = 0; i < t; i++) {
++		struct omap_display *display;
++		display = omap_dss_get_display(i);
++		if (!display) {
++			dev_err(&pdev->dev, "can't get display %d\n", i);
++			r = -EINVAL;
++			goto cleanup;
++		}
++
++		fbdev->displays[fbdev->num_displays++] = display;
++	}
++
++	if (fbdev->num_displays == 0) {
++		dev_err(&pdev->dev, "no displays\n");
++		r = -EINVAL;
++		goto cleanup;
++	}
++
++	fbdev->num_overlays = omap_dss_get_num_overlays();
++	for (i = 0; i < fbdev->num_overlays; i++)
++		fbdev->overlays[i] = omap_dss_get_overlay(i);
++
++	fbdev->num_managers = omap_dss_get_num_overlay_managers();
++	for (i = 0; i < fbdev->num_managers; i++)
++		fbdev->managers[i] = omap_dss_get_overlay_manager(i);
++
++
++	/* gfx overlay should be the default one. find a display
++	 * connected to that, and use it as default display */
++	ovl = omap_dss_get_overlay(0);
++	if (ovl->manager && ovl->manager->display) {
++		def_display = ovl->manager->display;
++	} else {
++		dev_err(&pdev->dev, "cannot find default display\n");
++		r = -EINVAL;
++		goto cleanup;
++	}
++
++	if (def_mode && strlen(def_mode) > 0)
++	{
++		struct omap_video_timings timings;
++		unsigned bpp;
++
++		if (omapfb_mode_to_timings(def_mode, &timings, &bpp) == 0) {
++			if (def_display->set_timings)
++				def_display->set_timings(def_display, &timings);
++
++			def_display->panel->bpp = bpp;
++		}
++	}
++
++	r = omapfb_create_framebuffers(fbdev);
++	if (r)
++		goto cleanup;
++
++	for (i = 0; i < fbdev->num_managers; i++) {
++		struct omap_overlay_manager *mgr;
++		mgr = fbdev->managers[i];
++		r = mgr->apply(mgr);
++		if (r) {
++			dev_err(fbdev->dev, "failed to apply dispc config\n");
++			goto cleanup;
++		}
++	}
++
++	DBG("mgr->apply'ed\n");
++
++	r = def_display->enable(def_display);
++	if (r) {
++		dev_err(fbdev->dev, "Failed to enable display '%s'\n",
++				def_display->name);
++		goto cleanup;
++	}
++
++	/* set the update mode */
++	if (def_display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
++#ifdef CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE
++		if (def_display->set_update_mode)
++			def_display->set_update_mode(def_display,
++					OMAP_DSS_UPDATE_AUTO);
++		if (def_display->enable_te)
++			def_display->enable_te(def_display, 1);
++#else
++		if (def_display->set_update_mode)
++			def_display->set_update_mode(def_display,
++					OMAP_DSS_UPDATE_MANUAL);
++		if (def_display->enable_te)
++			def_display->enable_te(def_display, 0);
++#endif
++	} else {
++		if (def_display->set_update_mode)
++			def_display->set_update_mode(def_display,
++					OMAP_DSS_UPDATE_AUTO);
++	}
++
++	for (i = 0; i < fbdev->num_displays; i++) {
++		struct omap_display *display = fbdev->displays[i];
++
++		if (display->update)
++			display->update(display,
++					0, 0,
++					display->panel->timings.x_res,
++					display->panel->timings.y_res);
++	}
++
++	DBG("display->updated\n");
++
++	omapfb_create_sysfs(fbdev);
++	DBG("sysfs created\n");
++
++	return 0;
++
++cleanup:
++	omapfb_free_resources(fbdev);
++err0:
++	dev_err(&pdev->dev, "failed to setup omapfb\n");
++	return r;
++}
++
++static int omapfb_remove(struct platform_device *pdev)
++{
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++
++	/* FIXME: wait till completion of pending events */
++
++	omapfb_remove_sysfs(fbdev);
++
++	omapfb_free_resources(fbdev);
++
++	return 0;
++}
++
++static struct platform_driver omapfb_driver = {
++	.probe          = omapfb_probe,
++	.remove         = omapfb_remove,
++	.driver         = {
++		.name   = "omapfb",
++		.owner  = THIS_MODULE,
++	},
++};
++
++static int __init omapfb_init(void)
++{
++	DBG("omapfb_init\n");
++
++	if (platform_driver_register(&omapfb_driver)) {
++		printk(KERN_ERR "failed to register omapfb driver\n");
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static void __exit omapfb_exit(void)
++{
++	DBG("omapfb_exit\n");
++	platform_driver_unregister(&omapfb_driver);
++}
++
++module_param_named(video_mode, def_mode, charp, 0);
++module_param_named(vram, def_vram, charp, 0);
++
++/* late_initcall to let panel/ctrl drivers loaded first.
++ * I guess better option would be a more dynamic approach,
++ * so that omapfb reacts to new panels when they are loaded */
++late_initcall(omapfb_init);
++/*module_init(omapfb_init);*/
++module_exit(omapfb_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("OMAP2/3 Framebuffer");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/video/omap2/omapfb-sysfs.c b/drivers/video/omap2/omapfb-sysfs.c
+new file mode 100644
+index 0000000..4383e44
+--- /dev/null
++++ b/drivers/video/omap2/omapfb-sysfs.c
+@@ -0,0 +1,901 @@
++/*
++ * linux/drivers/video/omap2/omapfb-sysfs.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/fb.h>
++#include <linux/sysfs.h>
++#include <linux/device.h>
++#include <linux/uaccess.h>
++#include <linux/platform_device.h>
++#include <linux/kernel.h>
++
++#include <mach/display.h>
++#include <mach/omapfb.h>
++
++#include "omapfb.h"
++
++static int omapfb_attach_framebuffer(struct fb_info *fbi,
++		struct omap_overlay *ovl)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++	int i, t;
++	int r;
++
++	if (ofbi->num_overlays >= OMAPFB_MAX_OVL_PER_FB) {
++		dev_err(fbdev->dev, "fb has max number of overlays already\n");
++		return -EINVAL;
++	}
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i] == ovl) {
++			dev_err(fbdev->dev, "fb already attached to overlay\n");
++			return -EINVAL;
++		}
++	}
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct omapfb_info *ofbi2 = FB2OFB(fbdev->fbs[i]);
++		for (t = 0; t < ofbi2->num_overlays; t++) {
++			if (ofbi2->overlays[t] == ovl) {
++				dev_err(fbdev->dev, "overlay already in use\n");
++				return -EINVAL;
++			}
++		}
++	}
++
++	ofbi->overlays[ofbi->num_overlays++] = ovl;
++
++/*
++	if (ovl->manager && ovl->manager->display)
++		omapfb_adjust_fb(fbi, ovl, 0, 0);
++*/
++	r = omapfb_apply_changes(fbi, 1);
++	if (r)
++		return r;
++
++	if (ovl->manager)
++		ovl->manager->apply(ovl->manager);
++
++	return 0;
++}
++
++static int omapfb_detach_framebuffer(struct fb_info *fbi,
++		struct omap_overlay *ovl)
++{
++	int i;
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct omapfb2_device *fbdev = ofbi->fbdev;
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i] == ovl)
++			break;
++	}
++
++	if (i == ofbi->num_overlays) {
++		dev_err(fbdev->dev, "cannot detach fb, overlay not attached\n");
++		return -EINVAL;
++	}
++
++	ovl->enable(ovl, 0);
++
++	if (ovl->manager)
++		ovl->manager->apply(ovl->manager);
++
++	for (i = i + 1; i < ofbi->num_overlays; i++)
++		ofbi->overlays[i-1] = ofbi->overlays[i];
++
++	ofbi->num_overlays--;
++
++	return 0;
++}
++
++
++static ssize_t show_framebuffers(struct device *dev,
++		struct device_attribute *attr,
++		char *buf)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++	ssize_t l = 0, size = PAGE_SIZE;
++	int i, t;
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < fbdev->num_fbs; i++) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++		struct omapfb_mem_region *rg;
++
++		rg = &ofbi->region;
++
++		l += snprintf(buf + l, size - l, "%d p:%08x v:%p size:%lu t:",
++				ofbi->id,
++				rg->paddr, rg->vaddr, rg->size);
++
++		if (ofbi->num_overlays == 0)
++			l += snprintf(buf + l, size - l, "none");
++
++		for (t = 0; t < ofbi->num_overlays; t++) {
++			struct omap_overlay *ovl;
++			ovl = ofbi->overlays[t];
++
++			l += snprintf(buf + l, size - l, "%s%s",
++					t == 0 ? "" : ",",
++					ovl->name);
++		}
++
++		l += snprintf(buf + l, size - l, "\n");
++	}
++
++	omapfb_unlock(fbdev);
++
++	return l;
++}
++
++static struct omap_overlay *find_overlay_by_name(struct omapfb2_device *fbdev,
++		char *name)
++{
++	int i;
++
++	for (i = 0; i < fbdev->num_overlays; i++)
++		if (strcmp(name, fbdev->overlays[i]->name) == 0)
++			return fbdev->overlays[i];
++
++	return NULL;
++}
++
++static struct omap_display *find_display_by_name(struct omapfb2_device *fbdev,
++		char *name)
++{
++	int i;
++
++	for (i = 0; i < fbdev->num_displays; i++)
++		if (strcmp(name, fbdev->displays[i]->name) == 0)
++			return fbdev->displays[i];
++
++	return NULL;
++}
++
++static struct omap_overlay_manager *find_manager_by_name(
++		struct omapfb2_device *fbdev,
++		char *name)
++{
++	int i;
++
++	for (i = 0; i < fbdev->num_managers; i++)
++		if (strcmp(name, fbdev->managers[i]->name) == 0)
++			return fbdev->managers[i];
++
++	return NULL;
++}
++
++static int parse_overlays(struct omapfb2_device *fbdev, char *str,
++		struct omap_overlay *ovls[])
++{
++	int num_ovls = 0;
++	int s, e = 0;
++	char ovlname[10];
++
++	while (1) {
++		struct omap_overlay *ovl;
++
++		s = e;
++
++		while (e < strlen(str) && str[e] != ',')
++			e++;
++
++		strncpy(ovlname, str + s, e - s);
++		ovlname[e-s] = 0;
++
++		DBG("searching for '%s'\n", ovlname);
++		ovl = find_overlay_by_name(fbdev, ovlname);
++
++		if (ovl) {
++			DBG("found an overlay\n");
++			ovls[num_ovls] = ovl;
++			num_ovls++;
++		} else {
++			DBG("unknown overlay %s\n", str);
++			return 0;
++		}
++
++		if (e == strlen(str))
++			break;
++
++		e++;
++	}
++
++	return num_ovls;
++}
++
++static ssize_t store_framebuffers(struct device *dev,
++		struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++	int idx;
++	char fbname[3];
++	unsigned long fbnum;
++	char ovlnames[40];
++	int num_ovls = 0;
++	struct omap_overlay *ovls[OMAPFB_MAX_OVL_PER_FB];
++	struct fb_info *fbi;
++	struct omapfb_info *ofbi;
++	int r, i;
++
++	idx = 0;
++	while (idx < count && buf[idx] != ' ')
++		++idx;
++
++	if (idx == count)
++		return -EINVAL;
++
++	if (idx >= sizeof(fbname))
++		return -EINVAL;
++
++	strncpy(fbname, buf, idx);
++	fbname[idx] = 0;
++	idx++;
++
++	if (strict_strtoul(fbname, 10, &fbnum))
++		return -EINVAL;
++
++	r = sscanf(buf + idx, "t:%39s", ovlnames);
++
++	if (r != 1) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	omapfb_lock(fbdev);
++
++	if (fbnum >= fbdev->num_fbs) {
++		dev_err(dev, "fb not found\n");
++		r = -EINVAL;
++		goto err;
++	}
++
++	fbi = fbdev->fbs[fbnum];
++	ofbi = FB2OFB(fbi);
++
++	if (strcmp(ovlnames, "none") == 0) {
++		num_ovls = 0;
++	} else {
++		num_ovls = parse_overlays(fbdev, ovlnames, ovls);
++
++		if (num_ovls == 0) {
++			dev_err(dev, "overlays not found\n");
++			r = -EINVAL;
++			goto err;
++		}
++	}
++
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		r = omapfb_detach_framebuffer(fbi, ofbi->overlays[i]);
++		if (r) {
++			dev_err(dev, "detach failed\n");
++			goto err;
++		}
++	}
++
++	if (num_ovls > 0) {
++		for (i = 0; i < num_ovls; i++) {
++			r = omapfb_attach_framebuffer(fbi, ovls[i]);
++			if (r) {
++				dev_err(dev, "attach failed\n");
++				goto err;
++			}
++		}
++	}
++
++	omapfb_unlock(fbdev);
++	return count;
++
++err:
++	omapfb_unlock(fbdev);
++	return r;
++}
++
++static ssize_t show_overlays(struct device *dev, struct device_attribute *attr,
++		char *buf)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++	ssize_t l = 0, size = PAGE_SIZE;
++	int i, mgr_num;
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < fbdev->num_overlays; i++) {
++		struct omap_overlay *ovl;
++		struct omap_overlay_manager *mgr;
++
++		ovl = fbdev->overlays[i];
++		mgr = ovl->manager;
++
++		for (mgr_num = 0; mgr_num < fbdev->num_managers; mgr_num++)
++			if (fbdev->managers[mgr_num] == mgr)
++				break;
++
++		l += snprintf(buf + l, size - l,
++			"%s t:%s x:%d y:%d iw:%d ih:%d w: %d h: %d e:%d\n",
++			ovl->name,
++			mgr ? mgr->name : "none",
++			ovl->info.pos_x,
++			ovl->info.pos_y,
++			ovl->info.width,
++			ovl->info.height,
++			ovl->info.out_width,
++			ovl->info.out_height,
++			ovl->info.enabled);
++	}
++
++	omapfb_unlock(fbdev);
++
++	return l;
++}
++
++static ssize_t store_overlays(struct device *dev,
++		struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++	int idx;
++	struct omap_overlay *ovl = NULL;
++	struct omap_overlay_manager *mgr;
++	int r;
++	char ovlname[10];
++	int posx, posy, outw, outh;
++	int enabled;
++
++	idx = 0;
++	while (idx < count && buf[idx] != ' ')
++		++idx;
++
++	if (idx == count)
++		return -EINVAL;
++
++	if (idx >= sizeof(ovlname))
++		return -EINVAL;
++
++	strncpy(ovlname, buf, idx);
++	ovlname[idx] = 0;
++	idx++;
++
++	omapfb_lock(fbdev);
++
++	ovl = find_overlay_by_name(fbdev, ovlname);
++
++	if (!ovl) {
++		dev_err(dev, "ovl not found\n");
++		r = -EINVAL;
++		goto err;
++	}
++
++	DBG("ovl %s found\n", ovl->name);
++
++	mgr = ovl->manager;
++
++	posx = ovl->info.pos_x;
++	posy = ovl->info.pos_y;
++	outw = ovl->info.out_width;
++	outh = ovl->info.out_height;
++	enabled = ovl->info.enabled;
++
++	while (idx < count) {
++		char c;
++		int val;
++		int len;
++		char sval[10];
++
++		r = sscanf(buf + idx, "%c:%d%n", &c, &val, &len);
++
++		if (r != 2) {
++			val = 0;
++
++			r = sscanf(buf + idx, "%c:%9s%n", &c, sval, &len);
++
++			if (r != 2) {
++				dev_err(dev, "sscanf failed, aborting\n");
++				r = -EINVAL;
++				goto err;
++			}
++		} else {
++			sval[0] = 0;
++		}
++
++		switch (c) {
++		case 't':
++			if (strcmp(sval, "none") == 0) {
++				mgr = NULL;
++			} else {
++				mgr = find_manager_by_name(fbdev, sval);
++
++				if (mgr == NULL) {
++					dev_err(dev, "no such manager\n");
++					r = -EINVAL;
++					goto err;
++				}
++
++				DBG("manager %s found\n", mgr->name);
++			}
++
++			break;
++
++		case 'x':
++			posx = val;
++			break;
++
++		case 'y':
++			posy = val;
++			break;
++
++		case 'w':
++			if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE)
++				outw = val;
++			break;
++
++		case 'h':
++			if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE)
++				outh = val;
++			break;
++
++		case 'e':
++			enabled = val;
++			break;
++
++		default:
++			dev_err(dev, "unknown option %c\n", c);
++			r = -EINVAL;
++			goto err;
++		}
++
++		idx += len + 1;
++	}
++
++	r = ovl->setup_output(ovl, posx, posy, outw, outh);
++
++	if (r) {
++		dev_err(dev, "setup overlay failed\n");
++		goto err;
++	}
++
++	if (mgr != ovl->manager) {
++		/* detach old manager */
++		if (ovl->manager) {
++			r = ovl->unset_manager(ovl);
++			if (r) {
++				dev_err(dev, "detach failed\n");
++				goto err;
++			}
++		}
++
++		if (mgr) {
++			r = ovl->set_manager(ovl, mgr);
++			if (r) {
++				dev_err(dev, "Failed to attach overlay\n");
++				goto err;
++			}
++		}
++	}
++
++	r = ovl->enable(ovl, enabled);
++
++	if (r) {
++		dev_err(dev, "enable overlay failed\n");
++		goto err;
++	}
++
++	if (mgr) {
++		r = mgr->apply(mgr);
++		if (r) {
++			dev_err(dev, "failed to apply dispc config\n");
++			goto err;
++		}
++	} else {
++		ovl->enable(ovl, 0);
++	}
++
++	if (mgr && mgr->display && mgr->display->update)
++		mgr->display->update(mgr->display,
++				0, 0,
++				mgr->display->panel->timings.x_res,
++				mgr->display->panel->timings.y_res);
++
++	omapfb_unlock(fbdev);
++	return count;
++
++err:
++	omapfb_unlock(fbdev);
++	return r;
++}
++
++static ssize_t show_managers(struct device *dev, struct device_attribute *attr,
++		char *buf)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++	ssize_t l = 0, size = PAGE_SIZE;
++	int i;
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < fbdev->num_managers; i++) {
++		struct omap_display *display;
++		struct omap_overlay_manager *mgr;
++
++		mgr = fbdev->managers[i];
++		display = mgr->display;
++
++		l += snprintf(buf + l, size - l, "%s t:%s\n",
++				mgr->name, display ? display->name : "none");
++	}
++
++	omapfb_unlock(fbdev);
++
++	return l;
++}
++
++static ssize_t store_managers(struct device *dev,
++		struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++	int idx;
++	struct omap_overlay_manager *mgr;
++	struct omap_display *display;
++	char mgrname[10];
++	char displayname[10];
++	int r;
++
++	idx = 0;
++	while (idx < count && buf[idx] != ' ')
++		++idx;
++
++	if (idx == count)
++		return -EINVAL;
++
++	if (idx >= sizeof(mgrname))
++		return -EINVAL;
++
++	strncpy(mgrname, buf, idx);
++	mgrname[idx] = 0;
++	idx++;
++
++	omapfb_lock(fbdev);
++
++	mgr = find_manager_by_name(fbdev, mgrname);
++
++	if (!mgr) {
++		dev_err(dev, "manager not found\n");
++		r = -EINVAL;
++		goto err;
++	}
++
++	r = sscanf(buf + idx, "t:%9s", displayname);
++
++	if (r != 1) {
++		r = -EINVAL;
++		goto err;
++	}
++
++	if (strcmp(displayname, "none") == 0) {
++		display = NULL;
++	} else {
++		display = find_display_by_name(fbdev, displayname);
++
++		if (!display) {
++			dev_err(dev, "display not found\n");
++			r = -EINVAL;
++			goto err;
++		}
++	}
++
++	if (mgr->display) {
++		r = mgr->unset_display(mgr);
++		if (r) {
++			dev_err(dev, "failed to unset display\n");
++			goto err;
++		}
++	}
++
++	if (display) {
++		r = mgr->set_display(mgr, display);
++		if (r) {
++			dev_err(dev, "failed to set manager\n");
++			goto err;
++		}
++
++		r = mgr->apply(mgr);
++		if (r) {
++			dev_err(dev, "failed to apply dispc config\n");
++			goto err;
++		}
++	}
++
++	omapfb_unlock(fbdev);
++	return count;
++
++err:
++	omapfb_unlock(fbdev);
++	return r;
++}
++
++static ssize_t show_displays(struct device *dev, struct device_attribute *attr,
++		char *buf)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++	ssize_t l = 0, size = PAGE_SIZE;
++	int i;
++	struct omap_video_timings timings;
++
++	omapfb_lock(fbdev);
++
++	for (i = 0; i < fbdev->num_displays; i++) {
++		struct omap_display *display;
++		enum omap_dss_update_mode mode = -1;
++		int te = 0;
++
++		display = fbdev->displays[i];
++
++		if (display->get_update_mode)
++			mode = display->get_update_mode(display);
++
++		if (display->get_te)
++			te = display->get_te(display);
++
++		if (display->get_timings)
++			display->get_timings(display, &timings);
++		else
++			memset(&timings, 0, sizeof(timings));
++
++		l += snprintf(buf + l, size - l,
++				"%s e:%d u:%d t:%d h:%u/%u/%u/%u "
++				"v:%u/%u/%u/%u p:%u\n",
++				display->name,
++				display->state != OMAP_DSS_DISPLAY_DISABLED,
++				mode, te,
++				timings.x_res,
++				timings.hfp, timings.hbp, timings.hsw,
++				timings.y_res,
++				timings.vfp, timings.vbp, timings.vsw,
++				timings.pixel_clock);
++	}
++
++	omapfb_unlock(fbdev);
++
++	return l;
++}
++
++static ssize_t store_displays(struct device *dev,
++		struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++	int enable;
++	struct omap_video_timings old_timings;
++	struct omap_video_timings new_timings;
++	enum omap_dss_update_mode mode;
++	struct omap_display *display = NULL;
++	int r;
++	int te;
++	char str[128];
++	char *s, *tok;
++
++	if (strlen(buf) > sizeof(str) - 1)
++		return -EINVAL;
++
++	strcpy(str, buf);
++
++	/* remove trailing linefeeds */
++	s = str + strlen(str) - 1;
++	while (s >= str	&& *s == '\n') {
++		*s = 0;
++		s--;
++	}
++
++	s = str;
++
++	if ((tok = strsep(&s, " ")) == 0)
++		return -EINVAL;
++
++	omapfb_lock(fbdev);
++
++	display = find_display_by_name(fbdev, tok);
++
++	if (!display) {
++		dev_err(dev, "display not found\n");
++		r = -EINVAL;
++		goto err;
++	}
++
++	enable = display->state != OMAP_DSS_DISPLAY_DISABLED;
++	if (display->get_update_mode)
++		mode = display->get_update_mode(display);
++	else
++		mode = 0;
++
++	if (display->get_te)
++		te = display->get_te(display);
++	else
++		te = 0;
++
++	if (display->get_timings)
++		display->get_timings(display, &old_timings);
++	else
++		memset(&old_timings, 0, sizeof(old_timings));
++
++	memcpy(&new_timings, &old_timings, sizeof(new_timings));
++
++	while ((tok = strsep(&s, " "))) {
++		char c, *o;
++
++		if (strlen(tok) < 3 || tok[1] != ':') {
++			dev_err(dev, "illegal option\n");
++			r = -EINVAL;
++			goto err;
++		}
++
++		c = tok[0];
++		o = tok + 2;
++
++		switch (c) {
++		case 'e':
++			enable = simple_strtoul(o, NULL, 0);
++			break;
++
++		case 'u':
++			mode = simple_strtoul(o, NULL, 0);
++			break;
++
++		case 't':
++			te = simple_strtoul(o, NULL, 0);
++			break;
++
++		case 'm': {
++			unsigned bpp;
++			if (omapfb_mode_to_timings(o, &new_timings, &bpp) != 0)
++				memset(&new_timings, 0, sizeof(new_timings));
++
++			break;
++		}
++
++		case 'h': {
++			unsigned xres, hfp, hbp, hsw;
++
++			if (sscanf(o, "%u/%u/%u/%u",
++						&xres, &hfp, &hbp, &hsw) != 4) {
++				dev_err(dev, "illegal horizontal timings\n");
++				r = -EINVAL;
++				goto err;
++			}
++
++			new_timings.x_res = xres;
++			new_timings.hfp = hfp;
++			new_timings.hbp = hbp;
++			new_timings.hsw = hsw;
++			break;
++		}
++
++		case 'v': {
++			unsigned yres, vfp, vbp, vsw;
++
++			if (sscanf(o, "%u/%u/%u/%u",
++						&yres, &vfp, &vbp, &vsw) != 4) {
++				dev_err(dev, "illegal vertical timings\n");
++				r = -EINVAL;
++				goto err;
++			}
++
++			new_timings.y_res = yres;
++			new_timings.vfp = vfp;
++			new_timings.vbp = vbp;
++			new_timings.vsw = vsw;
++			break;
++		}
++
++		case 'p':
++			new_timings.pixel_clock = simple_strtoul(o, NULL, 0);
++			break;
++
++		default:
++			dev_err(dev, "unknown option %c\n", c);
++			r = -EINVAL;
++			goto err;
++		}
++	}
++
++	if (memcmp(&new_timings, &old_timings, sizeof(new_timings)) != 0) {
++		if (display->set_timings)
++			display->set_timings(display, &new_timings);
++
++		/* sigh, bpp is not a setting of the display, but
++		 * the overlay. */
++		//def_display->panel->bpp = bpp;
++	}
++
++	if (enable != (display->state != OMAP_DSS_DISPLAY_DISABLED)) {
++		if (enable) {
++			r = display->enable(display);
++			if (r)
++				dev_err(dev, "failed to enable display\n");
++		} else {
++			display->disable(display);
++		}
++	}
++
++	if (display->set_update_mode && display->get_update_mode) {
++		if (mode != display->get_update_mode(display))
++			display->set_update_mode(display, mode);
++	}
++
++	if (display->enable_te && display->get_te) {
++		if (te != display->get_te(display))
++			display->enable_te(display, te);
++	}
++
++	r = count;
++err:
++	omapfb_unlock(fbdev);
++	return r;
++}
++
++
++static DEVICE_ATTR(framebuffers, S_IRUGO | S_IWUSR,
++		show_framebuffers, store_framebuffers);
++static DEVICE_ATTR(overlays, S_IRUGO | S_IWUSR,
++		show_overlays, store_overlays);
++static DEVICE_ATTR(managers, S_IRUGO | S_IWUSR,
++		show_managers, store_managers);
++static DEVICE_ATTR(displays, S_IRUGO | S_IWUSR,
++		show_displays, store_displays);
++
++static struct attribute *omapfb_attrs[] = {
++	&dev_attr_framebuffers.attr,
++	&dev_attr_overlays.attr,
++	&dev_attr_managers.attr,
++	&dev_attr_displays.attr,
++	NULL,
++};
++
++static struct attribute_group omapfb_attr_group = {
++	.attrs = omapfb_attrs,
++};
++
++void omapfb_create_sysfs(struct omapfb2_device *fbdev)
++{
++	int r;
++
++	r = sysfs_create_group(&fbdev->dev->kobj, &omapfb_attr_group);
++	if (r)
++		dev_err(fbdev->dev, "failed to create sysfs clk file\n");
++}
++
++void omapfb_remove_sysfs(struct omapfb2_device *fbdev)
++{
++	sysfs_remove_group(&fbdev->dev->kobj, &omapfb_attr_group);
++}
++
+diff --git a/drivers/video/omap2/omapfb.h b/drivers/video/omap2/omapfb.h
+new file mode 100644
+index 0000000..9ba4f1b
+--- /dev/null
++++ b/drivers/video/omap2/omapfb.h
+@@ -0,0 +1,115 @@
++/*
++ * linux/drivers/video/omap2/omapfb.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
++#define __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
++
++#ifdef CONFIG_FB_OMAP2_DEBUG
++#define DEBUG
++#endif
++
++#ifdef DEBUG
++extern unsigned int omapfb_debug;
++#define DBG(format, ...) \
++	if (omapfb_debug) \
++		printk(KERN_DEBUG "OMAPFB: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define FB2OFB(fb_info) ((struct omapfb_info *)(fb_info->par))
++
++/* max number of overlays to which a framebuffer data can be direct */
++#define OMAPFB_MAX_OVL_PER_FB 3
++
++/* appended to fb_info */
++struct omapfb_info {
++	int id;
++	struct omapfb_mem_region region;
++	atomic_t map_count;
++	int num_overlays;
++	struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB];
++	struct omapfb2_device *fbdev;
++};
++
++struct omapfb2_device {
++	struct device *dev;
++	struct mutex  mtx;
++
++	u32 pseudo_palette[17];
++
++	int state;
++
++	int num_fbs;
++	struct fb_info *fbs[10];
++
++	int num_displays;
++	struct omap_display *displays[10];
++	int num_overlays;
++	struct omap_overlay *overlays[10];
++	int num_managers;
++	struct omap_overlay_manager *managers[10];
++};
++
++void set_fb_fix(struct fb_info *fbi);
++int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var);
++int omapfb_realloc_fbmem(struct omapfb2_device *fbdev, int fbnum,
++		unsigned long size);
++int omapfb_apply_changes(struct fb_info *fbi, int init);
++int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
++		int posx, int posy, int outw, int outh);
++
++void omapfb_create_sysfs(struct omapfb2_device *fbdev);
++void omapfb_remove_sysfs(struct omapfb2_device *fbdev);
++
++int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg);
++
++int omapfb_mode_to_timings(const char *mode_str,
++		struct omap_video_timings *timings, unsigned *bpp);
++
++/* find the display connected to this fb, if any */
++static inline struct omap_display *fb2display(struct fb_info *fbi)
++{
++	struct omapfb_info *ofbi = FB2OFB(fbi);
++	int i;
++
++	/* XXX: returns the display connected to first attached overlay */
++	for (i = 0; i < ofbi->num_overlays; i++) {
++		if (ofbi->overlays[i]->manager)
++			return ofbi->overlays[i]->manager->display;
++	}
++
++	return NULL;
++}
++
++static inline void omapfb_lock(struct omapfb2_device *fbdev)
++{
++	mutex_lock(&fbdev->mtx);
++}
++
++static inline void omapfb_unlock(struct omapfb2_device *fbdev)
++{
++	mutex_unlock(&fbdev->mtx);
++}
++
++
++#endif
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0003-DSS-Add-generic-DVI-panel.patch b/recipes/linux/linux-omap-2.6.28/0003-DSS-Add-generic-DVI-panel.patch
new file mode 100644
index 0000000000..d043671eaf
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0003-DSS-Add-generic-DVI-panel.patch
@@ -0,0 +1,146 @@
+From e9f476d658fb5c7de57498d54c0acd6429439350 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Mon, 5 Jan 2009 15:06:40 +0200
+Subject: [PATCH] DSS: Add generic DVI panel
+
+You also need DSI PLL to generate pix clock for 1280x1024.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/Kconfig         |    5 ++
+ drivers/video/omap2/Makefile        |    2 +
+ drivers/video/omap2/panel-generic.c |   97 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 104 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/panel-generic.c
+
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index 8be51a3..be00882 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -37,6 +37,11 @@ config FB_OMAP2_NUM_FBS
+ menu "OMAP2/3 Display Device Drivers"
+         depends on OMAP2_DSS
+ 
++config PANEL_GENERIC
++        tristate "Generic Panel"
++        help
++	  Generic panel driver.
++	  Used for DVI output for Beagle and OMAP3 SDP.
+ 
+ endmenu
+ 
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index 51c2e00..f471a2b 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -1,2 +1,4 @@
+ obj-$(CONFIG_FB_OMAP2) += omapfb.o
+ omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
++
++obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
+diff --git a/drivers/video/omap2/panel-generic.c b/drivers/video/omap2/panel-generic.c
+new file mode 100644
+index 0000000..5c8fecd
+--- /dev/null
++++ b/drivers/video/omap2/panel-generic.c
+@@ -0,0 +1,97 @@
++/*
++ * Generic panel support
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int generic_panel_init(struct omap_display *display)
++{
++	return 0;
++}
++
++static int generic_panel_enable(struct omap_display *display)
++{
++	int r = 0;
++
++	if (display->hw_config.panel_enable)
++		r = display->hw_config.panel_enable(display);
++
++	return r;
++}
++
++static void generic_panel_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++}
++
++static int generic_panel_suspend(struct omap_display *display)
++{
++	generic_panel_disable(display);
++	return 0;
++}
++
++static int generic_panel_resume(struct omap_display *display)
++{
++	return generic_panel_enable(display);
++}
++
++static struct omap_panel generic_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "panel-generic",
++	.init		= generic_panel_init,
++	.enable		= generic_panel_enable,
++	.disable	= generic_panel_disable,
++	.suspend	= generic_panel_suspend,
++	.resume		= generic_panel_resume,
++
++	.timings = {
++		/* 640 x 480 @ 60 Hz  Reduced blanking VESA CVT 0.31M3-R */
++		.x_res		= 640,
++		.y_res		= 480,
++		.pixel_clock	= 23500,
++		.hfp		= 48,
++		.hsw		= 32,
++		.hbp		= 80,
++		.vfp		= 3,
++		.vsw		= 4,
++		.vbp		= 7,
++	},
++
++	.bpp		= 24,
++	.config		= OMAP_DSS_LCD_TFT,
++};
++
++
++static int __init generic_panel_drv_init(void)
++{
++	omap_dss_register_panel(&generic_panel);
++	return 0;
++}
++
++static void __exit generic_panel_drv_exit(void)
++{
++	omap_dss_unregister_panel(&generic_panel);
++}
++
++module_init(generic_panel_drv_init);
++module_exit(generic_panel_drv_exit);
++MODULE_LICENSE("GPL");
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0004-DSS-support-for-Beagle-Board.patch b/recipes/linux/linux-omap-2.6.28/0004-DSS-support-for-Beagle-Board.patch
new file mode 100644
index 0000000000..e9fe999baf
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0004-DSS-support-for-Beagle-Board.patch
@@ -0,0 +1,1605 @@
+From 76e1700add1c77b614ed11c3e29e8a39bd4e6b8c Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Mon, 29 Sep 2008 17:03:36 +0300
+Subject: [PATCH] DSS: support for Beagle Board
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/configs/dss_omap3_beagle_defconfig | 1437 +++++++++++++++++++++++++++
+ arch/arm/mach-omap2/board-omap3beagle.c     |  101 ++-
+ 2 files changed, 1524 insertions(+), 14 deletions(-)
+ create mode 100644 arch/arm/configs/dss_omap3_beagle_defconfig
+
+diff --git a/arch/arm/configs/dss_omap3_beagle_defconfig b/arch/arm/configs/dss_omap3_beagle_defconfig
+new file mode 100644
+index 0000000..f39167f
+--- /dev/null
++++ b/arch/arm/configs/dss_omap3_beagle_defconfig
+@@ -0,0 +1,1437 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.28-omap1
++# Wed Jan  7 15:22:00 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_MMU=y
++# CONFIG_NO_IOPORT is not set
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_LATENCYTOP_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_CGROUPS is not set
++CONFIG_GROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_RT_GROUP_SCHED is not set
++CONFIG_USER_SCHED=y
++# CONFIG_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
++# CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_EMBEDDED=y
++CONFIG_UID16=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++CONFIG_KALLSYMS_EXTRA_PASS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_COMPAT_BRK=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++CONFIG_CLASSIC_RCU=y
++# CONFIG_FREEZER is not set
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++CONFIG_ARCH_OMAP=y
++# CONFIG_ARCH_MSM is not set
++
++#
++# TI OMAP Implementations
++#
++CONFIG_ARCH_OMAP_OTG=y
++# CONFIG_ARCH_OMAP1 is not set
++# CONFIG_ARCH_OMAP2 is not set
++CONFIG_ARCH_OMAP3=y
++
++#
++# OMAP Feature Selections
++#
++# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
++# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
++# CONFIG_OMAP_SMARTREFLEX is not set
++# CONFIG_OMAP_RESET_CLOCKS is not set
++CONFIG_OMAP_BOOT_TAG=y
++CONFIG_OMAP_BOOT_REASON=y
++# CONFIG_OMAP_COMPONENT_VERSION is not set
++# CONFIG_OMAP_GPIO_SWITCH is not set
++# CONFIG_OMAP_MUX is not set
++# CONFIG_OMAP_MCBSP is not set
++# CONFIG_OMAP_MMU_FWK is not set
++# CONFIG_OMAP_MBOX_FWK is not set
++# CONFIG_OMAP_MPU_TIMER is not set
++CONFIG_OMAP_32K_TIMER=y
++CONFIG_OMAP_32K_TIMER_HZ=128
++CONFIG_OMAP_DM_TIMER=y
++# CONFIG_OMAP_LL_DEBUG_UART1 is not set
++# CONFIG_OMAP_LL_DEBUG_UART2 is not set
++CONFIG_OMAP_LL_DEBUG_UART3=y
++CONFIG_OMAP2_DSS=m
++CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
++CONFIG_ARCH_OMAP34XX=y
++CONFIG_ARCH_OMAP3430=y
++
++#
++# OMAP Board Type
++#
++# CONFIG_MACH_OMAP_LDP is not set
++# CONFIG_MACH_OMAP_3430SDP is not set
++# CONFIG_MACH_OMAP3EVM is not set
++CONFIG_MACH_OMAP3_BEAGLE=y
++# CONFIG_MACH_OVERO is not set
++# CONFIG_MACH_OMAP3_PANDORA is not set
++CONFIG_OMAP_TICK_GPTIMER=12
++
++#
++# Boot options
++#
++
++#
++# Power management
++#
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_IFAR=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_HAS_TLS_REG=y
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=128
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++CONFIG_ARCH_FLATMEM_HAS_HOLES=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++CONFIG_UNEVICTABLE_LRU=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# CPU Power Management
++#
++# CONFIG_CPU_FREQ is not set
++# CONFIG_CPU_IDLE is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++# CONFIG_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_MISC=y
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_SUSPEND is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_MMAP is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_NET_KEY=y
++# CONFIG_NET_KEY_MIGRATE is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_PHONET is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++CONFIG_WIRELESS_OLD_REGULATORY=y
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=16384
++# CONFIG_BLK_DEV_XIP is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MISC_DEVICES is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_NET_ETHERNET is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_IWLWIFI_LEDS is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_DEVKMEM=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++CONFIG_I2C_OMAP=y
++# CONFIG_I2C2_OMAP_BEAGLE is not set
++# CONFIG_I2C_SIMTEC is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_STUB is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_DS1682 is not set
++# CONFIG_AT24 is not set
++# CONFIG_SENSORS_EEPROM is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_PCF8575 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TWL4030_MADC is not set
++# CONFIG_TWL4030_PWRBUTTON is not set
++# CONFIG_TWL4030_POWEROFF is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_LP5521 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++# CONFIG_SPI is not set
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++# CONFIG_DEBUG_GPIO is not set
++# CONFIG_GPIO_SYSFS is not set
++
++#
++# Memory mapped GPIO expanders:
++#
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++CONFIG_GPIO_TWL4030=y
++
++#
++# PCI GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++CONFIG_TWL4030_CORE=y
++# CONFIG_TWL4030_POWER is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_VIDEO_MEDIA is not set
++
++#
++# Multimedia drivers
++#
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=m
++CONFIG_FB_CFB_COPYAREA=m
++CONFIG_FB_CFB_IMAGEBLIT=m
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=4
++CONFIG_FB_OMAP2=m
++# CONFIG_FB_OMAP2_DEBUG is not set
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++CONFIG_FB_OMAP2_NUM_FBS=3
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_GENERIC=m
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++# CONFIG_HID_SUPPORT is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++CONFIG_USB_SUSPEND=y
++CONFIG_USB_OTG=y
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++CONFIG_USB_MON=y
++# CONFIG_USB_WUSB is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HWA_HCD is not set
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SOC=y
++
++#
++# OMAP 343x high speed USB support
++#
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_PERIPHERAL is not set
++CONFIG_USB_MUSB_OTG=y
++CONFIG_USB_GADGET_MUSB_HDRC=y
++CONFIG_USB_MUSB_HDRC_HCD=y
++# CONFIG_MUSB_PIO_ONLY is not set
++CONFIG_USB_INVENTRA_DMA=y
++# CONFIG_USB_TI_CPPI_DMA is not set
++# CONFIG_USB_MUSB_DEBUG is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
++#
++
++#
++# see USB_STORAGE Help for more information
++#
++# CONFIG_USB_STORAGE is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_VST is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_PXA25X is not set
++# CONFIG_USB_GADGET_PXA27X is not set
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_FSL_QE is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++CONFIG_USB_ETH=y
++CONFIG_USB_ETH_RNDIS=y
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_ISP1301_OMAP is not set
++CONFIG_TWL4030_USB=y
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_SDHCI is not set
++CONFIG_MMC_OMAP_HS=y
++# CONFIG_MEMSTICK is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_NEW_LEDS is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++CONFIG_RTC_DRV_TWL4030=y
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++
++#
++# SPI RTC drivers
++#
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_DMADEVICES is not set
++# CONFIG_REGULATOR is not set
++# CONFIG_UIO is not set
++
++#
++# CBUS support
++#
++# CONFIG_CBUS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_FS_XATTR is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QFMT_V1 is not set
++CONFIG_QFMT_V2=y
++CONFIG_QUOTACTL=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_REGISTER_V4 is not set
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++
++#
++# Tracers
++#
++# CONFIG_FUNCTION_TRACER is not set
++# CONFIG_IRQSOFF_TRACER is not set
++# CONFIG_SCHED_TRACER is not set
++# CONFIG_CONTEXT_SWITCH_TRACER is not set
++# CONFIG_BOOT_TRACER is not set
++# CONFIG_STACK_TRACER is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_ERRORS=y
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_LL is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++# CONFIG_CRYPTO_FIPS is not set
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=m
++# CONFIG_CRYPTO_LRW is not set
++CONFIG_CRYPTO_PCBC=m
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++
++#
++# Digest
++#
++# CONFIG_CRYPTO_CRC32C is not set
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++# CONFIG_CRYPTO_AES is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_CRC_CCITT=y
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=y
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index fe97bab..61f0fc9 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -43,6 +43,8 @@
+ #include <mach/gpmc.h>
+ #include <mach/nand.h>
+ #include <mach/mux.h>
++#include <mach/omapfb.h>
++#include <mach/display.h>
+ 
+ #include "twl4030-generic-scripts.h"
+ #include "mmc-twl4030.h"
+@@ -238,15 +240,6 @@ static void __init omap3_beagle_init_irq(void)
+ 	omap_gpio_init();
+ }
+ 
+-static struct platform_device omap3_beagle_lcd_device = {
+-	.name		= "omap3beagle_lcd",
+-	.id		= -1,
+-};
+-
+-static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
+-};
+-
+ static struct gpio_led gpio_leds[] = {
+ 	{
+ 		.name			= "beagleboard::usr0",
+@@ -300,13 +293,94 @@ static struct platform_device keys_gpio = {
+ 	},
+ };
+ 
++/* DSS */
++
++static int beagle_enable_dvi(struct omap_display *display)
++{
++	if (display->hw_config.panel_reset_gpio != -1)
++		gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
++
++	return 0;
++}
++
++static void beagle_disable_dvi(struct omap_display *display)
++{
++	if (display->hw_config.panel_reset_gpio != -1)
++		gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
++}
++
++static struct omap_display_data beagle_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-generic",
++	.u.dpi.data_lines = 24,
++	.panel_reset_gpio = 170,
++	.panel_enable = beagle_enable_dvi,
++	.panel_disable = beagle_disable_dvi,
++};
++
++
++static int beagle_panel_enable_tv(struct omap_display *display)
++{
++#define ENABLE_VDAC_DEDICATED           0x03
++#define ENABLE_VDAC_DEV_GRP             0x20
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEDICATED,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++
++	return 0;
++}
++
++static void beagle_panel_disable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_display_data beagle_display_data_tv = {
++	.type = OMAP_DISPLAY_TYPE_VENC,
++	.name = "tv",
++	.u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++	.panel_enable = beagle_panel_enable_tv,
++	.panel_disable = beagle_panel_disable_tv,
++};
++
++static struct omap_dss_platform_data beagle_dss_data = {
++	.num_displays = 2,
++	.displays = {
++		&beagle_display_data_dvi,
++		&beagle_display_data_tv,
++	}
++};
++
++static struct platform_device beagle_dss_device = {
++	.name          = "omap-dss",
++	.id            = -1,
++	.dev            = {
++		.platform_data = &beagle_dss_data,
++	},
++};
++
++static void __init beagle_display_init(void)
++{
++	int r;
++
++	r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
++	if (r < 0)
++		printk(KERN_ERR "Unable to get DVI reset GPIO\n");
++}
++
+ static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&omap3_beagle_uart_config },
+-	{ OMAP_TAG_LCD,		&omap3_beagle_lcd_config },
+ };
+ 
+ static struct platform_device *omap3_beagle_devices[] __initdata = {
+-	&omap3_beagle_lcd_device,
++	&beagle_dss_device,
+ 	&leds_gpio,
+ 	&keys_gpio,
+ };
+@@ -359,18 +433,17 @@ static void __init omap3_beagle_init(void)
+ 	omap_serial_init();
+ 
+ 	omap_cfg_reg(J25_34XX_GPIO170);
+-	gpio_request(170, "DVI_nPD");
+-	/* REVISIT leave DVI powered down until it's needed ... */
+-	gpio_direction_output(170, true);
+ 
+ 	usb_musb_init();
+ 	usb_ehci_init();
+ 	omap3beagle_flash_init();
++	beagle_display_init();
+ }
+ 
+ static void __init omap3_beagle_map_io(void)
+ {
+ 	omap2_set_globals_343x();
++	omap2_set_sdram_vram(1280 * 1024 * 4 * 3, 0);
+ 	omap2_map_common_io();
+ }
+ 
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0005-DSS-Sharp-LS037V7DW01-LCD-Panel-driver.patch b/recipes/linux/linux-omap-2.6.28/0005-DSS-Sharp-LS037V7DW01-LCD-Panel-driver.patch
new file mode 100644
index 0000000000..57cec272fb
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0005-DSS-Sharp-LS037V7DW01-LCD-Panel-driver.patch
@@ -0,0 +1,156 @@
+From b0d997fcd65c4389e3d4a5e375774e51ebe6186a Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 14 Nov 2008 15:47:19 +0200
+Subject: [PATCH] DSS: Sharp LS037V7DW01 LCD Panel driver
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/Kconfig                   |    7 ++-
+ drivers/video/omap2/Makefile                  |    1 +
+ drivers/video/omap2/panel-sharp-ls037v7dw01.c |  109 +++++++++++++++++++++++++
+ 3 files changed, 116 insertions(+), 1 deletions(-)
+ create mode 100644 drivers/video/omap2/panel-sharp-ls037v7dw01.c
+
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index be00882..b54c955 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -43,5 +43,10 @@ config PANEL_GENERIC
+ 	  Generic panel driver.
+ 	  Used for DVI output for Beagle and OMAP3 SDP.
+ 
+-endmenu
++config PANEL_SHARP_LS037V7DW01
++        tristate "Sharp LS037V7DW01 LCD Panel"
++        depends on OMAP2_DSS
++        help
++          LCD Panel used in TI's SDP3430 and EVM boards
+ 
++endmenu
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index f471a2b..fe6858e 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -2,3 +2,4 @@ obj-$(CONFIG_FB_OMAP2) += omapfb.o
+ omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
+ 
+ obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
++obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
+diff --git a/drivers/video/omap2/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/panel-sharp-ls037v7dw01.c
+new file mode 100644
+index 0000000..7d67b6d
+--- /dev/null
++++ b/drivers/video/omap2/panel-sharp-ls037v7dw01.c
+@@ -0,0 +1,109 @@
++/*
++ * LCD panel driver for Sharp LS037V7DW01
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int sharp_ls_panel_init(struct omap_display *display)
++{
++	return 0;
++}
++
++static void sharp_ls_panel_cleanup(struct omap_display *display)
++{
++}
++
++static int sharp_ls_panel_enable(struct omap_display *display)
++{
++	int r = 0;
++
++	if (display->hw_config.panel_enable)
++		r = display->hw_config.panel_enable(display);
++
++	return r;
++}
++
++static void sharp_ls_panel_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++}
++
++static int sharp_ls_panel_suspend(struct omap_display *display)
++{
++	sharp_ls_panel_disable(display);
++	return 0;
++}
++
++static int sharp_ls_panel_resume(struct omap_display *display)
++{
++	return sharp_ls_panel_enable(display);
++}
++
++static struct omap_panel sharp_ls_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "sharp-ls037v7dw01",
++	.init		= sharp_ls_panel_init,
++	.cleanup	= sharp_ls_panel_cleanup,
++	.enable		= sharp_ls_panel_enable,
++	.disable	= sharp_ls_panel_disable,
++	.suspend	= sharp_ls_panel_suspend,
++	.resume		= sharp_ls_panel_resume,
++	/*.set_mode	= sharp_ls_set_mode, */
++
++	.timings = {
++		.x_res = 480,
++		.y_res = 640,
++
++		.pixel_clock	= 19200,
++
++		.hsw		= 2,
++		.hfp		= 1,
++		.hbp		= 28,
++
++		.vsw		= 1,
++		.vfp		= 1,
++		.vbp		= 1,
++	},
++
++	.acb		= 0x28,
++
++	.config		= OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
++		OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
++
++	.bpp = 16,
++};
++
++
++static int __init sharp_ls_panel_drv_init(void)
++{
++	omap_dss_register_panel(&sharp_ls_panel);
++	return 0;
++}
++
++static void __exit sharp_ls_panel_drv_exit(void)
++{
++	omap_dss_unregister_panel(&sharp_ls_panel);
++}
++
++module_init(sharp_ls_panel_drv_init);
++module_exit(sharp_ls_panel_drv_exit);
++MODULE_LICENSE("GPL");
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0006-DSS-Support-for-OMAP3-SDP-board.patch b/recipes/linux/linux-omap-2.6.28/0006-DSS-Support-for-OMAP3-SDP-board.patch
new file mode 100644
index 0000000000..e73264ebb6
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0006-DSS-Support-for-OMAP3-SDP-board.patch
@@ -0,0 +1,1877 @@
+From 7806a298a80d260473dc488c7cea2a72fe96866f Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 14 Nov 2008 15:47:55 +0200
+Subject: [PATCH] DSS: Support for OMAP3 SDP board
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/configs/dss_omap_3430sdp_defconfig | 1603 +++++++++++++++++++++++++++
+ arch/arm/mach-omap2/board-3430sdp.c         |  215 ++++-
+ 2 files changed, 1809 insertions(+), 9 deletions(-)
+ create mode 100644 arch/arm/configs/dss_omap_3430sdp_defconfig
+
+diff --git a/arch/arm/configs/dss_omap_3430sdp_defconfig b/arch/arm/configs/dss_omap_3430sdp_defconfig
+new file mode 100644
+index 0000000..42d7f5e
+--- /dev/null
++++ b/arch/arm/configs/dss_omap_3430sdp_defconfig
+@@ -0,0 +1,1603 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.28-omap1
++# Wed Jan  7 15:22:34 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_MMU=y
++# CONFIG_NO_IOPORT is not set
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_LATENCYTOP_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_CGROUPS is not set
++CONFIG_GROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_RT_GROUP_SCHED is not set
++CONFIG_USER_SCHED=y
++# CONFIG_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
++# CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_EMBEDDED=y
++CONFIG_UID16=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++CONFIG_KALLSYMS_EXTRA_PASS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_COMPAT_BRK=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++CONFIG_CLASSIC_RCU=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++CONFIG_ARCH_OMAP=y
++# CONFIG_ARCH_MSM is not set
++
++#
++# TI OMAP Implementations
++#
++CONFIG_ARCH_OMAP_OTG=y
++# CONFIG_ARCH_OMAP1 is not set
++# CONFIG_ARCH_OMAP2 is not set
++CONFIG_ARCH_OMAP3=y
++
++#
++# OMAP Feature Selections
++#
++# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
++# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
++CONFIG_OMAP_SMARTREFLEX=y
++# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
++CONFIG_OMAP_RESET_CLOCKS=y
++CONFIG_OMAP_BOOT_TAG=y
++CONFIG_OMAP_BOOT_REASON=y
++# CONFIG_OMAP_COMPONENT_VERSION is not set
++# CONFIG_OMAP_GPIO_SWITCH is not set
++CONFIG_OMAP_MUX=y
++CONFIG_OMAP_MUX_DEBUG=y
++CONFIG_OMAP_MUX_WARNINGS=y
++# CONFIG_OMAP_MCBSP is not set
++# CONFIG_OMAP_MMU_FWK is not set
++# CONFIG_OMAP_MBOX_FWK is not set
++# CONFIG_OMAP_MPU_TIMER is not set
++CONFIG_OMAP_32K_TIMER=y
++CONFIG_OMAP_32K_TIMER_HZ=128
++CONFIG_OMAP_DM_TIMER=y
++CONFIG_OMAP_LL_DEBUG_UART1=y
++# CONFIG_OMAP_LL_DEBUG_UART2 is not set
++# CONFIG_OMAP_LL_DEBUG_UART3 is not set
++CONFIG_OMAP_SERIAL_WAKE=y
++CONFIG_OMAP2_DSS=m
++CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
++CONFIG_ARCH_OMAP34XX=y
++CONFIG_ARCH_OMAP3430=y
++
++#
++# OMAP Board Type
++#
++# CONFIG_MACH_OMAP_LDP is not set
++CONFIG_MACH_OMAP_3430SDP=y
++# CONFIG_MACH_OMAP3EVM is not set
++# CONFIG_MACH_OMAP3_BEAGLE is not set
++# CONFIG_MACH_OVERO is not set
++# CONFIG_MACH_OMAP3_PANDORA is not set
++CONFIG_OMAP_TICK_GPTIMER=1
++
++#
++# Boot options
++#
++
++#
++# Power management
++#
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_IFAR=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_HAS_TLS_REG=y
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=128
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++CONFIG_ARCH_FLATMEM_HAS_HOLES=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++CONFIG_UNEVICTABLE_LRU=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# CPU Power Management
++#
++# CONFIG_CPU_FREQ is not set
++# CONFIG_CPU_IDLE is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++# CONFIG_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_MISC=y
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_APM_EMULATION is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_MMAP is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_NET_KEY=y
++# CONFIG_NET_KEY_MIGRATE is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_PHONET is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++CONFIG_WIRELESS_OLD_REGULATORY=y
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++CONFIG_MTD_CONCAT=y
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++# CONFIG_MTD_CFI_AMDSTD is not set
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++CONFIG_MTD_OMAP_NOR=y
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++CONFIG_MTD_NAND_ECC_SMC=y
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++CONFIG_MTD_ONENAND=y
++CONFIG_MTD_ONENAND_VERIFY_WRITE=y
++# CONFIG_MTD_ONENAND_GENERIC is not set
++CONFIG_MTD_ONENAND_OMAP2=y
++# CONFIG_MTD_ONENAND_OTP is not set
++# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
++# CONFIG_MTD_ONENAND_SIM is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=16384
++# CONFIG_BLK_DEV_XIP is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_OMAP_STI is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_C2PORT is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++CONFIG_SMC91X=y
++# CONFIG_DM9000 is not set
++# CONFIG_ENC28J60 is not set
++# CONFIG_SMC911X is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
++# CONFIG_B44 is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_IWLWIFI_LEDS is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ATKBD is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++CONFIG_KEYBOARD_TWL4030=y
++# CONFIG_KEYBOARD_LM8323 is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ADS7846=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_INEXIO is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_TSC2005 is not set
++# CONFIG_TOUCHSCREEN_TSC210X is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_DEVKMEM=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++CONFIG_I2C_OMAP=y
++# CONFIG_I2C_SIMTEC is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_STUB is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_DS1682 is not set
++# CONFIG_AT24 is not set
++# CONFIG_SENSORS_EEPROM is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_PCF8575 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TWL4030_MADC is not set
++# CONFIG_TWL4030_PWRBUTTON is not set
++# CONFIG_TWL4030_POWEROFF is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_LP5521 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_BITBANG is not set
++CONFIG_SPI_OMAP24XX=y
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_TSC210X is not set
++# CONFIG_SPI_TSC2301 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++# CONFIG_DEBUG_GPIO is not set
++# CONFIG_GPIO_SYSFS is not set
++
++#
++# Memory mapped GPIO expanders:
++#
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++CONFIG_GPIO_TWL4030=y
++
++#
++# PCI GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MCP23S08 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_NOWAYOUT=y
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_OMAP_WATCHDOG=y
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++CONFIG_TWL4030_CORE=y
++# CONFIG_TWL4030_POWER is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_VIDEO_MEDIA is not set
++
++#
++# Multimedia drivers
++#
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++CONFIG_VIDEO_OUTPUT_CONTROL=m
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=m
++CONFIG_FB_CFB_COPYAREA=m
++CONFIG_FB_CFB_IMAGEBLIT=m
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_OMAP_LCD_VGA is not set
++CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
++CONFIG_FB_OMAP2=m
++CONFIG_FB_OMAP2_DEBUG=y
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++CONFIG_FB_OMAP2_NUM_FBS=3
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_GENERIC=m
++CONFIG_PANEL_SHARP_LS037V7DW01=m
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# Special HID drivers
++#
++CONFIG_HID_COMPAT=y
++CONFIG_HID_A4TECH=y
++CONFIG_HID_APPLE=y
++CONFIG_HID_BELKIN=y
++CONFIG_HID_BRIGHT=y
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++CONFIG_HID_CYPRESS=y
++CONFIG_HID_DELL=y
++CONFIG_HID_EZKEY=y
++CONFIG_HID_GYRATION=y
++CONFIG_HID_LOGITECH=y
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++CONFIG_HID_PANTHERLORD=y
++# CONFIG_PANTHERLORD_FF is not set
++CONFIG_HID_PETALYNX=y
++CONFIG_HID_SAMSUNG=y
++CONFIG_HID_SONY=y
++CONFIG_HID_SUNPLUS=y
++# CONFIG_THRUSTMASTER_FF is not set
++# CONFIG_ZEROPLUS_FF is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB=y
++CONFIG_USB_DEBUG=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_DEVICE_CLASS is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++CONFIG_USB_SUSPEND=y
++CONFIG_USB_OTG=y
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++CONFIG_USB_MON=y
++# CONFIG_USB_WUSB is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_EHCI_HCD=m
++CONFIG_OMAP_EHCI_PHY_MODE=y
++# CONFIG_OMAP_EHCI_TLL_MODE is not set
++# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
++# CONFIG_USB_EHCI_TT_NEWSCHED is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HWA_HCD is not set
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SOC=y
++
++#
++# OMAP 343x high speed USB support
++#
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_PERIPHERAL is not set
++CONFIG_USB_MUSB_OTG=y
++CONFIG_USB_GADGET_MUSB_HDRC=y
++CONFIG_USB_MUSB_HDRC_HCD=y
++# CONFIG_MUSB_PIO_ONLY is not set
++CONFIG_USB_INVENTRA_DMA=y
++# CONFIG_USB_TI_CPPI_DMA is not set
++# CONFIG_USB_MUSB_DEBUG is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
++#
++
++#
++# see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_DEBUG=y
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_DPCM is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_SISUSBVGA is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++CONFIG_USB_TEST=y
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_VST is not set
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DEBUG=y
++CONFIG_USB_GADGET_DEBUG_FILES=y
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_PXA25X is not set
++# CONFIG_USB_GADGET_PXA27X is not set
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_FSL_QE is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++CONFIG_USB_ZERO=m
++# CONFIG_USB_ZERO_HNPTEST is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_ISP1301_OMAP is not set
++CONFIG_TWL4030_USB=y
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_SDHCI is not set
++CONFIG_MMC_OMAP_HS=m
++# CONFIG_MMC_SPI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_NEW_LEDS is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++CONFIG_RTC_DRV_TWL4030=y
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_DS3234 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_DMADEVICES is not set
++# CONFIG_REGULATOR is not set
++# CONFIG_UIO is not set
++
++#
++# CBUS support
++#
++# CONFIG_CBUS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_FS_XATTR is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++# CONFIG_QFMT_V1 is not set
++CONFIG_QFMT_V2=y
++CONFIG_QUOTACTL=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_JFFS2_CMODE_NONE is not set
++CONFIG_JFFS2_CMODE_PRIORITY=y
++# CONFIG_JFFS2_CMODE_SIZE is not set
++# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_REGISTER_V4 is not set
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++
++#
++# Tracers
++#
++# CONFIG_FUNCTION_TRACER is not set
++# CONFIG_IRQSOFF_TRACER is not set
++# CONFIG_SCHED_TRACER is not set
++# CONFIG_CONTEXT_SWITCH_TRACER is not set
++# CONFIG_BOOT_TRACER is not set
++# CONFIG_STACK_TRACER is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_ERRORS=y
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_LL is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++# CONFIG_CRYPTO_FIPS is not set
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=m
++# CONFIG_CRYPTO_LRW is not set
++CONFIG_CRYPTO_PCBC=m
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++
++#
++# Digest
++#
++# CONFIG_CRYPTO_CRC32C is not set
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++# CONFIG_CRYPTO_AES is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_CRC_CCITT=y
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=y
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index ade186b..529322f 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -39,6 +39,7 @@
+ #include <mach/keypad.h>
+ #include <mach/dma.h>
+ #include <mach/gpmc.h>
++#include <mach/display.h>
+ 
+ #include <asm/io.h>
+ #include <asm/delay.h>
+@@ -238,14 +239,214 @@ static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
+ 	},
+ };
+ 
+-static struct platform_device sdp3430_lcd_device = {
+-	.name		= "sdp2430_lcd",
+-	.id		= -1,
++
++#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO	91
++#define SDP2430_LCD_PANEL_ENABLE_GPIO		154
++#if 0
++#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO	24
++#define SDP3430_LCD_PANEL_ENABLE_GPIO		28
++#else
++#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO	8
++#define SDP3430_LCD_PANEL_ENABLE_GPIO		5
++#endif
++
++#define PM_RECEIVER             TWL4030_MODULE_PM_RECEIVER
++#define ENABLE_VAUX2_DEDICATED  0x09
++#define ENABLE_VAUX2_DEV_GRP    0x20
++#define ENABLE_VAUX3_DEDICATED	0x03
++#define ENABLE_VAUX3_DEV_GRP	0x20
++
++#define ENABLE_VPLL2_DEDICATED	0x05
++#define ENABLE_VPLL2_DEV_GRP	0xE0
++#define TWL4030_VPLL2_DEV_GRP	0x33
++#define TWL4030_VPLL2_DEDICATED	0x36
++
++#define t2_out(c, r, v) twl4030_i2c_write_u8(c, r, v)
++
++static unsigned backlight_gpio;
++static unsigned enable_gpio;
++static int lcd_enabled;
++static int dvi_enabled;
++
++static void __init sdp3430_display_init(void)
++{
++	int r;
++
++	enable_gpio    = SDP3430_LCD_PANEL_ENABLE_GPIO;
++	backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
++
++	r = gpio_request(enable_gpio, "LCD reset");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD reset GPIO\n");
++		goto err0;
++	}
++
++	r = gpio_request(backlight_gpio, "LCD Backlight");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD backlight GPIO\n");
++		goto err1;
++	}
++
++	gpio_direction_output(enable_gpio, 0);
++	gpio_direction_output(backlight_gpio, 0);
++
++	return;
++err1:
++	gpio_free(enable_gpio);
++err0:
++	return;
++}
++
++
++static int sdp3430_panel_enable_lcd(struct omap_display *display)
++{
++	u8 ded_val, ded_reg;
++	u8 grp_val, grp_reg;
++
++	if (dvi_enabled) {
++		printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++		return -EINVAL;
++	}
++
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		t2_out(PM_RECEIVER, ENABLE_VPLL2_DEDICATED,
++				TWL4030_VPLL2_DEDICATED);
++		t2_out(PM_RECEIVER, ENABLE_VPLL2_DEV_GRP,
++				TWL4030_VPLL2_DEV_GRP);
++	}
++
++	ded_reg = TWL4030_VAUX3_DEDICATED;
++	ded_val = ENABLE_VAUX3_DEDICATED;
++	grp_reg = TWL4030_VAUX3_DEV_GRP;
++	grp_val = ENABLE_VAUX3_DEV_GRP;
++
++	gpio_direction_output(enable_gpio, 1);
++	gpio_direction_output(backlight_gpio, 1);
++
++	if (0 != t2_out(PM_RECEIVER, ded_val, ded_reg))
++		return -EIO;
++	if (0 != t2_out(PM_RECEIVER, grp_val, grp_reg))
++		return -EIO;
++
++	lcd_enabled = 1;
++
++	return 0;
++}
++
++static void sdp3430_panel_disable_lcd(struct omap_display *display)
++{
++	lcd_enabled = 0;
++
++	gpio_direction_output(enable_gpio, 0);
++	gpio_direction_output(backlight_gpio, 0);
++
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEDICATED);
++		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEV_GRP);
++		mdelay(4);
++	}
++}
++
++static struct omap_display_data sdp3430_display_data = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "lcd",
++	.panel_name = "sharp-ls037v7dw01",
++	.u.dpi.data_lines = 16,
++	.panel_enable = sdp3430_panel_enable_lcd,
++	.panel_disable = sdp3430_panel_disable_lcd,
++};
++
++static int sdp3430_panel_enable_dvi(struct omap_display *display)
++{
++	if (lcd_enabled) {
++		printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++		return -EINVAL;
++	}
++
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		t2_out(PM_RECEIVER, ENABLE_VPLL2_DEDICATED,
++				TWL4030_VPLL2_DEDICATED);
++		t2_out(PM_RECEIVER, ENABLE_VPLL2_DEV_GRP,
++				TWL4030_VPLL2_DEV_GRP);
++	}
++
++	dvi_enabled = 1;
++
++	return 0;
++}
++
++static void sdp3430_panel_disable_dvi(struct omap_display *display)
++{
++	dvi_enabled = 0;
++
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEDICATED);
++		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEV_GRP);
++		mdelay(4);
++	}
++}
++
++
++static struct omap_display_data sdp3430_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-generic",
++	.u.dpi.data_lines = 24,
++	.panel_enable = sdp3430_panel_enable_dvi,
++	.panel_disable = sdp3430_panel_disable_dvi,
+ };
+ 
++static int sdp3430_panel_enable_tv(struct omap_display *display)
++{
++#define ENABLE_VDAC_DEDICATED           0x03
++#define ENABLE_VDAC_DEV_GRP             0x20
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEDICATED,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++
++	return 0;
++}
++
++static void sdp3430_panel_disable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_display_data sdp3430_display_data_tv = {
++	.type = OMAP_DISPLAY_TYPE_VENC,
++	.name = "tv",
++	.u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++	.panel_enable = sdp3430_panel_enable_tv,
++	.panel_disable = sdp3430_panel_disable_tv,
++};
++
++static struct omap_dss_platform_data sdp3430_dss_data = {
++	.num_displays = 3,
++	.displays = {
++		&sdp3430_display_data,
++		&sdp3430_display_data_dvi,
++		&sdp3430_display_data_tv,
++	}
++};
++
++static struct platform_device sdp3430_dss_device = {
++	.name          = "omap-dss",
++	.id            = -1,
++	.dev            = {
++		.platform_data = &sdp3430_dss_data,
++	},
++};
++
++
+ static struct platform_device *sdp3430_devices[] __initdata = {
+ 	&sdp3430_smc91x_device,
+-	&sdp3430_lcd_device,
++	&sdp3430_dss_device,
+ };
+ 
+ static inline void __init sdp3430_init_smc91x(void)
+@@ -292,13 +493,8 @@ static struct omap_uart_config sdp3430_uart_config __initdata = {
+ 	.enabled_uarts	= ((1 << 0) | (1 << 1) | (1 << 2)),
+ };
+ 
+-static struct omap_lcd_config sdp3430_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
+-};
+-
+ static struct omap_board_config_kernel sdp3430_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&sdp3430_uart_config },
+-	{ OMAP_TAG_LCD,		&sdp3430_lcd_config },
+ };
+ 
+ static int sdp3430_batt_table[] = {
+@@ -481,6 +677,7 @@ static void __init omap_3430sdp_init(void)
+ 	usb_musb_init();
+ 	usb_ehci_init();
+ 	twl4030_mmc_init(mmc);
++	sdp3430_display_init();
+ }
+ 
+ static void __init omap_3430sdp_map_io(void)
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0007-DSS-Support-for-OMAP3-EVM-board.patch b/recipes/linux/linux-omap-2.6.28/0007-DSS-Support-for-OMAP3-EVM-board.patch
new file mode 100644
index 0000000000..fb12ea4c03
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0007-DSS-Support-for-OMAP3-EVM-board.patch
@@ -0,0 +1,255 @@
+From 98b4c02ad7229074414bc51bae1452fe93ab5111 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Mon, 5 Jan 2009 14:57:32 +0200
+Subject: [PATCH] DSS: Support for OMAP3 EVM board
+
+Coded by Vaibhav Hiremath <hvaibhav@ti.com>
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c |  203 ++++++++++++++++++++++++++++++++-
+ 1 files changed, 196 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index e4e60e2..e7ec9e6 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -36,6 +36,7 @@
+ #include <mach/usb-ehci.h>
+ #include <mach/common.h>
+ #include <mach/mcspi.h>
++#include <mach/display.h>
+ 
+ #include "sdram-micron-mt46h32m32lf-6.h"
+ #include "twl4030-generic-scripts.h"
+@@ -160,13 +161,201 @@ static int __init omap3_evm_i2c_init(void)
+ 	return 0;
+ }
+ 
+-static struct platform_device omap3_evm_lcd_device = {
+-	.name		= "omap3evm_lcd",
+-	.id		= -1,
++#define LCD_PANEL_LR		2
++#define LCD_PANEL_UD		3
++#define LCD_PANEL_INI		152
++#define LCD_PANEL_ENABLE_GPIO	153
++#define LCD_PANEL_QVGA		154
++#define LCD_PANEL_RESB		155
++
++#define ENABLE_VDAC_DEDICATED	0x03
++#define ENABLE_VDAC_DEV_GRP	0x20
++#define ENABLE_VPLL2_DEDICATED	0x05
++#define ENABLE_VPLL2_DEV_GRP	0xE0
++
++#define TWL4030_GPIODATA_IN3	0x03
++#define TWL4030_GPIODATA_DIR3	0x06
++#define TWL4030_VPLL2_DEV_GRP	0x33
++#define TWL4030_VPLL2_DEDICATED	0x36
++
++static int lcd_enabled;
++static int dvi_enabled;
++
++static void __init omap3_evm_display_init(void)
++{
++	int r;
++	r = gpio_request(LCD_PANEL_LR, "lcd_panel_lr");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_LR\n");
++		return;
++	}
++	r = gpio_request(LCD_PANEL_UD, "lcd_panel_ud");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_UD\n");
++		goto err_1;
++	}
++
++	r = gpio_request(LCD_PANEL_INI, "lcd_panel_ini");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_INI\n");
++		goto err_2;
++	}
++	r = gpio_request(LCD_PANEL_RESB, "lcd_panel_resb");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_RESB\n");
++		goto err_3;
++	}
++	r = gpio_request(LCD_PANEL_QVGA, "lcd_panel_qvga");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_QVGA\n");
++		goto err_4;
++	}
++
++	gpio_direction_output(LCD_PANEL_LR, 0);
++	gpio_direction_output(LCD_PANEL_UD, 0);
++	gpio_direction_output(LCD_PANEL_INI, 0);
++	gpio_direction_output(LCD_PANEL_RESB, 0);
++	gpio_direction_output(LCD_PANEL_QVGA, 0);
++
++#define TWL_LED_LEDEN           0x00
++#define TWL_PWMA_PWMAON         0x00
++#define TWL_PWMA_PWMAOFF        0x01
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
++
++	gpio_direction_output(LCD_PANEL_RESB, 1);
++	gpio_direction_output(LCD_PANEL_INI, 1);
++	gpio_direction_output(LCD_PANEL_QVGA, 0);
++	gpio_direction_output(LCD_PANEL_LR, 1);
++	gpio_direction_output(LCD_PANEL_UD, 1);
++
++	return;
++
++err_4:
++	gpio_free(LCD_PANEL_RESB);
++err_3:
++	gpio_free(LCD_PANEL_INI);
++err_2:
++	gpio_free(LCD_PANEL_UD);
++err_1:
++	gpio_free(LCD_PANEL_LR);
++
++}
++
++static int omap3_evm_panel_enable_lcd(struct omap_display *display)
++{
++	if (dvi_enabled) {
++		printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++		return -EINVAL;
++	}
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
++	}
++	gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
++	lcd_enabled = 1;
++	return 0;
++}
++
++static void omap3_evm_panel_disable_lcd(struct omap_display *display)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEV_GRP);
++	}
++	gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
++	lcd_enabled = 0;
++}
++
++static struct omap_display_data omap3_evm_display_data = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "lcd",
++	.panel_name = "sharp-ls037v7dw01",
++	.u.dpi.data_lines = 18,
++	.panel_enable = omap3_evm_panel_enable_lcd,
++	.panel_disable = omap3_evm_panel_disable_lcd,
+ };
+ 
+-static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
++static int omap3_evm_panel_enable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEDICATED, TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++	return 0;
++}
++
++static void omap3_evm_panel_disable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_display_data omap3_evm_display_data_tv = {
++	.type = OMAP_DISPLAY_TYPE_VENC,
++	.name = "tv",
++	.u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++	.panel_enable = omap3_evm_panel_enable_tv,
++	.panel_disable = omap3_evm_panel_disable_tv,
++};
++
++
++static int omap3_evm_panel_enable_dvi(struct omap_display *display)
++{
++	if (lcd_enabled) {
++		printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++		return -EINVAL;
++	}
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++			TWL4030_GPIODATA_IN3);
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++			TWL4030_GPIODATA_DIR3);
++	dvi_enabled = 1;
++
++	return 0;
++}
++
++static void omap3_evm_panel_disable_dvi(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++			TWL4030_GPIODATA_IN3);
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++			TWL4030_GPIODATA_DIR3);
++	dvi_enabled = 0;
++}
++
++
++static struct omap_display_data omap3_evm_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-generic",
++	.u.dpi.data_lines = 24,
++	.panel_enable = omap3_evm_panel_enable_dvi,
++	.panel_disable = omap3_evm_panel_disable_dvi,
++};
++
++static struct omap_dss_platform_data omap3_evm_dss_data = {
++	.num_displays = 3,
++	.displays = {
++		&omap3_evm_display_data,
++		&omap3_evm_display_data_dvi,
++		&omap3_evm_display_data_tv,
++	}
++};
++static struct platform_device omap3_evm_dss_device = {
++	.name		= "omap-dss",
++	.id		= -1,
++	.dev            = {
++		.platform_data = &omap3_evm_dss_data,
++	},
+ };
+ 
+ static void ads7846_dev_init(void)
+@@ -225,11 +414,10 @@ static void __init omap3_evm_init_irq(void)
+ 
+ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&omap3_evm_uart_config },
+-	{ OMAP_TAG_LCD,		&omap3_evm_lcd_config },
+ };
+ 
+ static struct platform_device *omap3_evm_devices[] __initdata = {
+-	&omap3_evm_lcd_device,
++	&omap3_evm_dss_device,
+ 	&omap3evm_smc911x_device,
+ };
+ 
+@@ -260,6 +448,7 @@ static void __init omap3_evm_init(void)
+ 	usb_ehci_init();
+ 	omap3evm_flash_init();
+ 	ads7846_dev_init();
++	omap3_evm_display_init();
+ }
+ 
+ static void __init omap3_evm_map_io(void)
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0008-DSS-Hacked-N810-support.patch b/recipes/linux/linux-omap-2.6.28/0008-DSS-Hacked-N810-support.patch
new file mode 100644
index 0000000000..e2f21699b9
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0008-DSS-Hacked-N810-support.patch
@@ -0,0 +1,1076 @@
+From a36dfe9ce6faa6a13bb82b3039856d8aa1528dc2 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 18 Dec 2008 15:37:42 +0200
+Subject: [PATCH] DSS: Hacked N810 support
+
+---
+ arch/arm/mach-omap2/board-n800.c    |  214 ++++++++++++++---
+ drivers/video/omap2/Kconfig         |   10 +
+ drivers/video/omap2/Makefile        |    3 +
+ drivers/video/omap2/ctrl-blizzard.c |  279 ++++++++++++++++++++++
+ drivers/video/omap2/panel-n800.c    |  437 +++++++++++++++++++++++++++++++++++
+ 5 files changed, 905 insertions(+), 38 deletions(-)
+ create mode 100644 drivers/video/omap2/ctrl-blizzard.c
+ create mode 100644 drivers/video/omap2/panel-n800.c
+
+diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
+index b38b295..ffa5aad 100644
+--- a/arch/arm/mach-omap2/board-n800.c
++++ b/arch/arm/mach-omap2/board-n800.c
+@@ -40,6 +40,7 @@
+ #include <mach/gpio-switch.h>
+ #include <mach/omapfb.h>
+ #include <mach/blizzard.h>
++#include <mach/display.h>
+ 
+ #include <../drivers/cbus/tahvo.h>
+ #include <../drivers/media/video/tcm825x.h>
+@@ -156,23 +157,175 @@ static struct omap_uart_config n800_uart_config __initdata = {
+ 
+ #include "../../../drivers/cbus/retu.h"
+ 
+-static struct omap_fbmem_config n800_fbmem0_config __initdata = {
+-	.size = 752 * 1024,
++static struct omap_tmp105_config n800_tmp105_config __initdata = {
++	.tmp105_irq_pin = 125,
++	.set_power = n800_tmp105_set_power,
+ };
+ 
+-static struct omap_fbmem_config n800_fbmem1_config __initdata = {
+-	.size = 752 * 1024,
+-};
+ 
+-static struct omap_fbmem_config n800_fbmem2_config __initdata = {
+-	.size = 752 * 1024,
++
++
++/* DISPLAY */
++static struct {
++	struct clk *sys_ck;
++} blizzard;
++
++static int blizzard_get_clocks(void)
++{
++	blizzard.sys_ck = clk_get(0, "osc_ck");
++	if (IS_ERR(blizzard.sys_ck)) {
++		printk(KERN_ERR "can't get Blizzard clock\n");
++		return PTR_ERR(blizzard.sys_ck);
++	}
++	return 0;
++}
++
++static unsigned long blizzard_get_clock_rate(void)
++{
++	return clk_get_rate(blizzard.sys_ck);
++}
++
++static int n800_pn800_enable(struct omap_display *display)
++{
++	if (display->hw_config.panel_reset_gpio != -1) {
++		printk("enabling panel gpio\n");
++		gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
++	}
++
++	return 0;
++}
++
++static void n800_pn800_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_reset_gpio != -1) {
++		printk("disabling panel gpio\n");
++		gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
++		msleep(120);
++	}
++}
++
++static int n800_blizzard_enable(struct omap_display *display)
++{
++	printk("enabling bliz powers\n");
++
++	/* Vcore to 1.475V */
++	tahvo_set_clear_reg_bits(0x07, 0, 0xf);
++	msleep(10);
++
++	clk_enable(blizzard.sys_ck);
++
++	if (display->hw_config.ctrl_reset_gpio != -1)
++		gpio_direction_output(display->hw_config.ctrl_reset_gpio, 1);
++
++	printk("osc_ck %lu\n", blizzard_get_clock_rate());
++
++	return 0;
++}
++
++static void n800_blizzard_disable(struct omap_display *display)
++{
++	printk("disabling bliz powers\n");
++
++	if (display->hw_config.ctrl_reset_gpio != -1)
++		gpio_direction_output(display->hw_config.ctrl_reset_gpio, 0);
++
++	clk_disable(blizzard.sys_ck);
++
++	/* Vcore to 1.005V */
++	tahvo_set_clear_reg_bits(0x07, 0xf, 0);
++}
++
++static int n800_set_backlight_level(struct omap_display *display, int level)
++{
++	return 0;
++}
++
++static struct omap_display_data n800_dsi_display_data = {
++	.type = OMAP_DISPLAY_TYPE_DBI,
++	.name = "lcd",
++	.ctrl_name = "ctrl-blizzard",
++	.panel_name = "panel-pn800",
++	.panel_reset_gpio = -1,
++	.ctrl_reset_gpio = N800_BLIZZARD_POWERDOWN_GPIO,
++	.panel_enable = n800_pn800_enable,
++	.panel_disable = n800_pn800_disable,
++	.ctrl_enable = n800_blizzard_enable,
++	.ctrl_disable = n800_blizzard_disable,
++	.set_backlight = n800_set_backlight_level,
++	.u.rfbi = {
++		.channel = 0,
++		/* 8 for cmd mode, 16 for pixel data. ctrl-blizzard handles switching */
++		.data_lines = 8,
++	},
++	.priv = 0, // XXX used for panel datalines
++};
++static struct omap_dss_platform_data n800_dss_data = {
++	.num_displays = 1,
++	.displays = {
++		&n800_dsi_display_data,
++	},
+ };
+ 
+-static struct omap_tmp105_config n800_tmp105_config __initdata = {
+-	.tmp105_irq_pin = 125,
+-	.set_power = n800_tmp105_set_power,
++static struct platform_device n800_dss_device = {
++	.name          = "omap-dss",
++	.id            = -1,
++	.dev            = {
++		.platform_data = &n800_dss_data,
++	},
+ };
+ 
++static void __init n800_display_init(void)
++{
++	int r;
++	const struct omap_lcd_config *conf;
++
++	conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
++	if (conf != NULL) {
++		n800_dsi_display_data.panel_reset_gpio = conf->nreset_gpio;
++		n800_dsi_display_data.priv = (void*)(u32)conf->data_lines; // XXX
++		//printk("\n\nTULI %d\n\n", conf->data_lines);
++	} else {
++		printk("\n\nEI TULLU MIOTÄÄÄ\n\n");
++	}
++
++	blizzard_get_clocks();
++	clk_enable(blizzard.sys_ck); // XXX always enable
++
++	//omapfb_set_ctrl_platform_data(&n800_blizzard_data);
++	//
++	if (n800_dsi_display_data.ctrl_reset_gpio != -1) {
++		r = gpio_request(n800_dsi_display_data.ctrl_reset_gpio,
++				"Blizzard pd");
++		if (r < 0) {
++			n800_dsi_display_data.ctrl_reset_gpio = -1;
++			printk(KERN_ERR "Unable to get Blizzard GPIO\n");
++		} else {
++			gpio_direction_output(n800_dsi_display_data.ctrl_reset_gpio,
++					1);
++			// XXX always enable
++		}
++	}
++
++	if (n800_dsi_display_data.panel_reset_gpio != -1) {
++		r = gpio_request(n800_dsi_display_data.panel_reset_gpio,
++				"panel reset");
++		if (r < 0) {
++			n800_dsi_display_data.panel_reset_gpio = -1;
++			printk(KERN_ERR "Unable to get pn800 GPIO\n");
++		} else {
++			gpio_direction_output(n800_dsi_display_data.panel_reset_gpio,
++					1);
++			// XXX always enable
++		}
++	}
++}
++
++/* DISPLAY END */
++
++
++
++
++
+ static void mipid_shutdown(struct mipid_platform_data *pdata)
+ {
+ 	if (pdata->nreset_gpio != -1) {
+@@ -186,6 +339,7 @@ static struct mipid_platform_data n800_mipid_platform_data = {
+ 	.shutdown = mipid_shutdown,
+ };
+ 
++#if 0
+ static void __init mipid_dev_init(void)
+ {
+ 	const struct omap_lcd_config *conf;
+@@ -196,26 +350,9 @@ static void __init mipid_dev_init(void)
+ 		n800_mipid_platform_data.data_lines = conf->data_lines;
+ 	}
+ }
++#endif
+ 
+-static struct {
+-	struct clk *sys_ck;
+-} blizzard;
+-
+-static int blizzard_get_clocks(void)
+-{
+-	blizzard.sys_ck = clk_get(0, "osc_ck");
+-	if (IS_ERR(blizzard.sys_ck)) {
+-		printk(KERN_ERR "can't get Blizzard clock\n");
+-		return PTR_ERR(blizzard.sys_ck);
+-	}
+-	return 0;
+-}
+-
+-static unsigned long blizzard_get_clock_rate(struct device *dev)
+-{
+-	return clk_get_rate(blizzard.sys_ck);
+-}
+-
++#if 0
+ static void blizzard_enable_clocks(int enable)
+ {
+ 	if (enable)
+@@ -260,14 +397,12 @@ static void __init blizzard_dev_init(void)
+ 	gpio_direction_output(N800_BLIZZARD_POWERDOWN_GPIO, 1);
+ 
+ 	blizzard_get_clocks();
+-	omapfb_set_ctrl_platform_data(&n800_blizzard_data);
++	//omapfb_set_ctrl_platform_data(&n800_blizzard_data);
+ }
++#endif
+ 
+ static struct omap_board_config_kernel n800_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	                &n800_uart_config },
+-	{ OMAP_TAG_FBMEM,			&n800_fbmem0_config },
+-	{ OMAP_TAG_FBMEM,			&n800_fbmem1_config },
+-	{ OMAP_TAG_FBMEM,			&n800_fbmem2_config },
+ 	{ OMAP_TAG_TMP105,			&n800_tmp105_config },
+ };
+ 
+@@ -374,7 +509,7 @@ static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
+ 
+ static struct spi_board_info n800_spi_board_info[] __initdata = {
+ 	{
+-		.modalias	= "lcd_mipid",
++		.modalias	= "panel-n800",
+ 		.bus_num	= 1,
+ 		.chip_select	= 1,
+ 		.max_speed_hz	= 4000000,
+@@ -399,7 +534,7 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
+ 
+ static struct spi_board_info n810_spi_board_info[] __initdata = {
+ 	{
+-		.modalias	 = "lcd_mipid",
++		.modalias	 = "panel-n800",
+ 		.bus_num	 = 1,
+ 		.chip_select	 = 1,
+ 		.max_speed_hz	 = 4000000,
+@@ -567,6 +702,7 @@ static struct platform_device *n800_devices[] __initdata = {
+ #if defined(CONFIG_CBUS_RETU) && defined(CONFIG_LEDS_OMAP_PWM)
+ 	&n800_keypad_led_device,
+ #endif
++	&n800_dss_device,
+ };
+ 
+ #ifdef CONFIG_MENELAUS
+@@ -689,9 +825,10 @@ void __init nokia_n800_common_init(void)
+ 	if (machine_is_nokia_n810())
+ 		i2c_register_board_info(2, n810_i2c_board_info_2,
+ 			ARRAY_SIZE(n810_i2c_board_info_2));
+-		
+-	mipid_dev_init();
+-	blizzard_dev_init();
++
++	//mipid_dev_init();
++	//blizzard_dev_init();
++	n800_display_init();
+ }
+ 
+ static void __init nokia_n800_init(void)
+@@ -712,6 +849,7 @@ void __init nokia_n800_map_io(void)
+ 	omap_board_config_size = ARRAY_SIZE(n800_config);
+ 
+ 	omap2_set_globals_242x();
++	omap2_set_sdram_vram(800 * 480 * 2 * 3, 0);
+ 	omap2_map_common_io();
+ }
+ 
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index b54c955..4e9211e 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -49,4 +49,14 @@ config PANEL_SHARP_LS037V7DW01
+         help
+           LCD Panel used in TI's SDP3430 and EVM boards
+ 
++config PANEL_N800
++        tristate "panel n800"
++        help
++          N800 LCD
++
++config CTRL_BLIZZARD
++        tristate "blizzard ctrl"
++        help
++          Blizzard Ctrl
++
+ endmenu
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index fe6858e..7727f9c 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -3,3 +3,6 @@ omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
+ 
+ obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
+ obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
++
++obj-$(CONFIG_CTRL_BLIZZARD) += ctrl-blizzard.o
++obj-$(CONFIG_PANEL_N800) += panel-n800.o
+diff --git a/drivers/video/omap2/ctrl-blizzard.c b/drivers/video/omap2/ctrl-blizzard.c
+new file mode 100644
+index 0000000..e1e5569
+--- /dev/null
++++ b/drivers/video/omap2/ctrl-blizzard.c
+@@ -0,0 +1,279 @@
++
++//#define DEBUG
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++
++#include <mach/display.h>
++#include <mach/dma.h>
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "Blizzard: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define BLIZZARD_REV_CODE			0x00
++#define BLIZZARD_CONFIG				0x02
++#define BLIZZARD_PLL_DIV			0x04
++#define BLIZZARD_PLL_LOCK_RANGE			0x06
++#define BLIZZARD_PLL_CLOCK_SYNTH_0		0x08
++#define BLIZZARD_PLL_CLOCK_SYNTH_1		0x0a
++#define BLIZZARD_PLL_MODE			0x0c
++#define BLIZZARD_CLK_SRC			0x0e
++#define BLIZZARD_MEM_BANK0_ACTIVATE		0x10
++#define BLIZZARD_MEM_BANK0_STATUS		0x14
++#define BLIZZARD_PANEL_CONFIGURATION		0x28
++#define BLIZZARD_HDISP				0x2a
++#define BLIZZARD_HNDP				0x2c
++#define BLIZZARD_VDISP0				0x2e
++#define BLIZZARD_VDISP1				0x30
++#define BLIZZARD_VNDP				0x32
++#define BLIZZARD_HSW				0x34
++#define BLIZZARD_VSW				0x38
++#define BLIZZARD_DISPLAY_MODE			0x68
++#define BLIZZARD_INPUT_WIN_X_START_0		0x6c
++#define BLIZZARD_DATA_SOURCE_SELECT		0x8e
++#define BLIZZARD_DISP_MEM_DATA_PORT		0x90
++#define BLIZZARD_DISP_MEM_READ_ADDR0		0x92
++#define BLIZZARD_POWER_SAVE			0xE6
++#define BLIZZARD_NDISP_CTRL_STATUS		0xE8
++
++/* Data source select */
++/* For S1D13745 */
++#define BLIZZARD_SRC_WRITE_LCD_BACKGROUND	0x00
++#define BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE	0x01
++#define BLIZZARD_SRC_WRITE_OVERLAY_ENABLE	0x04
++#define BLIZZARD_SRC_DISABLE_OVERLAY		0x05
++/* For S1D13744 */
++#define BLIZZARD_SRC_WRITE_LCD			0x00
++#define BLIZZARD_SRC_BLT_LCD			0x06
++
++#define BLIZZARD_COLOR_RGB565			0x01
++#define BLIZZARD_COLOR_YUV420			0x09
++
++#define BLIZZARD_VERSION_S1D13745		0x01	/* Hailstorm */
++#define BLIZZARD_VERSION_S1D13744		0x02	/* Blizzard */
++
++#define BLIZZARD_AUTO_UPDATE_TIME		(HZ / 20)
++
++
++
++static struct {
++	int			version;
++} blizzard;
++
++
++static inline void blizzard_cmd(u8 cmd)
++{
++        omap_rfbi_write_command(&cmd, 1);
++}
++
++static inline void blizzard_write(u8 cmd, const u8 *buf, int len)
++{
++        omap_rfbi_write_command(&cmd, 1);
++        omap_rfbi_write_data(buf, len);
++}
++
++static inline void blizzard_read(u8 cmd, u8 *buf, int len)
++{
++        omap_rfbi_write_command(&cmd, 1);
++        omap_rfbi_read_data(buf, len);
++}
++
++static u8 blizzard_read_reg(u8 cmd)
++{
++	u8 data;
++	blizzard_read(cmd, &data, 1);
++	return data;
++}
++
++static int blizzard_ctrl_init(struct omap_display *display)
++{
++	DBG("blizzard_ctrl_init\n");
++
++	return 0;
++}
++
++
++static int blizzard_ctrl_enable(struct omap_display *display)
++{
++	int r = 0;
++	u8 rev, conf;
++
++	DBG("blizzard_ctrl_enable\n");
++
++	if (display->hw_config.ctrl_enable) {
++		r = display->hw_config.ctrl_enable(display);
++		if (r)
++			return r;
++	}
++
++	msleep(100);
++
++	rev = blizzard_read_reg(BLIZZARD_CLK_SRC);
++	printk("CLK_SRC %x\n", rev);
++
++	rev = blizzard_read_reg(BLIZZARD_PLL_DIV);
++	printk("PLLDIV %x\n", rev);
++
++	rev = blizzard_read_reg(BLIZZARD_REV_CODE);
++	conf = blizzard_read_reg(BLIZZARD_CONFIG);
++
++	printk("rev %x, conf %x\n", rev, conf);
++
++	switch (rev & 0xfc) {
++	case 0x9c:
++		blizzard.version = BLIZZARD_VERSION_S1D13744;
++		pr_info("omapfb: s1d13744 LCD controller rev %d "
++			"initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
++		break;
++	case 0xa4:
++		blizzard.version = BLIZZARD_VERSION_S1D13745;
++		pr_info("omapfb: s1d13745 LCD controller rev %d "
++			"initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
++		break;
++	default:
++		printk("invalid s1d1374x revision %02x\n",
++			rev);
++		r = -ENODEV;
++	}
++
++	return r;
++}
++
++static void blizzard_ctrl_disable(struct omap_display *display)
++{
++	DBG("blizzard_ctrl_disable\n");
++
++	if (display->hw_config.ctrl_disable)
++		display->hw_config.ctrl_disable(display);
++}
++
++int rfbi_configure(int rfbi_module, int bpp, int lines);
++
++static void blizzard_ctrl_setup_update(struct omap_display *display,
++				    int x, int y, int w, int h)
++{
++	u8 tmp[18];
++	int x_end, y_end;
++
++	DBG("blizzard_ctrl_setup_update\n");
++
++	x_end = x + w - 1;
++	y_end = y + h - 1;
++
++	tmp[0] = x;
++	tmp[1] = x >> 8;
++	tmp[2] = y;
++	tmp[3] = y >> 8;
++	tmp[4] = x_end;
++	tmp[5] = x_end >> 8;
++	tmp[6] = y_end;
++	tmp[7] = y_end >> 8;
++
++	/* scaling? */
++	tmp[8] = x;
++	tmp[9] = x >> 8;
++	tmp[10] = y;
++	tmp[11] = y >> 8;
++	tmp[12] = x_end;
++	tmp[13] = x_end >> 8;
++	tmp[14] = y_end;
++	tmp[15] = y_end >> 8;
++
++	tmp[16] = BLIZZARD_COLOR_RGB565; //color_mode;
++
++	if (blizzard.version == BLIZZARD_VERSION_S1D13745)
++		tmp[17] = BLIZZARD_SRC_WRITE_LCD_BACKGROUND;
++	else
++		tmp[17] = blizzard.version == BLIZZARD_VERSION_S1D13744 ?
++				BLIZZARD_SRC_WRITE_LCD :
++				BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE;
++
++	rfbi_configure(display->hw_config.u.rfbi.channel,
++		       16,
++		       8);
++
++	blizzard_write(BLIZZARD_INPUT_WIN_X_START_0, tmp, 18);
++
++	rfbi_configure(display->hw_config.u.rfbi.channel,
++		       16,
++		       16);
++}
++
++static int blizzard_ctrl_enable_te(struct omap_display *display, int enable)
++{
++	return 0;
++}
++
++static int blizzard_ctrl_rotate(struct omap_display *display, int rotate)
++{
++	return 0;
++}
++
++static int blizzard_ctrl_mirror(struct omap_display *display, int enable)
++{
++	return 0;
++}
++
++static int blizzard_run_test(struct omap_display *display, int test_num)
++{
++	return 0;
++}
++
++static struct omap_ctrl blizzard_ctrl = {
++	.owner = THIS_MODULE,
++	.name = "ctrl-blizzard",
++	.init = blizzard_ctrl_init,
++	.enable = blizzard_ctrl_enable,
++	.disable = blizzard_ctrl_disable,
++	.setup_update = blizzard_ctrl_setup_update,
++	.enable_te = blizzard_ctrl_enable_te,
++	.rotate = blizzard_ctrl_rotate,
++	.mirror = blizzard_ctrl_mirror,
++	.run_test = blizzard_run_test,
++	.pixel_size = 16,
++
++	.timings = {
++                .cs_on_time     = 0,
++
++                .we_on_time     = 9000,
++                .we_off_time    = 18000,
++                .we_cycle_time  = 36000,
++
++                .re_on_time     = 9000,
++                .re_off_time    = 27000,
++                .re_cycle_time  = 36000,
++
++                .access_time    = 27000,
++                .cs_off_time    = 36000,
++
++                .cs_pulse_width = 0,
++        },
++};
++
++
++static int __init blizzard_init(void)
++{
++	DBG("blizzard_init\n");
++	omap_dss_register_ctrl(&blizzard_ctrl);
++	return 0;
++}
++
++static void __exit blizzard_exit(void)
++{
++	DBG("blizzard_exit\n");
++
++	omap_dss_unregister_ctrl(&blizzard_ctrl);
++}
++
++module_init(blizzard_init);
++module_exit(blizzard_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("Blizzard Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/panel-n800.c b/drivers/video/omap2/panel-n800.c
+new file mode 100644
+index 0000000..3ae0a16
+--- /dev/null
++++ b/drivers/video/omap2/panel-n800.c
+@@ -0,0 +1,437 @@
++
++/*#define DEBUG*/
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/spi/spi.h>
++#include <linux/jiffies.h>
++#include <linux/sched.h>
++#include <linux/backlight.h>
++#include <linux/fb.h>
++
++#include <mach/display.h>
++#include <mach/dma.h>
++
++#define MIPID_CMD_READ_DISP_ID		0x04
++#define MIPID_CMD_READ_RED		0x06
++#define MIPID_CMD_READ_GREEN		0x07
++#define MIPID_CMD_READ_BLUE		0x08
++#define MIPID_CMD_READ_DISP_STATUS	0x09
++#define MIPID_CMD_RDDSDR		0x0F
++#define MIPID_CMD_SLEEP_IN		0x10
++#define MIPID_CMD_SLEEP_OUT		0x11
++#define MIPID_CMD_DISP_OFF		0x28
++#define MIPID_CMD_DISP_ON		0x29
++
++#define MIPID_VER_LPH8923		3
++#define MIPID_VER_LS041Y3		4
++
++#define MIPID_ESD_CHECK_PERIOD		msecs_to_jiffies(5000)
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "PN800: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++struct pn800_device {
++	struct backlight_device *bl_dev;
++	int		enabled;
++	int		model;
++	int		revision;
++	u8		display_id[3];
++	unsigned int	saved_bklight_level;
++	unsigned long	hw_guard_end;		/* next value of jiffies
++						   when we can issue the
++						   next sleep in/out command */
++	unsigned long	hw_guard_wait;		/* max guard time in jiffies */
++
++	struct spi_device	*spi;
++	struct mutex		mutex;
++	struct omap_panel	panel;
++	struct omap_display	*display;
++};
++
++
++static void pn800_transfer(struct pn800_device *md, int cmd,
++			      const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
++{
++	struct spi_message	m;
++	struct spi_transfer	*x, xfer[4];
++	u16			w;
++	int			r;
++
++	BUG_ON(md->spi == NULL);
++
++	spi_message_init(&m);
++
++	memset(xfer, 0, sizeof(xfer));
++	x = &xfer[0];
++
++	cmd &=  0xff;
++	x->tx_buf = &cmd;
++	x->bits_per_word = 9;
++	x->len = 2;
++	spi_message_add_tail(x, &m);
++
++	if (wlen) {
++		x++;
++		x->tx_buf = wbuf;
++		x->len = wlen;
++		x->bits_per_word = 9;
++		spi_message_add_tail(x, &m);
++	}
++
++	if (rlen) {
++		x++;
++		x->rx_buf = &w;
++		x->len = 1;
++		spi_message_add_tail(x, &m);
++
++		if (rlen > 1) {
++			/* Arrange for the extra clock before the first
++			 * data bit.
++			 */
++			x->bits_per_word = 9;
++			x->len		 = 2;
++
++			x++;
++			x->rx_buf	 = &rbuf[1];
++			x->len		 = rlen - 1;
++			spi_message_add_tail(x, &m);
++		}
++	}
++
++	r = spi_sync(md->spi, &m);
++	if (r < 0)
++		dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
++
++	if (rlen)
++		rbuf[0] = w & 0xff;
++}
++
++static inline void pn800_cmd(struct pn800_device *md, int cmd)
++{
++	pn800_transfer(md, cmd, NULL, 0, NULL, 0);
++}
++
++static inline void pn800_write(struct pn800_device *md,
++			       int reg, const u8 *buf, int len)
++{
++	pn800_transfer(md, reg, buf, len, NULL, 0);
++}
++
++static inline void pn800_read(struct pn800_device *md,
++			      int reg, u8 *buf, int len)
++{
++	pn800_transfer(md, reg, NULL, 0, buf, len);
++}
++
++static void set_data_lines(struct pn800_device *md, int data_lines)
++{
++	u16 par;
++
++	switch (data_lines) {
++	case 16:
++		par = 0x150;
++		break;
++	case 18:
++		par = 0x160;
++		break;
++	case 24:
++		par = 0x170;
++		break;
++	}
++	pn800_write(md, 0x3a, (u8 *)&par, 2);
++}
++
++static void send_init_string(struct pn800_device *md)
++{
++	u16 initpar[] = { 0x0102, 0x0100, 0x0100 };
++	int data_lines;
++
++	pn800_write(md, 0xc2, (u8 *)initpar, sizeof(initpar));
++
++	data_lines = (int)md->display->hw_config.priv; // XXX
++
++	set_data_lines(md, data_lines);
++}
++
++static void hw_guard_start(struct pn800_device *md, int guard_msec)
++{
++	md->hw_guard_wait = msecs_to_jiffies(guard_msec);
++	md->hw_guard_end = jiffies + md->hw_guard_wait;
++}
++
++static void hw_guard_wait(struct pn800_device *md)
++{
++	unsigned long wait = md->hw_guard_end - jiffies;
++
++	if ((long)wait > 0 && wait <= md->hw_guard_wait) {
++		set_current_state(TASK_UNINTERRUPTIBLE);
++		schedule_timeout(wait);
++	}
++}
++
++static void set_sleep_mode(struct pn800_device *md, int on)
++{
++	int cmd, sleep_time = 50;
++
++	if (on)
++		cmd = MIPID_CMD_SLEEP_IN;
++	else
++		cmd = MIPID_CMD_SLEEP_OUT;
++	hw_guard_wait(md);
++	pn800_cmd(md, cmd);
++	hw_guard_start(md, 120);
++	/*
++	 * When we enable the panel, it seems we _have_ to sleep
++	 * 120 ms before sending the init string. When disabling the
++	 * panel we'll sleep for the duration of 2 frames, so that the
++	 * controller can still provide the PCLK,HS,VS signals. */
++	if (!on)
++		sleep_time = 120;
++	msleep(sleep_time);
++}
++
++static void set_display_state(struct pn800_device *md, int enabled)
++{
++	int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
++
++	pn800_cmd(md, cmd);
++}
++
++static int panel_enabled(struct pn800_device *md)
++{
++	u32 disp_status;
++	int enabled;
++
++	pn800_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
++	disp_status = __be32_to_cpu(disp_status);
++	enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
++	dev_dbg(&md->spi->dev,
++		"LCD panel %s enabled by bootloader (status 0x%04x)\n",
++		enabled ? "" : "not ", disp_status);
++	DBG("status %#08x\n", disp_status);
++	return enabled;
++}
++
++static int panel_detect(struct pn800_device *md)
++{
++	pn800_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
++	dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
++		md->display_id[0], md->display_id[1], md->display_id[2]);
++
++	switch (md->display_id[0]) {
++	case 0x45:
++		md->model = MIPID_VER_LPH8923;
++		md->panel.name = "lph8923";
++		break;
++	case 0x83:
++		md->model = MIPID_VER_LS041Y3;
++		md->panel.name = "ls041y3";
++		//md->esd_check = ls041y3_esd_check;
++		break;
++	default:
++		md->panel.name = "unknown";
++		dev_err(&md->spi->dev, "invalid display ID\n");
++		return -ENODEV;
++	}
++
++	md->revision = md->display_id[1];
++	pr_info("omapfb: %s rev %02x LCD detected\n",
++			md->panel.name, md->revision);
++
++	return 0;
++}
++
++
++
++static int pn800_panel_enable(struct omap_display *display)
++{
++	int r;
++	struct pn800_device *md =
++		(struct pn800_device *)display->panel->priv;
++
++	DBG("pn800_panel_enable\n");
++
++	mutex_lock(&md->mutex);
++
++	if (display->hw_config.panel_enable)
++		display->hw_config.panel_enable(display);
++
++	msleep(50); // wait for power up
++
++	r = panel_detect(md);
++	if (r) {
++		mutex_unlock(&md->mutex);
++		return r;
++	}
++
++	md->enabled = panel_enabled(md);
++
++	if (md->enabled) {
++		DBG("panel already enabled\n");
++		; /*pn800_esd_start_check(md);*/
++	} else {
++		; /*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
++	}
++
++
++	if (md->enabled) {
++		mutex_unlock(&md->mutex);
++		return 0;
++	}
++
++	set_sleep_mode(md, 0);
++	md->enabled = 1;
++	send_init_string(md);
++	set_display_state(md, 1);
++	//mipid_set_bklight_level(panel, md->saved_bklight_level);
++	//mipid_esd_start_check(md);
++
++	mutex_unlock(&md->mutex);
++	return 0;
++}
++
++static void pn800_panel_disable(struct omap_display *display)
++{
++	struct pn800_device *md =
++		(struct pn800_device *)display->panel->priv;
++
++	DBG("pn800_panel_disable\n");
++
++	mutex_lock(&md->mutex);
++
++	if (!md->enabled) {
++		mutex_unlock(&md->mutex);
++		return;
++	}
++	/*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
++	/*pn800_set_bklight_level(panel, 0);*/
++
++	set_display_state(md, 0);
++	set_sleep_mode(md, 1);
++	md->enabled = 0;
++
++
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++
++	mutex_unlock(&md->mutex);
++}
++
++static int pn800_panel_init(struct omap_display *display)
++{
++	struct pn800_device *md =
++		(struct pn800_device *)display->panel->priv;
++
++	DBG("pn800_panel_init\n");
++
++	mutex_init(&md->mutex);
++	md->display = display;
++
++	return 0;
++}
++
++static int pn800_run_test(struct omap_display *display, int test_num)
++{
++	return 0;
++}
++
++static struct omap_panel pn800_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "panel-pn800",
++	.init		= pn800_panel_init,
++	/*.remove	= pn800_cleanup,*/
++	.enable		= pn800_panel_enable,
++	.disable	= pn800_panel_disable,
++	//.set_mode	= pn800_set_mode,
++	.run_test	= pn800_run_test,
++
++	.timings = {
++		.x_res = 800,
++		.y_res = 480,
++
++		.pixel_clock	= 21940,
++		.hsw		= 50,
++		.hfp		= 20,
++		.hbp		= 15,
++
++		.vsw		= 2,
++		.vfp		= 1,
++		.vbp		= 3,
++	},
++	.config		= OMAP_DSS_LCD_TFT,
++
++	.bpp = 16,
++};
++
++static int pn800_spi_probe(struct spi_device *spi)
++{
++	struct pn800_device *md;
++
++	DBG("pn800_spi_probe\n");
++
++	md = kzalloc(sizeof(*md), GFP_KERNEL);
++	if (md == NULL) {
++		dev_err(&spi->dev, "out of memory\n");
++		return -ENOMEM;
++	}
++
++	spi->mode = SPI_MODE_0;
++	md->spi = spi;
++	dev_set_drvdata(&spi->dev, md);
++	md->panel = pn800_panel;
++	pn800_panel.priv = md;
++
++	omap_dss_register_panel(&pn800_panel);
++
++	return 0;
++}
++
++static int pn800_spi_remove(struct spi_device *spi)
++{
++	struct pn800_device *md = dev_get_drvdata(&spi->dev);
++
++	DBG("pn800_spi_remove\n");
++
++	omap_dss_unregister_panel(&pn800_panel);
++
++	/*pn800_disable(&md->panel);*/
++	kfree(md);
++
++	return 0;
++}
++
++static struct spi_driver pn800_spi_driver = {
++	.driver = {
++		.name	= "panel-n800",
++		.bus	= &spi_bus_type,
++		.owner	= THIS_MODULE,
++	},
++	.probe	= pn800_spi_probe,
++	.remove	= __devexit_p(pn800_spi_remove),
++};
++
++static int __init pn800_init(void)
++{
++	DBG("pn800_init\n");
++	return spi_register_driver(&pn800_spi_driver);
++}
++
++static void __exit pn800_exit(void)
++{
++	DBG("pn800_exit\n");
++	spi_unregister_driver(&pn800_spi_driver);
++}
++
++module_init(pn800_init);
++module_exit(pn800_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("N800 LCD Driver");
++MODULE_LICENSE("GPL");
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0009-DSS-OMAPFB-allocate-fbmem-only-for-fb0-or-if-spes.patch b/recipes/linux/linux-omap-2.6.28/0009-DSS-OMAPFB-allocate-fbmem-only-for-fb0-or-if-spes.patch
new file mode 100644
index 0000000000..89174909a0
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0009-DSS-OMAPFB-allocate-fbmem-only-for-fb0-or-if-spes.patch
@@ -0,0 +1,121 @@
+From bd4fd1dd3be7ff31a6cf779f0683d617280ac92e Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 7 Jan 2009 16:44:17 +0200
+Subject: [PATCH] DSS: OMAPFB: allocate fbmem only for fb0, or if spesified in vram arg
+
+---
+ drivers/video/omap2/omapfb-main.c |   65 +++++++++++++++++++-----------------
+ 1 files changed, 34 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb-main.c b/drivers/video/omap2/omapfb-main.c
+index 76bd416..9dbff42 100644
+--- a/drivers/video/omap2/omapfb-main.c
++++ b/drivers/video/omap2/omapfb-main.c
+@@ -939,11 +939,12 @@ static int omapfb_alloc_fbmem_display(struct omapfb2_device *fbdev, int fbnum,
+ 		break;
+ 	}
+ 
+-	size = display->panel->timings.x_res * display->panel->timings.y_res *
+-		bytespp;
+-
+-	if (def_vram > size)
++	if (def_vram)
+ 		size = def_vram;
++	else
++		size = display->panel->timings.x_res *
++			display->panel->timings.y_res *
++			bytespp;
+ 
+ 	return omapfb_alloc_fbmem(fbdev, fbnum, size);
+ }
+@@ -956,13 +957,25 @@ static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
+ 	memset(vrams, 0, sizeof(vrams));
+ 
+ 	if (def_vram) {
+-		char *p = def_vram;
++		char str[64];
++		char *tok, *s;
++
++		if (strlen(def_vram) > sizeof(str) - 1) {
++			dev_err(fbdev->dev, "Illegal vram parameters\n");
++			return -EINVAL;
++		}
++
++		strcpy(str, def_vram);
++
++		s = str;
+ 		i = 0;
+ 
+-		while (true) {
++		while ((tok = strsep(&s, ","))) {
+ 			unsigned long size;
+ 
+-			size = memparse(p, &p);
++			printk("param '%s'\n", tok);
++
++			size = memparse(tok, NULL);
+ 
+ 			if (size == 0) {
+ 				dev_err(fbdev->dev, "illegal vram size\n");
+@@ -970,19 +983,18 @@ static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
+ 			}
+ 
+ 			vrams[i++] = size;
+-
+-			if (*p != ',')
+-				break;
+-
+-			p++;
+ 		}
+ 	}
+ 
+ 	for (i = 0; i < fbdev->num_fbs; i++) {
+-		r = omapfb_alloc_fbmem_display(fbdev, i, vrams[i]);
++		/* allocate memory automatically only for fb0, or if
++		 * excplicitly defined with vram option */
++		if (i == 0 || vrams[i] != 0) {
++			r = omapfb_alloc_fbmem_display(fbdev, i, vrams[i]);
+ 
+-		if (r)
+-			return r;
++			if (r)
++				return r;
++		}
+ 	}
+ 
+ 	for (i = 0; i < fbdev->num_fbs; i++) {
+@@ -1167,24 +1179,15 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
+ 			dev_err(fbdev->dev, "failed to change mode\n");
+ 	}
+ 
+-	/* Enable the first framebuffer that has overlay that is connected
+-	 * to display. Usually this would be the GFX plane. */
+-	r = 0;
+-	for (i = 0; i < fbdev->num_fbs; i++) {
+-		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
+-		int t;
++	/* Enable fb0 */
++	if (fbdev->num_fbs > 0) {
++		struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[0]);
+ 
+-		for (t = 0; t < ofbi->num_overlays; t++) {
+-			struct omap_overlay *ovl = ofbi->overlays[t];
+-			if (ovl->manager && ovl->manager->display) {
+-				ovl->enable(ovl, 1);
+-				r = 1;
+-				break;
+-			}
+-		}
++		if (ofbi->num_overlays > 0 ) {
++			struct omap_overlay *ovl = ofbi->overlays[0];
+ 
+-		if (r)
+-			break;
++			ovl->enable(ovl, 1);
++		}
+ 	}
+ 
+ 	DBG("create_framebuffers done\n");
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0010-DSS-OMAPFB-remove-extra-omapfb_setup_overlay-call.patch b/recipes/linux/linux-omap-2.6.28/0010-DSS-OMAPFB-remove-extra-omapfb_setup_overlay-call.patch
new file mode 100644
index 0000000000..c5ce980772
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0010-DSS-OMAPFB-remove-extra-omapfb_setup_overlay-call.patch
@@ -0,0 +1,29 @@
+From 70c3edb223f7bfbc6c5b095826c779b7dd853f10 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 7 Jan 2009 17:00:46 +0200
+Subject: [PATCH] OMAPFB: remove extra omapfb_setup_overlay call
+
+It kinda messed things up...
+---
+ drivers/video/omap2/omapfb-ioctl.c |    5 -----
+ 1 files changed, 0 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb-ioctl.c b/drivers/video/omap2/omapfb-ioctl.c
+index 1f0f044..bb5f791 100644
+--- a/drivers/video/omap2/omapfb-ioctl.c
++++ b/drivers/video/omap2/omapfb-ioctl.c
+@@ -67,11 +67,6 @@ static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
+ 			goto out;
+ 	}
+ 
+-	r = omapfb_setup_overlay(fbi, ovl, pi->pos_x, pi->pos_y,
+-			pi->out_width, pi->out_height);
+-	if (r)
+-		goto out;
+-
+ 	ovl->enable(ovl, pi->enabled);
+ 
+ 	if (ovl->manager)
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0011-DSS-OMAPFB-fix-GFX_SYNC-to-be-compatible-with-DSS1.patch b/recipes/linux/linux-omap-2.6.28/0011-DSS-OMAPFB-fix-GFX_SYNC-to-be-compatible-with-DSS1.patch
new file mode 100644
index 0000000000..8d4165ac7a
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0011-DSS-OMAPFB-fix-GFX_SYNC-to-be-compatible-with-DSS1.patch
@@ -0,0 +1,27 @@
+From 36d6e7edd70d16ad57ed745a1c48694805035dc7 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 7 Jan 2009 17:17:08 +0200
+Subject: [PATCH] OMAPFB: fix GFX_SYNC to be compatible with DSS1
+
+DSS1 never returned an error from GFX_SYNC ioctl. So we neither.
+---
+ drivers/video/omap2/omapfb-ioctl.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb-ioctl.c b/drivers/video/omap2/omapfb-ioctl.c
+index bb5f791..0cb0370 100644
+--- a/drivers/video/omap2/omapfb-ioctl.c
++++ b/drivers/video/omap2/omapfb-ioctl.c
+@@ -314,7 +314,8 @@ int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
+ 	switch (cmd) {
+ 	case OMAPFB_SYNC_GFX:
+ 		if (!display || !display->sync) {
+-			r = -EINVAL;
++			/* DSS1 never returns an error here, so we neither */
++			/*r = -EINVAL;*/
+ 			break;
+ 		}
+ 
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0012-DSS-Add-comments-to-FAKE_VSYNC-to-make-things-more.patch b/recipes/linux/linux-omap-2.6.28/0012-DSS-Add-comments-to-FAKE_VSYNC-to-make-things-more.patch
new file mode 100644
index 0000000000..85e7952c8d
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0012-DSS-Add-comments-to-FAKE_VSYNC-to-make-things-more.patch
@@ -0,0 +1,27 @@
+From 942267b679b7f60b33e034ee29e313925cfbcae0 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 7 Jan 2009 17:20:24 +0200
+Subject: [PATCH] DSS: Add comments to FAKE_VSYNC to make things more clear
+
+---
+ arch/arm/plat-omap/dss/Kconfig |    4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/dss/Kconfig b/arch/arm/plat-omap/dss/Kconfig
+index 6b342df..f0b1f1c 100644
+--- a/arch/arm/plat-omap/dss/Kconfig
++++ b/arch/arm/plat-omap/dss/Kconfig
+@@ -46,7 +46,9 @@ config OMAP2_DSS_FAKE_VSYNC
+ 	default n
+ 	help
+ 	  If this is selected, DSI will fake a DISPC VSYNC interrupt
+-	  when DSI has sent a frame.
++	  when DSI has sent a frame. This is only needed with DSI or
++	  RFBI displays using manual mode, and you want VSYNC to time,
++	  for example, animation.
+ 
+ config OMAP2_DSS_MIN_FCK_PER_PCK
+ 	int "Minimum FCK/PCK ratio (for scaling)"
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0013-DSS-OMAPFB-remove-extra-spaces.patch b/recipes/linux/linux-omap-2.6.28/0013-DSS-OMAPFB-remove-extra-spaces.patch
new file mode 100644
index 0000000000..fac269a319
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0013-DSS-OMAPFB-remove-extra-spaces.patch
@@ -0,0 +1,25 @@
+From 17f3d30a218efba9bf947a667c9c1fa2f4286794 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 7 Jan 2009 17:40:59 +0200
+Subject: [PATCH] OMAPFB: remove extra spaces
+
+---
+ drivers/video/omap2/omapfb-sysfs.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb-sysfs.c b/drivers/video/omap2/omapfb-sysfs.c
+index 4383e44..0e153b9 100644
+--- a/drivers/video/omap2/omapfb-sysfs.c
++++ b/drivers/video/omap2/omapfb-sysfs.c
+@@ -337,7 +337,7 @@ static ssize_t show_overlays(struct device *dev, struct device_attribute *attr,
+ 				break;
+ 
+ 		l += snprintf(buf + l, size - l,
+-			"%s t:%s x:%d y:%d iw:%d ih:%d w: %d h: %d e:%d\n",
++			"%s t:%s x:%d y:%d iw:%d ih:%d w:%d h:%d e:%d\n",
+ 			ovl->name,
+ 			mgr ? mgr->name : "none",
+ 			ovl->info.pos_x,
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0014-DSS-fix-clk_get_usecount.patch b/recipes/linux/linux-omap-2.6.28/0014-DSS-fix-clk_get_usecount.patch
new file mode 100644
index 0000000000..a935709a9e
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0014-DSS-fix-clk_get_usecount.patch
@@ -0,0 +1,67 @@
+From ba234fff55f8a1ef96b57ce2e18ab90df76f2c82 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 8 Jan 2009 12:01:39 +0200
+Subject: [PATCH] DSS: fix clk_get_usecount
+
+---
+ arch/arm/plat-omap/dss/dss.c |   12 ++++++------
+ 1 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/plat-omap/dss/dss.c b/arch/arm/plat-omap/dss/dss.c
+index 4a403c1..b9f35d8 100644
+--- a/arch/arm/plat-omap/dss/dss.c
++++ b/arch/arm/plat-omap/dss/dss.c
+@@ -236,7 +236,7 @@ ssize_t dss_print_clocks(char *buf, ssize_t size)
+ 		l += snprintf(buf + l, size - l, "%-15s\t%lu\t%d\n",
+ 				clocks[i]->name,
+ 				clk_get_rate(clocks[i]),
+-				clk_get_usecount(clocks[i]));
++				clocks[i]->usecount);
+ 	}
+ 
+ 	return l;
+@@ -590,28 +590,28 @@ void dss_exit(void)
+ 	free_irq(INT_24XX_DSS_IRQ, NULL);
+ 
+ 	/* these should be removed at some point */
+-	c = clk_get_usecount(dss.dss_ick);
++	c = dss.dss_ick->usecount;
+ 	if (c > 0) {
+ 		DSSERR("warning: dss_ick usecount %d, disabling\n", c);
+ 		while (c-- > 0)
+ 			clk_disable(dss.dss_ick);
+ 	}
+ 
+-	c = clk_get_usecount(dss.dss1_fck);
++	c = dss.dss1_fck->usecount;
+ 	if (c > 0) {
+ 		DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
+ 		while (c-- > 0)
+ 			clk_disable(dss.dss1_fck);
+ 	}
+ 
+-	c = clk_get_usecount(dss.dss2_fck);
++	c = dss.dss2_fck->usecount;
+ 	if (c > 0) {
+ 		DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
+ 		while (c-- > 0)
+ 			clk_disable(dss.dss2_fck);
+ 	}
+ 
+-	c = clk_get_usecount(dss.dss_54m_fck);
++	c = dss.dss_54m_fck->usecount;
+ 	if (c > 0) {
+ 		DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
+ 		while (c-- > 0)
+@@ -619,7 +619,7 @@ void dss_exit(void)
+ 	}
+ 
+ 	if (dss.dss_96m_fck) {
+-		c = clk_get_usecount(dss.dss_96m_fck);
++		c = dss.dss_96m_fck->usecount;
+ 		if (c > 0) {
+ 			DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
+ 					c);
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/0015-OMAPFB-remove-debug-print.patch b/recipes/linux/linux-omap-2.6.28/0015-OMAPFB-remove-debug-print.patch
new file mode 100644
index 0000000000..ecb7aecba7
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/0015-OMAPFB-remove-debug-print.patch
@@ -0,0 +1,25 @@
+From 73f2a252fc273b6d3ee7daab9681728a915f7236 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 8 Jan 2009 12:02:07 +0200
+Subject: [PATCH] OMAPFB: remove debug print
+
+---
+ drivers/video/omap2/omapfb-main.c |    2 --
+ 1 files changed, 0 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb-main.c b/drivers/video/omap2/omapfb-main.c
+index 9dbff42..d043c43 100644
+--- a/drivers/video/omap2/omapfb-main.c
++++ b/drivers/video/omap2/omapfb-main.c
+@@ -973,8 +973,6 @@ static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
+ 		while ((tok = strsep(&s, ","))) {
+ 			unsigned long size;
+ 
+-			printk("param '%s'\n", tok);
+-
+ 			size = memparse(tok, NULL);
+ 
+ 			if (size == 0) {
+-- 
+1.5.6.3
+
diff --git a/recipes/linux/linux-omap-2.6.28/add-resizer-driver.patch b/recipes/linux/linux-omap-2.6.28/add-resizer-driver.patch
new file mode 100644
index 0000000000..9457bec576
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/add-resizer-driver.patch
@@ -0,0 +1,19823 @@
+Index: git/drivers/media/video/isp/bluegamma_table.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/bluegamma_table.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,1040 @@
++/*
++ * drivers/media/video/omap/isp/redgamma_table.h
++ *
++ * Gamma Table values for Red for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2007 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
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+Index: git/drivers/media/video/isp/cfa_coef_table.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/cfa_coef_table.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,592 @@
++/*
++ * drivers/media/video/omap/isp/cfa_coef_table.h
++ *
++ * CFA Coefficient Table values for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2007 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
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+Index: git/drivers/media/video/isp/greengamma_table.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/greengamma_table.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,1040 @@
++/*
++ * drivers/media/video/omap/isp/redgamma_table.h
++ *
++ * Gamma Table values for Red for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2007 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
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+Index: git/drivers/media/video/isp/isp.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isp.c	2009-02-12 15:21:14.000000000 -0600
+@@ -0,0 +1,2301 @@
++/*
++ * drivers/media/video/isp/isp.c
++ *
++ * Driver Library for ISP Control module in TI's OMAP3430 Camera ISP
++ * ISP interface and IRQ related APIs are defined here.
++ *
++ * Copyright (C) 2008 Texas Instruments.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <asm/irq.h>
++#include <asm/scatterlist.h>
++#include <asm/mach-types.h>
++#include <linux/device.h>
++#include <linux/autoconf.h>
++#include <asm/io.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "ispccdc.h"
++#include "isppreview.h"
++#include "ispresizer.h"
++#include "ispmmu.h"
++#include "isph3a.h"
++#include "isp_af.h"
++#include "isphist.h"
++
++#define ISP_XCLKA_DEFAULT 	0x12
++
++#ifdef CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER
++#define USE_ISP_PREVIEW
++#endif
++
++#ifdef CONFIG_VIDEO_OMAP34XX_ISP_RESIZER
++#define USE_ISP_RESZ
++#endif
++/* list of image formats supported via OMAP ISP */
++const static struct v4l2_fmtdesc isp_formats[] = {
++	{
++#ifndef ENABLE_BT_656_CAPTURE
++		.description	= "UYVY, packed",
++#else
++		.description	= "UYVY (YUV 4:2:2), packed",
++#endif
++		.pixelformat	= V4L2_PIX_FMT_UYVY,
++	},
++	{
++		.description	= "YUYV (YUV 4:2:2), packed",
++		.pixelformat	= V4L2_PIX_FMT_YUYV,
++	},
++	{
++		.description	= "Bayer10 (GrR/BGb)",
++		.pixelformat	= V4L2_PIX_FMT_SGRBG10,
++	},
++};
++
++#define NUM_ISP_CAPTURE_FORMATS (sizeof(isp_formats)/sizeof(isp_formats[0]))
++
++
++/* ISP Crop capabilities */
++static struct v4l2_rect ispcroprect;
++static struct v4l2_rect cur_rect;
++
++/* Video controls */
++static struct vcontrol {
++	struct v4l2_queryctrl qc;
++	int current_value;
++} video_control[] = {
++	{
++		{
++			.id = V4L2_CID_BRIGHTNESS,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Brightness",
++			.minimum = ISPPRV_BRIGHT_LOW,
++			.maximum = ISPPRV_BRIGHT_HIGH,
++			.step = ISPPRV_BRIGHT_STEP,
++			.default_value = ISPPRV_BRIGHT_DEF,
++		},
++		.current_value = ISPPRV_BRIGHT_DEF,
++	},
++	{
++		{
++			.id = V4L2_CID_CONTRAST,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Contrast",
++			.minimum = ISPPRV_CONTRAST_LOW,
++			.maximum = ISPPRV_CONTRAST_HIGH,
++			.step = ISPPRV_CONTRAST_STEP,
++			.default_value = ISPPRV_CONTRAST_DEF,
++		},
++		.current_value = ISPPRV_CONTRAST_DEF,
++	},
++	{
++		{
++			.id = V4L2_CID_PRIVATE_ISP_COLOR_FX,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Color Effects",
++			.minimum = PREV_DEFAULT_COLOR,
++			.maximum = PREV_SEPIA_COLOR,
++			.step = 1,
++			.default_value = PREV_DEFAULT_COLOR,
++		},
++		.current_value = PREV_DEFAULT_COLOR,
++	},
++	{
++		{
++			.id = V4L2_CID_PRIVATE_ISP_CCDC_CFG,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "CCDC",
++			.minimum = 0,
++			.maximum = 1,
++			.step = 1,
++			.default_value = 0,
++		},
++		.current_value = 0,
++	},
++	{
++		{
++			.id = V4L2_CID_PRIVATE_ISP_PRV_CFG,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Previewer",
++			.minimum = 0,
++			.maximum = 1,
++			.step = 1,
++			.default_value = 0,
++		},
++		.current_value = 0,
++	},
++	{
++		{
++			.id = V4L2_CID_PRIVATE_ISP_LSC_UPDATE,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Tables",
++			.minimum = 0,
++			.maximum = 1,
++			.step = 1,
++			.default_value = 0,
++		},
++		.current_value = 0,
++	},
++	{
++		{
++			.id = V4L2_CID_PRIVATE_ISP_AEWB_CFG,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Auto Exposure, Auto WB Config",
++			.minimum = 0,
++			.maximum = 1,
++			.step = 1,
++			.default_value = 0,
++		},
++		.current_value = 0,
++	},
++	{
++		{
++			.id = V4L2_CID_PRIVATE_ISP_AEWB_REQ,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "AEWB Request Statistics",
++			.minimum = 0,
++			.maximum = 1,
++			.step = 1,
++			.default_value = 0,
++		},
++		.current_value = 0,
++	},
++		{
++		{
++			.id = V4L2_CID_PRIVATE_ISP_AF_CFG,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "Auto Focus Config",
++			.minimum = 0,
++			.maximum = 1,
++			.step = 1,
++			.default_value = 0,
++		},
++		.current_value = 0,
++	},
++	{
++		{
++			.id = V4L2_CID_PRIVATE_ISP_AF_REQ,
++			.type = V4L2_CTRL_TYPE_INTEGER,
++			.name = "AF Request Statistics",
++			.minimum = 0,
++			.maximum = 1,
++			.step = 1,
++			.default_value = 0,
++		},
++		.current_value = 0,
++	}
++};
++
++/*Structure for IRQ related info */
++static struct ispirq {
++	isp_callback_t isp_callbk[10];
++	isp_vbq_callback_ptr isp_callbk_arg1[10];
++	void *isp_callbk_arg2[10];
++} ispirq_obj;
++
++/* Structure for storing ISP Control module information*/
++static struct isp {
++	spinlock_t lock;	/* spinlock to sync b/w isr and processes */
++	spinlock_t isp_temp_buf_lock;
++	struct mutex isp_mutex;
++	u8 if_status;
++	u8 interfacetype;
++	int ref_count;
++	struct clk *cam_ick;
++	struct clk *cam_fck;
++} isp_obj;
++
++struct isp_sgdma ispsg;
++
++/* Structure for storing ISP sub-module information - CCDC,PRV,RSZ */
++struct ispmodule {
++	/* Bit mask for sub-modules enabled within the ISP */
++	unsigned int isp_pipeline;
++	int isp_temp_state;
++	int applyCrop;
++	struct v4l2_pix_format pix;
++	/* tried ISP output sizes for video mode */
++	unsigned int ccdc_input_width;
++	unsigned int ccdc_input_height;
++	unsigned int ccdc_output_width;
++	unsigned int ccdc_output_height;
++	unsigned int preview_input_width;
++	unsigned int preview_input_height;
++	unsigned int preview_output_width;
++	unsigned int preview_output_height;
++	unsigned int resizer_input_width;
++	unsigned int resizer_input_height;
++	unsigned int resizer_output_width;
++	unsigned int resizer_output_height;
++#ifdef ENABLE_BT_656_CAPTURE
++	/* Flag to indicate whether capture is interlaced or progressive */
++	int capture_type;
++	int current_field;
++	__u32 input_pixelformat;
++#endif
++};
++
++#ifdef ENABLE_BT_656_CAPTURE
++#define ISP_SD_STD_PARAMS \
++	{"NTSC", 858, 525, 720, 480, 720 * 2, 30, V4L2_PIX_FMT_UYVY, \
++	 V4L2_FIELD_INTERLACED, 720 * 2, 720 * 2 * 480, \
++	 V4L2_COLORSPACE_SMPTE170M}, \
++	{"PAL", 864, 625, 720, 576, 720 * 2, 25, V4L2_PIX_FMT_UYVY, \
++	 V4L2_FIELD_INTERLACED, 720 * 2, 720 * 2 * 480, \
++	 V4L2_COLORSPACE_SMPTE170M}
++
++struct isp_std_config_params {
++	char name[30];
++	unsigned int num_pixels;
++	unsigned int num_lines;
++	unsigned int active_pixels;
++	unsigned int active_lines;
++	unsigned int pitch;
++	unsigned int fps;
++	__u32 pixelformat;
++	enum v4l2_field field;
++	__u32 bytesperline;
++	__u32 sizeimage;
++	enum v4l2_colorspace colorspace;
++};
++
++static struct isp_std_config_params std_params[] = {
++	ISP_SD_STD_PARAMS
++};
++#endif
++
++static struct ispmodule ispmodule_obj = {
++	.isp_pipeline = OMAP_ISP_CCDC,
++	.isp_temp_state = ISP_BUF_INIT,
++	.applyCrop = 0,
++	.pix = {
++		.width = 176,
++		.height = 144,
++		.pixelformat = V4L2_PIX_FMT_UYVY,
++		.field = V4L2_FIELD_NONE,
++		.bytesperline = 176*2,
++		.colorspace = V4L2_COLORSPACE_JPEG,
++		.priv = 0,
++	},
++#ifdef ENABLE_BT_656_CAPTURE
++	.capture_type = 0,
++	.current_field = 0,
++	.input_pixelformat = V4L2_PIX_FMT_UYVY,
++#endif
++};
++
++/* Structure for saving/restoring ISP module registers*/
++
++static struct isp_reg isp_reg_list[] = {
++	{ISP_SYSCONFIG, 0x0000},
++	{ISP_IRQ0ENABLE, 0x0000},
++	{ISP_IRQ1ENABLE, 0x0000},
++	{ISP_TCTRL_GRESET_LENGTH, 0x0000},
++	{ISP_TCTRL_PSTRB_REPLAY, 0x0000},
++	{ISP_CTRL, 0x0000},
++	{ISP_TCTRL_CTRL, 0x0000},
++	{ISP_TCTRL_FRAME, 0x0000},
++	{ISP_TCTRL_PSTRB_DELAY, 0x0000},
++	{ISP_TCTRL_STRB_DELAY, 0x0000},
++	{ISP_TCTRL_SHUT_DELAY, 0x0000},
++	{ISP_TCTRL_PSTRB_LENGTH, 0x0000},
++	{ISP_TCTRL_STRB_LENGTH, 0x0000},
++	{ISP_TCTRL_SHUT_LENGTH, 0x0000},
++	{ISP_CBUFF_SYSCONFIG, 0x0000},
++	{ISP_CBUFF_IRQENABLE, 0x0000},
++	{ISP_CBUFF0_CTRL, 0x0000},
++	{ISP_CBUFF1_CTRL, 0x0000},
++	{ISP_CBUFF0_START, 0x0000},
++	{ISP_CBUFF1_START, 0x0000},
++	{ISP_CBUFF0_END, 0x0000},
++	{ISP_CBUFF1_END, 0x0000},
++	{ISP_CBUFF0_WINDOWSIZE, 0x0000},
++	{ISP_CBUFF1_WINDOWSIZE, 0x0000},
++	{ISP_CBUFF0_THRESHOLD, 0x0000},
++	{ISP_CBUFF1_THRESHOLD, 0x0000},
++	{ISP_TOK_TERM, 0x0000}
++};
++
++/*
++ *
++ * V4L2 Handling
++ *
++ */
++
++/* Returns the index of the requested ID from the control structure array */
++static int
++find_vctrl(int id)
++{
++	int i;
++
++	if (id < V4L2_CID_BASE)
++		return -EDOM;
++
++	for (i = (ARRAY_SIZE(video_control) - 1); i >= 0; i--)
++		if (video_control[i].qc.id == id)
++			break;
++	if (i < 0)
++		i = -EINVAL;
++	return i;
++}
++
++void isp_open(void)
++{
++	ispccdc_request();
++	isppreview_request();
++	ispresizer_request();
++	return;
++}
++EXPORT_SYMBOL(isp_open);
++
++void isp_close(void)
++{
++	ispccdc_free();
++	isppreview_free();
++	ispresizer_free();
++	memset(&ispcroprect, 0, sizeof(ispcroprect));
++	memset(&cur_rect, 0, sizeof(cur_rect));
++	return;
++}
++EXPORT_SYMBOL(isp_close);
++
++/* flag to check first time of isp_get */
++static int off_mode;
++
++int isp_set_sgdma_callback(struct isp_sgdma_state *sgdma_state,
++						isp_vbq_callback_ptr func_ptr)
++{
++#ifdef USE_ISP_RESZ
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER) {
++		isp_set_callback(CBK_RESZ_DONE, sgdma_state->callback,
++						func_ptr, sgdma_state->arg);
++	}
++#endif
++
++#ifdef USE_ISP_PREVIEW
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW) {
++		isp_set_callback(CBK_PREV_DONE, sgdma_state->callback,
++						func_ptr, sgdma_state->arg);
++	}
++#endif
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_CCDC) {
++		isp_set_callback(CBK_CCDC_VD0, sgdma_state->callback, func_ptr,
++							sgdma_state->arg);
++		isp_set_callback(CBK_CCDC_VD1, sgdma_state->callback, func_ptr,
++							sgdma_state->arg);
++#ifndef ENABLE_BT_656_CAPTURE
++		isp_set_callback(CBK_LSC_ISR, NULL, NULL, NULL);
++#endif
++	}
++	isp_set_callback(CBK_HS_VS, sgdma_state->callback, func_ptr,
++							sgdma_state->arg);
++	return 0;
++}
++
++/*
++ *Sets the callback for the ISP module done events.
++ * type		: Type of the event for which callback is requested.
++ * callback	: Method to be called as callback in the ISR context.
++ * arg1		: Argument to be passed when callback is called in ISR.
++ * arg2		: Argument to be passed when callback is called in ISR.
++ */
++int isp_set_callback(enum isp_callback_type type, isp_callback_t callback,
++						isp_vbq_callback_ptr arg1,
++						void *arg2)
++{
++	unsigned long irqflags = 0;
++
++	if (callback == NULL) {
++		DPRINTK_ISPCTRL("ISP_ERR : Null Callback\n");
++		return -EINVAL;
++	}
++
++	spin_lock_irqsave(&isp_obj.lock, irqflags);
++	ispirq_obj.isp_callbk[type] = callback;
++	ispirq_obj.isp_callbk_arg1[type] = arg1;
++	ispirq_obj.isp_callbk_arg2[type] = arg2;
++	spin_unlock_irqrestore(&isp_obj.lock, irqflags);
++
++	switch (type) {
++	case CBK_HS_VS:
++		omap_writel(IRQ0ENABLE_HS_VS_IRQ, ISP_IRQ0STATUS);
++		omap_writel(omap_readl(ISP_IRQ0ENABLE) | IRQ0ENABLE_HS_VS_IRQ,
++							ISP_IRQ0ENABLE);
++		break;
++	case CBK_PREV_DONE:
++		omap_writel(IRQ0ENABLE_PRV_DONE_IRQ, ISP_IRQ0STATUS);
++		omap_writel(omap_readl(ISP_IRQ0ENABLE) |
++					IRQ0ENABLE_PRV_DONE_IRQ,
++					ISP_IRQ0ENABLE);
++		break;
++	case CBK_RESZ_DONE:
++		omap_writel(IRQ0ENABLE_RSZ_DONE_IRQ, ISP_IRQ0STATUS);
++		omap_writel(omap_readl(ISP_IRQ0ENABLE) |
++					IRQ0ENABLE_RSZ_DONE_IRQ,
++					ISP_IRQ0ENABLE);
++		break;
++	case CBK_MMU_ERR:
++		omap_writel(omap_readl(ISP_IRQ0ENABLE) |
++					IRQ0ENABLE_MMU_ERR_IRQ,
++					ISP_IRQ0ENABLE);
++
++		omap_writel(omap_readl(ISPMMU_IRQENABLE) |
++					IRQENABLE_MULTIHITFAULT |
++					IRQENABLE_TWFAULT |
++					IRQENABLE_EMUMISS |
++					IRQENABLE_TRANSLNFAULT |
++					IRQENABLE_TLBMISS,
++					ISPMMU_IRQENABLE);
++		break;
++	case CBK_H3A_AWB_DONE:
++		omap_writel(IRQ0ENABLE_H3A_AWB_DONE_IRQ, ISP_IRQ0STATUS);
++		omap_writel(omap_readl(ISP_IRQ0ENABLE) |
++					IRQ0ENABLE_H3A_AWB_DONE_IRQ,
++					ISP_IRQ0ENABLE);
++		break;
++	case CBK_H3A_AF_DONE:
++		omap_writel(IRQ0ENABLE_H3A_AF_DONE_IRQ, ISP_IRQ0STATUS);
++		omap_writel(omap_readl(ISP_IRQ0ENABLE)|
++				IRQ0ENABLE_H3A_AF_DONE_IRQ,
++				ISP_IRQ0ENABLE);
++		break;
++	case CBK_HIST_DONE:
++		omap_writel(IRQ0ENABLE_HIST_DONE_IRQ, ISP_IRQ0STATUS);
++		omap_writel(omap_readl(ISP_IRQ0ENABLE) |
++					IRQ0ENABLE_HIST_DONE_IRQ,
++					ISP_IRQ0ENABLE);
++		break;
++	case CBK_LSC_ISR:
++		omap_writel(IRQ0ENABLE_CCDC_LSC_DONE_IRQ |
++					IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ |
++					IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ,
++					ISP_IRQ0STATUS);
++		omap_writel(omap_readl(ISP_IRQ0ENABLE) |
++					IRQ0ENABLE_CCDC_LSC_DONE_IRQ |
++					IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ |
++					IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ,
++					ISP_IRQ0ENABLE);
++		break;
++	default:
++		break;
++	};
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_set_callback);
++
++/**
++ * isp_unset_callback - Clears the callback for the ISP module done events.
++ * @type: Type of the event for which callback to be cleared.
++ *
++ * This function clears a callback function for a done event in the ISP
++ * module, and disables the corresponding interrupt.
++ **/
++int isp_unset_callback(enum isp_callback_type type)
++{
++	unsigned long irqflags = 0;
++
++	spin_lock_irqsave(&isp_obj.lock, irqflags);
++	ispirq_obj.isp_callbk[type] = NULL;
++	ispirq_obj.isp_callbk_arg1[type] = NULL;
++	ispirq_obj.isp_callbk_arg2[type] = NULL;
++	spin_unlock_irqrestore(&isp_obj.lock, irqflags);
++
++	switch (type) {
++	case CBK_CCDC_VD0:
++		omap_writel((omap_readl(ISP_IRQ0ENABLE)) &
++				~IRQ0ENABLE_CCDC_VD0_IRQ,
++				ISP_IRQ0ENABLE);
++		break;
++	case CBK_CCDC_VD1:
++		omap_writel((omap_readl(ISP_IRQ0ENABLE)) &
++				~IRQ0ENABLE_CCDC_VD1_IRQ,
++				ISP_IRQ0ENABLE);
++		break;
++	case CBK_PREV_DONE:
++		omap_writel((omap_readl(ISP_IRQ0ENABLE)) &
++				~IRQ0ENABLE_PRV_DONE_IRQ,
++				ISP_IRQ0ENABLE);
++		break;
++	case CBK_RESZ_DONE:
++		omap_writel((omap_readl(ISP_IRQ0ENABLE)) &
++				~IRQ0ENABLE_RSZ_DONE_IRQ,
++				ISP_IRQ0ENABLE);
++		break;
++	case CBK_MMU_ERR:
++		omap_writel(omap_readl(ISPMMU_IRQENABLE) &
++				~(IRQENABLE_MULTIHITFAULT |
++					IRQENABLE_TWFAULT |
++					IRQENABLE_EMUMISS |
++					IRQENABLE_TRANSLNFAULT |
++					IRQENABLE_TLBMISS),
++				ISPMMU_IRQENABLE);
++		break;
++	case CBK_H3A_AWB_DONE:
++		omap_writel((omap_readl(ISP_IRQ0ENABLE)) &
++				~IRQ0ENABLE_H3A_AWB_DONE_IRQ,
++				ISP_IRQ0ENABLE);
++		break;
++	case CBK_H3A_AF_DONE:
++		omap_writel((omap_readl(ISP_IRQ0ENABLE))&
++				(~IRQ0ENABLE_H3A_AF_DONE_IRQ),ISP_IRQ0ENABLE);
++		break;
++	case CBK_HIST_DONE:
++		omap_writel((omap_readl(ISP_IRQ0ENABLE)) &
++				~IRQ0ENABLE_HIST_DONE_IRQ,
++				ISP_IRQ0ENABLE);
++		break;
++	case CBK_HS_VS:
++		omap_writel((omap_readl(ISP_IRQ0ENABLE)) &
++				~IRQ0ENABLE_HS_VS_IRQ,
++				ISP_IRQ0ENABLE);
++		break;
++	case CBK_LSC_ISR:
++		omap_writel(omap_readl(ISP_IRQ0ENABLE) &
++					~(IRQ0ENABLE_CCDC_LSC_DONE_IRQ |
++					IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ |
++					IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ),
++					ISP_IRQ0ENABLE);
++		break;
++	default:
++		break;
++	};
++	return 0;
++}
++EXPORT_SYMBOL(isp_unset_callback);
++
++/**
++ * isp_request_interface - Requests an ISP interface type (parallel or serial).
++ * @if_t: Type of requested ISP interface (parallel or serial).
++ *
++ * This function requests for allocation of an ISP interface type.
++ **/
++int isp_request_interface(enum isp_interface_type if_t)
++{
++	if (isp_obj.if_status & if_t) {
++		DPRINTK_ISPCTRL("ISP_ERR : Requested Interface already \
++			allocated\n");
++		goto err_ebusy;
++	}
++	if ((isp_obj.if_status == (ISP_PARLL | ISP_CSIA))
++			|| isp_obj.if_status == (ISP_CSIA | ISP_CSIB)) {
++		DPRINTK_ISPCTRL("ISP_ERR : No Free interface now\n");
++		goto err_ebusy;
++	}
++
++	if (((isp_obj.if_status == ISP_PARLL) && (if_t == ISP_CSIA)) ||
++				((isp_obj.if_status == ISP_CSIA) &&
++				(if_t == ISP_PARLL)) ||
++				((isp_obj.if_status == ISP_CSIA) &&
++				(if_t == ISP_CSIB)) ||
++				((isp_obj.if_status == ISP_CSIB) &&
++				(if_t == ISP_CSIA)) ||
++				(isp_obj.if_status == 0)) {
++		isp_obj.if_status |= if_t;
++		return 0;
++	} else {
++		DPRINTK_ISPCTRL("ISP_ERR : Invalid Combination Serial- \
++			Parallel interface\n");
++		return -EINVAL;
++	}
++
++err_ebusy:
++	return -EBUSY;
++}
++EXPORT_SYMBOL(isp_request_interface);
++
++/**
++ * isp_free_interface - Frees an ISP interface type (parallel or serial).
++ * @if_t: Type of ISP interface to be freed (parallel or serial).
++ *
++ * This function frees the allocation of an ISP interface type.
++ **/
++int isp_free_interface(enum isp_interface_type if_t)
++{
++	isp_obj.if_status &= ~if_t;
++	return 0;
++}
++EXPORT_SYMBOL(isp_free_interface);
++
++/**
++ * isp_set_xclk - Configures the specified cam_xclk to the desired frequency.
++ * @xclk: Desired frequency of the clock in Hz.
++ * @xclksel: XCLK to configure (0 = A, 1 = B).
++ *
++ * Configures the specified MCLK divisor in the ISP timing control register
++ * (TCTRL_CTRL) to generate the desired xclk clock value.
++ *
++ * Divisor = CM_CAM_MCLK_HZ / xclk
++ *
++ * Returns the final frequency that is actually being generated
++ **/
++u32 isp_set_xclk(u32 xclk, u8 xclksel)
++{
++	u32 divisor;
++	u32 currentxclk;
++
++	if (xclk == CM_CAM_MCLK_HZ) {
++		divisor = (xclksel == 0) ? ISPTCTRL_CTRL_DIVA_Bypass :
++					ISPTCTRL_CTRL_DIVB_Bypass;
++		currentxclk = CM_CAM_MCLK_HZ;
++	} else {
++		if (xclk >= 2) {
++			divisor = CM_CAM_MCLK_HZ / xclk;
++			divisor &= (xclksel == 0) ? ISPTCTRL_CTRL_DIVA_Bypass :
++					ISPTCTRL_CTRL_DIVB_Bypass;
++			currentxclk = CM_CAM_MCLK_HZ / divisor;
++		} else {
++			divisor = xclk;
++			currentxclk = 0;
++		}
++	}
++
++	switch (xclksel) {
++	case 0:
++		omap_writel((omap_readl(ISP_TCTRL_CTRL) &
++				~ISPTCTRL_CTRL_DIVA_Bypass) |
++				(divisor << ISPTCTRL_CTRL_DIVA_SHIFT),
++				ISP_TCTRL_CTRL);
++		DPRINTK_ISPCTRL("isp_set_xclk(): cam_xclka set to %x Hz\n",
++								currentxclk);
++		break;
++	case 1:
++		omap_writel((omap_readl(ISP_TCTRL_CTRL) &
++				~ISPTCTRL_CTRL_DIVB_Bypass) |
++				(divisor << ISPTCTRL_CTRL_DIVB_SHIFT),
++				ISP_TCTRL_CTRL);
++		DPRINTK_ISPCTRL("isp_set_xclk(): cam_xclkb set to %x Hz\n",
++								currentxclk);
++		break;
++	default:
++		DPRINTK_ISPCTRL("ISP_ERR: isp_set_xclk(): Invalid requested "
++						"xclk. Must be 0 (A) or 1 (B)."
++						"\n");
++		return -EINVAL;
++	}
++
++	return currentxclk;
++}
++EXPORT_SYMBOL(isp_set_xclk);
++
++/**
++ * isp_get_xclk - Returns the frequency in Hz of the desired cam_xclk.
++ * @xclksel: XCLK to retrieve (0 = A, 1 = B).
++ *
++ * This function returns the External Clock (XCLKA or XCLKB) value generated
++ * by the ISP.
++ **/
++u32 isp_get_xclk(u8 xclksel)
++{
++	u32 xclkdiv;
++	u32 xclk;
++
++	switch (xclksel) {
++	case 0:
++		xclkdiv = omap_readl(ISP_TCTRL_CTRL) & ISPTCTRL_CTRL_DIVA_MASK;
++		xclkdiv = xclkdiv >> ISPTCTRL_CTRL_DIVA_SHIFT;
++		break;
++	case 1:
++		xclkdiv = omap_readl(ISP_TCTRL_CTRL) & ISPTCTRL_CTRL_DIVB_MASK;
++		xclkdiv = xclkdiv >> ISPTCTRL_CTRL_DIVB_SHIFT;
++		break;
++	default:
++		DPRINTK_ISPCTRL("ISP_ERR: isp_get_xclk(): Invalid requested "
++						"xclk. Must be 0 (A) or 1 (B)."
++						"\n");
++		return -EINVAL;
++	}
++
++	switch (xclkdiv) {
++	case 0:
++	case 1:
++		xclk = 0;
++		break;
++	case 0x1f:
++		xclk = CM_CAM_MCLK_HZ;
++		break;
++	default:
++		xclk = CM_CAM_MCLK_HZ / xclkdiv;
++	}
++
++	return xclk;
++}
++EXPORT_SYMBOL(isp_get_xclk);
++
++/**
++ * isp_power_settings - Sysconfig settings, for Power Management.
++ * @isp_sysconfig: Structure containing the power settings for ISP to configure
++ *
++ * Sets the power settings for the ISP, and SBL bus.
++ **/
++void isp_power_settings(struct isp_sysc isp_sysconfig)
++{
++	if (isp_sysconfig.idle_mode) {
++		omap_writel(ISP_SYSCONFIG_AUTOIDLE |
++				(ISP_SYSCONFIG_MIdleMode_SmartStandBy <<
++				ISP_SYSCONFIG_MIdleMode_SHIFT),
++				ISP_SYSCONFIG);
++
++		omap_writel(ISPMMU_AUTOIDLE | (ISPMMU_SIdlemode_Smartidle <<
++						ISPMMU_SIdlemode_Shift),
++						ISPMMU_SYSCONFIG);
++///		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
++			omap_writel(ISPCSI1_AUTOIDLE |
++					(ISPCSI1_MIdleMode_SmartStandBy <<
++					ISPCSI1_MIdleMode_Shift),
++					ISP_CSIA_SYSCONFIG);
++			omap_writel(ISPCSI1_AUTOIDLE |
++					(ISPCSI1_MIdleMode_SmartStandBy <<
++					ISPCSI1_MIdleMode_Shift),
++					ISP_CSIB_SYSCONFIG);
++///		}
++		omap_writel(ISPCTRL_SBL_AutoIdle, ISP_CTRL);
++
++	} else {
++		omap_writel(ISP_SYSCONFIG_AUTOIDLE |
++			(ISP_SYSCONFIG_MIdleMode_ForceStandBy <<
++			ISP_SYSCONFIG_MIdleMode_SHIFT), ISP_SYSCONFIG);
++
++		omap_writel(ISPMMU_AUTOIDLE |
++			(ISPMMU_SIdlemode_Noidle << ISPMMU_SIdlemode_Shift),
++						ISPMMU_SYSCONFIG);
++///		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
++			omap_writel(ISPCSI1_AUTOIDLE |
++				(ISPCSI1_MIdleMode_ForceStandBy <<
++				ISPCSI1_MIdleMode_Shift), ISP_CSIA_SYSCONFIG);
++
++			omap_writel(ISPCSI1_AUTOIDLE |
++				(ISPCSI1_MIdleMode_ForceStandBy <<
++				ISPCSI1_MIdleMode_Shift), ISP_CSIB_SYSCONFIG);
++///		}
++
++		omap_writel(ISPCTRL_SBL_AutoIdle, ISP_CTRL);
++
++		}
++
++
++}
++EXPORT_SYMBOL(isp_power_settings);
++
++/**
++ * isp_configure_interface - Configures ISP Control I/F related parameters.
++ * @config: Structure containing the desired configuration for the ISP.
++ *
++ * Configures ISP control register (ISP_CTRL) with the values specified inside
++ * the config structure. Controls:
++ * - Selection of parallel or serial input to the preview hardware.
++ * - Data lane shifter.
++ * - Pixel clock polarity.
++ * - 8 to 16-bit bridge at the input of CCDC module.
++ * - HS or VS synchronization signal detection
++ **/
++int isp_configure_interface(struct isp_interface_config *config)
++{
++	u32 ispctrl_val = omap_readl(ISP_CTRL);
++	u32 ispccdc_vdint_val;
++
++	ispctrl_val &= (ISPCTRL_PAR_SER_CLK_SEL_MASK);
++	ispctrl_val |= config->ccdc_par_ser;
++	ispctrl_val &= ISPCTRL_SHIFT_MASK;
++	ispctrl_val |= (config->dataline_shift << ISPCTRL_SHIFT_SHIFT);
++	ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
++	ispctrl_val |= (config->para_clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT);
++	ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_BENDIAN;
++	ispctrl_val |= (config->par_bridge << ISPCTRL_PAR_BRIDGE_SHIFT);
++	ispctrl_val &= ~(ISPCTRL_SYNC_DETECT_VSRISE);
++	ispctrl_val |= (config->hsvs_syncdetect << ISPCTRL_SYNC_DETECT_SHIFT);
++
++	omap_writel(ispctrl_val, ISP_CTRL);
++
++	ispccdc_vdint_val = omap_readl(ISPCCDC_VDINT);
++	ispccdc_vdint_val &= ~(ISPCCDC_VDINT_0_MASK << ISPCCDC_VDINT_0_SHIFT);
++	ispccdc_vdint_val &= ~(ISPCCDC_VDINT_1_MASK << ISPCCDC_VDINT_1_SHIFT);
++	omap_writel((config->vdint0_timing << ISPCCDC_VDINT_0_SHIFT) |
++					(config->vdint1_timing <<
++					ISPCCDC_VDINT_1_SHIFT),
++					ISPCCDC_VDINT);
++	return 0;
++}
++EXPORT_SYMBOL(isp_configure_interface);
++
++/**
++ * isp_CCDC_VD01_enable - Enables VD0 and VD1 IRQs.
++ *
++ * Sets VD0 and VD1 bits in IRQ0STATUS to reset the flag, and sets them in
++ * IRQ0ENABLE to enable the corresponding IRQs.
++ **/
++void isp_CCDC_VD01_enable(void)
++{
++	omap_writel(IRQ0STATUS_CCDC_VD0_IRQ | IRQ0STATUS_CCDC_VD1_IRQ,
++				ISP_IRQ0STATUS);
++	omap_writel(omap_readl(ISP_IRQ0ENABLE) | IRQ0ENABLE_CCDC_VD0_IRQ |
++			IRQ0ENABLE_CCDC_VD1_IRQ, ISP_IRQ0ENABLE);
++}
++
++/**
++ * isp_CCDC_VD01_disable - Disables VD0 and VD1 IRQs.
++ *
++ * Clears VD0 and VD1 bits in IRQ0ENABLE register.
++ **/
++void isp_CCDC_VD01_disable(void)
++{
++	omap_writel(omap_readl(ISP_IRQ0ENABLE) &
++			~(IRQ0ENABLE_CCDC_VD0_IRQ | IRQ0ENABLE_CCDC_VD1_IRQ),
++			ISP_IRQ0ENABLE);
++}
++
++/**
++ * omap34xx_isp_isr - Interrupt Service Routine for Camera ISP module.
++ * @irq: Not used currently.
++ * @ispirq_disp: The object that is passed while request_irq is called.
++ *               This is the ispirq_obj object containing info on the callback.
++ *
++ * Handles the corresponding callback if plugged in.
++ **/
++static irqreturn_t omap34xx_isp_isr(int irq, void *ispirq_disp)
++{
++	struct ispirq *irqdis = (struct ispirq *) ispirq_disp;
++	u32 irqstatus = 0;
++	unsigned long irqflags = 0;
++	u8 is_irqhandled = 0;
++
++	irqstatus = omap_readl(ISP_IRQ0STATUS);
++
++	spin_lock_irqsave(&isp_obj.lock, irqflags);
++
++	if ((irqstatus & MMU_ERR) == MMU_ERR) {
++		if (irqdis->isp_callbk[CBK_MMU_ERR])
++			irqdis->isp_callbk[CBK_MMU_ERR](irqstatus,
++				irqdis->isp_callbk_arg1[CBK_MMU_ERR],
++				irqdis->isp_callbk_arg2[CBK_MMU_ERR]);
++		is_irqhandled = 1;
++		goto out;
++	}
++
++	if ((irqstatus & CCDC_VD1) == CCDC_VD1) {
++		if (irqdis->isp_callbk[CBK_CCDC_VD1])
++				irqdis->isp_callbk[CBK_CCDC_VD1](CCDC_VD1,
++				irqdis->isp_callbk_arg1[CBK_CCDC_VD1],
++				irqdis->isp_callbk_arg2[CBK_CCDC_VD1]);
++		is_irqhandled = 1;
++	}
++
++	if ((irqstatus & CCDC_VD0) == CCDC_VD0) {
++		if (irqdis->isp_callbk[CBK_CCDC_VD0])
++			irqdis->isp_callbk[CBK_CCDC_VD0](CCDC_VD0,
++				irqdis->isp_callbk_arg1[CBK_CCDC_VD0],
++				irqdis->isp_callbk_arg2[CBK_CCDC_VD0]);
++		is_irqhandled = 1;
++	}
++
++	if ((irqstatus & PREV_DONE) == PREV_DONE) {
++		if (irqdis->isp_callbk[CBK_PREV_DONE])
++			irqdis->isp_callbk[CBK_PREV_DONE](PREV_DONE,
++				irqdis->isp_callbk_arg1[CBK_PREV_DONE],
++				irqdis->isp_callbk_arg2[CBK_PREV_DONE]);
++		is_irqhandled = 1;
++	}
++
++	if ((irqstatus & RESZ_DONE) == RESZ_DONE) {
++		if (irqdis->isp_callbk[CBK_RESZ_DONE])
++			irqdis->isp_callbk[CBK_RESZ_DONE](RESZ_DONE,
++				irqdis->isp_callbk_arg1[CBK_RESZ_DONE],
++				irqdis->isp_callbk_arg2[CBK_RESZ_DONE]);
++		is_irqhandled = 1;
++	}
++
++	if ((irqstatus & H3A_AWB_DONE) == H3A_AWB_DONE) {
++		if (irqdis->isp_callbk[CBK_H3A_AWB_DONE])
++			irqdis->isp_callbk[CBK_H3A_AWB_DONE](H3A_AWB_DONE,
++				irqdis->isp_callbk_arg1[CBK_H3A_AWB_DONE],
++				irqdis->isp_callbk_arg2[CBK_H3A_AWB_DONE]);
++		is_irqhandled = 1;
++	}
++
++	if ((irqstatus & HIST_DONE) == HIST_DONE) {
++		if (irqdis->isp_callbk[CBK_HIST_DONE])
++			irqdis->isp_callbk[CBK_HIST_DONE](HIST_DONE,
++				irqdis->isp_callbk_arg1[CBK_HIST_DONE],
++				irqdis->isp_callbk_arg2[CBK_HIST_DONE]);
++		is_irqhandled = 1;
++	}
++
++	if ((irqstatus & HS_VS) == HS_VS) {
++		if (irqdis->isp_callbk[CBK_HS_VS])
++			irqdis->isp_callbk[CBK_HS_VS](HS_VS,
++				irqdis->isp_callbk_arg1[CBK_HS_VS],
++				irqdis->isp_callbk_arg2[CBK_HS_VS]);
++		is_irqhandled = 1;
++	}
++
++		if ((irqstatus & H3A_AF_DONE) == H3A_AF_DONE){
++			if (irqdis->isp_callbk[CBK_H3A_AF_DONE])
++				irqdis->isp_callbk[CBK_H3A_AF_DONE](H3A_AF_DONE,
++						irqdis->isp_callbk_arg1[CBK_H3A_AF_DONE],
++						irqdis->isp_callbk_arg2[CBK_H3A_AF_DONE]);
++		is_irqhandled = 1;
++	}
++
++	if (irqstatus & LSC_PRE_ERR) {
++		DPRINTK_ISPCTRL("isp_sr: LSC_PRE_ERR \n");
++		omap_writel(irqstatus, ISP_IRQ0STATUS);
++		ispccdc_enable_lsc(0);
++		ispccdc_enable_lsc(1);
++		spin_unlock_irqrestore(&isp_obj.lock, irqflags);
++		return IRQ_HANDLED;
++	}
++out:
++	omap_writel(irqstatus, ISP_IRQ0STATUS);
++	spin_unlock_irqrestore(&isp_obj.lock, irqflags);
++
++	if (is_irqhandled)
++		return IRQ_HANDLED;
++	else
++		return IRQ_NONE;
++}
++#ifdef CONFIG_TRACK_RESOURCES
++/* device name needed for resource tracking layer */
++struct device_driver camera_drv = {
++	.name = "camera"
++};
++
++struct device camera_dev = {
++	.driver = &camera_drv,
++};
++#endif
++
++void isp_set_pipeline(int soc_type)
++{
++	ispmodule_obj.isp_pipeline |= OMAP_ISP_CCDC;
++
++	/* 1- Smart sensor, 0 - Raw sensor */
++	if (!soc_type)
++		ispmodule_obj.isp_pipeline |= (OMAP_ISP_PREVIEW |
++							OMAP_ISP_RESIZER);
++
++	return;
++}
++
++void
++omapisp_unset_callback()
++{
++	isp_unset_callback(CBK_HS_VS);
++#ifdef USE_ISP_RESZ
++	/* This has to occur before the vysnc of the intended frame comes */
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER)
++		isp_unset_callback(CBK_RESZ_DONE);
++#endif
++#ifdef USE_ISP_PREVIEW
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW)
++		isp_unset_callback(CBK_PREV_DONE);
++#endif
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_CCDC) {
++		isp_unset_callback(CBK_CCDC_VD0);
++		isp_unset_callback(CBK_CCDC_VD1);
++		isp_unset_callback(CBK_LSC_ISR);
++	}
++	omap_writel(omap_readl(ISP_IRQ0STATUS) | ISP_INT_CLR, ISP_IRQ0STATUS);
++}
++
++void isp_start(void)
++{
++	/* start the needed isp components assuming these components
++	 * are configured correctly.
++	 */
++#ifdef USE_ISP_PREVIEW
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW)
++		isppreview_enable(1);
++#endif
++	return ;
++}
++EXPORT_SYMBOL(isp_start);
++
++void isp_stop()
++{
++	int timeout;
++
++	spin_lock(&isp_obj.isp_temp_buf_lock);
++	ispmodule_obj.isp_temp_state = ISP_FREE_RUNNING;
++	spin_unlock(&isp_obj.isp_temp_buf_lock);
++	omapisp_unset_callback();
++
++#ifdef USE_ISP_RESZ
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER) {
++		ispresizer_enable(0);
++		timeout = 0;
++		while (ispresizer_busy() && (timeout < 20)) {
++			timeout++;
++			schedule();
++		}
++	}
++#endif
++#ifdef USE_ISP_PREVIEW
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW) {
++		isppreview_enable(0);
++		timeout = 0;
++		while (isppreview_busy() && (timeout < 20)) {
++			timeout++;
++			schedule();
++		}
++	}
++#endif
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_CCDC) {
++		ispccdc_enable(0);
++		timeout = 0;
++		while (ispccdc_busy() && (timeout < 20)) {
++			timeout++;
++			schedule();
++		}
++	}
++	if (ispccdc_busy() || isppreview_busy() || ispresizer_busy()) {
++		isp_save_ctx();
++		omap_writel(omap_readl(ISP_SYSCONFIG) |
++			ISP_SYSCONFIG_SOFTRESET, ISP_SYSCONFIG);
++		timeout = 0;
++		while ((!(omap_readl(ISP_SYSSTATUS) & 0x1)) && timeout < 40) {
++			timeout++;
++			mdelay(1);
++		}
++	isp_restore_ctx();
++	}
++}
++EXPORT_SYMBOL(isp_stop);
++
++void isp_set_buf(struct isp_sgdma_state *sgdma_state)
++{
++#ifdef USE_ISP_RESZ
++	/* This has to occur before the vysnc of the intended frame comes */
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER) {
++		ispresizer_set_outaddr(sgdma_state->isp_addr);
++	} else
++#endif
++#ifdef USE_ISP_PREVIEW
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW) {
++		isppreview_set_outaddr(sgdma_state->isp_addr);
++	} else
++#endif
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_CCDC) {
++		ispccdc_set_outaddr(sgdma_state->isp_addr);
++	}
++}
++
++void isp_calc_pipeline(struct v4l2_pix_format *pix_input,
++			struct v4l2_pix_format *pix_output)
++{
++
++	ispmodule_obj.isp_pipeline = OMAP_ISP_CCDC;
++
++#ifdef ENABLE_BT_656_CAPTURE
++	if (pix_input->field == V4L2_FIELD_NONE)
++		ispmodule_obj.capture_type = 0;	/* Progressive */
++	else
++		ispmodule_obj.capture_type = 1;	/* Interlaced */
++
++	ispmodule_obj.input_pixelformat = pix_input->pixelformat;
++#endif
++
++	if ((pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10) &&
++		(pix_output->pixelformat != V4L2_PIX_FMT_SGRBG10)) {
++		ispmodule_obj.isp_pipeline |= (OMAP_ISP_PREVIEW |
++						OMAP_ISP_RESIZER);
++		ispccdc_config_datapath(CCDC_RAW, CCDC_OTHERS_VP);
++		isppreview_config_datapath(PRV_RAW_CCDC,
++					PREVIEW_RSZ);
++		ispresizer_config_datapath(RSZ_OTFLY_YUV);
++	} else {
++		if (pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10)
++			ispccdc_config_datapath(CCDC_RAW, CCDC_OTHERS_MEM);
++		else
++#ifndef ENABLE_BT_656_CAPTURE
++			ispccdc_config_datapath(CCDC_YUV_SYNC, CCDC_OTHERS_MEM);
++#else
++			ispccdc_config_datapath(CCDC_YUV_BT, CCDC_OTHERS_MEM);
++#endif
++	}
++	return;
++}
++
++
++void isp_config_pipeline(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output)
++{
++	ispccdc_config_size(ispmodule_obj.ccdc_input_width,
++			ispmodule_obj.ccdc_input_height,
++			ispmodule_obj.ccdc_output_width,
++			ispmodule_obj.ccdc_output_height);
++
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW)
++		isppreview_config_size(ispmodule_obj.preview_input_width,
++			ispmodule_obj.preview_input_height,
++			ispmodule_obj.preview_output_width,
++			ispmodule_obj.preview_output_height);
++
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER)
++		ispresizer_config_size(ispmodule_obj.resizer_input_width,
++			ispmodule_obj.resizer_input_height,
++			ispmodule_obj.resizer_output_width,
++			ispmodule_obj.resizer_output_height);
++
++#ifdef ENABLE_BT_656_CAPTURE
++	if (pix_input->pixelformat == V4L2_PIX_FMT_UYVY)
++		ispccdc_config_y8pos(Y8POS_ODD);
++	else if (pix_input->pixelformat == V4L2_PIX_FMT_YUYV)
++		ispccdc_config_y8pos(Y8POS_EVEN);
++
++	if (((pix_input->pixelformat == V4L2_PIX_FMT_UYVY) &&
++	                (pix_output->pixelformat == V4L2_PIX_FMT_UYVY)) ||
++	    ((pix_input->pixelformat == V4L2_PIX_FMT_YUYV) &&
++	                (pix_output->pixelformat == V4L2_PIX_FMT_YUYV)))
++		/* input and output formats are in same order */
++		ispccdc_config_byteswap(0);
++	else if (((pix_input->pixelformat == V4L2_PIX_FMT_YUYV) &&
++	                (pix_output->pixelformat == V4L2_PIX_FMT_UYVY)) ||
++	    ((pix_input->pixelformat == V4L2_PIX_FMT_UYVY) &&
++	                (pix_output->pixelformat == V4L2_PIX_FMT_YUYV)))
++		/* input and output formats are in reverse order */
++		ispccdc_config_byteswap(1);
++
++	/* Configure Pitch */
++	ispccdc_config_outlineoffset(ispmodule_obj.pix.bytesperline, 0, 0);
++#endif
++
++	if (pix_output->pixelformat == V4L2_PIX_FMT_UYVY) {
++		isppreview_config_ycpos(YCPOS_YCrYCb);
++#ifdef USE_ISP_RESZ
++		ispresizer_config_ycpos(0);
++#endif
++	} else {
++		isppreview_config_ycpos(YCPOS_CrYCbY);
++#ifdef USE_ISP_RESZ
++		ispresizer_config_ycpos(1);
++#endif
++	}
++
++	return;
++}
++
++/* Callback for interrupt completion*/
++void isp_vbq_done(unsigned long status, isp_vbq_callback_ptr arg1, void *arg2)
++{
++	struct videobuf_buffer *vb = (struct videobuf_buffer *) arg2;
++	int notify = 0;
++	int rval = 0;
++	unsigned long flags;
++#ifdef ENABLE_BT_656_CAPTURE
++	unsigned long fld_stat = (omap_readl(ISPCCDC_SYN_MODE) >> 15) & 0x1;
++#endif
++	switch (status) {
++	case CCDC_VD0:
++#ifdef ENABLE_BT_656_CAPTURE
++		if (ispmodule_obj.capture_type) {
++			spin_lock(&isp_obj.isp_temp_buf_lock);
++			if (ispmodule_obj.current_field != fld_stat) {
++				if (fld_stat == 0)
++					ispmodule_obj.current_field = fld_stat;
++
++				spin_unlock(&isp_obj.isp_temp_buf_lock);
++				return;
++			}
++			spin_unlock(&isp_obj.isp_temp_buf_lock);
++
++			if (fld_stat == 0) {	/* Skip even fields */
++				return;
++			}
++		}
++#endif
++
++		ispccdc_config_shadow_registers();
++		if ((ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER) ||
++			(ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW))
++			return;
++		else {
++			spin_lock(&isp_obj.isp_temp_buf_lock);
++			if (ispmodule_obj.isp_temp_state != ISP_BUF_INIT) {
++				spin_unlock(&isp_obj.isp_temp_buf_lock);
++				return;
++
++			} else {
++				spin_unlock(&isp_obj.isp_temp_buf_lock);
++				break;
++			}
++		}
++		break;
++	case CCDC_VD1:
++#ifdef ENABLE_BT_656_CAPTURE
++		if (ispmodule_obj.capture_type) {
++			spin_lock(&isp_obj.isp_temp_buf_lock);
++			if (ispmodule_obj.current_field != fld_stat) {
++				if (fld_stat == 0)
++					ispmodule_obj.current_field = fld_stat;
++
++				spin_unlock(&isp_obj.isp_temp_buf_lock);
++				return;
++			}
++
++			if (fld_stat == 0) {	/* Skip even fields */
++				return;
++			}
++
++			spin_unlock(&isp_obj.isp_temp_buf_lock);
++		}
++#endif
++
++		if ((ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER) ||
++			(ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW))
++			return;
++		spin_lock(&isp_obj.isp_temp_buf_lock);
++		if (ispmodule_obj.isp_temp_state == ISP_BUF_INIT) {
++			spin_unlock(&isp_obj.isp_temp_buf_lock);
++			ispccdc_enable(0);
++			return;
++		}
++		spin_unlock(&isp_obj.isp_temp_buf_lock);
++		return;
++		break;
++
++#ifdef USE_ISP_PREVIEW
++	case PREV_DONE:
++		if (ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER) {
++			if (!ispmodule_obj.applyCrop &&
++					(ispmodule_obj.isp_temp_state ==
++					ISP_BUF_INIT))
++				ispresizer_enable(1);
++			if (ispmodule_obj.applyCrop && !ispresizer_busy()) {
++				ispresizer_enable(0);
++				ispresizer_applycrop();
++				ispmodule_obj.applyCrop = 0;
++			}
++		}
++		isppreview_config_shadow_registers();
++		isph3a_update_wb();
++		if (ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER)
++			return;
++		break;
++#endif
++
++#ifdef USE_ISP_RESZ
++	case RESZ_DONE:
++		ispresizer_config_shadow_registers();
++		spin_lock(&isp_obj.isp_temp_buf_lock);
++		if (ispmodule_obj.isp_temp_state != ISP_BUF_INIT) {
++			spin_unlock(&isp_obj.isp_temp_buf_lock);
++			return;
++		}
++		spin_unlock(&isp_obj.isp_temp_buf_lock);
++		break;
++#endif
++
++	case HS_VS:
++#ifndef ENABLE_BT_656_CAPTURE
++		spin_lock(&isp_obj.isp_temp_buf_lock);
++		if (ispmodule_obj.isp_temp_state == ISP_BUF_TRAN) {
++			isp_CCDC_VD01_enable();
++			ispmodule_obj.isp_temp_state = ISP_BUF_INIT;
++		}
++		spin_unlock(&isp_obj.isp_temp_buf_lock);
++		return;
++#else
++		if (ispmodule_obj.capture_type) {
++			ispmodule_obj.current_field ^= 1;
++			spin_lock(&isp_obj.isp_temp_buf_lock);
++			if ((ispmodule_obj.isp_temp_state == ISP_BUF_TRAN) &&
++			    (fld_stat == 1)) {
++				isp_CCDC_VD01_enable();
++				ispmodule_obj.current_field = fld_stat;
++				ispmodule_obj.isp_temp_state = ISP_BUF_INIT;
++			}
++			spin_unlock(&isp_obj.isp_temp_buf_lock);
++			return;
++		} else {
++			spin_lock(&isp_obj.isp_temp_buf_lock);
++			if (ispmodule_obj.isp_temp_state == ISP_BUF_TRAN) {
++				isp_CCDC_VD01_enable();
++				ispmodule_obj.isp_temp_state = ISP_BUF_INIT;
++			}
++			spin_unlock(&isp_obj.isp_temp_buf_lock);
++			return;
++		}
++#endif
++
++	default:
++		break;
++	}
++
++	spin_lock_irqsave(&ispsg.lock, flags);
++	ispsg.free_sgdma++;
++	if (ispsg.free_sgdma > NUM_SG_DMA)
++		ispsg.free_sgdma = NUM_SG_DMA;
++	spin_unlock_irqrestore(&ispsg.lock, flags);
++
++	rval = arg1(vb);
++
++	if (rval)
++		isp_sgdma_process(&ispsg, 1, &notify, arg1);
++
++	return;
++}
++
++void
++isp_sgdma_init()
++{
++	int sg;
++
++	ispsg.free_sgdma = NUM_SG_DMA;
++	ispsg.next_sgdma = 0;
++	for (sg = 0; sg < NUM_SG_DMA; sg++) {
++		ispsg.sg_state[sg].status = 0;
++		ispsg.sg_state[sg].callback = NULL;
++		ispsg.sg_state[sg].arg = NULL;
++	}
++}
++EXPORT_SYMBOL(isp_sgdma_init);
++
++void isp_sgdma_process(struct isp_sgdma *sgdma, int irq, int *dma_notify,
++						isp_vbq_callback_ptr func_ptr)
++{
++	struct isp_sgdma_state *sgdma_state;
++	unsigned long flags;
++	spin_lock_irqsave(&sgdma->lock, flags);
++
++	 /* we can at most start or queue one sgdma */
++	if ((NUM_SG_DMA - sgdma->free_sgdma) > 0) {
++		/* get the next sgdma */
++		sgdma_state = sgdma->sg_state +
++			(sgdma->next_sgdma + sgdma->free_sgdma) % NUM_SG_DMA;
++		if (!irq) {
++			if (*dma_notify) {
++				/* case 1: queue & start. */
++				isp_set_sgdma_callback(sgdma_state, func_ptr);
++				isp_set_buf(sgdma_state);
++				ispccdc_enable(1);
++				isp_start();
++				*dma_notify = 0;
++				ispmodule_obj.isp_temp_state = ISP_BUF_TRAN;
++			} else {
++				/*
++				 * case 3: only need to queue
++				 * (update buf ptr).
++				 */
++				if (ispmodule_obj.isp_temp_state ==
++							ISP_FREE_RUNNING) {
++					isp_set_sgdma_callback(sgdma_state,
++								func_ptr);
++					isp_set_buf(sgdma_state);
++					/* Non startup case */
++					ispccdc_enable(1);
++					ispmodule_obj.isp_temp_state =
++								ISP_BUF_TRAN;
++				}
++			}
++		} else {
++			/* case 3:only need to queue (update buf ptr). */
++			isp_set_sgdma_callback(sgdma_state, func_ptr);
++			isp_set_buf(sgdma_state);
++			/* Non startup case */
++			ispccdc_enable(1);
++			ispmodule_obj.isp_temp_state = ISP_BUF_INIT;
++			/* TODO: clear irq. old interrupt can come first.
++			 * OK for preview.
++			 */
++			if (*dma_notify) {
++				isp_start();
++				*dma_notify = 0;
++			}
++		}
++	} else {
++		spin_lock(&isp_obj.isp_temp_buf_lock);
++		/* Disable VD0 and CCDC here before next VSYNC */
++		isp_CCDC_VD01_disable();
++		ispmodule_obj.isp_temp_state = ISP_FREE_RUNNING;
++		spin_unlock(&isp_obj.isp_temp_buf_lock);
++	}
++	spin_unlock_irqrestore(&sgdma->lock, flags);
++	return;
++}
++
++int isp_sgdma_queue(struct videobuf_dmabuf *vdma, struct videobuf_buffer *vb,
++						int irq, int *dma_notify,
++						isp_vbq_callback_ptr func_ptr)
++{
++	unsigned long flags;
++	struct isp_sgdma_state *sg_state;
++	const struct scatterlist *sglist = vdma->sglist;
++	int sglen = vdma->sglen;
++
++	if ((sglen < 0) || ((sglen > 0) & !sglist))
++		return -EINVAL;
++
++	spin_lock_irqsave(&ispsg.lock, flags);
++
++	if (!ispsg.free_sgdma) {
++		spin_unlock_irqrestore(&ispsg.lock, flags);
++		return -EBUSY;
++	}
++
++	sg_state = ispsg.sg_state + ispsg.next_sgdma;
++	sg_state->isp_addr = ispsg.isp_addr_capture[vb->i];
++	sg_state->status = 0;
++	sg_state->callback = isp_vbq_done;
++	sg_state->arg = vb;
++
++	ispsg.next_sgdma = (ispsg.next_sgdma + 1) % NUM_SG_DMA;
++	ispsg.free_sgdma--;
++
++	spin_unlock_irqrestore(&ispsg.lock, flags);
++
++	isp_sgdma_process(&ispsg, irq, dma_notify, func_ptr);
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_sgdma_queue);
++
++int isp_vbq_prepare(struct videobuf_queue *vbq, struct videobuf_buffer *vb,
++							enum v4l2_field field)
++{
++	unsigned int isp_addr;
++	struct videobuf_dmabuf	*vdma;
++
++	int err = 0;
++
++	vdma = videobuf_to_dma(vb);
++
++	/* Map the address to ISP MMU */
++	isp_addr = ispmmu_map_sg(vdma->sglist, vdma->sglen);
++
++	if (!isp_addr)
++		err = -EIO;
++	else
++		ispsg.isp_addr_capture[vb->i] = isp_addr;
++
++	return err;
++}
++EXPORT_SYMBOL(isp_vbq_prepare);
++
++void isp_vbq_release(struct videobuf_queue *vbq, struct videobuf_buffer *vb)
++{
++	/* Un-Map the address in ISP MMU */
++	ispmmu_unmap(ispsg.isp_addr_capture[vb->i]);
++	ispsg.isp_addr_capture[vb->i] = (dma_addr_t) NULL;
++	vb->state = VIDEOBUF_NEEDS_INIT;
++	return;
++}
++EXPORT_SYMBOL(isp_vbq_release);
++
++int isp_queryctrl(struct v4l2_queryctrl *a)
++{
++	int i;
++
++	i = find_vctrl(a->id);
++	if (i == -EINVAL)
++		a->flags = V4L2_CTRL_FLAG_DISABLED;
++
++	if (i < 0)
++		return -EINVAL;
++
++	*a = video_control[i].qc;
++	return 0;
++}
++EXPORT_SYMBOL(isp_queryctrl);
++
++int isp_g_ctrl(struct v4l2_control *a)
++{
++	u8 current_value;
++	int rval = 0;
++
++	switch (a->id) {
++	case V4L2_CID_BRIGHTNESS:
++		isppreview_query_brightness(&current_value);
++		a->value = current_value / ISPPRV_BRIGHT_UNITS;
++		break;
++	case V4L2_CID_CONTRAST:
++		isppreview_query_contrast(&current_value);
++		a->value = current_value / ISPPRV_CONTRAST_UNITS;
++		break;
++	case V4L2_CID_PRIVATE_ISP_COLOR_FX:
++		isppreview_get_color(&current_value);
++		a->value = current_value;
++		break;
++	case V4L2_CID_PRIVATE_ISP_CCDC_CFG:
++		a->value = 0;
++		break;
++	case V4L2_CID_PRIVATE_ISP_PRV_CFG:
++		a->value = 0;
++		break;
++	case V4L2_CID_PRIVATE_ISP_LSC_UPDATE:
++		a->value = 0;
++		break;
++	case V4L2_CID_PRIVATE_ISP_AEWB_CFG:
++		a->value = 0;
++		break;
++	case V4L2_CID_PRIVATE_ISP_AEWB_REQ:
++		a->value = 0;
++		break;
++	case V4L2_CID_PRIVATE_ISP_AF_CFG:
++		a->value = 0;
++		break;
++	case V4L2_CID_PRIVATE_ISP_AF_REQ:
++		a->value = 0;
++		break;
++	default:
++		rval = -EINVAL;
++		break;
++	}
++	return rval;
++}
++EXPORT_SYMBOL(isp_g_ctrl);
++
++int isp_s_ctrl(struct v4l2_control *a)
++{
++	int rval = 0;
++	u8 new_value = a->value;
++
++	switch (a->id) {
++	case V4L2_CID_BRIGHTNESS:
++		if (new_value > ISPPRV_BRIGHT_HIGH)
++			rval = -EINVAL;
++		else
++			isppreview_update_brightness(&new_value);
++		break;
++	case V4L2_CID_CONTRAST:
++		if (new_value > ISPPRV_CONTRAST_HIGH)
++			rval = -EINVAL;
++		else
++			isppreview_update_contrast(&new_value);
++		break;
++	case V4L2_CID_PRIVATE_ISP_COLOR_FX:
++		if (new_value > PREV_SEPIA_COLOR)
++			rval = -EINVAL;
++		else
++			isppreview_set_color(&new_value);
++		break;
++	case V4L2_CID_PRIVATE_ISP_CCDC_CFG:
++		omap34xx_isp_ccdc_config((void *)a->value);
++		break;
++	case V4L2_CID_PRIVATE_ISP_PRV_CFG:
++		omap34xx_isp_preview_config((void *)a->value);
++		break;
++	case V4L2_CID_PRIVATE_ISP_LSC_UPDATE:
++		omap34xx_isp_tables_update((void *)a->value);
++		omap34xx_isp_lsc_update((void *)a->value);
++		break;
++	case V4L2_CID_PRIVATE_ISP_AEWB_CFG:
++		if (!a->value)
++			rval = -EFAULT;
++		else {
++			struct isph3a_aewb_config params;
++			if (copy_from_user(&params, (void *)a->value,
++							sizeof(params))) {
++				rval = -EFAULT;
++				printk(KERN_ERR "Failed copy_from_user\n");
++			} else
++				rval = isph3a_aewb_configure(&params);
++		}
++		break;
++	case V4L2_CID_PRIVATE_ISP_AEWB_REQ:
++		if (!a->value)
++			rval = -EFAULT;
++		else {
++			struct isph3a_aewb_data data;
++			if (copy_from_user(&data, (void *)a->value,
++							sizeof(data))) {
++				rval = -EFAULT;
++				printk(KERN_ERR "Failed copy_from_user\n");
++				break;
++			}
++			rval = isph3a_aewb_request_statistics(&data);
++			if (!rval)
++				if (copy_to_user((void *)a->value, &data,
++							sizeof(data))) {
++					rval = -EFAULT;
++					printk(KERN_ERR
++						"Failed copy_to_user\n");
++				}
++		}
++		break;
++	case V4L2_CID_PRIVATE_ISP_AF_CFG:
++	if (!a->value)
++			rval = -EFAULT;
++		else {
++			struct af_configuration params;
++
++			if (copy_from_user(&params, (struct af_configuration *)a->value,
++							sizeof(struct af_configuration))) {
++				rval = -EFAULT;
++				printk(KERN_ERR "Failed copy_from_user\n");
++			} else
++				rval = isp_af_configure(&params);
++		}
++		break;
++	case V4L2_CID_PRIVATE_ISP_AF_REQ:
++		if (!a->value)
++			rval = -EFAULT;
++		else {
++			struct isp_af_data data;
++				if (copy_from_user(&data, (void *) (a->value),
++							sizeof(data))) {
++				      	printk(KERN_ERR "Failed copy_from_user\n");
++					return -EFAULT;
++				}
++
++				if(data.update & LENS_CURRENT_POSITION){
++#if 0
++				        if(dw9710_af_getfocus(&data.lens_current_position))
++#endif
++				        	return -EFAULT;
++
++				        if (copy_to_user((void *)a->value, &data,
++							sizeof(data))) {
++					rval = -EFAULT;
++					printk(KERN_ERR
++						"Failed copy_to_user\n");
++					}
++				}
++				if(data.update & LENS_DESIRED_POSITION)
++#if 0
++					if(dw9710_af_setfocus(data.desired_lens_direction))
++#endif
++						return -EFAULT;
++
++			rval = isp_af_request_statistics(&data);
++			if (!rval)
++				if (copy_to_user((void *)a->value, &data,
++							sizeof(data))) {
++					rval = -EFAULT;
++					printk(KERN_ERR
++						"Failed copy_to_user\n");
++				}
++		}
++
++		break;
++	case V4L2_CID_PRIVATE_ISP_HIST_CFG:
++	if (!a->value)
++			rval = -EFAULT;
++		else {
++			struct isp_hist_config params;
++			if (copy_from_user(&params, (struct isp_hist_config *)a->value,
++							sizeof(struct isp_hist_config))) {
++				rval = -EFAULT;
++				printk(KERN_ERR "Failed copy_from_user\n");
++			} else
++				rval = isp_hist_configure(&params);
++		}
++		break;
++
++	case V4L2_CID_PRIVATE_ISP_HIST_REQ:
++	if (!a->value)
++			rval = -EFAULT;
++		else {
++			struct isp_hist_data data;
++
++			if (copy_from_user(&data, (struct isp_hist_data *)a->value,
++							sizeof(struct isp_hist_data))) {
++				rval = -EFAULT;
++				printk(KERN_ERR "Failed copy_from_user\n");
++			} else
++				rval = isp_hist_request_statistics(&data);
++		}
++		break;
++	default:
++		rval = -EINVAL;
++		break;
++	}
++	return rval;
++}
++EXPORT_SYMBOL(isp_s_ctrl);
++
++int isp_enum_fmt_cap(struct v4l2_fmtdesc *f)
++{
++	int index = f->index;
++	enum v4l2_buf_type type = f->type;
++	int rval = -EINVAL;
++#ifdef ENABLE_BT_656_CAPTURE
++	int num_formats = NUM_ISP_CAPTURE_FORMATS;
++
++	if (ispmodule_obj.input_pixelformat != V4L2_PIX_FMT_SGRBG10)
++		num_formats--;
++#endif
++
++#ifndef ENABLE_BT_656_CAPTURE
++	if (index >= NUM_ISP_CAPTURE_FORMATS)
++		goto err;
++#else
++	if (index >= num_formats)
++		goto err;
++#endif
++
++	memset(f, 0, sizeof(*f));
++	f->index = index;
++	f->type = type;
++
++	switch (f->type) {
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++		rval = 0;
++		break;
++	default:
++		goto err;
++	}
++
++	f->flags = isp_formats[index].flags;
++	strncpy(f->description, isp_formats[index].description,
++						sizeof(f->description));
++	f->pixelformat = isp_formats[index].pixelformat;
++err:
++	return rval;
++}
++EXPORT_SYMBOL(isp_enum_fmt_cap);
++
++void isp_g_fmt_cap(struct v4l2_format *f)
++{
++	f->fmt.pix = ispmodule_obj.pix;
++	return;
++}
++EXPORT_SYMBOL(isp_g_fmt_cap);
++
++int isp_s_fmt_cap(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output)
++{
++	int crop_scaling_w = 0;
++	int crop_scaling_h = 0;
++	int rval;
++
++	/* Call Try Size for the ISP */
++	isp_calc_pipeline(pix_input, pix_output);
++	rval = isp_try_size(pix_input, pix_output);
++
++	if (rval)
++		goto out;
++
++	rval = isp_try_fmt(pix_input, pix_output);
++	if (rval)
++		goto out;
++
++	/* Reset crop settings if needed as image size might have changed */
++	if (ispcroprect.width == pix_output->width) {
++		crop_scaling_w = 0;
++	} else {
++		if (ispcroprect.width != 0)
++			crop_scaling_w = 1;
++		ispcroprect.left = 0;
++		ispcroprect.width = pix_output->width;
++	}
++
++	if (ispcroprect.height == pix_output->height) {
++		crop_scaling_h = 0;
++	} else {
++		if (ispcroprect.height != 0)
++			crop_scaling_h = 1;
++		ispcroprect.top = 0;
++		ispcroprect.height = pix_output->height;
++	}
++
++	/* Configure the ISP */
++	isp_config_pipeline(pix_input, pix_output);
++	/* Reapply resizer settings in case a crop is set. */
++	if (crop_scaling_h || crop_scaling_w)
++		isp_config_crop(pix_output);
++out:
++	return rval;
++}
++EXPORT_SYMBOL(isp_s_fmt_cap);
++
++void isp_config_crop(struct v4l2_pix_format *croppix)
++{
++	u8 crop_scaling_w;
++	u8 crop_scaling_h;
++	struct v4l2_pix_format *pix = croppix;
++
++	crop_scaling_w = (ispmodule_obj.preview_output_width * 10) /
++								pix->width;
++	crop_scaling_h = (ispmodule_obj.preview_output_height * 10) /
++								pix->height;
++
++	cur_rect.left = (ispcroprect.left * crop_scaling_w) / 10;
++	cur_rect.top = (ispcroprect.top * crop_scaling_h) / 10;
++	cur_rect.width = (ispcroprect.width * crop_scaling_w) / 10;
++	cur_rect.height = (ispcroprect.height * crop_scaling_h) / 10;
++
++	ispresizer_trycrop(cur_rect.left, cur_rect.top, cur_rect.width,
++					cur_rect.height,
++					ispmodule_obj.resizer_output_width,
++					ispmodule_obj.resizer_output_height);
++	return;
++}
++
++int isp_g_crop(struct v4l2_crop *a)
++{
++	struct v4l2_crop *crop = a;
++
++	crop->c = ispcroprect;
++	return 0;
++}
++EXPORT_SYMBOL(isp_g_crop);
++
++int isp_s_crop(struct v4l2_crop *a, struct v4l2_pix_format *pix)
++{
++	struct v4l2_crop *crop = a;
++	int rval = 0;
++
++	if ((crop->c.left + crop->c.width) > pix->width) {
++		rval = -EINVAL;
++		goto out;
++	}
++
++	if ((crop->c.top + crop->c.height) > pix->height) {
++		rval = -EINVAL;
++		goto out;
++	}
++
++	ispcroprect.left = crop->c.left;
++	ispcroprect.top = crop->c.top;
++	ispcroprect.width = crop->c.width;
++	ispcroprect.height = crop->c.height;
++
++	isp_config_crop(pix);
++
++	ispmodule_obj.applyCrop = 1;
++out:
++	return rval;
++}
++EXPORT_SYMBOL(isp_s_crop);
++
++int isp_try_fmt_cap(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output)
++{
++	int rval = 0;
++
++	isp_calc_pipeline(pix_input, pix_output);
++	rval = isp_try_size(pix_input, pix_output);
++
++	if (rval)
++		goto out;
++
++	rval = isp_try_fmt(pix_input, pix_output);
++
++	if (rval)
++		goto out;
++
++out:
++	return rval;
++}
++EXPORT_SYMBOL(isp_try_fmt_cap);
++
++int isp_try_size(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output)
++{
++	int rval = 0;
++	/*
++	 * First initialize local ISP struct
++	 */
++	ispmodule_obj.ccdc_input_width = pix_input->width;
++	ispmodule_obj.ccdc_input_height = pix_input->height;
++	ispmodule_obj.resizer_output_width = pix_output->width;
++	ispmodule_obj.resizer_output_height = pix_output->height;
++
++	/* Try size for CCDC Module if enabled */
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_CCDC) {
++		rval = ispccdc_try_size(ispmodule_obj.ccdc_input_width,
++					ispmodule_obj.ccdc_input_height,
++					&ispmodule_obj.ccdc_output_width,
++					&ispmodule_obj.ccdc_output_height);
++		pix_output->width = ispmodule_obj.ccdc_output_width;
++		pix_output->height = ispmodule_obj.ccdc_output_height;
++	 }
++
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_PREVIEW) {
++		ispmodule_obj.preview_input_width =
++					ispmodule_obj.ccdc_output_width;
++		ispmodule_obj.preview_input_height =
++					ispmodule_obj.ccdc_output_height;
++		rval = isppreview_try_size(ispmodule_obj.preview_input_width,
++					ispmodule_obj.preview_input_height,
++					&ispmodule_obj.preview_output_width,
++					&ispmodule_obj.preview_output_height);
++		pix_output->width = ispmodule_obj.preview_output_width;
++		pix_output->height = ispmodule_obj.preview_output_height;
++	}
++
++	if (ispmodule_obj.isp_pipeline & OMAP_ISP_RESIZER) {
++		ispmodule_obj.resizer_input_width =
++					ispmodule_obj.preview_output_width;
++		ispmodule_obj.resizer_input_height =
++					ispmodule_obj.preview_output_height;
++		rval = ispresizer_try_size(&ispmodule_obj.resizer_input_width,
++					&ispmodule_obj.resizer_input_height,
++					&ispmodule_obj.resizer_output_width,
++					&ispmodule_obj.resizer_output_height);
++		pix_output->width = ispmodule_obj.resizer_output_width;
++		pix_output->height = ispmodule_obj.resizer_output_height;
++	}
++	return rval;
++}
++EXPORT_SYMBOL(isp_try_size);
++
++int isp_try_fmt(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output)
++{
++	int ifmt;
++
++	/* done with size negotiation, now fill other info */
++	for (ifmt = 0; ifmt < NUM_ISP_CAPTURE_FORMATS; ifmt++) {
++		if (pix_output->pixelformat == isp_formats[ifmt].pixelformat)
++			break;
++	}
++	if (ifmt == NUM_ISP_CAPTURE_FORMATS)
++		ifmt = 1;
++	pix_output->pixelformat = isp_formats[ifmt].pixelformat;
++
++#ifndef ENABLE_BT_656_CAPTURE
++	pix_output->field = V4L2_FIELD_NONE;
++	pix_output->bytesperline = pix_output->width * 2;
++#else
++	pix_output->field = pix_input->field;
++#endif
++
++	pix_output->sizeimage = pix_output->bytesperline * pix_output->height;
++	pix_output->priv = 0;
++	switch (pix_output->pixelformat) {
++	case V4L2_PIX_FMT_YUYV:
++	case V4L2_PIX_FMT_UYVY:
++#ifndef ENABLE_BT_656_CAPTURE
++		pix_output->colorspace = V4L2_COLORSPACE_JPEG;
++#else
++		pix_output->colorspace = pix_input->colorspace;
++#endif
++		break;
++	default:
++		pix_output->colorspace = V4L2_COLORSPACE_SRGB;
++		break;
++	}
++
++	ispmodule_obj.pix.pixelformat = pix_output->pixelformat;
++	ispmodule_obj.pix.width = pix_output->width;
++	ispmodule_obj.pix.height = pix_output->height;
++	ispmodule_obj.pix.field = pix_output->field;
++	ispmodule_obj.pix.bytesperline = pix_output->bytesperline;
++	ispmodule_obj.pix.sizeimage = pix_output->sizeimage;
++	ispmodule_obj.pix.priv = pix_output->priv;
++	ispmodule_obj.pix.colorspace = pix_output->colorspace;
++	return 0;
++}
++
++#ifdef ENABLE_BT_656_CAPTURE
++/* Configure ISP depending on standard */
++int isp_configure_std(v4l2_std_id std)
++{
++	struct isp_std_config_params *params;
++	int rval = 0;
++	struct v4l2_pix_format pix_input, pix_output;
++
++	if (std & V4L2_STD_NTSC) {
++		params = &std_params[0];
++	} else if (std & V4L2_STD_PAL) {
++		params = &std_params[1];
++	} else
++		return -EINVAL;
++
++	ispmodule_obj.pix.pixelformat = params->pixelformat;
++	ispmodule_obj.pix.width = params->active_pixels;
++	ispmodule_obj.pix.height = params->active_lines;
++	ispmodule_obj.pix.field = params->field;
++	ispmodule_obj.pix.bytesperline = params->bytesperline;
++	ispmodule_obj.pix.sizeimage = params->sizeimage;
++	ispmodule_obj.pix.colorspace = params->colorspace;
++
++	if ((std & V4L2_STD_NTSC) || (std & V4L2_STD_PAL)) {
++		pix_input = ispmodule_obj.pix;
++		pix_output = ispmodule_obj.pix;
++	} else
++		return -EINVAL;
++
++	rval = isp_s_fmt_cap(&pix_input, &pix_output);
++
++	return rval;
++}
++EXPORT_SYMBOL(isp_configure_std);
++
++/* Checks for proper pixel parameters */
++int isp_check_format(struct v4l2_pix_format *pixfmt)
++{
++	u32 hpitch, vpitch;
++
++	if (pixfmt->bytesperline <= 0) {
++		DPRINTK_ISPCTRL("Invalid pitch\n");
++		return -EINVAL;
++	}
++
++	hpitch = pixfmt->bytesperline;
++	vpitch = pixfmt->sizeimage / hpitch;
++
++	/* Check for valid value of pitch */
++	if ((hpitch < ispmodule_obj.pix.width * 2) ||
++	    (vpitch < ispmodule_obj.pix.height)) {
++		DPRINTK_ISPCTRL("Invalid pitch\n");
++		return -EINVAL;
++	}
++	/* Check for 32 byte alignment */
++	if (hpitch != (hpitch & ~0x1F)) {
++		DPRINTK_ISPCTRL("Invalid pitch alignment\n");
++		return -EINVAL;
++	}
++	pixfmt->width = ispmodule_obj.pix.width;
++	pixfmt->height = ispmodule_obj.pix.height;
++	return 0;
++}
++EXPORT_SYMBOL(isp_check_format);
++#endif
++
++/**
++ * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
++ *
++ * Routine for saving the context of each module in the ISP.
++ * CCDC, HIST, H3A, PREV, RESZ and MMU.
++ **/
++void isp_save_ctx(void)
++{
++	isp_save_context(isp_reg_list);
++	ispccdc_save_context();
++	isphist_save_context();
++	isph3a_save_context();
++	isppreview_save_context();
++	ispresizer_save_context();
++	ispmmu_save_context();
++}
++EXPORT_SYMBOL(isp_save_ctx);
++
++/**
++ * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
++ *
++ * Routine for restoring the context of each module in the ISP.
++ * CCDC, HIST, H3A, PREV, RESZ and MMU.
++ **/
++void isp_restore_ctx(void)
++{
++	isp_restore_context(isp_reg_list);
++	ispccdc_restore_context();
++	isphist_restore_context();
++	isph3a_restore_context();
++	isppreview_restore_context();
++	ispresizer_restore_context();
++	ispmmu_restore_context();
++}
++EXPORT_SYMBOL(isp_restore_ctx);
++
++/**
++ * isp_get - Adquires the ISP resource.
++ *
++ * Initializes the clocks for the first acquire.
++ **/
++int isp_get(void)
++{
++	int ret_err = 0;
++	DPRINTK_ISPCTRL("isp_get: old %d\n", isp_obj.ref_count);
++	mutex_lock(&(isp_obj.isp_mutex));
++	if (isp_obj.ref_count == 0) {
++#ifdef CONFIG_TRACK_RESOURCES
++		isp_obj.cam_ick = clk_get(&camera_dev, "cam_ick");
++#else
++		isp_obj.cam_ick = clk_get(NULL, "cam_ick");
++#endif
++		if (IS_ERR(isp_obj.cam_ick)) {
++			mutex_unlock(&(isp_obj.isp_mutex));
++			DPRINTK_ISPCTRL("ISP_ERR: clk_get for ick failed\n");
++			return PTR_ERR(isp_obj.cam_ick);
++		}
++#ifndef ENABLE_BT_656_CAPTURE
++#ifdef CONFIG_TRACK_RESOURCES
++		isp_obj.cam_fck = clk_get(&camera_dev, "cam_mclk");
++#else
++		isp_obj.cam_fck = clk_get(NULL, "cam_mclk");
++#endif
++#else
++#ifdef CONFIG_TRACK_RESOURCES
++		isp_obj.cam_fck = clk_get(&camera_dev, "cam_fck");
++#else
++		isp_obj.cam_fck = clk_get(NULL, "cam_fck");
++#endif
++#endif
++		if (IS_ERR(isp_obj.cam_fck)) {
++			mutex_unlock(&(isp_obj.isp_mutex));
++			DPRINTK_ISPCTRL("ISP_ERR: clk_get for fck failed\n");
++			return PTR_ERR(isp_obj.cam_fck);
++		}
++		/* Cam IF Clk */
++		ret_err = clk_enable(isp_obj.cam_ick);
++		if (ret_err) {
++			mutex_unlock(&(isp_obj.isp_mutex));
++			clk_put(isp_obj.cam_ick);
++			clk_put(isp_obj.cam_fck);
++			DPRINTK_ISPCTRL("ISP_ERR: clk_en for ick failed\n");
++			return ret_err;
++		}
++		/* Cam Func Clk */
++		ret_err = clk_enable(isp_obj.cam_fck);
++		if (ret_err) {
++			mutex_unlock(&(isp_obj.isp_mutex));
++			clk_put(isp_obj.cam_ick);
++			clk_put(isp_obj.cam_fck);
++			DPRINTK_ISPCTRL("ISP_ERR: clk_en for fck failed\n");
++			return ret_err;
++		}
++		/* Context restore */
++		if (off_mode == 1)
++			isp_restore_ctx();
++	}
++	isp_obj.ref_count++;
++	mutex_unlock(&(isp_obj.isp_mutex));
++
++
++	DPRINTK_ISPCTRL("isp_get: new %d\n", isp_obj.ref_count);
++	return isp_obj.ref_count;
++}
++EXPORT_SYMBOL(isp_get);
++
++/**
++ * isp_put - Releases the ISP resource.
++ *
++ * Releases the clocks also for the last release.
++ **/
++int isp_put(void)
++{
++	DPRINTK_ISPCTRL("isp_put: old %d\n", isp_obj.ref_count);
++	mutex_lock(&(isp_obj.isp_mutex));
++	if (isp_obj.ref_count)
++		if (--isp_obj.ref_count == 0) {
++			isp_save_ctx();
++			off_mode = 1;
++
++			/* Disable all interrupts */
++			/* shut down ISP clocks */
++			clk_disable(isp_obj.cam_ick);
++			clk_disable(isp_obj.cam_fck);
++			clk_put(isp_obj.cam_ick);
++			clk_put(isp_obj.cam_fck);
++		}
++	mutex_unlock(&(isp_obj.isp_mutex));
++	DPRINTK_ISPCTRL("isp_put: new %d\n", isp_obj.ref_count);
++	return isp_obj.ref_count;
++}
++EXPORT_SYMBOL(isp_put);
++
++/**
++ * isp_save_context - Saves the values of the ISP module registers.
++ * @reg_list: Structure containing pairs of register address and value to
++ *            modify on OMAP.
++ **/
++void isp_save_context(struct isp_reg *reg_list)
++{
++	struct isp_reg *next = reg_list;
++
++	for (; next->reg != ISP_TOK_TERM; next++)
++		next->val = omap_readl(next->reg);
++}
++EXPORT_SYMBOL(isp_save_context);
++
++/**
++ * isp_restore_context - Restores the values of the ISP module registers.
++ * @reg_list: Structure containing pairs of register address and value to
++ *            modify on OMAP.
++ **/
++void isp_restore_context(struct isp_reg *reg_list)
++{
++	struct isp_reg *next = reg_list;
++
++	for (; next->reg != ISP_TOK_TERM; next++)
++		omap_writel(next->val, next->reg);
++}
++EXPORT_SYMBOL(isp_restore_context);
++
++/**
++ * isp_init - ISP module initialization.
++ **/
++static int __init isp_init(void)
++{
++	DPRINTK_ISPCTRL("+isp_init for Omap 3430 Camera ISP\n");
++	isp_obj.ref_count = 0;
++
++	mutex_init(&(isp_obj.isp_mutex));
++	spin_lock_init(&isp_obj.isp_temp_buf_lock);
++
++	if (request_irq(INT_34XX_CAM_IRQ, omap34xx_isp_isr, IRQF_SHARED,
++				"Omap 34xx Camera ISP", &ispirq_obj)) {
++		DPRINTK_ISPCTRL("Could not install ISR\n");
++		return -EINVAL;
++	} else {
++		spin_lock_init(&isp_obj.lock);
++		DPRINTK_ISPCTRL("-isp_init for Omap 3430 Camera ISP\n");
++		return 0;
++	}
++}
++
++/**
++ * isp_cleanup - ISP module cleanup.
++ **/
++static void __exit isp_cleanup(void)
++{
++	free_irq(INT_34XX_CAM_IRQ, &ispirq_obj);
++}
++
++/**
++ * isp_print_status - Prints the values of the ISP Control Module registers
++ *
++ * Also prints other debug information stored in the ISP module structure.
++ **/
++void isp_print_status(void)
++{
++#ifdef	OMAP_ISPCTRL_DEBUG
++	DPRINTK_ISPCTRL("###CM_FCLKEN_CAM=0x%x\n",
++			omap_readl(CM_FCLKEN_CAM));
++	DPRINTK_ISPCTRL("###CM_ICLKEN_CAM=0x%x\n",
++			omap_readl(CM_ICLKEN_CAM));
++	DPRINTK_ISPCTRL("###CM_CLKSEL_CAM=0x%x\n",
++			omap_readl(CM_CLKSEL_CAM));
++	DPRINTK_ISPCTRL("###CM_AUTOIDLE_CAM=0x%x\n",
++			omap_readl(CM_AUTOIDLE_CAM));
++	DPRINTK_ISPCTRL("###CM_CLKEN_PLL[18:16] \
++			should be 0x7, = 0x%x\n",
++			omap_readl(CM_CLKEN_PLL));
++	DPRINTK_ISPCTRL("###CM_CLKSEL2_PLL[18:8] should be 0x2D,\
++			[6:0] should be 1 = 0x%x\n",
++			omap_readl(CM_CLKSEL2_PLL));
++	DPRINTK_ISPCTRL("###CTRL_PADCONF_CAM_HS=0x%x\n",
++			omap_readl(CTRL_PADCONF_CAM_HS));
++	DPRINTK_ISPCTRL("###CTRL_PADCONF_CAM_XCLKA=0x%x\n",
++			omap_readl(CTRL_PADCONF_CAM_XCLKA));
++	DPRINTK_ISPCTRL("###CTRL_PADCONF_CAM_D1=0x%x\n",
++			omap_readl(CTRL_PADCONF_CAM_D1));
++	DPRINTK_ISPCTRL("###CTRL_PADCONF_CAM_D3=0x%x\n",
++			omap_readl(CTRL_PADCONF_CAM_D3));
++	DPRINTK_ISPCTRL("###CTRL_PADCONF_CAM_D5=0x%x\n",
++			omap_readl(CTRL_PADCONF_CAM_D5));
++	DPRINTK_ISPCTRL("###CTRL_PADCONF_CAM_D7=0x%x\n",
++			omap_readl(CTRL_PADCONF_CAM_D7));
++	DPRINTK_ISPCTRL("###CTRL_PADCONF_CAM_D9=0x%x\n",
++			omap_readl(CTRL_PADCONF_CAM_D9));
++	DPRINTK_ISPCTRL("###CTRL_PADCONF_CAM_D11=0x%x\n",
++			omap_readl(CTRL_PADCONF_CAM_D11));
++#endif
++}
++EXPORT_SYMBOL(isp_print_status);
++
++module_init(isp_init);
++module_exit(isp_cleanup);
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("ISP Control Module Library");
++MODULE_LICENSE("GPL");
+Index: git/drivers/media/video/isp/isp.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isp.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,275 @@
++/*
++ * drivers/media/video/isp/isp.h
++ *
++ * Top level public header file for ISP Control module in
++ * TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_TOP_H
++#define OMAP_ISP_TOP_H
++#include <media/videobuf-dma-sg.h>
++#include <linux/videodev2.h>
++#define OMAP_ISP_CCDC    	(1 << 0)
++#define OMAP_ISP_PREVIEW	(1 << 1)
++#define OMAP_ISP_RESIZER	(1 << 2)
++#define OMAP_ISP_AEWB   	(1 << 3)
++#define OMAP_ISP_AF     	(1 << 4)
++#define OMAP_ISP_HIST   	(1 << 5)
++
++/* Define this macro to enable BT.656 capture support. Comment this out when
++   BT.656 capture support is not needed */
++#define ENABLE_BT_656_CAPTURE
++
++/* Our ISP specific controls */
++#define V4L2_CID_PRIVATE_ISP_COLOR_FX     (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_PRIVATE_ISP_CCDC_CFG     (V4L2_CID_PRIVATE_BASE + 1)
++#define V4L2_CID_PRIVATE_ISP_PRV_CFG      (V4L2_CID_PRIVATE_BASE + 2)
++#define V4L2_CID_PRIVATE_ISP_LSC_UPDATE   (V4L2_CID_PRIVATE_BASE + 3)
++#define V4L2_CID_PRIVATE_ISP_AEWB_CFG     (V4L2_CID_PRIVATE_BASE + 4)
++#define V4L2_CID_PRIVATE_ISP_AEWB_REQ     (V4L2_CID_PRIVATE_BASE + 5)
++#define V4L2_CID_PRIVATE_ISP_AF_CFG       (V4L2_CID_PRIVATE_BASE + 6)
++#define V4L2_CID_PRIVATE_ISP_AF_REQ       (V4L2_CID_PRIVATE_BASE + 7)
++#define V4L2_CID_PRIVATE_ISP_HIST_CFG     (V4L2_CID_PRIVATE_BASE + 8)
++#define V4L2_CID_PRIVATE_ISP_HIST_REQ     (V4L2_CID_PRIVATE_BASE + 9)
++
++typedef int (*isp_vbq_callback_ptr) (struct videobuf_buffer *vb);
++typedef void (*isp_callback_t) (unsigned long status,
++					isp_vbq_callback_ptr arg1, void *arg2);
++
++enum isp_interface_type{
++	ISP_PARLL = 1,
++	ISP_CSIA = 2,
++	ISP_CSIB = 4
++};
++enum isp_irqevents{
++	CCDC_VD0 = 0x100,
++	CCDC_VD1 = 0x200,
++	CCDC_VD2 = 0x400,
++	CCDC_ERR = 0x800,
++	H3A_AWB_DONE = 0x2000,
++	H3A_AF_DONE = 0x1000,
++	HIST_DONE = 0x10000,
++	PREV_DONE = 0x100000,
++	LSC_DONE = 0x20000,
++	LSC_PRE_COMP = 0x40000,
++	LSC_PRE_ERR = 0x80000,
++	RESZ_DONE = 0x1000000,
++	SBL_OVF = 0x2000000,
++	MMU_ERR = 0x10000000,
++	OCP_ERR = 0x20000000,
++	HS_VS = 0x80000000
++};
++
++enum isp_callback_type{
++	CBK_CCDC_VD0,
++	CBK_CCDC_VD1,
++	CBK_PREV_DONE,
++	CBK_RESZ_DONE,
++	CBK_MMU_ERR,
++	CBK_H3A_AWB_DONE,
++	CBK_HIST_DONE,
++	CBK_HS_VS,
++	CBK_LSC_ISR,
++	CBK_H3A_AF_DONE
++};
++
++#define ISP_TOK_TERM 	0xFFFFFFFF	/* terminating token for ISP modules
++					 * reg list
++					 */
++#define NUM_SG_DMA (VIDEO_MAX_FRAME+2)
++
++#define ISP_BUF_INIT     0
++#define ISP_FREE_RUNNING 1
++#define ISP_BUF_TRAN     2
++/* defines a structure for isp registers values */
++struct isp_reg {
++	u32 	reg;    /* 32-bit address */
++	u32 	val;	/* 32-bit value */
++};
++
++/* sgdma state for each of the possible videobuf_buffers + 2 overlays */
++struct isp_sgdma_state {
++	/* mapped ISP mmu addrs */
++	dma_addr_t isp_addr;    /* ISP space addr */
++	u32 status;	/* DMA return code */
++	isp_callback_t callback;
++	void *arg;
++};
++
++struct isp_sgdma {
++	dma_addr_t isp_addr_capture[VIDEO_MAX_FRAME];
++	/* scatter-gather DMA management */
++	spinlock_t lock;
++	int free_sgdma;	/* number of free sg dma slots */
++	int next_sgdma;	/* index of next sg dma slot to use */
++	struct isp_sgdma_state sg_state[NUM_SG_DMA];
++};
++
++void isp_open(void);
++
++void isp_close(void);
++
++void isp_start(void);
++
++void isp_stop(void);
++
++void isp_sgdma_init(void);
++
++void isp_vbq_done(unsigned long status, isp_vbq_callback_ptr arg1, void *arg2);
++
++void isp_sgdma_process(struct isp_sgdma *sgdma, int irq, int *dma_notify,
++						isp_vbq_callback_ptr func_ptr);
++
++int isp_sgdma_queue(struct videobuf_dmabuf *vdma, struct videobuf_buffer *vb,
++						int irq, int *dma_notify,
++						isp_vbq_callback_ptr func_ptr);
++
++int isp_vbq_prepare(struct videobuf_queue *vbq, struct videobuf_buffer *vb,
++							enum v4l2_field field);
++
++void isp_vbq_release(struct videobuf_queue *vbq, struct videobuf_buffer *vb);
++/*
++ *Sets the callback for the ISP module done events.*/
++int isp_set_callback(enum isp_callback_type type, isp_callback_t callback,
++					isp_vbq_callback_ptr arg1, void *arg2);
++
++void omapisp_unset_callback(void);
++
++/*Clears  the callback for the ISP module done events. */
++int isp_unset_callback(enum isp_callback_type type);
++
++u32 isp_set_xclk(u32 xclk, u8 xclksel);
++
++u32 isp_get_xclk(u8 xclksel);
++
++int isp_request_interface(enum isp_interface_type if_t);
++
++/* Frees the parallel or serial interface that is passed.*/
++int isp_free_interface(enum isp_interface_type if_t);
++
++struct isp_interface_config {
++	/*0 - Parallell  1- CSIA, 2-CSIB to CCDC */
++	enum isp_interface_type ccdc_par_ser;
++	/*0- Disable, 1 - Enable, first byte->cam_d[7:0],*/
++	/*2 - Enable, first byte -> cam_d[15:8]*/
++	u8 par_bridge;
++	/* 0 - Non Inverted, 1- Inverted*/
++	u8 para_clk_pol;
++	/* 0 - No Shift, 1 -CAMEXT[11:2]->CAM[8:0]*/
++	/* 2 - [11:4]->[7:0]*/
++	u8 dataline_shift;
++	/* 0 - HS Falling, 1-HS rising, 2 - VS falling, 3 - VS rising*/
++	u8 hsvs_syncdetect;
++	/* VD0 Interrupt timing */
++	u16 vdint0_timing;
++	/* VD1 Interrupt timing */
++	u16 vdint1_timing;
++	/* Strobe related parameter*/
++	int strobe;
++	/* PreStrobe related parameter*/
++	int prestrobe;
++	/* Shutter related parameter*/
++	int shutter;
++};
++
++struct isp_sysc	{
++	char reset;
++	char idle_mode;
++};
++
++/* sysconfig settings */
++void isp_power_settings(struct isp_sysc);
++
++/* Configures the ISP Control interace related parameters.*/
++int isp_configure_interface(struct isp_interface_config *config);
++
++void isp_CCDC_VD01_disable(void);
++void isp_CCDC_VD01_enable(void);
++
++/*  Acquires the ISP resource. Initialises the clocks for the first aquire.*/
++int isp_get(void);
++
++/* Releases the ISP resource. Releases the clocks also for the last release.*/
++int isp_put(void);
++
++/* Set up ISP pipeline */
++void isp_set_pipeline(int soc_type);
++
++/* Config ISP pipeline */
++void isp_config_pipeline(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output);
++
++/* Query Control */
++int isp_queryctrl(struct v4l2_queryctrl *a);
++
++/* Get Control */
++int isp_g_ctrl(struct v4l2_control *a);
++
++/* Set Control */
++int isp_s_ctrl(struct v4l2_control *a);
++/* Enum format capture for ISP */
++int isp_enum_fmt_cap(struct v4l2_fmtdesc *f);
++
++/* try Format capture for ISP */
++int isp_try_fmt_cap(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output);
++
++/* Get format for ISP sub-modules */
++void isp_g_fmt_cap(struct v4l2_format *f);
++/* Set format for ISP sub-modules */
++int isp_s_fmt_cap(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output);
++
++/* Get Crop capabilities */
++int isp_g_crop(struct v4l2_crop *a);
++
++/* Set Crop capabilities */
++int isp_s_crop(struct v4l2_crop *a, struct v4l2_pix_format *pix);
++
++/* Config crop */
++void isp_config_crop(struct v4l2_pix_format *pix);
++
++/* Try Size for ISP sub-modules */
++int isp_try_size(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output);
++
++/* Try Format for ISP */
++int isp_try_fmt(struct v4l2_pix_format *pix_input,
++					struct v4l2_pix_format *pix_output);
++
++#ifdef ENABLE_BT_656_CAPTURE
++/* Configure ISP depending on standard */
++int isp_configure_std(v4l2_std_id std);
++
++/* Checks for proper pixel parameters */
++int isp_check_format(struct v4l2_pix_format *pixfmt);
++#endif
++
++/*Saves ISP context*/
++void isp_save_context(struct isp_reg *);
++
++/*Restores ISP context*/
++void isp_restore_context(struct isp_reg *);
++
++/*Saves ISP context*/
++void isp_save_ctx(void);
++
++/*Restores ISP context*/
++void isp_restore_ctx(void);
++
++
++void isp_print_status(void);
++
++
++
++#endif	/* OMAP_ISP_TOP_H */
+Index: git/drivers/media/video/isp/isp_af.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isp_af.c	2009-02-12 10:29:18.000000000 -0600
+@@ -0,0 +1,829 @@
++/*
++ * drivers/media/video/isp/isp_af.c
++ *
++ * AF module for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++/* Linux specific include files */
++#include <linux/cdev.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <asm/cacheflush.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++/*#include <asm/arch/io.h>*/
++
++/*#include <linux/mm.h>*/
++#include <linux/mman.h>
++#include <linux/syscalls.h>
++/*#include <linux/module.h>*/
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++/*#include <asm/io.h>*/
++/*#include <asm/cacheflush.h>*/
++/*#include <asm/uaccess.h>*/
++
++#include "isp.h"
++#include "ispreg.h"
++#include "isph3a.h"
++#include "isp_af.h"
++#include "ispmmu.h"
++#include "../dw9710.h"
++
++/**
++ * struct isp_af_buffer - AF frame stats buffer.
++ * @virt_addr: Virtual address to mmap the buffer.
++ * @phy_addr: Physical address of the buffer.
++ * @addr_align: Virtual Address 32 bytes aligned.
++ * @ispmmu_addr: Address of the buffer mapped by the ISPMMU.
++ * @mmap_addr: Mapped memory area of buffer. For userspace access.
++ * @locked: 1 - Buffer locked from write. 0 - Buffer can be overwritten.
++ * @frame_num: Frame number from which the statistics are taken.
++ * @lens_position: Lens position currently set in the DW9710 Coil motor driver.
++ * @next: Pointer to link next buffer.
++ */
++struct isp_af_buffer {
++	unsigned long virt_addr;
++	unsigned long phy_addr;
++	unsigned long addr_align;
++	unsigned long ispmmu_addr;
++	unsigned long mmap_addr;
++
++	u8 locked;
++	u16 frame_num;
++	struct isp_af_xtrastats xtrastats;
++	struct isp_af_buffer *next;
++};
++
++/**
++ * struct isp_af_status - AF status.
++ * @initialized: 1 - Buffers initialized.
++ * @update: 1 - Update registers.
++ * @stats_req: 1 - Future stats requested.
++ * @stats_done: 1 - Stats ready for user.
++ * @frame_req: Number of frame requested for statistics.
++ * @af_buff: Array of statistics buffers to access.
++ * @stats_buf_size: Statistics buffer size.
++ * @min_buf_size: Minimum statisitics buffer size.
++ * @frame_count: Frame Count.
++ * @stats_wait: Wait primitive for locking/unlocking the stats request.
++ * @buffer_lock: Spinlock for statistics buffers access.
++ */
++static struct isp_af_status {
++	u8 initialized;
++	u8 update;
++	u8 stats_req;
++	u8 stats_done;
++	u16 frame_req;
++
++	struct isp_af_buffer af_buff[H3A_MAX_BUFF];
++	unsigned int stats_buf_size;
++	unsigned int min_buf_size;
++
++	u32 frame_count;
++	wait_queue_head_t stats_wait;
++	spinlock_t buffer_lock;
++} afstat;
++
++struct af_device *af_dev_configptr;
++static struct isp_af_buffer *active_buff;
++static int af_major = -1;
++static int camnotify;
++
++
++/**
++ * isp_af_setxtrastats - Receives extra statistics from prior frames.
++ * @xtrastats: Pointer to structure containing extra statistics fields like
++ *             field count and timestamp of frame.
++ *
++ * Called from update_vbq in camera driver
++ **/
++void isp_af_setxtrastats(struct isp_af_xtrastats *xtrastats, u8 updateflag)
++{
++	int i, past_i;
++
++	if (active_buff == NULL)
++		return;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if (afstat.af_buff[i].frame_num == active_buff->frame_num)
++			break;
++	}
++
++	if (i == H3A_MAX_BUFF)
++		return;
++
++	if (i == 0) {
++		if (afstat.af_buff[H3A_MAX_BUFF - 1].locked == 0)
++			past_i = H3A_MAX_BUFF - 1;
++		else
++			past_i = H3A_MAX_BUFF - 2;
++	} else if (i == 1) {
++		if (afstat.af_buff[0].locked == 0)
++			past_i = 0;
++		else
++			past_i = H3A_MAX_BUFF - 1;
++	} else {
++		if (afstat.af_buff[i - 1].locked == 0)
++			past_i = i - 1;
++		else
++			past_i = i - 2;
++	}
++
++	if (updateflag & AF_UPDATEXS_TS)
++		afstat.af_buff[past_i].xtrastats.ts = xtrastats->ts;
++
++	if (updateflag & AF_UPDATEXS_FIELDCOUNT)
++		afstat.af_buff[past_i].xtrastats.field_count =
++							xtrastats->field_count;
++}
++EXPORT_SYMBOL(isp_af_setxtrastats);
++
++/*
++ * Helper function to update buffer cache pages
++ */
++static void isp_af_update_req_buffer(struct isp_af_buffer *buffer)
++{
++	int size = afstat.stats_buf_size;
++
++	size = PAGE_ALIGN(size);
++	/* Update the kernel pages of the requested buffer */
++	dmac_inv_range((void *)buffer->addr_align, (void *)buffer->addr_align +
++									size);
++}
++
++/* Function to check paxel parameters */
++int isp_af_check_paxel(void)
++{
++	/* Check horizontal Count */
++	if ((af_dev_configptr->config->paxel_config.hz_cnt
++	     < AF_PAXEL_HORIZONTAL_COUNT_MIN)
++	    || (af_dev_configptr->config->paxel_config.hz_cnt
++		> AF_PAXEL_HORIZONTAL_COUNT_MAX)) {
++		DPRINTK_ISPH3A("Error : Horizontal Count is incorrect");
++		return -AF_ERR_HZ_COUNT;
++	}
++
++	/*Check Vertical Count */
++	if ((af_dev_configptr->config->paxel_config.vt_cnt
++	     < AF_PAXEL_VERTICAL_COUNT_MIN)
++	    || (af_dev_configptr->config->paxel_config.vt_cnt
++		> AF_PAXEL_VERTICAL_COUNT_MAX)) {
++		DPRINTK_ISPH3A("Error : Vertical Count is incorrect");
++		return -AF_ERR_VT_COUNT;
++	}
++
++	/*Check Height */
++	if ((af_dev_configptr->config->paxel_config.height
++	     < AF_PAXEL_HEIGHT_MIN)
++	    || (af_dev_configptr->config->paxel_config.height
++		> AF_PAXEL_HEIGHT_MAX)) {
++		DPRINTK_ISPH3A("Error : Height is incorrect");
++		return -AF_ERR_HEIGHT;
++	}
++
++	/*Check width */
++	if ((af_dev_configptr->config->paxel_config.width < AF_PAXEL_WIDTH_MIN)
++	    || (af_dev_configptr->config->paxel_config.width
++		> AF_PAXEL_WIDTH_MAX)) {
++		DPRINTK_ISPH3A("Error : Width is incorrect");
++		return -AF_ERR_WIDTH;
++	}
++
++	/*Check Line Increment */
++	if ((af_dev_configptr->config->paxel_config.line_incr
++	     < AF_PAXEL_INCREMENT_MIN)
++	    || (af_dev_configptr->config->paxel_config.line_incr
++		> AF_PAXEL_INCREMENT_MAX)) {
++		DPRINTK_ISPH3A("Error : Line Increment is incorrect");
++		return -AF_ERR_INCR;
++	}
++
++	/*Check Horizontal Start */
++	if ((af_dev_configptr->config->paxel_config.hz_start % 2 != 0)
++	    || (af_dev_configptr->config->paxel_config.hz_start
++		< (af_dev_configptr->config->iir_config.hz_start_pos + 2))
++	    || (af_dev_configptr->config->paxel_config.hz_start
++		> AF_PAXEL_HZSTART_MAX)
++	    || (af_dev_configptr->config->paxel_config.hz_start
++		< AF_PAXEL_HZSTART_MIN)) {
++		DPRINTK_ISPH3A("Error : Horizontal Start is incorrect");
++		return -AF_ERR_HZ_START;
++	}
++
++	/*Check Vertical Start */
++	if ((af_dev_configptr->config->paxel_config.vt_start
++	     < AF_PAXEL_VTSTART_MIN)
++	    || (af_dev_configptr->config->paxel_config.vt_start
++		> AF_PAXEL_VTSTART_MAX)) {
++		DPRINTK_ISPH3A("Error : Vertical Start is incorrect");
++		return -AF_ERR_VT_START;
++	}
++	return 0;		/*Success */
++}
++
++/**
++ * isp_af_check_iir - Function to check IIR Coefficient.
++ **/
++int isp_af_check_iir(void)
++{
++	int index;
++
++	for (index = 0; index < AF_NUMBER_OF_COEF; index++) {
++		if ((af_dev_configptr->config->iir_config.coeff_set0[index])
++		    > AF_COEF_MAX) {
++			DPRINTK_ISPH3A(
++				"Error : Coefficient for set 0 is incorrect");
++			return -AF_ERR_IIR_COEF;
++		}
++
++		if ((af_dev_configptr->config->iir_config.coeff_set1[index])
++		    > AF_COEF_MAX) {
++			DPRINTK_ISPH3A(
++				"Error : Coefficient for set 1 is incorrect");
++			return -AF_ERR_IIR_COEF;
++		}
++	}
++
++	if ((af_dev_configptr->config->iir_config.hz_start_pos < AF_IIRSH_MIN)
++	    || (af_dev_configptr->config->iir_config.hz_start_pos >
++		AF_IIRSH_MAX)) {
++		DPRINTK_ISPH3A("Error : IIRSH is incorrect");
++		return -AF_ERR_IIRSH;
++	}
++
++	return 0;
++}
++/**
++ * isp_af_unlock_buffers - Helper function to unlock all buffers.
++ **/
++static void isp_af_unlock_buffers(void)
++{
++	int i;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&afstat.buffer_lock, irqflags);
++	for (i = 0; i < H3A_MAX_BUFF; i++)
++		afstat.af_buff[i].locked = 0;
++
++	spin_unlock_irqrestore(&afstat.buffer_lock, irqflags);
++}
++
++/*
++ * Helper function to link allocated buffers
++ */
++static void isp_af_link_buffers(void)
++{
++	int i;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if ((i + 1) < H3A_MAX_BUFF)
++			afstat.af_buff[i].next = &afstat.af_buff[i + 1];
++		else
++			afstat.af_buff[i].next = &afstat.af_buff[0];
++	}
++}
++
++/*
++ * Helper function to munmap kernel buffers from user space.
++ */
++static int isp_af_munmap(struct isp_af_buffer *buffer)
++{
++	/* TO DO: munmap succesfully the kernel buffers, so they can be
++	   remmaped again */
++	buffer->mmap_addr = 0;
++	return 0;
++}
++
++/*
++ * Helper function to mmap buffers to user space.
++ * buffer passed need to already have a valid physical address: buffer->phy_addr
++ * It returns user pointer as unsigned long in buffer->mmap_addr
++ */
++static int isp_af_mmap_buffers(struct isp_af_buffer *buffer)
++{
++	struct vm_area_struct vma;
++	struct mm_struct *mm = current->mm;
++	int size = afstat.stats_buf_size;
++	unsigned long addr = 0;
++	unsigned long pgoff = 0, flags = MAP_SHARED | MAP_ANONYMOUS;
++	unsigned long prot = PROT_READ | PROT_WRITE;
++	void *pos = (void *)buffer->addr_align;
++
++	size = PAGE_ALIGN(size);
++
++	addr = get_unmapped_area(NULL, addr, size, pgoff, flags);
++	vma.vm_mm = mm;
++	vma.vm_start = addr;
++	vma.vm_end = addr + size;
++	vma.vm_flags = calc_vm_prot_bits(prot) | calc_vm_flag_bits(flags);
++	vma.vm_pgoff = pgoff;
++	vma.vm_file = NULL;
++	vma.vm_page_prot = protection_map[vma.vm_flags];
++
++	while (size > 0) {
++		if (vm_insert_page(&vma, addr, vmalloc_to_page(pos)))
++			return -EAGAIN;
++		addr += PAGE_SIZE;
++		pos += PAGE_SIZE;
++		size -= PAGE_SIZE;
++	}
++
++	buffer->mmap_addr = vma.vm_start;
++	return 0;
++}
++
++/* Function to perform hardware set up */
++int isp_af_configure(struct af_configuration *afconfig)
++{
++	int result;
++	int buff_size, i;
++	unsigned int busyaf;
++
++	if (NULL == afconfig) {
++		printk(KERN_ERR "Null argument in configuration. \n");
++		return -EINVAL;
++	}
++
++	af_dev_configptr->config = afconfig;
++	/* Get the value of PCR register */
++	busyaf = omap_readl(ISPH3A_PCR);
++
++	if ((busyaf & AF_BUSYAF) == AF_BUSYAF) {
++		DPRINTK_ISPH3A("AF_register_setup_ERROR : Engine Busy");
++		DPRINTK_ISPH3A("\n Configuration cannot be done ");
++		return -AF_ERR_ENGINE_BUSY;
++	}
++
++	/*Check IIR Coefficient and start Values */
++	result = isp_af_check_iir();
++	if (result < 0)
++		return result;
++
++	/*Check Paxel Values */
++	result = isp_af_check_paxel();
++	if (result < 0)
++		return result;
++
++	/*Check HMF Threshold Values */
++	if (af_dev_configptr->config->hmf_config.threshold > AF_THRESHOLD_MAX) {
++		DPRINTK_ISPH3A("Error : HMF Threshold is incorrect");
++		return -AF_ERR_THRESHOLD;
++	}
++
++	/* Compute buffer size */
++	buff_size =
++	    (af_dev_configptr->config->paxel_config.hz_cnt + 1) *
++	    (af_dev_configptr->config->paxel_config.vt_cnt + 1) * AF_PAXEL_SIZE;
++
++	/*Deallocate the previous buffers */
++	if (afstat.stats_buf_size && (buff_size	> afstat.stats_buf_size)) {
++		isp_af_enable(0);
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			isp_af_munmap(&afstat.af_buff[i]);
++			ispmmu_unmap(afstat.af_buff[i].ispmmu_addr);
++			dma_free_coherent(NULL,
++				  afstat.min_buf_size + 64,
++				  (void *)afstat.af_buff[i].virt_addr,
++				  (dma_addr_t)afstat.af_buff[i].phy_addr);
++			afstat.af_buff[i].virt_addr = 0;
++		}
++		afstat.stats_buf_size = 0;
++	}
++
++	if (!afstat.af_buff[0].virt_addr) {
++		afstat.stats_buf_size = buff_size;
++		afstat.min_buf_size = PAGE_ALIGN(afstat.stats_buf_size);
++
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			afstat.af_buff[i].virt_addr =
++				(unsigned long)dma_alloc_coherent(NULL,
++						afstat.min_buf_size,
++						(dma_addr_t *)
++						 &afstat.af_buff[i].phy_addr,
++						GFP_KERNEL | GFP_DMA);
++			if (afstat.af_buff[i].virt_addr == 0) {
++				printk(KERN_ERR "Can't acquire memory for "
++					"buffer[%d]\n", i);
++				return -ENOMEM;
++			}
++			afstat.af_buff[i].addr_align =
++					afstat.af_buff[i].virt_addr;
++			while ((afstat.af_buff[i].addr_align & 0xFFFFFFC0) !=
++				       afstat.af_buff[i].addr_align)
++				afstat.af_buff[i].addr_align++;
++			afstat.af_buff[i].ispmmu_addr =
++				ispmmu_map(afstat.af_buff[i].phy_addr,
++					   afstat.min_buf_size);
++		}
++		isp_af_unlock_buffers();
++		isp_af_link_buffers();
++
++		/* First active buffer */
++		if (active_buff == NULL)
++			active_buff = &afstat.af_buff[0];
++		isp_af_set_address(active_buff->ispmmu_addr);
++	}
++	/* Always remap when calling Configure */
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if (afstat.af_buff[i].mmap_addr)
++			isp_af_munmap(&afstat.af_buff[i]);
++		isp_af_mmap_buffers(&afstat.af_buff[i]);
++	}
++
++	result = isp_af_register_setup(af_dev_configptr);
++	if (result < 0)
++		return result;
++	af_dev_configptr->size_paxel = buff_size;
++	afstat.initialized = 1;
++	/*Set configuration flag to indicate HW setup done */
++	if (af_dev_configptr->config->af_config)
++		isp_af_enable(1);
++	else
++		isp_af_enable(0);
++
++	/*Success */
++	return 0;
++}
++EXPORT_SYMBOL(isp_af_configure);
++
++int isp_af_register_setup(struct af_device *af_dev)
++{
++	unsigned int pcr = 0, pax1 = 0, pax2 = 0, paxstart = 0;
++	unsigned int coef = 0;
++	unsigned int base_coef_set0 = 0;
++	unsigned int base_coef_set1 = 0;
++	int index;
++
++
++	/* Configure Hardware Registers */
++	/* Set PCR Register */
++	pcr = omap_readl(ISPH3A_PCR);	/* Read PCR Register */
++
++	/*Set Accumulator Mode */
++	if (af_dev->config->mode == ACCUMULATOR_PEAK)
++		pcr |= FVMODE;
++	else
++		pcr &= ~FVMODE;
++
++	/*Set A-law */
++	if (af_dev->config->alaw_enable == H3A_AF_ALAW_ENABLE)
++		pcr |= AF_ALAW_EN;
++	else
++		pcr &= ~AF_ALAW_EN;
++
++	/*Set RGB Position */
++	pcr &= ~RGBPOS;
++	pcr |= (af_dev->config->rgb_pos) << AF_RGBPOS_SHIFT;
++
++	/*HMF Configurations */
++	if (af_dev->config->hmf_config.enable == H3A_AF_HMF_ENABLE) {
++		pcr &= ~AF_MED_EN;
++		/* Enable HMF */
++		pcr |= AF_MED_EN;
++
++		/* Set Median Threshold */
++		pcr &= ~MED_TH;
++		pcr |=
++		    (af_dev->config->hmf_config.threshold) << AF_MED_TH_SHIFT;
++	} else
++		pcr &= ~AF_MED_EN;
++
++	omap_writel(pcr, ISPH3A_PCR);
++
++	pax1 &= ~PAXW;
++	pax1 |= (af_dev->config->paxel_config.width) << AF_PAXW_SHIFT;
++
++	/* Set height in AFPAX1 */
++	pax1 &= ~PAXH;
++	pax1 |= af_dev->config->paxel_config.height;
++
++	omap_writel(pax1, ISPH3A_AFPAX1);
++
++	/* Configure AFPAX2 Register */
++	/* Set Line Increment in AFPAX2 Register */
++	pax2 &= ~AFINCV;
++	pax2 |= (af_dev->config->paxel_config.line_incr) << AF_LINE_INCR_SHIFT;
++	/* Set Vertical Count */
++	pax2 &= ~PAXVC;
++	pax2 |= (af_dev->config->paxel_config.vt_cnt) << AF_VT_COUNT_SHIFT;
++	/* Set Horizontal Count */
++	pax2 &= ~PAXHC;
++	pax2 |= af_dev->config->paxel_config.hz_cnt;
++	omap_writel(pax2, ISPH3A_AFPAX2);
++
++	/* Configure PAXSTART Register */
++	/*Configure Horizontal Start */
++	paxstart &= ~PAXSH;
++	paxstart |=
++	    (af_dev->config->paxel_config.hz_start) << AF_HZ_START_SHIFT;
++	/* Configure Vertical Start */
++	paxstart &= ~PAXSV;
++	paxstart |= af_dev->config->paxel_config.vt_start;
++	omap_writel(paxstart, ISPH3A_AFPAXSTART);
++
++	/*SetIIRSH Register */
++	omap_writel(af_dev->config->iir_config.hz_start_pos, ISPH3A_AFIIRSH);
++
++	/*Set IIR Filter0 Coefficients */
++	base_coef_set0 = ISPH3A_AFCOEF010;
++	for (index = 0; index <= 8; index += 2) {
++		coef &= ~COEF_MASK0;
++		coef |= af_dev->config->iir_config.coeff_set0[index];
++		coef &= ~COEF_MASK1;
++		coef |=
++		    (af_dev->config->iir_config.
++		     coeff_set0[index + 1]) << AF_COEF_SHIFT;
++		omap_writel(coef, base_coef_set0);
++
++		base_coef_set0 = base_coef_set0 + AFCOEF_OFFSET;
++	}
++
++	/* set AFCOEF0010 Register */
++	omap_writel(af_dev->config->iir_config.coeff_set0[10],
++							ISPH3A_AFCOEF010);
++
++	/*Set IIR Filter1 Coefficients */
++
++	base_coef_set1 = ISPH3A_AFCOEF110;
++	for (index = 0; index <= 8; index += 2) {
++		coef &= ~COEF_MASK0;
++		coef |= af_dev->config->iir_config.coeff_set1[index];
++		coef &= ~COEF_MASK1;
++		coef |=
++		    (af_dev->config->iir_config.
++		     coeff_set1[index + 1]) << AF_COEF_SHIFT;
++		omap_writel(coef, base_coef_set1);
++
++		base_coef_set1 = base_coef_set1 + AFCOEF_OFFSET;
++	}
++	omap_writel(af_dev->config->iir_config.coeff_set1[10],
++							ISPH3A_AFCOEF1010);
++
++	return 0;
++}
++
++/* Function to set address */
++void isp_af_set_address(unsigned long address)
++{
++	omap_writel(address, ISPH3A_AFBUFST);
++}
++
++static int isp_af_stats_available(struct isp_af_data *afdata)
++{
++	int i;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&afstat.buffer_lock, irqflags);
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if ((afdata->frame_number == afstat.af_buff[i].frame_num)
++			&& (afstat.af_buff[i].frame_num !=
++				active_buff->frame_num)) {
++			afstat.af_buff[i].locked = 1;
++			spin_unlock_irqrestore(&afstat.buffer_lock, irqflags);
++			isp_af_update_req_buffer(&afstat.af_buff[i]);
++			afstat.af_buff[i].frame_num = 0;
++			afdata->af_statistics_buf = (void *)
++				afstat.af_buff[i].mmap_addr;
++			afdata->xtrastats.ts = afstat.af_buff[i].xtrastats.ts;
++			afdata->xtrastats.field_count =
++				afstat.af_buff[i].xtrastats.field_count;
++			afdata->xtrastats.lens_position =
++				afstat.af_buff[i].xtrastats.lens_position;
++			return 0;
++		}
++	}
++	spin_unlock_irqrestore(&afstat.buffer_lock, irqflags);
++	/* Stats unavailable */
++
++	afdata->af_statistics_buf = NULL;
++	return -1;
++}
++
++void isp_af_notify(int notify)
++{
++	camnotify = notify;
++	if (camnotify && afstat.initialized) {
++		printk(KERN_DEBUG "Warning Camera Off \n");
++		afstat.stats_req = 0;
++		afstat.stats_done = 1;
++		wake_up_interruptible(&afstat.stats_wait);
++	}
++}
++EXPORT_SYMBOL(isp_af_notify);
++/*
++ * This API allows the user to update White Balance gains, as well as
++ * exposure time and analog gain. It is also used to request frame
++ * statistics.
++ */
++int isp_af_request_statistics(struct isp_af_data *afdata)
++{
++	int ret = 0;
++	u16 frame_diff = 0;
++	u16 frame_cnt = afstat.frame_count;
++	wait_queue_t wqt;
++
++	if (!af_dev_configptr->config->af_config) {
++		printk(KERN_ERR "AF engine not enabled\n");
++		return -EINVAL;
++	}
++	afdata->af_statistics_buf = NULL;
++
++	if (afdata->update != 0) {
++		if (afdata->update & REQUEST_STATISTICS) {
++			isp_af_unlock_buffers();
++				/* Stats available? */
++			DPRINTK_ISPH3A("Stats available?\n");
++			ret = isp_af_stats_available(afdata);
++			if (!ret)
++				goto out;
++
++			/* Stats in near future? */
++			DPRINTK_ISPH3A("Stats in near future?\n");
++			if (afdata->frame_number > frame_cnt) {
++				frame_diff = afdata->frame_number - frame_cnt;
++			} else if (afdata->frame_number < frame_cnt) {
++				if ((frame_cnt >
++					(MAX_FRAME_COUNT - MAX_FUTURE_FRAMES))
++					&& (afdata->frame_number
++						< MAX_FRAME_COUNT))
++					frame_diff = afdata->frame_number
++						    + MAX_FRAME_COUNT
++						    - frame_cnt;
++				else {
++					/* Frame unavailable */
++					frame_diff = MAX_FUTURE_FRAMES + 1;
++					afdata->af_statistics_buf = NULL;
++				}
++			}
++
++			if (frame_diff > MAX_FUTURE_FRAMES) {
++				printk(KERN_ERR "Invalid frame requested\n");
++			} else if (!camnotify) {
++				/* Block until frame in near future completes */
++				afstat.frame_req = afdata->frame_number;
++				afstat.stats_req = 1;
++				afstat.stats_done = 0;
++				init_waitqueue_entry(&wqt, current);
++				ret =
++				   wait_event_interruptible(afstat.stats_wait,
++						afstat.stats_done == 1);
++				if (ret < 0)
++					return ret;
++			DPRINTK_ISPH3A("ISP AF request status"
++						" interrupt raised\n");
++
++				/* Stats now available */
++				ret = isp_af_stats_available(afdata);
++				if (ret) {
++					printk(KERN_ERR "After waiting for"
++						" stats, stats not available!!"
++						"\n");
++				}
++			}
++		}
++	}
++
++out:
++	afdata->curr_frame = afstat.frame_count;
++
++	return 0;
++}
++EXPORT_SYMBOL(isp_af_request_statistics);
++
++/* This function will handle the H3A interrupt. */
++static void isp_af_isr(unsigned long status, isp_vbq_callback_ptr arg1,
++								void *arg2)
++{
++	u16 frame_align;
++
++	if ((H3A_AF_DONE & status) != H3A_AF_DONE)
++		return;
++
++	/* Exchange buffers */
++	active_buff = active_buff->next;
++	if (active_buff->locked == 1)
++		active_buff = active_buff->next;
++	isp_af_set_address(active_buff->ispmmu_addr);
++
++	/* Update frame counter */
++	afstat.frame_count++;
++	frame_align = afstat.frame_count;
++	if (afstat.frame_count > MAX_FRAME_COUNT) {
++		afstat.frame_count = 1;
++		frame_align++;
++	}
++	active_buff->frame_num = afstat.frame_count;
++
++	dw9710_af_getfocus_cached(&active_buff->xtrastats.lens_position);
++	/* Future Stats requested? */
++	if (afstat.stats_req) {
++		/* Is the frame we want already done? */
++		if (frame_align >= (afstat.frame_req + 1)) {
++			afstat.stats_req = 0;
++			afstat.stats_done = 1;
++			wake_up_interruptible(&afstat.stats_wait);
++		}
++	}
++}
++
++/* Function to Enable/Disable AF Engine */
++int isp_af_enable(int enable)
++{
++	unsigned int pcr;
++
++	pcr = omap_readl(ISPH3A_PCR);
++
++	/* Set AF_EN bit in PCR Register */
++	if (enable) {
++		if (isp_set_callback(CBK_H3A_AF_DONE, isp_af_isr,
++						(void *)NULL, (void *)NULL)) {
++			printk(KERN_ERR "No callback for AF\n");
++			return -EINVAL;
++		}
++
++		pcr |= AF_EN;
++	} else {
++		isp_unset_callback(CBK_H3A_AF_DONE);
++		pcr &= ~AF_EN;
++	}
++	mdelay(100);
++	omap_writel(pcr, ISPH3A_PCR);
++	return 0;
++}
++
++/* Function to register the AF character device driver. */
++int __init isp_af_init(void)
++{
++	/*allocate memory for device structure and initialize it with 0 */
++	af_dev_configptr = kzalloc(sizeof(struct af_device), GFP_KERNEL);
++	if (!af_dev_configptr)
++		goto err_nomem1;
++
++	active_buff = NULL;
++
++	af_dev_configptr->config = (struct af_configuration *)
++			kzalloc(sizeof(struct af_configuration), GFP_KERNEL);
++
++	if (af_dev_configptr->config == NULL)
++		goto err_nomem2;
++
++	printk(KERN_DEBUG "isp_af_init\n");
++	memset(&afstat, 0, sizeof(afstat));
++
++	init_waitqueue_head(&afstat.stats_wait);
++	spin_lock_init(&afstat.buffer_lock);
++
++	return 0;
++
++err_nomem2:
++	kfree(af_dev_configptr);
++err_nomem1:
++	printk(KERN_ERR "Error: kmalloc fail");
++	return -ENOMEM;
++}
++
++void __exit isp_af_exit(void)
++{
++	int i;
++
++	if (afstat.af_buff) {
++	/* Free buffers */
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			ispmmu_unmap(afstat.af_buff[i].ispmmu_addr);
++			dma_free_coherent(NULL,
++				afstat.min_buf_size + 64,
++				(void *)afstat.af_buff[i].virt_addr,
++				(dma_addr_t)afstat.af_buff[i].phy_addr);
++		}
++	}
++	kfree(af_dev_configptr->config);
++	kfree(af_dev_configptr);
++
++	memset(&afstat, 0, sizeof(afstat));
++
++	af_major = -1;
++	isp_af_enable(0);
++}
++
++module_init(isp_af_init)
++module_exit(isp_af_exit)
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("AF ISP Module");
++MODULE_LICENSE("GPL");
+Index: git/drivers/media/video/isp/isp_af.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isp_af.h	2009-02-12 16:32:13.000000000 -0600
+@@ -0,0 +1,258 @@
++/*
++ * drivers/media/video/isp/isp_af.h
++ *
++ * Include file for AF module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++/* Device Constants */
++#ifndef OMAP_ISP_AF_H
++#define OMAP_ISP_AF_H
++
++#define AF_MAJOR_NUMBER			0
++#define ISPAF_NAME			"OMAPISP_AF"
++#define AF_NR_DEVS			1
++#define AF_TIMEOUT			(300 * HZ) / 1000
++
++
++/* Range Constants */
++#define AF_IIRSH_MIN			0
++#define AF_IIRSH_MAX			4094
++#define AF_PAXEL_HORIZONTAL_COUNT_MIN	0
++#define AF_PAXEL_HORIZONTAL_COUNT_MAX	35
++#define AF_PAXEL_VERTICAL_COUNT_MIN	0
++#define AF_PAXEL_VERTICAL_COUNT_MAX	127
++#define AF_PAXEL_INCREMENT_MIN		0
++#define AF_PAXEL_INCREMENT_MAX		14
++#define AF_PAXEL_HEIGHT_MIN		0
++#define AF_PAXEL_HEIGHT_MAX		127
++#define AF_PAXEL_WIDTH_MIN		0
++#define AF_PAXEL_WIDTH_MAX		127
++#define AF_PAXEL_HZSTART_MIN		2
++#define AF_PAXEL_HZSTART_MAX		4094
++
++#define AF_PAXEL_VTSTART_MIN		0
++#define AF_PAXEL_VTSTART_MAX		4095
++#define AF_THRESHOLD_MAX		255
++#define AF_COEF_MAX			4095
++#define AF_PAXEL_SIZE			48
++
++/* Print Macros */
++/*list of error code */
++#define AF_ERR_HZ_COUNT			800	/* Invalid Horizontal Count */
++#define AF_ERR_VT_COUNT			801	/* Invalid Vertical Count */
++#define AF_ERR_HEIGHT			802	/* Invalid Height */
++#define AF_ERR_WIDTH			803	/* Invalid width */
++#define AF_ERR_INCR			804	/* Invalid Increment */
++#define AF_ERR_HZ_START			805	/* Invalid horizontal Start */
++#define AF_ERR_VT_START			806	/* Invalud vertical Start */
++#define AF_ERR_IIRSH			807	/* Invalid IIRSH value */
++#define AF_ERR_IIR_COEF			808	/* Invalid Coefficient */
++#define AF_ERR_SETUP			809	/* Setup not done */
++#define AF_ERR_THRESHOLD		810	/* Invalid Threshold */
++#define AF_ERR_ENGINE_BUSY		811	/* Engine is busy */
++#define AF_NUMBER_OF_COEF		11
++/* list of ioctls */
++#pragma pack(1)
++
++#pragma pack()
++#define AFPID				0x0	/* Peripheral Revision
++						 * and Class Information
++						 */
++
++#define AFCOEF_OFFSET			0x00000004	/* COEFFICIENT BASE
++							 * ADDRESS
++							 */
++
++/*
++ * PCR fields
++ */
++#define AF_BUSYAF			(1 << 15)
++#define FVMODE				(1 << 14)
++#define RGBPOS				(0x7 << 11)
++#define MED_TH				(0xFF << 3)
++#define AF_MED_EN			(1 << 2)
++#define AF_ALAW_EN			(1 << 1)
++#define AF_EN				(1 << 0)
++
++/*
++ * AFPAX1 fields
++ */
++#define PAXW				(0x7F << 16)
++#define PAXH				0x7F
++
++/*
++ * AFPAX2 fields
++ */
++#define AFINCV				(0xF << 13)
++#define PAXVC				(0x7F << 6)
++#define PAXHC				0x3F
++
++/*
++ * AFPAXSTART fields
++ */
++#define PAXSH				(0xFFF<<16)
++#define PAXSV				0xFFF
++
++/*
++ * COEFFICIENT MASK
++ */
++
++#define COEF_MASK0			0xFFF
++#define COEF_MASK1			(0xFFF<<16)
++
++/* BIT SHIFTS */
++#define AF_RGBPOS_SHIFT			11
++#define AF_MED_TH_SHIFT			3
++#define AF_PAXW_SHIFT			16
++#define AF_LINE_INCR_SHIFT		13
++#define AF_VT_COUNT_SHIFT		6
++#define AF_HZ_START_SHIFT		16
++#define AF_COEF_SHIFT			16
++
++/* Flags for update field */
++#define REQUEST_STATISTICS		(1 << 0)
++#define LENS_DESIRED_POSITION		(1 << 1)
++#define LENS_CURRENT_POSITION		(1 << 2)
++
++#define AF_UPDATEXS_TS			(1 << 0)
++#define AF_UPDATEXS_FIELDCOUNT		(1 << 1)
++#define AF_UPDATEXS_LENSPOS		(1 << 2)
++
++/**
++ * struct isp_af_xtrastats - Extra statistics related to AF generated stats.
++ * @ts: Timestamp when the frame gets delivered to the user.
++ * @field_count: Field count of the frame delivered to the user.
++ * @lens_position: Lens position when the stats are being generated.
++ */
++struct isp_af_xtrastats {
++	struct timeval ts;
++	unsigned long field_count;
++	u16 lens_position;
++};
++
++/**
++ * struct isp_af_data - AF statistics data to transfer between driver and user.
++ * @af_statistics_buf: Pointer to pass to user.
++ * @lens_current_position: Read value of lens absolute position.
++ * @desired_lens_direction: Lens desired location.
++ * @update: Bitwise flags to update parameters.
++ * @frame_number: Data for which frame is desired/given.
++ * @curr_frame: Current frame number being processed by AF module.
++ * @xtrastats: Extra statistics structure.
++ */
++struct isp_af_data {
++	void *af_statistics_buf;
++	u16 lens_current_position;
++	u16 desired_lens_direction;
++	u16 update;
++	u16 frame_number;
++	u16 curr_frame;
++	struct isp_af_xtrastats xtrastats;
++};
++
++/* enum used for status of specific feature */
++enum af_alaw_enable {
++	H3A_AF_ALAW_DISABLE = 0,
++	H3A_AF_ALAW_ENABLE = 1
++};
++
++enum af_hmf_enable {
++	H3A_AF_HMF_DISABLE = 0,
++	H3A_AF_HMF_ENABLE = 1
++};
++
++enum af_config_flag {
++	H3A_AF_CFG_DISABLE = 0,
++	H3A_AF_CFG_ENABLE = 1
++};
++
++enum af_mode {
++	ACCUMULATOR_SUMMED = 0,
++	ACCUMULATOR_PEAK = 1
++};
++
++/* Red, Green, and blue pixel location in the AF windows */
++enum rgbpos {
++	GR_GB_BAYER = 0,	/* GR and GB as Bayer pattern */
++	RG_GB_BAYER = 1,	/* RG and GB as Bayer pattern */
++	GR_BG_BAYER = 2,	/* GR and BG as Bayer pattern */
++	RG_BG_BAYER = 3,	/* RG and BG as Bayer pattern */
++	GG_RB_CUSTOM = 4,	/* GG and RB as custom pattern */
++	RB_GG_CUSTOM = 5	/* RB and GG as custom pattern */
++};
++
++/* Contains the information regarding the Horizontal Median Filter */
++struct af_hmf {
++	enum af_hmf_enable enable;	/* Status of Horizontal Median Filter */
++	unsigned int threshold;	/* Threshhold Value for Horizontal Median
++				 * Filter
++				 */
++};
++
++/* Contains the information regarding the IIR Filters */
++struct af_iir {
++	unsigned int hz_start_pos;	/* IIR Start Register Value */
++	int coeff_set0[AF_NUMBER_OF_COEF];	/*
++						 * IIR Filter Coefficient for
++						 * Set 0
++						 */
++	int coeff_set1[AF_NUMBER_OF_COEF];	/*
++						 * IIR Filter Coefficient for
++						 * Set 1
++						 */
++};
++
++/* Contains the information regarding the Paxels Structure in AF Engine */
++struct af_paxel {
++	unsigned int width;	/* Width of the Paxel */
++	unsigned int height;	/* Height of the Paxel */
++	unsigned int hz_start;	/* Horizontal Start Position */
++	unsigned int vt_start;	/* Vertical Start Position */
++	unsigned int hz_cnt;	/* Horizontal Count */
++	unsigned int vt_cnt;	/* vertical Count */
++	unsigned int line_incr;	/* Line Increment */
++};
++/* Contains the parameters required for hardware set up of AF Engine */
++struct af_configuration {
++	enum af_alaw_enable alaw_enable;	/*ALWAW status */
++	struct af_hmf hmf_config;	/*HMF configurations */
++	enum rgbpos rgb_pos;		/*RGB Positions */
++	struct af_iir iir_config;	/*IIR filter configurations */
++	struct af_paxel paxel_config;	/*Paxel parameters */
++	enum af_mode mode;		/*Accumulator mode */
++	enum af_config_flag af_config; /*Flag indicates Engine is configured */
++};
++
++/* Structure for device of AF Engine */
++struct af_device {
++	struct af_configuration *config; /*Device configuration structure */
++	int size_paxel;		/*Paxel size in bytes */
++};
++
++int isp_af_check_paxel(void);
++int isp_af_check_iir(void);
++int isp_af_register_setup(struct af_device *af_dev);
++int isp_af_enable(int);
++void isp_af_notify(int notify);
++
++#include <linux/autoconf.h>
++#ifdef CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER
++int isp_af_request_statistics(struct isp_af_data *afdata);
++int isp_af_configure(struct af_configuration *afconfig);
++#else
++static inline int isp_af_request_statistics(struct isp_af_data *afdata){return 0;}
++static inline int isp_af_configure(struct af_configuration *afconfig){return 0;}
++#endif
++void isp_af_set_address(unsigned long);
++void isp_af_setxtrastats(struct isp_af_xtrastats *xtrastats, u8 updateflag);
++#endif	/* OMAP_ISP_AF_H */
+Index: git/drivers/media/video/isp/ispccdc.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/ispccdc.c	2009-02-12 11:39:19.000000000 -0600
+@@ -0,0 +1,1631 @@
++/*
++ * drivers/media/video/isp/ispccdc.c
++ *
++ * Driver Library for CCDC module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/types.h>
++#include <asm/mach-types.h>
++#include <asm/io.h>
++#include <asm/scatterlist.h>
++#include <asm/uaccess.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "ispccdc.h"
++#ifndef CONFIG_ARCH_OMAP3410
++#include "isppreview.h"
++#endif
++#include "ispmmu.h"
++
++#ifndef CONFIG_ARCH_OMAP3410
++#define USE_ISP_LSC
++#else
++#undef USE_ISP_LSC
++#endif
++
++static u32 *fpc_table_add;
++static unsigned long fpc_table_add_m;
++
++/*
++ * Structure for the CCDC module to store its own information.
++ */
++static struct isp_ccdc {
++	u8 ccdc_inuse;
++	u32 ccdcout_w;
++	u32 ccdcout_h;
++	u32 ccdcin_w;
++	u32 ccdcin_h;
++	u32 ccdcin_woffset;
++	u32 ccdcin_hoffset;
++	u32 crop_w;
++	u32 crop_h;
++	u8 ccdc_inpfmt;
++	u8 ccdc_outfmt;
++	u8 vpout_en;
++	u8 wen;
++	u8 exwen;
++	u8 refmt_en;
++	u8 ccdcslave;
++	u8 syncif_ipmod;
++	u8 obclamp_en;
++	u8 lsc_en;
++	struct semaphore semlock;
++} ispccdc_obj;
++
++#ifdef USE_ISP_LSC
++	static struct ispccdc_lsc_config lsc_config;
++	static u8 *lsc_gain_table;
++	static unsigned long lsc_ispmmu_addr;
++	static int lsc_initialized;
++	static int size_mismatch;
++	static u8 ccdc_use_lsc;
++	static u8 ispccdc_lsc_tbl[] = {
++		#include "ispccd_lsc.dat"
++	};
++#endif
++
++/* Structure for saving/restoring CCDC module registers*/
++static struct isp_reg ispccdc_reg_list[] = {
++	{ISPCCDC_SYN_MODE, 0x0000},
++	{ISPCCDC_HD_VD_WID, 0x0000},
++	{ISPCCDC_PIX_LINES, 0x0000},
++	{ISPCCDC_HORZ_INFO, 0x0000},
++	{ISPCCDC_VERT_START, 0x0000},
++	{ISPCCDC_VERT_LINES, 0x0000},
++	{ISPCCDC_CULLING, 0x0000},
++	{ISPCCDC_HSIZE_OFF, 0x0000},
++	{ISPCCDC_SDOFST, 0x0000},
++	{ISPCCDC_SDR_ADDR, 0x0000},
++	{ISPCCDC_CLAMP, 0x0000},
++	{ISPCCDC_DCSUB, 0x0000},
++	{ISPCCDC_COLPTN, 0x0000},
++	{ISPCCDC_BLKCMP, 0x0000},
++	{ISPCCDC_FPC, 0x0000},
++	{ISPCCDC_FPC_ADDR, 0x0000},
++	{ISPCCDC_VDINT, 0x0000},
++	{ISPCCDC_ALAW, 0x0000},
++	{ISPCCDC_REC656IF, 0x0000},
++	{ISPCCDC_CFG, 0x0000},
++	{ISPCCDC_FMTCFG, 0x0000},
++	{ISPCCDC_FMT_HORZ, 0x0000},
++	{ISPCCDC_FMT_VERT, 0x0000},
++	{ISPCCDC_FMT_ADDR0, 0x0000},
++	{ISPCCDC_FMT_ADDR1, 0x0000},
++	{ISPCCDC_FMT_ADDR2, 0x0000},
++	{ISPCCDC_FMT_ADDR3, 0x0000},
++	{ISPCCDC_FMT_ADDR4, 0x0000},
++	{ISPCCDC_FMT_ADDR5, 0x0000},
++	{ISPCCDC_FMT_ADDR6, 0x0000},
++	{ISPCCDC_FMT_ADDR7, 0x0000},
++	{ISPCCDC_PRGEVEN0, 0x0000},
++	{ISPCCDC_PRGEVEN1, 0x0000},
++	{ISPCCDC_PRGODD0, 0x0000},
++	{ISPCCDC_PRGODD1, 0x0000},
++	{ISPCCDC_VP_OUT, 0x0000},
++	{ISPCCDC_LSC_CONFIG, 0x0000},
++	{ISPCCDC_LSC_INITIAL, 0x0000},
++	{ISPCCDC_LSC_TABLE_BASE, 0x0000},
++	{ISPCCDC_LSC_TABLE_OFFSET, 0x0000},
++	{ISP_TOK_TERM, 0x0000}
++};
++
++/*
++ * Abstraction layer CCDC Module configuration.
++ */
++int omap34xx_isp_ccdc_config(void *userspace_add)
++{
++	struct ispccdc_bclamp bclamp_t;
++	struct ispccdc_blcomp blcomp_t;
++	struct ispccdc_fpc fpc_t;
++	struct ispccdc_culling cull_t;
++	struct ispccdc_update_config ccdc_struct;
++	u32 old_size;
++
++	if (userspace_add == NULL)
++		return -EINVAL;
++
++	if (copy_from_user(&ccdc_struct,
++				(struct ispccdc_update_config *)(userspace_add),
++					sizeof(struct ispccdc_update_config)))
++		goto copy_from_user_err;
++
++	if ((ISP_ABS_CCDC_ALAW & ccdc_struct.flag) ==
++							ISP_ABS_CCDC_ALAW) {
++		if ((ISP_ABS_CCDC_ALAW & ccdc_struct.update) ==
++							ISP_ABS_CCDC_ALAW) {
++			ispccdc_config_alaw(ccdc_struct.alawip);
++			ispccdc_enable_alaw(1);
++		} else
++			ispccdc_enable_alaw(1);
++	} else {
++		if ((ISP_ABS_CCDC_ALAW & ccdc_struct.update) ==
++							ISP_ABS_CCDC_ALAW)
++			ispccdc_enable_alaw(0);
++	}
++
++	if ((ISP_ABS_CCDC_LPF & ccdc_struct.flag) == ISP_ABS_CCDC_LPF)
++		ispccdc_enable_lpf(1);
++	else
++		ispccdc_enable_lpf(0);
++
++	if ((ISP_ABS_CCDC_BLCLAMP & ccdc_struct.flag) ==
++							ISP_ABS_CCDC_BLCLAMP) {
++		if ((ISP_ABS_CCDC_BLCLAMP & ccdc_struct.update) ==
++							ISP_ABS_CCDC_BLCLAMP) {
++			if (copy_from_user(&bclamp_t,
++						(struct ispccdc_bclamp *)
++						(ccdc_struct.bclamp),
++						sizeof(struct ispccdc_bclamp)))
++				goto copy_from_user_err;
++
++				ispccdc_config_black_clamp(bclamp_t);
++				ispccdc_enable_black_clamp(1);
++		} else
++			ispccdc_enable_black_clamp(1);
++	} else {
++		if ((ISP_ABS_CCDC_BLCLAMP & ccdc_struct.update) ==
++							ISP_ABS_CCDC_BLCLAMP)
++			ispccdc_enable_black_clamp(0);
++	}
++
++	if ((ISP_ABS_CCDC_BCOMP & ccdc_struct.update) == ISP_ABS_CCDC_BCOMP) {
++		if (copy_from_user(&blcomp_t,
++				(struct ispccdc_blcomp *)(ccdc_struct.blcomp),
++				sizeof(blcomp_t)))
++			goto copy_from_user_err;
++
++		ispccdc_config_black_comp(blcomp_t);
++	}
++
++	if ((ISP_ABS_CCDC_FPC & ccdc_struct.flag) == ISP_ABS_CCDC_FPC) {
++		if ((ISP_ABS_CCDC_FPC & ccdc_struct.update) ==
++							ISP_ABS_CCDC_FPC) {
++			if (copy_from_user(&fpc_t,
++					(struct ispccdc_fpc *)(ccdc_struct.fpc),
++					sizeof(fpc_t)))
++				goto copy_from_user_err;
++			fpc_table_add = (u32 *)
++					kmalloc((64 + ((fpc_t.fpnum) * 4)),
++					GFP_KERNEL|GFP_DMA);
++			if (fpc_table_add == NULL) {
++			printk(KERN_ERR "Cannot allocate memory for FPC table");
++				return -ENOMEM;
++			}
++
++		while (((int)fpc_table_add & 0xFFFFFFC0) != (int)fpc_table_add)
++			fpc_table_add++;
++
++		fpc_table_add_m = ispmmu_map(virt_to_phys(fpc_table_add),
++							(fpc_t.fpnum)*4);
++
++			if (copy_from_user(fpc_table_add, (void *)fpc_t.fpcaddr,
++							fpc_t.fpnum * 4))
++				goto copy_from_user_err;
++
++			fpc_t.fpcaddr = fpc_table_add_m;
++			ispccdc_config_fpc(fpc_t);
++			ispccdc_enable_fpc(1);
++			} else
++		ispccdc_enable_fpc(1);
++		} else {
++		if ((ISP_ABS_CCDC_FPC & ccdc_struct.update) ==
++							ISP_ABS_CCDC_FPC)
++			ispccdc_enable_fpc(0);
++		}
++
++	if ((ISP_ABS_CCDC_CULL & ccdc_struct.update) ==	ISP_ABS_CCDC_CULL) {
++		if (copy_from_user(&cull_t,
++			(struct ispccdc_culling *)(ccdc_struct.cull),
++			sizeof(cull_t)))
++			goto copy_from_user_err;
++		ispccdc_config_culling(cull_t);
++	}
++#ifdef USE_ISP_LSC
++	if ((ISP_ABS_CCDC_CONFIG_LSC & ccdc_struct.flag) ==
++						ISP_ABS_CCDC_CONFIG_LSC) {
++		if ((ISP_ABS_CCDC_CONFIG_LSC & ccdc_struct.update) ==
++						ISP_ABS_CCDC_CONFIG_LSC) {
++			old_size = lsc_config.size;
++			if (copy_from_user(&lsc_config,
++					(struct ispccdc_lsc_config *)
++					(ccdc_struct.lsc_cfg),
++					sizeof(struct ispccdc_lsc_config)))
++				goto copy_from_user_err;
++
++			lsc_initialized = 0;
++
++			if (lsc_config.size <= old_size)
++				size_mismatch = 0;
++			else
++				size_mismatch = 1;
++
++			ispccdc_config_lsc(&lsc_config);
++			}
++	}
++
++	if ((ISP_ABS_CCDC_CONFIG_LSC & ccdc_struct.flag) ==
++						ISP_ABS_CCDC_CONFIG_LSC)
++		ccdc_use_lsc = 1;
++	else {
++		ispccdc_enable_lsc(0);
++		ccdc_use_lsc = 0;
++	}
++#endif
++	if ((ISP_ABS_CCDC_COLPTN & ccdc_struct.update) ==
++						ISP_ABS_CCDC_COLPTN)
++		ispccdc_config_imgattr(ccdc_struct.colptn);
++
++	return 0;
++
++copy_from_user_err:
++	printk(KERN_ERR "CCDC Config:Copy From User Error");
++	return -EINVAL ;
++}
++EXPORT_SYMBOL(omap34xx_isp_ccdc_config);
++
++/*
++ * Reserve the CCDC module.
++ * Only one user at a time.
++ */
++int ispccdc_request(void)
++{
++	down(&(ispccdc_obj.semlock));
++	if (!(ispccdc_obj.ccdc_inuse)) {
++		ispccdc_obj.ccdc_inuse = 1;
++		up(&(ispccdc_obj.semlock));
++		/* Turn on CCDC module Clocks. */
++		omap_writel((omap_readl(ISP_CTRL)) | ISPCTRL_CCDC_RAM_EN |
++							ISPCTRL_CCDC_CLK_EN |
++							ISPCTRL_SBL_WR1_RAM_EN,
++							ISP_CTRL);
++		/* VDLC = 1 is a must if CCDC to be used */
++		omap_writel((omap_readl(ISPCCDC_CFG)) | ISPCCDC_CFG_VDLC
++					, ISPCCDC_CFG);
++		return 0;
++	} else{
++		up(&(ispccdc_obj.semlock));
++		DPRINTK_ISPCCDC("ISP_ERR : CCDC Module Busy");
++		return -EBUSY;
++	}
++}
++EXPORT_SYMBOL(ispccdc_request);
++
++/*
++ * Marks CCDC module free.
++ */
++int ispccdc_free(void)
++{
++	down(&(ispccdc_obj.semlock));
++	if (ispccdc_obj.ccdc_inuse) {
++		ispccdc_obj.ccdc_inuse = 0;
++		up(&(ispccdc_obj.semlock));
++		/* Turn off CCDC module Clocks. */
++		omap_writel((omap_readl(ISP_CTRL)) & ~(ISPCTRL_CCDC_CLK_EN
++				| ISPCTRL_CCDC_RAM_EN
++				| ISPCTRL_SBL_WR1_RAM_EN), ISP_CTRL);
++		return 0;
++	} else {
++		up(&(ispccdc_obj.semlock));
++		DPRINTK_ISPCCDC("ISP_ERR : CCDC Module already freed");
++		return -EINVAL;
++	}
++}
++EXPORT_SYMBOL(ispccdc_free);
++
++#ifdef USE_ISP_LSC
++/*
++ * Load lens shading table
++ */
++int ispccdc_load_lsc(u32 table_size)
++{
++	if (table_size == 0)
++		return -EINVAL;
++
++	if (lsc_initialized)
++		return 0;
++
++	/* Disable LSC module*/
++	ispccdc_enable_lsc(0);
++	lsc_gain_table = kmalloc(table_size, GFP_KERNEL | GFP_DMA);
++
++	if (lsc_gain_table == NULL) {
++		printk(KERN_ERR "Cannot allocate memory for gain tables\n");
++		return -ENOMEM;
++	}
++
++	memcpy(lsc_gain_table, ispccdc_lsc_tbl, table_size);
++	lsc_ispmmu_addr = ispmmu_map(virt_to_phys(lsc_gain_table), table_size);
++
++	omap_writel(lsc_ispmmu_addr , ISPCCDC_LSC_TABLE_BASE);
++	lsc_initialized = 1;
++
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_load_lsc);
++
++/*
++ * Configures the lens shading compensation module
++ * lsc_cfg	: LSC configuration structure
++ */
++void ispccdc_config_lsc(struct ispccdc_lsc_config *lsc_cfg)
++{
++	int reg;
++
++	/* Disable LSC module*/
++	ispccdc_enable_lsc(0);
++
++	omap_writel(lsc_cfg->offset, ISPCCDC_LSC_TABLE_OFFSET);
++
++	reg = 0x0000;
++	reg |= (lsc_cfg->gain_mode_n << ISPCCDC_LSC_GAIN_MODE_N_SHIFT);
++	reg |= (lsc_cfg->gain_mode_m << ISPCCDC_LSC_GAIN_MODE_M_SHIFT);
++	reg |= (lsc_cfg->gain_format << ISPCCDC_LSC_GAIN_FORMAT_SHIFT);
++	omap_writel(reg , ISPCCDC_LSC_CONFIG);
++
++	reg = 0x0000;
++	reg &= ~ISPCCDC_LSC_INITIAL_X_MASK;
++	reg |= (lsc_cfg->initial_x << ISPCCDC_LSC_INITIAL_X_SHIFT);
++	reg &= ~ISPCCDC_LSC_INITIAL_Y_MASK;
++	reg |= (lsc_cfg->initial_y << ISPCCDC_LSC_INITIAL_Y_SHIFT);
++	omap_writel(reg , ISPCCDC_LSC_INITIAL);
++}
++EXPORT_SYMBOL(ispccdc_config_lsc);
++
++/*
++ * Enables  lens shading compensation module
++ * enable	:0 - Disable LSC	: 1- Enables LSC
++ */
++void ispccdc_enable_lsc(u8 enable)
++{
++	if (enable & ccdc_use_lsc) {
++		omap_writel(omap_readl(ISP_CTRL) | ISPCTRL_SBL_SHARED_RPORTB |
++					ISPCTRL_SBL_RD_RAM_EN, ISP_CTRL);
++		omap_writel(omap_readl(ISPCCDC_LSC_CONFIG) | 0x01,
++					ISPCCDC_LSC_CONFIG);
++		ispccdc_obj.lsc_en = 1;
++	} else {
++		omap_writel(omap_readl(ISPCCDC_LSC_CONFIG) & 0xFFFE,
++					ISPCCDC_LSC_CONFIG);
++		ispccdc_obj.lsc_en = 0;
++	}
++}
++EXPORT_SYMBOL(ispccdc_enable_lsc);
++
++/*
++* Abstraction layer LSC Updates
++*/
++int omap34xx_isp_lsc_update(void *userspace_add)
++{
++	struct isptables_update isptables_struct;
++
++	if (userspace_add == NULL)
++		return -EINVAL;
++
++	if (copy_from_user(&isptables_struct, (void *)userspace_add,
++				sizeof(struct isptables_update)))
++		goto copy_from_user_err;
++
++	if ((ISP_ABS_TBL_LSC & isptables_struct.flag) == ISP_ABS_TBL_LSC) {
++		if ((ISP_ABS_TBL_LSC & isptables_struct.update) ==
++							ISP_ABS_TBL_LSC) {
++			ispccdc_enable_lsc(0);
++			if (size_mismatch) {
++				ispmmu_unmap(lsc_ispmmu_addr);
++				kfree(lsc_gain_table);
++				lsc_gain_table = kmalloc(lsc_config.size,
++							GFP_KERNEL | GFP_DMA);
++				if (!lsc_gain_table) {
++					printk(KERN_ERR "Cannot allocate "
++						"memory for gain tables \n");
++					return -ENOMEM;
++				}
++
++				lsc_ispmmu_addr = ispmmu_map(
++						virt_to_phys(lsc_gain_table),
++						lsc_config.size);
++				omap_writel(lsc_ispmmu_addr,
++						ISPCCDC_LSC_TABLE_BASE);
++				lsc_initialized = 1;
++				size_mismatch = 0;
++			}
++
++			if (copy_from_user(lsc_gain_table, isptables_struct.lsc,
++							lsc_config.size))
++				goto copy_from_user_err;
++		}
++
++		ccdc_use_lsc = 1;
++	} else {
++		if ((ISP_ABS_TBL_LSC & isptables_struct.update) ==
++								ISP_ABS_TBL_LSC)
++		ispccdc_enable_lsc(0);
++		ccdc_use_lsc = 0;
++	}
++
++	return 0;
++
++copy_from_user_err:
++	printk(KERN_ERR "LSC Update:Copy From User Error");
++	return -EINVAL;
++}
++#else
++void ispccdc_enable_lsc(u8 enable) {}
++#endif
++EXPORT_SYMBOL(omap34xx_isp_lsc_update);
++
++void ispccdc_config_crop(u32 left, u32 top, u32 height, u32 width)
++{
++/* The following restrictions are applied for the crop settings. If incoming
++ *  values do not follow these restrictions then we map the settings to the
++ *  closest acceptable crop value.
++ * 1) Left offset is always odd. This can be avoided if we enable byte swap
++ *    option for incoming data into CCDC.
++ * 2) Height offset is always even.
++ * 3) Crop width is always a multiple of 16 pixels
++ * 4) Crop height is always even.
++ */
++
++	ispccdc_obj.ccdcin_woffset = left + ((left+1)%2);
++	ispccdc_obj.ccdcin_hoffset = top + (top % 2);
++
++	ispccdc_obj.crop_w = width - (width % 16);
++	ispccdc_obj.crop_h = height + (height % 2);
++
++	DPRINTK_ISPCCDC("\n\tOffsets L %d T %d W %d H %d\n",
++			ispccdc_obj.ccdcin_woffset,
++			ispccdc_obj.ccdcin_hoffset,
++			ispccdc_obj.crop_w,
++			ispccdc_obj.crop_h);
++
++}
++/* Sets up the default CCDC configuration according to the arguments.
++ * input		: Indicates the module that gives the image to CCDC
++ * output		: Indicates the module to which the CCDC outputs to.
++ */
++int ispccdc_config_datapath(enum ccdc_input input,
++				enum ccdc_output output)
++{
++	u32 syn_mode = 0;
++	struct ispccdc_vp vpcfg;
++	struct ispccdc_syncif syncif;
++	struct ispccdc_bclamp blkcfg;
++	/* Color pattern is
++	Gr   R   Gr   R   Gr   R ...
++	B   Gb . B   Gb   B   Gb.....
++	Gr   R   Gr   R   Gr   R ...
++	B   Gb . B   Gb   B   Gb.....
++	*/
++	u32 colptn = ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC0_SHIFT
++		| ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC1_SHIFT
++		| ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP0PLC2_SHIFT
++		| ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP0PLC3_SHIFT
++		| ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC0_SHIFT
++		| ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC1_SHIFT
++		| ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP1PLC2_SHIFT
++		| ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP1PLC3_SHIFT
++		| ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC0_SHIFT
++		| ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC1_SHIFT
++		| ISPCCDC_COLPTN_Gr_Cy << ISPCCDC_COLPTN_CP2PLC2_SHIFT
++		| ISPCCDC_COLPTN_R_Ye << ISPCCDC_COLPTN_CP2PLC3_SHIFT
++		| ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC0_SHIFT
++		| ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC1_SHIFT
++		| ISPCCDC_COLPTN_B_Mg << ISPCCDC_COLPTN_CP3PLC2_SHIFT
++		| ISPCCDC_COLPTN_Gb_G << ISPCCDC_COLPTN_CP3PLC3_SHIFT;
++
++	/* CCDC does not convert the image format */
++	if (((input == CCDC_RAW) || (input == CCDC_OTHERS))
++						&& (output == CCDC_YUV_RSZ)) {
++		DPRINTK_ISPCCDC("ISP_ERR : Wrong CCDC i/p,o/p Combination");
++		return -EINVAL;
++	}
++
++	syn_mode = omap_readl(ISPCCDC_SYN_MODE);
++
++	switch (output) {
++	case CCDC_YUV_RSZ:
++		syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
++		syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
++		break;
++
++	case CCDC_YUV_MEM_RSZ:
++		syn_mode |= ISPCCDC_SYN_MODE_SDR2RSZ;
++		ispccdc_obj.wen = 1;
++		syn_mode |= ISPCCDC_SYN_MODE_WEN;
++		break;
++
++	case CCDC_OTHERS_VP:
++		syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
++		syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
++		syn_mode &= ~ISPCCDC_SYN_MODE_WEN;
++		/* Video Port Configuration */
++		vpcfg.bitshift_sel = BIT9_0;
++		vpcfg.freq_sel = PIXCLKBY2;
++		ispccdc_config_vp(vpcfg);
++		ispccdc_enable_vp(1);
++		break;
++
++	case CCDC_OTHERS_MEM:
++		syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR;
++		syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ;
++		syn_mode |= ISPCCDC_SYN_MODE_WEN;
++		/* Generally cam_wen is used with cam_hs, vs signals */
++#ifndef ENABLE_BT_656_CAPTURE
++		syn_mode |= ISPCCDC_SYN_MODE_EXWEN;
++		omap_writel((omap_readl(ISPCCDC_CFG))
++				| ISPCCDC_CFG_WENLOG, ISPCCDC_CFG);
++#else
++		syn_mode &= ~ISPCCDC_SYN_MODE_EXWEN;
++#endif
++		break;
++
++	case CCDC_OTHERS_VP_MEM:
++		syn_mode |= ISPCCDC_SYN_MODE_VP2SDR;
++		syn_mode |= ISPCCDC_SYN_MODE_WEN;
++		/* Generally cam_wen is used with cam_hs, vs signals */
++		syn_mode |= ISPCCDC_SYN_MODE_EXWEN;
++		omap_writel((omap_readl(ISPCCDC_CFG))
++				| ISPCCDC_CFG_WENLOG, ISPCCDC_CFG);
++		/* Video Port Configuration */
++		vpcfg.bitshift_sel = BIT9_0;
++		vpcfg.freq_sel = PIXCLKBY2;
++		ispccdc_config_vp(vpcfg);
++		ispccdc_enable_vp(1);
++		break;
++	default:
++		DPRINTK_ISPCCDC("ISP_ERR : Wrong CCDC Input");
++		return -EINVAL;
++	};
++
++#ifdef USE_ISP_LSC
++	if (input == CCDC_RAW) {
++		lsc_config.initial_x = 0;
++		lsc_config.initial_y = 0;
++		lsc_config.gain_mode_n = 0x06;
++		lsc_config.gain_mode_m = 0x06;
++		lsc_config.gain_format = 0x04;
++		lsc_config.offset = 0x60;
++		ispccdc_config_lsc(&lsc_config);
++		ispccdc_load_lsc(lsc_config.size);
++	/*	mdelay(100);
++		ispccdc_enable_lsc(1);	*/
++	}
++#endif
++
++	omap_writel(syn_mode, ISPCCDC_SYN_MODE);
++
++	switch (input) {
++	case CCDC_RAW:
++		/* Slave mode */
++		syncif.ccdc_mastermode = 0;
++		/* Normal */
++		syncif.datapol = 0;
++		syncif.datsz = DAT10;
++		/* Progressive Mode */
++		syncif.fldmode = 0;
++		/* Input */
++		syncif.fldout = 0;
++		/* Positive */
++		syncif.fldpol = 0;
++		/* Odd Field */
++		syncif.fldstat = 0;
++		/*Positive */
++		syncif.hdpol = 0;
++		syncif.ipmod = RAW;
++		/* Positive */
++		syncif.vdpol = 0;
++		ispccdc_config_sync_if(syncif);
++		ispccdc_config_imgattr(colptn);
++		blkcfg.dcsubval = 42;
++		ispccdc_config_black_clamp(blkcfg);
++		break;
++	case CCDC_YUV_SYNC:
++		/* Slave mode */
++		syncif.ccdc_mastermode = 0;
++		/* Normal */
++		syncif.datapol = 0;
++		syncif.datsz = DAT8;
++		/* Progressive Mode */
++		syncif.fldmode = 0;
++		/* Input */
++		syncif.fldout = 0;
++		/* Positive */
++		syncif.fldpol = 0;
++		/* Odd Field */
++		syncif.fldstat = 0;
++		/*Positive */
++		syncif.hdpol = 0;
++		syncif.ipmod = YUV16;
++		/*Positive */
++		syncif.vdpol = 0;
++#ifdef ENABLE_BT_656_CAPTURE
++		syncif.bt_r656_en = 0;
++#endif
++		ispccdc_config_imgattr(0);
++		ispccdc_config_sync_if(syncif);
++		blkcfg.dcsubval = 0;
++		ispccdc_config_black_clamp(blkcfg);
++		break;
++	case CCDC_YUV_BT:
++#ifdef ENABLE_BT_656_CAPTURE
++		/* Slave mode */
++		syncif.ccdc_mastermode = 0;
++		/* Normal */
++		syncif.datapol = 0;
++		syncif.datsz = DAT8;
++		/* Progressive Mode */
++		syncif.fldmode = 1;
++		/* Input */
++		syncif.fldout = 0;
++		/* Positive */
++		syncif.fldpol = 0;
++		/* Odd Field */
++		syncif.fldstat = 0;
++		/*Positive */
++		syncif.hdpol = 0;
++		syncif.ipmod = YUV8;
++		/*Positive */
++		syncif.vdpol = 1;
++		syncif.bt_r656_en = 1;
++		ispccdc_config_imgattr(0);
++		ispccdc_config_sync_if(syncif);
++		blkcfg.dcsubval = 0;
++		ispccdc_config_black_clamp(blkcfg);
++#endif
++		break;
++	case CCDC_OTHERS:
++		break;
++	default:
++		DPRINTK_ISPCCDC("ISP_ERR : Wrong CCDC Input");
++		return -EINVAL;
++	}
++
++	ispccdc_obj.ccdc_inpfmt = input;
++	ispccdc_obj.ccdc_outfmt = output;
++	ispccdc_print_status();
++	isp_print_status();
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_datapath);
++
++/*
++ * Configures the sync interface parameters between the sensor and the CCDC.
++ * syncif		: Structure containing the sync parameters like
++ * field state,
++ * CCDC in master/slave mode, raw/yuv data, polarity of data,
++ * field, hs, vs signals.
++ */
++void ispccdc_config_sync_if(struct ispccdc_syncif syncif)
++{
++	u32 syn_mode = omap_readl(ISPCCDC_SYN_MODE);
++
++	syn_mode |= ISPCCDC_SYN_MODE_VDHDEN;
++
++	if (syncif.fldstat)
++		syn_mode |= ISPCCDC_SYN_MODE_FLDSTAT;
++	else
++		syn_mode &= ~ISPCCDC_SYN_MODE_FLDSTAT;
++
++	syn_mode &= ISPCCDC_SYN_MODE_INPMOD_MASK;
++	ispccdc_obj.syncif_ipmod = syncif.ipmod;
++
++	switch (syncif.ipmod) {
++	case RAW:
++		break;
++	case YUV16:
++		syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR16;
++		break;
++	case YUV8:
++		syn_mode |= ISPCCDC_SYN_MODE_INPMOD_YCBCR8;
++#ifdef ENABLE_BT_656_CAPTURE
++		syn_mode |= ISPCCDC_SYN_MODE_PACK8;
++#endif
++		break;
++	};
++
++	syn_mode &= ISPCCDC_SYN_MODE_DATSIZ_MASK;
++	switch (syncif.datsz) {
++	case DAT8:
++		syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_8;
++		break;
++	case DAT10:
++		syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_10;
++		break;
++	case DAT11:
++		syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_11;
++		break;
++	case DAT12:
++		syn_mode |= ISPCCDC_SYN_MODE_DATSIZ_12;
++		break;
++	};
++
++	if (syncif.fldmode)
++		/*Interlaced mode*/
++		syn_mode |= ISPCCDC_SYN_MODE_FLDMODE;
++	else
++		/*Progressive mode */
++		syn_mode &= ~ISPCCDC_SYN_MODE_FLDMODE;
++
++	if (syncif.datapol)
++		/*One's complement */
++		syn_mode |= ISPCCDC_SYN_MODE_DATAPOL;
++	else
++		/*Normal */
++		syn_mode &= ~ISPCCDC_SYN_MODE_DATAPOL;
++
++	if (syncif.fldpol)
++		/*Negative */
++		syn_mode |= ISPCCDC_SYN_MODE_FLDPOL;
++	else
++		/*Positive */
++		syn_mode &= ~ISPCCDC_SYN_MODE_FLDPOL;
++
++	if (syncif.hdpol)
++		/*Negative */
++		syn_mode |= ISPCCDC_SYN_MODE_HDPOL;
++	else
++		/*Positive */
++		syn_mode &= ~ISPCCDC_SYN_MODE_HDPOL;
++
++	if (syncif.vdpol)
++		/*Negative */
++		syn_mode |= ISPCCDC_SYN_MODE_VDPOL;
++	else
++		/*Positive */
++		syn_mode &= ~ISPCCDC_SYN_MODE_VDPOL;
++
++	if (syncif.ccdc_mastermode) {
++		/*fld, hd, vd are output signals in master mode */
++		syn_mode |= ISPCCDC_SYN_MODE_FLDOUT
++			| ISPCCDC_SYN_MODE_VDHDOUT;
++		omap_writel(syncif.hs_width << ISPCCDC_HD_VD_WID_HDW_SHIFT
++			| syncif.vs_width << ISPCCDC_HD_VD_WID_VDW_SHIFT,
++			ISPCCDC_HD_VD_WID);
++
++		/*Pixel per line, half line per frame are used
++		* along with HS/VS as output
++		*/
++		omap_writel(syncif.ppln << ISPCCDC_PIX_LINES_PPLN_SHIFT
++			| syncif.hlprf << ISPCCDC_PIX_LINES_HLPRF_SHIFT,
++			ISPCCDC_PIX_LINES);
++	} else
++		/*fld, hd,vd input signals in slave mode */
++		syn_mode &= ~(ISPCCDC_SYN_MODE_FLDOUT
++			| ISPCCDC_SYN_MODE_VDHDOUT);
++
++	omap_writel(syn_mode, ISPCCDC_SYN_MODE);
++
++	if (!(syncif.bt_r656_en))
++		omap_writel((omap_readl(ISPCCDC_REC656IF))
++			& (~ISPCCDC_REC656IF_R656ON), ISPCCDC_REC656IF);
++#ifdef ENABLE_BT_656_CAPTURE
++	else
++		omap_writel((omap_readl(ISPCCDC_REC656IF))
++			| (ISPCCDC_REC656IF_R656ON | ISPCCDC_REC656IF_ECCFVH), ISPCCDC_REC656IF);
++#endif
++}
++EXPORT_SYMBOL(ispccdc_config_sync_if);
++
++/*
++ * Configures the optical/digital black clamp parameters in CCDC.
++ * bclamp	: Structure containing the optical black average gain,
++ *		optical black sample length, sample lines, and the start pixel
++ *		position of the samples w.r.t the HS pulse .
++ */
++int ispccdc_config_black_clamp(struct ispccdc_bclamp bclamp)
++{
++	u32 bclamp_val = 0;
++	if (ispccdc_obj.obclamp_en) {
++		bclamp_val |= bclamp.obgain << ISPCCDC_CLAMP_OBGAIN_SHIFT;
++		bclamp_val |= bclamp.oblen << ISPCCDC_CLAMP_OBSLEN_SHIFT;
++		bclamp_val |= bclamp.oblines << ISPCCDC_CLAMP_OBSLN_SHIFT;
++		bclamp_val |= bclamp.obstpixel << ISPCCDC_CLAMP_OBST_SHIFT;
++		omap_writel(bclamp_val, ISPCCDC_CLAMP);
++	} else {
++		/*
++		* HW Errata 1.39. Camera ISP: DC substract not supported for
++		* YUV 8bit and ITU656
++		*/
++#if 0
++		if (is_sil_rev_less_than(OMAP3430_REV_ES2_0))
++			if ((ispccdc_obj.syncif_ipmod == YUV16) ||
++					(ispccdc_obj.syncif_ipmod == YUV8) ||
++					((omap_readl(ISPCCDC_REC656IF)
++					& ISPCCDC_REC656IF_R656ON)
++					== ISPCCDC_REC656IF_R656ON))
++				bclamp.dcsubval = 0;
++			omap_writel(bclamp.dcsubval, ISPCCDC_DCSUB);
++#endif
++	}
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_black_clamp);
++
++/*
++ * Enables  the optical or Digital black clamp.
++ * enable	:	: 1- Enables Optical Black clamp
++ *		0 - Enables Digital Black clamp.
++ */
++void ispccdc_enable_black_clamp(u8 enable)
++{
++	if (enable) {
++		omap_writel((omap_readl(ISPCCDC_CLAMP)) | ISPCCDC_CLAMP_CLAMPEN,
++								ISPCCDC_CLAMP);
++		ispccdc_obj.obclamp_en = 1;
++	} else {
++		omap_writel((omap_readl(ISPCCDC_CLAMP))
++				& (~ISPCCDC_CLAMP_CLAMPEN), ISPCCDC_CLAMP);
++		ispccdc_obj.obclamp_en = 0;
++	}
++}
++EXPORT_SYMBOL(ispccdc_enable_black_clamp);
++
++/*
++ * Configures the Faulty Pixel Correction parameters.
++ * fpc		: Structure containing the number of faulty pixels corrected
++ *		in the frame, address of the FPC table.
++ */
++int ispccdc_config_fpc(struct ispccdc_fpc fpc)
++{
++	u32 fpc_val = 0;
++
++	fpc_val = omap_readl(ISPCCDC_FPC);
++
++	if ((fpc.fpcaddr & 0xFFFFFFC0) == fpc.fpcaddr) {
++		/*Make sure that FPC is disabled*/
++		omap_writel(fpc_val&(~ISPCCDC_FPC_FPCEN), ISPCCDC_FPC);
++		omap_writel(fpc.fpcaddr, ISPCCDC_FPC_ADDR);
++	} else {
++		DPRINTK_ISPCCDC("FPC Address should be on 64byte boundary\n");
++		return -EINVAL;
++	}
++	/*Retain the FPC Enable bit along with the configuration*/
++	omap_writel(fpc_val|(fpc.fpnum<<ISPCCDC_FPC_FPNUM_SHIFT)
++			, ISPCCDC_FPC);
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_fpc);
++
++/*
++ * Enables  the Faulty Pixel Correction.
++ * enable	:	: 1- Enables FPC
++ */
++void ispccdc_enable_fpc(u8 enable)
++{
++	if (enable)
++		omap_writel((omap_readl(ISPCCDC_FPC))|ISPCCDC_FPC_FPCEN
++			, ISPCCDC_FPC);
++	else
++		omap_writel((omap_readl(ISPCCDC_FPC))
++			& (~ISPCCDC_FPC_FPCEN), ISPCCDC_FPC);
++}
++EXPORT_SYMBOL(ispccdc_enable_fpc);
++
++/*
++ * Configures the Black Level Compensation parameters.
++ * blcomp	: Structure containing the black level compensation value
++ *		for RGrGbB pixels. in 2's complement.
++ */
++void ispccdc_config_black_comp(struct ispccdc_blcomp blcomp)
++{
++	u32 blcomp_val = 0;
++	blcomp_val |= blcomp.b_mg << ISPCCDC_BLKCMP_B_MG_SHIFT;
++	blcomp_val |= blcomp.gb_g << ISPCCDC_BLKCMP_GB_G_SHIFT;
++	blcomp_val |= blcomp.gr_cy << ISPCCDC_BLKCMP_GR_CY_SHIFT;
++	blcomp_val |= blcomp.r_ye << ISPCCDC_BLKCMP_R_YE_SHIFT;
++
++	omap_writel(blcomp_val, ISPCCDC_BLKCMP);
++}
++EXPORT_SYMBOL(ispccdc_config_black_comp);
++
++/*
++ * Configures the Video Port Configuration parameters.
++ * vpcfg		: Structure containing the Video Port input frequency,
++ *		and the 10 bit format.
++ */
++void ispccdc_config_vp(struct ispccdc_vp vpcfg)
++{
++	u32 fmtcfg_vp = omap_readl(ISPCCDC_FMTCFG);
++
++	/*Clear the existing values */
++	fmtcfg_vp &= ISPCCDC_FMTCFG_VPIN_MASK &
++		ISPCCDC_FMTCF_VPIF_FRQ_MASK;
++
++	switch (vpcfg.bitshift_sel) {
++	case BIT9_0:
++		fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_9_0;
++		break;
++	case BIT10_1:
++		fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_10_1;
++		break;
++	case BIT11_2:
++		fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_11_2;
++		break;
++	case BIT12_3:
++		fmtcfg_vp |= ISPCCDC_FMTCFG_VPIN_12_3;
++		break;
++	};
++	switch (vpcfg.freq_sel) {
++	case PIXCLKBY2:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY2;
++		break;
++	case PIXCLKBY3_5:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY3;
++		break;
++	case PIXCLKBY4_5:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY4;
++		break;
++	case PIXCLKBY5_5:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY5;
++		break;
++	case PIXCLKBY6_5:
++		fmtcfg_vp |= ISPCCDC_FMTCF_VPIF_FRQ_BY6;
++		break;
++	};
++	omap_writel(fmtcfg_vp, ISPCCDC_FMTCFG);
++}
++EXPORT_SYMBOL(ispccdc_config_vp);
++
++/*
++ * Enables  the Video Port.
++ * enable	:	: 1- Enables VP
++ */
++void ispccdc_enable_vp(u8 enable)
++{
++	if (enable)
++		omap_writel((omap_readl(ISPCCDC_FMTCFG))
++			| ISPCCDC_FMTCFG_VPEN, ISPCCDC_FMTCFG);
++	else
++		omap_writel((omap_readl(ISPCCDC_FMTCFG))
++			& (~ISPCCDC_FMTCFG_VPEN), ISPCCDC_FMTCFG);
++}
++EXPORT_SYMBOL(ispccdc_enable_vp);
++
++/*
++ * Configures the Reformatter register values if line alternating is disabled.
++ * else just enabling the line alternating is enough.
++ * refmt	:	: Structure containing the memory address to format and
++ *		the bit fields for the reformatter registers.
++ */
++void ispccdc_config_reformatter(struct ispccdc_refmt refmt)
++{
++	u32 fmtcfg_val = 0;
++
++	fmtcfg_val = omap_readl(ISPCCDC_FMTCFG);
++
++	if (refmt.lnalt)
++		fmtcfg_val |=  ISPCCDC_FMTCFG_LNALT;
++	else{
++		fmtcfg_val &= ~ISPCCDC_FMTCFG_LNALT;
++		/*Clear fields of lnum plen_even/odd*/
++		fmtcfg_val &= 0xFFFFF003;
++		fmtcfg_val |= refmt.lnum << ISPCCDC_FMTCFG_LNUM_SHIFT;
++		fmtcfg_val |= refmt.plen_even <<
++						ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT;
++		fmtcfg_val |= refmt.plen_odd << ISPCCDC_FMTCFG_PLEN_ODD_SHIFT;
++
++		/*The arguments have the proper caluclated addresses
++		* and bit fields for the reformatter configuration*/
++		omap_writel(refmt.prgeven0, ISPCCDC_PRGEVEN0);
++		omap_writel(refmt.prgeven1, ISPCCDC_PRGEVEN1);
++		omap_writel(refmt.prgodd0, ISPCCDC_PRGODD0);
++		omap_writel(refmt.prgodd1, ISPCCDC_PRGODD1);
++		omap_writel(refmt.fmtaddr0, ISPCCDC_FMT_ADDR0);
++		omap_writel(refmt.fmtaddr1, ISPCCDC_FMT_ADDR1);
++		omap_writel(refmt.fmtaddr2, ISPCCDC_FMT_ADDR2);
++		omap_writel(refmt.fmtaddr3, ISPCCDC_FMT_ADDR3);
++		omap_writel(refmt.fmtaddr4, ISPCCDC_FMT_ADDR4);
++		omap_writel(refmt.fmtaddr5, ISPCCDC_FMT_ADDR5);
++		omap_writel(refmt.fmtaddr6, ISPCCDC_FMT_ADDR6);
++		omap_writel(refmt.fmtaddr7, ISPCCDC_FMT_ADDR7);
++	}
++	omap_writel(fmtcfg_val, ISPCCDC_FMTCFG);
++}
++EXPORT_SYMBOL(ispccdc_config_reformatter);
++
++/*
++ * Enables  the Reformatter
++ * enable	:	: 1- Enables Data Reformatter
++ */
++void ispccdc_enable_reformatter(u8 enable)
++{
++	if (enable) {
++		omap_writel((omap_readl(ISPCCDC_FMTCFG))
++			| ISPCCDC_FMTCFG_FMTEN, ISPCCDC_FMTCFG);
++		ispccdc_obj.refmt_en = 1;
++	} else {
++		omap_writel((omap_readl(ISPCCDC_FMTCFG))
++			& ~ISPCCDC_FMTCFG_FMTEN, ISPCCDC_FMTCFG);
++		ispccdc_obj.refmt_en = 0;
++	}
++}
++EXPORT_SYMBOL(ispccdc_enable_reformatter);
++
++/*
++ * Configures the Culling parameters.
++ * cull	:	: Structure containing the vertical culling pattern,
++ * 		and horizontal culling pattern for odd and even lines.
++ */
++void ispccdc_config_culling(struct ispccdc_culling cull)
++{
++	u32 culling_val = 0;
++
++	culling_val |= cull.v_pattern<<ISPCCDC_CULLING_CULV_SHIFT;
++	culling_val |= cull.h_even << ISPCCDC_CULLING_CULHEVN_SHIFT;
++	culling_val |= cull.h_odd << ISPCCDC_CULLING_CULHODD_SHIFT;
++
++	omap_writel(culling_val, ISPCCDC_CULLING);
++}
++EXPORT_SYMBOL(ispccdc_config_culling);
++
++/*
++ * Enables  the Low pass Filter
++ * enable	:	: 1- Enables LPF
++ */
++void ispccdc_enable_lpf(u8 enable)
++{
++	if (enable)
++		omap_writel((omap_readl(ISPCCDC_SYN_MODE))
++			| ISPCCDC_SYN_MODE_LPF, ISPCCDC_SYN_MODE);
++	else
++		omap_writel((omap_readl(ISPCCDC_SYN_MODE))
++			& (~ISPCCDC_SYN_MODE_LPF), ISPCCDC_SYN_MODE);
++}
++EXPORT_SYMBOL(ispccdc_enable_lpf);
++
++/*
++ * Configures the input width for A-law.
++ * ipwidth	: Input width for ALaw
++ */
++void ispccdc_config_alaw(enum alaw_ipwidth ipwidth)
++{
++	omap_writel(ipwidth << ISPCCDC_ALAW_GWDI_SHIFT, ISPCCDC_ALAW);
++}
++EXPORT_SYMBOL(ispccdc_config_alaw);
++
++/*
++ * Enables  the A-law compression
++ * enable	:	: 1- Enables A-Law
++ */
++void ispccdc_enable_alaw(u8 enable)
++{
++	if (enable)
++		omap_writel((omap_readl(ISPCCDC_ALAW))
++			| ISPCCDC_ALAW_CCDTBL, ISPCCDC_ALAW);
++	else
++		omap_writel((omap_readl(ISPCCDC_ALAW))
++			& ~ISPCCDC_ALAW_CCDTBL, ISPCCDC_ALAW);
++}
++EXPORT_SYMBOL(ispccdc_enable_alaw);
++
++/*
++ * Configures the sensor image specific attribute.
++ * colptn		: Color pattern of the sensor.
++ */
++void ispccdc_config_imgattr(u32 colptn)
++{
++	omap_writel(colptn, ISPCCDC_COLPTN);
++}
++EXPORT_SYMBOL(ispccdc_config_imgattr);
++
++/*
++ * Programs the shadow registers associated with CCDC.
++ */
++void ispccdc_config_shadow_registers(void)
++{
++	if (ccdc_use_lsc && !ispccdc_obj.lsc_en &&
++				(ispccdc_obj.ccdc_inpfmt == CCDC_RAW))
++		ispccdc_enable_lsc(1);
++	return;
++}
++EXPORT_SYMBOL(ispccdc_config_shadow_registers);
++
++/*
++ * Calculates the number of pixels cropped if the reformater is disabled,
++ * Fills up the output widht height variables in the isp_ccdc structure .
++ * input_w	: input width for the CCDC in number of pixels per line
++ * input_h	: input height for the CCDC in number of lines
++ * output_w	: output width from the CCDC in number of pixels per line
++ * output_h	: output height for the CCDC in number of lines
++*/
++int ispccdc_try_size(u32 input_w, u32 input_h, u32 *output_w,
++			u32 *output_h)
++{
++/*
++ * CCDC cannot handle less than 2 pixels for input.
++ */
++	if (input_w < 2) {
++		DPRINTK_ISPCCDC("ISP_ERR: CCDC cannot handle input width less"
++							" than 2 pixels\n");
++		return -EINVAL;
++	}
++
++/*
++ * If crop settings are issued then output size from CCDC
++ * will be equal to the crop window specified.
++ */
++
++	if (ispccdc_obj.crop_w)
++		*output_w = ispccdc_obj.crop_w;
++	else
++		*output_w = input_w;
++
++	if (ispccdc_obj.crop_h)
++		*output_h = ispccdc_obj.crop_h;
++	else
++		*output_h = input_h;
++
++	if ((!ispccdc_obj.refmt_en) && (ispccdc_obj.ccdc_outfmt !=
++							CCDC_OTHERS_MEM))
++		*output_h -= 1;
++
++	if ((ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_MEM) ||
++			(ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_VP_MEM)) {
++		if (*output_w % 16) {
++			*output_w -= (*output_w % 16);
++			*output_w += 16;
++		}
++	}
++
++	ispccdc_obj.ccdcout_w = *output_w;
++	ispccdc_obj.ccdcout_h = *output_h;
++	ispccdc_obj.ccdcin_w = input_w;
++	ispccdc_obj.ccdcin_h = input_h;
++
++	DPRINTK_ISPCCDC("try size: ccdcin_w=%u,ccdcin_h=%u,ccdcout_w=%u,"
++							" ccdcout_h=%u\n",
++							ispccdc_obj.ccdcin_w,
++							ispccdc_obj.ccdcin_h,
++							ispccdc_obj.ccdcout_w,
++							ispccdc_obj.ccdcout_h);
++
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_try_size);
++
++/*
++ * Configures the appropriate values stored in the isp_ccdc structure to
++ * HORZ/VERT_INFO registers and the VP_OUT depending on whether the image
++ * is stored in memory or given to the another module in the ISP pipeline.
++ * input_w	: input width for the CCDC  in number of pixels per line
++ * input_h	: input height for the CCDC in number of lines
++ * output_w	: output width from the CCDC in number of pixels per line
++ * output_h	: output height for the CCDC in number of lines
++ */
++int ispccdc_config_size(u32 input_w, u32 input_h, u32 output_w, u32 output_h)
++{
++	DPRINTK_ISPCCDC("config size: input_w=%u,input_h=%u,output_w=%u,"
++			"output_h=%u\n", input_w, input_h, output_w, output_h);
++
++	if ((output_w != ispccdc_obj.ccdcout_w)
++				|| (output_h != ispccdc_obj.ccdcout_h)) {
++		DPRINTK_ISPCCDC("ISP_ERR : ispccdc_try_size should "
++				"be called before config size\n");
++		return -EINVAL;
++	}
++
++	if (ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_VP) {
++		/* Start with 1 pixel apart */
++		omap_writel((ispccdc_obj.ccdcin_woffset
++				<< ISPCCDC_FMT_HORZ_FMTSPH_SHIFT)
++				| (ispccdc_obj.ccdcin_w
++				<< ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
++				ISPCCDC_FMT_HORZ);
++
++		omap_writel((ispccdc_obj.ccdcin_hoffset
++				<< ISPCCDC_FMT_VERT_FMTSLV_SHIFT)
++				| ((ispccdc_obj.ccdcin_h)
++				<< ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
++				ISPCCDC_FMT_VERT);
++
++		omap_writel((ispccdc_obj.ccdcout_w
++				<< ISPCCDC_VP_OUT_HORZ_NUM_SHIFT)
++				| (ispccdc_obj.ccdcout_h
++				<< ISPCCDC_VP_OUT_VERT_NUM_SHIFT),
++				ISPCCDC_VP_OUT);
++		omap_writel((((ispccdc_obj.ccdcout_h - 25)
++				& ISPCCDC_VDINT_0_MASK)
++				<< ISPCCDC_VDINT_0_SHIFT)
++				| (((50) &  ISPCCDC_VDINT_1_MASK)
++				<< ISPCCDC_VDINT_1_SHIFT),
++				ISPCCDC_VDINT);
++
++	} else if (ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_MEM) {
++#ifndef CONFIG_ARCH_OMAP3410
++#ifndef ENABLE_BT_656_CAPTURE
++		omap_writel(1 << ISPCCDC_HORZ_INFO_SPH_SHIFT
++				| ((ispccdc_obj.ccdcout_w - 1)
++				<< ISPCCDC_HORZ_INFO_NPH_SHIFT),
++				ISPCCDC_HORZ_INFO);
++#else
++		omap_writel(0 << ISPCCDC_HORZ_INFO_SPH_SHIFT
++				| (((ispccdc_obj.ccdcout_w << 1) - 1)
++				<< ISPCCDC_HORZ_INFO_NPH_SHIFT),
++				ISPCCDC_HORZ_INFO);
++#endif
++#else
++		omap_writel(0 << ISPCCDC_HORZ_INFO_SPH_SHIFT
++				| ((ispccdc_obj.ccdcout_w - 1)
++				<< ISPCCDC_HORZ_INFO_NPH_SHIFT),
++				ISPCCDC_HORZ_INFO);
++#endif
++
++#ifndef ENABLE_BT_656_CAPTURE
++		omap_writel(0 << ISPCCDC_VERT_START_SLV0_SHIFT,
++				ISPCCDC_VERT_START);
++		omap_writel((ispccdc_obj.ccdcout_h - 1)
++				<< ISPCCDC_VERT_LINES_NLV_SHIFT,
++				ISPCCDC_VERT_LINES);
++#else
++		omap_writel(2 << ISPCCDC_VERT_START_SLV0_SHIFT | 2 << ISPCCDC_VERT_START_SLV1_SHIFT,
++				ISPCCDC_VERT_START);
++		omap_writel(((ispccdc_obj.ccdcout_h >> 1) - 1)
++				<< ISPCCDC_VERT_LINES_NLV_SHIFT,
++				ISPCCDC_VERT_LINES);
++#endif
++
++		/*Configure the HSIZE_OFF with output buffer width */
++		ispccdc_config_outlineoffset(ispccdc_obj.ccdcout_w*2, 0, 0);
++
++#ifndef ENABLE_BT_656_CAPTURE
++		omap_writel((((ispccdc_obj.ccdcout_h - 1)
++				& ISPCCDC_VDINT_0_MASK)
++				<< ISPCCDC_VDINT_0_SHIFT)
++				| (((50) &  ISPCCDC_VDINT_1_MASK)
++				<< ISPCCDC_VDINT_1_SHIFT),
++				ISPCCDC_VDINT);
++#else
++		ispccdc_config_outlineoffset(ispccdc_obj.ccdcout_w*2,
++		                             EVENEVEN, 1);
++		ispccdc_config_outlineoffset(ispccdc_obj.ccdcout_w*2,
++		                             ODDEVEN, 1);
++		ispccdc_config_outlineoffset(ispccdc_obj.ccdcout_w*2,
++		                             EVENODD, 1);
++		ispccdc_config_outlineoffset(ispccdc_obj.ccdcout_w*2,
++		                             ODDODD, 1);
++
++		omap_writel(((((ispccdc_obj.ccdcout_h >> 1) - 1)
++				& ISPCCDC_VDINT_0_MASK)
++				<< ISPCCDC_VDINT_0_SHIFT)
++				| (((50) &  ISPCCDC_VDINT_1_MASK)
++				<< ISPCCDC_VDINT_1_SHIFT),
++				ISPCCDC_VDINT);
++#endif
++	} else if (ispccdc_obj.ccdc_outfmt == CCDC_OTHERS_VP_MEM) {
++		/* Start with 1 pixel apart */
++		omap_writel((1 << ISPCCDC_FMT_HORZ_FMTSPH_SHIFT)
++				| (ispccdc_obj.ccdcin_w
++				<< ISPCCDC_FMT_HORZ_FMTLNH_SHIFT),
++				ISPCCDC_FMT_HORZ);
++
++		omap_writel((0 << ISPCCDC_FMT_VERT_FMTSLV_SHIFT)
++				| ((ispccdc_obj.ccdcin_h)
++				<< ISPCCDC_FMT_VERT_FMTLNV_SHIFT),
++				ISPCCDC_FMT_VERT);
++
++		omap_writel((ispccdc_obj.ccdcout_w
++				<< ISPCCDC_VP_OUT_HORZ_NUM_SHIFT)
++				| (ispccdc_obj.ccdcout_h
++				<< ISPCCDC_VP_OUT_VERT_NUM_SHIFT),
++				ISPCCDC_VP_OUT);
++		omap_writel(0 << ISPCCDC_HORZ_INFO_SPH_SHIFT
++				| ((ispccdc_obj.ccdcout_w - 1)
++				<< ISPCCDC_HORZ_INFO_NPH_SHIFT),
++				ISPCCDC_HORZ_INFO);
++		omap_writel(0 << ISPCCDC_VERT_START_SLV0_SHIFT,
++				ISPCCDC_VERT_START);
++		omap_writel((ispccdc_obj.ccdcout_h - 1)
++				<< ISPCCDC_VERT_LINES_NLV_SHIFT,
++				ISPCCDC_VERT_LINES);
++		/*Configure the HSIZE_OFF with output buffer width*/
++		ispccdc_config_outlineoffset(ispccdc_obj.ccdcout_w*2, 0, 0);
++		omap_writel((((ispccdc_obj.ccdcout_h - 25)
++				& ISPCCDC_VDINT_0_MASK)
++				<< ISPCCDC_VDINT_0_SHIFT)
++				| (((50) &  ISPCCDC_VDINT_1_MASK)
++				<< ISPCCDC_VDINT_1_SHIFT),
++				ISPCCDC_VDINT);
++	}
++#ifdef USE_ISP_LSC
++	if (ispccdc_obj.ccdc_inpfmt == CCDC_RAW) {
++		ispccdc_config_lsc(&lsc_config);
++		ispccdc_load_lsc(lsc_config.size);
++	}
++#endif
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_size);
++
++/*
++ * Configures the output line offset when stored in memory.
++ * Configures the num of even and odd line fields in case of rearranging
++ * the lines
++ * offset: twice the Output width and aligned on 32byte boundary.
++ * oddeven: odd/even line pattern to be chosen to store the output
++ * numlines: Configure the value 0-3 for +1-4lines, 4-7 for -1-4lines
++ */
++int ispccdc_config_outlineoffset(u32 offset, u8 oddeven, u8 numlines)
++{
++
++
++	/*
++	 * Make sure offset is multiple of 32bytes. ie last 5bits should be
++	 * zero
++	 */
++	if ((offset & ISP_32B_BOUNDARY_OFFSET) == offset)
++		omap_writel((offset&0xFFFF), ISPCCDC_HSIZE_OFF);
++	else {
++		DPRINTK_ISPCCDC("ISP_ERR : Offset should be in 32 byte \
++			boundary");
++		return -EINVAL;
++	}
++
++	/*0 - By default Donot inverse the field identification */
++	omap_writel((omap_readl(ISPCCDC_SDOFST) & (~ISPCCDC_SDOFST_FINV)),
++			ISPCCDC_SDOFST);
++
++	/*0 - By default one line offset*/
++	omap_writel(omap_readl(ISPCCDC_SDOFST) & ISPCCDC_SDOFST_FOFST_1L,
++			ISPCCDC_SDOFST);
++
++	switch (oddeven) {
++	case EVENEVEN:		/*even lines even fields*/
++		omap_writel((omap_readl(ISPCCDC_SDOFST))|
++			((numlines & 0x7) << ISPCCDC_SDOFST_LOFST0_SHIFT)
++			, ISPCCDC_SDOFST);
++		break;
++	case ODDEVEN:		/*odd lines even fields*/
++		omap_writel((omap_readl(ISPCCDC_SDOFST))|
++			((numlines & 0x7) << ISPCCDC_SDOFST_LOFST1_SHIFT)
++			, ISPCCDC_SDOFST);
++		break;
++	case EVENODD:		/*even lines odd fields*/
++		omap_writel((omap_readl(ISPCCDC_SDOFST)) |
++			((numlines & 0x7) << ISPCCDC_SDOFST_LOFST2_SHIFT)
++			, ISPCCDC_SDOFST);
++		break;
++	case ODDODD:		/*odd lines odd fields*/
++		omap_writel((omap_readl(ISPCCDC_SDOFST)) |
++			((numlines & 0x7) << ISPCCDC_SDOFST_LOFST3_SHIFT)
++			, ISPCCDC_SDOFST);
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++EXPORT_SYMBOL(ispccdc_config_outlineoffset);
++
++/*
++ * Configures the memory address where the output should be stored.
++ * addr		: 32bit memory address aligned on 32 bit boundary.
++ */
++int ispccdc_set_outaddr(u32 addr)
++{
++	if ((addr & ISP_32B_BOUNDARY_BUF) == addr) {
++		omap_writel(addr, ISPCCDC_SDR_ADDR);
++		return 0;
++	} else {
++		DPRINTK_ISPCCDC("ISP_ERR : Address should be in 32 byte \
++			boundary");
++		return -EINVAL;
++	}
++
++}
++EXPORT_SYMBOL(ispccdc_set_outaddr);
++
++/*
++ *
++ * Enables the CCDC module.
++ * Client should configure all the sub modules in CCDC before this.
++ * enable		: 1- Enables the preview module.
++ */
++void ispccdc_enable(u8 enable)
++{
++	if (enable)
++		omap_writel(omap_readl(ISPCCDC_PCR) | (ISPCCDC_PCR_EN),
++								ISPCCDC_PCR);
++	else
++		omap_writel(omap_readl(ISPCCDC_PCR) & ~(ISPCCDC_PCR_EN),
++								ISPCCDC_PCR);
++}
++EXPORT_SYMBOL(ispccdc_enable);
++
++#ifdef ENABLE_BT_656_CAPTURE
++/*
++ * Configures the location of Y color component when YCbCr 8-bit data is input
++ */
++void ispccdc_config_y8pos(enum y8pos_mode mode)
++{
++	if (mode == Y8POS_EVEN)
++		omap_writel(omap_readl(ISPCCDC_CFG) & ~(ISPCCDC_CFG_Y8POS),
++								ISPCCDC_CFG);
++	else
++		omap_writel(omap_readl(ISPCCDC_CFG) | (ISPCCDC_CFG_Y8POS),
++								ISPCCDC_CFG);
++}
++EXPORT_SYMBOL(ispccdc_config_y8pos);
++
++/*
++ * Configures byte swap data stored in memory. 1 - swap bytes, 0 - normal
++ */
++void ispccdc_config_byteswap(int swap)
++{
++	if (swap)
++		omap_writel(omap_readl(ISPCCDC_CFG) | (ISPCCDC_CFG_BSWD),
++								ISPCCDC_CFG);
++	else
++		omap_writel(omap_readl(ISPCCDC_CFG) & ~(ISPCCDC_CFG_BSWD),
++								ISPCCDC_CFG);
++}
++EXPORT_SYMBOL(ispccdc_config_byteswap);
++#endif
++
++int ispccdc_busy(void)
++{
++	return (omap_readl(ISPCCDC_PCR) & ISPCCDC_PCR_BUSY);
++}
++EXPORT_SYMBOL(ispccdc_busy);
++
++/*
++ * Saves the values of the CCDC module registers.
++ */
++void ispccdc_save_context(void)
++{
++	DPRINTK_ISPCCDC(" Saving context \n");
++	isp_save_context(ispccdc_reg_list);
++
++}
++EXPORT_SYMBOL(ispccdc_save_context);
++
++/*
++ * Restores the values of the CCDC module registers.
++ */
++void ispccdc_restore_context(void)
++{
++	DPRINTK_ISPCCDC(" Restoring context\n");
++	isp_restore_context(ispccdc_reg_list);
++}
++EXPORT_SYMBOL(ispccdc_restore_context);
++
++/*
++ * Prints the values of the CCDC Module registers
++ * Also prints other debug information stored in the CCDC module
++ */
++void ispccdc_print_status(void)
++{
++#ifdef	OMAP_ISPCCDC_DEBUG
++	DPRINTK_ISPCCDC("Module in use =%d\n", ispccdc_obj.ccdc_inuse);
++	DPRINTK_ISPCCDC("Accepted CCDC Input (width = %d,Height = %d)\n",
++							ispccdc_obj.ccdcin_w,
++							ispccdc_obj.ccdcin_h);
++	DPRINTK_ISPCCDC("Accepted CCDC Output (width = %d,Height = %d)\n",
++							ispccdc_obj.ccdcout_w,
++							ispccdc_obj.ccdcout_h);
++
++	DPRINTK_ISPCCDC("###CCDC PCR=0x%x\n", omap_readl(ISPCCDC_PCR));
++	DPRINTK_ISPCCDC("ISP_CTRL =0x%x\n", omap_readl(ISP_CTRL));
++	switch (ispccdc_obj.ccdc_inpfmt) {
++	case CCDC_RAW:
++		DPRINTK_ISPCCDC("ccdc input format is CCDC_RAW\n");
++		break;
++	case CCDC_YUV_SYNC:
++		DPRINTK_ISPCCDC("ccdc input format is CCDC_YUV_SYNC\n");
++		break;
++	case CCDC_YUV_BT:
++		DPRINTK_ISPCCDC("ccdc input format is CCDC_YUV_BT\n");
++		break;
++
++	}
++	switch (ispccdc_obj.ccdc_outfmt) {
++	case CCDC_OTHERS_VP:
++		DPRINTK_ISPCCDC("ccdc output format is CCDC_OTHERS_VP\n");
++		break;
++	case CCDC_OTHERS_MEM:
++		DPRINTK_ISPCCDC("ccdc output format is CCDC_OTHERS_MEM\n");
++		break;
++	case CCDC_YUV_RSZ:
++		DPRINTK_ISPCCDC("ccdc output format is CCDC_YUV_RSZ\n");
++		break;
++	}
++	DPRINTK_ISPCCDC("###ISP_CTRL in ccdc =0x%x\n", omap_readl(ISP_CTRL));
++	DPRINTK_ISPCCDC("###ISP_IRQ0ENABLE in ccdc =0x%x\n",
++						omap_readl(ISP_IRQ0ENABLE));
++	DPRINTK_ISPCCDC("###ISP_IRQ0STATUS in ccdc =0x%x\n",
++						omap_readl(ISP_IRQ0STATUS));
++	DPRINTK_ISPCCDC("###CCDC SYN_MODE=0x%x\n",
++						omap_readl(ISPCCDC_SYN_MODE));
++	DPRINTK_ISPCCDC("###CCDC HORZ_INFO=0x%x\n",
++						omap_readl(ISPCCDC_HORZ_INFO));
++	DPRINTK_ISPCCDC("###CCDC VERT_START=0x%x\n",
++					omap_readl(ISPCCDC_VERT_START));
++	DPRINTK_ISPCCDC("###CCDC VERT_LINES=0x%x\n",
++					omap_readl(ISPCCDC_VERT_LINES));
++	DPRINTK_ISPCCDC("###CCDC CULLING=0x%x\n", omap_readl(ISPCCDC_CULLING));
++	DPRINTK_ISPCCDC("###CCDC HSIZE_OFF=0x%x\n",
++						omap_readl(ISPCCDC_HSIZE_OFF));
++	DPRINTK_ISPCCDC("###CCDC SDOFST=0x%x\n", omap_readl(ISPCCDC_SDOFST));
++	DPRINTK_ISPCCDC("###CCDC SDR_ADDR=0x%x\n",
++						omap_readl(ISPCCDC_SDR_ADDR));
++	DPRINTK_ISPCCDC("###CCDC CLAMP=0x%x\n", omap_readl(ISPCCDC_CLAMP));
++	DPRINTK_ISPCCDC("###CCDC COLPTN=0x%x\n", omap_readl(ISPCCDC_COLPTN));
++	DPRINTK_ISPCCDC("###CCDC CFG=0x%x\n", omap_readl(ISPCCDC_CFG));
++	DPRINTK_ISPCCDC("###CCDC VP_OUT=0x%x\n", omap_readl(ISPCCDC_VP_OUT));
++	DPRINTK_ISPCCDC("###CCDC_SDR_ADDR= 0x%x\n",
++						omap_readl(ISPCCDC_SDR_ADDR));
++	DPRINTK_ISPCCDC("###CCDC FMTCFG=0x%x\n", omap_readl(ISPCCDC_FMTCFG));
++	DPRINTK_ISPCCDC("###CCDC FMT_HORZ=0x%x\n",
++						omap_readl(ISPCCDC_FMT_HORZ));
++	DPRINTK_ISPCCDC("###CCDC FMT_VERT=0x%x\n",
++						omap_readl(ISPCCDC_FMT_VERT));
++	DPRINTK_ISPCCDC("###CCDC LSC_CONFIG=0x%x\n",
++					omap_readl(ISPCCDC_LSC_CONFIG));
++	DPRINTK_ISPCCDC("###CCDC LSC_INIT=0x%x\n",
++					omap_readl(ISPCCDC_LSC_INITIAL));
++	DPRINTK_ISPCCDC("###CCDC LSC_TABLE BASE=0x%x\n",
++					omap_readl(ISPCCDC_LSC_TABLE_BASE));
++	DPRINTK_ISPCCDC("###CCDC LSC TABLE OFFSET=0x%x\n",
++					omap_readl(ISPCCDC_LSC_TABLE_OFFSET));
++#endif
++}
++EXPORT_SYMBOL(ispccdc_print_status);
++
++/*
++ * Module Initialisation.
++ */
++static int __init isp_ccdc_init(void)
++{
++	ispccdc_obj.ccdc_inuse = 0;
++	ispccdc_config_crop(0, 0, 0, 0);
++	init_MUTEX(&(ispccdc_obj.semlock));
++
++#ifdef USE_ISP_LSC
++	lsc_config.initial_x = 0;
++	lsc_config.initial_y = 0;
++	lsc_config.gain_mode_n = 0x06;
++	lsc_config.gain_mode_m = 0x06;
++	lsc_config.gain_format = 0x04;
++	lsc_config.offset = 0x60;
++	lsc_config.size = sizeof(ispccdc_lsc_tbl);
++	ccdc_use_lsc = 1;
++#endif
++
++	return 0;
++}
++
++static void isp_ccdc_cleanup(void)
++{
++#ifdef USE_ISP_LSC
++	if (lsc_initialized) {
++		ispmmu_unmap(lsc_ispmmu_addr);
++		kfree(lsc_gain_table);
++		lsc_initialized = 0;
++	}
++#endif
++	if (fpc_table_add_m != 0) {
++		ispmmu_unmap(fpc_table_add_m);
++		kfree(fpc_table_add);
++	}
++}
++
++module_init(isp_ccdc_init);
++module_exit(isp_ccdc_cleanup);
++
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("ISP CCDC Library");
++MODULE_LICENSE("GPL");
+Index: git/drivers/media/video/isp/ispccdc.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/ispccdc.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,342 @@
++/*
++ * drivers/media/video/isp/ispccdc.h
++ *
++ * Driver include file for CCDC module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_CCDC_H
++#define OMAP_ISP_CCDC_H
++
++/*Abstraction layer CCDC configurations*/
++#define ISP_ABS_CCDC_ALAW					(1 << 0)
++#define ISP_ABS_CCDC_LPF 					(1 << 1)
++#define ISP_ABS_CCDC_BLCLAMP					(1 << 2)
++#define ISP_ABS_CCDC_BCOMP					(1 << 3)
++#define ISP_ABS_CCDC_FPC					(1 << 4)
++#define ISP_ABS_CCDC_CULL					(1 << 5)
++#define ISP_ABS_CCDC_COLPTN					(1 << 6)
++#define ISP_ABS_CCDC_CONFIG_LSC					(1 << 7)
++
++#define ISP_ABS_TBL_LSC						(1 << 0)
++
++#ifndef CONFIG_ARCH_OMAP3410
++	#include "isppreview.h"
++#endif
++
++int ispccdc_request(void);
++
++int ispccdc_free(void);
++
++/*Enumeration constants for CCDC input output format */
++enum ccdc_input {
++	CCDC_RAW,
++	CCDC_YUV_SYNC,
++	CCDC_YUV_BT,
++	CCDC_OTHERS
++};
++enum ccdc_output {
++	CCDC_YUV_RSZ,
++	CCDC_YUV_MEM_RSZ,
++	CCDC_OTHERS_VP,
++	CCDC_OTHERS_MEM,
++	CCDC_OTHERS_VP_MEM
++};
++
++/*
++ * Sets up the default CCDC configuration according to the arguments.
++ */
++int ispccdc_config_datapath(enum ccdc_input input, enum ccdc_output output);
++
++/*
++ * Configures the crop settings in the CCDC module.
++ */
++void ispccdc_config_crop(u32 left, u32 top, u32 height, u32 width);
++
++/* Enumeration constants for the sync interface parameters */
++enum inpmode {
++	RAW,
++	YUV16,
++	YUV8
++};
++enum datasize {
++	DAT8,
++	DAT10,
++	DAT11,
++	DAT12
++};
++
++#ifdef ENABLE_BT_656_CAPTURE
++/*
++ * Configure location of Y component in 8-bit YUV data input
++ */
++enum y8pos_mode {
++	Y8POS_EVEN = 0,
++	Y8POS_ODD = 1
++};
++#endif
++
++/* Structure for the Sync Interface between the sensor and CCDC*/
++struct ispccdc_syncif {
++	/* 1 - Master, 0- Slave */
++	u8 ccdc_mastermode;
++	/* 0 - Odd Field, 1- Even Field */
++	u8 fldstat;
++	enum inpmode ipmod;
++	enum datasize datsz;
++	/* 0 -Progressive Mode, 1 -Interlaced Mode */
++	u8 fldmode;
++	/* 0 -Positive, 1 - Negative */
++	u8 datapol;
++	/* 0 -Positive, 1 - Negative */
++	u8 fldpol;
++	/* 0 -Positive, 1 - Negative */
++	u8 hdpol;
++	/* 0 -Positive, 1 - Negative */
++	u8 vdpol;
++	/* 0 -Input, 1 - Output */
++	u8 fldout;
++	/* Width of the Horizontal Sync pulse - used for HS/VS Output*/
++	u8 hs_width;
++	/* Width of the Vertical Sync pulse - used for HS/VS Output*/
++	u8 vs_width;
++	/*Number of pixels per line - used for HS/VS Output*/
++	u8 ppln;
++	/*Number of half lines per frame - used for HS/VS Output*/
++	u8 hlprf;
++	/*1 - Enable ITU-R BT656 mode, 0 - Sync mode*/
++	u8 bt_r656_en;
++};
++
++/* Structure for LSC configuration*/
++struct ispccdc_lsc_config {
++	u8 offset;
++	u8 gain_mode_n;
++	u8 gain_mode_m;
++	u8 gain_format;
++	u16 fmtsph;
++	u16 fmtlnh;
++	u16 fmtslv;
++	u16 fmtlnv;
++	u8 initial_x;
++	u8 initial_y;
++	u32 size;
++};
++
++/*
++ * Configures the sync interface parameters between the sensor and the CCDC.
++ */
++void ispccdc_config_sync_if(struct ispccdc_syncif syncif);
++
++/* Structure for the optical black Clamp and Digital black Clamp subtract*/
++struct ispccdc_bclamp{
++	/*Optical black average gain*/
++	u8 obgain;
++	/*Start Pixel w.r.t. HS pulse in Optical black sample*/
++	u8 obstpixel;
++	/*Optical Black Sample lines*/
++	u8 oblines;
++	/*Optical Black Sample Length*/
++	u8 oblen;
++	/*Digital Black Clamp subtract value */
++	u16 dcsubval;
++	};
++
++/*
++ * Configures the optical/digital black clamp parameters in CCDC.
++ */
++int ispccdc_config_black_clamp(struct ispccdc_bclamp bclamp);
++
++/*
++ * Enables  the optical or Digital black clamp.
++ */
++void ispccdc_enable_black_clamp(u8 enable);
++
++/* Structure for FPC */
++struct ispccdc_fpc{
++	/* Number of faulty pixels to be corrected in the frame*/
++	u16 fpnum;
++	/* Memory address of the FPC Table */
++	u32 fpcaddr;
++	};
++
++/*
++ * Configures the Faulty Pixel Correction parameters.
++ */
++int ispccdc_config_fpc(struct ispccdc_fpc fpc);
++
++/*
++ * Enables  the Faulty Pixel Correction.
++ * enable	:	: 1- Enables FPC
++ */
++void ispccdc_enable_fpc(u8 enable);
++
++/* Structure for Black Level Compensation parameters*/
++struct ispccdc_blcomp{
++	u8 b_mg;
++	u8 gb_g;
++	u8 gr_cy;
++	u8 r_ye;
++	};
++
++/*
++ * Configures the Black Level Compensation parameters.
++ */
++void ispccdc_config_black_comp(struct ispccdc_blcomp blcomp);
++
++/* Enumeration constants for Video Port */
++enum vpin {
++	BIT12_3 = 3,
++	BIT11_2 = 4,
++	BIT10_1 = 5,
++	BIT9_0 = 6
++};
++enum vpif_freq {
++	PIXCLKBY2,
++	PIXCLKBY3_5,
++	PIXCLKBY4_5,
++	PIXCLKBY5_5,
++	PIXCLKBY6_5
++};
++
++/*Structure for Video Port parameters */
++struct ispccdc_vp {
++	enum vpin bitshift_sel;
++	enum vpif_freq freq_sel;
++};
++
++/*
++ * Configures the Video Port Configuration parameters.
++ */
++void ispccdc_config_vp(struct ispccdc_vp vp);
++
++/*
++ * Enables  the Video Port.
++ */
++void ispccdc_enable_vp(u8 enable);
++
++/* Structure for Reformatter parameters */
++struct ispccdc_refmt{
++	u8 lnalt;
++	u8 lnum;
++	u8 plen_even;
++	u8 plen_odd;
++	u32 prgeven0;
++	u32 prgeven1;
++	u32 prgodd0;
++	u32 prgodd1;
++	u32 fmtaddr0;
++	u32 fmtaddr1;
++	u32 fmtaddr2;
++	u32 fmtaddr3;
++	u32 fmtaddr4;
++	u32 fmtaddr5;
++	u32 fmtaddr6;
++	u32 fmtaddr7;
++};
++
++/*
++ * Configures the Reformatter register values if line alternating is disabled.
++ * else just enabling the line alternating is enough.
++ */
++void ispccdc_config_reformatter(struct ispccdc_refmt refmt);
++
++/*
++ * Enables  the Reformatter
++ */
++void ispccdc_enable_reformatter(u8 enable);
++
++/* Structure for Culling parameters */
++struct ispccdc_culling{
++	/* Vertical culling pattern */
++	u8 v_pattern;
++	/* Horizontal Culling pattern for odd lines */
++	u16 h_odd;
++	/* Horizontal Culling pattern for even lines */
++	u16 h_even;
++};
++
++/*
++ * Configures the Culling parameters.
++ */
++void ispccdc_config_culling(struct ispccdc_culling culling);
++
++/*
++ * Enables  the Low pass Filter
++ */
++void ispccdc_enable_lpf(u8 enable);
++
++/* Enumeration constants for Alaw input width */
++enum alaw_ipwidth{
++	ALAW_BIT12_3 = 0x3,
++	ALAW_BIT11_2 = 0x4,
++	ALAW_BIT10_1 = 0x5,
++	ALAW_BIT9_0 = 0x6
++};
++
++/* Structure for CCDC configuration*/
++struct ispccdc_update_config {
++	u16 update;
++	u16 flag;
++	enum alaw_ipwidth alawip;
++	struct ispccdc_bclamp *bclamp;
++	struct ispccdc_blcomp *blcomp;
++	struct ispccdc_fpc *fpc;
++	struct ispccdc_lsc_config *lsc_cfg;
++	struct ispccdc_culling *cull;
++	u32 colptn;
++};
++
++
++void ispccdc_config_alaw(enum alaw_ipwidth ipwidth);
++
++void ispccdc_enable_alaw(u8 enable);
++
++int ispccdc_load_lsc(u32 table_size);
++
++void ispccdc_config_lsc(struct ispccdc_lsc_config *lsc_cfg);
++
++void ispccdc_enable_lsc(u8 enable);
++
++void ispccdc_config_imgattr(u32 colptn);
++
++void ispccdc_config_shadow_registers(void);
++
++int ispccdc_try_size(u32 input_w, u32 input_h, u32 *output_w, u32 *output_h);
++
++int ispccdc_config_size(u32 input_w, u32 input_h, u32 output_w, u32 output_h);
++
++int ispccdc_config_outlineoffset(u32 offset, u8 oddeven, u8 numlines);
++
++int ispccdc_set_outaddr(u32 addr);
++
++void ispccdc_enable(u8 enable);
++
++#ifdef ENABLE_BT_656_CAPTURE
++void ispccdc_config_y8pos(enum y8pos_mode mode);
++
++void ispccdc_config_byteswap(int swap);
++#endif
++
++int ispccdc_busy(void);
++
++void ispccdc_save_context(void);
++
++void ispccdc_restore_context(void);
++
++void ispccdc_print_status(void);
++
++int omap34xx_isp_ccdc_config(void *userspace_add);
++
++int omap34xx_isp_lsc_update(void *userspace_add);
++
++#endif		/* OMAP_ISP_CCDC_H */
+Index: git/drivers/media/video/isp/isph3a.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isph3a.c	2009-02-12 10:29:18.000000000 -0600
+@@ -0,0 +1,901 @@
++/*
++ * drivers/media/video/omap/isp/isph3a.c
++ *
++ * H3A module for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/mm.h>
++#include <linux/mman.h>
++#include <linux/syscalls.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <asm/io.h>
++#include <asm/cacheflush.h>
++#include <asm/uaccess.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "isph3a.h"
++#include "ispmmu.h"
++#include "isppreview.h"
++
++
++struct isph3a_aewb_buffer {
++	unsigned long virt_addr;
++	unsigned long phy_addr;
++	unsigned long addr_align;
++	unsigned long ispmmu_addr;
++	unsigned long mmap_addr;	/* For userspace */
++
++	u8 locked;
++	u16 frame_num;
++	struct isph3a_aewb_buffer *next;
++};
++
++static struct isph3a_aewb_status {
++	u8 initialized;
++	u8 update;
++	u8 stats_req;
++	u8 stats_done;
++	u16 frame_req;
++
++	struct isph3a_aewb_buffer h3a_buff[H3A_MAX_BUFF];
++	unsigned int stats_buf_size;
++	unsigned int min_buf_size;
++
++	u16 win_count;
++	u32 frame_count;
++	wait_queue_head_t stats_wait;
++	spinlock_t buffer_lock;
++} aewbstat;
++
++static struct isph3a_aewb_regs {
++	u32 reg_pcr;
++	u32 reg_win1;
++	u32 reg_start;
++	u32 reg_blk;
++	u32 reg_subwin;
++} aewb_regs;
++
++static struct isph3a_aewb_config aewb_config_local = {
++	.saturation_limit = 	0x3FF,
++	.win_height = 		0,	/* Range: 2 - 256 even values only */
++	.win_width = 		0,	/* Range: 6 - 256 even values only */
++	.ver_win_count =	0,	/* Range: 1 - 128 */
++	.hor_win_count = 	0,	/* Range: 1 - 36 */
++	.ver_win_start = 	0,	/* Range: 0 - 4095 */
++	.hor_win_start = 	0,	/* Range: 0 - 4095 */
++	.blk_ver_win_start = 	0,	/* Range: 0 - 4095 */
++	.blk_win_height = 	0,	/* Range: 2 - 256 even values only */
++	.subsample_ver_inc = 	0,	/* Range: 2 - 32 even values only */
++	.subsample_hor_inc = 	0,	/* Range: 2 - 32 even values only */
++	.alaw_enable = 		0,	/* AEW ALAW EN flag */
++	.aewb_enable = 		0,	/* AE AWB stats generation EN flag */
++}; /* With reset values */
++
++
++/* Structure for saving/restoring h3a module registers*/
++static struct isp_reg isph3a_reg_list[] = {
++	{ISPH3A_AEWWIN1, 0x0000},
++	{ISPH3A_AEWINSTART, 0x0000},
++	{ISPH3A_AEWINBLK, 0x0000},
++	{ISPH3A_AEWSUBWIN, 0x0000},
++	{ISPH3A_AEWBUFST, 0x0000},
++	{ISPH3A_AFPAX1, 0x0000},
++	{ISPH3A_AFPAX2, 0x0000},
++	{ISPH3A_AFPAXSTART, 0x0000},
++	{ISPH3A_AFIIRSH, 0x0000},
++	{ISPH3A_AFBUFST, 0x0000},
++	{ISPH3A_AFCOEF010, 0x0000},
++	{ISPH3A_AFCOEF032, 0x0000},
++	{ISPH3A_AFCOEF054, 0x0000},
++	{ISPH3A_AFCOEF076, 0x0000},
++	{ISPH3A_AFCOEF098, 0x0000},
++	{ISPH3A_AFCOEF0010, 0x0000},
++	{ISPH3A_AFCOEF110, 0x0000},
++	{ISPH3A_AFCOEF132, 0x0000},
++	{ISPH3A_AFCOEF154, 0x0000},
++	{ISPH3A_AFCOEF176, 0x0000},
++	{ISPH3A_AFCOEF198, 0x0000},
++	{ISPH3A_AFCOEF1010, 0x0000},
++	{ISP_TOK_TERM, 0x0000}
++};
++
++static struct ispprev_wbal h3awb_update; /* Keep changes in AEWB gains */
++static struct isph3a_aewb_buffer *active_buff;
++static struct isph3a_aewb_xtrastats h3a_xtrastats[H3A_MAX_BUFF];
++static int camnotify;
++static int wb_update;
++static void isph3a_print_status(void);
++
++void isph3a_aewb_setxtrastats(struct isph3a_aewb_xtrastats *xtrastats)
++{
++	int i;
++	if (active_buff == NULL)
++		return;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if (aewbstat.h3a_buff[i].frame_num == active_buff->frame_num) {
++			if (i == 0) {
++				if (aewbstat.h3a_buff[H3A_MAX_BUFF - 1].
++								locked == 0)
++					h3a_xtrastats[H3A_MAX_BUFF - 1] =
++								*xtrastats;
++				else
++					h3a_xtrastats[H3A_MAX_BUFF - 2] =
++								*xtrastats;
++			} else if (i == 1) {
++				if (aewbstat.h3a_buff[0].locked == 0)
++					h3a_xtrastats[0] = *xtrastats;
++				else
++					h3a_xtrastats[H3A_MAX_BUFF - 1] =
++								*xtrastats;
++			} else {
++				if (aewbstat.h3a_buff[i - 1].locked == 0)
++					h3a_xtrastats[i - 1] = *xtrastats;
++				else
++					h3a_xtrastats[i - 2] = *xtrastats;
++			}
++			return;
++		}
++	}
++}
++EXPORT_SYMBOL(isph3a_aewb_setxtrastats);
++
++/*
++ * Enables AEW engine in the H3A module.
++ * Client should configure all the AE & AWB registers in H3A before this.
++ * enable		: 1- Enables the AE & AWB engine.
++ */
++static void
++isph3a_aewb_enable(u8 enable)
++{
++	/* Before enabling AEWB we need to clear H3A bit in IRQ0 status reg */
++	omap_writel(IRQ0STATUS_H3A_AWB_DONE_IRQ, ISP_IRQ0STATUS);
++
++	if (enable) {
++		aewb_regs.reg_pcr |= ISPH3A_PCR_AEW_EN;
++		omap_writel(omap_readl(ISPH3A_PCR) | (ISPH3A_PCR_AEW_EN),
++			ISPH3A_PCR);
++		DPRINTK_ISPH3A("    H3A enabled \n");
++	} else {
++		aewb_regs.reg_pcr &= ~ISPH3A_PCR_AEW_EN;
++		omap_writel(omap_readl(ISPH3A_PCR) & ~(ISPH3A_PCR_AEW_EN),
++			ISPH3A_PCR);
++		DPRINTK_ISPH3A("    H3A disabled \n");
++	}
++	aewb_config_local.aewb_enable = enable;
++}
++
++/*
++ * Updates WB parameters. Needs to be called when no ISP Preview processing is
++ * taking place.
++ */
++void
++isph3a_update_wb(void)
++{
++	if (wb_update) {
++		isppreview_config_whitebalance(h3awb_update);
++		wb_update = 0;
++	}
++	return;
++}
++EXPORT_SYMBOL(isph3a_update_wb);
++
++/*
++ * Helper function to update h3a registers
++ */
++static void
++isph3a_aewb_update_regs(void)
++{
++	omap_writel(aewb_regs.reg_pcr, ISPH3A_PCR);
++	omap_writel(aewb_regs.reg_win1, ISPH3A_AEWWIN1);
++	omap_writel(aewb_regs.reg_start, ISPH3A_AEWINSTART);
++	omap_writel(aewb_regs.reg_blk, ISPH3A_AEWINBLK);
++	omap_writel(aewb_regs.reg_subwin, ISPH3A_AEWSUBWIN);
++
++	aewbstat.update = 0;
++	aewbstat.frame_count = 0;
++}
++
++/*
++ * Helper function to update buffer cache pages
++ */
++static void
++isph3a_aewb_update_req_buffer(struct isph3a_aewb_buffer *buffer)
++{
++	int size = aewbstat.stats_buf_size;
++
++	size = PAGE_ALIGN(size);
++	/* Update the kernel pages of the requested buffer */
++	dmac_inv_range((void *)buffer->addr_align,
++		(void *)buffer->addr_align + size);
++}
++
++/*
++ * Helper function to check for stats available of specified frame
++ * Returns 0 if stats available for frame requested; -1 otherwise.
++ */
++static int
++isph3a_aewb_stats_available(struct isph3a_aewb_data *aewbdata)
++{
++	int i;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&aewbstat.buffer_lock, irqflags);
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if ((aewbdata->frame_number == aewbstat.h3a_buff[i].frame_num)
++			&& (aewbstat.h3a_buff[i].frame_num !=
++				active_buff->frame_num)) {
++			aewbstat.h3a_buff[i].locked = 1;
++			spin_unlock_irqrestore(&aewbstat.buffer_lock, irqflags);
++			isph3a_aewb_update_req_buffer(&aewbstat.h3a_buff[i]);
++			aewbstat.h3a_buff[i].frame_num = 0;
++			aewbdata->h3a_aewb_statistics_buf = (void *)
++				aewbstat.h3a_buff[i].mmap_addr;
++			aewbdata->ts = h3a_xtrastats[i].ts;
++			aewbdata->field_count = h3a_xtrastats[i].field_count;
++			return 0;
++		}
++	}
++	spin_unlock_irqrestore(&aewbstat.buffer_lock, irqflags);
++	/* Stats unavailable */
++
++	aewbdata->h3a_aewb_statistics_buf = NULL;
++	return -1;
++}
++
++/*
++ * Helper function to link allocated buffers
++ */
++static void
++isph3a_aewb_link_buffers(void)
++{
++	int i;
++
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if ((i + 1) < H3A_MAX_BUFF) {
++			aewbstat.h3a_buff[i].next = &aewbstat.h3a_buff[i + 1];
++			h3a_xtrastats[i].next = &h3a_xtrastats[i + 1];
++		} else {
++			aewbstat.h3a_buff[i].next = &aewbstat.h3a_buff[0];
++			h3a_xtrastats[i].next = &h3a_xtrastats[0];
++		}
++	}
++}
++
++/*
++ * Helper function to unlock all buffers
++ */
++static void
++isph3a_aewb_unlock_buffers(void)
++{
++	int i;
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&aewbstat.buffer_lock, irqflags);
++	for (i = 0; i < H3A_MAX_BUFF; i++)
++		aewbstat.h3a_buff[i].locked = 0;
++
++	spin_unlock_irqrestore(&aewbstat.buffer_lock, irqflags);
++}
++
++/*
++ * Callback from ISP driver for H3A AEW interrupt
++ * status 	: IRQ0STATUS in case of MMU error, 0 for h3a interrupt
++ * arg1		: Not used as of now.
++ * arg2		: Not used as of now.
++ */
++static void
++isph3a_aewb_isr(unsigned long status, isp_vbq_callback_ptr arg1, void *arg2)
++{
++	u16 frame_align;
++
++	if ((H3A_AWB_DONE & status) != H3A_AWB_DONE)
++		return;
++
++	/* Exchange buffers */
++	active_buff = active_buff->next;
++	if (active_buff->locked == 1)
++		active_buff = active_buff->next;
++	omap_writel(active_buff->ispmmu_addr, ISPH3A_AEWBUFST);
++
++	/* Update frame counter */
++	aewbstat.frame_count++;
++	frame_align = aewbstat.frame_count;
++	if (aewbstat.frame_count > MAX_FRAME_COUNT) {
++		aewbstat.frame_count = 1;
++		frame_align++;
++	}
++	active_buff->frame_num = aewbstat.frame_count;
++
++	/* Future Stats requested? */
++	if (aewbstat.stats_req) {
++		/* Is the frame we want already done? */
++		DPRINTK_ISPH3A("waiting for frame %d\n", aewbstat.frame_req);
++		if (frame_align >= (aewbstat.frame_req + 1)) {
++			aewbstat.stats_req = 0;
++			aewbstat.stats_done = 1;
++			wake_up_interruptible(&aewbstat.stats_wait);
++		}
++	}
++
++	if (aewbstat.update)
++		isph3a_aewb_update_regs();
++
++	DPRINTK_ISPH3A(".");
++}
++
++/*
++ * Helper function to check and store user given params.
++ * As most of them are busy-lock registers, need to wait
++ * until AEW_BUSY = 0 --> to program them during ISR.
++ */
++static int
++isph3a_aewb_set_params(struct isph3a_aewb_config *user_cfg)
++{
++	/* Saturation limit */
++	if (unlikely(user_cfg->saturation_limit > MAX_SATURATION_LIM)) {
++		printk(KERN_ERR "Invalid Saturation_limit: %d\n",
++			user_cfg->saturation_limit);
++		return -EINVAL;
++	} else if (aewb_config_local.saturation_limit !=
++						user_cfg->saturation_limit) {
++		WRITE_SAT_LIM(aewb_regs.reg_pcr, user_cfg->saturation_limit);
++		aewb_config_local.saturation_limit =
++						user_cfg->saturation_limit;
++		aewbstat.update = 1;
++	}
++	/* A-Law */
++	if (aewb_config_local.alaw_enable != user_cfg->alaw_enable) {
++		WRITE_ALAW(aewb_regs.reg_pcr, user_cfg->alaw_enable);
++		aewb_config_local.alaw_enable = user_cfg->alaw_enable;
++		aewbstat.update = 1;
++	}
++	/* Window height */
++	if (unlikely((user_cfg->win_height < MIN_WIN_H)
++			|| (user_cfg->win_height > MAX_WIN_H)
++			|| (user_cfg->win_height & 0x01))) {
++		printk(KERN_ERR "Invalid window height: %d\n",
++							user_cfg->win_height);
++		return -EINVAL;
++	} else if (aewb_config_local.win_height != user_cfg->win_height) {
++		WRITE_WIN_H(aewb_regs.reg_win1, user_cfg->win_height);
++		aewb_config_local.win_height = user_cfg->win_height;
++		aewbstat.update = 1;
++	}
++	/* Window width */
++	if (unlikely((user_cfg->win_width < MIN_WIN_W)
++			|| (user_cfg->win_width > MAX_WIN_W)
++			|| (user_cfg->win_width & 0x01))) {
++		printk(KERN_ERR "Invalid window width: %d\n",
++							user_cfg->win_width);
++		return -EINVAL;
++	} else if (aewb_config_local.win_width != user_cfg->win_width) {
++		WRITE_WIN_W(aewb_regs.reg_win1, user_cfg->win_width);
++		aewb_config_local.win_width = user_cfg->win_width;
++		aewbstat.update = 1;
++	}
++	/* Vertical window count */
++	if (unlikely((user_cfg->ver_win_count < 1)
++			|| (user_cfg->ver_win_count > MAX_WINVC))) {
++		printk(KERN_ERR "Invalid vertical window count: %d\n",
++						user_cfg->ver_win_count);
++		return -EINVAL;
++	} else if (aewb_config_local.ver_win_count
++				!= user_cfg->ver_win_count){
++		WRITE_VER_C(aewb_regs.reg_win1,
++					user_cfg->ver_win_count);
++		aewb_config_local.ver_win_count	=
++					user_cfg->ver_win_count;
++		aewbstat.update = 1;
++	}
++	/* Horizontal window count */
++	if (unlikely((user_cfg->hor_win_count < 1)
++			|| (user_cfg->hor_win_count > MAX_WINHC))) {
++		printk(KERN_ERR "Invalid horizontal window count: %d\n",
++			user_cfg->hor_win_count);
++		return -EINVAL;
++	} else if (aewb_config_local.hor_win_count
++				!= user_cfg->hor_win_count){
++		WRITE_HOR_C(aewb_regs.reg_win1,
++					user_cfg->hor_win_count);
++		aewb_config_local.hor_win_count	=
++					user_cfg->hor_win_count;
++		aewbstat.update = 1;
++	}
++	/* Windows vertical start position */
++	if (unlikely(user_cfg->ver_win_start > MAX_WINSTART)) {
++		printk(KERN_ERR "Invalid vertical window start: %d\n",
++			user_cfg->ver_win_start);
++		return -EINVAL;
++	} else if (aewb_config_local.ver_win_start
++				!= user_cfg->ver_win_start){
++		WRITE_VER_WIN_ST(aewb_regs.reg_start,
++					user_cfg->ver_win_start);
++		aewb_config_local.ver_win_start	=
++					user_cfg->ver_win_start;
++		aewbstat.update = 1;
++	}
++	/* Windows horizontal start position */
++	if (unlikely(user_cfg->hor_win_start > MAX_WINSTART)) {
++		printk(KERN_ERR "Invalid horizontal window start: %d\n",
++			user_cfg->hor_win_start);
++		return -EINVAL;
++	} else if (aewb_config_local.hor_win_start
++				!= user_cfg->hor_win_start){
++		WRITE_HOR_WIN_ST(aewb_regs.reg_start,
++					 user_cfg->hor_win_start);
++		aewb_config_local.hor_win_start	=
++					user_cfg->hor_win_start;
++		aewbstat.update = 1;
++	}
++	/* Black Line vertical start position */
++	if (unlikely(user_cfg->blk_ver_win_start > MAX_WINSTART)) {
++		printk(KERN_ERR "Invalid black vertical window start: %d\n",
++			user_cfg->blk_ver_win_start);
++		return -EINVAL;
++	} else if (aewb_config_local.blk_ver_win_start
++				!= user_cfg->blk_ver_win_start){
++		WRITE_BLK_VER_WIN_ST(aewb_regs.reg_blk,
++					user_cfg->blk_ver_win_start);
++		aewb_config_local.blk_ver_win_start =
++					user_cfg->blk_ver_win_start;
++		aewbstat.update = 1;
++	}
++	/* Black line height */
++	if (unlikely((user_cfg->blk_win_height < MIN_WIN_H)
++			|| (user_cfg->blk_win_height > MAX_WIN_H)
++			|| (user_cfg->blk_win_height & 0x01))) {
++		printk(KERN_ERR "Invalid black window height: %d\n",
++			user_cfg->blk_win_height);
++		return -EINVAL;
++	} else if (aewb_config_local.blk_win_height
++				!= user_cfg->blk_win_height) {
++		WRITE_BLK_WIN_H(aewb_regs.reg_blk,
++				user_cfg->blk_win_height);
++		aewb_config_local.blk_win_height
++				= user_cfg->blk_win_height;
++		aewbstat.update = 1;
++	}
++	/* Vertical sampling point increments */
++	if (unlikely((user_cfg->subsample_ver_inc < MIN_SUB_INC)
++			|| (user_cfg->subsample_ver_inc > MAX_SUB_INC)
++			|| (user_cfg->subsample_ver_inc & 0x01))) {
++		printk(KERN_ERR "Invalid vertical subsample increment: %d\n",
++			user_cfg->subsample_ver_inc);
++		return -EINVAL;
++	} else if (aewb_config_local.subsample_ver_inc
++				!= user_cfg->subsample_ver_inc) {
++		WRITE_SUB_VER_INC(aewb_regs.reg_subwin,
++						user_cfg->subsample_ver_inc);
++		aewb_config_local.subsample_ver_inc
++					= user_cfg->subsample_ver_inc;
++		aewbstat.update = 1;
++	}
++	/* Horizontal sampling point increments */
++	if (unlikely((user_cfg->subsample_hor_inc < MIN_SUB_INC)
++			|| (user_cfg->subsample_hor_inc > MAX_SUB_INC)
++			|| (user_cfg->subsample_hor_inc & 0x01))) {
++		printk(KERN_ERR "Invalid horizontal subsample increment: %d\n",
++			user_cfg->subsample_hor_inc);
++		return -EINVAL;
++	} else if (aewb_config_local.subsample_hor_inc
++				!= user_cfg->subsample_hor_inc) {
++		WRITE_SUB_HOR_INC(aewb_regs.reg_subwin,
++						user_cfg->subsample_hor_inc);
++		aewb_config_local.subsample_hor_inc
++					= user_cfg->subsample_hor_inc;
++		aewbstat.update = 1;
++	}
++
++	if ((!aewbstat.initialized) || (0 == aewb_config_local.aewb_enable)) {
++		isph3a_aewb_update_regs();
++		aewbstat.initialized = 1;
++	}
++	return 0;
++}
++
++/*
++ * Helper function to munmap kernel buffers from user space.
++ */
++static int
++isph3a_aewb_munmap(struct isph3a_aewb_buffer *buffer)
++{
++	/* TO DO: munmap succesfully the kernel buffers, so they can be
++	   remmaped again */
++	buffer->mmap_addr = 0;
++	return 0;
++}
++
++/*
++ * Helper function to mmap buffers to user space.
++ * buffer passed need to already have a valid physical address: buffer->phy_addr
++ * It returns user pointer as unsigned long in buffer->mmap_addr
++ */
++static int
++isph3a_aewb_mmap_buffers(struct isph3a_aewb_buffer *buffer)
++{
++	struct vm_area_struct vma;
++	struct mm_struct *mm = current->mm;
++	int size = aewbstat.stats_buf_size;
++	unsigned long addr = 0;
++	unsigned long pgoff = 0, flags = MAP_SHARED | MAP_ANONYMOUS;
++	unsigned long prot = PROT_READ | PROT_WRITE;
++	void *pos = (void *) buffer->addr_align;
++
++	size = PAGE_ALIGN(size);
++
++	addr = get_unmapped_area(NULL, addr, size, pgoff, flags);
++	vma.vm_mm = mm;
++	vma.vm_start = addr;
++	vma.vm_end = addr + size;
++	vma.vm_flags = calc_vm_prot_bits(prot) | calc_vm_flag_bits(flags);
++	vma.vm_pgoff = pgoff;
++	vma.vm_file = NULL;
++#ifndef ENABLE_BT_656_CAPTURE
++	vma.vm_page_prot = protection_map[vma.vm_flags];
++#else
++	vma.vm_page_prot = vm_get_page_prot(vma.vm_flags);
++#endif
++
++	while (size > 0) {
++		if (vm_insert_page(&vma, addr, vmalloc_to_page(pos)))
++			return -EAGAIN;
++		addr += PAGE_SIZE;
++		pos += PAGE_SIZE;
++		size -= PAGE_SIZE;
++	}
++
++	buffer->mmap_addr = vma.vm_start;
++	return 0;
++}
++
++/*
++ * API to configure AEW registers and enable/disable H3A engine
++ */
++int
++isph3a_aewb_configure(struct isph3a_aewb_config *aewbcfg)
++{
++	int ret = 0;
++	int i;
++	int win_count = 0;
++
++	if (NULL == aewbcfg) {
++		printk(KERN_ERR "Null argument in configuration. \n");
++		return -EINVAL;
++	}
++
++	if (!aewbstat.initialized) {
++		DPRINTK_ISPH3A("Setting callback for H3A\n");
++		ret = isp_set_callback(CBK_H3A_AWB_DONE, isph3a_aewb_isr,
++					(void *)NULL, (void *)NULL);
++		if (ret) {
++			printk(KERN_ERR "No callback for H3A\n");
++			return ret;
++		}
++	}
++
++	ret = isph3a_aewb_set_params(aewbcfg);
++	if (ret) {
++		printk(KERN_ERR "Invalid parameters! \n");
++		return ret;
++	}
++
++	win_count = (aewbcfg->ver_win_count * aewbcfg->hor_win_count);
++	win_count += aewbcfg->hor_win_count; /* Blk windows row*/
++	ret = (win_count / 8);
++	win_count += (win_count % 8)? 1: 0;
++	win_count += ret;
++
++	aewbstat.win_count = win_count;
++
++	if (aewbstat.stats_buf_size && ((win_count * AEWB_PACKET_SIZE)
++					> aewbstat.stats_buf_size)) {
++		DPRINTK_ISPH3A("There was a previous buffer... \n");
++		isph3a_aewb_enable(0);
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			isph3a_aewb_munmap(&aewbstat.h3a_buff[i]);
++			ispmmu_unmap(aewbstat.h3a_buff[i].ispmmu_addr);
++			dma_free_coherent(NULL,
++				aewbstat.min_buf_size + 64,
++				(void *)aewbstat.h3a_buff[i].virt_addr,
++				(dma_addr_t)aewbstat.h3a_buff[i].phy_addr);
++			aewbstat.h3a_buff[i].virt_addr = 0;
++		}
++		aewbstat.stats_buf_size = 0;
++	}
++
++	if (!aewbstat.h3a_buff[0].virt_addr) {
++		aewbstat.stats_buf_size = win_count * AEWB_PACKET_SIZE;
++		aewbstat.min_buf_size = PAGE_ALIGN(aewbstat.stats_buf_size);
++
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			aewbstat.h3a_buff[i].virt_addr =
++					(unsigned long)dma_alloc_coherent(NULL,
++						aewbstat.min_buf_size,
++						(dma_addr_t *)
++						&aewbstat.h3a_buff[i].
++						phy_addr, GFP_KERNEL |
++						GFP_DMA);
++			if (aewbstat.h3a_buff[i].virt_addr == 0) {
++				printk(KERN_ERR "Can't acquire memory for "
++					"buffer[%d]\n", i);
++				return -ENOMEM;
++			}
++			aewbstat.h3a_buff[i].addr_align =
++					aewbstat.h3a_buff[i].virt_addr;
++			while ((aewbstat.h3a_buff[i].addr_align &
++							0xFFFFFFC0) !=
++							aewbstat.h3a_buff[i].
++							addr_align)
++				aewbstat.h3a_buff[i].addr_align++;
++			aewbstat.h3a_buff[i].ispmmu_addr =
++							ispmmu_map(aewbstat.
++							h3a_buff[i].phy_addr,
++							aewbstat.min_buf_size);
++		}
++		isph3a_aewb_unlock_buffers();
++		isph3a_aewb_link_buffers();
++
++		/* First active buffer */
++		if (active_buff == NULL)
++			active_buff = &aewbstat.h3a_buff[0];
++		omap_writel(active_buff->ispmmu_addr, ISPH3A_AEWBUFST);
++	}
++	/* Always remap when calling Configure */
++	for (i = 0; i < H3A_MAX_BUFF; i++) {
++		if (aewbstat.h3a_buff[i].mmap_addr) {
++			isph3a_aewb_munmap(&aewbstat.h3a_buff[i]);
++			DPRINTK_ISPH3A("We have munmaped buffer 0x%lX\n",
++				aewbstat.h3a_buff[i].virt_addr);
++		}
++		isph3a_aewb_mmap_buffers(&aewbstat.h3a_buff[i]);
++		DPRINTK_ISPH3A("buff[%d] addr is:\n    virt    0x%lX\n"
++					"    aligned 0x%lX\n"
++					"    phys    0x%lX\n"
++					"    ispmmu  0x%08lX\n"
++					"    mmapped 0x%lX\n", i,
++					aewbstat.h3a_buff[i].virt_addr,
++					aewbstat.h3a_buff[i].addr_align,
++					aewbstat.h3a_buff[i].phy_addr,
++					aewbstat.h3a_buff[i].ispmmu_addr,
++					aewbstat.h3a_buff[i].mmap_addr);
++	}
++	/* Enable/disable engine */
++	isph3a_aewb_enable(aewbcfg->aewb_enable);
++	isph3a_print_status();
++
++	return 0;
++}
++EXPORT_SYMBOL(isph3a_aewb_configure);
++
++
++/*
++ * This API allows the user to update White Balance gains, as well as
++ * exposure time and analog gain. It is also used to request frame
++ * statistics.
++ */
++int
++isph3a_aewb_request_statistics(struct isph3a_aewb_data *aewbdata)
++{
++	int ret = 0;
++	u16 frame_diff = 0;
++	u16 frame_cnt = aewbstat.frame_count;
++	wait_queue_t wqt;
++
++	/*
++	 * This will be replaced by the gain settings using
++	 * Master->Slave approach in camera driver
++	 */
++
++	/*
++	u32 exp_time = aewbdata->shutter;
++	u16 gain = aewbdata->gain;
++	*/
++
++	if (!aewb_config_local.aewb_enable) {
++		printk(KERN_ERR "H3A engine not enabled\n");
++		return -EINVAL;
++	}
++	aewbdata->h3a_aewb_statistics_buf = NULL;
++
++	DPRINTK_ISPH3A("User data received: \n");
++	DPRINTK_ISPH3A("Digital gain = 0x%04x\n", aewbdata->dgain);
++	DPRINTK_ISPH3A("WB gain b *=   0x%04x\n", aewbdata->wb_gain_b);
++	DPRINTK_ISPH3A("WB gain r *=   0x%04x\n", aewbdata->wb_gain_r);
++	DPRINTK_ISPH3A("WB gain gb =   0x%04x\n", aewbdata->wb_gain_gb);
++	DPRINTK_ISPH3A("WB gain gr =   0x%04x\n", aewbdata->wb_gain_gr);
++	DPRINTK_ISPH3A("ISP AEWB request status wait for interrupt\n");
++
++	if (aewbdata->update != 0) {
++		if (aewbdata->update & SET_DIGITAL_GAIN)
++			h3awb_update.dgain = (u16)aewbdata->dgain;
++		if (aewbdata->update & SET_COLOR_GAINS) {
++			h3awb_update.coef3 = (u8)aewbdata->wb_gain_b;
++			h3awb_update.coef2 = (u8)aewbdata->wb_gain_gr;
++			h3awb_update.coef1 = (u8)aewbdata->wb_gain_gb;
++			h3awb_update.coef0 = (u8)aewbdata->wb_gain_r;
++		}
++		if (aewbdata->update & (SET_COLOR_GAINS | SET_DIGITAL_GAIN))
++			wb_update = 1;
++
++		if (aewbdata->update & REQUEST_STATISTICS) {
++			isph3a_aewb_unlock_buffers();
++
++			/* Stats available? */
++			DPRINTK_ISPH3A("Stats available?\n");
++			ret = isph3a_aewb_stats_available(aewbdata);
++			if (!ret)
++				goto out;
++
++			DPRINTK_ISPH3A("Stats in near future?\n");
++			/* Stats in near future? */
++			if (aewbdata->frame_number > frame_cnt) {
++				frame_diff = aewbdata->frame_number - frame_cnt;
++			} else if (aewbdata->frame_number < frame_cnt) {
++				if ((frame_cnt > (MAX_FRAME_COUNT -
++							MAX_FUTURE_FRAMES))
++							&& (aewbdata->
++							frame_number
++							< MAX_FRAME_COUNT))
++					frame_diff = aewbdata->frame_number
++							+ MAX_FRAME_COUNT
++							- frame_cnt;
++				else {
++					/* Frame unavailable */
++					frame_diff = MAX_FUTURE_FRAMES + 1;
++					aewbdata->h3a_aewb_statistics_buf =
++									NULL;
++				}
++			}
++
++			if (frame_diff > MAX_FUTURE_FRAMES) {
++				printk(KERN_ERR "Invalid frame requested\n");
++
++			} else if (!camnotify) {
++				/* Block until frame in near future completes */
++				aewbstat.frame_req = aewbdata->frame_number;
++				aewbstat.stats_req = 1;
++				aewbstat.stats_done = 0;
++				init_waitqueue_entry(&wqt, current);
++				ret = wait_event_interruptible
++						(aewbstat.stats_wait,
++						aewbstat.stats_done == 1);
++				if (ret < 0)
++					return ret;
++
++				DPRINTK_ISPH3A("ISP AEWB request status"
++						" interrupt raised\n");
++				/* Stats now available */
++				ret = isph3a_aewb_stats_available(aewbdata);
++				if (ret) {
++					DPRINTK_ISPH3A
++						("After waiting for stats,"
++						" stats not available!!\n");
++				}
++			}
++		}
++	}
++out:
++	aewbdata->curr_frame = aewbstat.frame_count;
++
++	return 0;
++}
++EXPORT_SYMBOL(isph3a_aewb_request_statistics);
++
++/*
++ * Module Initialisation.
++ */
++static int __init
++isph3a_aewb_init(void)
++{
++	memset(&aewbstat, 0, sizeof(aewbstat));
++	memset(&aewb_regs, 0, sizeof(aewb_regs));
++
++	init_waitqueue_head(&aewbstat.stats_wait);
++	spin_lock_init(&aewbstat.buffer_lock);
++	return 0;
++}
++
++/*
++ * Module exit.
++ */
++static void
++isph3a_aewb_cleanup(void)
++{
++	int i;
++	isph3a_aewb_enable(0);
++	isp_unset_callback(CBK_H3A_AWB_DONE);
++
++	if (aewbstat.h3a_buff) {
++		/* Free buffers */
++		for (i = 0; i < H3A_MAX_BUFF; i++) {
++			ispmmu_unmap(aewbstat.h3a_buff[i].ispmmu_addr);
++			dma_free_coherent(NULL,
++				aewbstat.min_buf_size + 64,
++				(void *)aewbstat.h3a_buff[i].virt_addr,
++				(dma_addr_t)aewbstat.h3a_buff[i].phy_addr);
++		}
++	}
++	memset(&aewbstat, 0, sizeof(aewbstat));
++	memset(&aewb_regs, 0, sizeof(aewb_regs));
++}
++
++/*
++ * Debug print
++ */
++static void
++isph3a_print_status(void)
++{
++	DPRINTK_ISPH3A("ISPH3A_PCR = 0x%08x\n",
++			omap_readl(ISPH3A_PCR));
++	DPRINTK_ISPH3A("ISPH3A_AEWWIN1 = 0x%08x\n",
++			omap_readl(ISPH3A_AEWWIN1));
++	DPRINTK_ISPH3A("ISPH3A_AEWINSTART = 0x%08x\n",
++			omap_readl(ISPH3A_AEWINSTART));
++	DPRINTK_ISPH3A("ISPH3A_AEWINBLK = 0x%08x\n",
++			omap_readl(ISPH3A_AEWINBLK));
++	DPRINTK_ISPH3A("ISPH3A_AEWSUBWIN = 0x%08x\n",
++			omap_readl(ISPH3A_AEWSUBWIN));
++	DPRINTK_ISPH3A("ISPH3A_AEWBUFST = 0x%08x\n",
++			omap_readl(ISPH3A_AEWBUFST));
++	DPRINTK_ISPH3A("stats windows = %d\n",
++			aewbstat.win_count);
++	DPRINTK_ISPH3A("stats buff size = %d\n",
++			aewbstat.stats_buf_size);
++}
++void
++isph3a_notify(int notify)
++{
++	camnotify = notify;
++	if (camnotify && aewbstat.initialized) {
++	printk(KERN_DEBUG "Warning Camera Off \n");
++	aewbstat.stats_req = 0;
++	aewbstat.stats_done = 1;
++	wake_up_interruptible(&aewbstat.stats_wait);
++	}
++}
++EXPORT_SYMBOL(isph3a_notify);
++/*
++ * Saves the values of the h3a module registers.
++ */
++void
++isph3a_save_context(void)
++{
++	DPRINTK_ISPH3A(" Saving context\n");
++	isp_save_context(isph3a_reg_list);
++}
++EXPORT_SYMBOL(isph3a_save_context);
++
++/*
++ * Restores the values of the h3a module registers.
++ */
++void
++isph3a_restore_context(void)
++{
++	DPRINTK_ISPH3A(" Restoring context\n");
++	isp_restore_context(isph3a_reg_list);
++}
++EXPORT_SYMBOL(isph3a_restore_context);
++
++module_init(isph3a_aewb_init);
++module_exit(isph3a_aewb_cleanup);
++
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("H3A ISP Module");
++MODULE_LICENSE("GPL");
++
+Index: git/drivers/media/video/isp/isph3a.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isph3a.h	2009-02-12 15:25:41.000000000 -0600
+@@ -0,0 +1,197 @@
++/*
++ * drivers/media/video/omap/isp/isph3a.h
++ *
++ * Include file for H3A module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_H3A_H
++#define OMAP_ISP_H3A_H
++
++#define AEWB_PACKET_SIZE	16
++#define H3A_MAX_BUFF		5
++
++/* Flags for changed registers */
++#define PCR_CHNG		(1 << 0)
++#define AEWWIN1_CHNG		(1 << 1)
++#define AEWINSTART_CHNG		(1 << 2)
++#define AEWINBLK_CHNG		(1 << 3)
++#define AEWSUBWIN_CHNG		(1 << 4)
++#define PRV_WBDGAIN_CHNG	(1 << 5)
++#define PRV_WBGAIN_CHNG		(1 << 6)
++
++/* Flags for update field */
++#define REQUEST_STATISTICS      (1 << 0)
++#define SET_COLOR_GAINS         (1 << 1)
++#define SET_DIGITAL_GAIN        (1 << 2)
++#define SET_EXPOSURE            (1 << 3)
++#define SET_ANALOG_GAIN         (1 << 4)
++
++#define MAX_SATURATION_LIM	1023
++#define MIN_WIN_H		2
++#define MAX_WIN_H		256
++#define MIN_WIN_W		6
++#define MAX_WIN_W		256
++#define MAX_WINVC		128
++#define MAX_WINHC		36
++#define MAX_WINSTART		4095
++#define MIN_SUB_INC		2
++#define MAX_SUB_INC		32
++
++#define MAX_FRAME_COUNT         0x0FFF
++#define MAX_FUTURE_FRAMES	10
++
++/* ISPH3A REGISTERS bits */
++#define ISPH3A_PCR_AF_EN    		(1 << 0)
++#define ISPH3A_PCR_AF_ALAW_EN		(1 << 1)
++#define ISPH3A_PCR_AF_MED_EN		(1 << 2)
++#define ISPH3A_PCR_AF_BUSY		(1 << 15)
++#define ISPH3A_PCR_AEW_EN    		(1 << 16)
++#define ISPH3A_PCR_AEW_ALAW_EN		(1 << 17)
++#define ISPH3A_PCR_AEW_BUSY  		(1 << 18)
++
++#define WRITE_SAT_LIM(reg, sat_limit)	\
++		(reg = (reg & (~(ISPH3A_PCR_AEW_AVE2LMT_MASK))) \
++			| (sat_limit << ISPH3A_PCR_AEW_AVE2LMT_SHIFT))
++
++#define WRITE_ALAW(reg, alaw_en) \
++		(reg = (reg & (~(ISPH3A_PCR_AEW_ALAW_EN))) \
++			| ((alaw_en & ISPH3A_PCR_AF_ALAW_EN) \
++			<< ISPH3A_PCR_AEW_ALAW_EN_SHIFT))
++
++#define WRITE_WIN_H(reg, height) \
++		(reg = (reg & (~(ISPH3A_AEWWIN1_WINH_MASK))) \
++			| (((height >> 1) - 1) << ISPH3A_AEWWIN1_WINH_SHIFT))
++
++#define WRITE_WIN_W(reg, width) \
++		(reg = (reg & (~(ISPH3A_AEWWIN1_WINW_MASK))) \
++			| (((width >> 1) - 1) << ISPH3A_AEWWIN1_WINW_SHIFT))
++
++#define WRITE_VER_C(reg, ver_count) \
++		(reg = (reg & ~(ISPH3A_AEWWIN1_WINVC_MASK)) \
++			| ((ver_count - 1) << ISPH3A_AEWWIN1_WINVC_SHIFT))
++
++#define WRITE_HOR_C(reg, hor_count) \
++		(reg = (reg & ~(ISPH3A_AEWWIN1_WINHC_MASK)) \
++			| ((hor_count - 1) << ISPH3A_AEWWIN1_WINHC_SHIFT))
++
++#define WRITE_VER_WIN_ST(reg, ver_win_st) \
++		(reg = (reg & ~(ISPH3A_AEWINSTART_WINSV_MASK)) \
++			| (ver_win_st << ISPH3A_AEWINSTART_WINSV_SHIFT))
++
++#define WRITE_HOR_WIN_ST(reg, hor_win_st) \
++		(reg = (reg & ~(ISPH3A_AEWINSTART_WINSH_MASK)) \
++			| (hor_win_st << ISPH3A_AEWINSTART_WINSH_SHIFT))
++
++#define WRITE_BLK_VER_WIN_ST(reg, blk_win_st) \
++		(reg = (reg & ~(ISPH3A_AEWINBLK_WINSV_MASK)) \
++			| (blk_win_st << ISPH3A_AEWINBLK_WINSV_SHIFT))
++
++#define WRITE_BLK_WIN_H(reg, height) \
++		(reg = (reg & ~(ISPH3A_AEWINBLK_WINH_MASK)) \
++			| (((height >> 1) - 1) << ISPH3A_AEWINBLK_WINH_SHIFT))
++
++#define WRITE_SUB_VER_INC(reg, sub_ver_inc) \
++		(reg = (reg & ~(ISPH3A_AEWSUBWIN_AEWINCV_MASK)) \
++		| (((sub_ver_inc >> 1) - 1) << ISPH3A_AEWSUBWIN_AEWINCV_SHIFT))
++
++#define WRITE_SUB_HOR_INC(reg, sub_hor_inc) \
++		(reg = (reg & ~(ISPH3A_AEWSUBWIN_AEWINCH_MASK)) \
++		| (((sub_hor_inc >> 1) - 1) << ISPH3A_AEWSUBWIN_AEWINCH_SHIFT))
++
++
++struct isph3a_aewb_config {
++	u16 saturation_limit;
++	u16 win_height;          /* Range: 2 - 256 */
++	u16 win_width;           /* Range: 2 - 256 */
++	u16 ver_win_count;       /* vertical window count: 1 - 128 */
++	u16 hor_win_count;       /* horizontal window count: 1 - 36 */
++	u16 ver_win_start;       /* ver window start position: 0 - 4095 */
++	u16 hor_win_start;       /* hor window start position: 0 - 4095 */
++	u16 blk_ver_win_start;   /* black line ver window start pos: 0 -4095 */
++	u16 blk_win_height;      /* black line height: 2 - 256 */
++	u16 subsample_ver_inc;   /* ver distance between subsamples: 2 - 32 */
++	u16 subsample_hor_inc;   /* hor distance between subsamples: 2 - 32 */
++	u8   alaw_enable;        /* enable AEW ALAW flag */
++	u8   aewb_enable;        /* AE AWB enable flag */
++};
++
++struct isph3a_aewb_data {
++	void *h3a_aewb_statistics_buf;  /* Pointer to pass to user */
++	u32 shutter;                 /* Shutter speed */
++	u16 gain;                    /* Sensor analog Gain */
++	u32 shutter_cap;             /* Shutter speed for capture */
++	u16 gain_cap;                /* Sensor Gain for capture */
++
++	u16 dgain;                   /* White balance digital gain */
++	u16 wb_gain_b;               /* White balance color gain blue */
++	u16 wb_gain_r;               /* White balance color gain red */
++	u16 wb_gain_gb;              /* White balance color gain green blue */
++	u16 wb_gain_gr;              /* White balance color gain green red */
++
++	u16 frame_number;            /* Frame number of requested stats */
++	u16 curr_frame;              /* Current frame number being processed */
++	u8 update;                   /* Bitwise flags to update parameters */
++
++	struct timeval ts;		/* Timestamp of returned framestats */
++	unsigned long field_count;	/*
++					 * Sequence number of returned
++					 * framestats
++					 */
++};
++
++struct isph3a_aewb_xtrastats {
++	struct timeval ts;
++	unsigned long field_count;
++
++	struct isph3a_aewb_xtrastats *next;
++};
++
++void isph3a_aewb_setxtrastats(struct isph3a_aewb_xtrastats *xtrastats);
++
++#include <linux/autoconf.h>
++#ifdef CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER
++/*
++ * Sets the parameters in H3A registers
++ */
++int isph3a_aewb_configure(struct isph3a_aewb_config *aewbcfg);
++
++/*
++ * Requests AE and AWB statistics
++ */
++int isph3a_aewb_request_statistics(struct isph3a_aewb_data *aewbdata);
++
++/*
++ * Saves h3a context
++ */
++void isph3a_save_context(void);
++
++/*
++ * Restores h3a context
++ */
++void isph3a_restore_context(void);
++
++#else
++#define isph3a_aewb_configure(x) -EFAULT
++#define isph3a_aewb_request_statistics(x) -EFAULT
++#define isph3a_save_context()
++#define isph3a_restore_context()
++
++#endif
++
++/*
++ * Update WB values after a H3A statistics request
++ */
++void isph3a_update_wb(void);
++
++void isph3a_notify(int notify);
++#endif   /* OMAP_ISP_H3A_H */
+Index: git/drivers/media/video/isp/isphist.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isphist.h	2009-02-12 15:23:05.000000000 -0600
+@@ -0,0 +1,145 @@
++/*
++ * drivers/media/video/isp/isphist.h
++ *
++ * Include file for HISTOGRAM module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_HIST_H
++#define OMAP_ISP_HIST_H
++
++/* Flags for number of bins */
++#define BINS_32                 0x0
++#define BINS_64                 0x1
++#define BINS_128                0x2
++#define BINS_256                0x3
++
++#define MAX_REGIONS             0x4
++#define MAX_WB_GAIN             255
++#define MIN_WB_GAIN             0x0
++#define MAX_BIT_WIDTH           14
++#define MIN_BIT_WIDTH           8
++
++#define ISPHIST_PCR_EN		(1 << 0)
++#define HIST_MEM_SIZE          	1024
++#define ISPHIST_CNT_CLR_EN    	(1 << 7)
++
++#define WRITE_SOURCE(reg, source)	\
++		(reg = (reg & ~(ISPHIST_CNT_SOURCE_MASK)) \
++    | (source << ISPHIST_CNT_SOURCE_SHIFT))
++
++#define WRITE_HV_INFO(reg, hv_info) \
++    (reg = ((reg & ~(ISPHIST_HV_INFO_MASK)) \
++    | (hv_info & ISPHIST_HV_INFO_MASK)))
++
++#define WRITE_RADD(reg, radd) \
++		(reg = (reg & ~(ISPHIST_RADD_MASK)) \
++    | (radd << ISPHIST_RADD_SHIFT))
++
++#define WRITE_RADD_OFF(reg, radd_off) \
++    (reg = (reg & ~(ISPHIST_RADD_OFF_MASK)) \
++    | (radd_off << ISPHIST_RADD_OFF_SHIFT))
++
++#define WRITE_BIT_SHIFT(reg, bit_shift) \
++    (reg = (reg & ~(ISPHIST_CNT_SHIFT_MASK)) \
++    | (bit_shift << ISPHIST_CNT_SHIFT_SHIFT))
++
++#define WRITE_DATA_SIZE(reg, data_size) \
++    (reg = (reg & ~(ISPHIST_CNT_DATASIZE_MASK)) \
++    | (data_size << ISPHIST_CNT_DATASIZE_SHIFT))
++
++#define WRITE_NUM_BINS(reg, num_bins) \
++    (reg = (reg & ~(ISPHIST_CNT_BINS_MASK)) \
++    | (num_bins << ISPHIST_CNT_BINS_SHIFT))
++
++#define WRITE_WB_R(reg, reg_wb_gain) \
++    reg = ((reg & ~(ISPHIST_WB_GAIN_WG00_MASK)) \
++    | (reg_wb_gain << ISPHIST_WB_GAIN_WG00_SHIFT))
++
++#define WRITE_WB_RG(reg, reg_wb_gain) \
++    (reg = (reg & ~(ISPHIST_WB_GAIN_WG01_MASK)) \
++    | (reg_wb_gain << ISPHIST_WB_GAIN_WG01_SHIFT))
++
++#define WRITE_WB_B(reg, reg_wb_gain) \
++    (reg = (reg & ~(ISPHIST_WB_GAIN_WG02_MASK)) \
++    | (reg_wb_gain << ISPHIST_WB_GAIN_WG02_SHIFT))
++
++#define WRITE_WB_BG(reg, reg_wb_gain) \
++    (reg = (reg & ~(ISPHIST_WB_GAIN_WG03_MASK)) \
++    | (reg_wb_gain << ISPHIST_WB_GAIN_WG03_SHIFT))
++
++#define WRITE_REG_HORIZ(reg, reg_n_hor) \
++    (reg = ((reg & ~ISPHIST_REGHORIZ_MASK) \
++    | (reg_n_hor & ISPHIST_REGHORIZ_MASK)))
++
++#define WRITE_REG_VERT(reg, reg_n_vert) \
++    (reg = ((reg & ~ISPHIST_REGVERT_MASK) \
++    | (reg_n_vert & ISPHIST_REGVERT_MASK)))
++
++struct isp_hist_config {
++	u8 hist_source;		/* CCDC or Memory */
++	u8 input_bit_width;	/* Needed o know the size per pixel */
++	u8 hist_frames;		/* Num of frames to be processed and accumulated */
++	u8 hist_h_v_info;	/* frame-input width and height if source is memory */
++	u16 hist_radd;		/* frame-input address in memory */
++	u16 hist_radd_off;	/* line-offset for frame-input */
++	u16 hist_bins;		/* number of bins: 32, 64, 128, or 256 */
++	u16 wb_gain_R;		/* White Balance Field-to-Pattern Assignments */
++	u16 wb_gain_RG;		/* White Balance Field-to-Pattern Assignments */
++	u16 wb_gain_B;		/* White Balance Field-to-Pattern Assignments */
++	u16 wb_gain_BG;		/* White Balance Field-to-Pattern Assignments */
++	u8 num_regions;		/* number of regions to be configured */
++	u16 reg0_hor;		/* Region 0 size and position */
++	u16 reg0_ver;		/* Region 0 size and position */
++	u16 reg1_hor;		/* Region 1 size and position */
++	u16 reg1_ver;		/* Region 1 size and position */
++	u16 reg2_hor;		/* Region 2 size and position */
++	u16 reg2_ver;		/* Region 2 size and position */
++	u16 reg3_hor;		/* Region 3 size and position */
++	u16 reg3_ver;		/* Region 3 size and position */
++};
++
++struct isp_hist_data {
++
++	u32 *hist_statistics_buf;	/* Pointer to pass to user */
++
++};
++
++#include <linux/autoconf.h>
++#ifdef CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER
++/*
++ * Validate parameters to be stored in HIST registers
++ */
++int isp_hist_configure(struct isp_hist_config *histcfg);
++
++/*
++ * Requests Histrogram statistics
++ */
++int isp_hist_request_statistics(struct isp_hist_data *histdata);
++
++/*
++ * Saves hist context
++ */
++void isphist_save_context(void);
++
++/*
++ * Restores hist context
++ */
++void isphist_restore_context(void);
++#else
++#define isp_hist_configure(x) -EFAULT
++#define isp_hist_request_statistics(x) -EFAULT
++#define isphist_save_context() 
++#define isphist_restore_context() 
++#endif
++
++#endif				/* OMAP_ISP_HIST */
+Index: git/drivers/media/video/isp/ispmmu.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/ispmmu.c	2009-02-12 11:41:19.000000000 -0600
+@@ -0,0 +1,792 @@
++/*
++ * drivers/media/video/isp/ispmmu.c
++ *
++ * Driver Library for ISP MMU module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/interrupt.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <linux/mm.h>
++
++#include <asm/io.h>
++#include <asm/byteorder.h>
++#include <asm/scatterlist.h>
++#include <asm/irq.h>
++
++
++#include "isp.h"
++#include "ispreg.h"
++#include "ispmmu.h"
++
++
++#define ISPMMU_L1D_TYPE_SHIFT		0
++#define ISPMMU_L1D_TYPE_MASK		0x3
++#define ISPMMU_L1D_TYPE_FAULT		0
++#define ISPMMU_L1D_TYPE_FAULT1		3
++#define ISPMMU_L1D_TYPE_PAGE		1
++#define ISPMMU_L1D_TYPE_SECTION		2
++#define ISPMMU_L1D_PAGE_ADDR_SHIFT	10
++
++#define ISPMMU_L2D_TYPE_SHIFT		0
++#define ISPMMU_L2D_TYPE_MASK		0x3
++#define ISPMMU_L2D_TYPE_FAULT		0
++#define ISPMMU_L2D_TYPE_LARGE_PAGE	1
++#define ISPMMU_L2D_TYPE_SMALL_PAGE	2
++#define ISPMMU_L2D_SMALL_ADDR_SHIFT	12
++#define ISPMMU_L2D_SMALL_ADDR_MASK	0xFFFFF000
++#define ISPMMU_L2D_M_ACCESSBASED	(1 << 11)
++#define ISPMMU_L2D_E_BIGENDIAN		(1 << 9)
++#define ISPMMU_L2D_ES_SHIFT		4
++#define ISPMMU_L2D_ES_MASK		~(3 << 4)
++#define ISPMMU_L2D_ES_8BIT		0
++#define ISPMMU_L2D_ES_16BIT		1
++#define ISPMMU_L2D_ES_32BIT		2
++#define ISPMMU_L2D_ES_NOENCONV		3
++
++#define ISPMMU_TTB_ENTRIES_NR		4096
++
++/* Number 1MB entries in TTB in one 32MB region */
++#define ISPMMU_REGION_ENTRIES_NR	32
++
++/* 128 region entries */
++#define ISPMMU_REGION_NR \
++			(ISPMMU_TTB_ENTRIES_NR / ISPMMU_REGION_ENTRIES_NR)
++
++/* Each region is 32MB */
++#define ISPMMU_REGION_SIZE	(ISPMMU_REGION_ENTRIES_NR * (1 << 20))
++
++/* Number of entries per L2 Page table */
++#define ISPMMU_L2D_ENTRIES_NR		256
++
++/*
++ * Statically allocate 16KB for L2 page tables. 16KB can be used for
++ * up to 16 L2 page tables which cover up to 16MB space. We use an array of 16
++ * to keep track of these 16 L2 page table's status.
++ */
++#define L2P_TABLE_SIZE		1024
++#define L2P_TABLE_NR 		41 /* Currently supports 4*5MP shots */
++#define L2P_TABLES_SIZE 	(L2P_TABLE_SIZE * L2P_TABLE_NR)
++
++/* Extra memory allocated to get ttb aligned on 16KB */
++#define ISPMMU_TTB_MISALIGN_SIZE	0x3000
++
++/* Page structure for statically allocated l1 and l2 page tables */
++static struct page *ttb_page;
++static struct page *l2p_page;
++
++/*
++* Allocate the same number as of TTB entries for easy tracking
++* even though L2P tables are limited to 16 or so
++*/
++static u32 l2p_table_addr[4096];
++
++/* An array of flags to keep the L2P table allotted */
++static int l2p_table_allotted[L2P_TABLE_NR];
++
++/* TTB virtual and physical address */
++static u32 *ttb, ttb_p;
++
++/* Worst case allocation for TTB for 16KB alignment */
++static u32 ttb_aligned_size;
++
++/* L2 page table base virtural and physical address */
++static u32 l2_page_cache, l2_page_cache_p;
++
++/* Structure for Mapping Attributes in the L1, L2 descriptor*/
++struct ispmmu_mapattr{
++	enum ISPMMU_MAP_ENDIAN endianism;
++	enum ISPMMU_MAP_ELEMENTSIZE element_size;
++	enum ISPMMU_MAP_MIXEDREGION mixed_size;
++	enum ISPMMU_MAP_SIZE map_size;
++};
++
++static struct ispmmu_mapattr l1_mapattr_obj, l2_mapattr_obj;
++
++/* Structure for saving/restoring mmu module registers*/
++static struct isp_reg ispmmu_reg_list[] = {
++	{ISPMMU_SYSCONFIG, 0x0000},
++	{ISPMMU_IRQENABLE, 0x0000},
++	{ISPMMU_CNTL, 0x0000},
++	{ISPMMU_TTB, 0x0000},
++	{ISPMMU_LOCK, 0x0000},
++	{ISPMMU_LD_TLB, 0x0000},
++	{ISPMMU_CAM, 0x0000},
++	{ISPMMU_RAM, 0x0000},
++	{ISPMMU_GFLUSH, 0x0000},
++	{ISPMMU_FLUSH_ENTRY, 0x0000},
++	{ISP_TOK_TERM, 0x0000}
++};
++
++/*
++ * Sets the L1,L2 descriptor with section/supersection/Largepage/Smallpage
++ * base address or with L2 Page table address depending on the size parameter.
++ * Returns the written L1/L2 descriptor.
++ * pte_addr	: Pointer to the Indexed address in the L1 Page table ie TTB.
++ * phy_addr	: Section/Supersection/L2page table physical address.
++ * mapattr	: Mapping attributes applicable for Section/Supersections.
++ */
++static u32 ispmmu_set_pte(u32 *pte_addr, u32 phy_addr,
++						struct ispmmu_mapattr mapattr)
++{
++	u32 pte = 0;
++
++	switch (mapattr.map_size) {
++	case PAGE :
++		pte = ISPMMU_L1D_TYPE_PAGE << ISPMMU_L1D_TYPE_SHIFT;
++		pte |= (phy_addr >> ISPMMU_L1D_PAGE_ADDR_SHIFT)
++			<< ISPMMU_L1D_PAGE_ADDR_SHIFT;
++		break;
++	case SMALLPAGE:
++		pte = ISPMMU_L2D_TYPE_SMALL_PAGE <<
++			ISPMMU_L2D_TYPE_SHIFT;
++		pte &= ~ISPMMU_L2D_M_ACCESSBASED;
++		if (mapattr.endianism)
++			pte |= ISPMMU_L2D_E_BIGENDIAN ;
++		else
++			pte &= ~ISPMMU_L2D_E_BIGENDIAN ;
++		pte &= ISPMMU_L2D_ES_MASK;
++		pte |= mapattr.element_size << ISPMMU_L2D_ES_SHIFT;
++		pte |= (phy_addr >> ISPMMU_L2D_SMALL_ADDR_SHIFT)
++				<< ISPMMU_L2D_SMALL_ADDR_SHIFT;
++		break;
++	case L1DFAULT:
++		pte = ISPMMU_L1D_TYPE_FAULT << ISPMMU_L1D_TYPE_SHIFT;
++		break;
++	case L2DFAULT:
++		pte = ISPMMU_L2D_TYPE_FAULT << ISPMMU_L2D_TYPE_SHIFT;
++		break;
++	default:
++		break;
++	};
++
++	*pte_addr = pte;
++	return pte;
++}
++
++/*
++ * Returns the index in the ttb for a free 32MB region
++ * Returns 0 as an error code, if run out of regions.
++ */
++static u32 find_free_region_index(void)
++{
++	int idx = 0;
++	/* Find the first free 32M region in ttb. */
++	/* skip region 0 to avoid NULL pointer */
++	for (idx = ISPMMU_REGION_ENTRIES_NR; idx < ISPMMU_TTB_ENTRIES_NR;
++			idx += ISPMMU_REGION_ENTRIES_NR){
++		if (((*(ttb + idx)) & ISPMMU_L1D_TYPE_MASK) ==
++			(ISPMMU_L1D_TYPE_FAULT << ISPMMU_L1D_TYPE_SHIFT))
++			break;
++	}
++	if (idx == ISPMMU_TTB_ENTRIES_NR) {
++		DPRINTK_ISPMMU("run out of virtual space\n");
++		return 0;
++	}
++	return idx;
++}
++
++/*
++ * Returns the Page aligned address
++ * addr		:Address to be page aligned
++ */
++static inline u32 page_aligned_addr(u32 addr)
++{
++	u32 paddress;
++	paddress = addr & ~(PAGE_SIZE-1) ;
++	return paddress;
++}
++
++
++/*
++ * Returns the physical address of the allocated L2 page Table.
++ * l2_table	: Virtual address of the allocated l2 table.
++ */
++static inline u32 l2_page_paddr(u32 l2_table)
++{
++	return (l2_page_cache_p + (l2_table - l2_page_cache));
++}
++
++/*
++ * Allocates contigous memory for L2 page tables.
++ */
++static int init_l2_page_cache(void)
++{
++	int i;
++	u32 *l2p;
++
++	l2p_page = alloc_pages(GFP_KERNEL, get_order(L2P_TABLES_SIZE));
++	if (!l2p_page) {
++		DPRINTK_ISPMMU("ISP_ERR : No Memory for L2 page tables\n");
++		return -ENOMEM;
++	}
++	l2p = page_address(l2p_page);
++	l2_page_cache = (u32)l2p;
++	l2_page_cache_p = __pa(l2p);
++	l2_page_cache = (u32)ioremap_nocache(l2_page_cache_p, L2P_TABLES_SIZE);
++
++	for (i = 0; i < L2P_TABLE_NR; i++)
++		l2p_table_allotted[i] = 0;
++
++	DPRINTK_ISPMMU("Mem for L2 page tables at l2_paddr = %x, \
++			l2_vaddr = 0x%x, of bytes = 0x%x\n",
++		l2_page_cache_p, l2_page_cache, L2P_TABLES_SIZE);
++	/*HW Errata 1.40. Camera ISP: MMU endianess polarity inverted */
++///	if (is_sil_rev_less_than(OMAP3430_REV_ES2_0))
++///		l2_mapattr_obj.endianism = B_ENDIAN;
++///	else
++		l2_mapattr_obj.endianism = L_ENDIAN;
++	l2_mapattr_obj.element_size = ES_8BIT;
++	l2_mapattr_obj.mixed_size = ACCESS_BASED;
++	l2_mapattr_obj.map_size = L2DFAULT;
++	return 0;
++}
++
++/*
++ * Frees the memory of L2 page tables.
++ */
++static void cleanup_l2_page_cache(void)
++{
++	if (l2p_page) {
++		ioremap_cached(l2_page_cache_p, L2P_TABLES_SIZE);
++		__free_pages(l2p_page, get_order(L2P_TABLES_SIZE));
++	}
++}
++
++/*
++ * Finds the free L2 Page table slot.
++ * Fills the allotted L2 Page table with default entries.
++ * Returns the virtual address of the allotted L2 Pagetable,
++ */
++static u32 request_l2_page_table(void)
++{
++	int i, j;
++	u32 l2_table;
++
++	for (i = 0; i < L2P_TABLE_NR; i++) {
++		if (!l2p_table_allotted[i])
++			break;
++	}
++	if (i < L2P_TABLE_NR) {
++		l2p_table_allotted[i] = 1;
++		l2_table = l2_page_cache + (i * L2P_TABLE_SIZE);
++		l2_mapattr_obj.map_size = L2DFAULT;
++		/*Fill up all the entries with fault */
++		for (j = 0; j < ISPMMU_L2D_ENTRIES_NR; j++)
++			ispmmu_set_pte((u32 *)l2_table+j, 0, l2_mapattr_obj);
++		DPRINTK_ISPMMU("Allotted l2 page table at 0x%x\n",
++					(u32)l2_table);
++		return l2_table;
++	} else {
++		DPRINTK_ISPMMU("ISP_ERR : Cannot allocate more than 16 L2\
++				Page Tables");
++		return 0;
++	}
++}
++
++/*
++ * Frees the allotted L2 Page table slot.
++ */
++static int free_l2_page_table(u32 l2_table)
++{
++	int i;
++
++	DPRINTK_ISPMMU("Free l2 page table at 0x%x\n", l2_table);
++	for (i = 0; i < L2P_TABLE_NR; i++)
++		if (l2_table == (l2_page_cache + (i * L2P_TABLE_SIZE))) {
++			if (!l2p_table_allotted[i]) {
++				DPRINTK_ISPMMU("L2 page not in use\n");
++			}
++			l2p_table_allotted[i] = 0;
++			return 0;
++		}
++	DPRINTK_ISPMMU("L2 table not found\n");
++	return -EINVAL;
++}
++
++/*
++ * Map a physically contiguous buffer to ISP space. This call is used to
++ * map a frame buffer
++ * p_addr	: Physical address of the contigous mem to be mapped.
++ * size		: Size of the contigous mem to be mapped.
++ */
++dma_addr_t ispmmu_map(u32 p_addr, int size)
++{
++	int i, j, idx, num;
++	u32 sz, first_padding;
++	u32 p_addr_align, p_addr_align_end;
++	u32 pd;
++	u32 *l2_table;
++
++	DPRINTK_ISPMMU("map: p_addr = 0x%x, size = 0x%x\n", p_addr, size);
++
++	p_addr_align = page_aligned_addr(p_addr);
++
++	first_padding = p_addr - p_addr_align;
++
++	if (first_padding > size)
++		sz = 0;
++	else
++		sz = size - first_padding;
++
++	num = (sz/PAGE_SIZE) + ((sz%PAGE_SIZE)?1:0) + (first_padding ?1:0);
++	p_addr_align_end = p_addr_align + num*PAGE_SIZE;
++
++	DPRINTK_ISPMMU("buffer at 0x%x of size 0x%x spans to %d pages\n",
++			p_addr, size, num);
++
++	idx = find_free_region_index();
++	if (!idx) {
++		DPRINTK_ISPMMU("Runs out of virtual space");
++		return -EINVAL;
++	}
++	DPRINTK_ISPMMU("allocating region %d\n", idx/ISPMMU_REGION_ENTRIES_NR);
++
++	/* how many second-level page tables we need */
++	num = num/ISPMMU_L2D_ENTRIES_NR +
++			((num%ISPMMU_L2D_ENTRIES_NR)?1:0);
++	DPRINTK_ISPMMU("need %d second-level page tables (1KB each)\n", num);
++
++	/* create second-level page tables */
++	for (i = 0; i < num; i++) {
++		l2_table = (u32 *)request_l2_page_table();
++		if (!l2_table) {
++			DPRINTK_ISPMMU("no memory\n");
++			i--;
++			goto release_mem;
++		}
++
++		/* Make the first level page descriptor */
++		l1_mapattr_obj.map_size = PAGE;
++		pd = ispmmu_set_pte(ttb+idx+i, l2_page_paddr((u32)l2_table),
++			l1_mapattr_obj);
++		DPRINTK_ISPMMU("L1 pte[%d] = 0x%x\n", idx+i, pd);
++
++		/* Make the second Level page descriptors */
++		l2_mapattr_obj.map_size = SMALLPAGE;
++		for (j = 0; j < ISPMMU_L2D_ENTRIES_NR; j++) {
++			pd = ispmmu_set_pte(l2_table + j, p_addr_align,
++							l2_mapattr_obj);
++			/* DPRINTK_ISPMMU("L2 pte[%d] = 0x%x\n", j, pd); */
++			/*Contigous memory, just increment with Page size */
++			p_addr_align += PAGE_SIZE;
++			if (p_addr_align == p_addr_align_end)
++				break;
++		}
++		/* save it so we can free this l2 table later */
++		l2p_table_addr[idx + i] = (u32)l2_table;
++	}
++
++	DPRINTK_ISPMMU("mapped to ISP virtual address 0x%x\n",
++		(u32)((idx << 20) + (p_addr & (PAGE_SIZE - 1))));
++
++	omap_writel(1, ISPMMU_GFLUSH);
++	return (dma_addr_t)((idx<<20) + (p_addr & (PAGE_SIZE - 1)));
++
++release_mem:
++	for (; i >= 0; i--) {
++		free_l2_page_table(l2p_table_addr[idx + i]);
++		l2p_table_addr[idx + i] = 0;
++	}
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ispmmu_map);
++
++/*
++ * Map a physically discontiguous buffer to ISP space. This call is used to
++ * map a user buffer or a vmalloc buffer. The sg list is a set of pages.
++ * sg_list		: Address of the Scatter gather linked list.
++ * sglen		: Number of elements in the sg list.
++ */
++dma_addr_t ispmmu_map_sg(const struct scatterlist *sglist, int sglen)
++{
++	int i, j, idx, num, sg_num = 0;
++	u32 pd, sg_element_addr;
++	u32 *l2_table;
++
++	DPRINTK_ISPMMU("Map_sg: sglen (num of pages) = %d\n", sglen);
++
++	idx = find_free_region_index();
++	if (!idx) {
++		DPRINTK_ISPMMU("Runs out of virtual space");
++		return -EINVAL;
++	}
++
++	DPRINTK_ISPMMU("allocating region %d\n", idx/ISPMMU_REGION_ENTRIES_NR);
++
++	/* How many second-level page tables we need */
++	/*
++	* Size of each sglist element does not exceed a page size
++	* so consider the number of elements in the list for calcuating
++	* number of L2P tables
++	*/
++	num = sglen/ISPMMU_L2D_ENTRIES_NR +
++			((sglen%ISPMMU_L2D_ENTRIES_NR)?1:0);
++	DPRINTK_ISPMMU("Need %d second-level page tables (1KB each)\n", num);
++
++	/* create second-level page tables */
++	for (i = 0; i < num; i++) {
++		l2_table = (u32 *)request_l2_page_table();
++		if (!l2_table) {
++			DPRINTK_ISPMMU("No memory\n");
++			i--;
++			goto release_mem;
++		}
++		/* Make the first level page descriptor */
++		l1_mapattr_obj.map_size = PAGE;
++		pd = ispmmu_set_pte(ttb+idx+i, l2_page_paddr((u32)l2_table),
++			l1_mapattr_obj);
++		DPRINTK_ISPMMU("L1 pte[%d] = 0x%x\n", idx+i, pd);
++
++		/* Make the second Level page descriptors */
++		l2_mapattr_obj.map_size = SMALLPAGE;
++		for (j = 0; j < ISPMMU_L2D_ENTRIES_NR; j++) {
++			/*
++			 * Assuming that sglist elements are always page
++			 * aligned
++			 */
++			sg_element_addr = sg_dma_address(sglist + sg_num);
++			if ((sg_num > 0) && page_aligned_addr(sg_element_addr)
++							!= sg_element_addr)
++				DPRINTK_ISPMMU("ISP_ERR : Intermediate SG"
++						" elements are not"
++						" page aligned = 0x%x\n",
++						sg_element_addr);
++			pd = ispmmu_set_pte(l2_table + j, sg_element_addr,
++							l2_mapattr_obj);
++
++			/* DPRINTK_ISPMMU("L2 pte[%d] = 0x%x\n", j, pd); */
++
++			sg_num++;
++			if (sg_num == sglen)
++				break;
++		}
++		/* save it so we can free this l2 table later */
++		l2p_table_addr[idx + i] = (u32)l2_table;
++	}
++
++	DPRINTK_ISPMMU("mapped sg list to ISP virtual address 0x%x, idx=%d\n",
++		(u32)((idx << 20) + (sg_dma_address(sglist + 0) &
++						(PAGE_SIZE - 1))), idx);
++
++	omap_writel(1, ISPMMU_GFLUSH);
++	return (dma_addr_t)((idx << 20) + (sg_dma_address(sglist + 0) &
++							(PAGE_SIZE - 1)));
++
++release_mem:
++	for (; i >= 0; i--) {
++		free_l2_page_table(l2p_table_addr[idx + i]);
++		l2p_table_addr[idx + i] = 0;
++	}
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ispmmu_map_sg);
++
++/*
++ * Unmap a ISP space that is mapped before via ispmmu_map and
++ * ispmmu_map_sg.
++ * v_addr	: Virtural address to be unmapped
++ */
++int ispmmu_unmap(dma_addr_t v_addr)
++{
++	u32 v_addr_align;
++	int idx;
++
++	DPRINTK_ISPMMU("+ispmmu_unmap: 0x%x\n", v_addr);
++
++	v_addr_align = page_aligned_addr(v_addr);
++	idx = v_addr_align >> 20;
++	if ((idx < ISPMMU_REGION_ENTRIES_NR) ||
++		(idx > (ISPMMU_REGION_ENTRIES_NR * (ISPMMU_REGION_NR - 1)))
++		|| ((idx << 20) != v_addr_align)
++		|| (idx%ISPMMU_REGION_ENTRIES_NR)) {
++		DPRINTK_ISPMMU("Cannot unmap a non region-aligned space \
++				0x%x\n", v_addr);
++		return -EINVAL;
++	}
++
++	if (((*(ttb + idx)) & (ISPMMU_L1D_TYPE_MASK <<
++						ISPMMU_L1D_TYPE_SHIFT)) !=
++						(ISPMMU_L1D_TYPE_PAGE <<
++						ISPMMU_L1D_TYPE_SHIFT)) {
++		DPRINTK_ISPMMU("unmap a wrong region\n");
++		return -EINVAL;
++	}
++
++	/* free the associated level-2 page tables */
++	while (((*(ttb + idx)) & (ISPMMU_L1D_TYPE_MASK <<
++						ISPMMU_L1D_TYPE_SHIFT)) ==
++						(ISPMMU_L1D_TYPE_PAGE <<
++						ISPMMU_L1D_TYPE_SHIFT)) {
++		*(ttb + idx) = (ISPMMU_L1D_TYPE_FAULT <<
++						ISPMMU_L1D_TYPE_SHIFT);
++		free_l2_page_table(l2p_table_addr[idx]);
++		l2p_table_addr[idx++] = 0;
++		if (!(idx%ISPMMU_REGION_ENTRIES_NR)) {
++			DPRINTK_ISPMMU("Do not exceed this 32M region\n");
++			break;
++		}
++	}
++	omap_writel(1, ISPMMU_GFLUSH);
++
++	DPRINTK_ISPMMU("-ispmmu_unmap()\n");
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ispmmu_unmap);
++
++/*
++ * Callback from ISP driver for MMU interrupt
++ * status 	: IRQ status of ISPMMU
++ * arg1		: Not used as of now.
++ * arg2		: Not used as of now.
++ */
++static void ispmmu_isr(unsigned long status, isp_vbq_callback_ptr arg1,
++								void *arg2)
++{
++	u32 irqstatus;
++
++	irqstatus = omap_readl(ISPMMU_IRQSTATUS);
++	DPRINTK_ISPMMU("mmu error 0x%lx, 0x%x\n", status, irqstatus);
++
++	if (irqstatus & IRQENABLE_TLBMISS)
++		DPRINTK_ISPMMU("ISP_ERR: TLB Miss\n");
++	if (irqstatus & IRQENABLE_TRANSLNFAULT)
++		DPRINTK_ISPMMU("ISP_ERR: Invalid descriptor in the "
++			"translation table - Translation Fault\n");
++	if (irqstatus & IRQENABLE_EMUMISS)
++		DPRINTK_ISPMMU("ISP_ERR: TLB Miss during debug - "
++			"Emulation mode\n");
++	if (irqstatus & IRQENABLE_TWFAULT)
++		DPRINTK_ISPMMU("ISP_ERR: Table Walk Fault\n");
++	if (irqstatus & IRQENABLE_MULTIHITFAULT)
++		DPRINTK_ISPMMU("ISP_ERR: Multiple Matches in the TLB\n");
++
++	DPRINTK_ISPMMU("Fault address for the ISPMMU is 0x%x\n",
++			omap_readl(ISPMMU_FAULT_AD));
++	/*
++	* TODO: Indicate the camera driver about the fault and it should
++	* stop using the ISP
++	*/
++	omap_writel(irqstatus, ISPMMU_IRQSTATUS);
++}
++
++/*
++ * Reserves memory for L1 and L2 Page tables.
++ * Initializes the ISPMMU with TTB address, fault entries as default in the
++ * TTB table.
++ * Enables MMU and TWL.
++ * Sets the callback for the MMU error events.
++ */
++static int __init ispmmu_init(void)
++{
++	int i, val = 5;
++	struct isp_sysc isp_sysconfig;
++
++	isp_get();
++
++	/* reset */
++	omap_writel(0x2, ISPMMU_SYSCONFIG);
++	while (((omap_readl(ISPMMU_SYSSTATUS) & 0x1) != 0x1) && val--)
++		udelay(10);
++
++	if ((omap_readl(ISPMMU_SYSSTATUS) & 0x1) != 0x1) {
++		DPRINTK_ISPMMU("can't take ISP MMU out of reset\n");
++		isp_put();
++		return -ENODEV;
++	}
++
++	isp_sysconfig.reset = 0;
++	isp_sysconfig.idle_mode = 1;
++	isp_power_settings(isp_sysconfig);
++
++	ttb_page = alloc_pages(GFP_KERNEL,
++				get_order(ISPMMU_TTB_ENTRIES_NR * 4));
++	if (!ttb_page) {
++		DPRINTK_ISPMMU("No Memory for TTB\n");
++		isp_put();
++		return -ENOMEM;
++	}
++
++	ttb = page_address(ttb_page);
++	ttb_p = __pa(ttb);
++	ttb_aligned_size = ISPMMU_TTB_ENTRIES_NR * 4;
++	ttb = ioremap_nocache(ttb_p, ttb_aligned_size);
++	if ((ttb_p & 0xFFFFC000) != ttb_p) {
++		DPRINTK_ISPMMU("ISP_ERR : TTB address not aligned at 16KB\n");
++		__free_pages(ttb_page, get_order(ISPMMU_TTB_ENTRIES_NR * 4));
++		ttb_aligned_size = (ISPMMU_TTB_ENTRIES_NR * 4)
++				+ (ISPMMU_TTB_MISALIGN_SIZE);
++		ttb_page = alloc_pages(GFP_KERNEL,
++					get_order(ttb_aligned_size));
++		if (!ttb_page) {
++			DPRINTK_ISPMMU("No Memory for TTB\n");
++			isp_put();
++			return -ENOMEM;
++		}
++		ttb = page_address(ttb_page);
++		ttb_p = __pa(ttb);
++		ttb = ioremap_nocache(ttb_p, ttb_aligned_size);
++		if ((ttb_p & 0xFFFFC000) != ttb_p) {
++			/*
++			 * Move the unaligned address to the next 16KB
++			 * alignment
++			 */
++			ttb = (u32 *)(((u32)ttb & 0xFFFFC000) + 0x4000);
++			ttb_p = __pa(ttb);
++		}
++	}
++
++	DPRINTK_ISPMMU("TTB allocated at p = 0x%x, v = 0x%x, size = 0x%x\n",
++		ttb_p, (u32)ttb, ttb_aligned_size);
++	/*HW Errata 1.40. Camera ISP: MMU endianess polarity inverted */
++///	if (is_sil_rev_less_than(OMAP3430_REV_ES2_0))
++///		l1_mapattr_obj.endianism = B_ENDIAN;
++///	else
++		l1_mapattr_obj.endianism = L_ENDIAN;
++
++	l1_mapattr_obj.element_size = ES_8BIT;
++	l1_mapattr_obj.mixed_size = ACCESS_BASED;
++	l1_mapattr_obj.map_size = L1DFAULT;
++
++	val = init_l2_page_cache();
++	if (val) {
++		DPRINTK_ISPMMU("ISP_ERR : init l2 page cache\n");
++		ttb = page_address(ttb_page);
++		ttb_p = __pa(ttb);
++		ioremap_cached(ttb_p, ttb_aligned_size);
++		__free_pages(ttb_page, get_order(ttb_aligned_size));
++
++		isp_put();
++		return val;
++	}
++
++	/* Setting all the entries to generate fault by default */
++	for (i = 0; i < ISPMMU_TTB_ENTRIES_NR; i++)
++		ispmmu_set_pte(ttb + i, 0, l1_mapattr_obj);
++	/*
++	* TTB 31:7 is the address, since TTB is on 16KB boundary the last
++	* 14 bits are 0
++	*/
++	omap_writel(ttb_p, ISPMMU_TTB);
++
++	/* Enable MMU with table walking logic */
++	omap_writel((ISPMMU_MMUCNTL_MMU_EN|ISPMMU_MMUCNTL_TWL_EN),
++			ISPMMU_CNTL);
++	omap_writel(omap_readl(ISPMMU_IRQSTATUS), ISPMMU_IRQSTATUS);
++	omap_writel(0xf, ISPMMU_IRQENABLE);
++
++	isp_set_callback(CBK_MMU_ERR, ispmmu_isr, (void *)NULL, (void *)NULL);
++
++	val = omap_readl(ISPMMU_REVISION);
++	DPRINTK_ISPMMU("ISP MMU Rev %c.%c initialized\n",
++		(val>>ISPMMU_REVISION_REV_MAJOR_SHIFT)+'0',
++		(val & ISPMMU_REVISION_REV_MINOR_MASK)+'0');
++	/* Release the clocks now */
++	isp_put();
++	return 0;
++}
++
++/*
++ * Frees the L1 and L2 Page tables.
++ * Unsets the callback for MMU
++ */
++static void ispmmu_cleanup(void)
++{
++	/* free ttb */
++	ttb = page_address(ttb_page);
++	ttb_p = __pa(ttb);
++	ioremap_cached(ttb_p, ttb_aligned_size);
++	__free_pages(ttb_page, get_order(ttb_aligned_size));
++
++	isp_unset_callback(CBK_MMU_ERR);
++
++	cleanup_l2_page_cache();
++
++	return;
++}
++
++/*
++ * Saves the values of the mmu module registers.
++ */
++void ispmmu_save_context(void)
++{
++	DPRINTK_ISPMMU(" Saving context\n");
++	isp_save_context(ispmmu_reg_list);
++}
++EXPORT_SYMBOL_GPL(ispmmu_save_context);
++
++/*
++ * Restores the values of the mmu module registers.
++ */
++void ispmmu_restore_context(void)
++{
++	DPRINTK_ISPMMU(" Restoring context\n");
++	isp_restore_context(ispmmu_reg_list);
++}
++EXPORT_SYMBOL_GPL(ispmmu_restore_context);
++
++/*
++ * Prints the values of the ISPMMU registers
++ * Also prints other debug information stored
++ */
++void ispmmu_print_status(void)
++{
++#ifdef OMAP_ISPMMU_DEBUG
++	DPRINTK_ISPMMU("TTB v_addr = 0x%x, p_addr = 0x%x\n", (u32)ttb, ttb_p);
++	DPRINTK_ISPMMU("L2P base v_addr = 0x%x, p_addr = 0x%x\n"
++				, l2_page_cache, l2_page_cache_p);
++	DPRINTK_ISPMMU("ISPMMU_REVISION = 0x%x\n",
++						omap_readl(ISPMMU_REVISION));
++	DPRINTK_ISPMMU("ISPMMU_SYSCONFIG = 0x%x\n",
++						omap_readl(ISPMMU_SYSCONFIG));
++	DPRINTK_ISPMMU("ISPMMU_SYSSTATUS = 0x%x\n",
++						omap_readl(ISPMMU_SYSSTATUS));
++	DPRINTK_ISPMMU("ISPMMU_IRQSTATUS = 0x%x\n",
++						omap_readl(ISPMMU_IRQSTATUS));
++	DPRINTK_ISPMMU("ISPMMU_IRQENABLE = 0x%x\n",
++						omap_readl(ISPMMU_IRQENABLE));
++	DPRINTK_ISPMMU("ISPMMU_WALKING_ST = 0x%x\n",
++						omap_readl(ISPMMU_WALKING_ST));
++	DPRINTK_ISPMMU("ISPMMU_CNTL = 0x%x\n", omap_readl(ISPMMU_CNTL));
++	DPRINTK_ISPMMU("ISPMMU_FAULT_AD = 0x%x\n",
++						omap_readl(ISPMMU_FAULT_AD));
++	DPRINTK_ISPMMU("ISPMMU_TTB = 0x%x\n", omap_readl(ISPMMU_TTB));
++	DPRINTK_ISPMMU("ISPMMU_LOCK = 0x%x\n", omap_readl(ISPMMU_LOCK));
++	DPRINTK_ISPMMU("ISPMMU_LD_TLB= 0x%x\n", omap_readl(ISPMMU_LD_TLB));
++	DPRINTK_ISPMMU("ISPMMU_CAM = 0x%x\n", omap_readl(ISPMMU_CAM));
++	DPRINTK_ISPMMU("ISPMMU_RAM = 0x%x\n", omap_readl(ISPMMU_RAM));
++	DPRINTK_ISPMMU("ISPMMU_GFLUSH = 0x%x\n", omap_readl(ISPMMU_GFLUSH));
++	DPRINTK_ISPMMU("ISPMMU_FLUSH_ENTRY = 0x%x\n",
++					omap_readl(ISPMMU_FLUSH_ENTRY));
++	DPRINTK_ISPMMU("ISPMMU_READ_CAM = 0x%x\n",
++						omap_readl(ISPMMU_READ_CAM));
++	DPRINTK_ISPMMU("ISPMMU_READ_RAM = 0x%x\n",
++						omap_readl(ISPMMU_READ_RAM));
++#endif
++}
++EXPORT_SYMBOL_GPL(ispmmu_print_status);
++
++MODULE_AUTHOR("Texas Instruments.");
++MODULE_DESCRIPTION("OMAP3430 ISP MMU Driver");
++MODULE_LICENSE("GPL");
++
++module_init(ispmmu_init);
++module_exit(ispmmu_cleanup);
+Index: git/drivers/media/video/isp/ispmmu.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/ispmmu.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,57 @@
++/*
++ * drivers/media/video/isp/ispmmu.h
++ *
++ * OMAP3430 Camera ISP MMU API
++ *
++ * Copyright (C) 2008 Texas Instruments.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_MMU_H
++#define OMAP_ISP_MMU_H
++
++#ifdef CONFIG_ARCH_OMAP3410
++#include <asm/scatterlist.h>
++#endif
++
++dma_addr_t ispmmu_map(unsigned int p_addr, int size);
++
++/*
++* To be called from camera driver with scatter gather list
++*/
++dma_addr_t ispmmu_map_sg(const struct scatterlist *sglist, int sglen);
++int ispmmu_unmap(dma_addr_t isp_addr);
++
++void ispmmu_print_status(void);
++
++enum
++ISPMMU_MAP_ENDIAN{L_ENDIAN, B_ENDIAN};
++
++enum
++ISPMMU_MAP_ELEMENTSIZE{ES_8BIT, ES_16BIT, ES_32BIT, ES_NOENCONV};
++
++enum
++ISPMMU_MAP_MIXEDREGION{ACCESS_BASED, PAGE_BASED};
++
++enum
++ISPMMU_MAP_SIZE{L1DFAULT, PAGE, SECTION, SUPERSECTION, L2DFAULT,
++			LARGEPAGE, SMALLPAGE};
++
++/*
++ * Saves mmu context
++ */
++void ispmmu_save_context(void);
++
++/*
++ * Restores mmu context
++ */
++void ispmmu_restore_context(void);
++
++#endif /* OMAP_ISP_MMU_H */
+Index: git/drivers/media/video/isp/isppreview.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isppreview.c	2009-02-12 10:29:18.000000000 -0600
+@@ -0,0 +1,1894 @@
++/*
++ * drivers/media/video/isp/isppreview.c
++ *
++ * Driver Library for Preview module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/mutex.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <asm/io.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "isppreview.h"
++#include <asm/uaccess.h>
++
++static struct ispprev_nf prev_nf_t;
++static int RG_update, GG_update, BG_update, NF_enable, NF_update;
++
++/* Structure for saving/restoring preview module registers*/
++static struct isp_reg ispprev_reg_list[] = {
++	{ISPPRV_HORZ_INFO, 0x0000},
++	{ISPPRV_VERT_INFO, 0x0000},
++	{ISPPRV_RSDR_ADDR, 0x0000},
++	{ISPPRV_RADR_OFFSET, 0x0000},
++	{ISPPRV_DSDR_ADDR, 0x0000},
++	{ISPPRV_DRKF_OFFSET, 0x0000},
++	{ISPPRV_WSDR_ADDR, 0x0000},
++	{ISPPRV_WADD_OFFSET, 0x0000},
++	{ISPPRV_AVE, 0x0000},
++	{ISPPRV_HMED, 0x0000},
++	{ISPPRV_NF, 0x0000},
++	{ISPPRV_WB_DGAIN, 0x0000},
++	{ISPPRV_WBGAIN, 0x0000},
++	{ISPPRV_WBSEL, 0x0000},
++	{ISPPRV_CFA, 0x0000},
++	{ISPPRV_BLKADJOFF, 0x0000},
++	{ISPPRV_RGB_MAT1, 0x0000},
++	{ISPPRV_RGB_MAT2, 0x0000},
++	{ISPPRV_RGB_MAT3, 0x0000},
++	{ISPPRV_RGB_MAT4, 0x0000},
++	{ISPPRV_RGB_MAT5, 0x0000},
++	{ISPPRV_RGB_OFF1, 0x0000},
++	{ISPPRV_RGB_OFF2, 0x0000},
++	{ISPPRV_CSC0, 0x0000},
++	{ISPPRV_CSC1, 0x0000},
++	{ISPPRV_CSC2, 0x0000},
++	{ISPPRV_CSC_OFFSET, 0x0000},
++	{ISPPRV_CNT_BRT, 0x0000},
++	{ISPPRV_CSUP, 0x0000},
++	{ISPPRV_SETUP_YC, 0x0000},
++	{ISPPRV_SET_TBL_ADDR, 0x0000},
++	{ISPPRV_SET_TBL_DATA, 0x0000},
++	{ISPPRV_CDC_THR0, 0x0000},
++	{ISPPRV_CDC_THR1, 0x0000},
++	{ISPPRV_CDC_THR2, 0x0000},
++	{ISPPRV_CDC_THR3, 0x0000},
++	{ISP_TOK_TERM, 0x0000}
++};
++
++
++/* Default values in Office Flourescent Light for RGBtoRGB Blending */
++static struct ispprev_rgbtorgb flr_rgb2rgb = {
++	{	/* RGB-RGB Matrix */
++		{ 0x01E2, 0x0F30, 0x0FEE },
++		{ 0x0F9B, 0x01AC, 0x0FB9 },
++		{ 0x0FE0, 0x0EC0, 0x0260 }
++	},	/* RGB Offset */
++		{0x0000, 0x0000, 0x0000}
++};
++
++/* Default values in Office Flourescent Light for RGB to YUV Conversion*/
++static struct ispprev_csc flr_prev_csc[] = {
++	{
++		{	/* CSC Coef Matrix */
++			{ 66, 129, 25},
++			{ -38, -75, 112},
++			{ 112, -94 , -18}
++		},	/* CSC Offset */
++			{0x0, 0x0, 0x0}
++	},
++	{
++		{	/* CSC Coef Matrix Sepia*/
++			{ 19, 38, 7},
++			{ 0, 0, 0},
++			{ 0, 0, 0}
++		},	/* CSC Offset */
++			{0x0, 0xE7, 0x14}
++	},
++	{
++		{	/* CSC Coef Matrix BW*/
++			{ 66, 129, 25},
++			{ 0, 0, 0},
++			{ 0, 0, 0}
++		},	/* CSC Offset */
++			{0x0, 0x0, 0x0}
++	}
++};
++
++
++/* Default values in Office Flourescent Light for CFA Gradient*/
++static u8 flr_cfa_gradthrs_horz = 0x28;
++static u8 flr_cfa_gradthrs_vert = 0x28;
++
++/* Default values in Office Flourescent Light for Chroma Suppression*/
++static u8 flr_csup_gain = 0x0D;
++static u8 flr_csup_thres = 0xEB;
++
++/* Default values in Office Flourescent Light for Noise Filter*/
++static u8 flr_nf_strgth = 0x03;
++
++/* Default values in Office Flourescent Light for White Balance*/
++static u16 flr_wbal_dgain = 0x100;
++static u8 flr_wbal_coef0 = 0x68;
++static u8 flr_wbal_coef1 = 0x5c;
++static u8 flr_wbal_coef2 = 0x5c;
++static u8 flr_wbal_coef3 = 0x94;
++
++/* Default values in Office Flourescent Light for Black Adjustment*/
++static u8 flr_blkadj_blue = 0x0;
++static u8 flr_blkadj_green = 0x0;
++static u8 flr_blkadj_red = 0x0;
++
++static int update_color_matrix;
++
++/*
++ * Structure for the preview module to store its own information.
++ */
++static struct isp_prev {
++	u8 prev_inuse;
++	u32 prevout_w;
++	u32 prevout_h;
++	u32 previn_w;
++	u32 previn_h;
++	enum preview_input prev_inpfmt;
++	enum preview_output prev_outfmt;
++	u8 hmed_en;
++	u8 nf_en;
++	u8 dcor_en;
++	u8 cfa_en;
++	u8 csup_en;
++	u8 yenh_en;
++	u8 fmtavg;
++	u8 brightness;
++	u8 contrast;
++	enum preview_color_effect color;
++	enum cfa_fmt cfafmt;
++	struct mutex ispprev_mutex;
++} ispprev_obj;
++
++/* Saved parameters */
++struct prev_params *prev_config_params;
++
++/*
++ * Coeficient Tables for the submodules in Preview.
++ * Array is initialised with the values from.the tables text file.
++ */
++
++/*
++ * CFA Filter Coefficient Table
++ *
++ */
++static u32 cfa_coef_table[] = {
++#include "cfa_coef_table.h"
++};
++
++/*
++ * Gamma Correction Table - Red
++ */
++static u32 redgamma_table[] = {
++#include "redgamma_table.h"
++};
++
++/*
++ * Gamma Correction Table - Green
++ */
++static u32 greengamma_table[] = {
++#include "greengamma_table.h"
++};
++
++/*
++ * Gamma Correction Table - Blue
++ */
++static u32 bluegamma_table[] = {
++#include "bluegamma_table.h"
++};
++
++/*
++ * Noise Filter Threshold table
++ */
++static u32 noise_filter_table[] = {
++#include "noise_filter_table.h"
++};
++
++/*
++ * Luminance Enhancement Table
++ */
++static u32 luma_enhance_table[] = {
++#include "luma_enhance_table.h"
++};
++
++int omap34xx_isp_preview_config(void *userspace_add)
++{
++	struct prev_params *params = prev_config_params;
++	struct ispprev_hmed prev_hmed_t;
++	struct ispprev_cfa prev_cfa_t;
++	struct ispprev_csup csup_t;
++	struct ispprev_wbal prev_wbal_t;
++	struct ispprev_blkadj prev_blkadj_t;
++	struct ispprev_rgbtorgb rgb2rgb_t;
++	struct ispprev_csc prev_csc_t;
++	struct ispprev_yclimit yclimit_t;
++	struct ispprev_dcor prev_dcor_t;
++	struct ispprv_update_config preview_struct;
++	int yen_t[128];
++
++	if (userspace_add == NULL)
++		return -EINVAL ;
++	if (copy_from_user(&preview_struct,
++				(struct ispprv_update_config *)userspace_add,
++				sizeof(struct ispprv_update_config))) {
++		goto err_copy_from_user;
++	}
++	if ((ISP_ABS_PREV_LUMAENH & preview_struct.flag) ==
++							ISP_ABS_PREV_LUMAENH) {
++	if ((ISP_ABS_PREV_LUMAENH & preview_struct.update) ==
++							ISP_ABS_PREV_LUMAENH) {
++		if (copy_from_user(yen_t, (preview_struct.yen),
++							sizeof(yen_t)))
++			goto err_copy_from_user;
++
++		isppreview_config_luma_enhancement(yen_t);
++			params->features |= (PREV_LUMA_ENHANCE);
++		} else
++			params->features |= (PREV_LUMA_ENHANCE);
++	} else {
++		if ((ISP_ABS_PREV_LUMAENH & preview_struct.update) ==
++							ISP_ABS_PREV_LUMAENH)
++			params->features &= ~(PREV_LUMA_ENHANCE);
++	}
++
++	if ((ISP_ABS_PREV_INVALAW & preview_struct.flag)
++						== ISP_ABS_PREV_INVALAW) {
++		isppreview_enable_invalaw(1);
++		params->features |= (PREV_INVERSE_ALAW);
++	} else {
++		isppreview_enable_invalaw(0);
++		params->features &= ~(PREV_INVERSE_ALAW);
++	}
++
++	if ((ISP_ABS_PREV_HRZ_MED & preview_struct.flag) ==
++						ISP_ABS_PREV_HRZ_MED) {
++		if ((ISP_ABS_PREV_HRZ_MED & preview_struct.update)
++						== ISP_ABS_PREV_HRZ_MED) {
++			if (copy_from_user(&prev_hmed_t,
++						(struct ispprev_hmed *)
++						(preview_struct.prev_hmed),
++						sizeof(struct ispprev_hmed)))
++				goto err_copy_from_user;
++				isppreview_config_hmed(prev_hmed_t);
++				isppreview_enable_hmed(1);
++				params->features |= (PREV_HORZ_MEDIAN_FILTER);
++			} else {
++				isppreview_enable_hmed(1);
++				params->features |= (PREV_HORZ_MEDIAN_FILTER);
++			}
++		} else {
++			if ((ISP_ABS_PREV_HRZ_MED & preview_struct.update) ==
++							ISP_ABS_PREV_HRZ_MED) {
++				isppreview_enable_hmed(0);
++				params->features &= ~(PREV_HORZ_MEDIAN_FILTER);
++			}
++		}
++
++	if ((ISP_ABS_PREV_CFA & preview_struct.flag) ==
++						ISP_ABS_PREV_CFA) {
++		if ((ISP_ABS_PREV_CFA & preview_struct.update) ==
++						ISP_ABS_PREV_CFA) {
++			if (copy_from_user(&prev_cfa_t,
++					(struct ispprev_cfa *)preview_struct.
++					prev_cfa, sizeof(struct ispprev_cfa)))
++				goto err_copy_from_user;
++
++			isppreview_config_cfa(prev_cfa_t);
++			isppreview_enable_cfa(1);
++			params->features |= (PREV_CFA);
++
++		} else {
++			isppreview_enable_cfa(1);
++			params->features |= (PREV_CFA);
++		}
++	} else {
++		if ((ISP_ABS_PREV_CFA & preview_struct.update) ==
++							ISP_ABS_PREV_CFA) {
++			isppreview_enable_cfa(0);
++			params->features &= ~(PREV_CFA);
++		}
++	}
++
++	if ((ISP_ABS_PREV_CHROMA_SUPP & preview_struct.flag) ==
++						ISP_ABS_PREV_CHROMA_SUPP) {
++		if ((ISP_ABS_PREV_CHROMA_SUPP &
++						preview_struct.update) ==
++						ISP_ABS_PREV_CHROMA_SUPP) {
++			if (copy_from_user(&csup_t,
++						(struct ispprev_csup *)
++						(preview_struct.csup),
++						sizeof(struct ispprev_csup)))
++				goto err_copy_from_user;
++
++			isppreview_config_chroma_suppression(csup_t);
++			isppreview_enable_chroma_suppression(1);
++			params->features |= (PREV_CHROMA_SUPPRESS);
++
++		} else {
++			isppreview_enable_chroma_suppression(1);
++			params->features |= (PREV_CHROMA_SUPPRESS);
++			}
++	} else {
++		if ((ISP_ABS_PREV_CHROMA_SUPP &
++						preview_struct.update) ==
++						ISP_ABS_PREV_CHROMA_SUPP) {
++			isppreview_enable_chroma_suppression(0);
++			params->features &= ~(PREV_CHROMA_SUPPRESS);
++		}
++	}
++
++	if ((ISP_ABS_PREV_WB & preview_struct.update) == ISP_ABS_PREV_WB) {
++		if (copy_from_user(&prev_wbal_t,
++				(struct ispprev_wbal *)(preview_struct.
++				prev_wbal), sizeof(struct ispprev_wbal)))
++			goto err_copy_from_user;
++
++		isppreview_config_whitebalance(prev_wbal_t);
++	}
++
++	if ((ISP_ABS_PREV_BLKADJ & preview_struct.update)
++						== ISP_ABS_PREV_BLKADJ) {
++		if (copy_from_user(&prev_blkadj_t,
++				(struct ispprev_blkadjl *)(preview_struct.
++				prev_blkadj), sizeof(struct ispprev_blkadj))) {
++			goto err_copy_from_user;
++		}
++		isppreview_config_blkadj(prev_blkadj_t);
++	}
++
++	if ((ISP_ABS_PREV_RGB2RGB & preview_struct.update)
++						== ISP_ABS_PREV_RGB2RGB) {
++		if (copy_from_user(&rgb2rgb_t,
++				(struct ispprev_rgbtorgb *)(preview_struct.
++				rgb2rgb), sizeof(struct ispprev_rgbtorgb)))
++			goto err_copy_from_user;
++
++		isppreview_config_rgb_blending(rgb2rgb_t);
++	}
++
++	if ((ISP_ABS_PREV_COLOR_CONV & preview_struct.update)
++						== ISP_ABS_PREV_COLOR_CONV) {
++		if (copy_from_user(&prev_csc_t,
++				(struct ispprev_csc *)(preview_struct.
++				prev_csc), sizeof(struct ispprev_csc)))
++			goto err_copy_from_user;
++
++		isppreview_config_rgb_to_ycbcr(prev_csc_t);
++	}
++
++	if ((ISP_ABS_PREV_YC_LIMIT & preview_struct.update)
++						== ISP_ABS_PREV_YC_LIMIT) {
++		if (copy_from_user(&yclimit_t,
++				(struct ispprev_yclimit *)(preview_struct.
++				yclimit), sizeof(struct ispprev_yclimit)))
++			goto err_copy_from_user;
++
++		isppreview_config_yc_range(yclimit_t);
++	}
++
++	if ((ISP_ABS_PREV_DEFECT_COR & preview_struct.flag) ==
++						ISP_ABS_PREV_DEFECT_COR) {
++		if ((ISP_ABS_PREV_DEFECT_COR & preview_struct.update) ==
++						ISP_ABS_PREV_DEFECT_COR) {
++			if (copy_from_user(&prev_dcor_t,
++						(struct ispprev_dcor *)
++						(preview_struct.prev_dcor),
++						sizeof(struct ispprev_dcor)))
++				goto err_copy_from_user;
++
++				isppreview_config_dcor(prev_dcor_t);
++				isppreview_enable_dcor(1);
++				params->features |= (PREV_DEFECT_COR);
++			} else {
++				isppreview_enable_dcor(1);
++				params->features |= (PREV_DEFECT_COR);
++			}
++		} else {
++			if ((ISP_ABS_PREV_DEFECT_COR & preview_struct.update) ==
++						ISP_ABS_PREV_DEFECT_COR) {
++				isppreview_enable_dcor(0);
++				params->features &= ~(PREV_DEFECT_COR);
++				}
++		}
++
++	if ((ISP_ABS_PREV_GAMMABYPASS & preview_struct.flag) ==
++						ISP_ABS_PREV_GAMMABYPASS) {
++		isppreview_enable_gammabypass(1);
++		params->features |= (PREV_GAMMA_BYPASS);
++	} else {
++		isppreview_enable_gammabypass(0);
++		params->features &= ~(PREV_GAMMA_BYPASS);
++	}
++
++	return 0;
++
++err_copy_from_user:
++	printk(KERN_ERR);
++	DPRINTK_ISPPREV("ISP_ERR : Preview Copy From User Error \n");
++	return -EINVAL ;
++}
++EXPORT_SYMBOL(omap34xx_isp_preview_config);
++
++int omap34xx_isp_tables_update(void *userspace_add)
++{
++	struct isptables_update isptables_struct;
++	struct prev_params *params = prev_config_params;
++
++	if (userspace_add == NULL)
++		return -EINVAL;
++
++	if (copy_from_user(&isptables_struct,
++				(struct isptables_update *)(userspace_add),
++				sizeof(struct isptables_update)))
++		goto err_copy_from_user;
++
++	if ((ISP_ABS_TBL_NF & isptables_struct.flag) == ISP_ABS_TBL_NF) {
++		NF_enable = 1;
++		params->features |= (PREV_NOISE_FILTER);
++	} else {
++		NF_enable = 0;
++		params->features &= ~(PREV_NOISE_FILTER);
++	}
++
++	if ((ISP_ABS_TBL_NF & isptables_struct.update) == ISP_ABS_TBL_NF) {
++		if (copy_from_user(&prev_nf_t, (void *)isptables_struct.prev_nf,
++						sizeof(struct ispprev_nf)))
++			goto err_copy_from_user;
++
++		if (copy_from_user(noise_filter_table, prev_nf_t.table,
++						sizeof(noise_filter_table))) {
++			NF_update = 0;
++			goto err_copy_from_user;
++		}
++		prev_nf_t.table = noise_filter_table;
++		NF_update = 1;
++	}
++
++	if ((ISP_ABS_TBL_REDGAMMA & isptables_struct.update) ==
++						ISP_ABS_TBL_REDGAMMA) {
++		if (copy_from_user(redgamma_table,
++				(isptables_struct.red_gamma),
++				sizeof(redgamma_table))) {
++			RG_update = 0;
++			goto err_copy_from_user;
++		}
++		RG_update = 1;
++	}
++
++	if ((ISP_ABS_TBL_GREENGAMMA & isptables_struct.update) ==
++						ISP_ABS_TBL_GREENGAMMA) {
++		if (copy_from_user(greengamma_table,
++					(isptables_struct.green_gamma),
++					sizeof(greengamma_table)))  {
++			GG_update = 0;
++			goto err_copy_from_user;
++		}
++		GG_update = 1;
++	}
++
++	if ((ISP_ABS_TBL_BLUEGAMMA & isptables_struct.update) ==
++						ISP_ABS_TBL_BLUEGAMMA) {
++		if (copy_from_user(bluegamma_table,
++					(isptables_struct.blue_gamma),
++					sizeof(bluegamma_table))) {
++			BG_update = 0;
++			goto err_copy_from_user;
++		}
++		BG_update = 1;
++	}
++
++	return 0;
++
++err_copy_from_user:
++	printk(KERN_ERR "Preview Tables:Copy From User Error");
++	return -EINVAL;
++}
++EXPORT_SYMBOL(omap34xx_isp_tables_update);
++
++/*
++ * Allows user to program shadow registers associated with preview module.
++ */
++void
++isppreview_config_shadow_registers()
++{
++	struct prev_params *params = prev_config_params;
++	u8 current_brightness_contrast;
++	int ctr, prv_disabled;
++
++	/* Program Brightness if needed */
++	isppreview_query_brightness(&current_brightness_contrast);
++	if (current_brightness_contrast != ((ispprev_obj.brightness) *
++							ISPPRV_BRIGHT_UNITS)) {
++		DPRINTK_ISPPREV(" Changing Brightness level to %d\n",
++						ispprev_obj.brightness);
++		isppreview_config_brightness((ispprev_obj.brightness) *
++							ISPPRV_BRIGHT_UNITS);
++	}
++
++	/* Program Contrast if needed */
++	isppreview_query_contrast(&current_brightness_contrast);
++	if (current_brightness_contrast != ((ispprev_obj.contrast) *
++						ISPPRV_CONTRAST_UNITS)) {
++		DPRINTK_ISPPREV(" Changing Contrast level to %d\n",
++							ispprev_obj.contrast);
++		isppreview_config_contrast((ispprev_obj.contrast) *
++							ISPPRV_CONTRAST_UNITS);
++	}
++
++	if (update_color_matrix) {
++		isppreview_config_rgb_to_ycbcr(
++			flr_prev_csc[ispprev_obj.color]);
++		update_color_matrix = 0;
++	}
++
++	if (GG_update || RG_update || BG_update || NF_update) {
++		isppreview_enable(0);
++		prv_disabled = 1;
++	}
++
++	if (GG_update) {
++		omap_writel(0x400, ISPPRV_SET_TBL_ADDR);
++
++		for (ctr = 0; ctr < ISP_GAMMA_TABLE_SIZE; ctr++)
++			omap_writel(greengamma_table[ctr],
++							ISPPRV_SET_TBL_DATA);
++
++		GG_update = 0;
++	}
++
++	if (RG_update) {
++		omap_writel(0, ISPPRV_SET_TBL_ADDR);
++
++		for (ctr = 0; ctr < ISP_GAMMA_TABLE_SIZE; ctr++)
++			omap_writel(redgamma_table[ctr], ISPPRV_SET_TBL_DATA);
++
++		RG_update = 0;
++	}
++
++	if (BG_update) {
++		omap_writel(0x800, ISPPRV_SET_TBL_ADDR);
++
++		for (ctr = 0; ctr < ISP_GAMMA_TABLE_SIZE; ctr++)
++			omap_writel(bluegamma_table[ctr], ISPPRV_SET_TBL_DATA);
++
++		BG_update = 0;
++	}
++
++	if (NF_update) {
++		isppreview_config_noisefilter(prev_nf_t);
++
++		if (NF_enable) {
++			isppreview_enable_noisefilter(1);
++			params->features |= ~(PREV_NOISE_FILTER);
++		} else {
++			isppreview_enable_noisefilter(0);
++			params->features &= ~(PREV_NOISE_FILTER);
++		}
++
++		NF_update = 0;
++	}
++
++	if (prv_disabled) {
++		isppreview_enable(1);
++		prv_disabled = 0;
++	}
++}
++EXPORT_SYMBOL(isppreview_config_shadow_registers);
++
++/**
++ * isppreview_request - Reserves the preview module.
++ *
++ * Returns 0 if successful, or -EBUSY if the module was already reserved.
++ **/
++int isppreview_request()
++{
++	mutex_lock(&ispprev_obj.ispprev_mutex);
++	if (!(ispprev_obj.prev_inuse)) {
++		ispprev_obj.prev_inuse = 1;
++		mutex_unlock(&ispprev_obj.ispprev_mutex);
++		/* Turn on Preview module Clocks. */
++		omap_writel((omap_readl(ISP_CTRL)) | ISPCTRL_PREV_RAM_EN |
++			ISPCTRL_PREV_CLK_EN | ISPCTRL_SBL_WR1_RAM_EN
++			, ISP_CTRL);
++		return 0;
++	} else{
++		mutex_unlock(&ispprev_obj.ispprev_mutex);
++		printk(KERN_ERR "ISP_ERR : Preview Module Busy\n");
++		return -EBUSY;
++	}
++}
++EXPORT_SYMBOL(isppreview_request);
++
++/*
++ * Marks Preview module free.
++ */
++int
++isppreview_free()
++{
++	mutex_lock(&ispprev_obj.ispprev_mutex);
++	if (ispprev_obj.prev_inuse) {
++		ispprev_obj.prev_inuse = 0;
++		mutex_unlock(&ispprev_obj.ispprev_mutex);
++		omap_writel(omap_readl(ISP_CTRL) & ~(ISPCTRL_PREV_CLK_EN |
++				ISPCTRL_PREV_RAM_EN
++				| ISPCTRL_SBL_WR1_RAM_EN), ISP_CTRL);
++		return 0;
++	} else {
++		mutex_unlock(&ispprev_obj.ispprev_mutex);
++		DPRINTK_ISPPREV("ISP_ERR : Preview Module already freed\n");
++		return -EINVAL;
++	}
++
++}
++EXPORT_SYMBOL(isppreview_free);
++
++/* Sets up the default preview configuration according to the arguments.
++ * input: Indicates the module that gives the image to preview
++ * output: Indicates the module to which the preview outputs to.
++ */
++int
++isppreview_config_datapath(enum preview_input input,
++					enum preview_output output)
++{
++	u32 pcr = 0;
++	u8 enable = 0;
++	struct prev_params *params = prev_config_params;
++	struct ispprev_yclimit yclimit;
++
++	pcr = omap_readl(ISPPRV_PCR);
++
++	switch (input) {
++	case PRV_RAW_CCDC:
++		pcr &= ~(ISPPRV_PCR_SOURCE);
++		pcr &= ~(ISPPRV_PCR_ONESHOT);
++		ispprev_obj.prev_inpfmt = PRV_RAW_CCDC;
++		break;
++	case PRV_RAW_MEM:
++		pcr |= ISPPRV_PCR_SOURCE;
++		pcr |= ISPPRV_PCR_ONESHOT;
++		ispprev_obj.prev_inpfmt = PRV_RAW_MEM;
++		break;
++	case PRV_CCDC_DRKF:
++		pcr |= ISPPRV_PCR_DRKFCAP;
++		pcr |= ISPPRV_PCR_ONESHOT;
++		ispprev_obj.prev_inpfmt = PRV_CCDC_DRKF;
++		break;
++	/* Just check for input path validity. No PCR update required
++	* for the current HW setup.
++	*/
++	case PRV_COMPCFA:
++		ispprev_obj.prev_inpfmt = PRV_COMPCFA;
++		break;
++	case PRV_OTHERS:
++		ispprev_obj.prev_inpfmt = PRV_OTHERS;
++		break;
++	case PRV_RGBBAYERCFA:
++		ispprev_obj.prev_inpfmt = PRV_RGBBAYERCFA;
++		break;
++	default:
++		printk(KERN_ERR "ISP_ERR : Wrong Input\n");
++		return -EINVAL;
++	};
++
++	if (output == PREVIEW_RSZ) {
++		pcr |= ISPPRV_PCR_RSZPORT;
++		pcr &= (~ISPPRV_PCR_SDRPORT);
++		ispprev_obj.prev_outfmt = PREVIEW_RSZ;
++	} else if (output == PREVIEW_MEM) {
++		pcr &= (~ISPPRV_PCR_RSZPORT);
++		pcr |= ISPPRV_PCR_SDRPORT;
++		ispprev_obj.prev_outfmt = PREVIEW_MEM;
++	} else {
++		printk(KERN_ERR "ISP_ERR : Wrong Output\n");
++		return -EINVAL;
++	}
++	omap_writel(pcr, ISPPRV_PCR);
++
++	/* Default Output format configured is YCrYCb (UYVY) */
++	isppreview_config_ycpos(params->pix_fmt);
++
++	/* CFA */
++	if (params->cfa.cfa_table != NULL)
++		isppreview_config_cfa(params->cfa);
++	/* Chroma Suppression */
++	if (params->csup.hypf_en == 1)
++		isppreview_config_chroma_suppression(params->csup);
++	/* Luma */
++	if (params->ytable != NULL)
++		isppreview_config_luma_enhancement(params->ytable);
++	/* Noise Filter */
++	/* Gamma Correction */
++	if (params->gtable.redtable != NULL)
++		isppreview_config_gammacorrn(params->gtable);
++
++	/* Enabling specific features */
++	enable = ((params->features & PREV_CFA) == PREV_CFA) ? 1 : 0;
++	isppreview_enable_cfa(enable);
++
++	enable = ((params->features & PREV_CHROMA_SUPPRESS)
++			== PREV_CHROMA_SUPPRESS) ? 1 : 0;
++	isppreview_enable_chroma_suppression(enable);
++
++	enable = ((params->features & PREV_LUMA_ENHANCE)
++			== PREV_LUMA_ENHANCE) ? 1 : 0;
++	isppreview_enable_luma_enhancement(enable);
++
++	enable = ((params->features & PREV_NOISE_FILTER)
++			== PREV_NOISE_FILTER) ? 1 : 0;
++	if (enable)
++		isppreview_config_noisefilter(params->nf);
++	isppreview_enable_noisefilter(enable);
++
++	enable = ((params->features & PREV_DEFECT_COR)
++			== PREV_DEFECT_COR) ? 1 : 0;
++	if (enable)
++		isppreview_config_dcor(params->dcor);
++	isppreview_enable_dcor(enable);
++
++	enable = ((params->features & PREV_GAMMA_BYPASS)
++			== PREV_GAMMA_BYPASS) ? 1 : 0;
++	isppreview_enable_gammabypass(enable);
++
++	isppreview_config_whitebalance(params->wbal);
++	isppreview_config_blkadj(params->blk_adj);
++	isppreview_config_rgb_blending(params->rgb2rgb);
++	isppreview_config_rgb_to_ycbcr(params->rgb2ycbcr);
++
++	isppreview_config_contrast(params->contrast * ISPPRV_CONTRAST_UNITS);
++	isppreview_config_brightness(params->brightness * ISPPRV_BRIGHT_UNITS);
++
++	yclimit.minC = ISPPRV_YC_MIN;
++	yclimit.maxC = ISPPRV_YC_MAX;
++	yclimit.minY = ISPPRV_YC_MIN;
++	yclimit.maxY = ISPPRV_YC_MAX;
++	isppreview_config_yc_range(yclimit);
++
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_config_datapath);
++
++/*
++ * Configure byte layout of YUV image
++ */
++void isppreview_config_ycpos(enum preview_ycpos_mode mode)
++{
++	u32 pcr = omap_readl(ISPPRV_PCR);
++	pcr &= (~ISPPRV_PCR_YCPOS_CrYCbY);
++	pcr |= (mode << ISPPRV_PCR_YCPOS_SHIFT);
++	omap_writel(pcr, ISPPRV_PCR);
++}
++EXPORT_SYMBOL(isppreview_config_ycpos);
++
++/*
++ * Enable/disable/configure averager
++ */
++void
++isppreview_config_averager(u8 average)
++{
++	int reg = 0;
++
++	reg = AVE_ODD_PIXEL_DIST | AVE_EVEN_PIXEL_DIST | average;
++	omap_writel(reg, ISPPRV_AVE);
++}
++EXPORT_SYMBOL(isppreview_config_averager);
++
++/*
++ * Enable/Disable the Inverse A-Law module in Preview
++ * enable: 1- Reverse the ALaw done in CCDC.
++ */
++void isppreview_enable_invalaw(u8 enable)
++{
++	u32 pcr_val = 0;
++	pcr_val = omap_readl(ISPPRV_PCR);
++
++	if (enable)
++		omap_writel(pcr_val | ISPPRV_PCR_WIDTH | ISPPRV_PCR_INVALAW,
++			ISPPRV_PCR);
++	else
++		omap_writel(pcr_val & ~(ISPPRV_PCR_WIDTH | ISPPRV_PCR_INVALAW),
++			ISPPRV_PCR);
++}
++EXPORT_SYMBOL(isppreview_enable_invalaw);
++
++/* Enable/Disable of the darkframe subtract for each captured frame.
++ * enable: 1- Acquires memory bandwidth since the pixels in each frame is
++ * subtracted with the pixels in the current frame.
++ */
++void
++isppreview_enable_drkframe(u8 enable)
++{
++	if (enable)
++		omap_writel(omap_readl(ISPPRV_PCR) | ISPPRV_PCR_DRKFEN,
++					ISPPRV_PCR);
++	else
++		omap_writel((omap_readl(ISPPRV_PCR)) & ~ISPPRV_PCR_DRKFEN,
++					ISPPRV_PCR);
++}
++EXPORT_SYMBOL(isppreview_enable_drkframe);
++
++/* If dark frame subtract not to be used, then enable this shading compensation
++ * enable: 1- Enables the shading compensation.
++ */
++void
++isppreview_enable_shadcomp(u8 enable)
++{
++
++	if (enable) {
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_SCOMP_EN,
++				ISPPRV_PCR);
++		isppreview_enable_drkframe(1);
++	} else
++		omap_writel((omap_readl(ISPPRV_PCR)) & ~ISPPRV_PCR_SCOMP_EN,
++				ISPPRV_PCR);
++}
++EXPORT_SYMBOL(isppreview_enable_shadcomp);
++
++/* Configure the shift value to be used in shading compensation.
++ * scomp_shtval: 3bit value of shift used in shading compensation.
++ */
++void isppreview_config_drkf_shadcomp(u8 scomp_shtval)
++{
++	u32 pcr_val = omap_readl(ISPPRV_PCR);
++
++	pcr_val &= ISPPRV_PCR_SCOMP_SFT_MASK;
++	omap_writel(pcr_val | (scomp_shtval << ISPPRV_PCR_SCOMP_SFT_SHIFT),
++				ISPPRV_PCR);
++}
++EXPORT_SYMBOL(isppreview_config_drkf_shadcomp);
++
++/*
++ * Enable/Disable of the Horizontal Median Filter
++ * enable: 1- Enables Horizontal Median Filter
++ */
++void isppreview_enable_hmed(u8 enable)
++{
++	if (enable) {
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_HMEDEN,
++			ISPPRV_PCR);
++		ispprev_obj.hmed_en = 1;
++	} else {
++		omap_writel((omap_readl(ISPPRV_PCR)) & (~ISPPRV_PCR_HMEDEN),
++			ISPPRV_PCR);
++		ispprev_obj.hmed_en = 0;
++	}
++}
++EXPORT_SYMBOL(isppreview_enable_hmed);
++
++/*
++ *Configures the Horizontal Median Filter
++ * prev_hmed: Structure containing the odd and even distance between the
++ * 		pixels in the image along with the filter threshold.
++ */
++void isppreview_config_hmed(struct ispprev_hmed prev_hmed)
++{
++
++	u32 odddist = 0;
++	u32 evendist = 0;
++
++	if (prev_hmed.odddist == 1)
++		odddist = ~ISPPRV_HMED_ODDDIST;
++	else /* else the odd distance is 2 */
++		odddist = ISPPRV_HMED_ODDDIST;
++
++	if (prev_hmed.evendist == 1)
++		evendist = ~ISPPRV_HMED_EVENDIST;
++	else /* else the even distance is 2 */
++		evendist = ISPPRV_HMED_EVENDIST;
++
++	omap_writel(odddist | evendist
++			| (prev_hmed.thres<<ISPPRV_HMED_THRESHOLD_SHIFT),
++			ISPPRV_HMED);
++
++}
++EXPORT_SYMBOL(isppreview_config_hmed);
++
++/*
++ * Configures the Noise Filter
++ * prev_nf: Structure containing the noisefilter table, strength to be used
++ *          for the noise filter and the defect correction enable flag.
++ */
++void
++isppreview_config_noisefilter(struct ispprev_nf prev_nf)
++{
++	int i = 0;
++	omap_writel(prev_nf.spread, ISPPRV_NF);
++	omap_writel(ISPPRV_NF_TABLE_ADDR, ISPPRV_SET_TBL_ADDR);
++	for (i = 0; i < 64; i++)
++		omap_writel(prev_nf.table[i], ISPPRV_SET_TBL_DATA);
++}
++EXPORT_SYMBOL(isppreview_config_noisefilter);
++
++/*
++ * Configures the defect correction
++ * prev_nf: Structure containing the defect correction structure
++ */
++void
++isppreview_config_dcor(struct ispprev_dcor prev_dcor)
++{
++	if (prev_dcor.couplet_mode_en) {
++		omap_writel(prev_dcor.detect_correct[0], ISPPRV_CDC_THR0);
++		omap_writel(prev_dcor.detect_correct[1], ISPPRV_CDC_THR1);
++		omap_writel(prev_dcor.detect_correct[2], ISPPRV_CDC_THR2);
++		omap_writel(prev_dcor.detect_correct[3], ISPPRV_CDC_THR3);
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_DCCOUP,
++			ISPPRV_PCR);
++	} else
++		omap_writel((omap_readl(ISPPRV_PCR)) & (~ISPPRV_PCR_DCCOUP),
++			ISPPRV_PCR);
++}
++EXPORT_SYMBOL(isppreview_config_dcor);
++
++/*
++ * Configures the CFA Interpolation parameters
++ * prev_cfa: Structure containing the CFA interpolation table, CFA format
++ *		in the image, vertical and horizontal gradient threshold.
++ */
++void isppreview_config_cfa(struct ispprev_cfa prev_cfa)
++{
++	int i = 0;
++	ispprev_obj.cfafmt = prev_cfa.cfafmt;
++
++	omap_writel((omap_readl(ISPPRV_PCR))
++		| (prev_cfa.cfafmt << ISPPRV_PCR_CFAFMT_SHIFT), ISPPRV_PCR);
++
++	omap_writel((prev_cfa.cfa_gradthrs_vert << ISPPRV_CFA_GRADTH_VER_SHIFT)
++		| (prev_cfa.cfa_gradthrs_horz << ISPPRV_CFA_GRADTH_HOR_SHIFT),
++		ISPPRV_CFA);
++
++	omap_writel(ISPPRV_CFA_TABLE_ADDR, ISPPRV_SET_TBL_ADDR);
++
++	/* Array of 576 */
++	for (i = 0; i < 576; i++)
++		omap_writel(prev_cfa.cfa_table[i], ISPPRV_SET_TBL_DATA);
++}
++EXPORT_SYMBOL(isppreview_config_cfa);
++
++/*
++ * Configures the Gamma Correction table values
++ * gtable: Structure containing the table for red, blue, green gamma table.
++ */
++void
++isppreview_config_gammacorrn(struct ispprev_gtable gtable)
++{
++	int i = 0;
++
++	omap_writel(ISPPRV_REDGAMMA_TABLE_ADDR, ISPPRV_SET_TBL_ADDR);
++	/* Array of 1024 */
++	for (i = 0; i < 1024; i++)
++		omap_writel(gtable.redtable[i], ISPPRV_SET_TBL_DATA);
++
++	omap_writel(ISPPRV_GREENGAMMA_TABLE_ADDR, ISPPRV_SET_TBL_ADDR);
++	/* Array of 1024 */
++	for (i = 0; i < 1024; i++)
++		omap_writel(gtable.greentable[i], ISPPRV_SET_TBL_DATA);
++
++	omap_writel(ISPPRV_BLUEGAMMA_TABLE_ADDR, ISPPRV_SET_TBL_ADDR);
++	/* Array of 1024 */
++	for (i = 0; i < 1024; i++)
++		omap_writel(gtable.bluetable[i], ISPPRV_SET_TBL_DATA);
++}
++EXPORT_SYMBOL(isppreview_config_gammacorrn);
++
++/*
++ * Configures the Luminance Enhancement table values
++ * ytable: Structure containing the table for Luminance Enhancement table.
++ */
++void
++isppreview_config_luma_enhancement(u32 *ytable)
++{
++	int i = 0;
++	omap_writel(ISPPRV_YENH_TABLE_ADDR, ISPPRV_SET_TBL_ADDR);
++	/* Array of 128 */
++	for (i = 0; i < 128; i++)
++		omap_writel(ytable[i], ISPPRV_SET_TBL_DATA);
++}
++EXPORT_SYMBOL(isppreview_config_luma_enhancement);
++
++/*
++ * Configures the Chroma Suppression
++ * csup: Structure containing the threshold value for suppression
++ *		and the hypass filter enable flag.
++ */
++void
++isppreview_config_chroma_suppression(struct ispprev_csup csup)
++{
++	omap_writel(csup.gain | (csup.thres << ISPPRV_CSUP_THRES_SHIFT)
++			| (csup.hypf_en << ISPPRV_CSUP_HPYF_SHIFT)
++			, ISPPRV_CSUP);
++}
++EXPORT_SYMBOL(isppreview_config_chroma_suppression);
++
++/*
++ * Enable/Disable the Noise Filter
++ * enable: 1 - Enables the Noise Filter.
++ */
++void
++isppreview_enable_noisefilter(u8 enable)
++{
++	if (enable) {
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_NFEN,
++			ISPPRV_PCR);
++		ispprev_obj.nf_en = 1;
++	} else {
++		omap_writel((omap_readl(ISPPRV_PCR)) & (~ISPPRV_PCR_NFEN),
++			ISPPRV_PCR);
++		ispprev_obj.nf_en = 0;
++	}
++}
++EXPORT_SYMBOL(isppreview_enable_noisefilter);
++
++/*
++ * Enable/Disable the defect correction
++ * enable: 1 - Enables the defect correction.
++ */
++void
++isppreview_enable_dcor(u8 enable)
++{
++	if (enable) {
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_DCOREN,
++			ISPPRV_PCR);
++		ispprev_obj.dcor_en = 1;
++	} else {
++		omap_writel((omap_readl(ISPPRV_PCR)) & (~ISPPRV_PCR_DCOREN),
++			ISPPRV_PCR);
++		ispprev_obj.dcor_en = 0;
++	}
++}
++EXPORT_SYMBOL(isppreview_enable_dcor);
++
++/*
++ * Enable/Disable the CFA Interpolation
++ * enable: 1 - Enables the CFA.
++ */
++void
++isppreview_enable_cfa(u8 enable)
++{
++	if (enable) {
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_CFAEN,
++			ISPPRV_PCR);
++		ispprev_obj.cfa_en = 1;
++	} else {
++		omap_writel((omap_readl(ISPPRV_PCR)) & (~ISPPRV_PCR_CFAEN),
++			ISPPRV_PCR);
++		ispprev_obj.cfa_en = 0;
++	}
++
++}
++EXPORT_SYMBOL(isppreview_enable_cfa);
++
++/*
++ * Enable/Disable the GammaByPass
++ * enable: 1 - Bypasses Gamma - 10bit input is cropped to 8MSB.
++ * 0 - Goes through Gamma Correction. input and output is 10bit.
++ */
++void
++isppreview_enable_gammabypass(u8 enable)
++{
++	if (enable)
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_GAMMA_BYPASS,
++			ISPPRV_PCR);
++	else
++		omap_writel((omap_readl(ISPPRV_PCR)) &
++						(~ISPPRV_PCR_GAMMA_BYPASS),
++						ISPPRV_PCR);
++}
++EXPORT_SYMBOL(isppreview_enable_gammabypass);
++
++/*
++ * Enable/Disable the Luminance Enhancement
++ * enable: 1 - Enable the Luminance Enhancement.
++ */
++void
++isppreview_enable_luma_enhancement(u8 enable)
++{
++	if (enable) {
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_YNENHEN,
++			ISPPRV_PCR);
++		ispprev_obj.yenh_en = 1;
++	} else {
++		omap_writel((omap_readl(ISPPRV_PCR)) & (~ISPPRV_PCR_YNENHEN),
++			ISPPRV_PCR);
++		ispprev_obj.yenh_en = 0;
++	}
++}
++EXPORT_SYMBOL(isppreview_enable_luma_enhancement);
++
++/*
++ * Enable/Disable the Chrominance Suppression
++ * enable: 1 - Enable the Chrominance Suppression.
++ */
++void
++isppreview_enable_chroma_suppression(u8 enable)
++{
++	if (enable) {
++		omap_writel((omap_readl(ISPPRV_PCR)) | ISPPRV_PCR_SUPEN,
++			ISPPRV_PCR);
++		ispprev_obj.csup_en = 1;
++	} else {
++		omap_writel((omap_readl(ISPPRV_PCR)) & (~ISPPRV_PCR_SUPEN),
++			ISPPRV_PCR);
++		ispprev_obj.csup_en = 0;
++	}
++}
++EXPORT_SYMBOL(isppreview_enable_chroma_suppression);
++
++/*
++ * Configures the White Balance parameters. Coefficient matrix always with
++ * 		default values.
++ * prev_wbal: Structure containing the digital gain and white balance
++ *		coefficient.
++ */
++void isppreview_config_whitebalance(struct ispprev_wbal prev_wbal)
++{
++
++	omap_writel(prev_wbal.dgain, ISPPRV_WB_DGAIN);
++	omap_writel(prev_wbal.coef0 |
++		prev_wbal.coef1 << ISPPRV_WBGAIN_COEF1_SHIFT |
++		prev_wbal.coef2 << ISPPRV_WBGAIN_COEF2_SHIFT |
++		prev_wbal.coef3 << ISPPRV_WBGAIN_COEF3_SHIFT, ISPPRV_WBGAIN);
++
++	/* Keeping the HW default value as such */
++	omap_writel(ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_0_SHIFT
++		| ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_1_SHIFT
++		| ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_2_SHIFT
++		| ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_3_SHIFT
++		| ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_0_SHIFT
++		| ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_1_SHIFT
++		| ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_2_SHIFT
++		| ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_3_SHIFT
++		| ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_0_SHIFT
++		| ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_1_SHIFT
++		| ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_2_SHIFT
++		| ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_3_SHIFT
++		| ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_0_SHIFT
++		| ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_1_SHIFT
++		| ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_2_SHIFT
++		| ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_3_SHIFT,
++		ISPPRV_WBSEL);
++
++}
++EXPORT_SYMBOL(isppreview_config_whitebalance);
++
++/*
++ * Configures the White Balance parameters. Coefficient matrix can be changed.
++ * prev_wbal: Structure containing the digital gain and white balance
++ *		coefficient.
++ */
++void isppreview_config_whitebalance2(struct prev_white_balance prev_wbal)
++{
++	omap_writel(prev_wbal.wb_dgain, ISPPRV_WB_DGAIN);
++	omap_writel(prev_wbal.wb_gain[0]
++		| prev_wbal.wb_gain[1] << ISPPRV_WBGAIN_COEF1_SHIFT
++		| prev_wbal.wb_gain[2] << ISPPRV_WBGAIN_COEF2_SHIFT
++		| prev_wbal.wb_gain[3] << ISPPRV_WBGAIN_COEF3_SHIFT,
++		ISPPRV_WBGAIN);
++
++	/* Changing the HW default value */
++	omap_writel(prev_wbal.wb_coefmatrix[0][0] << ISPPRV_WBSEL_N0_0_SHIFT
++		| prev_wbal.wb_coefmatrix[0][1] << ISPPRV_WBSEL_N0_1_SHIFT
++		| prev_wbal.wb_coefmatrix[0][2] << ISPPRV_WBSEL_N0_2_SHIFT
++		| prev_wbal.wb_coefmatrix[0][3] << ISPPRV_WBSEL_N0_3_SHIFT
++		| prev_wbal.wb_coefmatrix[1][0] << ISPPRV_WBSEL_N1_0_SHIFT
++		| prev_wbal.wb_coefmatrix[1][1] << ISPPRV_WBSEL_N1_1_SHIFT
++		| prev_wbal.wb_coefmatrix[1][2] << ISPPRV_WBSEL_N1_2_SHIFT
++		| prev_wbal.wb_coefmatrix[1][3] << ISPPRV_WBSEL_N1_3_SHIFT
++		| prev_wbal.wb_coefmatrix[2][0] << ISPPRV_WBSEL_N2_0_SHIFT
++		| prev_wbal.wb_coefmatrix[2][1] << ISPPRV_WBSEL_N2_1_SHIFT
++		| prev_wbal.wb_coefmatrix[2][2] << ISPPRV_WBSEL_N2_2_SHIFT
++		| prev_wbal.wb_coefmatrix[2][3] << ISPPRV_WBSEL_N2_3_SHIFT
++		| prev_wbal.wb_coefmatrix[3][0] << ISPPRV_WBSEL_N3_0_SHIFT
++		| prev_wbal.wb_coefmatrix[3][1] << ISPPRV_WBSEL_N3_1_SHIFT
++		| prev_wbal.wb_coefmatrix[3][2] << ISPPRV_WBSEL_N3_2_SHIFT
++		| prev_wbal.wb_coefmatrix[3][3] << ISPPRV_WBSEL_N3_3_SHIFT,
++		ISPPRV_WBSEL);
++}
++EXPORT_SYMBOL(isppreview_config_whitebalance2);
++
++/*
++ * Configures the Black Adjustment parameters
++ * prev_blkadj: Structure containing the black adjustment towards red,
++ *		green, blue.
++ */
++void
++isppreview_config_blkadj(struct ispprev_blkadj prev_blkadj)
++{
++	omap_writel(prev_blkadj.blue
++		| (prev_blkadj.green << ISPPRV_BLKADJOFF_G_SHIFT)
++		| (prev_blkadj.red << ISPPRV_BLKADJOFF_R_SHIFT)
++		, ISPPRV_BLKADJOFF);
++}
++EXPORT_SYMBOL(isppreview_config_blkadj);
++
++/*
++ * Configures the RGB-RGB Blending matrix
++ * rgb2rgb: Structure containing the rgb to rgb blending matrix and the
++ *		rgb offset.
++ */
++void
++isppreview_config_rgb_blending(struct ispprev_rgbtorgb rgb2rgb)
++{
++	omap_writel((rgb2rgb.matrix[0][0] << ISPPRV_RGB_MAT1_MTX_RR_SHIFT)
++		| (rgb2rgb.matrix[0][1] << ISPPRV_RGB_MAT1_MTX_GR_SHIFT),
++		ISPPRV_RGB_MAT1);
++
++	omap_writel((rgb2rgb.matrix[0][2] << ISPPRV_RGB_MAT2_MTX_BR_SHIFT)
++		| (rgb2rgb.matrix[1][0] << ISPPRV_RGB_MAT2_MTX_RG_SHIFT),
++		ISPPRV_RGB_MAT2);
++
++	omap_writel((rgb2rgb.matrix[1][1] << ISPPRV_RGB_MAT3_MTX_GG_SHIFT)
++		| (rgb2rgb.matrix[1][2] << ISPPRV_RGB_MAT3_MTX_BG_SHIFT),
++		ISPPRV_RGB_MAT3);
++
++	omap_writel((rgb2rgb.matrix[2][0] << ISPPRV_RGB_MAT4_MTX_RB_SHIFT)
++		| (rgb2rgb.matrix[2][1] << ISPPRV_RGB_MAT4_MTX_GB_SHIFT),
++		ISPPRV_RGB_MAT4);
++
++	omap_writel((rgb2rgb.matrix[2][2] << ISPPRV_RGB_MAT5_MTX_BB_SHIFT),
++		ISPPRV_RGB_MAT5);
++
++	omap_writel((rgb2rgb.offset[0] << ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT)
++		| (rgb2rgb.offset[1] << ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT),
++		ISPPRV_RGB_OFF1);
++
++	omap_writel(rgb2rgb.offset[2] << ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT,
++		ISPPRV_RGB_OFF2);
++
++}
++EXPORT_SYMBOL(isppreview_config_rgb_blending);
++
++/*
++ * Configures the RGB-YCbYCr conversion matrix
++ * prev_csc: Structure containing the RGB to YCbYCr matrix and the
++ *		YCbCr offset.
++ */
++void
++isppreview_config_rgb_to_ycbcr(struct ispprev_csc prev_csc)
++{
++	omap_writel(prev_csc.matrix[0][0] << ISPPRV_CSC0_RY_SHIFT
++		| prev_csc.matrix[0][1] << ISPPRV_CSC0_GY_SHIFT
++		| prev_csc.matrix[0][2] << ISPPRV_CSC0_BY_SHIFT,
++		ISPPRV_CSC0);
++
++	omap_writel(prev_csc.matrix[1][0] << ISPPRV_CSC1_RCB_SHIFT
++		| prev_csc.matrix[1][1] << ISPPRV_CSC1_GCB_SHIFT
++		| prev_csc.matrix[1][2] << ISPPRV_CSC1_BCB_SHIFT,
++		ISPPRV_CSC1);
++
++	omap_writel(prev_csc.matrix[2][0] << ISPPRV_CSC2_RCR_SHIFT
++		| prev_csc.matrix[2][1] << ISPPRV_CSC2_GCR_SHIFT
++		| prev_csc.matrix[2][2] << ISPPRV_CSC2_BCR_SHIFT,
++		ISPPRV_CSC2);
++
++	omap_writel(prev_csc.offset[0] << ISPPRV_CSC_OFFSET_CR_SHIFT
++		| prev_csc.offset[1] << ISPPRV_CSC_OFFSET_CB_SHIFT
++		| prev_csc.offset[2] << ISPPRV_CSC_OFFSET_Y_SHIFT,
++		ISPPRV_CSC_OFFSET);
++}
++EXPORT_SYMBOL(isppreview_config_rgb_to_ycbcr);
++
++/*
++ * Query the contrast.
++ * contrast: Pointer to hold the current programmed contrast value.
++ */
++void
++isppreview_query_contrast(u8 *contrast)
++{
++	u32 brt_cnt_val = 0;
++	brt_cnt_val = omap_readl(ISPPRV_CNT_BRT);
++	*contrast = (brt_cnt_val >> ISPPRV_CNT_BRT_CNT_SHIFT) & 0xFF;
++	DPRINTK_ISPPREV(" Current brt cnt value in hw is %x\n", brt_cnt_val);
++}
++EXPORT_SYMBOL(isppreview_query_contrast);
++
++/*
++ * Updates the contrast.
++ * 		Value should be programmed before enabling the module.
++ */
++void
++isppreview_update_contrast(u8 *contrast)
++{
++	ispprev_obj.contrast = *contrast;
++}
++EXPORT_SYMBOL(isppreview_update_contrast);
++
++/*
++ * Configures the Contrast.
++ * contrast: 8bitvalue in U8Q4 format.
++ * 		Value should be programmed before enabling the module.
++ */
++void
++isppreview_config_contrast(u8 contrast)
++{
++	u32 brt_cnt_val = 0;
++
++	brt_cnt_val = omap_readl(ISPPRV_CNT_BRT);
++	brt_cnt_val &= ~(0xFF << ISPPRV_CNT_BRT_CNT_SHIFT);
++	contrast &= 0xFF;
++	omap_writel((brt_cnt_val)|(contrast << ISPPRV_CNT_BRT_CNT_SHIFT)
++			, ISPPRV_CNT_BRT);
++}
++EXPORT_SYMBOL(isppreview_config_contrast);
++
++/*
++ * Gets the range contrast value
++ * min_contrast: Pointer to hold the minimum Contrast value
++ * max_contrast: Pointer to hold the maximum Contrast value
++ */
++void
++isppreview_get_contrast_range(u8 *min_contrast, u8 *max_contrast)
++{
++	*min_contrast = ISPPRV_CONTRAST_MIN;
++	*max_contrast = ISPPRV_CONTRAST_MAX;
++}
++EXPORT_SYMBOL(isppreview_get_contrast_range);
++
++/*
++ * Updates the brightness in the preview module.
++ */
++void
++isppreview_update_brightness(u8 *brightness)
++{
++	ispprev_obj.brightness = *brightness;
++}
++EXPORT_SYMBOL(isppreview_update_brightness);
++
++/*
++ * Configures the brightness.
++ * contrast: 8bitvalue in U8Q0 format.
++ */
++void
++isppreview_config_brightness(u8 brightness)
++{
++	u32 brt_cnt_val = 0;
++	DPRINTK_ISPPREV("\tConfiguring brightness in ISP: %d\n", brightness);
++	brt_cnt_val = omap_readl(ISPPRV_CNT_BRT);
++	brt_cnt_val &= ~(0xFF << ISPPRV_CNT_BRT_BRT_SHIFT);
++	brightness &= 0xFF;
++	omap_writel((brt_cnt_val)|(brightness << ISPPRV_CNT_BRT_BRT_SHIFT)
++			, ISPPRV_CNT_BRT);
++}
++EXPORT_SYMBOL(isppreview_config_brightness);
++
++/*
++ * Query the brightness.
++ * brightness: Pointer to hold the current programmed brightness value.
++ */
++void
++isppreview_query_brightness(u8 *brightness)
++{
++
++	*brightness = omap_readl(ISPPRV_CNT_BRT);
++}
++EXPORT_SYMBOL(isppreview_query_brightness);
++
++/*
++ * Gets the range brightness value
++ * min_brightness: Pointer to hold the minimum brightness value
++ * max_brightness: Pointer to hold the maximum brightness value
++ */
++void
++isppreview_get_brightness_range(u8 *min_brightness, u8 *max_brightness)
++{
++	*min_brightness = ISPPRV_BRIGHT_MIN;
++	*max_brightness = ISPPRV_BRIGHT_MAX;
++}
++EXPORT_SYMBOL(isppreview_get_brightness_range);
++
++/**
++ * @brief isppreview_set_color -- sets the color effect.
++ * @param mode -- indicates the required color effect.
++ */
++void isppreview_set_color(u8 *mode)
++{
++	ispprev_obj.color = *mode;
++	update_color_matrix = 1;
++}
++EXPORT_SYMBOL(isppreview_set_color);
++
++/**
++ * @brief isppreview_get_color -- gets the current color effect.
++ * @param mode -- indicates the current color effect.
++ */
++void isppreview_get_color(u8 *mode)
++{
++	*mode = ispprev_obj.color;
++}
++EXPORT_SYMBOL(isppreview_get_color);
++
++/*
++ * Configures the max and minim Y and C values.
++ * yclimit: Structure containing the min,max Y,C values.
++ */
++void
++isppreview_config_yc_range(struct ispprev_yclimit yclimit)
++{
++	omap_writel(((yclimit.maxC << ISPPRV_SETUP_YC_MAXC_SHIFT)
++			| (yclimit.maxY << ISPPRV_SETUP_YC_MAXY_SHIFT)
++			| (yclimit.minC << ISPPRV_SETUP_YC_MINC_SHIFT)
++			| (yclimit.minY << ISPPRV_SETUP_YC_MINY_SHIFT))
++			, ISPPRV_SETUP_YC);
++}
++EXPORT_SYMBOL(isppreview_config_yc_range);
++
++/*
++ * Calculates the number of pixels cropped in the submodules that are enabled,
++ * Fills up the output widht height variables in the isp_prev structure .
++ * input_w: input width for the preview in number of pixels per line
++ * input_h: input height for the preview in number of lines
++ * output_w: output width from the preview in number of pixels per line
++ * output_h: output height for the preview in number of lines
++*/
++int
++isppreview_try_size(u32 input_w, u32 input_h, u32 *output_w,
++			u32 *output_h)
++{
++	u32 prevout_w = input_w;
++	u32 prevout_h = input_h;
++	u32 div = 0;
++	int max_out;
++
++	ispprev_obj.previn_w = input_w;
++	ispprev_obj.previn_h = input_h;
++
++	/*Checks if input size is more than the preview output width limit,
++	*else suggests for downsampling in the averager.
++	*/
++	if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
++		max_out = ISPPRV_MAXOUTPUT_WIDTH;
++	else
++		max_out = ISPPRV_MAXOUTPUT_WIDTH_ES2;
++
++	ispprev_obj.fmtavg = 0;
++
++	if (input_w > max_out) {
++		div = (input_w/max_out);
++		if (div >= 2 && div < 4) {
++			ispprev_obj.fmtavg = 1;
++			prevout_w /= 2;
++		} else if (div >= 4 && div < 8) {
++			ispprev_obj.fmtavg = 2;
++			prevout_w /= 4;
++		} else if (div >= 8) {
++			ispprev_obj.fmtavg = 3;
++			prevout_w /= 8;
++		}
++	}
++
++	if (ispprev_obj.hmed_en)
++		prevout_w -= 4;
++	if (ispprev_obj.nf_en) {
++		prevout_w -= 4;
++		prevout_h -= 4;
++	}
++	if (ispprev_obj.cfa_en) {
++		switch (ispprev_obj.cfafmt) {
++		case CFAFMT_BAYER:
++		case CFAFMT_SONYVGA:
++			prevout_w -= 4;
++			prevout_h -= 4;
++			break;
++		case CFAFMT_RGBFOVEON:
++		case CFAFMT_RRGGBBFOVEON:
++		case CFAFMT_DNSPL:
++		case CFAFMT_HONEYCOMB:
++			prevout_h -= 2;
++			break;
++		};
++	}
++	if ((ispprev_obj.yenh_en) || (ispprev_obj.csup_en))
++		prevout_w -= 2;
++
++	/* FMTSPH is always set to be 4 */
++	 prevout_w -= 4;
++	/* Reserving for now, another 2 extra pixels from Preview to Resizer
++	prevout_w -=2;*/
++
++	/*
++	 * Make sure that preview always outputs even number of pixels
++	 */
++	if (prevout_w % 2)
++		prevout_w -= 1;
++
++	if (ispprev_obj.prev_outfmt == PREVIEW_MEM) {
++		if (((prevout_w*2)&ISP_32B_BOUNDARY_OFFSET) != (prevout_w*2))
++			prevout_w = ((prevout_w*2)&ISP_32B_BOUNDARY_OFFSET)/2;
++	}
++	ispprev_obj.prevout_w = *output_w = prevout_w;
++	ispprev_obj.prevout_h = *output_h = prevout_h;
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_try_size);
++
++/*
++ * Configures the appropriate values stored in the isp_prev structure to
++ * HORZ/VERT_INFO.
++ * Configures PRV_AVE if needed for downsampling as calculated in trysize.
++ * input_w: input width for the preview in number of pixels per line
++ * input_h: input height for the preview in number of lines
++ * output_w: output width from the preview in number of pixels per line
++ * output_h: output height for the preview in number of lines
++ */
++int
++isppreview_config_size(u32 input_w, u32 input_h, u32 output_w,
++			u32 output_h)
++{
++	u32 prevsdroff;
++
++	/* Checks if the parameters match the values calculated in the
++	* isppreview_try_size(). If not return error.
++	*/
++	if ((output_w != ispprev_obj.prevout_w)
++		|| (output_h != ispprev_obj.prevout_h)) {
++			printk(KERN_ERR "ISP_ERR : isppreview_try_size should "
++				"be called before config size\n");
++			return -EINVAL;
++	}
++
++	omap_writel((4 << ISPPRV_HORZ_INFO_SPH_SHIFT) |
++						(ispprev_obj.previn_w - 1),
++						ISPPRV_HORZ_INFO);
++	omap_writel((0 << ISPPRV_VERT_INFO_SLV_SHIFT) |
++						(ispprev_obj.previn_h - 1),
++						ISPPRV_VERT_INFO);
++
++	if (ispprev_obj.cfafmt == CFAFMT_BAYER)
++		omap_writel(ISPPRV_AVE_EVENDIST_2 << ISPPRV_AVE_EVENDIST_SHIFT
++			| ISPPRV_AVE_ODDDIST_2 << ISPPRV_AVE_ODDDIST_SHIFT
++			| ispprev_obj.fmtavg,
++			ISPPRV_AVE);
++
++	/* When written to memory output should be of 32byte boundary */
++	if (ispprev_obj.prev_outfmt == PREVIEW_MEM) {
++		prevsdroff = ispprev_obj.prevout_w*2;
++		if ((prevsdroff & ISP_32B_BOUNDARY_OFFSET) != prevsdroff) {
++			DPRINTK_ISPPREV("ISP_WARN : Preview output buffer line"
++				" size is truncated to 32byte boundary\n");
++			prevsdroff &= ISP_32B_BOUNDARY_BUF ;
++		}
++		isppreview_config_outlineoffset(prevsdroff);
++	}
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_config_size);
++
++/*
++ * Configures the Read address line offset.
++ * offset: Line Offset for the input image.
++ */
++int
++isppreview_config_inlineoffset(u32 offset)
++{
++	if ((offset & ISP_32B_BOUNDARY_OFFSET) == offset)
++		omap_writel(offset&0xFFFF, ISPPRV_RADR_OFFSET);
++	else{
++		printk(KERN_ERR "ISP_ERR : Offset should be in 32 byte "
++			"boundary\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_config_inlineoffset);
++
++/*
++ * Configures the memory address from which the input frame is to be read.
++ * addr: 32bit memory address aligned on 32byte boundary.
++ */
++int isppreview_set_inaddr(u32 addr)
++{
++	if ((addr & ISP_32B_BOUNDARY_BUF) == addr)
++		omap_writel(addr, ISPPRV_RSDR_ADDR);
++	else{
++		printk(KERN_ERR "ISP_ERR : Address should be in 32 byte "
++			"boundary\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_set_inaddr);
++
++/*
++ * Configures the Write address line offset.
++ * offset: Line Offset for the preview output.
++ */
++int isppreview_config_outlineoffset(u32 offset)
++{
++	if ((offset & ISP_32B_BOUNDARY_OFFSET) == offset) {
++		omap_writel(offset&0xFFFF, ISPPRV_WADD_OFFSET);
++		}
++	else{
++		printk(KERN_ERR "ISP_ERR : Offset should be in 32 byte "
++			"boundary\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_config_outlineoffset);
++
++/*
++ * Configures the memory address to which the output frame is written.
++ * addr: 32bit memory address aligned on 32byte boundary.
++ */
++int
++isppreview_set_outaddr(u32 addr)
++{
++	if ((addr & ISP_32B_BOUNDARY_BUF) == addr) {
++		omap_writel(addr, ISPPRV_WSDR_ADDR);
++	} else {
++		printk(KERN_ERR "ISP_ERR : Address should be in 32 byte "
++			"boundary\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_set_outaddr);
++
++/*
++ * Configures the Dark frame address line offset.
++ * offset: Line Offset for the Darkframe.
++ */
++int
++isppreview_config_darklineoffset(u32 offset)
++{
++	if ((offset & ISP_32B_BOUNDARY_OFFSET) == offset)
++		omap_writel(offset&0xFFFF, ISPPRV_DRKF_OFFSET);
++	else{
++		printk(KERN_ERR "ISP_ERR : Offset should be in 32 byte "
++			"boundary\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_config_darklineoffset);
++
++/*
++ * Configures the memory address where the Dark frame should be stored.
++ * addr: 32bit memory address aligned on 32 bit boundary.
++ */
++int
++isppreview_set_darkaddr(u32 addr)
++{
++	if ((addr & ISP_32B_BOUNDARY_BUF) == addr)
++		omap_writel(addr, ISPPRV_DSDR_ADDR);
++	else{
++		printk(KERN_ERR "ISP_ERR : Address should be in 32 byte "
++			"boundary\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++EXPORT_SYMBOL(isppreview_set_darkaddr);
++
++/*
++ *
++ * Enables the Preview module.
++ * Client should configure all the sub modules in Preview before this.
++ * enable: 1- Enables the preview module.
++ */
++void
++isppreview_enable(u8 enable)
++{
++
++	if (enable)
++		omap_writel((omap_readl(ISPPRV_PCR))
++				| ISPPRV_PCR_EN, ISPPRV_PCR);
++	else
++		omap_writel((omap_readl(ISPPRV_PCR))
++				& ~ISPPRV_PCR_EN, ISPPRV_PCR);
++}
++EXPORT_SYMBOL(isppreview_enable);
++
++int isppreview_busy(void)
++{
++	return (omap_readl(ISPPRV_PCR) & ISPPRV_PCR_BUSY);
++}
++EXPORT_SYMBOL(isppreview_busy);
++
++struct prev_params *isppreview_get_config(void)
++{
++	return prev_config_params;
++}
++EXPORT_SYMBOL(isppreview_get_config);
++
++/*
++ * Saves the values of the preview module registers.
++ */
++void isppreview_save_context(void)
++{
++	DPRINTK_ISPPREV(" Saving context\n");
++	isp_save_context(ispprev_reg_list);
++}
++EXPORT_SYMBOL(isppreview_save_context);
++
++/*
++ * Restores the values of the preview module registers.
++ */
++void isppreview_restore_context(void)
++{
++	DPRINTK_ISPPREV(" Restoring context\n");
++	isp_restore_context(ispprev_reg_list);
++}
++EXPORT_SYMBOL(isppreview_restore_context);
++
++/*
++ * Prints the values of the Preview Module registers
++ * Also prints other debug information stored in the preview moduel
++ */
++void isppreview_print_status(void)
++{
++#ifdef OMAP_ISPPREV_DEBUG
++	printk("Module in use =%d\n", ispprev_obj.prev_inuse);
++	DPRINTK_ISPPREV("Preview Input format =%d, Output Format =%d\n",
++						ispprev_obj.prev_inpfmt,
++						ispprev_obj.prev_outfmt);
++	DPRINTK_ISPPREV("Accepted Preview Input (width = %d,Height = %d)\n",
++						ispprev_obj.previn_w,
++						ispprev_obj.previn_h);
++	DPRINTK_ISPPREV("Accepted Preview Output (width = %d,Height = %d)\n",
++						ispprev_obj.prevout_w,
++						ispprev_obj.prevout_h);
++	DPRINTK_ISPPREV("###ISP_CTRL in preview =0x%x\n",
++						omap_readl(ISP_CTRL));
++	DPRINTK_ISPPREV("###ISP_IRQ0ENABLE in preview =0x%x\n",
++						omap_readl(ISP_IRQ0ENABLE));
++	DPRINTK_ISPPREV("###ISP_IRQ0STATUS in preview =0x%x\n",
++						omap_readl(ISP_IRQ0STATUS));
++	DPRINTK_ISPPREV("###PRV PCR =0x%x\n", omap_readl(ISPPRV_PCR));
++	DPRINTK_ISPPREV("###PRV HORZ_INFO =0x%x\n",
++						omap_readl(ISPPRV_HORZ_INFO));
++	DPRINTK_ISPPREV("###PRV VERT_INFO =0x%x\n",
++						omap_readl(ISPPRV_VERT_INFO));
++	DPRINTK_ISPPREV("###PRV WSDR_ADDR =0x%x\n",
++						omap_readl(ISPPRV_WSDR_ADDR));
++	DPRINTK_ISPPREV("###PRV WADD_OFFSET =0x%x\n",
++					omap_readl(ISPPRV_WADD_OFFSET));
++	DPRINTK_ISPPREV("###PRV AVE =0x%x\n", omap_readl(ISPPRV_AVE));
++	DPRINTK_ISPPREV("###PRV HMED =0x%x\n", omap_readl(ISPPRV_HMED));
++	DPRINTK_ISPPREV("###PRV NF =0x%x\n", omap_readl(ISPPRV_NF));
++	DPRINTK_ISPPREV("###PRV WB_DGAIN =0x%x\n",
++						omap_readl(ISPPRV_WB_DGAIN));
++	DPRINTK_ISPPREV("###PRV WBGAIN =0x%x\n", omap_readl(ISPPRV_WBGAIN));
++	DPRINTK_ISPPREV("###PRV WBSEL =0x%x\n", omap_readl(ISPPRV_WBSEL));
++	DPRINTK_ISPPREV("###PRV CFA =0x%x\n", omap_readl(ISPPRV_CFA));
++	DPRINTK_ISPPREV("###PRV BLKADJOFF =0x%x\n",
++						omap_readl(ISPPRV_BLKADJOFF));
++	DPRINTK_ISPPREV("###PRV RGB_MAT1 =0x%x\n",
++						omap_readl(ISPPRV_RGB_MAT1));
++	DPRINTK_ISPPREV("###PRV RGB_MAT2 =0x%x\n",
++						omap_readl(ISPPRV_RGB_MAT2));
++	DPRINTK_ISPPREV("###PRV RGB_MAT3 =0x%x\n",
++						omap_readl(ISPPRV_RGB_MAT3));
++	DPRINTK_ISPPREV("###PRV RGB_MAT4 =0x%x\n",
++						omap_readl(ISPPRV_RGB_MAT4));
++	DPRINTK_ISPPREV("###PRV RGB_MAT5 =0x%x\n",
++						omap_readl(ISPPRV_RGB_MAT5));
++	DPRINTK_ISPPREV("###PRV RGB_OFF1 =0x%x\n",
++						omap_readl(ISPPRV_RGB_OFF1));
++	DPRINTK_ISPPREV("###PRV RGB_OFF2 =0x%x\n",
++						omap_readl(ISPPRV_RGB_OFF2));
++	DPRINTK_ISPPREV("###PRV CSC0 =0x%x\n", omap_readl(ISPPRV_CSC0));
++	DPRINTK_ISPPREV("###PRV CSC1 =0x%x\n", omap_readl(ISPPRV_CSC1));
++	DPRINTK_ISPPREV("###PRV CSC2 =0x%x\n", omap_readl(ISPPRV_CSC2));
++	DPRINTK_ISPPREV("###PRV CSC_OFFSET =0x%x\n",
++						omap_readl(ISPPRV_CSC_OFFSET));
++	DPRINTK_ISPPREV("###PRV CNT_BRT =0x%x\n", omap_readl(ISPPRV_CNT_BRT));
++	DPRINTK_ISPPREV("###PRV CSUP =0x%x\n", omap_readl(ISPPRV_CSUP));
++	DPRINTK_ISPPREV("###PRV SETUP_YC =0x%x\n",
++						omap_readl(ISPPRV_SETUP_YC));
++#endif
++}
++EXPORT_SYMBOL(isppreview_print_status);
++
++/*
++ * Module Initialisation.
++ */
++static int __init
++isp_preview_init(void)
++{
++	struct prev_params *params;
++	int i = 0;
++
++	prev_config_params = kmalloc(sizeof(*prev_config_params), GFP_KERNEL);
++	if (prev_config_params == NULL) {
++		printk(KERN_ERR "Can't get memory for isp_preview params!\n");
++		return -ENOMEM;
++	}
++	params = prev_config_params;
++
++	ispprev_obj.prev_inuse = 0;
++	mutex_init(&ispprev_obj.ispprev_mutex);
++
++	if (is_sil_rev_equal_to(OMAP3430_REV_ES2_0)) {
++		flr_wbal_coef0 = 0x23;
++		flr_wbal_coef1 = 0x20;
++		flr_wbal_coef2 = 0x20;
++		flr_wbal_coef3 = 0x39;
++	}
++
++	/* Init values */
++	ispprev_obj.color = PREV_DEFAULT_COLOR;
++	params->contrast = ispprev_obj.contrast = ISPPRV_CONTRAST_DEF;
++	params->brightness = ispprev_obj.brightness = ISPPRV_BRIGHT_DEF;
++	params->average = NO_AVE;
++	params->lens_shading_shift = 0;
++	params->pix_fmt = YCPOS_YCrYCb;
++	/* Color Filter Array */
++	params->cfa.cfafmt = CFAFMT_BAYER;
++	params->cfa.cfa_table = cfa_coef_table;
++	params->cfa.cfa_gradthrs_horz = flr_cfa_gradthrs_horz;
++	params->cfa.cfa_gradthrs_vert = flr_cfa_gradthrs_vert;
++	/* Chroma Suppression */
++	params->csup.gain = flr_csup_gain;
++	params->csup.thres = flr_csup_thres;
++	params->csup.hypf_en = 0;
++	/* Lumma Enhancement Table */
++	params->ytable = luma_enhance_table;
++	/* Noise Filter */
++	params->nf.spread = flr_nf_strgth;
++	params->nf.table = noise_filter_table;
++	/* defect correction */
++	params->dcor.couplet_mode_en = 1;
++	for (i = 0; i < 4; i++)
++		params->dcor.detect_correct[i] = 0xE;
++	/* Gamma Correction */
++	params->gtable.bluetable = bluegamma_table;
++	params->gtable.greentable = greengamma_table;
++	params->gtable.redtable = redgamma_table;
++	/* White Balance */
++	params->wbal.dgain = flr_wbal_dgain;
++	params->wbal.coef0 = flr_wbal_coef0;
++	params->wbal.coef1 = flr_wbal_coef1;
++	params->wbal.coef2 = flr_wbal_coef2;
++	params->wbal.coef3 = flr_wbal_coef3;
++	/* Black Adjustment */
++	params->blk_adj.red = flr_blkadj_red;
++	params->blk_adj.green = flr_blkadj_green;
++	params->blk_adj.blue = flr_blkadj_blue;
++	/* RGB to RGB Blending */
++	params->rgb2rgb = flr_rgb2rgb;
++	/* RGB to YCbCr Blending */
++	params->rgb2ycbcr = flr_prev_csc[ispprev_obj.color];
++
++	/* Features enabled by default */
++	params->features = PREV_CFA | PREV_CHROMA_SUPPRESS | PREV_LUMA_ENHANCE
++				| PREV_DEFECT_COR | PREV_NOISE_FILTER;
++	params->features &= ~(PREV_AVERAGER | PREV_INVERSE_ALAW |
++						PREV_HORZ_MEDIAN_FILTER |
++						PREV_GAMMA_BYPASS |
++						PREV_DARK_FRAME_SUBTRACT |
++						PREV_LENS_SHADING |
++						PREV_DARK_FRAME_CAPTURE);
++	return 0;
++}
++
++static void
++isp_preview_cleanup(void)
++{
++	kfree(prev_config_params);
++	prev_config_params = NULL;
++}
++
++module_init(isp_preview_init);
++module_exit(isp_preview_cleanup);
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("ISP Preview Library");
++MODULE_LICENSE("GPL");
+Index: git/drivers/media/video/isp/isppreview.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/isppreview.h	2009-02-12 16:32:50.000000000 -0600
+@@ -0,0 +1,525 @@
++/*
++ * drivers/media/video/isp/isppreview.h
++ *
++ * Driver include file for Preview module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_PREVIEW_H
++#define OMAP_ISP_PREVIEW_H
++
++/* Isp query control structure */
++
++#define ISPPRV_BRIGHT_STEP		0x1
++#define ISPPRV_BRIGHT_DEF		0x1
++#define ISPPRV_BRIGHT_LOW		0x0
++#define ISPPRV_BRIGHT_HIGH		0xF
++#define ISPPRV_BRIGHT_UNITS      	0x7
++
++#define ISPPRV_CONTRAST_STEP	0x1
++#define ISPPRV_CONTRAST_DEF	0x2
++#define ISPPRV_CONTRAST_LOW	0x0
++#define ISPPRV_CONTRAST_HIGH	0xF
++#define ISPPRV_CONTRAST_UNITS	0x5
++
++#define NO_AVE   	0x0
++#define AVE_2_PIX	0x1
++#define AVE_4_PIX	0x2
++#define AVE_8_PIX	0x3
++#define AVE_ODD_PIXEL_DIST  	(1 << 4) /* For Bayer Sensors */
++#define AVE_EVEN_PIXEL_DIST 	(1 << 2)
++
++#define WB_GAIN_MAX	4
++#define RGB_MAX         3
++
++/* Features list */
++#define PREV_AVERAGER			(1 << 0)
++#define PREV_INVERSE_ALAW 		(1 << 1)
++#define PREV_HORZ_MEDIAN_FILTER		(1 << 2)
++#define PREV_NOISE_FILTER 		(1 << 3)
++#define PREV_CFA         		(1 << 4)
++#define PREV_GAMMA_BYPASS      		(1 << 5)
++#define PREV_LUMA_ENHANCE     		(1 << 6)
++#define PREV_CHROMA_SUPPRESS  		(1 << 7)
++#define PREV_DARK_FRAME_SUBTRACT	(1 << 8)
++#define PREV_LENS_SHADING    		(1 << 9)
++#define PREV_DARK_FRAME_CAPTURE  	(1 << 10)
++#define PREV_DEFECT_COR  		(1 << 11)
++
++/* Abstraction layer preview configurations */
++#define ISP_ABS_PREV_LUMAENH		(1 << 1)
++#define ISP_ABS_PREV_INVALAW		(1 << 2)
++#define ISP_ABS_PREV_HRZ_MED		(1 << 5)
++#define ISP_ABS_PREV_CFA		(1 << 6)
++#define ISP_ABS_PREV_CHROMA_SUPP	(1 << 7)
++#define ISP_ABS_PREV_WB			(1 << 8)
++#define ISP_ABS_PREV_BLKADJ		(1 << 9)
++#define ISP_ABS_PREV_RGB2RGB		(1 << 10)
++#define ISP_ABS_PREV_COLOR_CONV		(1 << 11)
++#define ISP_ABS_PREV_YC_LIMIT		(1 << 12)
++#define ISP_ABS_PREV_DEFECT_COR		(1 << 13)
++#define ISP_ABS_PREV_GAMMABYPASS	(1 << 14)
++
++/* Abstraction layer Table Update Flags */
++#define ISP_ABS_TBL_NF 			(1 << 1)
++#define ISP_ABS_TBL_REDGAMMA		(1 << 2)
++#define ISP_ABS_TBL_GREENGAMMA		(1 << 3)
++#define ISP_ABS_TBL_BLUEGAMMA		(1 << 4)
++
++#define ISP_NF_TABLE_SIZE 		64
++#define ISP_GAMMA_TABLE_SIZE 		1024
++
++/*
++ *Enumeration Constants for input and output format
++ */
++enum preview_input {
++	PRV_RAW_CCDC,
++	PRV_RAW_MEM,
++	PRV_RGBBAYERCFA,
++	PRV_COMPCFA,
++	PRV_CCDC_DRKF,
++	PRV_OTHERS
++};
++
++enum preview_output {
++	PREVIEW_RSZ,
++	PREVIEW_MEM
++};
++/*
++ * Configure byte layout of YUV image
++ */
++enum preview_ycpos_mode {
++	YCPOS_YCrYCb = 0,
++	YCPOS_YCbYCr = 1,
++	YCPOS_CbYCrY = 2,
++	YCPOS_CrYCbY = 3
++};
++
++enum preview_color_effect {
++	PREV_DEFAULT_COLOR = 0,
++	PREV_BW_COLOR = 1,
++	PREV_SEPIA_COLOR = 2
++};
++
++/**
++ * struct ispprev_hmed - Structure for Horizontal Median Filter.
++ * @odddist: Distance between consecutive pixels of same color in the odd line.
++ * @evendist: Distance between consecutive pixels of same color in the even
++ *            line.
++ * @thres: Horizontal median filter threshold.
++ */
++struct ispprev_hmed {
++	u8 odddist;
++	u8 evendist;
++	u8 thres;
++};
++
++/*
++ * Structure for Noise Filter
++ */
++struct ispprev_nf {
++	/* Spread value to be used in Noise Filter*/
++	u8 spread;
++	/*Pointer to the Noise Filter table */
++	u32 *table;
++};
++
++/*
++ * Structure for Defect correction
++ */
++struct ispprev_dcor {
++	/* Flag to enable or disable the couplet dc Correction in NF*/
++	u8 couplet_mode_en;
++	/* Thresholds for correction bit 0:10 detect 16:25 correct*/
++	u32 detect_correct[4];
++};
++
++
++
++/*
++ * Enumeration for CFA Formats supported by preview
++ */
++enum cfa_fmt {
++	CFAFMT_BAYER, CFAFMT_SONYVGA, CFAFMT_RGBFOVEON,
++	CFAFMT_DNSPL, CFAFMT_HONEYCOMB, CFAFMT_RRGGBBFOVEON
++};
++/*
++ * Structure for CFA Inpterpolation
++ */
++struct ispprev_cfa {
++	/* CFA Format Enum value supported by preview.*/
++	enum cfa_fmt cfafmt;
++	/* CFA Gradient Threshold - Vertical */
++	u8 cfa_gradthrs_vert;
++	/* CFA Gradient Threshold - Horizontal */
++	u8 cfa_gradthrs_horz;
++	/* Pointer to the CFA table */
++	u32 *cfa_table;
++};
++/*
++ * Structure for Gamma Correction
++ */
++struct ispprev_gtable {
++	/* Pointer to the red gamma table */
++	u32 *redtable;
++	/* Pointer to the green gamma table */
++	u32 *greentable;
++	/* Pointer to the blue gamma table */
++	u32 *bluetable;
++};
++/*
++ * Structure for Chrominance Suppression
++ */
++struct ispprev_csup {
++	/* Gain */
++	u8 gain;
++	/* Threshold */
++	u8 thres;
++	/* Flag to enable/disable the High Pass Filter */
++	u8 hypf_en;
++};
++/*
++ * Structure for White Balance
++ */
++struct ispprev_wbal {
++	/*Digital gain (U10Q8) */
++	u16 dgain;
++	/*White balance gain - COEF 3 (U8Q5) */
++	u8 coef3;
++	/*White balance gain - COEF 2 (U8Q5) */
++	u8 coef2;
++	/*White balance gain - COEF 1 (U8Q5) */
++	u8 coef1;
++	/*White balance gain - COEF 0 (U8Q5) */
++	u8 coef0;
++};
++
++struct prev_white_balance {
++	u16 wb_dgain;	/* white balance common gain */
++	u8 wb_gain[WB_GAIN_MAX];  /* individual color gains */
++	u8 wb_coefmatrix[WB_GAIN_MAX][WB_GAIN_MAX];
++};
++/*
++ * Structure for Black Adjustment
++ */
++struct ispprev_blkadj {
++	/*Black level offset adjustment for Red in 2's complement format */
++	u8 red;
++	/*Black level offset adjustment for Green in 2's complement format */
++	u8 green;
++	/* Black level offset adjustment for Blue in 2's complement format */
++	u8 blue;
++};
++/*
++ * Structure for RGB to RGB Blending
++ */
++struct ispprev_rgbtorgb {
++	/*
++	 * Blending values(S12Q8 format)
++	 *	[RR] [GR] [BR]
++	 *	[RG] [GG] [BG]
++	 *	[RB] [GB] [BB]
++	 */
++	u16 matrix[3][3];
++	/*Blending offset value for R,G,B in 2's complement integer format*/
++	u16 offset[3];
++};
++/*
++ * Structure for Color Space Conversion from RGB-YCbYCr
++ */
++struct ispprev_csc {
++	/*
++	 *Color space conversion coefficients(S10Q8)
++	 *	[CSCRY]    [CSCGY]   [CSCBY]
++	 *	[CSCRCB] [CSCGCB] [CSCBCB]
++	 *	[CSCRCR] [CSCGCR] [CSCBCR]
++	 */
++	u16 matrix[RGB_MAX][RGB_MAX];
++	/*
++	 *CSC offset values for Y offset, CB offset and CR offset respectively
++	 */
++	s16 offset[RGB_MAX];
++};
++/*
++ * Structure for Y, C Value Limit
++ */
++struct ispprev_yclimit{
++	u8 minC;
++	u8 maxC;
++	u8 minY;
++	u8 maxY;
++};
++
++/*
++ * Structure for size parameters
++ */
++struct prev_size_params {
++	unsigned int hstart;	/* Starting pixel */
++	unsigned int vstart;	/* Starting line */
++	unsigned int hsize;	/* width of input image */
++	unsigned int vsize;	/* height of input image */
++	unsigned char pixsize;	/* pixel size of the image in
++				   terms of bits */
++	unsigned short in_pitch;	/* line offset of input image */
++	unsigned short out_pitch;	/* line offset of output image */
++};
++
++/*
++ * Structure RGB2YCbCr parameters
++ */
++struct prev_rgb2ycbcr_coeffs {
++	short coeff[RGB_MAX][RGB_MAX];	/* color conversion gains in
++					   3x3 matrix */
++	short offset[RGB_MAX];	/* color conversion offsets */
++};
++
++/*
++ * Structure for Dark frame suppression
++ */
++struct prev_darkfrm_params {
++	u32 addr;	/* memory start address */
++	u32 offset;	/* line offset */
++};
++
++
++/*
++ * Structure for all configuration
++ */
++struct prev_params {
++	u16 features;	/* Set of features enabled */
++
++	enum preview_ycpos_mode pix_fmt; /* output pixel format */
++
++	struct ispprev_cfa cfa; /* CFA coefficients */
++
++	struct ispprev_csup csup;  /* chroma suppression coefficients */
++
++	u32 *ytable;	/* luma enhancement coeffs */
++
++	struct ispprev_nf nf; /* noise filter coefficients */
++
++	struct ispprev_dcor dcor; /* noise filter coefficients */
++
++	struct ispprev_gtable gtable;	/* gamma coefficients */
++
++	struct ispprev_wbal wbal;
++	/*
++	struct prev_white_balance prev_wbal;
++	*/
++	struct ispprev_blkadj blk_adj;	/* black adjustment parameters */
++
++	struct ispprev_rgbtorgb rgb2rgb;  /* rgb blending parameters */
++
++	struct ispprev_csc rgb2ycbcr;  /* rgb to ycbcr parameters */
++
++	struct ispprev_hmed hmf_params;	/* horizontal median filter */
++
++	struct prev_size_params size_params;	/* size parameters */
++	struct prev_darkfrm_params drkf_params;
++	u8 lens_shading_shift;
++	u8 average;	/* down sampling rate for averager */
++
++	u8 contrast;		/* contrast */
++	u8 brightness;		/* brightness */
++};
++
++/**
++ * struct ispprv_update_config - Structure for Preview Configuration (user).
++ * @update: Specifies which ISP Preview registers should be updated.
++ * @flag: Specifies which ISP Preview functions should be enabled.
++ * @yen: Pointer to luma enhancement table.
++ * @shading_shift: 3bit value of shift used in shading compensation.
++ * @prev_hmed: Pointer to structure containing the odd and even distance.
++ *             between the pixels in the image along with the filter threshold.
++ * @prev_cfa: Pointer to structure containing the CFA interpolation table, CFA.
++ *            format in the image, vertical and horizontal gradient threshold.
++ * @csup: Pointer to Structure for Chrominance Suppression coefficients.
++ * @prev_wbal: Pointer to structure for White Balance.
++ * @prev_blkadj: Pointer to structure for Black Adjustment.
++ * @rgb2rgb: Pointer to structure for RGB to RGB Blending.
++ * @prev_csc: Pointer to structure for Color Space Conversion from RGB-YCbYCr.
++ * @yclimit: Pointer to structure for Y, C Value Limit.
++ * @prev_dcor: Pointer to structure for defect correction.
++ */
++struct ispprv_update_config {
++	u16 update;
++	u16 flag;
++	void *yen;
++	u32 shading_shift;
++	struct ispprev_hmed *prev_hmed;
++	struct ispprev_cfa *prev_cfa;
++	struct ispprev_csup *csup;
++	struct ispprev_wbal *prev_wbal;
++	struct ispprev_blkadj *prev_blkadj;
++	struct ispprev_rgbtorgb *rgb2rgb;
++	struct ispprev_csc *prev_csc;
++	struct ispprev_yclimit *yclimit;
++	struct ispprev_dcor *prev_dcor;
++};
++
++/**
++ * struct isptables_update - Structure for Table Configuration.
++ * @update: Specifies which tables should be updated.
++ * @flag: Specifies which tables should be enabled.
++ * @lsc_cfg: Pointer to structure for LSC configuration.
++ * @prev_nf: Pointer to structure for Noise Filter
++ * @lsc: Pointer to LSC gain table. (currently not used)
++ * @red_gamma: Pointer to red gamma correction table.
++ * @green_gamma: Pointer to green gamma correction table.
++ * @blue_gamma: Pointer to blue gamma correction table.
++ */
++struct isptables_update {
++	u16 update;
++	u16 flag;
++	struct ispprev_nf *prev_nf;
++	u32 *lsc;
++	u32 *red_gamma;
++	u32 *green_gamma;
++	u32 *blue_gamma;
++};
++
++void isppreview_config_shadow_registers(void);
++
++#include <linux/autoconf.h>
++#ifdef CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER
++int isppreview_request(void);
++
++int isppreview_free(void);
++
++int isppreview_config_datapath(enum preview_input input,
++						enum preview_output output);
++
++void isppreview_config_ycpos(enum preview_ycpos_mode mode);
++
++void isppreview_set_color(u8 *mode);
++
++void isppreview_get_color(u8 *mode);
++
++void isppreview_query_contrast(u8 *contrast);
++
++void isppreview_query_brightness(u8 *brightness);
++
++int isppreview_try_size(u32 input_w, u32 input_h, u32 *output_w, u32 *output_h);
++
++int isppreview_config_size(u32 input_w, u32 input_h, u32 output_w,
++								u32 output_h);
++
++void isppreview_update_contrast(u8 *contrast);
++
++void isppreview_update_brightness(u8 *brightness);
++
++int isppreview_busy(void);
++
++void isppreview_save_context(void);
++
++void isppreview_restore_context(void);
++
++int omap34xx_isp_preview_config(void *userspace_add);
++
++int omap34xx_isp_tables_update(void *userspace_add);
++
++#else
++static inline int isppreview_request(void) { return 0;}
++static inline int isppreview_free(void) { return 0;}
++static inline int isppreview_config_datapath(enum preview_input input,
++					enum preview_output output) { return 0;}
++static inline void isppreview_config_ycpos(enum preview_ycpos_mode mode) {}
++static inline void isppreview_set_color(u8 *mode) {}
++static inline void isppreview_get_color(u8 *mode) {}
++static inline void isppreview_query_brightness(u8 *brightness) {}
++static inline void isppreview_query_contrast(u8 *contrast){}
++static inline int isppreview_try_size(u32 input_w, u32 input_h, u32 *output_w, u32 *output_h){ return 0;}
++static inline int isppreview_config_size(u32 input_w, u32 input_h, u32 output_w, u32 output_h) {return 0;}
++static inline void isppreview_update_contrast(u8 *contrast) {}
++static inline void isppreview_update_brightness(u8 *brightness) {}
++static inline int isppreview_busy(void){return 0;}
++static inline int omap34xx_isp_preview_config(void *userspace_add){return 0;}
++static inline int omap34xx_isp_tables_update(void *userspace_add){return 0;}
++static inline void isppreview_save_context(void) {}
++static inline void isppreview_restore_context(void) {}
++#endif
++
++void isppreview_config_averager(u8 average);
++
++void isppreview_enable_invalaw(u8 enable);
++
++void isppreview_enable_drkframe(u8 enable);
++
++void isppreview_enable_shadcomp(u8 enable);
++
++void isppreview_config_drkf_shadcomp(u8 scomp_shtval);
++
++void isppreview_enable_gammabypass(u8 enable);
++
++void isppreview_enable_hmed(u8 enable);
++
++void isppreview_config_hmed(struct ispprev_hmed);
++
++void isppreview_enable_noisefilter(u8 enable);
++
++void isppreview_config_noisefilter(struct ispprev_nf prev_nf);
++
++void isppreview_enable_dcor(u8 enable);
++
++void isppreview_config_dcor(struct ispprev_dcor prev_dcor);
++
++void isppreview_config_cfa(struct ispprev_cfa);
++
++void isppreview_config_gammacorrn(struct ispprev_gtable);
++
++void isppreview_config_chroma_suppression(struct ispprev_csup csup);
++
++void isppreview_enable_cfa(u8 enable);
++
++void isppreview_config_luma_enhancement(u32 *ytable);
++
++void isppreview_enable_luma_enhancement(u8 enable);
++
++void isppreview_enable_chroma_suppression(u8 enable);
++
++void isppreview_config_whitebalance(struct ispprev_wbal);
++
++void isppreview_config_blkadj(struct ispprev_blkadj);
++
++void isppreview_config_rgb_blending(struct ispprev_rgbtorgb);
++
++void isppreview_config_rgb_to_ycbcr(struct ispprev_csc);
++
++void isppreview_config_contrast(u8 contrast);
++
++void isppreview_get_contrast_range(u8 *min_contrast, u8 *max_contrast);
++
++void isppreview_config_brightness(u8 brightness);
++
++void isppreview_get_brightness_range(u8 *min_brightness, u8 *max_brightness);
++
++void isppreview_config_yc_range(struct ispprev_yclimit yclimit);
++
++int isppreview_config_inlineoffset(u32 offset);
++
++int isppreview_set_inaddr(u32 addr);
++
++int isppreview_config_outlineoffset(u32 offset);
++
++int isppreview_set_outaddr(u32 addr);
++
++int isppreview_config_darklineoffset(u32 offset);
++
++int isppreview_set_darkaddr(u32 addr);
++
++void isppreview_enable(u8 enable);
++
++struct prev_params *isppreview_get_config(void);
++
++void isppreview_print_status(void);
++
++#endif/* OMAP_ISP_PREVIEW_H */
+Index: git/drivers/media/video/isp/ispreg.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/ispreg.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,1225 @@
++/*
++ * drivers/media/video/omap/isp/ispreg.h
++ *
++ * Header file for all the ISP module in TI's OMAP3430 Camera ISP.
++ * It has the OMAP HW register definitions.
++ *
++ * Copyright (C) 2007 Texas Instruments.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef __ISPREG_H__
++#define __ISPREG_H__
++
++#if 0
++#define OMAP_ISPCTRL_DEBUG
++#define OMAP_ISPCCDC_DEBUG
++#define OMAP_ISPPREV_DEBUG
++#define OMAP_ISPRESZ_DEBUG
++#define OMAP_ISPMMU_DEBUG
++#define OMAP_ISPH3A_DEBUG
++#define OMAP_ISPHIST_DEBUG
++#endif
++
++#ifdef OMAP_ISPCTRL_DEBUG
++#define DPRINTK_ISPCTRL(format,...)\
++	printk("ISPCTRL: " format, ## __VA_ARGS__)
++#else
++#define DPRINTK_ISPCTRL(format, ...)
++#endif
++
++#ifdef OMAP_ISPCCDC_DEBUG
++#define DPRINTK_ISPCCDC(format, ...)\
++	printk("ISPCCDC: " format, ## __VA_ARGS__)
++#else
++#define DPRINTK_ISPCCDC(format, ...)
++#endif
++
++#ifdef OMAP_ISPPREV_DEBUG
++#define DPRINTK_ISPPREV(format, ...)\
++	printk("ISPPREV: " format, ## __VA_ARGS__)
++#else
++#define DPRINTK_ISPPREV(format, ...)
++#endif
++
++#ifdef OMAP_ISPRESZ_DEBUG
++#define DPRINTK_ISPRESZ(format, ...)\
++	printk("ISPRESZ: " format, ## __VA_ARGS__)
++#else
++#define DPRINTK_ISPRESZ(format, ...)
++#endif
++
++#ifdef OMAP_ISPMMU_DEBUG
++#define DPRINTK_ISPMMU(format, ...)\
++	printk("ISPMMU: " format, ## __VA_ARGS__)
++#else
++#define DPRINTK_ISPMMU(format, ...)
++#endif
++
++#ifdef OMAP_ISPH3A_DEBUG
++#define DPRINTK_ISPH3A(format, ...)\
++	printk("ISPH3A: " format, ## __VA_ARGS__)
++#else
++#define DPRINTK_ISPH3A(format, ...)
++#endif
++
++#ifdef OMAP_ISPHIST_DEBUG
++#define DPRINTK_ISPHIST(format, ...)\
++	printk("ISPHIST: " format, ## __VA_ARGS__)
++#else
++#define DPRINTK_ISPHIST(format, ...)
++#endif
++
++#define ISP_32B_BOUNDARY_BUF		0xFFFFFFE0
++#define ISP_32B_BOUNDARY_OFFSET	0x0000FFE0
++
++/*PRCM Clock definition*/
++
++#define CM_FCLKEN_CAM			0x48004f00
++#define CM_ICLKEN_CAM			0x48004f10
++#define CM_AUTOIDLE_CAM		0x48004f30
++#define CM_CLKSEL_CAM			0x48004f40
++#define CM_CLKEN_PLL			0x48004D00
++#define CM_CLKSEL2_PLL			0x48004D44
++#define CTRL_PADCONF_CAM_HS		0x4800210C
++#define CTRL_PADCONF_CAM_XCLKA	0x48002110
++#define CTRL_PADCONF_CAM_D1		0x48002118
++#define CTRL_PADCONF_CAM_D3		0x4800211C
++#define CTRL_PADCONF_CAM_D5		0x48002120
++
++#define CTRL_PADCONF_CAM_D7		0x48002124
++#define CTRL_PADCONF_CAM_D9		0x48002128
++#define CTRL_PADCONF_CAM_D11		0x4800212C
++
++#define CM_ICLKEN_CAM_EN		0x1
++#define CM_FCLKEN_CAM_EN		0x1
++
++#define CM_CAM_MCLK_HZ		216000000
++
++/* ISP Submodules offset */
++
++#define ISP_REG_BASE			0x480BC000
++#define ISP_REG_SIZE			0x00001600
++
++#define ISPCBUFF_REG_BASE		0x480BC100
++#define ISPCBUFF_REG(offset)		(ISPCBUFF_REG_BASE + (offset))
++
++#define ISPCCP2A_REG_OFFSET		0x00000200
++#define ISPCCP2A_REG_BASE		0x480BC200
++
++#define ISPCCP2B_REG_OFFSET		0x00000400
++#define ISPCCP2B_REG_BASE		0x480BC400
++
++#define ISPCCDC_REG_OFFSET		0x00000600
++#define ISPCCDC_REG_BASE		0x480BC600
++
++#define ISPSCMP_REG_OFFSET		0x00000800
++#define ISPSCMP_REG_BASE		0x480BC800
++
++#define ISPHIST_REG_OFFSET		0x00000A00
++#define ISPHIST_REG_BASE		0x480BCA00
++#define ISPHIST_REG(offset)		(ISPHIST_REG_BASE + (offset))
++
++#define ISPH3A_REG_OFFSET		0x00000C00
++#define ISPH3A_REG_BASE	   		0x480BCC00
++#define ISPH3A_REG(offset) 		(ISPH3A_REG_BASE + (offset))
++
++#define ISPPREVIEW_REG_OFFSET		0x00000E00
++#define ISPPREVIEW_REG_BASE		0x480BCE00
++
++#define ISPRESIZER_REG_OFFSET		0x00001000
++#define ISPRESIZER_REG_BASE		0x480BD000
++
++#define ISPSBL_REG_OFFSET		0x00001200
++#define ISPSBL_REG_BASE			0x480BD200
++
++#define ISPMMU_REG_OFFSET		0x00001400
++#define ISPMMU_REG_BASE		0x480BD400
++
++/* ISP module register offset */
++
++#define ISP_REVISION			0x480BC000
++#define ISP_SYSCONFIG			0x480BC004
++#define ISP_SYSSTATUS			0x480BC008
++#define ISP_IRQ0ENABLE			0x480BC00C
++#define ISP_IRQ0STATUS			0x480BC010
++#define ISP_IRQ1ENABLE			0x480BC014
++#define ISP_IRQ1STATUS			0x480BC018
++#define ISP_TCTRL_GRESET_LENGTH		0x480BC030
++#define ISP_TCTRL_PSTRB_REPLAY		0x480BC034
++#define ISP_CTRL				0x480BC040
++#define ISP_SECURE			0x480BC044
++#define ISP_TCTRL_CTRL			0x480BC050
++#define ISP_TCTRL_FRAME			0x480BC054
++#define ISP_TCTRL_PSTRB_DELAY		0x480BC058
++#define ISP_TCTRL_STRB_DELAY		0x480BC05C
++#define ISP_TCTRL_SHUT_DELAY		0x480BC060
++#define ISP_TCTRL_PSTRB_LENGTH		0x480BC064
++#define ISP_TCTRL_STRB_LENGTH		0x480BC068
++#define ISP_TCTRL_SHUT_LENGTH		0x480BC06C
++#define ISP_PING_PONG_ADDR		0x480BC070
++#define ISP_PING_PONG_MEM_RANGE	0x480BC074
++#define ISP_PING_PONG_BUF_SIZE		0x480BC078
++
++/* CSI1 receiver registers */
++
++#define ISP_CSIA_SYSCONFIG		0x480BC204
++#define ISP_CSIB_SYSCONFIG		0x480BC404
++
++/* ISP_CBUFF Registers */
++
++#define ISP_CBUFF_SYSCONFIG 		ISPCBUFF_REG(0x010)
++#define ISP_CBUFF_IRQENABLE 		ISPCBUFF_REG(0x01C)
++
++#define ISP_CBUFF0_CTRL 		ISPCBUFF_REG(0x020)
++#define ISP_CBUFF1_CTRL 		(ISP_CBUFF0_CTRL + (0x004))
++
++#define ISP_CBUFF0_START 		ISPCBUFF_REG(0x040)
++#define ISP_CBUFF1_START 		(ISP_CBUFF0_START + (0x004))
++
++#define ISP_CBUFF0_END 			ISPCBUFF_REG(0x050)
++#define ISP_CBUFF1_END 			(ISP_CBUFF0_END + (0x04))
++
++#define ISP_CBUFF0_WINDOWSIZE 		ISPCBUFF_REG(0x060)
++#define ISP_CBUFF1_WINDOWSIZE 		(ISP_CBUFF0_WINDOWSIZE + (0x004))
++
++#define ISP_CBUFF0_THRESHOLD 		ISPCBUFF_REG(0x070)
++#define ISP_CBUFF1_THRESHOLD 		(ISP_CBUFF0_THRESHOLD + (0x004))
++
++
++/* CCDC module register offset */
++
++#define ISPCCDC_PID			0x480BC600
++#define ISPCCDC_PCR			0x480BC604
++#define ISPCCDC_SYN_MODE		0x480BC608
++#define ISPCCDC_HD_VD_WID		0x480BC60C
++#define ISPCCDC_PIX_LINES		0x480BC610
++#define ISPCCDC_HORZ_INFO		0x480BC614
++#define ISPCCDC_VERT_START		0x480BC618
++#define ISPCCDC_VERT_LINES		0x480BC61C
++#define ISPCCDC_CULLING			0x480BC620
++#define ISPCCDC_HSIZE_OFF		0x480BC624
++#define ISPCCDC_SDOFST			0x480BC628
++#define ISPCCDC_SDR_ADDR		0x480BC62C
++#define ISPCCDC_CLAMP			0x480BC630
++#define ISPCCDC_DCSUB			0x480BC634
++#define ISPCCDC_COLPTN			0x480BC638
++#define ISPCCDC_BLKCMP			0x480BC63C
++#define ISPCCDC_FPC			0x480BC640
++#define ISPCCDC_FPC_ADDR		0x480BC644
++#define ISPCCDC_VDINT			0x480BC648
++#define ISPCCDC_ALAW			0x480BC64C
++#define ISPCCDC_REC656IF		0x480BC650
++#define ISPCCDC_CFG			0x480BC654
++#define ISPCCDC_FMTCFG			0x480BC658
++#define ISPCCDC_FMT_HORZ		0x480BC65C
++#define ISPCCDC_FMT_VERT		0x480BC660
++#define ISPCCDC_FMT_ADDR0		0x480BC664
++#define ISPCCDC_FMT_ADDR1		0x480BC668
++#define ISPCCDC_FMT_ADDR2		0x480BC66C
++#define ISPCCDC_FMT_ADDR3		0x480BC670
++#define ISPCCDC_FMT_ADDR4		0x480BC674
++#define ISPCCDC_FMT_ADDR5		0x480BC678
++#define ISPCCDC_FMT_ADDR6		0x480BC67C
++#define ISPCCDC_FMT_ADDR7		0x480BC680
++#define ISPCCDC_PRGEVEN0		0x480BC684
++#define ISPCCDC_PRGEVEN1		0x480BC688
++#define ISPCCDC_PRGODD0		0x480BC68C
++#define ISPCCDC_PRGODD1		0x480BC690
++#define ISPCCDC_VP_OUT			0x480BC694
++
++#define ISPCCDC_LSC_CONFIG		0x480BC698
++#define ISPCCDC_LSC_INITIAL 		0x480BC69C
++#define ISPCCDC_LSC_TABLE_BASE		0x480BC6A0
++#define ISPCCDC_LSC_TABLE_OFFSET	0x480BC6A4
++
++
++/* Histogram registers */
++#define ISPHIST_PID           ISPHIST_REG(0x000)
++#define ISPHIST_PCR           ISPHIST_REG(0x004)
++#define ISPHIST_CNT           ISPHIST_REG(0x008)
++#define ISPHIST_WB_GAIN	   		ISPHIST_REG(0x00C)
++#define ISPHIST_R0_HORZ       ISPHIST_REG(0x010)
++#define ISPHIST_R0_VERT       ISPHIST_REG(0x014)
++#define ISPHIST_R1_HORZ       ISPHIST_REG(0x018)
++#define ISPHIST_R1_VERT       ISPHIST_REG(0x01C)
++#define ISPHIST_R2_HORZ       ISPHIST_REG(0x020)
++#define ISPHIST_R2_VERT       ISPHIST_REG(0x024)
++#define ISPHIST_R3_HORZ       ISPHIST_REG(0x028)
++#define ISPHIST_R3_VERT       ISPHIST_REG(0x02C)
++#define ISPHIST_ADDR          ISPHIST_REG(0x030)
++#define ISPHIST_DATA          ISPHIST_REG(0x034)
++#define ISPHIST_RADD          ISPHIST_REG(0x038)
++#define ISPHIST_RADD_OFF      ISPHIST_REG(0x03C)
++#define ISPHIST_H_V_INFO      ISPHIST_REG(0x040)
++
++/* H3A module registers */
++#define ISPH3A_PID         		ISPH3A_REG(0x000)
++#define ISPH3A_PCR         		ISPH3A_REG(0x004)
++#define ISPH3A_AEWWIN1    		ISPH3A_REG(0x04C)
++#define ISPH3A_AEWINSTART 		ISPH3A_REG(0x050)
++#define ISPH3A_AEWINBLK   		ISPH3A_REG(0x054)
++#define ISPH3A_AEWSUBWIN  		ISPH3A_REG(0x058)
++#define ISPH3A_AEWBUFST   		ISPH3A_REG(0x05C)
++#define ISPH3A_AFPAX1			ISPH3A_REG(0x008)
++#define ISPH3A_AFPAX2 			ISPH3A_REG(0x00C)
++#define ISPH3A_AFPAXSTART		ISPH3A_REG(0x010)
++#define ISPH3A_AFIIRSH 			ISPH3A_REG(0x014)
++#define ISPH3A_AFBUFST 			ISPH3A_REG(0x018)
++#define ISPH3A_AFCOEF010 		ISPH3A_REG(0x01C)
++#define ISPH3A_AFCOEF032 		ISPH3A_REG(0x020)
++#define ISPH3A_AFCOEF054 		ISPH3A_REG(0x024)
++#define ISPH3A_AFCOEF076 		ISPH3A_REG(0x028)
++#define ISPH3A_AFCOEF098 		ISPH3A_REG(0x02C)
++#define ISPH3A_AFCOEF0010		ISPH3A_REG(0x030)
++#define ISPH3A_AFCOEF110 		ISPH3A_REG(0x034)
++#define ISPH3A_AFCOEF132 		ISPH3A_REG(0x038)
++#define ISPH3A_AFCOEF154 		ISPH3A_REG(0x03C)
++#define ISPH3A_AFCOEF176 		ISPH3A_REG(0x040)
++#define ISPH3A_AFCOEF198 		ISPH3A_REG(0x044)
++#define ISPH3A_AFCOEF1010		ISPH3A_REG(0x048)
++
++
++
++
++#define ISPPRV_PCR			0x480BCE04
++#define ISPPRV_HORZ_INFO		0x480BCE08
++#define ISPPRV_VERT_INFO		0x480BCE0C
++#define ISPPRV_RSDR_ADDR		0x480BCE10
++#define ISPPRV_RADR_OFFSET		0x480BCE14
++#define ISPPRV_DSDR_ADDR		0x480BCE18
++#define ISPPRV_DRKF_OFFSET		0x480BCE1C
++#define ISPPRV_WSDR_ADDR		0x480BCE20
++#define ISPPRV_WADD_OFFSET		0x480BCE24
++#define ISPPRV_AVE			0x480BCE28
++#define ISPPRV_HMED			0x480BCE2C
++#define ISPPRV_NF			0x480BCE30
++#define ISPPRV_WB_DGAIN		0x480BCE34
++#define ISPPRV_WBGAIN			0x480BCE38
++#define ISPPRV_WBSEL			0x480BCE3C
++#define ISPPRV_CFA			0x480BCE40
++#define ISPPRV_BLKADJOFF		0x480BCE44
++#define ISPPRV_RGB_MAT1		0x480BCE48
++#define ISPPRV_RGB_MAT2		0x480BCE4C
++#define ISPPRV_RGB_MAT3		0x480BCE50
++#define ISPPRV_RGB_MAT4		0x480BCE54
++#define ISPPRV_RGB_MAT5		0x480BCE58
++#define ISPPRV_RGB_OFF1		0x480BCE5C
++#define ISPPRV_RGB_OFF2		0x480BCE60
++#define ISPPRV_CSC0			0x480BCE64
++#define ISPPRV_CSC1			0x480BCE68
++#define ISPPRV_CSC2			0x480BCE6C
++#define ISPPRV_CSC_OFFSET		0x480BCE70
++#define ISPPRV_CNT_BRT			0x480BCE74
++#define ISPPRV_CSUP			0x480BCE78
++#define ISPPRV_SETUP_YC			0x480BCE7C
++#define ISPPRV_SET_TBL_ADDR		0x480BCE80
++#define ISPPRV_SET_TBL_DATA		0x480BCE84
++#define ISPPRV_CDC_THR0			0x480BCE90
++#define ISPPRV_CDC_THR1			(ISPPRV_CDC_THR0 + (0x4))
++#define ISPPRV_CDC_THR2			(ISPPRV_CDC_THR0 + (0x4)*2)
++#define ISPPRV_CDC_THR3			(ISPPRV_CDC_THR0 + (0x4)*3)
++
++#define ISPPRV_REDGAMMA_TABLE_ADDR	0x0000
++#define ISPPRV_GREENGAMMA_TABLE_ADDR	0x0400
++#define ISPPRV_BLUEGAMMA_TABLE_ADDR	0x0800
++#define ISPPRV_NF_TABLE_ADDR		0x0C00
++#define ISPPRV_YENH_TABLE_ADDR		0x1000
++#define ISPPRV_CFA_TABLE_ADDR		0x1400
++
++#define ISPPRV_MAXOUTPUT_WIDTH		1280
++#define ISPPRV_MAXOUTPUT_WIDTH_ES2	3300
++
++/* Resizer module register offset */
++
++#define ISPRSZ_PID			0x480BD000
++#define ISPRSZ_PCR			0x480BD004
++#define ISPRSZ_CNT			0x480BD008
++#define ISPRSZ_OUT_SIZE			0x480BD00C
++#define ISPRSZ_IN_START		   	0x480BD010
++#define ISPRSZ_IN_SIZE			0x480BD014
++#define ISPRSZ_SDR_INADD		0x480BD018
++#define ISPRSZ_SDR_INOFF		0x480BD01C
++#define ISPRSZ_SDR_OUTADD		0x480BD020
++#define ISPRSZ_SDR_OUTOFF		0x480BD024
++#define ISPRSZ_HFILT10			0x480BD028
++#define ISPRSZ_HFILT32			0x480BD02C
++#define ISPRSZ_HFILT54			0x480BD030
++#define ISPRSZ_HFILT76			0x480BD034
++#define ISPRSZ_HFILT98			0x480BD038
++#define ISPRSZ_HFILT1110		0x480BD03C
++#define ISPRSZ_HFILT1312		0x480BD040
++#define ISPRSZ_HFILT1514		0x480BD044
++#define ISPRSZ_HFILT1716		0x480BD048
++#define ISPRSZ_HFILT1918		0x480BD04C
++#define ISPRSZ_HFILT2120		0x480BD050
++#define ISPRSZ_HFILT2322		0x480BD054
++#define ISPRSZ_HFILT2524		0x480BD058
++#define ISPRSZ_HFILT2726		0x480BD05C
++#define ISPRSZ_HFILT2928		0x480BD060
++#define ISPRSZ_HFILT3130		0x480BD064
++#define ISPRSZ_VFILT10			0x480BD068
++#define ISPRSZ_VFILT32			0x480BD06C
++#define ISPRSZ_VFILT54			0x480BD070
++#define ISPRSZ_VFILT76			0x480BD074
++#define ISPRSZ_VFILT98			0x480BD078
++#define ISPRSZ_VFILT1110		0x480BD07C
++#define ISPRSZ_VFILT1312		0x480BD080
++#define ISPRSZ_VFILT1514		0x480BD084
++#define ISPRSZ_VFILT1716		0x480BD088
++#define ISPRSZ_VFILT1918		0x480BD08C
++#define ISPRSZ_VFILT2120		0x480BD090
++#define ISPRSZ_VFILT2322		0x480BD094
++#define ISPRSZ_VFILT2524		0x480BD098
++#define ISPRSZ_VFILT2726		0x480BD09C
++#define ISPRSZ_VFILT2928		0x480BD0A0
++#define ISPRSZ_VFILT3130		0x480BD0A4
++#define ISPRSZ_YENH			0x480BD0A8
++
++
++/* MMU module registers */
++#define ISPMMU_REVISION		0x480BD400
++#define ISPMMU_SYSCONFIG		0x480BD410
++#define ISPMMU_SYSSTATUS		0x480BD414
++#define ISPMMU_IRQSTATUS		0x480BD418
++#define ISPMMU_IRQENABLE		0x480BD41C
++#define ISPMMU_WALKING_ST		0x480BD440
++#define ISPMMU_CNTL			0x480BD444
++#define ISPMMU_FAULT_AD		0x480BD448
++#define ISPMMU_TTB			0x480BD44C
++#define ISPMMU_LOCK			0x480BD450
++#define ISPMMU_LD_TLB			0x480BD454
++#define ISPMMU_CAM			0x480BD458
++#define ISPMMU_RAM			0x480BD45C
++#define ISPMMU_GFLUSH			0x480BD460
++#define ISPMMU_FLUSH_ENTRY		0x480BD464
++#define ISPMMU_READ_CAM		0x480BD468
++#define ISPMMU_READ_RAM		0x480BD46c
++#define ISPMMU_EMU_FAULT_AD		0x480BD470
++
++
++#define ISP_INT_CLR                     0xFF113F11
++#define ISPPRV_PCR_EN			1
++#define ISPPRV_PCR_BUSY		(1<<1)
++#define ISPPRV_PCR_SOURCE		(1<<2)
++#define ISPPRV_PCR_ONESHOT		(1<<3)
++#define ISPPRV_PCR_WIDTH		(1<<4)
++#define ISPPRV_PCR_INVALAW		(1<<5)
++#define ISPPRV_PCR_DRKFEN		(1<<6)
++#define ISPPRV_PCR_DRKFCAP		(1<<7)
++#define ISPPRV_PCR_HMEDEN		(1<<8)
++#define ISPPRV_PCR_NFEN			(1<<9)
++#define ISPPRV_PCR_CFAEN		(1<<10)
++#define ISPPRV_PCR_CFAFMT_SHIFT	11
++#define ISPPRV_PCR_CFAFMT_MASK	0x7800
++#define ISPPRV_PCR_CFAFMT_BAYER	(0<<11)
++#define ISPPRV_PCR_CFAFMT_SONYVGA	(1<<11)
++#define ISPPRV_PCR_CFAFMT_RGBFOVEON	(2<<11)
++#define ISPPRV_PCR_CFAFMT_DNSPL	(3<<11)
++#define ISPPRV_PCR_CFAFMT_HONEYCOMB	(4<<11)
++#define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON	(5<<11)
++#define ISPPRV_PCR_YNENHEN		(1<<15)
++#define ISPPRV_PCR_SUPEN		(1<<16)
++#define ISPPRV_PCR_YCPOS_SHIFT		17
++#define ISPPRV_PCR_YCPOS_YCrYCb	(0<<17)
++#define ISPPRV_PCR_YCPOS_YCbYCr	(1<<17)
++#define ISPPRV_PCR_YCPOS_CbYCrY	(2<<17)
++#define ISPPRV_PCR_YCPOS_CrYCbY	(3<<17)
++#define ISPPRV_PCR_RSZPORT		(1<<19)
++#define ISPPRV_PCR_SDRPORT		(1<<20)
++#define ISPPRV_PCR_SCOMP_EN		(1<<21)
++#define ISPPRV_PCR_SCOMP_SFT_SHIFT	(22)
++#define ISPPRV_PCR_SCOMP_SFT_MASK	~(7<<22)
++#define ISPPRV_PCR_GAMMA_BYPASS	(1<<26)
++#define ISPPRV_PCR_DCOREN		(1<<27)
++#define ISPPRV_PCR_DCCOUP		(1<<28)
++#define ISPPRV_PCR_DRK_FAIL		(1<<31)
++
++#define ISPPRV_HORZ_INFO_EPH_SHIFT	0
++#define ISPPRV_HORZ_INFO_EPH_MASK	0x3fff;
++#define ISPPRV_HORZ_INFO_SPH_SHIFT	16
++#define ISPPRV_HORZ_INFO_SPH_MASK	0x3fff0
++
++#define ISPPRV_VERT_INFO_ELV_SHIFT	0
++#define ISPPRV_VERT_INFO_ELV_MASK	0x3fff
++#define ISPPRV_VERT_INFO_SLV_SHIFT	16
++#define ISPPRV_VERT_INFO_SLV_MASK	0x3fff0
++
++#define ISPPRV_AVE_EVENDIST_SHIFT	2
++#define ISPPRV_AVE_EVENDIST_1	 	0x0
++#define ISPPRV_AVE_EVENDIST_2		 0x1
++#define ISPPRV_AVE_EVENDIST_3		0x2
++#define ISPPRV_AVE_EVENDIST_4		0x3
++#define ISPPRV_AVE_ODDDIST_SHIFT	4
++#define ISPPRV_AVE_ODDDIST_1		0x0
++#define ISPPRV_AVE_ODDDIST_2		0x1
++#define ISPPRV_AVE_ODDDIST_3		0x2
++#define ISPPRV_AVE_ODDDIST_4		0x3
++
++#define ISPPRV_HMED_THRESHOLD_SHIFT	0
++#define ISPPRV_HMED_EVENDIST		(1<<8)
++#define ISPPRV_HMED_ODDDIST		(1<<9)
++
++#define ISPPRV_WBGAIN_COEF0_SHIFT	0
++#define ISPPRV_WBGAIN_COEF1_SHIFT	8
++#define ISPPRV_WBGAIN_COEF2_SHIFT	16
++#define ISPPRV_WBGAIN_COEF3_SHIFT	24
++
++#define ISPPRV_WBSEL_COEF0		0x0
++#define ISPPRV_WBSEL_COEF1		0x1
++#define ISPPRV_WBSEL_COEF2		0x2
++#define ISPPRV_WBSEL_COEF3		0x3
++
++#define ISPPRV_WBSEL_N0_0_SHIFT	0
++#define ISPPRV_WBSEL_N0_1_SHIFT	2
++#define ISPPRV_WBSEL_N0_2_SHIFT	4
++#define ISPPRV_WBSEL_N0_3_SHIFT	6
++#define ISPPRV_WBSEL_N1_0_SHIFT	8
++#define ISPPRV_WBSEL_N1_1_SHIFT	10
++#define ISPPRV_WBSEL_N1_2_SHIFT	12
++#define ISPPRV_WBSEL_N1_3_SHIFT	14
++#define ISPPRV_WBSEL_N2_0_SHIFT	16
++#define ISPPRV_WBSEL_N2_1_SHIFT	18
++#define ISPPRV_WBSEL_N2_2_SHIFT	20
++#define ISPPRV_WBSEL_N2_3_SHIFT	22
++#define ISPPRV_WBSEL_N3_0_SHIFT	24
++#define ISPPRV_WBSEL_N3_1_SHIFT	26
++#define ISPPRV_WBSEL_N3_2_SHIFT	28
++#define ISPPRV_WBSEL_N3_3_SHIFT	30
++
++#define ISPPRV_CFA_GRADTH_HOR_SHIFT	0
++#define ISPPRV_CFA_GRADTH_VER_SHIFT	8
++
++#define ISPPRV_BLKADJOFF_B_SHIFT	0
++#define ISPPRV_BLKADJOFF_G_SHIFT	8
++#define ISPPRV_BLKADJOFF_R_SHIFT	16
++
++#define ISPPRV_RGB_MAT1_MTX_RR_SHIFT	0
++#define ISPPRV_RGB_MAT1_MTX_GR_SHIFT	16
++
++#define ISPPRV_RGB_MAT2_MTX_BR_SHIFT	0
++#define ISPPRV_RGB_MAT2_MTX_RG_SHIFT	16
++
++#define ISPPRV_RGB_MAT3_MTX_GG_SHIFT	0
++#define ISPPRV_RGB_MAT3_MTX_BG_SHIFT	16
++
++#define ISPPRV_RGB_MAT4_MTX_RB_SHIFT	0
++#define ISPPRV_RGB_MAT4_MTX_GB_SHIFT	16
++
++#define ISPPRV_RGB_MAT5_MTX_BB_SHIFT	0
++
++#define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT	0
++#define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT	16
++
++#define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT	0
++
++#define ISPPRV_CSC0_RY_SHIFT		0
++#define ISPPRV_CSC0_GY_SHIFT		10
++#define ISPPRV_CSC0_BY_SHIFT		20
++
++#define ISPPRV_CSC1_RCB_SHIFT	 	0
++#define ISPPRV_CSC1_GCB_SHIFT	 	10
++#define ISPPRV_CSC1_BCB_SHIFT	 	20
++
++#define ISPPRV_CSC2_RCR_SHIFT	 	0
++#define ISPPRV_CSC2_GCR_SHIFT	 	10
++#define ISPPRV_CSC2_BCR_SHIFT	 	20
++
++#define ISPPRV_CSC_OFFSET_CR_SHIFT	0
++#define ISPPRV_CSC_OFFSET_CB_SHIFT	8
++#define ISPPRV_CSC_OFFSET_Y_SHIFT	16
++
++#define ISPPRV_CNT_BRT_BRT_SHIFT	0
++#define ISPPRV_CNT_BRT_CNT_SHIFT	8
++
++#define ISPPRV_CONTRAST_MAX		0x10
++#define ISPPRV_CONTRAST_MIN		0xFF
++#define ISPPRV_BRIGHT_MIN		0x00
++#define ISPPRV_BRIGHT_MAX		0xFF
++
++
++#define ISPPRV_CSUP_CSUPG_SHIFT	0
++#define ISPPRV_CSUP_THRES_SHIFT	8
++#define ISPPRV_CSUP_HPYF_SHIFT		16
++
++#define ISPPRV_SETUP_YC_MINC_SHIFT	0
++#define ISPPRV_SETUP_YC_MAXC_SHIFT	8
++#define ISPPRV_SETUP_YC_MINY_SHIFT	16
++#define ISPPRV_SETUP_YC_MAXY_SHIFT	24
++#define ISPPRV_YC_MAX			0xFF
++#define ISPPRV_YC_MIN			0x0
++
++
++
++
++/* Define bit fields within selected registers */
++
++#define ISP_REVISION_SHIFT		0
++
++#define ISP_SYSCONFIG_AUTOIDLE		0
++#define ISP_SYSCONFIG_SOFTRESET	(1<<1)
++#define ISP_SYSCONFIG_MIdleMode_SHIFT	12
++#define ISP_SYSCONFIG_MIdleMode_ForceStandBy	0x0
++#define ISP_SYSCONFIG_MIdleMode_NoStandBy	0x1
++#define ISP_SYSCONFIG_MIdleMode_SmartStandBy	0x2
++
++#define ISP_SYSSTATUS_ResetDone		0
++
++#define IRQ0ENABLE_CSIA_IRQ			1
++#define IRQ0ENABLE_CSIA_LC1_IRQ		(1<<1)
++#define IRQ0ENABLE_CSIA_LC2_IRQ		(1<<2)
++#define IRQ0ENABLE_CSIA_LC3_IRQ		(1<<3)
++#define IRQ0ENABLE_CSIB_IRQ			(1<<4)
++#define IRQ0ENABLE_CSIB_LC1_IRQ		(1<<5)
++#define IRQ0ENABLE_CSIB_LC2_IRQ		(1<<6)
++#define IRQ0ENABLE_CSIB_LC3_IRQ		(1<<7)
++#define IRQ0ENABLE_CCDC_VD0_IRQ		(1<<8)
++#define IRQ0ENABLE_CCDC_VD1_IRQ		(1<<9)
++#define IRQ0ENABLE_CCDC_VD2_IRQ		(1<<10)
++#define IRQ0ENABLE_CCDC_ERR_IRQ		(1<<11)
++#define IRQ0ENABLE_H3A_AF_DONE_IRQ		(1<<12)
++#define IRQ0ENABLE_H3A_AWB_DONE_IRQ		(1<<13)
++#define IRQ0ENABLE_HIST_DONE_IRQ		(1<<16)
++#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ		(1<<17)
++#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ		(1<<18)
++#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ		(1<<19)
++#define IRQ0ENABLE_PRV_DONE_IRQ		(1<<20)
++#define IRQ0ENABLE_RSZ_DONE_IRQ		(1<<24)
++#define IRQ0ENABLE_OVF_IRQ			(1<<25)
++#define IRQ0ENABLE_PING_IRQ			(1<<26)
++#define IRQ0ENABLE_PONG_IRQ			(1<<27)
++#define IRQ0ENABLE_MMU_ERR_IRQ		(1<<28)
++#define IRQ0ENABLE_OCP_ERR_IRQ		(1<<29)
++#define IRQ0ENABLE_SEC_ERR_IRQ			(1<<30)
++#define IRQ0ENABLE_HS_VS_IRQ			(1<<31)
++
++#define IRQ0STATUS_CSIA_IRQ			1
++#define IRQ0STATUS_CSIA_LC1_IRQ		(1<<1)
++#define IRQ0STATUS_CSIA_LC2_IRQ		(1<<2)
++#define IRQ0STATUS_CSIA_LC3_IRQ		(1<<3)
++#define IRQ0STATUS_CSIB_IRQ			(1<<4)
++#define IRQ0STATUS_CSIB_LC1_IRQ		(1<<5)
++#define IRQ0STATUS_CSIB_LC2_IRQ		(1<<6)
++#define IRQ0STATUS_CSIB_LC3_IRQ		(1<<7)
++#define IRQ0STATUS_CCDC_VD0_IRQ		(1<<8)
++#define IRQ0STATUS_CCDC_VD1_IRQ		(1<<9)
++#define IRQ0STATUS_CCDC_VD2_IRQ		(1<<10)
++#define IRQ0STATUS_CCDC_ERR_IRQ		(1<<11)
++#define IRQ0STATUS_H3A_AF_DONE_IRQ		(1<<12)
++#define IRQ0STATUS_H3A_AWB_DONE_IRQ		(1<<13)
++#define IRQ0STATUS_HIST_DONE_IRQ		(1<<16)
++#define IRQ0STATUS_PRV_DONE_IRQ		(1<<20)
++#define IRQ0STATUS_RSZ_DONE_IRQ		(1<<24)
++#define IRQ0STATUS_OVF_IRQ			(1<<25)
++#define IRQ0STATUS_PING_IRQ			(1<<26)
++#define IRQ0STATUS_PONG_IRQ			(1<<27)
++#define IRQ0STATUS_MMU_ERR_IRQ		(1<<28)
++#define IRQ0STATUS_OCP_ERR_IRQ			(1<<29)
++#define IRQ0STATUS_SEC_ERR_IRQ			(1<<30)
++#define IRQ0STATUS_HS_VS_IRQ			(1<<31)
++
++#define TCTRL_GRESET_LEN			0
++
++#define TCTRL_PSTRB_REPLAY_DELAY		0
++#define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT	25
++
++#define ISPCTRL_PAR_SER_CLK_SEL_parallel	0x0
++#define ISPCTRL_PAR_SER_CLK_SEL_CSIA		0x1
++#define ISPCTRL_PAR_SER_CLK_SEL_CSIB		0x2
++#define ISPCTRL_PAR_SER_CLK_SEL_MASK		0xFFFFFFFC
++
++#define ISPCTRL_PAR_BRIDGE_SHIFT	2
++#define ISPCTRL_PAR_BRIDGE_DISABLE	(0x0 << 2)
++#define ISPCTRL_PAR_BRIDGE_LENDIAN	(0x2 << 2)
++#define ISPCTRL_PAR_BRIDGE_BENDIAN	(0x3 << 2)
++
++#define ISPCTRL_PAR_CLK_POL_SHIFT	4
++#define ISPCTRL_PAR_CLK_POL_INV	(1 << 4)
++#define ISPCTRL_PING_PONG_EN		(1 << 5)
++#define ISPCTRL_SHIFT_SHIFT		6
++#define ISPCTRL_SHIFT_0			(0x0 << 6)
++#define ISPCTRL_SHIFT_2			(0x1 << 6)
++#define ISPCTRL_SHIFT_4			(0x2 << 6)
++#define ISPCTRL_SHIFT_MASK		(~(0x3 << 6))
++
++#define ISPCTRL_CCDC_CLK_EN		(1 << 8)
++#define ISPCTRL_SCMP_CLK_EN		(1 << 9)
++#define ISPCTRL_H3A_CLK_EN		(1 << 10)
++#define ISPCTRL_HIST_CLK_EN		(1 << 11)
++#define ISPCTRL_PREV_CLK_EN		(1 << 12)
++#define ISPCTRL_RSZ_CLK_EN		(1 << 13)
++#define ISPCTRL_SYNC_DETECT_SHIFT	14
++#define ISPCTRL_SYNC_DETECT_HSFALL	0x0
++#define ISPCTRL_SYNC_DETECT_HSRISE	0x1
++#define ISPCTRL_SYNC_DETECT_VSFALL	0x2
++#define ISPCTRL_SYNC_DETECT_VSRISE	0x3
++
++#define ISPCTRL_CCDC_RAM_EN		(1 << 16)
++#define ISPCTRL_PREV_RAM_EN		(1 << 17)
++#define ISPCTRL_SBL_RD_RAM_EN		(1 << 18)
++#define ISPCTRL_SBL_WR1_RAM_EN	(1 << 19)
++#define ISPCTRL_SBL_WR0_RAM_EN	(1 << 20)
++#define ISPCTRL_SBL_AutoIdle		(1 << 21)
++#define ISPCTRL_SBL_SHARED_RPORTB	(1 << 28)
++#define ISPCTRL_JPEG_FLUSH		(1 << 30)
++#define ISPCTRL_CCDC_FLUSH		(1 << 31)
++
++#define ISPSECURE_SecureMode		0
++
++#define ISPTCTRL_CTRL_DIVA_SHIFT	0
++#define ISPTCTRL_CTRL_DIVA_MASK		(0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
++#define ISPTCTRL_CTRL_DIVA_Low		0x0
++#define ISPTCTRL_CTRL_DIVA_High	 	0x1
++#define ISPTCTRL_CTRL_DIVA_Bypass	0x1F
++
++#define ISPTCTRL_CTRL_DIVB_SHIFT	5
++#define ISPTCTRL_CTRL_DIVB_MASK		(0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
++#define ISPTCTRL_CTRL_DIVB_Low		(0x0 << 5)
++#define ISPTCTRL_CTRL_DIVB_High		(0x1 << 5)
++#define ISPTCTRL_CTRL_DIVB_Bypass	(0x1F << 5)
++
++#define ISPTCTRL_CTRL_DIVC_SHIFT	10
++#define ISPTCTRL_CTRL_DIVC_NoClock	(0x0 << 10)
++
++#define ISPTCTRL_CTRL_SHUTEN		(1 << 21)
++#define ISPTCTRL_CTRL_PSTRBEN		(1 << 22)
++#define ISPTCTRL_CTRL_STRBEN		(1 << 23)
++#define ISPTCTRL_CTRL_SHUTPOL		(1 << 24)
++#define ISPTCTRL_CTRL_STRBPSTRBPOL	(1 << 26)
++
++#define ISPTCTRL_CTRL_INSEL_SHIFT	27
++#define ISPTCTRL_CTRL_INSEL_Parallel	(0x0 << 27)
++#define ISPTCTRL_CTRL_INSEL_CSIA 	(0x1 << 27)
++#define ISPTCTRL_CTRL_INSEL_CSIB 	(0x2 << 27)
++
++#define ISPTCTRL_CTRL_GRESETEn		(1 << 29)
++#define ISPTCTRL_CTRL_GRESETPOL	(1 << 30)
++#define ISPTCTRL_CTRL_GRESETDIR		(1 << 31)
++
++#define ISPTCTRL_FRAME_SHUT_SHIFT	0
++#define ISPTCTRL_FRAME_PSTRB_SHIFT	6
++#define ISPTCTRL_FRAME_STRB_SHIFT	12
++
++#define ISPCCDC_PID_PREV_SHIFT	 	0
++#define ISPCCDC_PID_CID_SHIFT		8
++#define ISPCCDC_PID_TID_SHIFT		16
++
++#define ISPCCDC_PCR_EN			1
++#define ISPCCDC_PCR_BUSY		(1 << 1)
++
++#define ISPCCDC_SYN_MODE_VDHDOUT	0x1
++#define ISPCCDC_SYN_MODE_FLDOUT	(1 << 1)
++#define ISPCCDC_SYN_MODE_VDPOL	(1 << 2)
++#define ISPCCDC_SYN_MODE_HDPOL	(1 << 3)
++#define ISPCCDC_SYN_MODE_FLDPOL	(1 << 4)
++#define ISPCCDC_SYN_MODE_EXWEN	(1 << 5)
++#define ISPCCDC_SYN_MODE_DATAPOL  	(1 << 6)
++#define ISPCCDC_SYN_MODE_FLDMODE	(1 << 7)
++#define ISPCCDC_SYN_MODE_DATSIZ_MASK	  0xFFFFF8FF
++#define ISPCCDC_SYN_MODE_DATSIZ_8_16 	(0x0 << 8)
++#define ISPCCDC_SYN_MODE_DATSIZ_12	(0x4 << 8)
++#define ISPCCDC_SYN_MODE_DATSIZ_11	(0x5 << 8)
++#define ISPCCDC_SYN_MODE_DATSIZ_10	(0x6 << 8)
++#define ISPCCDC_SYN_MODE_DATSIZ_8	(0x7 << 8)
++#define ISPCCDC_SYN_MODE_PACK8	(1 << 11)
++#define ISPCCDC_SYN_MODE_INPMOD_MASK	0xFFFFCFFF
++#define ISPCCDC_SYN_MODE_INPMOD_RAW		(0 << 12)
++#define ISPCCDC_SYN_MODE_INPMOD_YCBCR16	(1 << 12)
++#define ISPCCDC_SYN_MODE_INPMOD_YCBCR8	(2 << 12)
++#define ISPCCDC_SYN_MODE_LPF			(1 << 14)
++#define ISPCCDC_SYN_MODE_FLDSTAT		(1 << 15)
++#define ISPCCDC_SYN_MODE_VDHDEN		(1 << 16)
++#define ISPCCDC_SYN_MODE_WEN			(1 << 17)
++#define ISPCCDC_SYN_MODE_VP2SDR		(1 << 18)
++#define ISPCCDC_SYN_MODE_SDR2RSZ		(1 << 19)
++
++#define ISPCCDC_HD_VD_WID_VDW_SHIFT		0
++#define ISPCCDC_HD_VD_WID_HDW_SHIFT		16
++
++#define ISPCCDC_PIX_LINES_HLPRF_SHIFT		0
++#define ISPCCDC_PIX_LINES_PPLN_SHIFT		16
++
++#define ISPCCDC_HORZ_INFO_NPH_SHIFT		0
++#define ISPCCDC_HORZ_INFO_NPH_MASK		0xFFFF8000
++#define ISPCCDC_HORZ_INFO_SPH_MASK		0x1000FFFF
++#define ISPCCDC_HORZ_INFO_SPH_SHIFT		16
++
++#define ISPCCDC_VERT_START_SLV0_SHIFT		16
++#define ISPCCDC_VERT_START_SLV0_MASK		0x1000FFFF
++#define ISPCCDC_VERT_START_SLV1_SHIFT		0
++
++#define ISPCCDC_VERT_LINES_NLV_MASK		0xFFFF8000
++#define ISPCCDC_VERT_LINES_NLV_SHIFT		0
++
++#define ISPCCDC_CULLING_CULV_SHIFT		0
++#define ISPCCDC_CULLING_CULHODD_SHIFT	16
++#define ISPCCDC_CULLING_CULHEVN_SHIFT	 	24
++
++#define ISPCCDC_HSIZE_OFF_SHIFT		0
++
++#define ISPCCDC_SDOFST_FINV			(1 << 14)
++#define ISPCCDC_SDOFST_FOFST_1L		(~(3 << 12))
++#define ISPCCDC_SDOFST_FOFST_4L		(3 << 12)
++#define ISPCCDC_SDOFST_LOFST3_SHIFT		0
++#define ISPCCDC_SDOFST_LOFST2_SHIFT		3
++#define ISPCCDC_SDOFST_LOFST1_SHIFT		6
++#define ISPCCDC_SDOFST_LOFST0_SHIFT		9
++#define EVENEVEN			1
++#define ODDEVEN				2
++#define EVENODD				3
++#define ODDODD				4
++
++#define ISPCCDC_CLAMP_OBGAIN_SHIFT		0
++#define ISPCCDC_CLAMP_OBST_SHIFT		10
++#define ISPCCDC_CLAMP_OBSLN_SHIFT		25
++#define ISPCCDC_CLAMP_OBSLEN_SHIFT		28
++#define ISPCCDC_CLAMP_CLAMPEN			(1 << 31)
++
++#define ISPCCDC_COLPTN_R_Ye			0x0
++#define ISPCCDC_COLPTN_Gr_Cy			0x1
++#define ISPCCDC_COLPTN_Gb_G			0x2
++#define ISPCCDC_COLPTN_B_Mg			0x3
++#define ISPCCDC_COLPTN_CP0PLC0_SHIFT		0
++#define ISPCCDC_COLPTN_CP0PLC1_SHIFT		2
++#define ISPCCDC_COLPTN_CP0PLC2_SHIFT		4
++#define ISPCCDC_COLPTN_CP0PLC3_SHIFT		6
++#define ISPCCDC_COLPTN_CP1PLC0_SHIFT		8
++#define ISPCCDC_COLPTN_CP1PLC1_SHIFT		10
++#define ISPCCDC_COLPTN_CP1PLC2_SHIFT		12
++#define ISPCCDC_COLPTN_CP1PLC3_SHIFT		14
++#define ISPCCDC_COLPTN_CP2PLC0_SHIFT		16
++#define ISPCCDC_COLPTN_CP2PLC1_SHIFT		18
++#define ISPCCDC_COLPTN_CP2PLC2_SHIFT		20
++#define ISPCCDC_COLPTN_CP2PLC3_SHIFT		22
++#define ISPCCDC_COLPTN_CP3PLC0_SHIFT		24
++#define ISPCCDC_COLPTN_CP3PLC1_SHIFT		26
++#define ISPCCDC_COLPTN_CP3PLC2_SHIFT		28
++#define ISPCCDC_COLPTN_CP3PLC3_SHIFT		30
++
++#define ISPCCDC_BLKCMP_B_MG_SHIFT	0
++#define ISPCCDC_BLKCMP_GB_G_SHIFT	8
++#define ISPCCDC_BLKCMP_GR_CY_SHIFT	6
++#define ISPCCDC_BLKCMP_R_YE_SHIFT	24
++
++#define ISPCCDC_FPC_FPNUM_SHIFT	0
++#define ISPCCDC_FPC_FPCEN		(1 << 15)
++#define ISPCCDC_FPC_FPERR		(1 << 16)
++
++#define ISPCCDC_VDINT_1_SHIFT		0
++#define ISPCCDC_VDINT_0_SHIFT		16
++#define ISPCCDC_VDINT_0_MASK		0x7FFF
++#define ISPCCDC_VDINT_1_MASK		0x7FFF
++
++#define ISPCCDC_ALAW_GWDI_SHIFT	0
++#define ISPCCDC_ALAW_CCDTBL		(1 << 3)
++
++#define ISPCCDC_REC656IF_R656ON	1
++#define ISPCCDC_REC656IF_ECCFVH	(1 << 1)
++
++#define ISPCCDC_CFG_BW656		(1 << 5)
++#define ISPCCDC_CFG_FIDMD_SHIFT	6
++#define ISPCCDC_CFG_WENLOG		(1 << 8)
++#define ISPCCDC_CFG_Y8POS		(1 << 11)
++#define ISPCCDC_CFG_BSWD		(1 << 12)
++#define ISPCCDC_CFG_MSBINVI		(1 << 13)
++#define ISPCCDC_CFG_VDLC		(1 << 15)
++
++#define ISPCCDC_FMTCFG_FMTEN		0x1
++#define ISPCCDC_FMTCFG_LNALT		(1 << 1)
++#define ISPCCDC_FMTCFG_LNUM_SHIFT	2
++#define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT	4
++#define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT	8
++#define ISPCCDC_FMTCFG_VPIN_MASK		0xFFFF8000
++#define ISPCCDC_FMTCFG_VPIN_12_3		(0x3 << 12)
++#define ISPCCDC_FMTCFG_VPIN_11_2		(0x4 << 12)
++#define ISPCCDC_FMTCFG_VPIN_10_1		(0x5 << 12)
++#define ISPCCDC_FMTCFG_VPIN_9_0		(0x6 << 12)
++#define ISPCCDC_FMTCFG_VPEN			(1 << 15)
++
++#define ISPCCDC_FMTCF_VPIF_FRQ_MASK		0xFFF8FFFF
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY2		(0x0 << 16)
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY3		(0x1 << 16)
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY4		(0x2 << 16)
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY5		(0x3 << 16)
++#define ISPCCDC_FMTCF_VPIF_FRQ_BY6		(0x4 << 16)
++
++#define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT	0
++#define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT	16
++
++#define ISPCCDC_FMT_VERT_FMTLNV_SHIFT	0
++#define ISPCCDC_FMT_VERT_FMTSLV_SHIFT	16
++
++#define ISPCCDC_FMT_HORZ_FMTSPH_MASK	0x1FFF0000
++#define ISPCCDC_FMT_HORZ_FMTLNH_MASK	0x1FFF
++
++#define ISPCCDC_FMT_VERT_FMTSLV_MASK	0x1FFF0000
++#define ISPCCDC_FMT_VERT_FMTLNV_MASK	0x1FFF
++
++
++#define ISPCCDC_VP_OUT_HORZ_ST_SHIFT		0
++#define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT	4
++#define ISPCCDC_VP_OUT_VERT_NUM_SHIFT	17
++
++#define ISPRSZ_PID_PREV_SHIFT			0
++#define ISPRSZ_PID_CID_SHIFT			8
++#define ISPRSZ_PID_TID_SHIFT			16
++
++
++#define ISPRSZ_PCR_ENABLE			0x5
++#define ISPRSZ_PCR_BUSY			 	(1 << 1)
++
++#define ISPRSZ_CNT_HRSZ_SHIFT			0
++#define ISPRSZ_CNT_HRSZ_MASK			0x3FF
++#define ISPRSZ_CNT_VRSZ_SHIFT			10
++#define ISPRSZ_CNT_VRSZ_MASK			0xFFC00
++#define ISPRSZ_CNT_HSTPH_SHIFT			20
++#define ISPRSZ_CNT_HSTPH_MASK			0x700000
++#define ISPRSZ_CNT_VSTPH_SHIFT			23
++#define	ISPRSZ_CNT_VSTPH_MASK			0x3800000
++#define	ISPRSZ_CNT_CBILIN_MASK			0x20000000
++#define	ISPRSZ_CNT_INPTYP_MASK			0x08000000
++#define	ISPRSZ_CNT_PIXFMT_MASK			0x04000000
++#define ISPRSZ_CNT_YCPOS            (1 << 26)
++#define ISPRSZ_CNT_INPTYP           (1 << 27)
++#define ISPRSZ_CNT_INPSRC           (1 << 28)
++#define ISPRSZ_CNT_CBILIN           (1 << 29)
++
++#define ISPRSZ_OUT_SIZE_HORZ_SHIFT		0
++#define ISPRSZ_OUT_SIZE_HORZ_MASK		0x7FF
++#define ISPRSZ_OUT_SIZE_VERT_SHIFT		16
++#define ISPRSZ_OUT_SIZE_VERT_MASK		0x7FF0000
++
++
++#define ISPRSZ_IN_START_HORZ_ST_SHIFT		0
++#define ISPRSZ_IN_START_HORZ_ST_MASK		0x1FFF
++#define ISPRSZ_IN_START_VERT_ST_SHIFT		16
++#define ISPRSZ_IN_START_VERT_ST_MASK		0x1FFF0000
++
++
++#define ISPRSZ_IN_SIZE_HORZ_SHIFT		0
++#define ISPRSZ_IN_SIZE_HORZ_MASK		0x1FFF
++#define ISPRSZ_IN_SIZE_VERT_SHIFT		16
++#define ISPRSZ_IN_SIZE_VERT_MASK		0x1FFF0000
++
++#define ISPRSZ_SDR_INADD_ADDR_SHIFT		0
++#define ISPRSZ_SDR_INADD_ADDR_MASK		0xFFFFFFFF
++
++#define ISPRSZ_SDR_INOFF_OFFSET_SHIFT		0
++#define ISPRSZ_SDR_INOFF_OFFSET_MASK		0xFFFF
++
++#define ISPRSZ_SDR_OUTADD_ADDR_SHIFT		0
++#define ISPRSZ_SDR_OUTADD_ADDR_MASK		0xFFFFFFFF
++
++
++#define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT		0
++#define ISPRSZ_SDR_OUTOFF_OFFSET_MASK		0xFFFF
++
++#define ISPRSZ_HFILT10_COEF0_SHIFT		0
++#define ISPRSZ_HFILT10_COEF0_MASK		0x3FF
++#define ISPRSZ_HFILT10_COEF1_SHIFT		16
++#define ISPRSZ_HFILT10_COEF1_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT32_COEF2_SHIFT		0
++#define ISPRSZ_HFILT32_COEF2_MASK		0x3FF
++#define ISPRSZ_HFILT32_COEF3_SHIFT		16
++#define ISPRSZ_HFILT32_COEF3_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT54_COEF4_SHIFT		0
++#define ISPRSZ_HFILT54_COEF4_MASK		0x3FF
++#define ISPRSZ_HFILT54_COEF5_SHIFT		16
++#define ISPRSZ_HFILT54_COEF5_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT76_COEFF6_SHIFT		0
++#define ISPRSZ_HFILT76_COEFF6_MASK		0x3FF
++#define ISPRSZ_HFILT76_COEFF7_SHIFT		16
++#define ISPRSZ_HFILT76_COEFF7_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT98_COEFF8_SHIFT		0
++#define ISPRSZ_HFILT98_COEFF8_MASK		0x3FF
++#define ISPRSZ_HFILT98_COEFF9_SHIFT		16
++#define ISPRSZ_HFILT98_COEFF9_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1110_COEF10_SHIFT		0
++#define ISPRSZ_HFILT1110_COEF10_MASK		0x3FF
++#define ISPRSZ_HFILT1110_COEF11_SHIFT		16
++#define ISPRSZ_HFILT1110_COEF11_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1312_COEFF12_SHIFT		0
++#define ISPRSZ_HFILT1312_COEFF12_MASK		0x3FF
++#define ISPRSZ_HFILT1312_COEFF13_SHIFT		16
++#define ISPRSZ_HFILT1312_COEFF13_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1514_COEFF14_SHIFT		0
++#define ISPRSZ_HFILT1514_COEFF14_MASK		0x3FF
++#define ISPRSZ_HFILT1514_COEFF15_SHIFT		16
++#define ISPRSZ_HFILT1514_COEFF15_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1716_COEF16_SHIFT		0
++#define ISPRSZ_HFILT1716_COEF16_MASK		0x3FF
++#define ISPRSZ_HFILT1716_COEF17_SHIFT		16
++#define ISPRSZ_HFILT1716_COEF17_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT1918_COEF18_SHIFT		0
++#define ISPRSZ_HFILT1918_COEF18_MASK		0x3FF
++#define ISPRSZ_HFILT1918_COEF19_SHIFT		16
++#define ISPRSZ_HFILT1918_COEF19_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2120_COEF20_SHIFT		0
++#define ISPRSZ_HFILT2120_COEF20_MASK		0x3FF
++#define ISPRSZ_HFILT2120_COEF21_SHIFT		16
++#define ISPRSZ_HFILT2120_COEF21_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2322_COEF22_SHIFT		0
++#define ISPRSZ_HFILT2322_COEF22_MASK		0x3FF
++#define ISPRSZ_HFILT2322_COEF23_SHIFT		16
++#define ISPRSZ_HFILT2322_COEF23_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2524_COEF24_SHIFT		0
++#define ISPRSZ_HFILT2524_COEF24_MASK		0x3FF
++#define ISPRSZ_HFILT2524_COEF25_SHIFT		16
++#define ISPRSZ_HFILT2524_COEF25_MASK		0x3FF0000
++
++#define ISPRSZ_HFILT2726_COEF26_SHIFT		0
++#define ISPRSZ_HFILT2726_COEF26_MASK		0x3FF
++#define ISPRSZ_HFILT2726_COEF27_SHIFT		16
++#define ISPRSZ_HFILT2726_COEF27_MASK		0x3FF0000
++
++
++#define ISPRSZ_HFILT2928_COEF28_SHIFT		0
++#define ISPRSZ_HFILT2928_COEF28_MASK		0x3FF
++#define ISPRSZ_HFILT2928_COEF29_SHIFT		16
++#define ISPRSZ_HFILT2928_COEF29_MASK		0x3FF0000
++
++
++#define ISPRSZ_HFILT3130_COEF30_SHIFT		0
++#define ISPRSZ_HFILT3130_COEF30_MASK		0x3FF
++#define ISPRSZ_HFILT3130_COEF31_SHIFT		16
++#define ISPRSZ_HFILT3130_COEF31_MASK		0x3FF0000
++
++
++#define ISPRSZ_VFILT10_COEF0_SHIFT		0
++#define ISPRSZ_VFILT10_COEF0_MASK		0x3FF
++#define ISPRSZ_VFILT10_COEF1_SHIFT		16
++#define ISPRSZ_VFILT10_COEF1_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT32_COEF2_SHIFT		0
++#define ISPRSZ_VFILT32_COEF2_MASK		0x3FF
++#define ISPRSZ_VFILT32_COEF3_SHIFT		16
++#define ISPRSZ_VFILT32_COEF3_MASK		0x3FF0000
++
++
++#define ISPRSZ_VFILT54_COEF4_SHIFT		0
++#define ISPRSZ_VFILT54_COEF4_MASK		0x3FF
++#define ISPRSZ_VFILT54_COEF5_SHIFT		16
++#define ISPRSZ_VFILT54_COEF5_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT76_COEFF6_SHIFT		0
++#define ISPRSZ_VFILT76_COEFF6_MASK		0x3FF
++#define ISPRSZ_VFILT76_COEFF7_SHIFT		16
++#define ISPRSZ_VFILT76_COEFF7_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT98_COEFF8_SHIFT		0
++#define ISPRSZ_VFILT98_COEFF8_MASK		0x3FF
++#define ISPRSZ_VFILT98_COEFF9_SHIFT		16
++#define ISPRSZ_VFILT98_COEFF9_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1110_COEF10_SHIFT		0
++#define ISPRSZ_VFILT1110_COEF10_MASK		0x3FF
++#define ISPRSZ_VFILT1110_COEF11_SHIFT		16
++#define ISPRSZ_VFILT1110_COEF11_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1312_COEFF12_SHIFT		0
++#define ISPRSZ_VFILT1312_COEFF12_MASK		0x3FF
++#define ISPRSZ_VFILT1312_COEFF13_SHIFT		16
++#define ISPRSZ_VFILT1312_COEFF13_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1514_COEFF14_SHIFT		0
++#define ISPRSZ_VFILT1514_COEFF14_MASK		0x3FF
++#define ISPRSZ_VFILT1514_COEFF15_SHIFT		16
++#define ISPRSZ_VFILT1514_COEFF15_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1716_COEF16_SHIFT		0
++#define ISPRSZ_VFILT1716_COEF16_MASK		0x3FF
++#define ISPRSZ_VFILT1716_COEF17_SHIFT		16
++#define ISPRSZ_VFILT1716_COEF17_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT1918_COEF18_SHIFT		0
++#define ISPRSZ_VFILT1918_COEF18_MASK		0x3FF
++#define ISPRSZ_VFILT1918_COEF19_SHIFT		16
++#define ISPRSZ_VFILT1918_COEF19_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2120_COEF20_SHIFT		0
++#define ISPRSZ_VFILT2120_COEF20_MASK		0x3FF
++#define ISPRSZ_VFILT2120_COEF21_SHIFT		16
++#define ISPRSZ_VFILT2120_COEF21_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2322_COEF22_SHIFT		0
++#define ISPRSZ_VFILT2322_COEF22_MASK		0x3FF
++#define ISPRSZ_VFILT2322_COEF23_SHIFT		16
++#define ISPRSZ_VFILT2322_COEF23_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2524_COEF24_SHIFT		0
++#define ISPRSZ_VFILT2524_COEF24_MASK		0x3FF
++#define ISPRSZ_VFILT2524_COEF25_SHIFT		16
++#define ISPRSZ_VFILT2524_COEF25_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2726_COEF26_SHIFT		0
++#define ISPRSZ_VFILT2726_COEF26_MASK		0x3FF
++#define ISPRSZ_VFILT2726_COEF27_SHIFT		16
++#define ISPRSZ_VFILT2726_COEF27_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT2928_COEF28_SHIFT		0
++#define ISPRSZ_VFILT2928_COEF28_MASK		0x3FF
++#define ISPRSZ_VFILT2928_COEF29_SHIFT		16
++#define ISPRSZ_VFILT2928_COEF29_MASK		0x3FF0000
++
++#define ISPRSZ_VFILT3130_COEF30_SHIFT		0
++#define ISPRSZ_VFILT3130_COEF30_MASK		0x3FF
++#define ISPRSZ_VFILT3130_COEF31_SHIFT		16
++#define ISPRSZ_VFILT3130_COEF31_MASK		0x3FF0000
++
++#define ISPRSZ_YENH_CORE_SHIFT			0
++#define ISPRSZ_YENH_CORE_MASK			0xFF
++#define ISPRSZ_YENH_SLOP_SHIFT			8
++#define ISPRSZ_YENH_SLOP_MASK			0xF00
++#define ISPRSZ_YENH_GAIN_SHIFT			12
++#define ISPRSZ_YENH_GAIN_MASK			0xF000
++#define ISPRSZ_YENH_ALGO_SHIFT			16
++#define ISPRSZ_YENH_ALGO_MASK			0x30000
++
++#define ISPH3A_PCR_AEW_ALAW_EN_SHIFT    	1
++#define ISPH3A_PCR_AF_MED_TH_SHIFT  		3
++#define ISPH3A_PCR_AF_RGBPOS_SHIFT  		11
++#define ISPH3A_PCR_AEW_AVE2LMT_SHIFT    	22
++#define ISPH3A_PCR_AEW_AVE2LMT_MASK   		0xFFC00000
++
++#define ISPH3A_AEWWIN1_WINHC_SHIFT   		0
++#define ISPH3A_AEWWIN1_WINHC_MASK   		0x3F
++#define ISPH3A_AEWWIN1_WINVC_SHIFT  		6
++#define ISPH3A_AEWWIN1_WINVC_MASK   		0x1FC0
++#define ISPH3A_AEWWIN1_WINW_SHIFT   		13
++#define ISPH3A_AEWWIN1_WINW_MASK     		0xFE000
++#define ISPH3A_AEWWIN1_WINH_SHIFT   		24
++#define ISPH3A_AEWWIN1_WINH_MASK     		0x7F000000
++
++#define ISPH3A_AEWINSTART_WINSH_SHIFT           0
++#define ISPH3A_AEWINSTART_WINSH_MASK            0x0FFF
++#define ISPH3A_AEWINSTART_WINSV_SHIFT           16
++#define ISPH3A_AEWINSTART_WINSV_MASK            0x0FFF0000
++
++#define ISPH3A_AEWINBLK_WINH_SHIFT   		0
++#define ISPH3A_AEWINBLK_WINH_MASK     		0x7F
++#define ISPH3A_AEWINBLK_WINSV_SHIFT  		16
++#define ISPH3A_AEWINBLK_WINSV_MASK   		0x0FFF0000
++
++#define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT          0
++#define ISPH3A_AEWSUBWIN_AEWINCH_MASK           0x0F
++#define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT          8
++#define ISPH3A_AEWSUBWIN_AEWINCV_MASK           0x0F00
++
++#define ISPHIST_PCR_ENABLE_SHIFT        0
++#define ISPHIST_PCR_ENABLE_MASK         0x01
++#define ISPHIST_PCR_BUSY_SHIFT          1
++#define ISPHIST_PCR_BUSY_MASK           0x02
++
++#define ISPHIST_CNT_DATASIZE_SHIFT      8
++#define ISPHIST_CNT_DATASIZE_MASK       0x0100
++#define ISPHIST_CNT_CLEAR_SHIFT         7
++#define ISPHIST_CNT_CLEAR_MASK          0x080
++#define ISPHIST_CNT_CFA_SHIFT           6
++#define ISPHIST_CNT_CFA_MASK            0x040
++#define ISPHIST_CNT_BINS_SHIFT          4
++#define ISPHIST_CNT_BINS_MASK           0x030
++#define ISPHIST_CNT_SOURCE_SHIFT        3
++#define ISPHIST_CNT_SOURCE_MASK         0x08
++#define ISPHIST_CNT_SHIFT_SHIFT         0
++#define ISPHIST_CNT_SHIFT_MASK          0x07
++
++#define ISPHIST_WB_GAIN_WG00_SHIFT      24
++#define ISPHIST_WB_GAIN_WG00_MASK       0xFF000000
++#define ISPHIST_WB_GAIN_WG01_SHIFT      16
++#define ISPHIST_WB_GAIN_WG01_MASK       0xFF0000
++#define ISPHIST_WB_GAIN_WG02_SHIFT      8
++#define ISPHIST_WB_GAIN_WG02_MASK       0xFF00
++#define ISPHIST_WB_GAIN_WG03_SHIFT      0
++#define ISPHIST_WB_GAIN_WG03_MASK       0xFF
++
++#define ISPHIST_REGHORIZ_HSTART_SHIFT    16      /*REGION 0 to 3 HORZ and VERT */
++#define ISPHIST_REGHORIZ_HSTART_MASK     0x3FFF0000
++#define ISPHIST_REGHORIZ_HEND_SHIFT      0
++#define ISPHIST_REGHORIZ_HEND_MASK       0x3FFF
++#define ISPHIST_REGVERT_VSTART_SHIFT     16
++#define ISPHIST_REGVERT_VSTART_MASK      0x3FFF0000
++#define ISPHIST_REGVERT_VEND_SHIFT       0
++#define ISPHIST_REGVERT_VEND_MASK        0x3FFF
++
++#define ISPHIST_REGHORIZ_MASK            0x3FFF3FFF
++#define ISPHIST_REGVERT_MASK             0x3FFF3FFF
++
++#define ISPHIST_ADDR_SHIFT               0
++#define ISPHIST_ADDR_MASK                0x3FF
++
++#define ISPHIST_DATA_SHIFT               0
++#define ISPHIST_DATA_MASK                0xFFFFF
++
++#define ISPHIST_RADD_SHIFT               0
++#define ISPHIST_RADD_MASK                0xFFFFFFFF
++
++#define ISPHIST_RADD_OFF_SHIFT           0
++#define ISPHIST_RADD_OFF_MASK            0xFFFF
++
++#define ISPHIST_HV_INFO_HSIZE_SHIFT      16
++#define ISPHIST_HV_INFO_HSIZE_MASK       0x3FFF0000
++#define ISPHIST_HV_INFO_VSIZE_SHIFT      0
++#define ISPHIST_HV_INFO_VSIZE_MASK       0x3FFF
++
++#define ISPHIST_HV_INFO_MASK             0x3FFF3FFF
++
++
++#define ISPCCDC_LSC_GAIN_MODE_N_MASK	0x700
++#define ISPCCDC_LSC_GAIN_MODE_N_SHIFT	8
++#define ISPCCDC_LSC_GAIN_MODE_M_MASK	0x3800
++#define ISPCCDC_LSC_GAIN_MODE_M_SHIFT	12
++#define ISPCCDC_LSC_GAIN_FORMAT_MASK	0xE
++#define ISPCCDC_LSC_GAIN_FORMAT_SHIFT	1
++#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK	(1<<6)
++
++
++#define ISPCCDC_LSC_INITIAL_X_MASK	0x3F
++#define ISPCCDC_LSC_INITIAL_X_SHIFT	0
++#define ISPCCDC_LSC_INITIAL_Y_MASK	0x3F0000
++#define ISPCCDC_LSC_INITIAL_Y_SHIFT	16
++
++
++#define ISPMMU_REVISION_REV_MINOR_MASK	0xF
++#define ISPMMU_REVISION_REV_MAJOR_SHIFT	0x4
++
++#define IRQENABLE_MULTIHITFAULT		(1<<4)
++#define IRQENABLE_TWFAULT			(1<<3)
++#define IRQENABLE_EMUMISS			(1<<2)
++#define IRQENABLE_TRANSLNFAULT			(1<<1)
++#define IRQENABLE_TLBMISS			(1)
++
++#define ISPMMU_MMUCNTL_MMU_EN		(1<<1)
++#define ISPMMU_MMUCNTL_TWL_EN		(1<<2)
++#define ISPMMU_MMUCNTL_EMUTLBUPDATE		(1<<3)
++#define ISPMMU_AUTOIDLE		0x1
++#define ISPMMU_SIdlemode_Forceidle      0
++#define ISPMMU_SIdlemode_Noidle         1
++#define ISPMMU_SIdlemode_Smartidle	2
++#define ISPMMU_SIdlemode_Shift		3
++
++#define ISPCSI1_AUTOIDLE		0x1
++#define ISPCSI1_MIdleMode_Shift 	 12
++#define ISPCSI1_MIdleMode_ForceStandBy	0x0
++#define ISPCSI1_MIdleMode_NoStandBy	0x1
++#define ISPCSI1_MIdleMode_SmartStandBy	0x2
++
++#endif	/* __ISPREG_H__ */
+Index: git/drivers/media/video/isp/ispresizer.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/ispresizer.c	2009-02-12 11:44:14.000000000 -0600
+@@ -0,0 +1,854 @@
++/*
++ * drivers/media/video/ispresizer.c
++ *
++ * Driver Library for Resizer module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C)2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ *
++ * Resizer module for ISP driver on OMAP3430. It implements
++ * the Resizer module APIs defined in ispresizer.h.
++ */
++
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <asm/io.h>
++#include <linux/module.h>
++
++#include "isp.h"
++#include "ispreg.h"
++#include "ispresizer.h"
++
++/*
++ * Resizer Constants
++ */
++#define MAX_IN_WIDTH_MEMORY_MODE 4095
++
++#define MAX_IN_WIDTH_ONTHEFLY_MODE 1280
++#define MAX_IN_WIDTH_ONTHEFLY_MODE_ES2 4095
++#define MAX_IN_HEIGHT 4095
++#define MINIMUM_RESIZE_VALUE 64
++#define MAXIMUM_RESIZE_VALUE 1024
++#define MID_RESIZE_VALUE 512
++
++#define MAX_7TAP_HRSZ_OUTWIDTH 1280
++#define MAX_7TAP_VRSZ_OUTWIDTH 640
++
++#define MAX_7TAP_HRSZ_OUTWIDTH_ES2 3300
++#define MAX_7TAP_VRSZ_OUTWIDTH_ES2 1650
++
++#define DEFAULTSTPIXEL 0
++#define DEFAULTSTPHASE 1
++#define DEFAULTHSTPIXEL4TAPMODE 3
++#define FOURPHASE 4
++#define EIGHTPHASE 8
++#define RESIZECONSTANT 256
++#define SHIFTER4TAPMODE 0
++#define SHIFTER7TAPMODE 1
++#define DEFAULTOFFSET 7
++#define OFFSETVERT4TAPMODE 4
++#define OPWDALIGNCONSTANT 0xFFFFFFF0
++
++/* Default configuration of resizer,filter coefficients,yenh for camera isp*/
++static struct isprsz_yenh ispreszdefaultyenh = {0, 0, 0, 0};
++static	struct isprsz_coef ispreszdefcoef = {
++{
++			0x0000, 0x0100, 0x0000, 0x0000,
++			0x03FA, 0x00F6, 0x0010, 0x0000,
++			0x03F9, 0x00DB, 0x002C, 0x0000,
++			0x03FB, 0x00B3, 0x0053, 0x03FF,
++			0x03FD, 0x0082, 0x0084, 0x03FD,
++			0x03FF, 0x0053, 0x00B3, 0x03FB,
++			0x0000, 0x002C, 0x00DB, 0x03F9,
++			0x0000, 0x0010, 0x00F6, 0x03FA
++			},
++			{
++			0x0000, 0x0100, 0x0000, 0x0000,
++			0x03FA, 0x00F6, 0x0010, 0x0000,
++			0x03F9, 0x00DB, 0x002C, 0x0000,
++			0x03FB, 0x00B3, 0x0053, 0x03FF,
++			0x03FD, 0x0082, 0x0084, 0x03FD,
++			0x03FF, 0x0053, 0x00B3, 0x03FB,
++			0x0000, 0x002C, 0x00DB, 0x03F9,
++			0x0000, 0x0010, 0x00F6, 0x03FA
++			},
++			{
++			0x0004, 0x0023, 0x005A, 0x0058,
++			0x0023, 0x0004, 0x0000, 0x0002,
++			0x0018, 0x004d, 0x0060, 0x0031,
++			0x0008, 0x0000, 0x0001, 0x000f,
++			0x003f, 0x0062, 0x003f, 0x000f,
++			0x0001, 0x0000, 0x0008, 0x0031,
++			0x0060, 0x004d, 0x0018, 0x0002
++			},
++			{
++			0x0004, 0x0023, 0x005A, 0x0058,
++			0x0023, 0x0004, 0x0000, 0x0002,
++			0x0018, 0x004d, 0x0060, 0x0031,
++			0x0008, 0x0000, 0x0001, 0x000f,
++			0x003f, 0x0062, 0x003f, 0x000f,
++			0x0001, 0x0000, 0x0008, 0x0031,
++			0x0060, 0x004d, 0x0018, 0x0002
++			}
++	};
++
++/*
++ * Structure for the resizer module to store its own information.
++ */
++static struct isp_res {
++	u8 res_inuse;
++	u8 h_startphase;
++	u8 v_startphase;
++	u16 h_resz;
++	u16 v_resz;
++	u32 outputwidth;
++	u32 outputheight;
++	u32 inputwidth;
++	u32 inputheight;
++	u8 algo;
++	u32 ipht_crop;
++	u32 ipwd_crop;
++	u32 cropwidth;
++	u32 cropheight;
++	enum ispresizer_input resinput;
++	struct isprsz_coef coeflist;
++	struct semaphore semlock;
++} ispres_obj;
++
++/* Structure for saving/restoring resizer module registers*/
++static struct isp_reg isprsz_reg_list[] = {
++	{ISPRSZ_CNT, 0x0000},
++	{ISPRSZ_OUT_SIZE, 0x0000},
++	{ISPRSZ_IN_START, 0x0000},
++	{ISPRSZ_IN_SIZE, 0x0000},
++	{ISPRSZ_SDR_INADD, 0x0000},
++	{ISPRSZ_SDR_INOFF, 0x0000},
++	{ISPRSZ_SDR_OUTADD, 0x0000},
++	{ISPRSZ_SDR_OUTOFF, 0x0000},
++	{ISPRSZ_HFILT10, 0x0000},
++	{ISPRSZ_HFILT32, 0x0000},
++	{ISPRSZ_HFILT54, 0x0000},
++	{ISPRSZ_HFILT76, 0x0000},
++	{ISPRSZ_HFILT98, 0x0000},
++	{ISPRSZ_HFILT1110, 0x0000},
++	{ISPRSZ_HFILT1312, 0x0000},
++	{ISPRSZ_HFILT1514, 0x0000},
++	{ISPRSZ_HFILT1716, 0x0000},
++	{ISPRSZ_HFILT1918, 0x0000},
++	{ISPRSZ_HFILT2120, 0x0000},
++	{ISPRSZ_HFILT2322, 0x0000},
++	{ISPRSZ_HFILT2524, 0x0000},
++	{ISPRSZ_HFILT2726, 0x0000},
++	{ISPRSZ_HFILT2928, 0x0000},
++	{ISPRSZ_HFILT3130, 0x0000},
++	{ISPRSZ_VFILT10, 0x0000},
++	{ISPRSZ_VFILT32, 0x0000},
++	{ISPRSZ_VFILT54, 0x0000},
++	{ISPRSZ_VFILT76, 0x0000},
++	{ISPRSZ_VFILT98, 0x0000},
++	{ISPRSZ_VFILT1110, 0x0000},
++	{ISPRSZ_VFILT1312, 0x0000},
++	{ISPRSZ_VFILT1514, 0x0000},
++	{ISPRSZ_VFILT1716, 0x0000},
++	{ISPRSZ_VFILT1918, 0x0000},
++	{ISPRSZ_VFILT2120, 0x0000},
++	{ISPRSZ_VFILT2322, 0x0000},
++	{ISPRSZ_VFILT2524, 0x0000},
++	{ISPRSZ_VFILT2726, 0x0000},
++	{ISPRSZ_VFILT2928, 0x0000},
++	{ISPRSZ_VFILT3130, 0x0000},
++	{ISPRSZ_YENH, 0x0000},
++	{ISP_TOK_TERM, 0x0000}
++};
++
++void ispresizer_config_shadow_registers()
++{
++	return;
++}
++EXPORT_SYMBOL(ispresizer_config_shadow_registers);
++
++void ispresizer_trycrop(u32 left, u32 top, u32 width, u32 height, u32 ow,
++									u32 oh)
++{
++	ispres_obj.cropwidth = width + 6;
++	ispres_obj.cropheight = height + 6;
++	ispresizer_try_size(&ispres_obj.cropwidth, &ispres_obj.cropheight, &ow,
++									&oh);
++	ispres_obj.ipht_crop = top;
++	ispres_obj.ipwd_crop = left;
++}
++EXPORT_SYMBOL(ispresizer_trycrop);
++
++void ispresizer_applycrop()
++{
++	ispresizer_config_size(ispres_obj.cropwidth, ispres_obj.cropheight,
++						ispres_obj.outputwidth,
++						ispres_obj.outputheight);
++	return;
++}
++
++
++/*
++ * Reserve the Resizer module.
++ * Only one user at a time.
++ */
++int ispresizer_request()
++{
++	down(&(ispres_obj.semlock));
++	if (!(ispres_obj.res_inuse)) {
++		ispres_obj.res_inuse = 1;
++		up(&(ispres_obj.semlock));
++		/* Turn on Resizer module Clocks.*/
++		omap_writel(omap_readl(ISP_CTRL) | ISPCTRL_SBL_WR0_RAM_EN |
++				ISPCTRL_RSZ_CLK_EN, ISP_CTRL);
++		return 0;
++	} else {
++		up(&(ispres_obj.semlock));
++		printk(KERN_ERR "ISP_ERR : Resizer Module Busy\n");
++		return -EBUSY;
++	}
++}
++EXPORT_SYMBOL(ispresizer_request);
++
++/*
++ * Makes Resizer module free.
++ */
++int ispresizer_free()
++{
++	down(&(ispres_obj.semlock));
++	if (ispres_obj.res_inuse) {
++		ispres_obj.res_inuse = 0;
++		up(&(ispres_obj.semlock));
++		omap_writel(omap_readl(ISP_CTRL) & ~(ISPCTRL_RSZ_CLK_EN |
++				ISPCTRL_SBL_WR0_RAM_EN), ISP_CTRL);
++		return 0;
++	} else {
++		up(&(ispres_obj.semlock));
++		DPRINTK_ISPRESZ("ISP_ERR : Resizer Module already freed\n");
++		return -EINVAL;
++	}
++}
++EXPORT_SYMBOL(ispresizer_free);
++
++/*
++ * Sets up the default resizer configuration according to the arguments.
++ * input		: Indicates the module that gives the image to resizer
++ */
++int
++ispresizer_config_datapath(enum ispresizer_input input)
++{
++	u32 cnt = 0;
++	DPRINTK_ISPRESZ("ispresizer_config_datapath()+\n");
++	ispres_obj.resinput = input;
++	switch (input) {
++	case RSZ_OTFLY_YUV:
++		cnt &= ~ISPRSZ_CNT_INPTYP;
++		cnt &= ~ISPRSZ_CNT_INPSRC;
++		/* according to TRM, inline address and inline offset must be
++		 * set to 0 for OTF input mode
++		 */
++		ispresizer_set_inaddr(0);
++		ispresizer_config_inlineoffset(0);
++		break;
++	case RSZ_MEM_YUV:
++		cnt |= ISPRSZ_CNT_INPSRC;
++		cnt &= ~ISPRSZ_CNT_INPTYP;
++		break;
++	case RSZ_MEM_COL8:
++		cnt |= ISPRSZ_CNT_INPSRC;
++		cnt |= ISPRSZ_CNT_INPTYP;
++		break;
++	default:
++		printk(KERN_ERR "ISP_ERR : Wrong Input\n");
++		return -EINVAL;
++	}
++	omap_writel(omap_readl(ISPRSZ_CNT) | cnt, ISPRSZ_CNT);
++	/*Set up default parameters
++	 */
++	ispresizer_config_ycpos(0);
++	ispresizer_config_filter_coef(&ispreszdefcoef);
++	ispresizer_enable_cbilin(0);
++	ispresizer_config_luma_enhance(&ispreszdefaultyenh);
++	DPRINTK_ISPRESZ("ispresizer_config_datapath()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_config_datapath);
++
++/*
++ * Calculates the horizontal and vertical resize ratio,number of pixels to
++ * be cropped in the resizer module and checks the validity of various
++ * parameters.This function internally calls trysize_calculation,which does
++ * the actual calculations and populates required members of isp_res struct
++ * Formula used for calculation is:-
++ * 8-phase 4-tap mode :-
++ * inputwidth = (32*sph + (ow - 1)*hrsz + 16) >> 8 + 7
++ * inputheight = (32*spv + (oh - 1)*vrsz + 16) >> 8 + 4
++ * endpahse for width = ( ( 32*sph + (ow - 1)*hrsz +16 ) >> 5 )% 8
++ * endphase for height = ( ( 32*sph + (oh - 1)*hrsz +16 ) >> 5 )% 8
++ * 4-phase 7-tap mode :-
++ * inputwidth = (64*sph + (ow - 1)*hrsz + 32) >> 8 + 7
++ * inputheight = (64*spv + (oh - 1)*vrsz + 32) >> 8 + 7
++ * endpahse for width = ( ( 64*sph + (ow - 1)*hrsz +32 ) >> 6 )% 4
++ * endphase for height = ( ( 64*sph + (oh - 1)*hrsz +32 ) >> 6 )% 4
++ * where
++ * sph = Start phase horizontal
++ * spv = Start phase vertical
++ * ow = Output width
++ * oh = Output height
++ * hrsz = Horizontal resize value
++ * vrsz = Vertical resize value
++ * Fills up the output/input widht/height,horizontal/vertical resize ratio,
++ * horizontal/vertical crop variables in the isp_res structure .
++ * input_w: input width for the resizer in number of pixels per line
++ * input_h: input height for the resizer in number of lines
++ * output_w: output width from the resizer in number of pixels per line
++ *           resizer when writing to memory needs this to be multiple of 16
++ * output_h: output height for the resizer in number of lines, must be even
++*/
++int ispresizer_try_size(u32 *input_width, u32 *input_height, u32 *output_w,
++								u32 *output_h)
++{
++	u32 rsz, rsz_7, rsz_4;
++	u32 sph;
++	u32 input_w, input_h;
++	u32 output;
++	int max_in_otf, max_out_7tap;
++	input_w = *input_width;
++	input_h = *input_height;
++
++	/*
++	 * This has to be done inorder to make sure that the try size does not
++	 * end up with input height/width greater than what the preview will
++	 * output.
++	 */
++	input_w = input_w - 6;
++	input_h = input_h - 6;
++
++	if (input_h > MAX_IN_HEIGHT)
++		return -EINVAL;
++
++///	if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
++///		max_in_otf = MAX_IN_WIDTH_ONTHEFLY_MODE;
++//		max_out_7tap = MAX_7TAP_VRSZ_OUTWIDTH;
++///	} else {
++		max_in_otf = MAX_IN_WIDTH_ONTHEFLY_MODE_ES2;
++		max_out_7tap = MAX_7TAP_VRSZ_OUTWIDTH_ES2;
++///	}
++
++	if (ispres_obj.resinput == RSZ_OTFLY_YUV) {
++		if (input_w > max_in_otf)
++			return -EINVAL;
++	} else {
++		if (input_w > MAX_IN_WIDTH_MEMORY_MODE)
++			return -EINVAL;
++	}
++
++
++	*(output_h) = *(output_h) & 0xFFFFFFFE;
++	output = *(output_h);
++	sph = DEFAULTSTPHASE;
++
++	/* For height */
++	rsz_7 = ((input_h - 7) * 256) / (output - 1);
++	rsz_4 = ((input_h - 4) * 256) / (output - 1);
++
++	rsz = (input_h * 256) / output;
++
++	if (rsz <= MID_RESIZE_VALUE) {
++		rsz = rsz_4;
++		if (rsz < MINIMUM_RESIZE_VALUE) {
++			rsz = MINIMUM_RESIZE_VALUE;
++			output = (((input_h - 4) * 256) / rsz) + 1;
++			printk(KERN_ERR "\t ISP_ERR: rsz was less than min -"
++						" new op_h is = %d\n", output);
++		}
++	} else {
++		rsz = rsz_7;
++		if (*(output_w) > max_out_7tap)
++			*(output_w) = max_out_7tap;
++		if (rsz > MAXIMUM_RESIZE_VALUE) {
++			rsz = MAXIMUM_RESIZE_VALUE;
++			output = (((input_h - 7) * 256) / rsz) + 1;
++			printk("\t ISP_ERR: rsz was more than max - new op_h"
++							" is %d\n", output);
++		}
++	}
++
++	/* Recalculate input */
++	if (rsz > MID_RESIZE_VALUE)
++		input_h = (((64 * sph) + ((output - 1) * rsz) + 32) / 256) + 7;
++	else
++		input_h = (((32 * sph) + ((output - 1) * rsz) + 16) / 256) + 4;
++
++	ispres_obj.outputheight = output;
++	ispres_obj.v_resz = rsz;
++	ispres_obj.inputheight = input_h;
++	ispres_obj.ipht_crop = DEFAULTSTPIXEL;
++	ispres_obj.v_startphase = sph;
++
++
++	*(output_w) = *(output_w) & 0xFFFFFFF0;
++	output = *(output_w);
++	sph = DEFAULTSTPHASE;
++
++	/* For Width */
++	rsz_7 = ((input_w - 7) * 256) / (output - 1);
++	rsz_4 = ((input_w - 4) * 256) / (output - 1);
++
++	rsz = (input_w * 256) / output;
++	if (rsz > MID_RESIZE_VALUE) {
++		rsz = rsz_7;
++		if (rsz > MAXIMUM_RESIZE_VALUE) {
++			rsz = MAXIMUM_RESIZE_VALUE;
++			output = (((input_w - 7) * 256) / rsz) + 1;
++			printk("\t ISP_ERR: rsz was greater than max - new"
++						" op_w is %d\n", output);
++		}
++	} else {
++		rsz = rsz_4;
++		if (rsz < MINIMUM_RESIZE_VALUE) {
++			rsz = MINIMUM_RESIZE_VALUE;
++			output = (((input_w - 4) * 256) / rsz) + 1;
++			printk("\t ISP_ERR: rsz was less than min - new op_w"
++							" is %d\n", output);
++		}
++	}
++
++	/* Recalculate input based on TRM equations */
++	if (rsz > MID_RESIZE_VALUE)
++		input_w = (((64 * sph) + ((output - 1) * rsz) + 32) / 256) + 7;
++	else
++		input_w = (((32 * sph) + ((output - 1) * rsz) + 16) / 256) + 7;
++
++	ispres_obj.outputwidth = output;
++	ispres_obj.h_resz = rsz;
++	ispres_obj.inputwidth = input_w;
++	ispres_obj.ipwd_crop = DEFAULTSTPIXEL;
++	ispres_obj.h_startphase = sph;
++
++	*input_height = input_h;
++	*input_width = input_w;
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_try_size);
++
++/*
++ * Configures the appropriate values stored in the isp_res structure in
++ * the resizer registers
++ * input_w	: input width for the resizer in number of pixels per line
++ * input_h	: input height for the resizer in number of lines
++ * output_w	: output width from the resizer in number of pixels per line
++ * output_h	: output height for the resizer in number of lines
++ */
++int
++ispresizer_config_size(u32 input_w, u32 input_h, u32 output_w, u32 output_h)
++{
++	int i, j;
++	u32 res;
++	DPRINTK_ISPRESZ("ispresizer_config_size()+, input_w = %d,input_h ="
++						" %d, output_w = %d, output_h"
++						" = %d,hresz = %d,vresz = %d,"
++						" hcrop = %d, vcrop = %d,"
++						" hstph = %d, vstph = %d\n",
++						ispres_obj.inputwidth,
++						ispres_obj.inputheight,
++						ispres_obj.outputwidth,
++						ispres_obj.outputheight,
++						ispres_obj.h_resz,
++						ispres_obj.v_resz,
++						ispres_obj.ipwd_crop,
++						ispres_obj.ipht_crop,
++						ispres_obj.h_startphase,
++						ispres_obj.v_startphase);
++	if ((output_w != ispres_obj.outputwidth)
++			|| (output_h != ispres_obj.outputheight)) {
++		printk(KERN_ERR "Output parameters passed do not match the"
++						" values calculated by the"
++						" trysize passed w %d, h %d"
++						" \n", output_w , output_h);
++		return -EINVAL;
++		}
++	/* Set horizontal and vertical starting phase */
++	res = omap_readl(ISPRSZ_CNT) & (~(ISPRSZ_CNT_HSTPH_MASK |
++					ISPRSZ_CNT_VSTPH_MASK));
++	omap_writel(res | (ispres_obj.h_startphase << ISPRSZ_CNT_HSTPH_SHIFT)
++			| (ispres_obj.v_startphase << ISPRSZ_CNT_VSTPH_SHIFT)
++			, ISPRSZ_CNT);
++	/* Set horizontal and vertical start pixel */
++	omap_writel(((ispres_obj.ipwd_crop * 2) <<
++					ISPRSZ_IN_START_HORZ_ST_SHIFT) |
++					(ispres_obj.ipht_crop <<
++					ISPRSZ_IN_START_VERT_ST_SHIFT),
++					ISPRSZ_IN_START);
++
++
++	/*Set input width and height*/
++	omap_writel((ispres_obj.inputwidth << ISPRSZ_IN_SIZE_HORZ_SHIFT) |
++						(ispres_obj.inputheight <<
++						ISPRSZ_IN_SIZE_VERT_SHIFT),
++						ISPRSZ_IN_SIZE);
++	/*Set output width and height*/
++	if (!ispres_obj.algo)
++		omap_writel((output_w << ISPRSZ_OUT_SIZE_HORZ_SHIFT) |
++						(output_h <<
++						ISPRSZ_OUT_SIZE_VERT_SHIFT),
++						ISPRSZ_OUT_SIZE);
++	else
++		omap_writel(((output_w - 4) << ISPRSZ_OUT_SIZE_HORZ_SHIFT) |
++						(output_h <<
++						ISPRSZ_OUT_SIZE_VERT_SHIFT),
++						ISPRSZ_OUT_SIZE);
++
++
++	/*Set horizontal and vertical resize ratios*/
++	res = omap_readl(ISPRSZ_CNT) & (~(ISPRSZ_CNT_HRSZ_MASK |
++						ISPRSZ_CNT_VRSZ_MASK));
++	omap_writel(res | ((ispres_obj.h_resz - 1) << ISPRSZ_CNT_HRSZ_SHIFT)
++			| ((ispres_obj.v_resz - 1) << ISPRSZ_CNT_VRSZ_SHIFT)
++			, ISPRSZ_CNT);
++	/*Set the horizontal/vertical filter coefficients depending on the
++	 * resize values
++	 */
++	if (ispres_obj.h_resz <= MID_RESIZE_VALUE) {
++		j = 0;
++		for (i = 0; i < 16; i++) {
++			omap_writel((ispres_obj.coeflist.
++			h_filter_coef_4tap[j] <<
++			ISPRSZ_HFILT10_COEF0_SHIFT) |
++			(ispres_obj.coeflist.h_filter_coef_4tap[j+1]
++			<< ISPRSZ_HFILT10_COEF1_SHIFT),
++			ISPRSZ_HFILT10 + (i * 0x04));
++			j += 2;
++		}
++	} else {
++		j = 0;
++		for (i = 0; i < 16; i++) {
++			if ((i + 1) % 4 == 0) {
++				omap_writel((ispres_obj.coeflist.
++				h_filter_coef_7tap[j] <<
++				ISPRSZ_HFILT10_COEF0_SHIFT) ,
++				ISPRSZ_HFILT10 + (i * 0x04));
++				j += 1;
++			} else {
++				omap_writel((ispres_obj.coeflist.
++				h_filter_coef_7tap[j] <<
++				ISPRSZ_HFILT10_COEF0_SHIFT) |
++				(ispres_obj.coeflist.
++				h_filter_coef_7tap[j+1] <<
++				ISPRSZ_HFILT10_COEF1_SHIFT),
++				ISPRSZ_HFILT10 + (i * 0x04));
++				j += 2;
++			}
++		}
++	}
++	if (ispres_obj.v_resz <= MID_RESIZE_VALUE) {
++		j = 0;
++		for (i = 0; i < 16; i++) {
++			omap_writel((ispres_obj.coeflist.
++			v_filter_coef_4tap[j] <<
++			ISPRSZ_VFILT10_COEF0_SHIFT) |
++			(ispres_obj.coeflist.v_filter_coef_4tap[j+1]
++			<< ISPRSZ_VFILT10_COEF1_SHIFT),
++			ISPRSZ_VFILT10 + (i * 0x04));
++			j += 2;
++		}
++	} else {
++		j = 0;
++		for (i = 0; i < 16; i++) {
++			if ((i + 1) % 4 == 0) {
++				omap_writel((ispres_obj.coeflist.
++				v_filter_coef_7tap[j] <<
++				ISPRSZ_VFILT10_COEF0_SHIFT) ,
++				ISPRSZ_VFILT10 + (i * 0x04));
++				j += 1;
++			} else {
++				omap_writel((ispres_obj.coeflist.
++				v_filter_coef_7tap[j] <<
++				ISPRSZ_VFILT10_COEF0_SHIFT) |
++				(ispres_obj.coeflist.
++				v_filter_coef_7tap[j+1] <<
++				ISPRSZ_VFILT10_COEF1_SHIFT),
++				ISPRSZ_VFILT10 + (i * 0x04));
++				j += 2;
++			}
++		}
++	}
++
++	/* Configure the outline offset to e outputwidth*2*/
++	ispresizer_config_outlineoffset(output_w*2);
++	DPRINTK_ISPRESZ("ispresizer_config_size()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_config_size);
++
++/*
++ * Enables the Resizer module.
++ * Client should configure all the sub modules in Resizer before this.
++ * enable	: 1- Enables the resizer module.
++ */
++void
++ispresizer_enable(u8 enable)
++{
++	DPRINTK_ISPRESZ("+ispresizer_enable()+\n");
++	if (enable)
++		omap_writel((omap_readl(ISPRSZ_PCR)) |
++				ISPRSZ_PCR_ENABLE, ISPRSZ_PCR);
++	else {
++		omap_writel((omap_readl(ISPRSZ_PCR)) &
++				~ISPRSZ_PCR_ENABLE, ISPRSZ_PCR);
++	}
++	DPRINTK_ISPRESZ("+ispresizer_enable()-\n");
++}
++EXPORT_SYMBOL(ispresizer_enable);
++
++int ispresizer_busy(void)
++{
++	return (omap_readl(ISPRSZ_PCR) & ISPPRV_PCR_BUSY);
++}
++EXPORT_SYMBOL(ispresizer_busy);
++
++/*
++ * Sets the horizontal and vertical start phase.
++ * This API just updates the isp_res struct.Actual register write happens in
++ * ispresizer_config_size.
++ * hstartphase	: horizontal start phase(0-7)
++ * vstartphase	: vertical startphase(0-7)
++ */
++void ispresizer_config_startphase(u8 hstartphase, u8 vstartphase)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_startphase()+\n");
++	ispres_obj.h_startphase = hstartphase;
++	ispres_obj.v_startphase = vstartphase;
++	DPRINTK_ISPRESZ("ispresizer_config_startphase()-\n");
++}
++EXPORT_SYMBOL(ispresizer_config_startphase);
++
++/*
++ * Sets whether the output should be in YC or CY format.
++ * yc	:0 - YC format
++ * 	 1 - CY format
++ */
++void ispresizer_config_ycpos(u8 yc)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_ycpos()+\n");
++	if (yc)
++		omap_writel((omap_readl(ISPRSZ_CNT)) |
++			(ISPRSZ_CNT_YCPOS), ISPRSZ_CNT);
++	else
++		omap_writel((omap_readl(ISPRSZ_CNT)) &
++			(~ISPRSZ_CNT_YCPOS), ISPRSZ_CNT);
++	DPRINTK_ISPRESZ("ispresizer_config_ycpos()-\n");
++}
++EXPORT_SYMBOL(ispresizer_config_ycpos);
++
++/*
++ * Sets the chrominance algorithm
++ * cbilin	:0 - chrominance uses same processing as luminance
++ * 		 1 - bilinear interpolation processing
++ */
++void
++ispresizer_enable_cbilin(u8 enable)
++{
++	DPRINTK_ISPRESZ("ispresizer_enable_cbilin()+\n");
++	if (enable)
++		omap_writel((omap_readl(ISPRSZ_CNT)) |
++			(ISPRSZ_CNT_CBILIN), ISPRSZ_CNT);
++	else
++		omap_writel((omap_readl(ISPRSZ_CNT)) &
++			(~ISPRSZ_CNT_CBILIN) , ISPRSZ_CNT);
++	DPRINTK_ISPRESZ("ispresizer_enable_cbilin()-\n");
++}
++EXPORT_SYMBOL(ispresizer_enable_cbilin);
++
++/*
++ * Configures luminance enhancer parameters.
++ * yenh		:structure containing desired values for core,slope,gain and
++ * 		 algo parameters
++ */
++void
++ispresizer_config_luma_enhance(struct isprsz_yenh *yenh)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_luma_enhance()+\n");
++	ispres_obj.algo = yenh->algo;
++	omap_writel((yenh->algo << ISPRSZ_YENH_ALGO_SHIFT) |
++			(yenh->gain << ISPRSZ_YENH_GAIN_SHIFT) |
++			(yenh->slope << ISPRSZ_YENH_SLOP_SHIFT) |
++			(yenh->coreoffset << ISPRSZ_YENH_CORE_SHIFT),
++			ISPRSZ_YENH);
++	DPRINTK_ISPRESZ("ispresizer_config_luma_enhance()-\n");
++}
++EXPORT_SYMBOL(ispresizer_config_luma_enhance);
++
++/*
++ * Sets the filter coefficients for both 4-tap and 7-tap mode.
++ * This API just updates the isp_res struct.Actual register write happens in
++ * ispresizer_config_size.
++ * coef		:structure containing horizontal and vertical filter
++ * 		 coefficients for both 4-tap and 7-tap mode
++ */
++void ispresizer_config_filter_coef(struct isprsz_coef *coef)
++{
++	int i;
++	DPRINTK_ISPRESZ("ispresizer_config_filter_coef()+\n");
++	for (i = 0; i < 32; i++) {
++		ispres_obj.coeflist.h_filter_coef_4tap[i] =
++			coef->h_filter_coef_4tap[i];
++		ispres_obj.coeflist.v_filter_coef_4tap[i] =
++			coef->v_filter_coef_4tap[i];
++	}
++	for (i = 0; i < 28; i++) {
++		ispres_obj.coeflist.h_filter_coef_7tap[i] =
++			coef->h_filter_coef_7tap[i];
++		ispres_obj.coeflist.v_filter_coef_7tap[i] =
++			coef->v_filter_coef_7tap[i];
++	}
++	DPRINTK_ISPRESZ("ispresizer_config_filter_coef()-\n");
++}
++EXPORT_SYMBOL(ispresizer_config_filter_coef);
++
++/*
++ * Configures the Read address line offset.
++ * offset		: Line Offset for the input image.
++ */
++int ispresizer_config_inlineoffset(u32 offset)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_inlineoffset()+\n");
++	if (offset%32)
++		return -EINVAL;
++	omap_writel(offset << ISPRSZ_SDR_INOFF_OFFSET_SHIFT, ISPRSZ_SDR_INOFF);
++	DPRINTK_ISPRESZ("ispresizer_config_inlineoffset()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_config_inlineoffset);
++
++/*
++ * Configures the memory address from which the input frame is to be read.
++ * addr		: 32bit memory address aligned on 32byte boundary.
++ */
++int
++ispresizer_set_inaddr(u32 addr)
++{
++	DPRINTK_ISPRESZ("ispresizer_set_inaddr()+\n");
++	if (addr%32)
++		return -EINVAL;
++	omap_writel(addr << ISPRSZ_SDR_INADD_ADDR_SHIFT, ISPRSZ_SDR_INADD);
++	DPRINTK_ISPRESZ("ispresizer_set_inaddr()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_set_inaddr);
++
++/*
++ * Configures the Write address line offset.
++ * offset	: Line Offset for the preview output.
++ */
++int ispresizer_config_outlineoffset(u32 offset)
++{
++	DPRINTK_ISPRESZ("ispresizer_config_outlineoffset()+\n");
++	if (offset%32)
++		return -EINVAL;
++	omap_writel(offset << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT,
++			ISPRSZ_SDR_OUTOFF);
++	DPRINTK_ISPRESZ("ispresizer_config_outlineoffset()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_config_outlineoffset);
++
++/*
++ * Configures the memory address to which the output frame is written.
++ * addr		: 32bit memory address aligned on 32byte boundary.
++ */
++int ispresizer_set_outaddr(u32 addr)
++{
++	DPRINTK_ISPRESZ("ispresizer_set_outaddr()+\n");
++	if (addr%32)
++		return -EINVAL;
++	omap_writel(addr << ISPRSZ_SDR_OUTADD_ADDR_SHIFT, ISPRSZ_SDR_OUTADD);
++
++	DPRINTK_ISPRESZ("ispresizer_set_outaddr()-\n");
++	return 0;
++}
++EXPORT_SYMBOL(ispresizer_set_outaddr);
++
++/*
++ * Saves the values of the resizer module registers.
++ */
++void ispresizer_save_context(void)
++{
++	DPRINTK_ISPRESZ("Saving context\n");
++	isp_save_context(isprsz_reg_list);
++}
++EXPORT_SYMBOL(ispresizer_save_context);
++
++/*
++ * Restores the values of the resizer module registers.
++ */
++void ispresizer_restore_context(void)
++{
++	DPRINTK_ISPRESZ("Restoring context\n");
++	isp_restore_context(isprsz_reg_list);
++}
++EXPORT_SYMBOL(ispresizer_restore_context);
++
++/*
++ * Prints the values of the Resizer Module registers
++ */
++void ispresizer_print_status()
++{
++#ifdef	OMAP_ISPRESZ_DEBUG
++	DPRINTK_ISPRESZ("###ISP_CTRL inresizer =0x%x\n", omap_readl(ISP_CTRL));
++
++	DPRINTK_ISPRESZ("###ISP_IRQ0ENABLE in resizer =0x%x\n",
++			omap_readl(ISP_IRQ0ENABLE));
++	DPRINTK_ISPRESZ("###ISP_IRQ0STATUS in resizer =0x%x\n",
++			omap_readl(ISP_IRQ0STATUS));
++	DPRINTK_ISPRESZ("###RSZ PCR =0x%x\n", omap_readl(ISPRSZ_PCR));
++	DPRINTK_ISPRESZ("###RSZ CNT =0x%x\n", omap_readl(ISPRSZ_CNT));
++	DPRINTK_ISPRESZ("###RSZ OUT SIZE =0x%x\n",
++			omap_readl(ISPRSZ_OUT_SIZE));
++	DPRINTK_ISPRESZ("###RSZ IN START =0x%x\n",
++			omap_readl(ISPRSZ_IN_START));
++	DPRINTK_ISPRESZ("###RSZ IN SIZE =0x%x\n", omap_readl(ISPRSZ_IN_SIZE));
++	DPRINTK_ISPRESZ("###RSZ SDR INADD =0x%x\n",
++			omap_readl(ISPRSZ_SDR_INADD));
++	DPRINTK_ISPRESZ("###RSZ SDR INOFF =0x%x\n",
++			omap_readl(ISPRSZ_SDR_INOFF));
++	DPRINTK_ISPRESZ("###RSZ SDR OUTADD =0x%x\n",
++			omap_readl(ISPRSZ_SDR_OUTADD));
++	DPRINTK_ISPRESZ("###RSZ SDR OTOFF =0x%x\n",
++			omap_readl(ISPRSZ_SDR_OUTOFF));
++	DPRINTK_ISPRESZ("###RSZ YENH =0x%x\n", omap_readl(ISPRSZ_YENH));
++#endif
++}
++EXPORT_SYMBOL(ispresizer_print_status);
++
++/*
++ * Module Initialisation.
++ */
++static int __init
++isp_resizer_init(void)
++{
++	/*Nothing to do other than mutex init*/
++	init_MUTEX(&(ispres_obj.semlock));
++	return 0;
++}
++
++static void
++isp_resizer_cleanup(void)
++{
++ /*Nothing to do*/
++}
++
++module_init(isp_resizer_init);
++module_exit(isp_resizer_cleanup);
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("ISP Resizer Library");
++MODULE_LICENSE("GPL");
+Index: git/drivers/media/video/isp/ispresizer.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/ispresizer.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,184 @@
++/*
++ * drivers/media/video/ispresizer.h
++ *
++ * Driver include file for Resizer module in TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_RESIZER_H
++#define OMAP_ISP_RESIZER_H
++
++/************************************************************************
++The client is supposed to call resizer API in the following sequence:
++	- request()
++	- config_datatpath()
++	- optionally config/enable sub modules
++	- try/config size
++	- setup callback
++	- setup in/out memory offsets and ptrs
++	- enable()
++	...
++	- disable()
++	- free()
++*************************************************************************/
++
++void ispresizer_config_shadow_registers(void);
++
++/*
++ * Reserve the resizer module and turns on the clocks
++ * Only one user at a time.
++ */
++int ispresizer_request(void);
++
++/*
++ * Marks Resizer module free and turns off the clocks.
++ */
++int ispresizer_free(void);
++
++/*
++ *Enumeration Constants for input format
++ */
++enum ispresizer_input {
++	RSZ_OTFLY_YUV,
++	RSZ_MEM_YUV,
++	RSZ_MEM_COL8
++};
++
++/*
++ * Sets up the default resizer configuration according to the arguments.
++ */
++int ispresizer_config_datapath(enum ispresizer_input input);
++
++/*
++ * Sets the chrominance algorithm
++ */
++void ispresizer_enable_cbilin(u8 enable);
++
++/*
++ * Sets whether the output should be in YC or CY format.
++ */
++void ispresizer_config_ycpos(u8 yc);
++
++/*
++ * Sets the horizontal and vertical start phase.
++ */
++void ispresizer_config_startphase(u8 hstartphase, u8 vstartphase);
++
++/*
++ * Structure for resizer filter coeffcients.
++ */
++struct isprsz_coef{
++	/* 8-phase/4-tap mode(.5x-4x) */
++	u16 h_filter_coef_4tap[32];
++	u16 v_filter_coef_4tap[32];
++	/* 4-phase/7-tap mode(.25x-.5x) */
++	u16 h_filter_coef_7tap[28];
++	u16 v_filter_coef_7tap[28];
++};
++
++/*
++ * Sets the filter coefficients for both 4-tap and 7-tap mode.
++ * Note this API doesn't program to hardware at all. It only make a local
++ * copy of filter arrays. The actual programming happnes when _config_size
++ * is called.
++ */
++void ispresizer_config_filter_coef(struct isprsz_coef *coef);
++
++/*
++ * Structure for resizer luminance enhancer parameters
++ */
++struct isprsz_yenh{
++	u8 algo;
++	u8 gain;
++	u8 slope;
++	u8 coreoffset;
++	};
++
++/*
++ * Configures luminance enhancer parameters.
++ */
++void ispresizer_config_luma_enhance(struct isprsz_yenh *yenh);
++/*
++ * Calculates the horizontal and vertical resize ratio,number of pixels to
++ * be cropped in the resizer module and checks the validity of various
++ * parameters.We don't expose API to change RSZ_IN_START (cropping). HORZ_ST
++ * and VERT_ST are implictly set based on the expected output size and the
++ * need of small cropping on the input image.
++ * User should already config yenh/stphase before attempting any size API.
++ */
++int ispresizer_try_size(u32 *input_w, u32 *input_h, u32 *output_w,
++						u32 *output_h);
++
++
++/*
++ * Applies Crop values to hardware
++ */
++void ispresizer_applycrop(void);
++
++/*
++ * Try size for applying crop. Updates global resizer structure. Does not
++ * update h/w
++ */
++void ispresizer_trycrop(u32 left, u32 top, u32 width, u32 height, u32 ow,
++								u32 oh);
++
++/*
++ * APT that programs I/O sizes, ratios, and the right filter coefficients
++ * to resizer hardware.
++ */
++int ispresizer_config_size(u32 input_w, u32 input_h, u32 output_w,
++		u32 output_h);
++
++/*
++ * Configures the Read address line offset.
++ */
++int ispresizer_config_inlineoffset(u32 offset);
++
++/*
++ * Configures the memory address from which the input frame is to be read.
++ */
++int ispresizer_set_inaddr(u32 addr);
++
++/*
++ * Configures the Write address line offset.
++ */
++int ispresizer_config_outlineoffset(u32 offset);
++
++/*
++ * Configures the memory address to which the output frame is written.
++ */
++int ispresizer_set_outaddr(u32 addr);
++
++/*
++ * Enables the Resizer module.
++ * ES1 only works on one-shot. ES2 allows On-The-Fly.
++ * A client should config everything else before enabling the resizer.
++ */
++void ispresizer_enable(u8 enable);
++int ispresizer_busy(void);
++
++/*
++ * Saves resizer context
++ */
++void ispresizer_save_context(void);
++
++/*
++ * Restores resizer context
++ */
++void ispresizer_restore_context(void);
++
++/*
++ * Prints the values of the Resizer Module registers
++ */
++void ispresizer_print_status(void);
++
++#endif   /* OMAP_ISP_RESIZER_H */
+Index: git/drivers/media/video/isp/luma_enhance_table.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/luma_enhance_table.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,144 @@
++/*
++ * drivers/media/video/isp/luma_enhance_table.h
++ *
++ * Luminance Enhancement table values for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1047552,
++1048575,
++1047551,
++1046527,
++1045503,
++1044479,
++1043455,
++1042431,
++1041407,
++1040383,
++1039359,
++1038335,
++1037311,
++1036287,
++1035263,
++1034239,
++1033215,
++1032191,
++1031167,
++1030143,
++1028096,
++1028096,
++1028096,
++1028096,
++1028096,
++1028096,
++1028096,
++1028096,
++1028096,
++1028096,
++1028100,
++1032196,
++1036292,
++1040388,
++1044484,
++0,
++0,
++0,
++5,
++5125,
++10245,
++15365,
++20485,
++25605,
++30720,
++30720,
++30720,
++30720,
++30720,
++30720,
++30720,
++30720,
++30720,
++30720,
++30720,
++31743,
++30719,
++29695,
++28671,
++27647,
++26623,
++25599,
++24575,
++23551,
++22527,
++21503,
++20479,
++19455,
++18431,
++17407,
++16383,
++15359,
++14335,
++13311,
++12287,
++11263,
++10239,
++9215,
++8191,
++7167,
++6143,
++5119,
++4095,
++3071,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024,
++1024
+Index: git/drivers/media/video/isp/omap_previewer.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/omap_previewer.c	2009-02-12 10:29:18.000000000 -0600
+@@ -0,0 +1,820 @@
++/*
++ * drivers/media/video/isp/omap_previewer.c
++ *
++ * Wrapper for Preview module in TI's OMAP3430 ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/mutex.h>
++#include <linux/cdev.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <media/v4l2-dev.h>
++#include <asm/cacheflush.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++#include <asm/arch/io.h>
++#include "isp.h"
++#include "ispmmu.h"
++#include "ispreg.h"
++#include "omap_previewer.h"
++
++#define OMAP_PREV_NAME		"omap-previewer"
++
++static int prev_major = -1;
++static struct device *prev_dev;
++static struct class *prev_class;
++static struct prev_device *prevdevice;
++static struct platform_driver omap_previewer_driver;
++
++static u32 prev_bufsize;
++
++/**
++ * prev_calculate_crop - Calculate crop size according to device parameters
++ * @device: Structure containing ISP preview wrapper global information
++ * @crop: Structure containing crop size
++ *
++ * This function is used to calculate frame size reduction depending on
++ * the features enabled by the application.
++ **/
++static void prev_calculate_crop(struct prev_device *device,
++						struct prev_cropsize *crop)
++{
++	dev_dbg(prev_dev, "prev_calculate_crop E\n");
++
++	if (!device || !crop) {
++		dev_err(prev_dev, "\nErron in argument");
++		return;
++	}
++
++	isppreview_try_size(device->params->size_params.hsize,
++					device->params->size_params.vsize,
++					&crop->hcrop, &crop->vcrop);
++	crop->hcrop &= PREV_16PIX_ALIGN_MASK;
++	dev_dbg(prev_dev, "prev_calculate_crop L\n");
++}
++
++/**
++ * prev_get_status - Get status of ISP preview module
++ * @status: Structure containing the busy state.
++ *
++ * Checks if the ISP preview module is busy.
++ *
++ * Returns 0 if successful, or -EINVAL if the status parameter is invalid.
++ **/
++static int prev_get_status(struct prev_status *status)
++{
++	if (!status) {
++		dev_err(prev_dev, "get_status: invalid parameter\n");
++		return -EINVAL;
++	}
++	status->hw_busy = (char)isppreview_busy();
++	return 0;
++}
++
++/**
++ * prev_hw_setup - Stores the desired configuration in the proper HW registers
++ * @config: Structure containing the desired configuration for ISP preview
++ *          module.
++ *
++ * Reads the structure sent, and modifies the desired registers.
++ *
++ * Always returns 0.
++ **/
++static int prev_hw_setup(struct prev_params *config)
++{
++	dev_dbg(prev_dev, "prev_hw_setup E\n");
++
++	if (config->features & PREV_AVERAGER)
++		isppreview_config_averager(config->average);
++	else
++		isppreview_config_averager(0);
++
++	if (config->features & PREV_INVERSE_ALAW)
++		isppreview_enable_invalaw(1);
++	else
++		isppreview_enable_invalaw(0);
++
++	if (config->features & PREV_HORZ_MEDIAN_FILTER) {
++		isppreview_config_hmed(config->hmf_params);
++		isppreview_enable_hmed(1);
++	} else
++		isppreview_enable_hmed(0);
++
++	if (config->features & PREV_DARK_FRAME_SUBTRACT) {
++		isppreview_set_darkaddr(config->drkf_params.addr);
++		isppreview_config_darklineoffset(config->drkf_params.offset);
++		isppreview_enable_drkframe(1);
++	} else
++		isppreview_enable_drkframe(0);
++
++	if (config->features & PREV_LENS_SHADING) {
++		isppreview_config_drkf_shadcomp(config->lens_shading_shift);
++		isppreview_enable_shadcomp(1);
++	} else
++		isppreview_enable_shadcomp(0);
++
++	dev_dbg(prev_dev, "prev_hw_setup L\n");
++	return 0;
++}
++
++/**
++ * prev_validate_params - Validate configuration parameters for Preview Wrapper
++ * @params: Structure containing configuration parameters
++ *
++ * Validate configuration parameters for Preview Wrapper
++ *
++ * Returns 0 if successful, or -EINVAL if a parameter value is invalid.
++ **/
++static int prev_validate_params(struct prev_params *params)
++{
++	if (!params) {
++		dev_err(prev_dev, "validate_params: error in argument");
++		goto err_einval;
++	}
++
++	if ((params->features & PREV_AVERAGER) == PREV_AVERAGER) {
++		if ((params->average != NO_AVE)
++					&& (params->average != AVE_2_PIX)
++					&& (params->average != AVE_4_PIX)
++					&& (params->average != AVE_8_PIX)) {
++			dev_err(prev_dev, "validate_params: wrong pix "
++								"average\n");
++			goto err_einval;
++		} else if (((params->average == AVE_2_PIX)
++					&& (params->size_params.hsize % 2))
++					|| ((params->average == AVE_4_PIX)
++					&& (params->size_params.hsize % 4))
++					|| ((params->average == AVE_8_PIX)
++					&& (params->size_params.hsize % 8))) {
++			dev_err(prev_dev, "validate_params: "
++					"wrong pix average for input size\n");
++			goto err_einval;
++		}
++	}
++
++	if ((params->size_params.pixsize != PREV_INWIDTH_8BIT)
++					&& (params->size_params.pixsize
++					!= PREV_INWIDTH_10BIT)) {
++		dev_err(prev_dev, "validate_params: wrong pixsize\n");
++		goto err_einval;
++	}
++
++	if (params->size_params.hsize > MAX_IMAGE_WIDTH
++					|| params->size_params.hsize < 0) {
++		dev_err(prev_dev, "validate_params: wrong hsize\n");
++		goto err_einval;
++	}
++
++	if ((params->pix_fmt != YCPOS_YCrYCb)
++					&& (YCPOS_YCbYCr != params->pix_fmt)
++					&& (YCPOS_CbYCrY != params->pix_fmt)
++					&& (YCPOS_CrYCbY != params->pix_fmt)) {
++		dev_err(prev_dev, "validate_params: wrong pix_fmt");
++		goto err_einval;
++	}
++
++	if ((params->features & PREV_DARK_FRAME_SUBTRACT)
++						&& (params->features
++						& PREV_DARK_FRAME_CAPTURE)) {
++		dev_err(prev_dev, "validate_params: DARK FRAME CAPTURE and "
++						"SUBSTRACT cannot be enabled "
++						"at same time\n");
++		goto err_einval;
++	}
++
++	if (params->features & PREV_DARK_FRAME_SUBTRACT)
++		if (!params->drkf_params.addr
++					|| (params->drkf_params.offset % 32)) {
++			dev_err(prev_dev, "validate_params: dark frame "
++								"address\n");
++			goto err_einval;
++		}
++
++	if (params->features & PREV_LENS_SHADING)
++		if ((params->lens_shading_shift > 7)
++					|| !params->drkf_params.addr
++					|| (params->drkf_params.offset % 32)) {
++			dev_err(prev_dev, "validate_params: lens shading "
++								"shift\n");
++			goto err_einval;
++		}
++
++	if ((params->size_params.in_pitch <= 0)
++				|| (params->size_params.in_pitch % 32)) {
++		params->size_params.in_pitch =
++				(params->size_params.hsize * 2) & 0xFFE0;
++		dev_err(prev_dev, "\nError in in_pitch; new value = %d",
++						params->size_params.in_pitch);
++	}
++
++	return 0;
++err_einval:
++	return -EINVAL;
++}
++
++/**
++ * preview_isr - Callback from ISP driver for ISP Preview Interrupt
++ * @status: ISP IRQ0STATUS register value
++ * @arg1: Structure containing ISP preview wrapper global information
++ * @arg2: Currently not used
++ **/
++static void preview_isr(unsigned long status, isp_vbq_callback_ptr arg1,
++								void *arg2)
++{
++	struct prev_device *device = (struct prev_device *)arg1;
++
++	if ((status & PREV_DONE) != PREV_DONE)
++		return;
++
++	if (device)
++		complete(&device->wfc);
++}
++
++/**
++ * prev_do_preview - Performs the Preview process
++ * @device: Structure containing ISP preview wrapper global information
++ * @arg: Currently not used
++ *
++ * Returns 0 if successful, or -EINVAL if the sent parameters are invalid.
++ **/
++static int prev_do_preview(struct prev_device *device, int *arg)
++{
++	int bpp, size;
++	int ret = 0;
++	u32 out_hsize, out_vsize, out_line_offset;
++
++	dev_dbg(prev_dev, "prev_do_preview E\n");
++
++	if (!device) {
++		dev_err(prev_dev, "preview: invalid parameters\n");
++		return -EINVAL;
++	}
++
++	if (device->params->size_params.pixsize == PREV_INWIDTH_8BIT)
++		bpp = 1;
++	else
++		bpp = 2;
++
++	size = device->params->size_params.hsize *
++		device->params->size_params.vsize * bpp;
++
++	ret = isppreview_set_inaddr(device->isp_addr_read);
++	if (ret)
++		goto out;
++
++	ret = isppreview_set_outaddr(device->isp_addr_read);
++	if (ret)
++		goto out;
++
++	isppreview_try_size(device->params->size_params.hsize,
++					device->params->size_params.vsize,
++					&out_hsize, &out_vsize);
++
++	ret = isppreview_config_inlineoffset(device->params->size_params.hsize
++						* bpp);
++	if (ret)
++		goto out;
++
++	out_line_offset = (out_hsize * bpp) & PREV_32BYTES_ALIGN_MASK;
++
++	ret = isppreview_config_outlineoffset(out_line_offset);
++	if (ret)
++		goto out;
++
++	ret = isppreview_config_size(device->params->size_params.hsize,
++					device->params->size_params.vsize,
++					out_hsize, out_vsize);
++	if (ret)
++		goto out;
++
++	isppreview_config_datapath(PRV_RAW_MEM, PREVIEW_MEM);
++
++	ret = isp_set_callback(CBK_PREV_DONE, preview_isr, (void *)device,
++								(void *)NULL);
++	if (ret) {
++		dev_err(prev_dev, "ERROR while setting Previewer callback!\n");
++		goto out;
++	}
++	isppreview_enable(1);
++
++	wait_for_completion_interruptible(&device->wfc);
++
++	if (device->isp_addr_read) {
++		ispmmu_unmap(device->isp_addr_read);
++		device->isp_addr_read = 0;
++	}
++
++	ret = isp_unset_callback(CBK_PREV_DONE);
++
++	dev_dbg(prev_dev, "prev_do_preview L\n");
++out:
++	return ret;
++}
++
++/**
++ * previewer_vbq_release - Videobuffer queue release
++ * @q: Structure containing the videobuffer queue.
++ * @vb: Structure containing the videobuffer used for previewer processing.
++ **/
++static void previewer_vbq_release(struct videobuf_queue *q,
++						struct videobuf_buffer *vb)
++{
++	struct prev_fh *fh = q->priv_data;
++	struct prev_device *device = fh->device;
++
++	ispmmu_unmap(device->isp_addr_read);
++	device->isp_addr_read = 0;
++	spin_lock(&device->vbq_lock);
++	vb->state = VIDEOBUF_NEEDS_INIT;
++	spin_unlock(&device->vbq_lock);
++	dev_dbg(prev_dev, "previewer_vbq_release\n");
++}
++
++/**
++ * previewer_vbq_setup - Sets up the videobuffer size and validates count.
++ * @q: Structure containing the videobuffer queue.
++ * @cnt: Number of buffers requested
++ * @size: Size in bytes of the buffer used for previewing
++ *
++ * Always returns 0.
++ **/
++static int previewer_vbq_setup(struct videobuf_queue *q,
++							unsigned int *cnt,
++							unsigned int *size)
++{
++	struct prev_fh *fh = q->priv_data;
++	struct prev_device *device = fh->device;
++	u32 bpp = 1;
++
++	spin_lock(&device->vbq_lock);
++	if (*cnt <= 0)
++		*cnt = VIDEO_MAX_FRAME;
++
++	if (*cnt > VIDEO_MAX_FRAME)
++		*cnt = VIDEO_MAX_FRAME;
++
++	if (!device->params->size_params.hsize ||
++		!device->params->size_params.vsize) {
++		dev_err(prev_dev, "Can't setup buffer size\n");
++		spin_unlock(&device->vbq_lock);
++		return -EINVAL;
++	}
++
++	if (device->params->size_params.pixsize == PREV_INWIDTH_10BIT)
++		bpp = 2;
++	*size = prev_bufsize = bpp * device->params->size_params.hsize
++					* device->params->size_params.vsize;
++	spin_unlock(&device->vbq_lock);
++	dev_dbg(prev_dev, "previewer_vbq_setup\n");
++	return 0;
++}
++
++/**
++ * previewer_vbq_prepare - Videobuffer is prepared and mmapped.
++ * @q: Structure containing the videobuffer queue.
++ * @vb: Structure containing the videobuffer used for previewer processing.
++ * @field: Type of field to set in videobuffer device.
++ *
++ * Returns 0 if successful, or -EINVAL if buffer couldn't get allocated, or
++ * -EIO if the ISP MMU mapping fails
++ **/
++static int previewer_vbq_prepare(struct videobuf_queue *q,
++						struct videobuf_buffer *vb,
++						enum v4l2_field field)
++{
++	struct prev_fh *fh = q->priv_data;
++	struct prev_device *device = fh->device;
++	int err = -EINVAL;
++	unsigned int isp_addr;
++	struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
++
++	dev_dbg(prev_dev, "previewer_vbq_prepare E\n");
++	spin_lock(&device->vbq_lock);
++	if (vb->baddr) {
++		vb->size = prev_bufsize;
++		vb->bsize = prev_bufsize;
++	} else {
++		spin_unlock(&device->vbq_lock);
++		dev_err(prev_dev, "No user buffer allocated\n");
++		goto out;
++	}
++
++	vb->width = device->params->size_params.hsize;
++	vb->height = device->params->size_params.vsize;
++	vb->field = field;
++	spin_unlock(&device->vbq_lock);
++
++	if (vb->state == VIDEOBUF_NEEDS_INIT) {
++		err = videobuf_iolock(q, vb, NULL);
++		if (!err) {
++			isp_addr = ispmmu_map_sg(dma->sglist, dma->sglen);
++			if (!isp_addr)
++				err = -EIO;
++			else
++				device->isp_addr_read = isp_addr;
++		}
++	}
++
++	if (!err) {
++		vb->state = VIDEOBUF_PREPARED;
++		flush_cache_user_range(NULL, vb->baddr,
++					(vb->baddr + vb->bsize));
++	} else
++		previewer_vbq_release(q, vb);
++
++	dev_dbg(prev_dev, "previewer_vbq_prepare L\n");
++out:
++	return err;
++}
++
++static void previewer_vbq_queue(struct videobuf_queue *q,
++						struct videobuf_buffer *vb)
++{
++	return;
++}
++
++/**
++ * previewer_open - Initializes and opens the Preview Wrapper
++ * @inode: Inode structure associated with the Preview Wrapper
++ * @filp: File structure associated with the Preview Wrapper
++ *
++ * Returns 0 if successful, -EACCES if its unable to initialize default config,
++ * -EBUSY if its already opened or the ISP module is not available, or -ENOMEM
++ * if its unable to allocate the device in kernel space memory.
++ **/
++static int previewer_open(struct inode *inode, struct file *filp)
++{
++	int ret = 0;
++	struct prev_device *device = prevdevice;
++	struct prev_params *config = isppreview_get_config();
++	struct prev_fh *fh;
++
++	if (config == NULL) {
++		dev_err(prev_dev, "Unable to initialize default config "
++			"from isppreviewer\n\n");
++		return -EACCES;
++	}
++
++	if (device->opened || (filp->f_flags & O_NONBLOCK)) {
++		dev_err(prev_dev, "previewer_open: device is already "
++								"opened\n");
++		return -EBUSY;
++	}
++
++	fh = kzalloc(sizeof(struct prev_fh), GFP_KERNEL);
++	if (NULL == fh)
++		return -ENOMEM;
++
++	isp_get();
++	ret = isppreview_request();
++	if (ret) {
++		isp_put();
++		dev_err(prev_dev, "Can't acquire isppreview\n");
++		return ret;
++	}
++
++	device->params = config;
++	device->opened = 1;
++
++	filp->private_data = fh;
++	fh->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	fh->device = device;
++
++	videobuf_queue_pci_init(&fh->vbq, &device->vbq_ops, NULL,
++					&device->vbq_lock, fh->type,
++					V4L2_FIELD_NONE,
++					sizeof(struct videobuf_buffer), fh);
++
++	init_completion(&device->wfc);
++	device->wfc.done = 0;
++	mutex_init(&device->prevwrap_mutex);
++
++	return 0;
++}
++
++/**
++ * previewer_release - Releases Preview Wrapper and frees up allocated memory
++ * @inode: Inode structure associated with the Preview Wrapper
++ * @filp: File structure associated with the Preview Wrapper
++ *
++ * Always returns 0.
++ **/
++static int previewer_release(struct inode *inode, struct file *filp)
++{
++	struct prev_fh *fh = filp->private_data;
++	struct prev_device *device = fh->device;
++	struct videobuf_queue *q = &fh->vbq;
++
++	device->opened = 0;
++	device->params = NULL;
++	isppreview_free();
++	isp_put();
++	videobuf_mmap_free(q);
++	prev_bufsize = 0;
++	filp->private_data = NULL;
++	kfree(fh);
++
++	dev_dbg(prev_dev, "previewer_release\n");
++	return 0;
++}
++
++/**
++ * previewer_mmap - Memory maps the Preview Wrapper module.
++ * @file: File structure associated with the Preview Wrapper
++ * @vma: Virtual memory area structure.
++ *
++ * Returns 0 if successful, or returned value by the videobuf_mmap_mapper()
++ * function.
++ **/
++static int previewer_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	struct prev_fh *fh = file->private_data;
++	dev_dbg(prev_dev, "previewer_mmap\n");
++
++	return videobuf_mmap_mapper(&fh->vbq, vma);
++}
++
++/**
++ * previewer_ioctl - I/O control function for Preview Wrapper
++ * @inode: Inode structure associated with the Preview Wrapper.
++ * @file: File structure associated with the Preview Wrapper.
++ * @cmd: Type of command to execute.
++ * @arg: Argument to send to requested command.
++ *
++ * Returns 0 if successful, -1 if bad command passed or access is denied,
++ * -EFAULT if copy_from_user() or copy_to_user() fails, -EINVAL if parameter
++ * validation fails or parameter structure is not present
++ **/
++static int previewer_ioctl(struct inode *inode, struct file *file,
++					unsigned int cmd, unsigned long arg)
++{
++	int ret = 0;
++	struct prev_params params;
++	struct prev_fh *fh = file->private_data;
++	struct prev_device *device = fh->device;
++
++	dev_dbg(prev_dev, "Entering previewer_ioctl()\n");
++
++	if ((_IOC_TYPE(cmd) != PREV_IOC_BASE)
++					|| (_IOC_NR(cmd) > PREV_IOC_MAXNR)) {
++		dev_err(prev_dev, "Bad command Value \n");
++		goto err_minusone;
++	}
++
++	if (_IOC_DIR(cmd) & _IOC_READ)
++		ret = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
++	else if (_IOC_DIR(cmd) & _IOC_WRITE)
++		ret = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
++	if (ret) {
++		dev_err(prev_dev, "access denied\n");
++		goto err_minusone;
++	}
++
++	switch (cmd) {
++	case PREV_REQBUF:
++		if (mutex_lock_interruptible(&device->prevwrap_mutex))
++			goto err_eintr;
++		ret = videobuf_reqbufs(&fh->vbq, (void *)arg);
++		mutex_unlock(&device->prevwrap_mutex);
++		break;
++
++	case PREV_QUERYBUF:
++		if (mutex_lock_interruptible(&device->prevwrap_mutex))
++			goto err_eintr;
++		ret = videobuf_querybuf(&fh->vbq, (void *)arg);
++		mutex_unlock(&device->prevwrap_mutex);
++		break;
++
++	case PREV_QUEUEBUF:
++		if (mutex_lock_interruptible(&device->prevwrap_mutex))
++			goto err_eintr;
++		ret = videobuf_qbuf(&fh->vbq, (void *)arg);
++		mutex_unlock(&device->prevwrap_mutex);
++		break;
++
++	case PREV_SET_PARAM:
++		if (mutex_lock_interruptible(&device->prevwrap_mutex))
++			goto err_eintr;
++		if (copy_from_user(&params, (struct prev_params *)arg,
++						sizeof(struct prev_params))) {
++			mutex_unlock(&device->prevwrap_mutex);
++			return -EFAULT;
++		}
++		ret = prev_validate_params(&params);
++		if (ret < 0) {
++			dev_err(prev_dev, "Error validating parameters!\n");
++			mutex_unlock(&device->prevwrap_mutex);
++			goto out;
++		}
++		if (device->params)
++			memcpy(device->params, &params,
++						sizeof(struct prev_params));
++		else {
++			mutex_unlock(&device->prevwrap_mutex);
++			return -EINVAL;
++		}
++
++		ret = prev_hw_setup(device->params);
++		mutex_unlock(&device->prevwrap_mutex);
++		break;
++
++	case PREV_GET_PARAM:
++		if (copy_to_user((struct prev_params *)arg, device->params,
++						sizeof(struct prev_params)))
++			ret = -EFAULT;
++		break;
++
++	case PREV_GET_STATUS:
++		ret = prev_get_status((struct prev_status *)arg);
++		break;
++
++	case PREV_PREVIEW:
++		if (mutex_lock_interruptible(&device->prevwrap_mutex))
++			goto err_eintr;
++		ret = prev_do_preview(device, (int *)arg);
++		mutex_unlock(&device->prevwrap_mutex);
++		break;
++
++	case PREV_GET_CROPSIZE:
++		{
++		struct prev_cropsize outputsize;
++		prev_calculate_crop(device, &outputsize);
++		if (copy_to_user((struct prev_cropsize *)arg, &outputsize,
++						sizeof(struct prev_cropsize)))
++			ret = -EFAULT;
++		}
++		break;
++
++	default:
++		dev_err(prev_dev, "previewer_ioctl: Invalid Command Value\n");
++		ret = -EINVAL;
++	}
++out:
++	return ret;
++err_minusone:
++	return -1;
++err_eintr:
++	return -EINTR;
++}
++
++/**
++ * previewer_platform_release - Acts when Reference count is zero
++ * @device: Structure containing ISP preview wrapper global information
++ *
++ * This is called when the reference count goes to zero
++ **/
++static void previewer_platform_release(struct device *device)
++{
++	dev_dbg(prev_dev, "previewer_platform_release()\n");
++}
++
++static struct file_operations prev_fops = {
++	.owner = THIS_MODULE,
++	.open = previewer_open,
++	.release = previewer_release,
++	.mmap = previewer_mmap,
++	.ioctl = previewer_ioctl,
++};
++
++static struct platform_device omap_previewer_device = {
++	.name = OMAP_PREV_NAME,
++	.id = -1,
++	.dev = {
++		.release = previewer_platform_release,
++	}
++};
++
++/**
++ * previewer_probe - Checks for device presence
++ * @pdev: Structure containing details of the current device.
++ *
++ * Always returns 0
++ **/
++static int __init previewer_probe(struct platform_device *pdev)
++{
++	return 0;
++}
++
++/**
++ * previewer_remove - Handles the removal of the driver
++ * @pdev: Structure containing details of the current device.
++ *
++ * Always returns 0.
++ **/
++static int previewer_remove(struct platform_device *pdev)
++{
++	dev_dbg(prev_dev, "previewer_remove()\n");
++
++	platform_device_unregister(&omap_previewer_device);
++	platform_driver_unregister(&omap_previewer_driver);
++	unregister_chrdev(prev_major, OMAP_PREV_NAME);
++	return 0;
++}
++
++static struct platform_driver omap_previewer_driver = {
++	.probe = previewer_probe,
++	.remove = previewer_remove,
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = OMAP_PREV_NAME,
++	},
++};
++
++/**
++ * omap_previewer_init - Initialization of Preview Wrapper
++ *
++ * Returns 0 if successful, -ENOMEM if could not allocate memory, -ENODEV if
++ * could not register the wrapper as a character device, or other errors if the
++ * device or driver can't register.
++ **/
++static int __init omap_previewer_init(void)
++{
++	int ret;
++	struct prev_device *device;
++
++	device = kzalloc(sizeof(struct prev_device), GFP_KERNEL);
++	if (!device) {
++		dev_err(prev_dev, OMAP_PREV_NAME ": could not allocate"
++								" memory\n");
++		return -ENOMEM;
++	}
++	prev_major = register_chrdev(0, OMAP_PREV_NAME, &prev_fops);
++
++	if (prev_major < 0) {
++		dev_err(prev_dev, OMAP_PREV_NAME ": initialization "
++				"failed. could not register character "
++				"device\n");
++		return -ENODEV;
++	}
++
++	ret = platform_driver_register(&omap_previewer_driver);
++	if (ret) {
++		dev_err(prev_dev, OMAP_PREV_NAME
++			": failed to register platform driver!\n");
++		goto fail2;
++	}
++	ret = platform_device_register(&omap_previewer_device);
++	if (ret) {
++		dev_err(prev_dev, OMAP_PREV_NAME
++			": failed to register platform device!\n");
++		goto fail3;
++	}
++
++	prev_class = class_create(THIS_MODULE, OMAP_PREV_NAME);
++	if (!prev_class)
++		goto fail4;
++
++	prev_dev = device_create(prev_class, prev_dev, (MKDEV(prev_major, 0)),
++				OMAP_PREV_NAME);
++	dev_dbg(prev_dev, OMAP_PREV_NAME ": Registered Previewer Wrapper\n");
++	device->opened = 0;
++
++	device->vbq_ops.buf_setup = previewer_vbq_setup;
++	device->vbq_ops.buf_prepare = previewer_vbq_prepare;
++	device->vbq_ops.buf_release = previewer_vbq_release;
++	device->vbq_ops.buf_queue = previewer_vbq_queue;
++	spin_lock_init(&device->vbq_lock);
++
++	prevdevice = device;
++	return 0;
++
++fail4:
++	platform_device_unregister(&omap_previewer_device);
++fail3:
++	platform_driver_unregister(&omap_previewer_driver);
++fail2:
++	unregister_chrdev(prev_major, OMAP_PREV_NAME);
++
++	return ret;
++}
++
++/**
++ * omap_previewer_exit - Close of Preview Wrapper
++ **/
++static void __exit omap_previewer_exit(void)
++{
++	previewer_remove(&omap_previewer_device);
++	kfree(prevdevice);
++	prev_major = -1;
++}
++
++module_init(omap_previewer_init);
++module_exit(omap_previewer_exit);
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("OMAP ISP Previewer");
++MODULE_LICENSE("GPL");
+Index: git/drivers/media/video/isp/omap_previewer.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/omap_previewer.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,136 @@
++/*
++ * drivers/media/video/isp/omap_previewer.h
++ *
++ * Include file for Preview module wrapper in TI's OMAP3430 ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include "isppreview.h"
++
++#ifndef OMAP_ISP_PREVIEW_WRAP_H
++#define OMAP_ISP_PREVIEW_WRAP_H
++
++#define PREV_IOC_BASE			'P'
++#define PREV_REQBUF			_IOWR(PREV_IOC_BASE, 1,\
++						struct v4l2_requestbuffers)
++#define PREV_QUERYBUF			_IOWR(PREV_IOC_BASE, 2,\
++							struct v4l2_buffer)
++#define PREV_SET_PARAM			_IOW(PREV_IOC_BASE, 3,\
++							struct prev_params)
++#define PREV_GET_PARAM			_IOWR(PREV_IOC_BASE, 4,\
++							struct prev_params)
++#define PREV_PREVIEW			_IOR(PREV_IOC_BASE, 5, int)
++#define PREV_GET_STATUS			_IOR(PREV_IOC_BASE, 6, char)
++#define PREV_GET_CROPSIZE		_IOR(PREV_IOC_BASE, 7,\
++							struct prev_cropsize)
++#define PREV_QUEUEBUF			_IOWR(PREV_IOC_BASE, 8,\
++							struct v4l2_buffer)
++#define PREV_IOC_MAXNR    8
++
++#define LUMA_TABLE_SIZE			128
++#define GAMMA_TABLE_SIZE		1024
++#define CFA_COEFF_TABLE_SIZE		576
++#define NOISE_FILTER_TABLE_SIZE		256
++
++#define MAX_IMAGE_WIDTH			3300
++
++#define PREV_INWIDTH_8BIT		0	/* pixel width of 8 bitS */
++#define PREV_INWIDTH_10BIT		1	/* pixel width of 10 bits */
++
++#define PREV_32BYTES_ALIGN_MASK		0xFFFFFFE0
++#define PREV_16PIX_ALIGN_MASK		0xFFFFFFF0
++
++/* list of structures */
++
++/* structure for RGB2RGB blending parameters */
++struct prev_rgbblending {
++	short blending[RGB_MAX][RGB_MAX];	/* color correlation 3x3
++						 * matrix.
++						 */
++	short offset[RGB_MAX];			/* color correlation offsets */
++};
++
++/* structure for CFA coefficients */
++struct prev_cfa_coeffs {
++	char hthreshold, vthreshold;		/* horizontal an vertical
++						 * threshold.
++						 */
++	int coeffs[CFA_COEFF_TABLE_SIZE];	/* cfa coefficients */
++};
++/* structure for Gamma Coefficients */
++struct prev_gamma_coeffs {
++	unsigned char red[GAMMA_TABLE_SIZE];	/* table of gamma correction
++						 * values for red color.
++						 */
++	unsigned char green[GAMMA_TABLE_SIZE];	/* table of gamma correction
++						 * values for green color.
++						 */
++	unsigned char blue[GAMMA_TABLE_SIZE];	/* table of gamma correction
++						 * values for blue color.
++						 */
++};
++/* Structure for Noise Filter Coefficients */
++struct prev_noiseflt_coeffs {
++	unsigned char noise[NOISE_FILTER_TABLE_SIZE];	/* noise filter
++							 * table.
++							 */
++	unsigned char strength;				/* to find out
++							 * weighted average.
++							 */
++};
++
++/* Structure for Chroma Suppression */
++struct prev_chroma_spr {
++	unsigned char hpfy;			/* whether to use high passed
++						 * version of Y or normal Y
++						 */
++	char threshold;				/* threshold for chroma
++						 * suppress.
++						 */
++	unsigned char gain;			/* chroma suppression gain */
++};
++
++/* structure to know status of the hardware */
++struct prev_status {
++	char hw_busy;
++};
++/* structure to knwo crop size */
++struct prev_cropsize {
++	int hcrop;
++	int vcrop;
++};
++
++
++/* device structure keeps track of global information */
++struct prev_device {
++	struct prev_params *params;
++	unsigned char opened;			/* state of the device */
++
++	struct completion wfc;
++	struct mutex prevwrap_mutex;
++
++	spinlock_t vbq_lock;			/* spinlock for videobuf
++						 * queues.
++						 */
++	struct videobuf_queue_ops vbq_ops;	/* videobuf queue operations */
++
++	dma_addr_t isp_addr_read;		/* Input/Output address */
++
++};
++
++/* per-filehandle data structure */
++struct prev_fh {
++	enum v4l2_buf_type type;
++	struct videobuf_queue vbq;
++	struct prev_device *device;
++};
++#endif
+Index: git/drivers/media/video/isp/omap_resizer.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/omap_resizer.c	2009-02-12 14:48:11.000000000 -0600
+@@ -0,0 +1,1812 @@
++/*
++ * drivers/media/video/isp/omap_resizer.c
++ *
++ * Wrapper for Resizer module in TI's OMAP3430 ISP
++ *
++ * Copyright (C) 2007 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#include <linux/mutex.h>
++#include <linux/cdev.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/time.h>
++#include <media/v4l2-dev.h>
++#include <asm/cacheflush.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++#include <mach/io.h>
++#include <asm/scatterlist.h>
++#include <linux/pci.h>
++#include "isp.h"
++#include "ispmmu.h"
++#include "ispreg.h"
++#include "ispresizer.h"
++#include <linux/omap_resizer.h>
++
++#define OMAP_REZR_NAME		"omap-resizer"
++
++/* Defines and Constants*/
++#define MAX_CHANNELS		16
++#define MAX_IMAGE_WIDTH		2047
++#define MAX_IMAGE_WIDTH_HIGH	2047
++#define ALIGNMENT		16
++#define CHANNEL_BUSY		1
++#define CHANNEL_FREE		0
++#define PIXEL_EVEN		2
++#define RATIO_MULTIPLIER	256
++/* Bit position Macro */
++/* macro for bit set and clear */
++#define BITSET(variable, bit)	(variable) | (1 << bit)
++#define BITRESET(variable, bit)	(variable) & ~(0x00000001 << (bit))
++#define SET_BIT_INPUTRAM	28
++#define SET_BIT_CBLIN		29
++#define SET_BIT_INPTYP		27
++#define SET_BIT_YCPOS		26
++#define INPUT_RAM		1
++#define UP_RSZ_RATIO		64
++#define DOWN_RSZ_RATIO		512
++#define UP_RSZ_RATIO1		513
++#define DOWN_RSZ_RATIO1		1024
++#define RSZ_IN_SIZE_VERT_SHIFT	16
++#define MAX_HORZ_PIXEL_8BIT	31
++#define MAX_HORZ_PIXEL_16BIT	15
++#define NUM_PHASES		8
++#define NUM_TAPS		4
++#define NUM_D2PH		4	/* for downsampling * 2+x ~ 4x,
++				    	 * number of phases
++					 */
++#define NUM_D2TAPS		7 	/* for downsampling * 2+x ~ 4x,
++					 * number of taps
++					 */
++#define ALIGN32			32
++#define MAX_COEF_COUNTER	16
++#define COEFF_ADDRESS_OFFSET	0x04
++
++#define RSZ_DEF_REQ_EXP		0xE	/* Default read operation expand
++					 * for the Resizer driver; value
++					 * taken from Davinci.
++					 */
++/*
++ * These magic numbers are copied from video-buf layer,
++ * since they gets set in to the same layer. To support
++ * contiguous memory and to remove max buffer size constraint from
++ * application, we implemented replication of some video-buf functions
++ * so magic numbers also.
++ */
++#define MAGIC_BUFFER 0x20070728
++#define MAGIC_DMABUF 0x19721112
++#define MAGIC_SG_MEM 0x17890714
++#define MAGIC_CHECK(is,should)	if (unlikely((is) != (should))) \
++	{ printk(KERN_ERR "magic mismatch: %x (expected %x)\n",is,should); BUG(); }
++
++/* Global structure which contains information about number of channels
++   and protection variables */
++struct device_params {
++
++	struct mutex reszwrap_mutex;		/* Semaphore for array */
++	struct completion compl_isr;		/* Completion for interrupt */
++	struct videobuf_queue_ops vbq_ops;	/* videobuf queue operations */
++};
++
++/* Register mapped structure which contains the every register
++   information */
++struct resizer_config {
++	u32 rsz_pcr;				/* pcr register mapping
++						 * variable.
++						 */
++	u32 rsz_in_start;			/* in_start register mapping
++						 * variable.
++						 */
++	u32 rsz_in_size;			/* in_size register mapping
++						 * variable.
++						 */
++	u32 rsz_out_size;			/* out_size register mapping
++						 * variable.
++						 */
++	u32 rsz_cnt;				/* rsz_cnt register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_inadd;			/* sdr_inadd register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_inoff;			/* sdr_inoff register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_outadd;			/* sdr_outadd register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_outoff;			/* sdr_outbuff register
++						 * mapping variable.
++						 */
++	u32 rsz_coeff_horz[16];			/* horizontal coefficients
++						 * mapping array.
++						 */
++	u32 rsz_coeff_vert[16];			/* vertical coefficients
++						 * mapping array.
++						 */
++	u32 rsz_yehn;				/* yehn(luma)register mapping
++						 * variable.
++						 */
++	u32 sdr_req_exp;			/* Configuration for Non
++						 * real time read expand
++						 */
++};
++struct rsz_mult {
++	s32 in_hsize;				/* input frame horizontal
++						 * size.
++						 */
++	s32 in_vsize;				/* input frame vertical size.
++						 */
++	s32 out_hsize;				/* output frame horizontal
++						 * size.
++						 */
++	s32 out_vsize;				/* output frame vertical
++						 * size.
++						 */
++	s32 in_pitch;				/* offset between two rows of
++						 * input frame.
++						 */
++	s32 out_pitch;				/* offset between two rows of
++						 * output frame.
++						 */
++	s32 end_hsize;
++	s32 end_vsize;
++	s32 num_htap;				/* 0 = 7tap; 1 = 4tap */
++	s32 num_vtap;				/* 0 = 7tap; 1 = 4tap */
++	s32 active;
++	s32 inptyp;
++	s32 vrsz;
++	s32 hrsz;
++	s32 hstph;				/* for specifying horizontal
++						 * starting phase.
++						 */
++	s32 vstph;
++	s32 pix_fmt;				/* # defined, UYVY or YUYV. */
++	s32 cbilin;				/* # defined, filter with luma
++						 * or bi-linear.
++						 */
++	u16 tap4filt_coeffs[32];		/* horizontal filter
++						 * coefficients.
++						 */
++	u16 tap7filt_coeffs[32];		/* vertical filter
++						 * coefficients.
++						 */
++};
++/* Channel specific structure contains information regarding
++   the every channel */
++struct channel_config {
++	struct resizer_config register_config;	/* Instance of register set
++						 * mapping structure
++						 */
++	int status;				/* Specifies whether the
++						 * channel is busy or not
++						 */
++	struct mutex chanprotection_mutex;	/* Pointer to channel
++						 * specific protection
++						 */
++	int buf_address[VIDEO_MAX_FRAME];
++	enum config_done config_state;
++	u8 input_buf_index, output_buf_index;
++
++};
++
++/* per-filehandle data structure */
++struct rsz_fh {
++	struct rsz_params *params;
++	struct channel_config *config;		/* Pointer to channel
++						 * configuration.
++						 */
++	enum v4l2_buf_type type;
++	struct videobuf_queue vbq;
++	struct device_params *device;
++	dma_addr_t isp_addr_read;		/* Input/Output address */
++	dma_addr_t isp_addr_write;		/* Input/Output address */
++	struct rsz_mult *multipass;		/* Multipass to support
++						 * resizing ration outside
++						 * of 0.25x to 4x
++						 */
++	spinlock_t vbq_lock;			/* spinlock for videobuf
++						 * queues.
++						 */
++	u32 rsz_bufsize;			/* channel specific buffersize
++						 */
++};
++
++static struct device_params *device_config;
++static struct device *rsz_device;
++static int rsz_major = -1;
++/* functions declaration */
++static void rsz_hardware_setup(struct channel_config *rsz_conf_chan);
++static int rsz_set_params(struct rsz_mult *multipass, struct rsz_params *,
++						struct channel_config *);
++static int rsz_get_params(struct rsz_params *, struct channel_config *);
++static void rsz_copy_data(struct rsz_mult *multipass,
++						struct rsz_params *params);
++static void rsz_isr(unsigned long status, isp_vbq_callback_ptr arg1,
++						void *arg2);
++static void rsz_calculate_crop(struct channel_config *rsz_conf_chan,
++                                                struct rsz_cropsize *cropsize);
++static int rsz_set_multipass(struct rsz_mult *multipass,
++					struct channel_config *rsz_conf_chan);
++static int rsz_set_ratio(struct rsz_mult *multipass,
++					struct channel_config *rsz_conf_chan);
++static void rsz_config_ratio(struct rsz_mult *multipass,
++					struct channel_config *rsz_conf_chan);
++
++/*
++ * resizer_busy - Enables the Resizer driver
++ */
++static int inline resizer_busy(void)
++{
++	return (omap_readl(ISPRSZ_PCR) & ISPPRV_PCR_BUSY);
++}
++
++static void inline rsz_set_exp(unsigned int exp)
++{
++	omap_writel(((exp & 0x3FF) << 10), ISPSBL_REG_BASE+0xF8);
++}
++/**
++ * rsz_hardware_setup - Sets hardware configuration registers
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Set hardware configuration registers
++ **/
++static void rsz_hardware_setup(struct channel_config *rsz_conf_chan)
++{
++	int coeffcounter;
++	int coeffoffset = 0;
++
++	omap_writel(rsz_conf_chan->register_config.rsz_cnt, ISPRSZ_CNT);
++
++	omap_writel(rsz_conf_chan->register_config.rsz_in_start,
++			ISPRSZ_IN_START);
++	omap_writel(rsz_conf_chan->register_config.rsz_in_size,
++			ISPRSZ_IN_SIZE);
++
++	omap_writel(rsz_conf_chan->register_config.rsz_out_size,
++			ISPRSZ_OUT_SIZE);
++	omap_writel(rsz_conf_chan->register_config.rsz_sdr_inadd,
++			ISPRSZ_SDR_INADD);
++	omap_writel(rsz_conf_chan->register_config.rsz_sdr_inoff,
++			ISPRSZ_SDR_INOFF);
++	omap_writel(rsz_conf_chan->register_config.rsz_sdr_outadd,
++			ISPRSZ_SDR_OUTADD);
++	omap_writel(rsz_conf_chan->register_config.rsz_sdr_outoff,
++			ISPRSZ_SDR_OUTOFF);
++	omap_writel(rsz_conf_chan->register_config.rsz_yehn, ISPRSZ_YENH);
++
++	for (coeffcounter = 0; coeffcounter < MAX_COEF_COUNTER;
++			coeffcounter++) {
++		omap_writel(rsz_conf_chan->register_config.
++				rsz_coeff_horz[coeffcounter],
++				ISPRSZ_HFILT10 + coeffoffset);
++
++		omap_writel(rsz_conf_chan->register_config.
++				rsz_coeff_vert[coeffcounter],
++				ISPRSZ_VFILT10 + coeffoffset);
++		coeffoffset = coeffoffset + COEFF_ADDRESS_OFFSET;
++	}
++	/* Configure the read expand register */
++	rsz_set_exp(rsz_conf_chan->register_config.sdr_req_exp);
++}
++
++/**
++ * rsz_start - Enables Resizer Wrapper
++ * @arg: Currently not used.
++ * @fh: File structure containing ISP resizer information specific to
++ *      channel opened.
++ *
++ * Submits a resizing task specified by the rsz_resize structure. The call can
++ * either be blocked until the task is completed or returned immediately based
++ * on the value of the blocking argument in the rsz_resize structure. If it is
++ * blocking, the status of the task can be checked by calling ioctl
++ * RSZ_G_STATUS. Only one task can be outstanding for each logical channel.
++ *
++ * Returns 0 if successful, or -EINVAL if could not set callback for RSZR IRQ
++ * event or the state of the channel is not configured.
++ **/
++int rsz_start(int *arg, struct rsz_fh *fh)
++{
++	struct channel_config *rsz_conf_chan = fh->config;
++	struct rsz_mult *multipass = fh->multipass;
++	struct videobuf_queue *q = &fh->vbq;
++	struct videobuf_buffer *buf;
++	int ret;
++
++	if (rsz_conf_chan->config_state) {
++		dev_err(rsz_device, "State not configured \n");
++		goto err_einval;
++	}
++	if(!rsz_conf_chan->register_config.rsz_sdr_inadd ||
++			!rsz_conf_chan->register_config.rsz_sdr_outadd) {
++		dev_err(rsz_device, "address is null\n");
++		goto err_einval;
++	}
++
++	rsz_conf_chan->status = CHANNEL_BUSY;
++	rsz_hardware_setup(rsz_conf_chan);
++	if (isp_set_callback(CBK_RESZ_DONE, rsz_isr, (void *) NULL,
++				(void *)NULL)) {
++		dev_err(rsz_device, "No callback for RSZR\n");
++		goto err_einval;
++	}
++mult:
++	device_config->compl_isr.done = 0;
++	ispresizer_enable(1);
++	ret = wait_for_completion_interruptible(&device_config->compl_isr);
++	if (ret != 0) {
++		dev_dbg(rsz_device, "Unexpected exit from "
++				"wait_for_completion_interruptible\n");
++		wait_for_completion(&device_config->compl_isr);
++	}
++
++	if (multipass->active) {
++		rsz_set_multipass(multipass, rsz_conf_chan);
++		goto mult;
++	}
++
++	rsz_conf_chan->status = CHANNEL_FREE;
++	rsz_conf_chan->register_config.rsz_sdr_outadd = 0;
++	rsz_conf_chan->register_config.rsz_sdr_inadd = 0;
++
++	isp_unset_callback(CBK_RESZ_DONE);
++
++	/* Empty the Videobuf queue which was filled during the qbuf */
++	buf = q->bufs[rsz_conf_chan->input_buf_index];
++	buf->state = VIDEOBUF_IDLE;
++	list_del(&buf->stream);
++	if (rsz_conf_chan->input_buf_index != rsz_conf_chan->output_buf_index) {
++		buf = q->bufs[rsz_conf_chan->output_buf_index];
++		buf->state = VIDEOBUF_IDLE;
++		list_del(&buf->stream);
++	}
++
++	return 0;
++err_einval:
++	return -EINVAL;
++}
++
++/**
++ * rsz_set_multipass - Set resizer multipass
++ * @fh: File structure containing ISP resizer information specific to
++ *      channel opened.
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Returns always 0
++ **/
++static int rsz_set_multipass(struct rsz_mult *multipass,
++				struct channel_config *rsz_conf_chan)
++{
++	multipass->in_hsize = multipass->out_hsize;
++	multipass->in_vsize = multipass->out_vsize;
++	multipass->out_hsize = multipass->end_hsize;
++	multipass->out_vsize = multipass->end_vsize;
++
++	multipass->out_pitch = (multipass->inptyp ? multipass->out_hsize
++			: (multipass->out_hsize * 2));
++	multipass->in_pitch = (multipass->inptyp ? multipass->in_hsize
++			: (multipass->in_hsize * 2));
++
++	rsz_set_ratio(multipass, rsz_conf_chan);
++	rsz_config_ratio(multipass, rsz_conf_chan);
++	rsz_hardware_setup(rsz_conf_chan);
++	return 0;
++}
++
++/**
++ * rsz_copy_data - Copy data
++ * @fh: File structure containing ISP resizer information specific to
++ *      channel opened.
++ * @params: Structure containing the Resizer Wrapper parameters
++ *
++ * Copy data
++ **/
++static void rsz_copy_data(struct rsz_mult *multipass, struct rsz_params *params)
++{
++	int i;
++	multipass->in_hsize = params->in_hsize;
++	multipass->in_vsize = params->in_vsize;
++	multipass->out_hsize = params->out_hsize;
++	multipass->out_vsize = params->out_vsize;
++	multipass->end_hsize = params->out_hsize;
++	multipass->end_vsize = params->out_vsize;
++	multipass->in_pitch = params->in_pitch;
++	multipass->out_pitch = params->out_pitch;
++	multipass->hstph = params->hstph;
++	multipass->vstph = params->vstph;
++	multipass->inptyp = params->inptyp;
++	multipass->pix_fmt = params->pix_fmt;
++	multipass->cbilin = params->cbilin;
++
++	for (i = 0; i < 32; i++) {
++		multipass->tap4filt_coeffs[i] = params->tap4filt_coeffs[i];
++		multipass->tap7filt_coeffs[i] = params->tap7filt_coeffs[i];
++	}
++}
++
++/**
++ * rsz_set_params - Set parameters for resizer wrapper
++ * @fh: File structure containing ISP resizer information specific to
++ *      channel opened.
++ * @params: Structure containing the Resizer Wrapper parameters
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Used to set the parameters of the Resizer hardware, including input and
++ * output image size, horizontal and vertical poly-phase filter coefficients,
++ * luma enchancement filter coefficients, etc.
++ **/
++static int rsz_set_params(struct rsz_mult *multipass, struct rsz_params *params,
++					struct channel_config *rsz_conf_chan)
++{
++	int mul = 1;
++	if(params->yenh_params.type < 0 || params->yenh_params.type > 2) {
++		dev_err(rsz_device, "rsz_set_params:Wrong yenh type\n");
++		return -EINVAL;
++	}
++	if(params->in_vsize <= 0 || params->in_hsize <= 0 ||
++			params->out_vsize <= 0 || params->out_hsize <= 0 ||
++			params->in_pitch <= 0 || params->out_pitch <= 0) {
++		dev_err(rsz_device,"rsz_set_size:invalid size params\n");
++		return -EINVAL;
++	}
++	if((params->inptyp != RSZ_INTYPE_YCBCR422_16BIT) &&
++			(params->inptyp != RSZ_INTYPE_PLANAR_8BIT)){
++		dev_err(rsz_device, "Invalid input type\n");
++		return -EINVAL;
++	}
++	if((params->pix_fmt != RSZ_PIX_FMT_UYVY) &&
++			(params->pix_fmt != RSZ_PIX_FMT_YUYV)) {
++		dev_err(rsz_device, "Invalid pix_fmt\n");
++		return -EINVAL;
++	}
++	if(params->inptyp == RSZ_INTYPE_YCBCR422_16BIT)
++		mul = 2;
++	else
++		mul = 1;
++	if(params->in_pitch < (params->in_hsize * mul)) {
++		dev_err(rsz_device, "pitch is incorrect\n");
++		return -EINVAL;
++	}
++	if(params->out_pitch < (params->out_hsize * mul)) {
++		dev_err(rsz_device,"out pitch is less than out hsize\n");
++		return -EINVAL;
++	}
++	/* Output h size should be even */
++	if((params->out_hsize % PIXEL_EVEN) != 0) {
++		dev_err(rsz_device, "output h size should be even\n");
++		return -EINVAL;
++	}
++	if(params->horz_starting_pixel < 0) {
++		dev_err(rsz_device, "horz start pixel cannot be less \
++				that zero\n");
++		return -EINVAL;
++	}
++
++	rsz_copy_data(multipass, params);
++	if (0 != rsz_set_ratio(multipass, rsz_conf_chan))
++		goto err_einval;
++
++	if(params->yenh_params.type) {
++		if((multipass->num_htap && multipass->out_hsize >
++					1280 ) ||
++				(!multipass->num_htap && multipass->out_hsize >
++				 640))
++			goto err_einval;
++	}
++	if ((multipass->in_pitch) % ALIGN32) {
++		dev_err(rsz_device, "Invalid input pitch: %d \n",
++				multipass->in_pitch);
++		goto err_einval;
++	}
++	if ((multipass->out_pitch) % ALIGN32) {
++		dev_err(rsz_device, "Invalid output pitch %d \n",
++				multipass->out_pitch);
++		goto err_einval;
++	}
++
++	if (INPUT_RAM)
++		params->vert_starting_pixel = 0;
++
++	rsz_conf_chan->register_config.rsz_in_start =
++		(params->vert_starting_pixel
++		 << ISPRSZ_IN_SIZE_VERT_SHIFT)
++		& ISPRSZ_IN_SIZE_VERT_MASK;
++
++	if (params->inptyp == RSZ_INTYPE_PLANAR_8BIT) {
++		if (params->horz_starting_pixel > MAX_HORZ_PIXEL_8BIT)
++			goto err_einval;
++	}
++	if (params->inptyp == RSZ_INTYPE_YCBCR422_16BIT) {
++		if (params->horz_starting_pixel > MAX_HORZ_PIXEL_16BIT)
++			goto err_einval;
++	}
++
++	rsz_conf_chan->register_config.rsz_in_start |=
++		params->horz_starting_pixel
++		& ISPRSZ_IN_START_HORZ_ST_MASK;
++
++	rsz_conf_chan->register_config.rsz_yehn =
++		(params->yenh_params.type
++		 << ISPRSZ_YENH_ALGO_SHIFT)
++		& ISPRSZ_YENH_ALGO_MASK;
++
++	if (params->yenh_params.type) {
++		rsz_conf_chan->register_config.rsz_yehn |=
++			params->yenh_params.core
++			& ISPRSZ_YENH_CORE_MASK;
++
++		rsz_conf_chan->register_config.rsz_yehn |=
++			(params->yenh_params.gain
++			 << ISPRSZ_YENH_GAIN_SHIFT)
++			& ISPRSZ_YENH_GAIN_MASK;
++
++		rsz_conf_chan->register_config.rsz_yehn |=
++			(params->yenh_params.slop
++			 << ISPRSZ_YENH_SLOP_SHIFT)
++			& ISPRSZ_YENH_SLOP_MASK;
++	}
++
++	rsz_config_ratio(multipass, rsz_conf_chan);
++	/* Default value for read expand:Taken from Davinci */
++	rsz_conf_chan->register_config.sdr_req_exp = RSZ_DEF_REQ_EXP;
++
++	rsz_conf_chan->config_state = STATE_CONFIGURED;
++
++	return 0;
++err_einval:
++	return -EINVAL;
++}
++
++/**
++ * rsz_set_ratio - Set ratio
++ * @fh: File structure containing ISP resizer information specific to
++ *      channel opened.
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Returns 0 if successful, -EINVAL if invalid output size, upscaling ratio is
++ * being requested, or other ratio configuration value is out of bounds
++ **/
++static int rsz_set_ratio(struct rsz_mult *multipass,
++				struct channel_config *rsz_conf_chan)
++{
++	int alignment = 0, hrsz, vrsz;
++	rsz_conf_chan->register_config.rsz_cnt = 0;
++	if ((multipass->out_hsize > MAX_IMAGE_WIDTH) ||
++			(multipass->out_vsize > MAX_IMAGE_WIDTH)) {
++		dev_err(rsz_device, "Invalid output size!");
++		goto err_einval;
++	}
++	if (multipass->cbilin) {
++		rsz_conf_chan->register_config.rsz_cnt =
++			BITSET(rsz_conf_chan->register_config.rsz_cnt,
++					SET_BIT_CBLIN);
++	}
++	if (INPUT_RAM) {
++		rsz_conf_chan->register_config.rsz_cnt =
++			BITSET(rsz_conf_chan->register_config.rsz_cnt,
++					SET_BIT_INPUTRAM);
++	}
++	if (multipass->inptyp == RSZ_INTYPE_PLANAR_8BIT) {
++		rsz_conf_chan->register_config.rsz_cnt =
++			BITSET(rsz_conf_chan->register_config.rsz_cnt,
++					SET_BIT_INPTYP);
++	} else {
++		rsz_conf_chan->register_config.rsz_cnt =
++			BITRESET(rsz_conf_chan->register_config.
++					rsz_cnt, SET_BIT_INPTYP);
++		if (multipass->pix_fmt == RSZ_PIX_FMT_UYVY) {
++			rsz_conf_chan->register_config.rsz_cnt =
++				BITRESET(rsz_conf_chan->register_config.
++						rsz_cnt, SET_BIT_YCPOS);
++		} else if (multipass->pix_fmt == RSZ_PIX_FMT_YUYV) {
++			rsz_conf_chan->register_config.rsz_cnt =
++				BITSET(rsz_conf_chan->register_config.
++						rsz_cnt, SET_BIT_YCPOS);
++		}
++
++	}
++	hrsz = (multipass->in_hsize * RATIO_MULTIPLIER) / multipass->out_hsize;
++	vrsz = (multipass->in_vsize * RATIO_MULTIPLIER) / multipass->out_vsize;
++	if(hrsz < 64 || hrsz > 1024 || vrsz < 64 || vrsz > 1024){
++		dev_err(rsz_device,"Wrong Resizing Ratio\n");
++		goto err_einval;
++	}
++
++	vrsz = multipass->vrsz = (multipass->in_vsize - NUM_D2TAPS) *
++		RATIO_MULTIPLIER / (multipass->out_vsize - 1);
++	hrsz = multipass->hrsz = ((multipass->in_hsize - NUM_D2TAPS) *
++			RATIO_MULTIPLIER) / (multipass->out_hsize - 1);
++
++	/* For Width */
++	if (multipass->hrsz <= 512) {
++		hrsz = multipass->hrsz = (multipass->in_hsize - NUM_TAPS)
++			* RATIO_MULTIPLIER
++			/ (multipass->out_hsize - 1);
++		if (multipass->hrsz < 64)
++			multipass->hrsz = 64;
++		if (multipass->hrsz > 512)
++			multipass->hrsz = 512;
++		if (multipass->hstph > NUM_PHASES)
++			goto err_einval;
++		multipass->num_htap = 1;
++	} else if (multipass->hrsz >= 513 && multipass->hrsz <= 1024) {
++		if (multipass->hstph > NUM_D2PH)
++			goto err_einval;
++		multipass->num_htap = 0;
++	}
++	/* For Height */
++	if (multipass->vrsz <= 512) {
++		vrsz = multipass->vrsz = (multipass->in_vsize - NUM_TAPS)
++			* RATIO_MULTIPLIER
++			/ (multipass->out_vsize - 1);
++		if (multipass->vrsz < 64)
++			multipass->vrsz = 64;
++		if (multipass->vrsz > 512)
++			multipass->vrsz = 512;
++		if (multipass->vstph > NUM_PHASES)
++			goto err_einval;
++		multipass->num_vtap = 1;
++	} else if (multipass->vrsz >= 513 && multipass->vrsz <= 1024) {
++		if (multipass->vstph > NUM_D2PH)
++			goto err_einval;
++		multipass->num_vtap = 0;
++	}
++	if(vrsz >= 64 && vrsz <= 512) {
++		if(multipass->out_hsize > 3300) {
++			dev_err(rsz_device, "wrong output hsize\n");
++			goto err_einval;
++		}
++	} else {
++		if(multipass->out_hsize > 1650) {
++			dev_err(rsz_device, "wrong output hsize\n");
++			goto err_einval;
++		}
++	}
++
++	if (multipass->vrsz < 256 &&
++			(multipass->in_vsize < multipass->out_vsize)) {
++		if (multipass->inptyp == RSZ_INTYPE_PLANAR_8BIT) {
++			alignment = ALIGNMENT;
++		} else if (multipass->inptyp == RSZ_INTYPE_YCBCR422_16BIT) {
++			alignment = (ALIGNMENT / 2);
++		} else {
++			dev_err(rsz_device, "Invalid input type\n");
++		}
++
++		if (!(((multipass->out_hsize % PIXEL_EVEN) == 0)
++					&& (multipass->out_hsize % alignment) == 0)) {
++			dev_err(rsz_device, "wrong hsize\n");
++			goto err_einval;
++		}
++	}
++	if (multipass->hrsz >= 64 && multipass->hrsz <= 1024) {
++		if (multipass->out_hsize > MAX_IMAGE_WIDTH) {
++			dev_err(rsz_device, "wrong width\n");
++			goto err_einval;
++		}
++		multipass->active = 0;
++
++	} else if (multipass->hrsz > 1024) {
++		if (multipass->out_hsize > MAX_IMAGE_WIDTH) {
++			dev_err(rsz_device, "wrong width\n");
++			goto err_einval;
++		}
++		if (multipass->hstph > NUM_D2PH)
++			goto err_einval;
++		multipass->num_htap = 0;
++		multipass->out_hsize = multipass->in_hsize * 256 / 1024;
++		if (multipass->out_hsize % ALIGN32) {
++			multipass->out_hsize +=
++				abs((multipass->out_hsize % ALIGN32) - ALIGN32);
++		}
++		multipass->out_pitch = ((multipass->inptyp) ? multipass->out_hsize
++				: (multipass->out_hsize * 2));
++		multipass->hrsz = ((multipass->in_hsize - NUM_D2TAPS)
++				* RATIO_MULTIPLIER)
++			/ (multipass->out_hsize - 1);
++		multipass->active = 1;
++
++	}
++	if (multipass->vrsz > 1024) {
++		if (multipass->out_vsize > MAX_IMAGE_WIDTH_HIGH) {
++			dev_err(rsz_device, "wrong width\n");
++			goto err_einval;
++		}
++
++		multipass->out_vsize = multipass->in_vsize * 256 / 1024;
++		multipass->vrsz = ((multipass->in_vsize - NUM_D2TAPS)
++				* RATIO_MULTIPLIER)
++			/ (multipass->out_vsize - 1);
++		multipass->active = 1;
++		multipass->num_vtap = 0;
++	}
++	rsz_conf_chan->register_config.rsz_out_size =
++		multipass->out_hsize
++		& ISPRSZ_OUT_SIZE_HORZ_MASK;
++
++	rsz_conf_chan->register_config.rsz_out_size |=
++		(multipass->out_vsize
++		 << ISPRSZ_OUT_SIZE_VERT_SHIFT)
++		& ISPRSZ_OUT_SIZE_VERT_MASK;
++
++	rsz_conf_chan->register_config.rsz_sdr_inoff =
++		multipass->in_pitch
++		& ISPRSZ_SDR_INOFF_OFFSET_MASK;
++
++	rsz_conf_chan->register_config.rsz_sdr_outoff =
++		multipass->out_pitch
++		& ISPRSZ_SDR_OUTOFF_OFFSET_MASK;
++
++	if (multipass->hrsz >= 64 && multipass->hrsz <= 512) {
++		if (multipass->hstph > NUM_PHASES)
++			goto err_einval;
++	} else if (multipass->hrsz >= 64 && multipass->hrsz <= 512) {
++		if (multipass->hstph > NUM_D2PH)
++			goto err_einval;
++	}
++
++	rsz_conf_chan->register_config.rsz_cnt |=
++		(multipass->hstph
++		 << ISPRSZ_CNT_HSTPH_SHIFT)
++		& ISPRSZ_CNT_HSTPH_MASK;
++
++	if (multipass->vrsz >= 64 && multipass->hrsz <= 512) {
++		if (multipass->vstph > NUM_PHASES)
++			goto err_einval;
++	} else if (multipass->vrsz >= 64 && multipass->vrsz <= 512) {
++		if (multipass->vstph > NUM_D2PH)
++			goto err_einval;
++	}
++
++	rsz_conf_chan->register_config.rsz_cnt |=
++		(multipass->vstph
++		 << ISPRSZ_CNT_VSTPH_SHIFT)
++		& ISPRSZ_CNT_VSTPH_MASK;
++
++	rsz_conf_chan->register_config.rsz_cnt |=
++		(multipass->hrsz - 1)
++		& ISPRSZ_CNT_HRSZ_MASK;
++
++	rsz_conf_chan->register_config.rsz_cnt |=
++		((multipass->vrsz - 1)
++		 << ISPRSZ_CNT_VRSZ_SHIFT)
++		& ISPRSZ_CNT_VRSZ_MASK;
++	return 0;
++err_einval:
++	return -EINVAL;
++}
++
++/**
++ * rsz_config_ratio - Configure ratio
++ * @fh: File structure containing ISP resizer information specific to
++ *      channel opened.
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Configure ratio
++ **/
++static void rsz_config_ratio(struct rsz_mult *multipass, struct channel_config *rsz_conf_chan)
++{
++	int hsize, vsize;
++	int coeffcounter;
++	if (multipass->hrsz <= 512) {
++		hsize = ((32 * multipass->hstph + (multipass->out_hsize - 1)
++					* multipass->hrsz + 16) >> 8) + 7;
++	} else {
++		hsize = ((64 * multipass->hstph + (multipass->out_hsize - 1)
++					* multipass->hrsz + 32) >> 8) + 7;
++	}
++	if (multipass->vrsz <= 512) {
++		vsize = ((32 * multipass->vstph + (multipass->out_vsize - 1)
++					* multipass->vrsz + 16) >> 8) + 4;
++	} else {
++		vsize = ((64 * multipass->vstph + (multipass->out_vsize - 1)
++					* multipass->vrsz + 32) >> 8) + 7;
++	}
++	rsz_conf_chan->register_config.rsz_in_size = hsize;
++
++	rsz_conf_chan->register_config.rsz_in_size |=
++		((vsize << ISPRSZ_IN_SIZE_VERT_SHIFT)
++		 & ISPRSZ_IN_SIZE_VERT_MASK);
++
++	for (coeffcounter = 0; coeffcounter < MAX_COEF_COUNTER;
++			coeffcounter++) {
++		if (multipass->num_htap) {
++			rsz_conf_chan->register_config.
++				rsz_coeff_horz[coeffcounter] =
++				(multipass->tap4filt_coeffs[2
++				 * coeffcounter]
++				 & ISPRSZ_HFILT10_COEF0_MASK);
++			rsz_conf_chan->register_config.
++				rsz_coeff_horz[coeffcounter] |=
++				((multipass->tap4filt_coeffs[2
++				  * coeffcounter + 1]
++				  << ISPRSZ_HFILT10_COEF1_SHIFT)
++				 & ISPRSZ_HFILT10_COEF1_MASK);
++		} else {
++			rsz_conf_chan->register_config.
++				rsz_coeff_horz[coeffcounter] =
++				(multipass->tap7filt_coeffs[2
++				 * coeffcounter]
++				 & ISPRSZ_HFILT10_COEF0_MASK);
++
++			rsz_conf_chan->register_config.
++				rsz_coeff_horz[coeffcounter] |=
++				((multipass->tap7filt_coeffs[2
++				  * coeffcounter + 1]
++				  << ISPRSZ_HFILT10_COEF1_SHIFT)
++				 & ISPRSZ_HFILT10_COEF1_MASK);
++		}
++
++		if (multipass->num_vtap) {
++			rsz_conf_chan->register_config.
++				rsz_coeff_vert[coeffcounter] =
++				(multipass->tap4filt_coeffs[2
++				 * coeffcounter]
++				 & ISPRSZ_VFILT10_COEF0_MASK);
++
++			rsz_conf_chan->register_config.
++				rsz_coeff_vert[coeffcounter] |=
++				((multipass->tap4filt_coeffs[2
++				  * coeffcounter + 1]
++				  << ISPRSZ_VFILT10_COEF1_SHIFT) &
++				 ISPRSZ_VFILT10_COEF1_MASK);
++		} else {
++			rsz_conf_chan->register_config.
++				rsz_coeff_vert[coeffcounter] =
++				(multipass->tap7filt_coeffs[2
++				 * coeffcounter]
++				 & ISPRSZ_VFILT10_COEF0_MASK);
++			rsz_conf_chan->register_config.
++				rsz_coeff_vert[coeffcounter] |=
++				((multipass->tap7filt_coeffs[2
++				  * coeffcounter + 1]
++				  << ISPRSZ_VFILT10_COEF1_SHIFT)
++				 & ISPRSZ_VFILT10_COEF1_MASK);
++		}
++	}
++}
++
++/**
++ * rsz_get_params - Gets the parameter values
++ * @params: Structure containing the Resizer Wrapper parameters
++ * @rsz_conf_chan: Structure containing channel configuration
++ *
++ * Used to get the Resizer hardware settings associated with the
++ * current logical channel represented by fd.
++ **/
++static int rsz_get_params(struct rsz_params *params,
++					struct channel_config *rsz_conf_chan)
++{
++	int coeffcounter;
++
++	if (rsz_conf_chan->config_state) {
++		dev_err(rsz_device, "state not configured\n");
++		return -EINVAL;
++	}
++
++	params->in_hsize = rsz_conf_chan->register_config.rsz_in_size
++		& ISPRSZ_IN_SIZE_HORZ_MASK;
++	params->in_vsize = (rsz_conf_chan->register_config.rsz_in_size
++			& ISPRSZ_IN_SIZE_VERT_MASK)
++		>> ISPRSZ_IN_SIZE_VERT_SHIFT;
++
++	params->in_pitch = rsz_conf_chan->register_config.rsz_sdr_inoff
++		& ISPRSZ_SDR_INOFF_OFFSET_MASK;
++
++	params->out_hsize = rsz_conf_chan->register_config.rsz_out_size
++		& ISPRSZ_OUT_SIZE_HORZ_MASK;
++
++	params->out_vsize = (rsz_conf_chan->register_config.rsz_out_size
++			& ISPRSZ_OUT_SIZE_VERT_MASK)
++		>> ISPRSZ_OUT_SIZE_VERT_SHIFT;
++
++	params->out_pitch = rsz_conf_chan->register_config.rsz_sdr_outoff
++		& ISPRSZ_SDR_OUTOFF_OFFSET_MASK;
++
++	params->cbilin = (rsz_conf_chan->register_config.rsz_cnt
++			& SET_BIT_CBLIN) >> SET_BIT_CBLIN;
++
++	params->inptyp = (rsz_conf_chan->register_config.rsz_cnt
++			& ISPRSZ_CNT_INPTYP_MASK)
++		>> SET_BIT_INPTYP;
++	params->horz_starting_pixel = ((rsz_conf_chan->register_config.
++				rsz_in_start
++				& ISPRSZ_IN_START_HORZ_ST_MASK));
++	params->vert_starting_pixel = ((rsz_conf_chan->register_config.
++				rsz_in_start
++				& ISPRSZ_IN_START_VERT_ST_MASK)
++			>> ISPRSZ_IN_START_VERT_ST_SHIFT);
++
++	params->hstph = ((rsz_conf_chan->register_config.rsz_cnt
++				& ISPRSZ_CNT_HSTPH_MASK
++				>> ISPRSZ_CNT_HSTPH_SHIFT));
++	params->vstph = ((rsz_conf_chan->register_config.rsz_cnt
++				& ISPRSZ_CNT_VSTPH_MASK
++				>> ISPRSZ_CNT_VSTPH_SHIFT));
++
++	for (coeffcounter = 0; coeffcounter < MAX_COEF_COUNTER;
++			coeffcounter++) {
++		params->tap4filt_coeffs[2 * coeffcounter] =
++			rsz_conf_chan->register_config.
++			rsz_coeff_horz[coeffcounter]
++			& ISPRSZ_HFILT10_COEF0_MASK;
++
++		params->tap4filt_coeffs[2 * coeffcounter + 1] =
++			(rsz_conf_chan->register_config.
++			 rsz_coeff_horz[coeffcounter]
++			 & ISPRSZ_HFILT10_COEF1_MASK)
++			>> ISPRSZ_HFILT10_COEF1_SHIFT;
++
++		params->tap7filt_coeffs[2 * coeffcounter] =
++			rsz_conf_chan->register_config.
++			rsz_coeff_vert[coeffcounter]
++			& ISPRSZ_VFILT10_COEF0_MASK;
++
++		params->tap7filt_coeffs[2 * coeffcounter + 1] =
++			(rsz_conf_chan->register_config.
++			 rsz_coeff_vert[coeffcounter]
++			 & ISPRSZ_VFILT10_COEF1_MASK)
++			>> ISPRSZ_VFILT10_COEF1_SHIFT;
++
++	}
++
++	params->yenh_params.type = (rsz_conf_chan->register_config.rsz_yehn
++			& ISPRSZ_YENH_ALGO_MASK)
++		>> ISPRSZ_YENH_ALGO_SHIFT;
++
++	params->yenh_params.core = rsz_conf_chan->register_config.rsz_yehn
++		& ISPRSZ_YENH_CORE_MASK;
++
++	params->yenh_params.gain = (rsz_conf_chan->register_config.rsz_yehn
++			& ISPRSZ_YENH_GAIN_MASK)
++		>> ISPRSZ_YENH_GAIN_SHIFT;
++
++	params->yenh_params.slop = (rsz_conf_chan->register_config.rsz_yehn
++			& ISPRSZ_YENH_SLOP_MASK)
++		>> ISPRSZ_YENH_SLOP_SHIFT;
++
++	params->pix_fmt = ((rsz_conf_chan->register_config.rsz_cnt
++				& ISPRSZ_CNT_PIXFMT_MASK)
++			>> SET_BIT_YCPOS);
++
++	if (params->pix_fmt)
++		params->pix_fmt = RSZ_PIX_FMT_UYVY;
++	else
++		params->pix_fmt = RSZ_PIX_FMT_YUYV;
++
++	return 0;
++}
++
++/**
++ * rsz_calculate_crop - Calculate Crop values
++ * @rsz_conf_chan: Structure containing channel configuration
++ * @cropsize: Structure containing crop parameters
++ *
++ * Calculate Crop values
++ **/
++static void rsz_calculate_crop(struct channel_config *rsz_conf_chan,
++					struct rsz_cropsize *cropsize)
++{
++	int luma_enable;
++
++	cropsize->hcrop = 0;
++	cropsize->vcrop = 0;
++
++	luma_enable = (rsz_conf_chan->register_config.rsz_yehn
++			& ISPRSZ_YENH_ALGO_MASK)
++		>> ISPRSZ_YENH_ALGO_SHIFT;
++
++	if (luma_enable) {
++		cropsize->hcrop += 2;
++	}
++}
++
++/**
++ * rsz_vbq_release - Videobuffer queue release
++ * @q: Structure containing the videobuffer queue file handle, and device
++ *     structure which contains the actual configuration.
++ * @vb: Structure containing the videobuffer used for resizer processing.
++ **/
++static void rsz_vbq_release(struct videobuf_queue *q,
++						struct videobuf_buffer *vb)
++{
++	struct rsz_fh *fh = q->priv_data;
++	struct videobuf_dmabuf *dma = NULL;
++
++	dma = videobuf_to_dma(q->bufs[vb->i]);
++	videobuf_dma_unmap(q, dma);
++	videobuf_dma_free(dma);
++	ispmmu_unmap(fh->config->buf_address[vb->i]);
++	fh->config->buf_address[vb->i] = 0;
++
++	spin_lock(&fh->vbq_lock);
++	vb->state = VIDEOBUF_NEEDS_INIT;
++	spin_unlock(&fh->vbq_lock);
++
++}
++
++/**
++ * rsz_vbq_setup - Sets up the videobuffer size and validates count.
++ * @q: Structure containing the videobuffer queue file handle, and device
++ *     structure which contains the actual configuration.
++ * @cnt: Number of buffers requested
++ * @size: Size in bytes of the buffer used for previewing
++ *
++ * Always returns 0.
++ **/
++static int rsz_vbq_setup(struct videobuf_queue *q, unsigned int *cnt,
++							unsigned int *size)
++{
++	struct rsz_fh *fh = q->priv_data;
++	struct rsz_mult *multipass = fh->multipass;
++	u32 bpp = 1, insize, outsize;
++
++	spin_lock(&fh->vbq_lock);
++
++	if (fh->params->inptyp == RSZ_INTYPE_YCBCR422_16BIT)
++		bpp = 2;
++	if (*cnt <= 0)
++		*cnt = VIDEO_MAX_FRAME;
++	if (*cnt > VIDEO_MAX_FRAME)
++		*cnt = VIDEO_MAX_FRAME;
++
++	outsize = multipass->out_pitch * multipass->out_vsize;
++	insize = multipass->in_pitch * multipass->in_vsize;
++	if (*cnt == 1 && (outsize > insize)) {
++		dev_err(rsz_device, "2 buffers are required for Upscaling "
++				"mode\n");
++		goto err_einval;
++	}
++	if (!fh->params->in_hsize || !fh->params->in_vsize) {
++		dev_err(rsz_device, "Can't setup buffer size\n");
++		goto err_einval;
++	} else {
++		if(outsize > insize)
++			*size = outsize;
++		else
++			*size = insize;
++
++		fh->rsz_bufsize = *size;
++	}
++	spin_unlock(&fh->vbq_lock);
++	return 0;
++err_einval:
++	spin_unlock(&fh->vbq_lock);
++	return -EINVAL;
++}
++/*
++ * This function is work around for the videobuf_iolock API,
++ * For User memory allocated with ioremap (VM_IO flag) the API
++ * get_user_pages fails.
++ *
++ * To fulfill this requirement, we have completely ignored VM layer of
++ * Linux, and configuring the ISP MMU with physical address.
++ */
++static int omap_videobuf_dma_init_user (struct videobuf_dmabuf *dma,
++		unsigned long physp)
++{
++	struct scatterlist *sglist;
++	int len, i = 0;
++
++	if (dma->nr_pages == 0)
++		return -EINVAL;
++
++	len = dma->nr_pages;
++
++	sglist = kcalloc(len, sizeof(*sglist), GFP_KERNEL);
++	if (NULL == sglist)
++		return -ENOMEM;
++	/* */
++	for (i = 0; i < len; i++) {
++		sglist[i].offset = 0;
++		sglist[i].length = PAGE_SIZE;
++		sglist[i].dma_address = (dma_addr_t)physp;
++		physp += PAGE_SIZE;
++	}
++	dma->sglist = sglist;
++	dma->sglen = len;
++	return 0;
++
++}
++static int omap_videobuf_dma_init(struct videobuf_dmabuf *dma,
++                        int rw, unsigned long data)
++{
++	int err = 0;
++
++	if(dma->nr_pages == 0)
++		return -EINVAL;
++
++        dma->pages = kmalloc(dma->nr_pages * sizeof(struct page*),
++                             GFP_KERNEL);
++        if (NULL == dma->pages)
++                return -ENOMEM;
++
++        dma->varea = (void *) data;
++        err = get_user_pages(current,current->mm,
++                             data & PAGE_MASK, dma->nr_pages,
++                             rw == READ, 1, /* force */
++                             dma->pages, NULL);
++
++        if (err != dma->nr_pages) {
++                dma->nr_pages = (err >= 0) ? err : 0;
++                printk("get_user_pages: err=%d [%d]\n",err,dma->nr_pages);
++                return err < 0 ? err : -EINVAL;
++        }
++        return 0;
++}
++
++static int omap_videobuf_iolock(struct videobuf_queue* q,
++		struct videobuf_buffer *vb,
++		unsigned long asize)
++{
++	int err = 0;
++	unsigned long start, first, last;
++	struct videobuf_dma_sg_memory *mem = vb->priv;
++	struct videobuf_dmabuf *dma;
++	struct vm_area_struct *vma;
++
++	BUG_ON(!mem);
++	MAGIC_CHECK(vb->magic, MAGIC_BUFFER);
++	MAGIC_CHECK(q->int_ops->magic, MAGIC_QTYPE_OPS);
++	MAGIC_CHECK(mem->magic,	MAGIC_SG_MEM);
++
++	dma = &mem->dma;
++	dma->direction = PCI_DMA_FROMDEVICE;
++	start = vb->baddr;
++	/* Calculate number of pages required */
++        first = (start & PAGE_MASK) >> PAGE_SHIFT;
++        last  = ((start+asize-1) & PAGE_MASK) >> PAGE_SHIFT;
++        dma->offset   = start & ~PAGE_MASK;
++        dma->nr_pages = last-first+1;
++
++	/* For kernel direct-mapped memory, take the easy way */
++	if (start >= PAGE_OFFSET) {
++		unsigned long physp = 0;
++		physp = virt_to_phys((void *)start);
++		err = omap_videobuf_dma_init_user(dma, physp);
++		if (err != 0)
++			return err;
++	} else if ((vma = find_vma(current->mm, start)) && (vma->vm_flags & VM_IO)
++			&& (vma->vm_pgoff)){
++		/* This will catch, kernel-allocated,
++		   mmaped-to-usermode addresses */
++		unsigned long physp = 0;
++		physp = (vma->vm_pgoff << PAGE_SHIFT) + (start -
++				vma->vm_start);
++		err = omap_videobuf_dma_init_user(dma, physp);
++		if (err != 0)
++			return err;
++	}
++	else {
++		down_read(&current->mm->mmap_sem);
++		asize = PAGE_ALIGN(asize);
++		err = omap_videobuf_dma_init(&mem->dma,
++				READ, start);
++		up_read(&current->mm->mmap_sem);
++		if (0 != err)
++			return err;
++
++		err = videobuf_dma_map(q,&mem->dma);
++		if (0 != err)
++			return err;
++	}
++	return 0;
++}
++/**
++ * rsz_vbq_prepare - Videobuffer is prepared and mmapped.
++ * @q: Structure containing the videobuffer queue file handle, and device
++ *     structure which contains the actual configuration.
++ * @vb: Structure containing the videobuffer used for resizer processing.
++ * @field: Type of field to set in videobuffer device.
++ *
++ * Returns 0 if successful, or -EINVAL if buffer couldn't get allocated, or
++ * -EIO if the ISP MMU mapping fails
++ **/
++static int rsz_vbq_prepare(struct videobuf_queue *q,
++						struct videobuf_buffer *vb,
++						enum v4l2_field field)
++{
++	struct rsz_fh *fh = q->priv_data;
++	struct channel_config *rsz_conf_chan = fh->config;
++	int err = 0;
++	unsigned int isp_addr, insize, outsize;
++	struct videobuf_dmabuf *dma;
++	struct rsz_mult *multipass = fh->multipass;
++	spin_lock(&fh->vbq_lock);
++	dma = videobuf_to_dma(vb);
++	if (vb->baddr) {
++		if (vb->baddr != (vb->baddr & PAGE_MASK)) {
++			dev_err(rsz_device, "Buffer address should be aligned \
++					to PAGE_SIZE\n");
++			return -EINVAL;
++		}
++		vb->size = fh->rsz_bufsize;
++		vb->bsize = fh->rsz_bufsize;
++	} else {
++		spin_unlock(&fh->vbq_lock);
++		dev_err(rsz_device, "No user buffer allocated\n");
++		goto out;
++	}
++	if (vb->i) {
++		vb->width = fh->params->out_hsize;
++		vb->height = fh->params->out_vsize;
++	} else {
++		vb->width = fh->params->in_hsize;
++		vb->height = fh->params->in_vsize;
++	}
++	vb->field = field;
++	spin_unlock(&fh->vbq_lock);
++
++	outsize = multipass->out_pitch * multipass->out_vsize;
++	insize = multipass->in_pitch * multipass->in_vsize;
++
++	if (vb->state == VIDEOBUF_NEEDS_INIT) {
++		spin_lock(&fh->vbq_lock);
++		if(vb->memory == V4L2_MEMORY_USERPTR)
++			err = omap_videobuf_iolock(q, vb,
++						vb->i?outsize:insize);
++		else
++			err = videobuf_iolock(q, vb, NULL);
++		spin_unlock(&fh->vbq_lock);
++		if(err) {
++			rsz_vbq_release(q, vb);
++			return err;
++		}
++		isp_addr = ispmmu_map_sg(dma->sglist, dma->sglen);
++		if (!isp_addr)
++			err = -EIO;
++		else {
++			if (vb->i) {
++				rsz_conf_chan->buf_address[vb->i] = isp_addr;
++				rsz_conf_chan->register_config.
++					rsz_sdr_outadd
++					= isp_addr;
++				fh->isp_addr_write = isp_addr;
++				rsz_conf_chan->output_buf_index = vb->i;
++			} else {
++				rsz_conf_chan->buf_address[vb->i] = isp_addr;
++				rsz_conf_chan->register_config.
++					rsz_sdr_inadd
++					= isp_addr;
++				rsz_conf_chan->input_buf_index = vb->i;
++				if(outsize < insize && rsz_conf_chan->
++						register_config.
++						rsz_sdr_outadd == 0) {
++					rsz_conf_chan->register_config.
++						rsz_sdr_outadd
++						= isp_addr;
++					rsz_conf_chan->
++						output_buf_index =
++						vb->i;
++				}
++				fh->isp_addr_read = isp_addr;
++			}
++		}
++
++	} else {
++		if(vb->i) {
++			rsz_conf_chan->register_config.
++				rsz_sdr_outadd = rsz_conf_chan->buf_address[vb->i];
++			fh->isp_addr_write = rsz_conf_chan->buf_address[vb->i];
++			rsz_conf_chan->output_buf_index = vb->i;
++		} else {
++			rsz_conf_chan->register_config.
++				rsz_sdr_inadd = rsz_conf_chan->buf_address[vb->i];
++			rsz_conf_chan->input_buf_index = vb->i;
++			if(outsize < insize && rsz_conf_chan->
++					register_config.
++					rsz_sdr_outadd == 0) {
++				rsz_conf_chan->register_config.
++					rsz_sdr_outadd
++					= rsz_conf_chan->buf_address[vb->i];
++				rsz_conf_chan->output_buf_index = vb->i;
++			}
++
++		}
++
++	}
++	if (!err) {
++		spin_lock(&fh->vbq_lock);
++		vb->state = VIDEOBUF_PREPARED;
++		spin_unlock(&fh->vbq_lock);
++	} else
++		rsz_vbq_release(q, vb);
++out:
++	return err;
++}
++
++static void rsz_vbq_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
++{
++	return;
++}
++
++/**
++ * rsz_open - Initializes and opens the Resizer Wrapper
++ * @inode: Inode structure associated with the Resizer Wrapper
++ * @filp: File structure associated with the Resizer Wrapper
++ *
++ * Returns 0 if successful, -EBUSY if its already opened or the ISP module is
++ * not available, or -ENOMEM if its unable to allocate the device in kernel
++ * space memory.
++ **/
++static int rsz_open(struct inode *inode, struct file *filp)
++{
++	int ret = 0;
++	struct channel_config *rsz_conf_chan;
++	struct rsz_fh *fh;
++	struct device_params *device = device_config;
++	struct rsz_params *params;
++	struct rsz_mult *multipass;
++
++	if ((filp->f_flags & O_NONBLOCK) == O_NONBLOCK) {
++		printk(KERN_DEBUG "omap-resizer: Device is opened in "
++				"non blocking mode\n");
++	}else{
++		printk(KERN_DEBUG "omap-resizer: Device is opened in blocking "
++				"mode\n");
++	}
++	fh = kzalloc(sizeof(struct rsz_fh), GFP_KERNEL);
++	if (NULL == fh)
++		return -ENOMEM;
++
++	isp_get();
++
++	rsz_conf_chan = kzalloc(sizeof(struct channel_config), GFP_KERNEL);
++	if (rsz_conf_chan == NULL) {
++		dev_err(rsz_device, "\n cannot allocate memory to config");
++		ret = -ENOMEM;
++		goto err_enomem0;
++	}
++	params = kzalloc(sizeof(struct rsz_params), GFP_KERNEL);
++	if (params == NULL) {
++		dev_err(rsz_device, "\n cannot allocate memory to params");
++		ret = -ENOMEM;
++		goto err_enomem1;
++	}
++	multipass = kzalloc(sizeof(struct rsz_mult), GFP_KERNEL);
++	if (multipass == NULL) {
++		dev_err(rsz_device, "\n cannot allocate memory to multipass");
++		ret = -ENOMEM;
++		goto err_enomem2;
++	}
++	fh->multipass = multipass;
++	fh->params = params;
++	fh->config = rsz_conf_chan;
++	rsz_conf_chan->config_state = STATE_NOT_CONFIGURED;
++	rsz_conf_chan->status = CHANNEL_FREE;
++	filp->private_data = fh;
++	fh->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	fh->device = device;
++
++	videobuf_queue_sg_init(&fh->vbq, &device->vbq_ops, NULL,
++			&fh->vbq_lock, fh->type,
++			V4L2_FIELD_NONE,
++			sizeof(struct videobuf_buffer), fh);
++
++	spin_lock_init(&fh->vbq_lock);
++	mutex_init(&rsz_conf_chan->chanprotection_mutex);
++	return 0;
++err_enomem2:
++	kfree(params);
++err_enomem1:
++	kfree(rsz_conf_chan);
++err_enomem0:
++	kfree(fh);
++	return ret;
++}
++
++/**
++ * rsz_release - Releases Resizer Wrapper and frees up allocated memory
++ * @inode: Inode structure associated with the Resizer Wrapper
++ * @filp: File structure associated with the Resizer Wrapper
++ *
++ * Returns 0 if successful, or -EBUSY if channel is being used.
++ **/
++static int rsz_release(struct inode *inode, struct file *filp)
++{
++	int i;
++	unsigned int timeout = 0;
++	struct rsz_fh *fh = filp->private_data;
++	struct channel_config *rsz_conf_chan = fh->config;
++	struct rsz_params *params = fh->params;
++	struct rsz_mult *multipass = fh->multipass;
++	struct videobuf_queue *q = &fh->vbq;
++
++	while((rsz_conf_chan->status != CHANNEL_FREE) && (timeout < 20)) {
++		timeout++;
++		schedule();
++	}
++	/* Free memory allocated to the buffers */
++	for (i = 0 ; i < VIDEO_MAX_FRAME ; i ++) {
++		struct videobuf_dmabuf *dma = NULL;
++		if(!q->bufs[i])
++			continue;
++		dma = videobuf_to_dma(q->bufs[i]);
++		videobuf_dma_unmap(q, dma);
++		videobuf_dma_free(dma);
++	}
++
++	videobuf_mmap_free(q);
++	fh->rsz_bufsize = 0;
++	filp->private_data = NULL;
++	kfree(rsz_conf_chan);
++	kfree(params);
++	kfree(multipass);
++	kfree(fh);
++	isp_put();
++	fh->params = NULL;
++	fh->config = NULL;
++	return 0;
++}
++
++/**
++ * rsz_mmap - Memory maps the Resizer Wrapper module.
++ * @file: File structure associated with the Resizer Wrapper
++ * @vma: Virtual memory area structure.
++ *
++ * Returns 0 if successful, or returned value by the videobuf_mmap_mapper()
++ * function.
++ **/
++static int rsz_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	struct rsz_fh *fh = file->private_data;
++
++	return videobuf_mmap_mapper(&fh->vbq, vma);
++}
++
++/**
++ * rsz_ioctl - I/O control function for Resizer Wrapper
++ * @inode: Inode structure associated with the Resizer Wrapper.
++ * @file: File structure associated with the Resizer Wrapper.
++ * @cmd: Type of command to execute.
++ * @arg: Argument to send to requested command.
++ *
++ * Returns 0 if successful, -EBUSY if channel is being used, -1 if bad command
++ * passed or access is denied, -EFAULT if copy_from_user() or copy_to_user()
++ * fails, -EINVAL if parameter validation fails or parameter structure is not
++ * present.
++ **/
++static long rsz_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++	int ret = 0, i;
++	struct rsz_fh *fh = file->private_data;
++	struct device_params *device = fh->device;
++	struct channel_config *rsz_conf_chan = fh->config;
++
++	if ((_IOC_TYPE(cmd) != RSZ_IOC_BASE)
++					|| (_IOC_NR(cmd) > RSZ_IOC_MAXNR)) {
++		dev_err(rsz_device, "Bad command value \n");
++		goto err_minusone;
++	}
++
++	if (_IOC_DIR(cmd) & _IOC_READ)
++		ret = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
++	else if (_IOC_DIR(cmd) & _IOC_WRITE)
++		ret = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
++
++	if (ret) {
++		dev_err(rsz_device, "Access denied\n");
++		goto err_minusone;
++	}
++
++	switch (cmd) {
++	case RSZ_REQBUF:
++	{
++		struct v4l2_requestbuffers req_buf;
++		struct videobuf_queue *q = &fh->vbq;
++		if (copy_from_user(&req_buf, (struct v4l2_requestbuffers *)arg,
++					sizeof(struct v4l2_requestbuffers))) {
++			goto err_efault;
++		}
++		if (mutex_lock_interruptible(&rsz_conf_chan->chanprotection_mutex))
++			goto err_eintr;
++		/* Free memory allocated to the buffers */
++		for (i = 0 ; i < VIDEO_MAX_FRAME ; i ++) {
++			struct videobuf_dmabuf *dma = NULL;
++			if(!q->bufs[i])
++				continue;
++			if(q->bufs[i]->memory != V4L2_MEMORY_MMAP)
++				continue;
++			dma = videobuf_to_dma(q->bufs[i]);
++			videobuf_dma_unmap(q, dma);
++			videobuf_dma_free(dma);
++
++		}
++		videobuf_mmap_free(q);
++
++		ret = videobuf_reqbufs(q, &req_buf);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		break;
++	}
++	case RSZ_QUERYBUF:
++	{
++		struct v4l2_buffer buf;
++		if (copy_from_user(&buf, (struct v4l2_buffer *)arg,
++						sizeof(struct v4l2_buffer))) {
++			goto err_efault;
++		}
++		if (mutex_lock_interruptible(&rsz_conf_chan->chanprotection_mutex))
++			goto err_eintr;
++		ret = videobuf_querybuf(&fh->vbq, &buf);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		if (copy_to_user((struct v4l2_buffer *)arg, &buf,
++						sizeof(struct v4l2_buffer)))
++			ret = -EFAULT;
++
++		break;
++	}
++	case RSZ_QUEUEBUF:
++	{
++		struct v4l2_buffer buf;
++		if (copy_from_user(&buf, (struct v4l2_buffer *)arg,
++					sizeof(struct v4l2_buffer))) {
++			goto err_efault;
++		}
++		if (mutex_lock_interruptible(&rsz_conf_chan->chanprotection_mutex))
++			goto err_eintr;
++		ret = videobuf_qbuf(&fh->vbq, &buf);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		break;
++	}
++	case RSZ_S_PARAM:
++	{
++		struct rsz_params *params = fh->params;
++		if (copy_from_user(params, (struct rsz_params *)arg,
++						sizeof(struct rsz_params))) {
++			goto err_efault;
++		}
++		ret = rsz_set_params(fh->multipass, fh->params,	rsz_conf_chan);
++		break;
++	}
++	case RSZ_G_PARAM:
++		ret = rsz_get_params((struct rsz_params *)arg, rsz_conf_chan);
++		break;
++
++	case RSZ_G_STATUS:
++	{
++		struct rsz_status *status;
++		status = (struct rsz_status *)arg;
++		status->chan_busy = rsz_conf_chan->status;
++		status->hw_busy = resizer_busy();
++		status->src = INPUT_RAM;
++		break;
++	}
++	case RSZ_RESIZE:
++		if(file->f_flags & O_NONBLOCK) {
++			if(resizer_busy())
++				return -EBUSY;
++			else {
++				 if(!mutex_trylock(&device->reszwrap_mutex))
++					return -EBUSY;
++			}
++		}
++		else {
++			if (mutex_lock_interruptible(&device->reszwrap_mutex))
++				goto err_eintr;
++		}
++		ret = rsz_start((int *)arg, fh);
++		mutex_unlock(&device->reszwrap_mutex);
++		break;
++
++	case RSZ_GET_CROPSIZE:
++		rsz_calculate_crop(rsz_conf_chan, (struct rsz_cropsize *)arg);
++		break;
++
++	case RSZ_S_EXP:
++		if (mutex_lock_interruptible(&rsz_conf_chan->chanprotection_mutex))
++			goto err_eintr;
++		rsz_conf_chan->register_config.sdr_req_exp = *((unsigned int *)arg);
++		mutex_unlock(&rsz_conf_chan->chanprotection_mutex);
++		break;
++	default:
++		dev_err(rsz_device, "resizer_ioctl: Invalid Command Value");
++		ret = -EINVAL;
++	}
++
++out:
++	return (long)ret;
++err_minusone:
++	ret = -1;
++	goto out;
++err_eintr:
++	ret = -EINTR;
++	goto out;
++err_efault:
++	ret = -EFAULT;
++	goto out;
++}
++
++static struct file_operations rsz_fops = {
++	.owner = THIS_MODULE,
++	.open = rsz_open,
++	.release = rsz_release,
++	.mmap = rsz_mmap,
++	.unlocked_ioctl = rsz_unlocked_ioctl,
++};
++
++/**
++ * rsz_isr - Interrupt Service Routine for Resizer wrapper
++ * @status: ISP IRQ0STATUS register value
++ * @arg1: Currently not used
++ * @arg2: Currently not used
++ *
++ * Interrupt Service Routine for Resizer wrapper
++ **/
++static void rsz_isr(unsigned long status, isp_vbq_callback_ptr arg1, void *arg2)
++{
++	if ((status & RESZ_DONE) != RESZ_DONE)
++		return;
++	complete(&(device_config->compl_isr));
++}
++
++/**
++ * resizer_platform_release - Acts when Reference count is zero
++ * @device: Structure containing ISP resizer wrapper global information
++ *
++ * This is called when the reference count goes to zero.
++ **/
++static void resizer_platform_release(struct device *device)
++{
++}
++
++/**
++ * resizer_probe - Checks for device presence
++ * @device: Structure containing details of the current device.
++ *
++ * Always returns 0.
++ **/
++static int __init resizer_probe(struct platform_device *device)
++{
++	return 0;
++}
++
++/**
++ * resizer_remove - Handles the removal of the driver
++ * @omap_resizer_device: Structure containing details of the current device.
++ *
++ * Always returns 0.
++ **/
++static int resizer_remove(struct platform_device *omap_resizer_device)
++{
++	return 0;
++}
++
++static struct class *rsz_class = NULL;
++static struct cdev c_dev;
++static dev_t dev;
++
++static struct platform_device omap_resizer_device = {
++	.name = OMAP_REZR_NAME,
++	.id = 2,
++	.dev = {
++		.release = resizer_platform_release,
++	}
++};
++
++static struct platform_driver omap_resizer_driver = {
++	.probe = resizer_probe,
++	.remove = resizer_remove,
++	.driver = {
++			.bus = &platform_bus_type,
++			.name = OMAP_REZR_NAME,
++	},
++};
++
++/**
++ * omap_rsz_init - Initialization of Resizer Wrapper
++ *
++ * Returns 0 if successful, -ENOMEM if could not allocate memory, -ENODEV if
++ * could not register the wrapper as a character device, or other errors if the
++ * device or driver can't register.
++ **/
++static int __init omap_rsz_init(void)
++{
++	int ret = 0;
++	struct device_params *device;
++
++	device = kzalloc(sizeof(struct device_params), GFP_KERNEL);
++	if (!device) {
++		dev_err(rsz_device, OMAP_REZR_NAME ": could not allocate "
++				"memory\n");
++		return -ENOMEM;
++	}
++	ret = alloc_chrdev_region(&dev, 0, 1, OMAP_REZR_NAME);
++	if (ret < 0) {
++		dev_err(rsz_device, OMAP_REZR_NAME ": intialization failed. "
++			"Could not allocate region "
++			"for character device\n");
++		kfree(device);
++		return -ENODEV;
++	}
++	/* Register the driver in the kernel */
++	/* Initialize of character device */
++	cdev_init(&c_dev, &rsz_fops);
++	c_dev.owner = THIS_MODULE;
++	c_dev.ops = &rsz_fops;
++	/* addding character device */
++	ret = cdev_add(&c_dev, dev, 1);
++	if (ret) {
++		dev_err(rsz_device, OMAP_REZR_NAME ": Error adding "
++			"device - %d\n", ret);
++		goto fail2;
++	}
++	rsz_major = MAJOR(dev);
++	/* register driver as a platform driver */
++	ret = platform_driver_register(&omap_resizer_driver);
++	if (ret) {
++		dev_err(rsz_device, OMAP_REZR_NAME
++		       ": failed to register platform driver!\n");
++		goto fail3;
++	}
++	/* Register the drive as a platform device */
++	ret = platform_device_register(&omap_resizer_device);
++	if (ret) {
++		dev_err(rsz_device, OMAP_REZR_NAME
++		       ": failed to register platform device!\n");
++		goto fail4;
++	}
++	rsz_class = class_create(THIS_MODULE, OMAP_REZR_NAME);
++	if (!rsz_class) {
++		dev_err(rsz_device, OMAP_REZR_NAME
++			": Failed to create class!\n");
++		goto fail5;
++	}
++	/* make entry in the devfs */
++	rsz_device = device_create(rsz_class, rsz_device, MKDEV(rsz_major, 0),
++				   NULL,OMAP_REZR_NAME);
++	dev_dbg(rsz_device, OMAP_REZR_NAME ": Registered Resizer Wrapper\n");
++
++	device->vbq_ops.buf_setup = rsz_vbq_setup;
++	device->vbq_ops.buf_prepare = rsz_vbq_prepare;
++	device->vbq_ops.buf_release = rsz_vbq_release;
++	device->vbq_ops.buf_queue = rsz_vbq_queue;
++
++	init_completion(&device->compl_isr);
++	mutex_init(&device->reszwrap_mutex);
++	device_config = device;
++	return 0;
++fail5:
++	platform_device_unregister(&omap_resizer_device);
++fail4:
++	platform_driver_unregister(&omap_resizer_driver);
++fail3:
++	cdev_del(&c_dev);
++fail2:
++	unregister_chrdev_region(dev, 1);
++	kfree(device);
++	return ret;
++}
++
++/**
++ * omap_rsz_exit - Close of Resizer Wrapper
++ **/
++void __exit omap_rsz_exit(void)
++{
++	device_destroy(rsz_class, dev);
++	class_destroy(rsz_class);
++	platform_device_unregister(&omap_resizer_device);
++	platform_driver_unregister(&omap_resizer_driver);
++	cdev_del(&c_dev);
++	unregister_chrdev_region(dev, 1);
++	kfree(device_config);
++}
++
++module_init(omap_rsz_init)
++module_exit(omap_rsz_exit)
++
++MODULE_AUTHOR("Texas Instruments");
++MODULE_DESCRIPTION("OMAP ISP Resizer");
++MODULE_LICENSE("GPL");
+Index: git/drivers/media/video/isp/omap_resizer.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/omap_resizer.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,323 @@
++/*
++ * drivers/media/video/isp/omap_resizer.h
++ *
++ * Include file for Resizer module wrapper in TI's OMAP3430 ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_ISP_RESIZER_WRAP_H
++#define OMAP_ISP_RESIZER_WRAP_H
++
++/* ioctls definition */
++#define RSZ_IOC_BASE			'R'
++#define RSZ_IOC_MAXNR			8
++
++/*Ioctl options which are to be passed while calling the ioctl*/
++#define RSZ_REQBUF			_IOWR(RSZ_IOC_BASE, 1,\
++						struct v4l2_requestbuffers)
++#define RSZ_QUERYBUF			_IOWR(RSZ_IOC_BASE, 2,\
++						struct v4l2_buffer)
++#define RSZ_S_PARAM			_IOWR(RSZ_IOC_BASE, 3,\
++						struct rsz_params)
++#define RSZ_G_PARAM			_IOWR(RSZ_IOC_BASE, 4,\
++						struct rsz_params)
++#define RSZ_RESIZE			_IOWR(RSZ_IOC_BASE, 5, int)
++#define RSZ_G_STATUS			_IOWR(RSZ_IOC_BASE, 6,\
++						struct rsz_status)
++#define RSZ_QUEUEBUF			_IOWR(RSZ_IOC_BASE, 7,\
++						struct v4l2_buffer)
++#define RSZ_GET_CROPSIZE		_IOWR(RSZ_IOC_BASE, 8,\
++						struct rsz_cropsize)
++
++/* Defines and Constants*/
++
++#define MAX_CHANNELS			16
++#define MAX_IMAGE_WIDTH			2047
++#define MAX_IMAGE_WIDTH_HIGH		2047
++
++#define ALIGNMENT			16
++#define CHANNEL_BUSY			1
++#define CHANNEL_FREE			0
++#define PIXEL_EVEN			2
++#define RATIO_MULTIPLIER		256
++
++/* Bit position Macro */
++/* macro for bit set and clear */
++#define BITSET(variable, bit)		(variable) | (1 << bit)
++#define BITRESET(variable, bit)		(variable) & ~(0x00000001 << (bit))
++#define SET_BIT_INPUTRAM		28
++#define SET_BIT_CBLIN			29
++#define SET_BIT_INPTYP			27
++#define SET_BIT_YCPOS			26
++#define INPUT_RAM			1
++#define UP_RSZ_RATIO			64
++#define DOWN_RSZ_RATIO			512
++#define UP_RSZ_RATIO1			513
++#define DOWN_RSZ_RATIO1			1024
++#define RSZ_IN_SIZE_VERT_SHIFT		16
++#define MAX_HORZ_PIXEL_8BIT		31
++#define MAX_HORZ_PIXEL_16BIT		15
++#define NUM_PHASES			8
++#define NUM_TAPS			4
++#define NUM_D2PH			4	/* for downsampling
++						 * 2+x ~ 4x, number of phases
++						 */
++#define NUM_D2TAPS			7 	/* for downsampling
++						 * 2+x ~ 4x,number of taps
++						 */
++#define ALIGN32				32
++#define MAX_COEF_COUNTER		16
++#define COEFF_ADDRESS_OFFSET		0x04
++
++#define RSZ_INTYPE_YCBCR422_16BIT	0
++#define RSZ_INTYPE_PLANAR_8BIT		1
++#define RSZ_PIX_FMT_UYVY		1	/* cb:y:cr:y */
++#define RSZ_PIX_FMT_YUYV		0	/* y:cb:y:cr */
++
++enum config_done {
++	STATE_CONFIGURED,			/* Resizer driver configured
++						 * by application.
++						 */
++	STATE_NOT_CONFIGURED			/* Resizer driver not
++						 * configured by application.
++						 */
++};
++
++/* Structure Definitions */
++
++/* used to luma enhancement options */
++
++struct rsz_yenh {
++	int type;				/* represents luma enable or
++						 * disable.
++						 */
++	unsigned char gain;			/* represents gain. */
++	unsigned char slop;			/* represents slop. */
++	unsigned char core;			/* Represents core value. */
++};
++
++/* Conatins all the parameters for resizing. This structure
++ * is used to configure resiser parameters
++ */
++struct rsz_params {
++	int in_hsize;				/* input frame horizontal
++						 * size.
++						 */
++	int in_vsize;				/* input frame vertical size */
++	int in_pitch;				/* offset between two rows of
++						 * input frame.
++						 */
++	int inptyp;				/* for determining 16 bit or
++						 * 8 bit data.
++						 */
++	int vert_starting_pixel;		/* for specifying vertical
++						 * starting pixel in input.
++						 */
++	int horz_starting_pixel;		/* for specyfing horizontal
++						 * starting pixel in input.
++						 */
++	int cbilin;				/* # defined, filter with luma
++						 * or bi-linear interpolation.
++						 */
++	int pix_fmt;				/* # defined, UYVY or YUYV */
++	int out_hsize;				/* output frame horizontal
++						 * size.
++						 */
++	int out_vsize;				/* output frame vertical
++						 * size.
++						 */
++	int out_pitch;				/* offset between two rows of
++						 * output frame.
++						 */
++	int hstph;				/* for specifying horizontal
++						 * starting phase.
++						 */
++	int vstph;				/* for specifying vertical
++						 * starting phase.
++						 */
++	u16 tap4filt_coeffs[32];		/* horizontal filter
++						 * coefficients.
++						 */
++	u16 tap7filt_coeffs[32];		/* vertical filter
++						 * coefficients.
++						 */
++	struct rsz_yenh yenh_params;
++};
++
++struct rsz_mult {
++	int in_hsize;				/* input frame horizontal
++						 * size.
++						 */
++	int in_vsize;				/* input frame vertical size.
++						 */
++	int out_hsize;				/* output frame horizontal
++						 * size.
++						 */
++	int out_vsize;				/* output frame vertical
++						 * size.
++						 */
++	int in_pitch;				/* offset between two rows of
++						 * input frame.
++						 */
++	int out_pitch;				/* offset between two rows of
++						 * output frame.
++						 */
++	int end_hsize;
++	int end_vsize;
++	int num_htap;				/* 0 = 7tap; 1 = 4tap */
++	int num_vtap;				/* 0 = 7tap; 1 = 4tap */
++	int active;
++	int inptyp;
++	int vrsz;
++	int hrsz;
++	int hstph;				/* for specifying horizontal
++						 * starting phase.
++						 */
++	int vstph;
++	int pix_fmt;				/* # defined, UYVY or YUYV. */
++	int cbilin;				/* # defined, filter with luma
++						 * or bi-linear.
++						 */
++	u16 tap4filt_coeffs[32];		/* horizontal filter
++						 * coefficients.
++						 */
++	u16 tap7filt_coeffs[32];		/* vertical filter
++						 * coefficients.
++						 */
++};
++
++/* Contains the status of hardware and channel */
++struct rsz_status {
++	int chan_busy;				/* 1: channel is busy,
++						 * 0: channel is not busy
++						 */
++	int hw_busy;				/* 1: hardware is busy,
++						 * 0: hardware is not busy
++						 */
++	int src;				/* # defined, can be either
++						 * SD-RAM or CCDC/PREVIEWER
++						 */
++};
++
++/* Passed by application for getting crop size */
++struct rsz_cropsize {
++	unsigned int hcrop;			/* Number of pixels per line
++						 * cropped in output image.
++						 */
++
++	unsigned int vcrop;			/* Number of lines cropped
++						 * in output image.
++						 */
++};
++
++/* Register mapped structure which contains the every register
++   information */
++struct resizer_config {
++	u32 rsz_pcr;				/* pcr register mapping
++						 * variable.
++						 */
++	u32 rsz_in_start;			/* in_start register mapping
++						 * variable.
++						 */
++	u32 rsz_in_size;			/* in_size register mapping
++						 * variable.
++						 */
++	u32 rsz_out_size;			/* out_size register mapping
++						 * variable.
++						 */
++	u32 rsz_cnt;				/* rsz_cnt register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_inadd;			/* sdr_inadd register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_inoff;			/* sdr_inoff register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_outadd;			/* sdr_outadd register mapping
++						 * variable.
++						 */
++	u32 rsz_sdr_outoff;			/* sdr_outbuff register
++						 * mapping variable.
++						 */
++	u32 rsz_coeff_horz[16];			/* horizontal coefficients
++						 * mapping array.
++						 */
++	u32 rsz_coeff_vert[16];			/* vertical coefficients
++						 * mapping array.
++						 */
++	u32 rsz_yehn;				/* yehn(luma)register mapping
++						 * variable.
++						 */
++};
++
++/* Channel specific structure contains information regarding
++   the every channel */
++struct channel_config {
++	struct resizer_config register_config;	/* Instance of register set
++						 * mapping structure
++						 */
++	int status;				/* Specifies whether the
++						 * channel is busy or not
++						 */
++	struct mutex chanprotection_mutex;	/* Pointer to channel
++						 * specific protection
++						 */
++	enum config_done config_state;
++	u8 input_buf_index, output_buf_index;
++
++};
++
++/* Global structure which contains information about number of channels
++   and protection variables */
++struct device_params {
++
++	struct mutex reszwrap_mutex;		/* Semaphore for array */
++	struct completion compl_isr;		/* Completion for interrupt */
++	struct videobuf_queue_ops vbq_ops;	/* videobuf queue operations */
++};
++
++/* per-filehandle data structure */
++struct rsz_fh {
++	struct rsz_params *params;
++	struct channel_config *config;		/* Pointer to channel
++						 * configuration.
++						 */
++	enum v4l2_buf_type type;
++	struct videobuf_queue vbq;
++	struct device_params *device;
++	dma_addr_t isp_addr_read;		/* Input/Output address */
++	dma_addr_t isp_addr_write;		/* Input/Output address */
++	struct rsz_mult *multipass;		/* Multipass to support 
++						 * resizing ration outside
++						 * of 0.25x to 4x 
++						 */
++	spinlock_t vbq_lock;			/* spinlock for videobuf
++						 * queues.
++						 */
++	u32 rsz_bufsize;			/* channel specific buffersize
++						 */
++};
++
++/* functions definition */
++void rsz_hardware_setup(struct channel_config *rsz_conf_chan);
++int rsz_set_params(struct rsz_mult *multipass, struct rsz_params *, struct channel_config *);
++int rsz_get_params(struct rsz_params *, struct channel_config *);
++void rsz_copy_data(struct rsz_mult *multipass, struct rsz_params *params);
++void rsz_isr(unsigned long status, isp_vbq_callback_ptr arg1, void *arg2);
++void rsz_calculate_crop(struct channel_config *rsz_conf_chan,
++						struct rsz_cropsize *cropsize);
++int rsz_set_multipass(struct rsz_mult *multipass, struct channel_config *rsz_conf_chan);
++int rsz_set_ratio(struct rsz_mult *multipass, struct channel_config *rsz_conf_chan);
++void rsz_config_ratio(struct rsz_mult *multipass, struct channel_config *rsz_conf_chan);
++
++#endif
+Index: git/drivers/media/video/isp/redgamma_table.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/redgamma_table.h	2009-02-12 10:29:26.000000000 -0600
+@@ -0,0 +1,1040 @@
++/*
++ * drivers/media/video/isp/redgamma_table.h
++ *
++ * Gamma Table values for Red for TI's OMAP3430 Camera ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++0,
++0,
++1,
++2,
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++3,
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++255
+Index: git/include/linux/omap_resizer.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/include/linux/omap_resizer.h	2009-02-12 10:31:16.000000000 -0600
+@@ -0,0 +1,136 @@
++/*
++ * drivers/media/video/isp/omap_resizer.h
++ *
++ * Include file for Resizer module wrapper in TI's OMAP3430 ISP
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++
++#ifndef OMAP_RESIZER_H
++#define OMAP_RESIZER_H
++
++#include <linux/types.h>
++
++/* ioctls definition */
++#define RSZ_IOC_BASE		'R'
++#define RSZ_IOC_MAXNR		9
++
++/*Ioctl options which are to be passed while calling the ioctl*/
++#define RSZ_REQBUF		_IOWR(RSZ_IOC_BASE, 1,\
++					struct v4l2_requestbuffers)
++#define RSZ_QUERYBUF		_IOWR(RSZ_IOC_BASE, 2, struct v4l2_buffer)
++#define RSZ_S_PARAM		_IOWR(RSZ_IOC_BASE, 3, struct rsz_params)
++#define RSZ_G_PARAM		_IOWR(RSZ_IOC_BASE, 4, struct rsz_params)
++#define RSZ_RESIZE		_IOWR(RSZ_IOC_BASE, 5, __s32)
++#define RSZ_G_STATUS		_IOWR(RSZ_IOC_BASE, 6, struct rsz_status)
++#define RSZ_QUEUEBUF		_IOWR(RSZ_IOC_BASE, 7, struct v4l2_buffer)
++#define RSZ_GET_CROPSIZE	_IOWR(RSZ_IOC_BASE, 8, struct rsz_cropsize)
++#define RSZ_S_EXP		_IOWR(RSZ_IOC_BASE, 9, __s32)
++#define RSZ_INTYPE_YCBCR422_16BIT	0
++#define RSZ_INTYPE_PLANAR_8BIT		1
++#define RSZ_PIX_FMT_UYVY		1	/* cb:y:cr:y */
++#define RSZ_PIX_FMT_YUYV		0	/* y:cb:y:cr */
++
++enum config_done {
++	STATE_CONFIGURED,			/* Resizer driver configured
++						 * by application.
++						 */
++	STATE_NOT_CONFIGURED			/* Resizer driver not
++						 * configured by application.
++						 */
++};
++
++/* Structure Definitions */
++
++/* used to luma enhancement options */
++
++struct rsz_yenh {
++	__s32 type;				/* represents luma enable or
++						 * disable.
++						 */
++	__u8 gain;			/* represents gain. */
++	__u8 slop;			/* represents slop. */
++	__u8 core;			/* Represents core value. */
++};
++
++/* Conatins all the parameters for resizing. This structure
++ * is used to configure resiser parameters
++ */
++struct rsz_params {
++	__s32 in_hsize;				/* input frame horizontal
++						 * size.
++						 */
++	__s32 in_vsize;				/* input frame vertical size */
++	__s32 in_pitch;				/* offset between two rows of
++						 * input frame.
++						 */
++	__s32 inptyp;				/* for determining 16 bit or
++						 * 8 bit data.
++						 */
++	__s32 vert_starting_pixel;		/* for specifying vertical
++						 * starting pixel in input.
++						 */
++	__s32 horz_starting_pixel;		/* for specyfing horizontal
++						 * starting pixel in input.
++						 */
++	__s32 cbilin;				/* # defined, filter with luma
++						 * or bi-linear interpolation.
++						 */
++	__s32 pix_fmt;				/* # defined, UYVY or YUYV */
++	__s32 out_hsize;				/* output frame horizontal
++						 * size.
++						 */
++	__s32 out_vsize;				/* output frame vertical
++						 * size.
++						 */
++	__s32 out_pitch;				/* offset between two rows of
++						 * output frame.
++						 */
++	__s32 hstph;				/* for specifying horizontal
++						 * starting phase.
++						 */
++	__s32 vstph;				/* for specifying vertical
++						 * starting phase.
++						 */
++	__u16 tap4filt_coeffs[32];		/* horizontal filter
++						 * coefficients.
++						 */
++	__u16 tap7filt_coeffs[32];		/* vertical filter
++						 * coefficients.
++						 */
++	struct rsz_yenh yenh_params;
++};
++
++/* Contains the status of hardware and channel */
++struct rsz_status {
++	__s32 chan_busy;				/* 1: channel is busy,
++						 * 0: channel is not busy
++						 */
++	__s32 hw_busy;				/* 1: hardware is busy,
++						 * 0: hardware is not busy
++						 */
++	__s32 src;				/* # defined, can be either
++						 * SD-RAM or CCDC/PREVIEWER
++						 */
++};
++
++/* Passed by application for getting crop size */
++struct rsz_cropsize {
++	__u32 hcrop;			/* Number of pixels per line
++						 * cropped in output image.
++						 */
++
++	__u32 vcrop;			/* Number of lines cropped
++						 * in output image.
++						 */
++};
++
++#endif
+Index: git/drivers/media/video/Kconfig
+===================================================================
+--- git.orig/drivers/media/video/Kconfig	2009-02-12 10:24:15.000000000 -0600
++++ git/drivers/media/video/Kconfig	2009-02-12 10:34:27.000000000 -0600
+@@ -370,6 +370,8 @@
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called tvp5150.
+ 
++source "drivers/media/video/isp/Kconfig"
++
+ config VIDEO_VPX3220
+ 	tristate "vpx3220a, vpx3216b & vpx3214c video decoders"
+ 	depends on VIDEO_V4L1 && I2C
+Index: git/drivers/media/video/isp/Kconfig
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/Kconfig	2009-02-12 14:53:17.000000000 -0600
+@@ -0,0 +1,13 @@
++config VIDEO_OMAP34XX_ISP
++        tristate "omap isp driver"
++        depends on ARCH_OMAP34XX
++	select VIDEOBUF_DMA_SG
++
++config VIDEO_OMAP34XX_ISP_PREVIEWER
++        tristate "omap isp previewer"
++        depends on VIDEO_OMAP34XX_ISP && !ARCH_OMAP3410
++
++config VIDEO_OMAP34XX_ISP_RESIZER
++        tristate "omap isp resizer"
++        depends on VIDEO_OMAP34XX_ISP && !ARCH_OMAP3410
++
+Index: git/drivers/media/video/Makefile
+===================================================================
+--- git.orig/drivers/media/video/Makefile	2009-02-12 11:02:15.000000000 -0600
++++ git/drivers/media/video/Makefile	2009-02-12 11:03:13.000000000 -0600
+@@ -18,6 +18,8 @@
+   obj-$(CONFIG_VIDEO_DEV) += v4l1-compat.o
+ endif
+ 
++obj-y += isp/
++
+ obj-$(CONFIG_VIDEO_TUNER) += tuner.o
+ 
+ obj-$(CONFIG_VIDEO_BT848) += bt8xx/
+Index: git/drivers/media/video/isp/Makefile
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/Makefile	2009-02-12 11:13:53.000000000 -0600
+@@ -0,0 +1,9 @@
++# Makefile for OMAP3 ISP driver
++
++obj-$(CONFIG_VIDEO_OMAP34XX_ISP) += isp.o ispccdc.o ispmmu.o
++
++obj-$(CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER) += isppreview.o isph3a.o isphist.o \
++	omap_previewer.o isp_af.o
++
++obj-$(CONFIG_VIDEO_OMAP34XX_ISP_RESIZER) += ispresizer.o omap_resizer.o
++
+Index: git/drivers/media/video/isp/ispccd_lsc.dat
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ git/drivers/media/video/isp/ispccd_lsc.dat	2009-02-12 11:38:30.000000000 -0600
+@@ -0,0 +1,123 @@
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+Index: git/include/media/videobuf-dma-sg.h
+===================================================================
+--- git.orig/include/media/videobuf-dma-sg.h	2009-02-12 12:03:38.000000000 -0600
++++ git/include/media/videobuf-dma-sg.h	2009-02-12 14:02:41.000000000 -0600
+@@ -68,6 +68,9 @@
+ 	/* for kernel buffers */
+ 	void                *vmalloc;
+ 
++	/* Stores the userspace pointer to vmalloc area */
++	void                *varea;
++
+ 	/* for overlay buffers (pci-pci dma) */
+ 	dma_addr_t          bus_addr;
+ 
diff --git a/recipes/linux/linux-omap-2.6.28/beagleboard/defconfig b/recipes/linux/linux-omap-2.6.28/beagleboard/defconfig
new file mode 100644
index 0000000000..45958e0e07
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/beagleboard/defconfig
@@ -0,0 +1,2189 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-omap1
+# Wed Jan 14 19:12:03 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_TICK_GPTIMER=12
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+CONFIG_OMAP2_DSS_VENC=y
+# CONFIG_OMAP2_DSS_SDI is not set
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_USE_DSI_PLL=y
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_OMAP3EVM is not set
+CONFIG_MACH_OMAP3_BEAGLE=y
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+# CONFIG_ARM_ERRATUM_451034 is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_VERBOSE is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=y
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=y
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+CONFIG_IEEE80211_CRYPT_CCMP=y
+CONFIG_IEEE80211_CRYPT_TKIP=y
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_93CX6=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_MII=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=y
+CONFIG_LIBERTAS_USB=y
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=y
+CONFIG_USB_NET_RNDIS_WLAN=y
+CONFIG_RTL8187=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_P54_COMMON=y
+CONFIG_P54_USB=y
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_ZD1211RW=y
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_RT2X00=y
+CONFIG_RT2500USB=y
+CONFIG_RT73USB=y
+CONFIG_RT2X00_LIB_USB=y
+CONFIG_RT2X00_LIB=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=y
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C2_OMAP_BEAGLE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_PWRBUTTON=y
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_LP5521 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_OMAP24XX is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_POWER is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX2341X=m
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+CONFIG_USB_M5602=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+# CONFIG_VIDEO_EM28XX is not set
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_USBVIDEO=m
+CONFIG_USB_VICAM=m
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_KONICAWC=m
+CONFIG_USB_QUICKCAM_MESSENGER=m
+# CONFIG_USB_ET61X251 is not set
+CONFIG_VIDEO_OVCAMCHIP=m
+CONFIG_USB_W9968CF=m
+CONFIG_USB_OV511=m
+CONFIG_USB_SE401=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_STV680=m
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_ZR364XX=m
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_DVB_SIANO_SMS1XXX=m
+CONFIG_DVB_SIANO_SMS1XXX_SMS_IDS=y
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+# CONFIG_DVB_DRX397XD is not set
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+# CONFIG_DVB_LGS8GL5 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+CONFIG_DVB_AF9013=m
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=14
+CONFIG_FB_OMAP2=y
+CONFIG_FB_OMAP2_DEBUG=y
+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
+CONFIG_FB_OMAP2_NUM_FBS=3
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_GENERIC=y
+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_PANEL_N800 is not set
+# CONFIG_CTRL_BLIZZARD is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TWL4030=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_OMAP_EHCI_PHY_MODE=y
+# CONFIG_OMAP_EHCI_TLL_MODE is not set
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+# CONFIG_USB_BERRY_CHARGE is not set
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_GPIO_VBUS=y
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+CONFIG_LEDS_OMAP=y
+# CONFIG_LEDS_OMAP_PWM is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_TWL4030=y
+# CONFIG_UIO is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=m
+# CONFIG_EXT4DEV_COMPAT is not set
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=m
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=m
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-omap-2.6.28/beagleboard/logo_linux_clut224.ppm b/recipes/linux/linux-omap-2.6.28/beagleboard/logo_linux_clut224.ppm
new file mode 100644
index 0000000000..d29fc1c544
--- /dev/null
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diff --git a/recipes/linux/linux-omap-2.6.28/cache-display-fix.patch b/recipes/linux/linux-omap-2.6.28/cache-display-fix.patch
new file mode 100644
index 0000000000..019fd5acf1
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/cache-display-fix.patch
@@ -0,0 +1,238 @@
+On Tue, 2008-07-01 at 06:23 +0100, Dirk Behme wrote:
+> Catalin Marinas wrote:
+> > But, anyway, if you want a patch, Harry is updating it to a recent
+> > kernel.
+> 
+> Any news on this? I think there are some people wanting a patch ;)
+
+See below for a preliminary patch updated to 2.6.26-rc8. Note that I
+don't plan to submit it in its current form but clean it up a bit first.
+
+
+Show the cache type of ARMv7 CPUs
+
+From: Catalin Marinas <catalin.marinas@arm.com>
+
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+---
+
+ arch/arm/kernel/setup.c  |  137 +++++++++++++++++++++++++++++++++++++++++++++-
+ include/asm-arm/system.h |   18 ++++++
+ 2 files changed, 153 insertions(+), 2 deletions(-)
+
+
+diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
+index 5ae0eb2..0cd238d 100644
+--- a/arch/arm/kernel/setup.c
++++ b/arch/arm/kernel/setup.c
+@@ -256,6 +256,24 @@ static const char *proc_arch[] = {
+ 	"?(17)",
+ };
+ 
++static const char *v7_cache_policy[4] = {
++	"reserved",
++	"AVIVT",
++	"VIPT",
++	"PIPT",
++};
++
++static const char *v7_cache_type[8] = {
++	"none",
++	"instruction only",
++	"data only",
++	"separate instruction and data",
++	"unified",
++	"unknown type",
++	"unknown type",
++	"unknown type",
++};
++
+ #define CACHE_TYPE(x)	(((x) >> 25) & 15)
+ #define CACHE_S(x)	((x) & (1 << 24))
+ #define CACHE_DSIZE(x)	(((x) >> 12) & 4095)	/* only if S=1 */
+@@ -266,6 +284,22 @@ static const char *proc_arch[] = {
+ #define CACHE_M(y)	((y) & (1 << 2))
+ #define CACHE_LINE(y)	((y) & 3)
+ 
++#define CACHE_TYPE_V7(x)	(((x) >> 14) & 3)
++#define CACHE_UNIFIED(x)	((((x) >> 27) & 7)+1)
++#define CACHE_COHERENT(x)	((((x) >> 24) & 7)+1)
++
++#define CACHE_ID_LEVEL_MASK	7
++#define CACHE_ID_LEVEL_BITS	3
++
++#define CACHE_LINE_V7(v)	((1 << (((v) & 7)+4)))
++#define CACHE_ASSOC_V7(v)	((((v) >> 3) & ((1<<10)-1))+1)
++#define CACHE_SETS_V7(v)	((((v) >> 13) & ((1<<15)-1))+1)
++#define CACHE_SIZE_V7(v)	(CACHE_LINE_V7(v)*CACHE_ASSOC_V7(v)*CACHE_SETS_V7(v))
++#define CACHE_WA_V7(v)		(((v) & (1<<28)) != 0)
++#define CACHE_RA_V7(v)		(((v) & (1<<29)) != 0)
++#define CACHE_WB_V7(v)		(((v) & (1<<30)) != 0)
++#define CACHE_WT_V7(v)		(((v) & (1<<31)) != 0)
++
+ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
+ {
+ 	unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
+@@ -279,11 +313,57 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
+ 			CACHE_LINE(cache)));
+ }
+ 
++static void dump_v7_cache(const char *type, int cpu, unsigned int level)
++{
++	unsigned int cachesize;
++                    
++	write_extended_cpuid(2,0,0,0,level);  /* Set the cache size selection register */
++	write_extended_cpuid(0,7,5,4,0);      /* Prefetch flush to wait for above */
++	cachesize = read_extended_cpuid(1,0,0,0);
++
++	printk("CPU%u: %s cache: %d bytes, associativity %d, %d byte lines, %d sets,\n      supports%s%s%s%s\n",
++	       cpu, type,
++	       CACHE_SIZE_V7(cachesize),CACHE_ASSOC_V7(cachesize),
++	       CACHE_LINE_V7(cachesize),CACHE_SETS_V7(cachesize),
++	       CACHE_WA_V7(cachesize) ? " WA" : "",
++	       CACHE_RA_V7(cachesize) ? " RA" : "",
++	       CACHE_WB_V7(cachesize) ? " WB" : "",
++	       CACHE_WT_V7(cachesize) ? " WT" : "");
++}
++
+ static void __init dump_cpu_info(int cpu)
+ {
+ 	unsigned int info = read_cpuid(CPUID_CACHETYPE);
+ 
+-	if (info != processor_id) {
++	if (info != processor_id && (info & (1 << 31))) {
++		/* ARMv7 style of cache info register */
++		unsigned int id = read_extended_cpuid(1,0,0,1);
++		unsigned int level = 0;
++		printk("CPU%u: L1 I %s cache. Caches unified at level %u, coherent at level %u\n",
++		       cpu,
++		       v7_cache_policy[CACHE_TYPE_V7(info)],
++		       CACHE_UNIFIED(id),
++		       CACHE_COHERENT(id));
++
++		while (id & CACHE_ID_LEVEL_MASK) {
++			printk("CPU%u: Level %u cache is %s\n",
++			       cpu, (level >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]);
++
++			if (id & 1) {
++				/* Dump I at this level */
++				dump_v7_cache("I", cpu, level | 1);
++			}
++
++			if (id & (4 | 2)) {
++				/* Dump D or unified at this level */
++				dump_v7_cache((id & 4) ? "unified" : "D", cpu, level);
++			}
++
++			/* Next level out */
++			level += 2;
++			id >>= CACHE_ID_LEVEL_BITS;
++		}
++	} else if (info != processor_id) {
+ 		printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
+ 		       cache_types[CACHE_TYPE(info)]);
+ 		if (CACHE_S(info)) {
+@@ -916,6 +996,30 @@ c_show_cache(struct seq_file *m, const char *type, unsigned int cache)
+ 			    CACHE_LINE(cache)));
+ }
+ 
++static void c_show_v7_cache(struct seq_file *m, const char *type, unsigned int levelselect)
++{
++	unsigned int cachesize;
++	unsigned int level = (levelselect >> 1) + 1;
++                    
++	write_extended_cpuid(2,0,0,0,levelselect);  /* Set the cache size selection register */
++	write_extended_cpuid(0,7,5,4,0);      /* Prefetch flush to wait for above */
++	cachesize = read_extended_cpuid(1,0,0,0);
++
++	seq_printf(m, "L%u %s size\t\t: %d bytes\n"
++		   "L%u %s assoc\t\t: %d\n"
++		   "L%u %s line length\t: %d\n"
++		   "L%u %s sets\t\t: %d\n"
++		   "L%u %s supports\t\t:%s%s%s%s\n",
++		   level, type, CACHE_SIZE_V7(cachesize),
++		   level, type, CACHE_ASSOC_V7(cachesize),
++		   level, type, CACHE_LINE_V7(cachesize),
++		   level, type, CACHE_SETS_V7(cachesize),
++		   level, type, CACHE_WA_V7(cachesize) ? " WA" : "",
++		   CACHE_RA_V7(cachesize) ? " RA" : "",
++		   CACHE_WB_V7(cachesize) ? " WB" : "",
++		   CACHE_WT_V7(cachesize) ? " WT" : "");
++}
++
+ static int c_show(struct seq_file *m, void *v)
+ {
+ 	int i;
+@@ -971,7 +1075,36 @@ static int c_show(struct seq_file *m, void *v)
+ 
+ 	{
+ 		unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
+-		if (cache_info != processor_id) {
++		if (cache_info != processor_id && (cache_info & (1<<31))) {
++			/* V7 style of cache info register */
++			unsigned int id = read_extended_cpuid(1,0,0,1);
++			unsigned int levelselect = 0;
++			seq_printf(m, "L1 I cache\t:%s\n"
++				   "Cache unification level\t: %u\n"
++				   "Cache coherency level\t: %u\n",
++				   v7_cache_policy[CACHE_TYPE_V7(cache_info)],
++				   CACHE_UNIFIED(id),
++				   CACHE_COHERENT(id));
++
++			while (id & CACHE_ID_LEVEL_MASK) {
++				seq_printf(m, "Level %u cache\t\t: %s\n",
++					   (levelselect >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]);
++
++				if (id & 1) {
++					/* Dump I at this level */
++					c_show_v7_cache(m, "I", levelselect | 1);
++				}
++
++				if (id & (4 | 2)) {
++					/* Dump D or unified at this level */
++					c_show_v7_cache(m, (id & 4) ? "cache" : "D", levelselect);
++				}
++
++				/* Next level out */
++				levelselect += 2;
++				id >>= CACHE_ID_LEVEL_BITS;
++			}
++		} else if (cache_info != processor_id) {
+ 			seq_printf(m, "Cache type\t: %s\n"
+ 				      "Cache clean\t: %s\n"
+ 				      "Cache lockdown\t: %s\n"
+diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
+index 514af79..704738e 100644
+--- a/arch/arm/include/asm/system.h
++++ b/arch/arm/include/asm/system.h
+@@ -74,6 +74,24 @@
+ 		    : "cc");						\
+ 		__val;							\
+ 	})
++#define read_extended_cpuid(op1,op2,op3,op4)		\
++	({								\
++		unsigned int __val;					\
++		asm("mrc p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4)	\
++		    : "=r" (__val)					\
++		    :							\
++		    : "cc");						\
++		__val;							\
++	})
++
++#define write_extended_cpuid(op1,op2,op3,op4,v)		\
++	({								\
++		unsigned int __val = v;					\
++		asm("mcr p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4)	\
++		    :							\
++		    : "r" (__val)					\
++		    : "cc");						\
++	})
+ #else
+ extern unsigned int processor_id;
+ #define read_cpuid(reg) (processor_id)
+
+
+-- 
+Catalin
+
+
diff --git a/recipes/linux/linux-omap-2.6.28/dvb-fix-dma.diff b/recipes/linux/linux-omap-2.6.28/dvb-fix-dma.diff
new file mode 100644
index 0000000000..e05473fc7f
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/dvb-fix-dma.diff
@@ -0,0 +1,60 @@
+Hi,
+I post this patch that fixes a kernel crash that happens when using a dvb
+usb stick on a mips platform and I think even on other platforms on which
+the dma access in not cache-coherent.
+
+The problem's origin is that, inside the method usb_bulk_urb_init of file
+drivers/media/dvb/dvb-usb/usb-urb.c, stream->urb_list[i]->transfer_buffer
+points to a memory area that has been allocated to be dma-coherent but
+stream->urb_list[i]->transfer_flags doesn't include the
+URB_NO_TRANSFER_DMA_MAP flag and stream->urb_list[i]->transfer_dma is not
+set.
+When later on the stream->urb_list[i]->transfer_buffer pointer is used
+inside function usb_hcd_submit_urb of file drivers/usb/core/hcd.c since the
+flag URB_NO_TRANSFER_DMA_MAP is not set the urb->transfer_buffer pointer is
+passed to the dma_map_single function that since the address is dma-coherent
+returns a wrong tranfer_dma address that later on leads to the kernel crash.
+
+The problem is solved by setting the URB_NO_TRANSFER_DMA_MAP flag and the
+stream->urb_list[i]->transfer_dma address.
+
+Perhaps to be more safe the URB_NO_TRANSFER_DMA_MAP flag can be set only
+if stream->urb_list[i]->transfer_dma != 0.
+
+I don't know if half of the fault can be of the dma_map_single function that
+should anyway returns a valid address both for a not dma-coherent and a
+dma-coherent address.
+
+Just to be clear:
+I've done this patch to solve my problem and I tested it only on a mips 
+platform
+but I think it should not cause any problems on other platforms.
+I posted it here to help someone else that can have my same problem and to 
+point it out
+to the mantainer of this part of code.
+You can use it at your own risk and I'm not resposible in any way for any 
+problem or
+damage that it can cause.
+I'm available to discuss about it
+
+Bye
+
+Michele Scorcia
+
+--------------------
+
+
+
+
+--- /tmp/usb-urb.c	2008-10-08 09:53:23.000000000 +0200
++++ git/drivers/media/dvb/dvb-usb/usb-urb.c	2008-10-08 09:54:16.000000000 +0200
+@@ -152,7 +152,8 @@
+ 				stream->props.u.bulk.buffersize,
+ 				usb_urb_complete, stream);
+ 
+-		stream->urb_list[i]->transfer_flags = 0;
++		stream->urb_list[i]->transfer_flags = URB_NO_TRANSFER_DMA_MAP;
++		stream->urb_list[i]->transfer_dma = stream->dma_addr[i];	
+ 		stream->urbs_initialized++;
+ 	}
+ 	return 0;
diff --git a/recipes/linux/linux-omap-2.6.28/evm-mcspi-ts.diff b/recipes/linux/linux-omap-2.6.28/evm-mcspi-ts.diff
new file mode 100644
index 0000000000..64d797cf96
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/evm-mcspi-ts.diff
@@ -0,0 +1,132 @@
+From linux-omap-owner@vger.kernel.org Sun Nov 02 21:08:25 2008
+Received: from localhost
+	([127.0.0.1] helo=dominion ident=koen)
+	by dominion.dominion.void with esmtp (Exim 4.69)
+	(envelope-from <linux-omap-owner@vger.kernel.org>)
+	id 1KwjFJ-0008Hg-0T
+	for koen@localhost; Sun, 02 Nov 2008 21:08:25 +0100
+Received: from xs.service.utwente.nl [130.89.5.250]
+	by dominion with POP3 (fetchmail-6.3.9-rc2)
+	for <koen@localhost> (single-drop); Sun, 02 Nov 2008 21:08:25 +0100 (CET)
+Received: from mail.service.utwente.nl ([130.89.5.253]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959);
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+        Sun, 02 Nov 2008 11:56:31 -0800 (PST)
+From: Grazvydas Ignotas <notasas@gmail.com>
+To: linux-omap@vger.kernel.org
+Cc: Grazvydas Ignotas <notasas@gmail.com>
+Subject: Re: omap3evm LCD red-tint workaround
+Date: 	Sun,  2 Nov 2008 21:56:19 +0200
+Message-Id: <1225655779-18934-1-git-send-email-notasas@gmail.com>
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+
+> PS: TS is still unusable with the 16x16 pixel resolution
+This is also the case for Pandora. The patch below fixes the problem,
+but as I have no other boards to test this on, I haven't sent it.
+See if it helps you.
+
+
+From 91f3af26bbf751b846e6265d86387e81be7c1364 Mon Sep 17 00:00:00 2001
+From: Grazvydas Ignotas <notasas@gmail.com>
+Date: Tue, 28 Oct 2008 22:01:42 +0200
+Subject: [PATCH] OMAP3: fix McSPI transfers
+
+Currently on OMAP3 if both write and read is set up for a transfer,
+the first byte returned on read is corrupted. Work around this by
+disabling channel between reads and writes, instead of transfers.
+---
+ drivers/spi/omap2_mcspi.c |    7 ++++---
+ 1 files changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
+index 454a271..4890b6c 100644
+--- a/drivers/spi/omap2_mcspi.c
++++ b/drivers/spi/omap2_mcspi.c
+@@ -710,7 +710,6 @@ static void omap2_mcspi_work(struct work_struct *work)
+ 		spi = m->spi;
+ 		cs = spi->controller_state;
+ 
+-		omap2_mcspi_set_enable(spi, 1);
+ 		list_for_each_entry(t, &m->transfers, transfer_list) {
+ 			if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
+ 				status = -EINVAL;
+@@ -741,6 +740,8 @@ static void omap2_mcspi_work(struct work_struct *work)
+ 			if (t->len) {
+ 				unsigned	count;
+ 
++				omap2_mcspi_set_enable(spi, 1);
++
+ 				/* RX_ONLY mode needs dummy data in TX reg */
+ 				if (t->tx_buf == NULL)
+ 					__raw_writel(0, cs->base
+@@ -752,6 +753,8 @@ static void omap2_mcspi_work(struct work_struct *work)
+ 					count = omap2_mcspi_txrx_pio(spi, t);
+ 				m->actual_length += count;
+ 
++				omap2_mcspi_set_enable(spi, 0);
++
+ 				if (count != t->len) {
+ 					status = -EIO;
+ 					break;
+@@ -777,8 +780,6 @@ static void omap2_mcspi_work(struct work_struct *work)
+ 		if (cs_active)
+ 			omap2_mcspi_force_cs(spi, 0);
+ 
+-		omap2_mcspi_set_enable(spi, 0);
+-
+ 		m->status = status;
+ 		m->complete(m->context);
+ 
+-- 
+1.5.4.3
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
+
diff --git a/recipes/linux/linux-omap-2.6.28/fix-clkrate-programming.diff b/recipes/linux/linux-omap-2.6.28/fix-clkrate-programming.diff
new file mode 100644
index 0000000000..10369d4200
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/fix-clkrate-programming.diff
@@ -0,0 +1,57 @@
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 17 Oct 2008 22:18:42 +0000 (-0600)
+Subject: OMAP3 clock: fix non-CORE DPLL rate assignment bugs
+X-Git-Tag: v2.6.27-omap1~8
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftmlind%2Flinux-omap-2.6.git;a=commitdiff_plain;h=2ac1da8c787f73f067e717408e631501ba60aabc
+
+OMAP3 clock: fix non-CORE DPLL rate assignment bugs
+
+Commit 8b1f0bd44fe490ec631230c8c040753a2bda8caa introduced a bug that
+caused non-CORE DPLL rates to be incorrectly set on boot in
+omap3_noncore_dpll_enable().  Debugged by Tomi Valkeinen
+<tomi.valkeinen@nokia.com> - thanks Tomi.
+
+Also fix omap3_noncore_dpll_set_rate() to assign clk->rate after a
+DPLL reprogram.
+
+Tested on 3430SDP.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Cc: Rick Bronson <rick@efn.org>
+Cc: Timo Kokkonen <timo.t.kokkonen@nokia.com>
+Cc: Sakari Poussa <sakari.poussa@nokia.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+
+diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
+index df258f7..cc43f4f 100644
+--- a/arch/arm/mach-omap2/clock34xx.c
++++ b/arch/arm/mach-omap2/clock34xx.c
+@@ -271,7 +271,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
+ static int omap3_noncore_dpll_enable(struct clk *clk)
+ {
+ 	int r;
+-	long rate;
+ 	struct dpll_data *dd;
+ 
+ 	if (clk == &dpll3_ck)
+@@ -287,7 +286,7 @@ static int omap3_noncore_dpll_enable(struct clk *clk)
+ 		r = _omap3_noncore_dpll_lock(clk);
+ 
+ 	if (!r)
+-		clk->rate = rate;
++		clk->rate = omap2_get_dpll_rate(clk);
+ 
+ 	return r;
+ }
+@@ -430,6 +429,9 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
+ 		ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
+ 						 dd->last_rounded_n, freqsel);
+ 
++		if (!ret)
++			clk->rate = rate;
++
+ 	}
+ 
+ 	omap3_dpll_recalc(clk);
diff --git a/recipes/linux/linux-omap-2.6.28/fix-dpll-m4.diff b/recipes/linux/linux-omap-2.6.28/fix-dpll-m4.diff
new file mode 100644
index 0000000000..1fa3bfe7fe
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/fix-dpll-m4.diff
@@ -0,0 +1,37 @@
+From linux-omap-owner@vger.kernel.org Mon Dec 08 14:41:05 2008
+
+This fixes commit e42218d45afbc3e654e289e021e6b80c657b16c2. The commit
+was based on old kernel tree, and with bad luck applied ok but to wrong
+position, modifying dpll4_m6_ck instead of dpll4_m4_ck.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/mach-omap2/clock34xx.h |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
+index 1c2b49f..5357507 100644
+--- a/arch/arm/mach-omap2/clock34xx.h
++++ b/arch/arm/mach-omap2/clock34xx.h
+@@ -825,6 +825,8 @@ static struct clk dpll4_m4_ck = {
+ 				PARENT_CONTROLS_CLOCK,
+ 	.clkdm		= { .name = "dpll4_clkdm" },
+ 	.recalc		= &omap2_clksel_recalc,
++	.set_rate	= &omap2_clksel_set_rate,
++	.round_rate	= &omap2_clksel_round_rate,
+ };
+ 
+ /* The PWRDN bit is apparently only available on 3430ES2 and above */
+@@ -879,8 +881,6 @@ static struct clk dpll4_m6_ck = {
+ 				PARENT_CONTROLS_CLOCK,
+ 	.clkdm		= { .name = "dpll4_clkdm" },
+ 	.recalc		= &omap2_clksel_recalc,
+-	.set_rate	= &omap2_clksel_set_rate,
+-	.round_rate	= &omap2_clksel_round_rate,
+ };
+ 
+ /* The PWRDN bit is apparently only available on 3430ES2 and above */
+-- 
+1.6.0.3
+
+
diff --git a/recipes/linux/linux-omap-2.6.28/fix-install.patch b/recipes/linux/linux-omap-2.6.28/fix-install.patch
new file mode 100644
index 0000000000..46bc25a50b
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/fix-install.patch
@@ -0,0 +1,23 @@
+From: Steve Sakoman <steve@sakoman.com>
+Date: Mon, 18 Aug 2008 16:07:31 +0000 (-0700)
+Subject: scripts/Makefile.fwinst: add missing space when setting mode in cmd_install
+X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=f039944bdd491cde7327133e9976881d3133ae70
+
+scripts/Makefile.fwinst: add missing space when setting mode in cmd_install
+
+This was causing build failures on some machines
+---
+
+diff --git a/scripts/Makefile.fwinst b/scripts/Makefile.fwinst
+index 6bf8e87..fb20532 100644
+--- a/scripts/Makefile.fwinst
++++ b/scripts/Makefile.fwinst
+@@ -37,7 +37,7 @@ install-all-dirs: $(installed-fw-dirs)
+ 	@true
+ 
+ quiet_cmd_install = INSTALL $(subst $(srctree)/,,$@)
+-      cmd_install = $(INSTALL) -m0644 $< $@
++      cmd_install = $(INSTALL) -m 0644 $< $@
+ 
+ $(installed-fw-dirs):
+ 	$(call cmd,mkdir)
diff --git a/recipes/linux/linux-omap-2.6.28/fix-irq33.diff b/recipes/linux/linux-omap-2.6.28/fix-irq33.diff
new file mode 100644
index 0000000000..709f042ab7
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/fix-irq33.diff
@@ -0,0 +1,111 @@
+From: "Nathan Monson" <nmonson@gmail.com>
+To: "linux-omap@vger.kernel.org List" <linux-omap@vger.kernel.org>
+Subject: Re: omapfb: help from userspace
+Cc: "TK, Pratheesh Gangadhar" <pratheesh@ti.com>
+
+On Wed, Oct 8, 2008 at 11:36 AM, Nathan Monson <nmonson@gmail.com> wrote:
+> "Felipe Contreras" <felipe.contreras@gmail.com> writes:
+>> irq -33, desc: c0335cf8, depth: 0, count: 0, unhandled: 0
+>
+> On the BeagleBoard list, Pratheesh Gangadhar said that mapping I/O
+> regions as Strongly Ordered suppresses this problem:
+> http://groups.google.com/group/beagleboard/browse_thread/thread/23e1c95b4bfb09b5/70d12dca569ca503?show_docid=70d12dca569ca503
+
+Pratheesh helped me make a patch against the latest linux-omap git to
+try this.
+
+With this patch, my IRQ -33 problems with the DSP have disappeared.
+Before, I would end up in IRQ -33 loop after 10 invocations of the DSP
+Bridge 'ping.out' utility.  I just finished running it 50,000 times
+without error.
+
+As stated before, this patch is just a workaround for testing
+purposes, not a fix.  Who knows what performance side effects it
+has...
+
+---
+diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
+index 9eb936e..5cb4f5f 100644
+--- a/arch/arm/include/asm/mach/map.h
++++ b/arch/arm/include/asm/mach/map.h
+@@ -25,6 +25,7 @@ struct map_desc {
+ #define MT_HIGH_VECTORS		8
+ #define MT_MEMORY		9
+ #define MT_ROM			10
++#define MT_MEMORY_SO		11
+
+ #define MT_NONSHARED_DEVICE	MT_DEVICE_NONSHARED
+ #define MT_IXP2000_DEVICE	MT_DEVICE_IXP2000
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index adbe21f..c11c0e8 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -119,13 +119,13 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
+ 		.virtual	= L3_34XX_VIRT,
+ 		.pfn		= __phys_to_pfn(L3_34XX_PHYS),
+ 		.length		= L3_34XX_SIZE,
+-		.type		= MT_DEVICE
++		.type		= MT_MEMORY_SO
+ 	},
+ 	{
+ 		.virtual	= L4_34XX_VIRT,
+ 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
+ 		.length		= L4_34XX_SIZE,
+-		.type		= MT_DEVICE
++		.type		= MT_MEMORY_SO
+ 	},
+ 	{
+ 		.virtual	= L4_WK_34XX_VIRT,
+@@ -137,19 +137,19 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
+ 		.virtual	= OMAP34XX_GPMC_VIRT,
+ 		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
+ 		.length		= OMAP34XX_GPMC_SIZE,
+-		.type		= MT_DEVICE
++		.type		= MT_MEMORY_SO
+ 	},
+ 	{
+ 		.virtual	= OMAP343X_SMS_VIRT,
+ 		.pfn		= __phys_to_pfn(OMAP343X_SMS_PHYS),
+ 		.length		= OMAP343X_SMS_SIZE,
+-		.type		= MT_DEVICE
++		.type		= MT_MEMORY_SO
+ 	},
+ 	{
+ 		.virtual	= OMAP343X_SDRC_VIRT,
+ 		.pfn		= __phys_to_pfn(OMAP343X_SDRC_PHYS),
+ 		.length		= OMAP343X_SDRC_SIZE,
+-		.type		= MT_DEVICE
++		.type		= MT_MEMORY_SO
+ 	},
+ 	{
+ 		.virtual	= L4_PER_34XX_VIRT,
+@@ -161,7 +161,7 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
+ 		.virtual	= L4_EMU_34XX_VIRT,
+ 		.pfn		= __phys_to_pfn(L4_EMU_34XX_PHYS),
+ 		.length		= L4_EMU_34XX_SIZE,
+-		.type		= MT_DEVICE
++		.type		= MT_MEMORY_SO
+ 	},
+ };
+ #endif
+diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
+index a713e40..d5f25ad 100644
+--- a/arch/arm/mm/mmu.c
++++ b/arch/arm/mm/mmu.c
+@@ -245,6 +245,10 @@ static struct mem_type mem_types[] = {
+ 		.prot_sect = PMD_TYPE_SECT,
+ 		.domain    = DOMAIN_KERNEL,
+ 	},
++	[MT_MEMORY_SO] = {
++		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_UNCACHED,
++		.domain    = DOMAIN_KERNEL,
++	},
+ };
+
+ const struct mem_type *get_mem_type(unsigned int type)
+--
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
+
diff --git a/recipes/linux/linux-omap-2.6.28/mru-256MB.diff b/recipes/linux/linux-omap-2.6.28/mru-256MB.diff
new file mode 100644
index 0000000000..0492ca2d8f
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/mru-256MB.diff
@@ -0,0 +1,24 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Thu, 2 Oct 2008 00:05:33 +0000 (+0100)
+Subject: OMAP: Increase VMALLOC_END to allow 256MB RAM
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=355a0ce968e4a7b0c8d8203f4517296e932e373d
+
+OMAP: Increase VMALLOC_END to allow 256MB RAM
+
+This increases VMALLOC_END to 0x18000000, making room for 256MB
+RAM with the default 128MB vmalloc region.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
+index d8515cb..b97dfaf 100644
+--- a/arch/arm/plat-omap/include/mach/vmalloc.h
++++ b/arch/arm/plat-omap/include/mach/vmalloc.h
+@@ -17,5 +17,5 @@
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+  */
+-#define VMALLOC_END	  (PAGE_OFFSET + 0x17000000)
++#define VMALLOC_END	  (PAGE_OFFSET + 0x18000000)
+ 
diff --git a/recipes/linux/linux-omap-2.6.28/mru-enable-overlay-optimalization.diff b/recipes/linux/linux-omap-2.6.28/mru-enable-overlay-optimalization.diff
new file mode 100644
index 0000000000..d027c53d6b
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/mru-enable-overlay-optimalization.diff
@@ -0,0 +1,117 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Fri, 29 Aug 2008 01:45:26 +0000 (+0100)
+Subject: OMAP: Enable overlay optimisation
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=7e052af7e4c73dc450412486ad37eb529e725dc7
+
+OMAP: Enable overlay optimisation
+
+This enables the overlay optimisation feature when the video
+overlay is active. This reduces memory bandwidth used by the
+display subsystem, improving overall performance.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index 888d2c2..0f0b2e5 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -315,6 +315,60 @@ void omap_dispc_enable_digit_out(int enable)
+ }
+ EXPORT_SYMBOL(omap_dispc_enable_digit_out);
+ 
++#define MIN(a, b) ((a)<(b)?(a):(b))
++#define MAX(a, b) ((a)>(b)?(a):(b))
++
++static void setup_overlay_opt(void)
++{
++	struct fb_info **fbi = dispc.fbdev->fb_info;
++	struct omapfb_plane_struct *gfx, *vid;
++	struct fb_var_screeninfo *gvar;
++	unsigned gx, gx2, gy, gy2, gw, gh;
++	unsigned vx, vx2, vy, vy2, vw, vh;
++	unsigned bpp, skip;
++	static unsigned last_skip;
++
++	if (!fbi[0] || !fbi[1])
++		return;
++
++	gfx = fbi[0]->par;
++	vid = fbi[1]->par;
++	gvar = &fbi[0]->var;
++
++	gx = gfx->info.pos_x;
++	gy = gfx->info.pos_y;
++	gw = gfx->info.out_width;
++	gh = gfx->info.out_height;
++	vx = vid->info.pos_x;
++	vy = vid->info.pos_y;
++	vw = vid->info.out_width;
++	vh = vid->info.out_height;
++	gx2 = gx + gw;
++	gy2 = gy + gh;
++	vx2 = vx + vw;
++	vy2 = vy + vh;
++	bpp = gvar->bits_per_pixel / 8;
++
++	if (!gfx->info.enabled || !vid->info.enabled ||
++	    dispc.color_key.key_type != OMAPFB_COLOR_KEY_DISABLED) {
++		skip = 0;
++	} else if (vx <= gx && vx2 >= gx2) {
++		unsigned y = MIN(gy2, vy2) - MAX(gy, vy);
++		skip = y * gvar->xres_virtual * bpp;
++	} else if (vx <= gx || vx2 >= gx2) {
++		unsigned x = MIN(gx2, vx2) - MAX(gx, vx);
++		skip = x * bpp;
++	} else {
++		skip = vw * bpp + 1;
++	}
++
++	if (skip != last_skip) {
++		last_skip = skip;
++		dispc_write_reg(DISPC_GFX_WINDOW_SKIP, skip);
++		MOD_REG_FLD(DISPC_CONTROL, 1<<12, !!skip<<12);
++	}
++}
++
+ static inline int _setup_plane(int plane, int channel_out,
+ 				  u32 paddr, int screen_width,
+ 				  int pos_x, int pos_y, int width, int height,
+@@ -437,6 +491,9 @@ static inline int _setup_plane(int plane, int channel_out,
+ 
+ 	dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
+ 
++	if (plane < 2)
++		setup_overlay_opt();
++
+ 	MOD_REG_FLD(DISPC_CONTROL, 1<<5, 1<<5);
+ 
+ 	return height * screen_width * bpp / 8;
+@@ -585,11 +642,19 @@ static int omap_dispc_enable_plane(int plane, int enable)
+ 	const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
+ 				DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
+ 				DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
++	struct omapfb_plane_struct *pi;
++
+ 	if ((unsigned int)plane > dispc.mem_desc.region_cnt)
+ 		return -EINVAL;
+ 
++	pi = dispc.fbdev->fb_info[plane]->par;
++	pi->info.enabled = enable;
++
+ 	enable_lcd_clocks(1);
+ 	MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);
++	if (plane < 2)
++		setup_overlay_opt();
++	MOD_REG_FLD(DISPC_CONTROL, 1<<5, 1<<5);
+ 	enable_lcd_clocks(0);
+ 
+ 	return 0;
+@@ -633,6 +698,7 @@ static int omap_dispc_set_color_key(struct omapfb_color_key *ck)
+ 	if (val != 0)
+ 		dispc_write_reg(tr_reg, ck->trans_key);
+ 	dispc_write_reg(df_reg, ck->background);
++	setup_overlay_opt();
+ 	enable_lcd_clocks(0);
+ 
+ 	dispc.color_key = *ck;
diff --git a/recipes/linux/linux-omap-2.6.28/mru-fix-display-panning.diff b/recipes/linux/linux-omap-2.6.28/mru-fix-display-panning.diff
new file mode 100644
index 0000000000..a4ba3d29f4
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/mru-fix-display-panning.diff
@@ -0,0 +1,49 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Fri, 29 Aug 2008 01:18:48 +0000 (+0100)
+Subject: OMAP: Fix omapfb display panning
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2ea46e9f28ff57a32d87bc380457a584c913fe78
+
+OMAP: Fix omapfb display panning
+
+This makes the FBIOPAN_DISPLAY ioctl work with omapfb.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index ce4c4de..64bf333 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -436,6 +436,8 @@ static inline int _setup_plane(int plane, int channel_out,
+ 
+ 	dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
+ 
++	MOD_REG_FLD(DISPC_CONTROL, 1<<5, 1<<5);
++
+ 	return height * screen_width * bpp / 8;
+ }
+ 
+diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
+index e7f3462..e9ffb92 100644
+--- a/drivers/video/omap/omapfb_main.c
++++ b/drivers/video/omap/omapfb_main.c
+@@ -207,8 +207,8 @@ static int ctrl_change_mode(struct fb_info *fbi)
+ 	struct omapfb_device *fbdev = plane->fbdev;
+ 	struct fb_var_screeninfo *var = &fbi->var;
+ 
+-	offset = var->yoffset * fbi->fix.line_length +
+-		 var->xoffset * var->bits_per_pixel / 8;
++	offset = (var->yoffset * var->xres_virtual + var->xoffset) *
++		var->bits_per_pixel / 8;
+ 
+ 	if (fbdev->ctrl->sync)
+ 		fbdev->ctrl->sync();
+@@ -426,6 +426,8 @@ static void set_fb_fix(struct fb_info *fbi)
+ 	}
+ 	fix->accel		= FB_ACCEL_OMAP1610;
+ 	fix->line_length	= var->xres_virtual * bpp / 8;
++	fix->xpanstep		= 1;
++	fix->ypanstep		= 1;
+ }
+ 
+ static int set_color_mode(struct omapfb_plane_struct *plane,
diff --git a/recipes/linux/linux-omap-2.6.28/mru-fix-timings.diff b/recipes/linux/linux-omap-2.6.28/mru-fix-timings.diff
new file mode 100644
index 0000000000..37ca7d33ac
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/mru-fix-timings.diff
@@ -0,0 +1,26 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Fri, 29 Aug 2008 01:16:14 +0000 (+0100)
+Subject: OMAP: Fix video timings info message
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=3a8bdf0967ae2c4eb3cebb97118ef0392f709c1c
+
+OMAP: Fix video timings info message
+
+This fixes the hsync frequency value printed on startup.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
+index d176a2c..e7f3462 100644
+--- a/drivers/video/omap/omapfb_main.c
++++ b/drivers/video/omap/omapfb_main.c
+@@ -1792,7 +1792,8 @@ static int omapfb_do_probe(struct platform_device *pdev,
+ 			vram, fbdev->mem_desc.region_cnt);
+ 	pr_info("omapfb: Pixclock %lu kHz hfreq %lu.%lu kHz "
+ 			"vfreq %lu.%lu Hz\n",
+-			phz / 1000, hhz / 10000, hhz % 10, vhz / 10, vhz % 10);
++			phz / 1000, hhz / 10000, hhz % 10000,
++			vhz / 10, vhz % 10);
+ 
+ 	return 0;
+ 
diff --git a/recipes/linux/linux-omap-2.6.28/mru-improve-pixclock-config.diff b/recipes/linux/linux-omap-2.6.28/mru-improve-pixclock-config.diff
new file mode 100644
index 0000000000..5a702128f2
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/mru-improve-pixclock-config.diff
@@ -0,0 +1,93 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Fri, 29 Aug 2008 01:34:39 +0000 (+0100)
+Subject: OMAP: Improve pixel clock configuration
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=01c2d720e59c291de9eb21eb65225f2f215fef84
+
+OMAP: Improve pixel clock configuration
+
+This sets the DSS1_ALWON_FCLK clock as close as possible to a
+multiple of the requested pixel clock, while keeping it below
+the 173MHz limit.
+
+Due to of the structure of the clock tree, dss1_alwon_fck cannot
+be set directly, and we must use dpll4_m4_ck instead.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index 64bf333..888d2c2 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -177,6 +177,7 @@ static struct {
+ 
+ 	struct clk	*dss_ick, *dss1_fck;
+ 	struct clk	*dss_54m_fck;
++	struct clk	*dpll4_m4_ck;
+ 
+ 	enum omapfb_update_mode	update_mode;
+ 	struct omapfb_device	*fbdev;
+@@ -736,19 +737,34 @@ static void setup_color_conv_coef(void)
+ 	MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
+ }
+ 
++#define MAX_FCK 173000000
++
+ static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
+ {
++	unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++	unsigned long pcd_min = is_tft? 2: 3;
++	unsigned long fck_div;
+ 	unsigned long fck, lck;
+ 
+-	*lck_div = 1;
+ 	pck = max(1, pck);
++
++	if (pck * pcd_min > MAX_FCK) {
++		dev_warn(dispc.fbdev->dev, "pixclock %d kHz too high.\n",
++			 pck / 1000);
++		pck = MAX_FCK / pcd_min;
++	}
++
++	fck = pck * 2;
++	fck_div = (prate + pck) / fck;
++	if (fck_div > 16)
++		fck_div /= (fck_div + 15) / 16;
++	if (fck_div < 1)
++		fck_div = 1;
++	clk_set_rate(dispc.dpll4_m4_ck, prate / fck_div);
+ 	fck = clk_get_rate(dispc.dss1_fck);
+-	lck = fck;
+-	*pck_div = (lck + pck - 1) / pck;
+-	if (is_tft)
+-		*pck_div = max(2, *pck_div);
+-	else
+-		*pck_div = max(3, *pck_div);
++
++	*lck_div = 1;
++	*pck_div = (fck + pck - 1) / pck;
+ 	if (*pck_div > 255) {
+ 		*pck_div = 255;
+ 		lck = pck * *pck_div;
+@@ -909,11 +925,21 @@ static int get_dss_clocks(void)
+ 		return PTR_ERR(dispc.dss_54m_fck);
+ 	}
+ 
++	if (IS_ERR((dispc.dpll4_m4_ck =
++				clk_get(dispc.fbdev->dev, "dpll4_m4_ck")))) {
++		dev_err(dispc.fbdev->dev, "can't get dpll4_m4_ck");
++		clk_put(dispc.dss_ick);
++		clk_put(dispc.dss1_fck);
++		clk_put(dispc.dss_54m_fck);
++		return PTR_ERR(dispc.dss_54m_fck);
++	}
++
+ 	return 0;
+ }
+ 
+ static void put_dss_clocks(void)
+ {
++	clk_put(dispc.dpll4_m4_ck);
+ 	clk_put(dispc.dss_54m_fck);
+ 	clk_put(dispc.dss1_fck);
+ 	clk_put(dispc.dss_ick);
diff --git a/recipes/linux/linux-omap-2.6.28/mru-make-video-timings-selectable.diff b/recipes/linux/linux-omap-2.6.28/mru-make-video-timings-selectable.diff
new file mode 100644
index 0000000000..bba3ef72cc
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/mru-make-video-timings-selectable.diff
@@ -0,0 +1,312 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Fri, 29 Aug 2008 01:42:12 +0000 (+0100)
+Subject: OMAP: Make video mode selectable from pre-defined list
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=7a9e55d7156dae6bc930c77620a88a669d2ed1c9
+
+OMAP: Make video mode selectable from pre-defined list
+
+This adds a list of common video modes and allows one to be
+selected with video=omapfb:mode:name on the command line,
+overriding the defaults from lcd_*.c. A default named mode
+can also be specified in the kernel configuration.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
+index 5ebd591..9977e80 100644
+--- a/drivers/video/omap/Kconfig
++++ b/drivers/video/omap/Kconfig
+@@ -7,26 +7,13 @@ config FB_OMAP
+ 	help
+           Frame buffer driver for OMAP based boards.
+ 
+-choice
+-	depends on FB_OMAP && MACH_OVERO
+-	prompt "Screen resolution"
+-	default FB_OMAP_079M3R
++config FB_OMAP_VIDEO_MODE
++	string "Default video mode"
++	depends on FB_OMAP
+ 	help
+-	  Selected desired screen resolution
+-
+-config FB_OMAP_031M3R
+-	boolean "640 x 480 @ 60 Hz Reduced blanking"
+-
+-config FB_OMAP_048M3R
+-	boolean "800 x 600 @ 60 Hz Reduced blanking"
+-
+-config FB_OMAP_079M3R
+-	boolean "1024 x 768 @ 60 Hz Reduced blanking"
+-
+-config FB_OMAP_092M9R
+-	boolean "1280 x 720 @ 60 Hz Reduced blanking"
+-
+-endchoice
++	  Enter video mode name to use if none is specified on the kernel
++	  command line. If left blank, board-specific default timings
++	  will be used. See omapfb_main.c for a list of valid mode names.
+ 
+ config FB_OMAP_LCDC_EXTERNAL
+ 	bool "External LCD controller support"
+diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
+index e9ffb92..c4c4049 100644
+--- a/drivers/video/omap/omapfb_main.c
++++ b/drivers/video/omap/omapfb_main.c
+@@ -36,6 +36,20 @@
+ 
+ #define MODULE_NAME	"omapfb"
+ 
++struct video_mode {
++	const char	*name;
++	int		x_res, y_res;
++	int		pixel_clock;	/* In kHz */
++	int		hsw;		/* Horizontal synchronization
++					   pulse width */
++	int		hfp;		/* Horizontal front porch */
++	int		hbp;		/* Horizontal back porch */
++	int		vsw;		/* Vertical synchronization
++					   pulse width */
++	int		vfp;		/* Vertical front porch */
++	int		vbp;		/* Vertical back porch */
++};
++
+ static unsigned int	def_accel;
+ static unsigned long	def_vram[OMAPFB_PLANE_NUM];
+ static unsigned int	def_vram_cnt;
+@@ -43,6 +57,7 @@ static unsigned long	def_vxres;
+ static unsigned long	def_vyres;
+ static unsigned int	def_rotate;
+ static unsigned int	def_mirror;
++static char		def_mode[16] = CONFIG_FB_OMAP_VIDEO_MODE;
+ 
+ #ifdef CONFIG_FB_OMAP_MANUAL_UPDATE
+ static int		manual_update = 1;
+@@ -53,6 +68,7 @@ static int		manual_update;
+ static struct platform_device	*fbdev_pdev;
+ static struct lcd_panel		*fbdev_panel;
+ static struct omapfb_device	*omapfb_dev;
++static struct video_mode	video_mode;
+ 
+ struct caps_table_struct {
+ 	unsigned long flag;
+@@ -83,6 +99,152 @@ static struct caps_table_struct color_caps[] = {
+ 	{ 1 << OMAPFB_COLOR_YUY422,	"YUY422", },
+ };
+ 
++static struct video_mode video_modes[] __initdata = {
++	{
++		/* 640 x 480 @ 60 Hz  Reduced blanking VESA CVT 0.31M3-R */
++		.name		= "640x480@60",
++		.x_res		= 640,
++		.y_res		= 480,
++		.hfp		= 48,
++		.hsw		= 32,
++		.hbp		= 80,
++		.vfp		= 3,
++		.vsw		= 4,
++		.vbp		= 7,
++		.pixel_clock	= 23500,
++	},
++	{
++		/* 800 x 600 @ 60 Hz  Reduced blanking VESA CVT 0.48M3-R */
++		.name		= "800x600@60",
++		.x_res		= 800,
++		.y_res		= 600,
++		.hfp		= 48,
++		.hsw		= 32,
++		.hbp		= 80,
++		.vfp		= 3,
++		.vsw		= 4,
++		.vbp		= 11,
++		.pixel_clock	= 35500,
++	},
++	{
++		/* 1024 x 768 @ 60 Hz  Reduced blanking VESA CVT 0.79M3-R */
++		.name		= "1024x768@60",
++		.x_res		= 1024,
++		.y_res		= 768,
++		.hfp		= 48,
++		.hsw		= 32,
++		.hbp		= 80,
++		.vfp		= 3,
++		.vsw		= 4,
++		.vbp		= 15,
++		.pixel_clock	= 56000,
++	},
++	{
++		/* 1280 x 720 @ 60 Hz  Reduced blanking VESA CVT 0.92M9-R */
++		.name		= "1280x720@60",
++		.x_res		= 1280,
++		.y_res		= 720,
++		.hfp		= 48,
++		.hsw		= 32,
++		.hbp		= 80,
++		.vfp		= 3,
++		.vsw		= 5,
++		.vbp		= 13,
++		.pixel_clock	= 64000,
++	},
++	{
++		/* 720 x 480 @ 60 Hz  CEA-861 Format 3 */
++		.name		= "480p60",
++		.x_res		= 720,
++		.y_res		= 480,
++		.hfp		= 16,
++		.hsw		= 62,
++		.hbp		= 60,
++		.vfp		= 9,
++		.vsw		= 6,
++		.vbp		= 30,
++		.pixel_clock	= 27027,
++	},
++	{
++		/* 720 x 576 @ 60 Hz  CEA-861 Format 18 */
++		.name		= "576p50",
++		.x_res		= 720,
++		.y_res		= 576,
++		.hfp		= 12,
++		.hsw		= 64,
++		.hbp		= 68,
++		.vfp		= 5,
++		.vsw		= 5,
++		.vbp		= 39,
++		.pixel_clock	= 27000,
++	},
++	{
++		/* 1280 x 720 @ 50 Hz  CEA-861B Format 19 */
++		.name 		= "720p50",
++		.x_res		= 1280,
++		.y_res		= 720,
++		.hfp		= 440,
++		.hsw		= 40,
++		.hbp		= 220,
++		.vfp		= 20,
++		.vsw		= 5,
++		.vbp		= 5,
++		.pixel_clock	= 74250,
++	},
++	{
++		/* 1280 x 720 @ 60 Hz  CEA-861B Format 4 */
++		.name		= "720p60",
++		.x_res		= 1280,
++		.y_res		= 720,
++		.hfp		= 110,
++		.hsw		= 40,
++		.hbp		= 220,
++		.vfp		= 20,
++		.vsw		= 5,
++		.vbp		= 5,
++		.pixel_clock	= 74250,
++	},
++	{
++		/* 1920 x 1080 @ 24 Hz  CEA-861B Format 32 */
++		.name		= "1080p24",
++		.x_res		= 1920,
++		.y_res		= 1080,
++		.hfp		= 148,
++		.hsw		= 44,
++		.hbp		= 638,
++		.vfp		= 36,
++		.vsw		= 5,
++		.vbp		= 4,
++		.pixel_clock	= 74250,
++	},
++	{
++		/* 1920 x 1080 @ 25 Hz  CEA-861B Format 33 */
++		.name		= "1080p25",
++		.x_res		= 1920,
++		.y_res		= 1080,
++		.hfp		= 148,
++		.hsw		= 44,
++		.hbp		= 528,
++		.vfp		= 36,
++		.vsw		= 5,
++		.vbp		= 4,
++		.pixel_clock	= 74250,
++	},
++	{
++		/* 1920 x 1080 @ 30 Hz  CEA-861B Format 34 */
++		.name		= "1080p30",
++		.x_res		= 1920,
++		.y_res		= 1080,
++		.hfp		= 148,
++		.hsw		= 44,
++		.hbp		= 88,
++		.vfp		= 36,
++		.vsw		= 5,
++		.vbp		= 4,
++		.pixel_clock	= 74250,
++	},
++};
++
+ /*
+  * ---------------------------------------------------------------------------
+  * LCD panel
+@@ -1714,6 +1876,20 @@ static int omapfb_do_probe(struct platform_device *pdev,
+ 		goto cleanup;
+ 	}
+ 
++	if (video_mode.name) {
++		pr_info("omapfb: using mode %s\n", video_mode.name);
++
++		fbdev->panel->x_res	= video_mode.x_res;
++		fbdev->panel->y_res	= video_mode.y_res;
++		fbdev->panel->pixel_clock = video_mode.pixel_clock;
++		fbdev->panel->hsw	= video_mode.hsw;
++		fbdev->panel->hfp	= video_mode.hfp;
++		fbdev->panel->hbp	= video_mode.hbp;
++		fbdev->panel->vsw	= video_mode.vsw;
++		fbdev->panel->vfp	= video_mode.vfp;
++		fbdev->panel->vbp	= video_mode.vbp;
++	}
++
+ 	r = fbdev->panel->init(fbdev->panel, fbdev);
+ 	if (r)
+ 		goto cleanup;
+@@ -1870,6 +2046,17 @@ static struct platform_driver omapfb_driver = {
+ 	},
+ };
+ 
++static void __init omapfb_find_mode(char *name, struct video_mode *vmode)
++{
++	int i;
++
++	for (i = 0; i < sizeof(video_modes)/sizeof(video_modes[0]); i++)
++		if (!strcmp(name, video_modes[i].name)) {
++			*vmode = video_modes[i];
++			break;
++		}
++}
++
+ #ifndef MODULE
+ 
+ /* Process kernel command line parameters */
+@@ -1918,6 +2105,8 @@ static int __init omapfb_setup(char *options)
+ 			def_mirror = (simple_strtoul(this_opt + 7, NULL, 0));
+ 		else if (!strncmp(this_opt, "manual_update", 13))
+ 			manual_update = 1;
++		else if (!strncmp(this_opt, "mode:", 5))
++			strncpy(def_mode, this_opt + 5, sizeof(def_mode));
+ 		else {
+ 			pr_debug("omapfb: invalid option\n");
+ 			r = -1;
+@@ -1939,6 +2128,9 @@ static int __init omapfb_init(void)
+ 		return -ENODEV;
+ 	omapfb_setup(option);
+ #endif
++
++	omapfb_find_mode(def_mode, &video_mode);
++
+ 	/* Register the driver with LDM */
+ 	if (platform_driver_register(&omapfb_driver)) {
+ 		pr_debug("failed to register omapfb driver\n");
+@@ -1960,6 +2152,7 @@ module_param_named(vyres, def_vyres, long, 0664);
+ module_param_named(rotate, def_rotate, uint, 0664);
+ module_param_named(mirror, def_mirror, uint, 0664);
+ module_param_named(manual_update, manual_update, bool, 0664);
++module_param_string(video_mode, def_mode, sizeof(def_mode), 0664);
+ 
+ module_init(omapfb_init);
+ module_exit(omapfb_cleanup);
diff --git a/recipes/linux/linux-omap-2.6.28/musb-support-high-bandwidth.patch.eml b/recipes/linux/linux-omap-2.6.28/musb-support-high-bandwidth.patch.eml
new file mode 100644
index 0000000000..0264a97045
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/musb-support-high-bandwidth.patch.eml
@@ -0,0 +1,134 @@
+Enables support for camera (as creative) requiring high bandwidth
+isochronous transfer.
+
+Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
+---
+ drivers/usb/musb/musb_core.c |   18 +++++++++---------
+ drivers/usb/musb/musb_host.c |   32 +++++++++++++++++++++-----------
+ 2 files changed, 30 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index c939f81..9914f70 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -1063,17 +1063,17 @@ static struct fifo_cfg __initdata mode_4_cfg[] = {
+ { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
+ { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
+ { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
++{ .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket =  64, },
+ { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
++{ .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket =  64, },
+ { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 512, },
+-{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 512, },
+-{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 512, },
+-{ .hw_ep_num = 13, .style = FIFO_TX,   .maxpacket = 512, },
+-{ .hw_ep_num = 13, .style = FIFO_RX,   .maxpacket = 512, },
++{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket =  64, },
++{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
++{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 256, },
++{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
++{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 256, },
++{ .hw_ep_num = 13, .style = FIFO_TX,   .maxpacket = 256, },
++{ .hw_ep_num = 13, .style = FIFO_RX,   .maxpacket = 4096, },
+ { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
+ { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
+ };
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index 08e421f..84173df 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -1443,6 +1443,10 @@ void musb_host_rx(struct musb *musb, u8 epnum)
+ 			/* packet error reported later */
+ 			iso_err = true;
+ 		}
++	} else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
++		DBG(3, "end %d Highbandwidth  incomplete ISO packet received\n"
++					, epnum);
++		status = -EPROTO;
+ 	}
+ 
+ 	/* faults abort the transfer */
+@@ -1595,7 +1599,13 @@ void musb_host_rx(struct musb *musb, u8 epnum)
+ 				val &= ~MUSB_RXCSR_H_AUTOREQ;
+ 			else
+ 				val |= MUSB_RXCSR_H_AUTOREQ;
+-			val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
++
++			if (qh->maxpacket & ~0x7ff)
++				/* Autoclear doesn't work in high bandwidth iso */
++				val |= MUSB_RXCSR_DMAENAB;
++			else
++				val |= MUSB_RXCSR_AUTOCLEAR
++					| MUSB_RXCSR_DMAENAB;
+ 
+ 			musb_writew(epio, MUSB_RXCSR,
+ 				MUSB_RXCSR_H_WZC_BITS | val);
+@@ -1666,6 +1676,7 @@ static int musb_schedule(
+ 	int			best_end, epnum;
+ 	struct musb_hw_ep	*hw_ep = NULL;
+ 	struct list_head	*head = NULL;
++	u16 			maxpacket;
+ 
+ 	/* use fixed hardware for control and bulk */
+ 	switch (qh->type) {
+@@ -1708,6 +1719,13 @@ static int musb_schedule(
+ 	best_diff = 4096;
+ 	best_end = -1;
+ 
++	if (qh->maxpacket & (1<<11))
++		maxpacket = 2 * (qh->maxpacket & 0x7ff);
++	else if (qh->maxpacket & (1<<12))
++		maxpacket = 3 * (qh->maxpacket & 0x7ff);
++	else
++		maxpacket = (qh->maxpacket & 0x7ff);
++
+ 	for (epnum = 1; epnum < musb->nr_endpoints; epnum++) {
+ 		int	diff;
+ 
+@@ -1718,9 +1736,9 @@ static int musb_schedule(
+ 			continue;
+ 
+ 		if (is_in)
+-			diff = hw_ep->max_packet_sz_rx - qh->maxpacket;
++			diff = hw_ep->max_packet_sz_rx - maxpacket;
+ 		else
+-			diff = hw_ep->max_packet_sz_tx - qh->maxpacket;
++			diff = hw_ep->max_packet_sz_tx - maxpacket;
+ 
+ 		if (diff > 0 && best_diff > diff) {
+ 			best_diff = diff;
+@@ -1797,13 +1815,6 @@ static int musb_urb_enqueue(
+ 	qh->is_ready = 1;
+ 
+ 	qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
+-
+-	/* no high bandwidth support yet */
+-	if (qh->maxpacket & ~0x7ff) {
+-		ret = -EMSGSIZE;
+-		goto done;
+-	}
+-
+ 	qh->epnum = epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ 	qh->type = epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+ 
+@@ -1897,7 +1908,6 @@ static int musb_urb_enqueue(
+ 	}
+ 	spin_unlock_irqrestore(&musb->lock, flags);
+ 
+-done:
+ 	if (ret != 0) {
+ 		usb_hcd_unlink_urb_from_ep(hcd, urb);
+ 		kfree(qh);
+-- 
+1.5.6
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
+
diff --git a/recipes/linux/linux-omap-2.6.28/no-cortex-deadlock.patch b/recipes/linux/linux-omap-2.6.28/no-cortex-deadlock.patch
new file mode 100644
index 0000000000..78547c8969
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/no-cortex-deadlock.patch
@@ -0,0 +1,77 @@
+From: Mans Rullgard <mans@mansr.com>
+Date: Sat, 16 Aug 2008 23:03:06 +0000 (+0100)
+Subject: ARM: Workaround for erratum 451034
+X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=b84fa87873ffb68ad23930cf6cddeea8bec43ede
+
+ARM: Workaround for erratum 451034
+
+On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer
+store in the store buffer, can cause a processor deadlock under
+certain conditions.
+
+Executing a DMB instruction before saving NEON/VFP registers and before
+return to userspace makes it safe to run code which includes similar
+counter-measures.  Userspace code can still trigger the deadlock, so
+a different workaround is required to safely run untrusted code.
+
+See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details.
+
+Signed-off-by: Mans Rullgard <mans@mansr.com>
+---
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index aa475d9..41d536e 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1117,6 +1117,22 @@ config NEON
+ 	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
+ 	  Extension.
+ 
++config ARM_ERRATUM_451034
++	bool "Enable workaround for ARM erratum 451034"
++	depends on VFPv3
++	help
++	  On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer
++	  store in the store buffer, can cause a processor deadlock under
++	  certain conditions.
++
++	  See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details.
++
++	  Say Y to include a partial workaround.
++
++	  WARNING: Even with this option enabled, userspace code can trigger
++	  the deadlock.	 To safely run untrusted code, a different fix is
++	  required.
++
+ endmenu
+ 
+ menu "Userspace binary formats"
+diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
+index 422f3cc..934798b 100644
+--- a/arch/arm/include/asm/vfpmacros.h
++++ b/arch/arm/include/asm/vfpmacros.h
+@@ -32,6 +32,9 @@
+ 
+ 	@ write all the working registers out of the VFP
+ 	.macro	VFPFSTMIA, base, tmp
++#ifdef CONFIG_ARM_ERRATUM_451034
++	dmb
++#endif
+ #if __LINUX_ARM_ARCH__ < 6
+ 	STC	p11, cr0, [\base],#33*4		    @ FSTMIAX \base!, {d0-d15}
+ #else
+diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
+index 060d7e2..9799a35 100644
+--- a/arch/arm/kernel/entry-common.S
++++ b/arch/arm/kernel/entry-common.S
+@@ -69,6 +69,10 @@ no_work_pending:
+ 	/* perform architecture specific actions before user return */
+ 	arch_ret_to_user r1, lr
+ 
++#ifdef CONFIG_ARM_ERRATUM_451034
++	dmb
++#endif
++
+ 	@ slow_restore_user_regs
+ 	ldr	r1, [sp, #S_PSR]		@ get calling cpsr
+ 	ldr	lr, [sp, #S_PC]!		@ get pc
diff --git a/recipes/linux/linux-omap-2.6.28/no-empty-flash-warnings.patch b/recipes/linux/linux-omap-2.6.28/no-empty-flash-warnings.patch
new file mode 100644
index 0000000000..ab344b0449
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/no-empty-flash-warnings.patch
@@ -0,0 +1,15 @@
+diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c
+index 1d437de..33b3feb 100644
+--- a/fs/jffs2/scan.c
++++ b/fs/jffs2/scan.c
+@@ -647,8 +647,8 @@ scan_more:
+ 			inbuf_ofs = ofs - buf_ofs;
+ 			while (inbuf_ofs < scan_end) {
+ 				if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) {
+-					printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
+-					       empty_start, ofs);
++//					printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
++//					       empty_start, ofs);
+ 					if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start)))
+ 						return err;
+ 					goto scan_more;
diff --git a/recipes/linux/linux-omap-2.6.28/no-harry-potter.diff b/recipes/linux/linux-omap-2.6.28/no-harry-potter.diff
new file mode 100644
index 0000000000..2bb20ab9c0
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/no-harry-potter.diff
@@ -0,0 +1,11 @@
+--- /tmp/Makefile	2008-04-24 14:36:20.509598016 +0200
++++ git/arch/arm/Makefile	2008-04-24 14:36:31.949546584 +0200
+@@ -47,7 +47,7 @@
+ # Note that GCC does not numerically define an architecture version
+ # macro, but instead defines a whole series of macros which makes
+ # testing for a specific architecture or later rather impossible.
+-arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
++arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+ arch-$(CONFIG_CPU_32v6)		:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+ # Only override the compiler option if ARMv6. The ARMv6K extensions are
+ # always available in ARMv7
diff --git a/recipes/linux/linux-omap-2.6.28/omap-2430-lcd.patch b/recipes/linux/linux-omap-2.6.28/omap-2430-lcd.patch
new file mode 100644
index 0000000000..8f8a687c06
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap-2430-lcd.patch
@@ -0,0 +1,11 @@
+--- git/drivers/video/omap/lcd_2430sdp.c.orig	2007-08-13 14:35:17.000000000 -0700
++++ git/drivers/video/omap/lcd_2430sdp.c	2007-08-13 14:35:55.000000000 -0700
+@@ -32,7 +32,7 @@
+ #define LCD_PANEL_BACKLIGHT_GPIO	91
+ #define LCD_PANEL_ENABLE_GPIO		154
+ #define LCD_PIXCLOCK_MAX		5400 /* freq 5.4 MHz */
+-#define PM_RECEIVER             TWL4030_MODULE_PM_RECIEVER
++#define PM_RECEIVER             TWL4030_MODULE_PM_RECEIVER
+ #define ENABLE_VAUX2_DEDICATED  0x09
+ #define ENABLE_VAUX2_DEV_GRP    0x20
+ 
diff --git a/recipes/linux/linux-omap-2.6.28/omap1710h3/defconfig b/recipes/linux/linux-omap-2.6.28/omap1710h3/defconfig
new file mode 100644
index 0000000000..21f7c54e4e
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap1710h3/defconfig
@@ -0,0 +1,1224 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23-rc2-omap1
+# Tue Aug 21 23:10:57 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+CONFIG_ARCH_OMAP1=y
+# CONFIG_ARCH_OMAP2 is not set
+# CONFIG_ARCH_OMAP3 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_RESET_CLOCKS is not set
+# CONFIG_OMAP_BOOT_TAG is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_MPU_TIMER=y
+# CONFIG_OMAP_32K_TIMER is not set
+# CONFIG_OMAP_DM_TIMER is not set
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_OMAP_DSP is not set
+
+#
+# OMAP Core Type
+#
+# CONFIG_ARCH_OMAP730 is not set
+# CONFIG_ARCH_OMAP15XX is not set
+CONFIG_ARCH_OMAP16XX=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_INNOVATOR is not set
+# CONFIG_MACH_OMAP_H2 is not set
+CONFIG_MACH_OMAP_H3=y
+# CONFIG_MACH_OMAP_OSK is not set
+# CONFIG_MACH_NOKIA770 is not set
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP CPU Speed
+#
+# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
+# CONFIG_OMAP_ARM_216MHZ is not set
+# CONFIG_OMAP_ARM_192MHZ is not set
+CONFIG_OMAP_ARM_168MHZ=y
+# CONFIG_OMAP_ARM_120MHZ is not set
+# CONFIG_OMAP_ARM_60MHZ is not set
+# CONFIG_OMAP_ARM_30MHZ is not set
+# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x10C08000
+CONFIG_ZBOOT_ROM_BSS=0x10200000
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 initrd=0x10A00000,8M root=/dev/ram0 rw ip=dhcp devfs=mount"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_IRDA=y
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+
+#
+# Old SIR device drivers
+#
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Old Serial dongle support
+#
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_MCS_FIR is not set
+# CONFIG_OMAP_IR is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=y
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_OMAP=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_OMAP_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_OMAP=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+CONFIG_ISP1301_OMAP=m
+CONFIG_TPS65010=y
+# CONFIG_SENSORS_TLV320AIC23 is not set
+CONFIG_GPIOEXPANDER_OMAP=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_OMAP_UWIRE=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC2101 is not set
+# CONFIG_SPI_TSC2102 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_NEW_LEDS is not set
+
+#
+# Multimedia devices
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_TUNER_3036 is not set
+# CONFIG_TUNER_TEA5761 is not set
+# CONFIG_VIDEO_OMAP_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_VIDEO_OVCAMCHIP is not set
+# CONFIG_USB_W9968CF is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_RADIO_TEA5761 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_FB_OMAP_DMA_TUNE is not set
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+# CONFIG_SND is not set
+
+#
+# Open Sound System
+#
+CONFIG_SOUND_PRIME=y
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_OMAP=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_OMAP=y
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-omap-2.6.28/omap2420h4/defconfig b/recipes/linux/linux-omap-2.6.28/omap2420h4/defconfig
new file mode 100644
index 0000000000..c1133eef9a
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap2420h4/defconfig
@@ -0,0 +1,1119 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23-rc2-omap1
+# Tue Aug 21 22:58:34 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2=y
+# CONFIG_ARCH_OMAP3 is not set
+
+#
+# OMAP Feature Selections
+#
+CONFIG_OMAP_DEBUG_DEVICES=y
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+# CONFIG_OMAP_BOOT_REASON is not set
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_MPU_TIMER=y
+# CONFIG_OMAP_32K_TIMER is not set
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_OMAP_DSP is not set
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP Core Type
+#
+CONFIG_ARCH_OMAP24XX=y
+CONFIG_ARCH_OMAP2420=y
+# CONFIG_ARCH_OMAP2430 is not set
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_NOKIA_N800 is not set
+CONFIG_MACH_OMAP_H4=y
+# CONFIG_MACH_OMAP_H4_TUSB is not set
+# CONFIG_MACH_OMAP_H4_OTG is not set
+# CONFIG_MACH_OMAP2_H4_USB1 is not set
+# CONFIG_MACH_OMAP_APOLLON is not set
+# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
+# CONFIG_MACH_OMAP_2430SDP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_IRDA=y
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=y
+CONFIG_IRCOMM=y
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+
+#
+# Old SIR device drivers
+#
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Old Serial dongle support
+#
+
+#
+# FIR device drivers
+#
+CONFIG_OMAP_IR=y
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_OMAP=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_OMAP=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_TLV320AIC23 is not set
+CONFIG_GPIOEXPANDER_OMAP=y
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+CONFIG_MENELAUS=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_NEW_LEDS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_OMAP=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-omap-2.6.28/omap2430sdp/defconfig b/recipes/linux/linux-omap-2.6.28/omap2430sdp/defconfig
new file mode 100644
index 0000000000..f3897e48a3
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap2430sdp/defconfig
@@ -0,0 +1,1303 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23-rc2-omap1
+# Sun Aug 12 17:38:46 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2=y
+# CONFIG_ARCH_OMAP3 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+# CONFIG_OMAP_BOOT_REASON is not set
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+# CONFIG_OMAP_MUX_WARNINGS is not set
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_MPU_TIMER=y
+# CONFIG_OMAP_32K_TIMER is not set
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_OMAP_DSP is not set
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP Core Type
+#
+CONFIG_ARCH_OMAP24XX=y
+# CONFIG_ARCH_OMAP2420 is not set
+CONFIG_ARCH_OMAP2430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_NOKIA_N800 is not set
+# CONFIG_MACH_OMAP_H4 is not set
+# CONFIG_MACH_OMAP_APOLLON is not set
+# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
+CONFIG_MACH_OMAP_2430SDP=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_OMAP is not set
+CONFIG_KEYBOARD_TWL4030=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_TSC2102 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_OMAP=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_TLV320AIC23 is not set
+# CONFIG_GPIOEXPANDER_OMAP is not set
+# CONFIG_MENELAUS is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_GPIO=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_OMAP24XX is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC2101 is not set
+# CONFIG_SPI_TSC2102 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_NEW_LEDS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_PERSIST is not set
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 243x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_USB_INVENTRA_FIFO is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+CONFIG_USB_INVENTRA_HCD_LOGGING=1
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ZERO_HNPTEST is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_OMAP=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-omap-2.6.28/omap3-pandora/defconfig b/recipes/linux/linux-omap-2.6.28/omap3-pandora/defconfig
new file mode 100644
index 0000000000..5db83f08da
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap3-pandora/defconfig
@@ -0,0 +1,2186 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc7-omap1
+# Fri Dec 12 19:50:40 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_DEBUG=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+CONFIG_OMAP2_DSS_VENC=y
+# CONFIG_OMAP2_DSS_SDI is not set
+CONFIG_OMAP2_DSS_DSI=y
+# CONFIG_OMAP2_DSS_USE_DSI_PLL is not set
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OVERO is not set
+CONFIG_MACH_OMAP3_PANDORA=y
+CONFIG_OMAP_TICK_GPTIMER=12
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+CONFIG_ARM_ERRATUM_451034=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=y
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=y
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+CONFIG_IEEE80211_CRYPT_CCMP=y
+CONFIG_IEEE80211_CRYPT_TKIP=y
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_93CX6=m
+# CONFIG_ICS932S401 is not set
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+CONFIG_REALTEK_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_TWL4030=y
+# CONFIG_KEYBOARD_LM8323 is not set
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_USB=y
+CONFIG_TWL4030_PWRBUTTON=y
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_LP5521 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX2341X=m
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+# CONFIG_VIDEO_EM28XX is not set
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_USBVIDEO=m
+CONFIG_USB_VICAM=m
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_KONICAWC=m
+CONFIG_USB_QUICKCAM_MESSENGER=m
+# CONFIG_USB_ET61X251 is not set
+CONFIG_VIDEO_OVCAMCHIP=m
+CONFIG_USB_W9968CF=m
+CONFIG_USB_OV511=m
+CONFIG_USB_SE401=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_STV680=m
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_ZR364XX=m
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+# CONFIG_DVB_USB_DW2102 is not set
+# CONFIG_DVB_USB_CINERGY_T2 is not set
+# CONFIG_DVB_USB_ANYSEE is not set
+# CONFIG_DVB_USB_DTV5100 is not set
+# CONFIG_DVB_USB_AF9015 is not set
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+# CONFIG_DVB_SIANO_SMS1XXX is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_SI21XX is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+# CONFIG_DVB_DRX397XD is not set
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+# CONFIG_DVB_LGS8GL5 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# CONFIG_DVB_AF9013 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=14
+CONFIG_FB_OMAP2=y
+# CONFIG_FB_OMAP2_DEBUG is not set
+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
+CONFIG_FB_OMAP2_NUM_FBS=3
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_DVI=y
+# CONFIG_PANEL_DVI_640X480 is not set
+# CONFIG_PANEL_DVI_800X600 is not set
+CONFIG_PANEL_DVI_1024X768=y
+# CONFIG_PANEL_DVI_1280X1024 is not set
+CONFIG_PANEL_SHARP_LS037V7DW01=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+CONFIG_LCD_ILI9320=y
+# CONFIG_LCD_TDO24M is not set
+CONFIG_LCD_VGG2432A4=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+# CONFIG_USB_BERRY_CHARGE is not set
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SPI=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+# CONFIG_LEDS_OMAP is not set
+# CONFIG_LEDS_OMAP_PWM is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACER_MAX_TRACE=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+CONFIG_PREEMPT_TRACER=y
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-omap-2.6.28/omap3evm/defconfig b/recipes/linux/linux-omap-2.6.28/omap3evm/defconfig
new file mode 100644
index 0000000000..da5a8c4b90
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap3evm/defconfig
@@ -0,0 +1,2197 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-omap1
+# Thu Jan  8 16:06:45 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+CONFIG_OMAP2_DSS_VENC=y
+# CONFIG_OMAP2_DSS_SDI is not set
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_USE_DSI_PLL=y
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+CONFIG_MACH_OMAP3EVM=y
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+CONFIG_OMAP_TICK_GPTIMER=12
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+CONFIG_ARM_ERRATUM_451034=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=y
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=y
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+CONFIG_IEEE80211_CRYPT_CCMP=y
+CONFIG_IEEE80211_CRYPT_TKIP=y
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_93CX6=m
+# CONFIG_ICS932S401 is not set
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+CONFIG_REALTEK_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_TWL4030=y
+# CONFIG_KEYBOARD_LM8323 is not set
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_PWRBUTTON=y
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_LP5521 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX2341X=m
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+# CONFIG_VIDEO_EM28XX is not set
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_USBVIDEO=m
+CONFIG_USB_VICAM=m
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_KONICAWC=m
+CONFIG_USB_QUICKCAM_MESSENGER=m
+# CONFIG_USB_ET61X251 is not set
+CONFIG_VIDEO_OVCAMCHIP=m
+CONFIG_USB_W9968CF=m
+CONFIG_USB_OV511=m
+CONFIG_USB_SE401=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_STV680=m
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_ZR364XX=m
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+# CONFIG_DVB_USB_DW2102 is not set
+# CONFIG_DVB_USB_CINERGY_T2 is not set
+# CONFIG_DVB_USB_ANYSEE is not set
+# CONFIG_DVB_USB_DTV5100 is not set
+# CONFIG_DVB_USB_AF9015 is not set
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+# CONFIG_DVB_SIANO_SMS1XXX is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_SI21XX is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+# CONFIG_DVB_DRX397XD is not set
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+# CONFIG_DVB_LGS8GL5 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# CONFIG_DVB_AF9013 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=14
+CONFIG_FB_OMAP2=y
+CONFIG_FB_OMAP2_DEBUG=y
+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
+CONFIG_FB_OMAP2_NUM_FBS=3
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_GENERIC=y
+CONFIG_PANEL_SHARP_LS037V7DW01=y
+# CONFIG_PANEL_N800 is not set
+# CONFIG_CTRL_BLIZZARD is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+CONFIG_LCD_ILI9320=y
+# CONFIG_LCD_TDO24M is not set
+CONFIG_LCD_VGG2432A4=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_OMAP3EVM=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TWL4030=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+# CONFIG_USB_BERRY_CHARGE is not set
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_GPIO_VBUS=y
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SPI=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+# CONFIG_LEDS_OMAP is not set
+# CONFIG_LEDS_OMAP_PWM is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACER_MAX_TRACE=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+CONFIG_PREEMPT_TRACER=y
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-omap-2.6.28/omap3evm/omap3evm-dss2.diff b/recipes/linux/linux-omap-2.6.28/omap3evm/omap3evm-dss2.diff
new file mode 100644
index 0000000000..60832e72ca
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap3evm/omap3evm-dss2.diff
@@ -0,0 +1,443 @@
+From: hvaibhav@ti.com
+To: linux-fbdev-devel@lists.sourceforge.net, linux-omap@vger.kernel.org
+Cc: Vaibhav Hiremath <hvaibhav@ti.com>
+Subject: [REVIEW PATCH] Added OMAP3EVM support on Tomis FBDEV/DSS Patches
+Date: 	Fri, 14 Nov 2008 12:02:32 +0530
+
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+
+Tested LCD, TV, DVI (480P) out on OMAP3EVM board.
+
+Please make sure that you change the option
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=7  and apply the
+Mans Rullgard clock patches to support set_rate and round_rate API.
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c |  224 ++++++++++++++++++++++++++++++++--
+ drivers/video/omap2/Kconfig          |    5 +
+ drivers/video/omap2/Makefile         |    1 +
+ drivers/video/omap2/panel-omap3evm.c |  110 +++++++++++++++++
+ 5 files changed, 341 insertions(+), 53 deletions(-)
+ create mode 100644 drivers/video/omap2/panel-omap3evm.c
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 42ab826..e244fa7 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -37,6 +37,8 @@
+ #include <mach/usb-ehci.h>
+ #include <mach/common.h>
+ #include <mach/mcspi.h>
++#include <mach/omapfb.h>
++#include <mach/display.h>
+
+ #include "sdram-micron-mt46h32m32lf-6.h"
+ #include "twl4030-generic-scripts.h"
+@@ -161,14 +163,215 @@ static int __init omap3_evm_i2c_init(void)
+ 	omap_register_i2c_bus(3, 400, NULL, 0);
+ 	return 0;
+ }
++static struct omap_fbmem_config evm_fbmem0_config = {
++		.size = 480*720*4,
++		.start = OMAPFB_MEMTYPE_SDRAM,
++};
+
+-static struct platform_device omap3_evm_lcd_device = {
+-	.name		= "omap3evm_lcd",
+-	.id		= -1,
++static struct omap_fbmem_config evm_fbmem1_config = {
++		.size = 480*720*4,
++		.start = OMAPFB_MEMTYPE_SDRAM,
+ };
+
+-static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
+-	.ctrl_name	= "internal",
++static struct omap_fbmem_config evm_fbmem2_config = {
++		.size = 480*720*4,
++		.start = OMAPFB_MEMTYPE_SDRAM,
++};
++#define LCD_PANEL_LR		2
++#define LCD_PANEL_UD		3
++#define LCD_PANEL_INI		152
++#define LCD_PANEL_ENABLE_GPIO	153
++#define LCD_PANEL_QVGA		154
++#define LCD_PANEL_RESB		155
++
++#define ENABLE_VDAC_DEDICATED	0x03
++#define ENABLE_VDAC_DEV_GRP	0x20
++#define ENABLE_VPLL2_DEDICATED	0x05
++#define ENABLE_VPLL2_DEV_GRP	0xE0
++
++#define TWL4030_GPIODATA_IN3	0x03
++#define TWL4030_GPIODATA_DIR3	0x06
++#define TWL4030_VPLL2_DEV_GRP	0x33
++#define TWL4030_VPLL2_DEDICATED	0x36
++
++static int lcd_enabled;
++static int dvi_enabled;
++
++static void __init evm_display_init(void)
++{
++	int r;
++	r = gpio_request(LCD_PANEL_LR, "lcd_panel_lr");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_LR\n");
++		return;
++	}
++	r = gpio_request(LCD_PANEL_UD, "lcd_panel_ud");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_UD\n");
++		goto err_1;
++	}
++
++	r = gpio_request(LCD_PANEL_INI, "lcd_panel_ini");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_INI\n");
++		goto err_2;
++	}
++	r = gpio_request(LCD_PANEL_RESB, "lcd_panel_resb");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_RESB\n");
++		goto err_3;
++	}
++	r = gpio_request(LCD_PANEL_QVGA, "lcd_panel_qvga");
++	if (r) {
++		printk(KERN_ERR "failed to get LCD_PANEL_QVGA\n");
++		goto err_4;
++	}
++
++	gpio_direction_output(LCD_PANEL_LR, 0);
++	gpio_direction_output(LCD_PANEL_UD, 0);
++	gpio_direction_output(LCD_PANEL_INI, 0);
++	gpio_direction_output(LCD_PANEL_RESB, 0);
++	gpio_direction_output(LCD_PANEL_QVGA, 0);
++
++#define TWL_LED_LEDEN           0x00
++#define TWL_PWMA_PWMAON         0x00
++#define TWL_PWMA_PWMAOFF        0x01
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
++
++	gpio_direction_output(LCD_PANEL_RESB, 1);
++	gpio_direction_output(LCD_PANEL_INI, 1);
++	gpio_direction_output(LCD_PANEL_QVGA, 0);
++	gpio_direction_output(LCD_PANEL_LR, 1);
++	gpio_direction_output(LCD_PANEL_UD, 1);
++
++	return;
++
++err_4:
++	gpio_free(LCD_PANEL_RESB);
++err_3:
++	gpio_free(LCD_PANEL_INI);
++err_2:
++	gpio_free(LCD_PANEL_UD);
++err_1:
++	gpio_free(LCD_PANEL_LR);
++
++}
++
++static int panel_enable_lcd(struct omap_display *display)
++{
++	if (dvi_enabled) {
++		printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++		return -EINVAL;
++	}
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
++	}
++	gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
++	lcd_enabled = 1;
++	return 0;
++}
++
++static void panel_disable_lcd(struct omap_display *display)
++{
++	if (omap_rev() > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++				TWL4030_VPLL2_DEV_GRP);
++	}
++	gpio_set_value(LCD_PANEL_ENABLE_GPIO, 1);
++	lcd_enabled = 0;
++}
++
++static struct omap_display_data evm_display_data = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "lcd",
++	.panel_name = "panel-sdp3430",
++	.u.dpi.data_lines = 16,
++	.panel_enable = panel_enable_lcd,
++	.panel_disable = panel_disable_lcd,
++};
++
++static int panel_enable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEDICATED, TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++	return 0;
++}
++
++static void panel_disable_tv(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEDICATED);
++	twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++			TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_display_data evm_display_data_tv = {
++	.type = OMAP_DISPLAY_TYPE_VENC,
++	.name = "tv",
++	.u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++	.panel_enable = panel_enable_tv,
++	.panel_disable = panel_disable_tv,
++};
++
++
++static int panel_enable_dvi(struct omap_display *display)
++{
++	if (lcd_enabled) {
++		printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++		return -EINVAL;
++	}
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++			TWL4030_GPIODATA_IN3);
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++			TWL4030_GPIODATA_DIR3);
++	dvi_enabled = 1;
++
++	return 0;
++}
++
++static void panel_disable_dvi(struct omap_display *display)
++{
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++			TWL4030_GPIODATA_IN3);
++	twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++			TWL4030_GPIODATA_DIR3);
++	dvi_enabled = 0;
++}
++
++
++static struct omap_display_data evm_display_data_dvi = {
++	.type = OMAP_DISPLAY_TYPE_DPI,
++	.name = "dvi",
++	.panel_name = "panel-dvi",
++	.u.dpi.data_lines = 24,
++	.panel_enable = panel_enable_dvi,
++	.panel_disable = panel_disable_dvi,
++};
++
++static struct omap_dss_platform_data evm_dss_data = {
++	.num_displays = 3,
++	.displays = {
++		&evm_display_data,
++		&evm_display_data_dvi,
++		&evm_display_data_tv,
++	}
++};
++static struct platform_device evm_dss_device = {
++	.name		= "omap-dss",
++	.id		= -1,
++	.dev            = {
++		.platform_data = &evm_dss_data,
++	},
+ };
+
+ static void ads7846_dev_init(void)
+@@ -227,11 +430,13 @@ static void __init omap3_evm_init_irq(void)
+
+ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&omap3_evm_uart_config },
+-	{ OMAP_TAG_LCD,		&omap3_evm_lcd_config },
++	{ OMAP_TAG_FBMEM,       &evm_fbmem0_config },
++	{ OMAP_TAG_FBMEM,       &evm_fbmem1_config },
++	{ OMAP_TAG_FBMEM,       &evm_fbmem2_config },
+ };
+
+ static struct platform_device *omap3_evm_devices[] __initdata = {
+-	&omap3_evm_lcd_device,
++	&evm_dss_device,
+ 	&omap3evm_smc911x_device,
+ };
+
+@@ -250,8 +455,6 @@ static void __init omap3_evm_init(void)
+ 	omap3_evm_i2c_init();
+
+ 	platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
+-	omap_board_config = omap3_evm_config;
+-	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
+
+ 	spi_register_board_info(omap3evm_spi_board_info,
+ 				ARRAY_SIZE(omap3evm_spi_board_info));
+@@ -262,10 +465,13 @@ static void __init omap3_evm_init(void)
+ 	usb_ehci_init();
+ 	omap3evm_flash_init();
+ 	ads7846_dev_init();
++	evm_display_init();
+ }
+
+ static void __init omap3_evm_map_io(void)
+ {
++	omap_board_config = omap3_evm_config;
++	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
+ 	omap2_set_globals_343x();
+ 	omap2_map_common_io();
+ }
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index 95691ad..8211ffd 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -51,4 +51,9 @@ config PANEL_SDP3430
+         help
+           SDP3430 LCD
+
++config PANEL_OMAP3EVM
++        tristate "OMAP3EVM Panel"
++        depends on OMAP2_DSS
++        help
++          OMAP3EVM LCD Panel
+ endmenu
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index 73ab1c0..668e8c6 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -3,3 +3,4 @@ omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
+
+ obj-$(CONFIG_PANEL_DVI) += panel-dvi.o
+ obj-$(CONFIG_PANEL_SDP3430) += panel-sdp3430.o
++obj-$(CONFIG_PANEL_OMAP3EVM) += panel-omap3evm.o
+diff --git a/drivers/video/omap2/panel-omap3evm.c b/drivers/video/omap2/panel-omap3evm.c
+new file mode 100644
+index 0000000..4a00b02
+--- /dev/null
++++ b/drivers/video/omap2/panel-omap3evm.c
+@@ -0,0 +1,110 @@
++/*
++ * LCD panel support for the TI OMAP3EVM board
++ *
++ * Copyright (C) 2008 Texas Instruments, Inc.
++ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
++ *
++ * Derived from drivers/video/omap2/panel-sdp3430.c
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int omap3evm_panel_init(struct omap_display *display)
++{
++	return 0;
++}
++
++static void omap3evm_panel_cleanup(struct omap_display *display)
++{
++}
++
++static int omap3evm_panel_enable(struct omap_display *display)
++{
++	int r = 0;
++
++	if (display->hw_config.panel_enable)
++		r = display->hw_config.panel_enable(display);
++
++	return r;
++}
++
++static void omap3evm_panel_disable(struct omap_display *display)
++{
++	if (display->hw_config.panel_disable)
++		display->hw_config.panel_disable(display);
++}
++
++static int omap3evm_panel_suspend(struct omap_display *display)
++{
++	omap3evm_panel_disable(display);
++	return 0;
++}
++
++static int omap3evm_panel_resume(struct omap_display *display)
++{
++	return omap3evm_panel_enable(display);
++}
++
++static struct omap_panel omap3evm_panel = {
++	.owner		= THIS_MODULE,
++	.name		= "panel-evm",
++	.init		= omap3evm_panel_init,
++	.cleanup	= omap3evm_panel_cleanup,
++	.enable		= omap3evm_panel_enable,
++	.disable	= omap3evm_panel_disable,
++	.suspend	= omap3evm_panel_suspend,
++	.resume		= omap3evm_panel_resume,
++	/*.set_mode	= omap3evm_set_mode, */
++
++	.timings = {
++		.pixel_clock	= 26000,
++
++		.hsw		= 4,
++		.hfp		= 4,
++		.hbp		= 40,
++
++		.vsw		= 2,
++		.vfp		= 2,
++		.vbp		= 7,
++	},
++
++	.acb		= 0x28,
++
++	.config		= OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
++		OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
++
++	.x_res = 480,
++	.y_res = 640,
++	.bpp = 18,
++};
++
++
++static int __init omap3evm_panel_drv_init(void)
++{
++	omap_dss_register_panel(&omap3evm_panel);
++	return 0;
++}
++
++static void __exit omap3evm_panel_drv_exit(void)
++{
++	omap_dss_unregister_panel(&omap3evm_panel);
++}
++
++module_init(omap3evm_panel_drv_init);
++module_exit(omap3evm_panel_drv_exit);
++MODULE_LICENSE("GPL");
+--
+1.5.6
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
+
diff --git a/recipes/linux/linux-omap-2.6.28/omap3evm/omap3evm-lcd-redtint.diff b/recipes/linux/linux-omap-2.6.28/omap3evm/omap3evm-lcd-redtint.diff
new file mode 100644
index 0000000000..54ea3c9f68
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap3evm/omap3evm-lcd-redtint.diff
@@ -0,0 +1,66 @@
+Message-ID: <c656a4d20809270046u341aec27k6d896d4b42e799d4@mail.gmail.com>
+Date: 	Sat, 27 Sep 2008 03:46:18 -0400
+From: "arun c" <arun.edarath@gmail.com>
+To: "Daniel Schaeffer" <daniel.schaeffer@timesys.com>
+Subject: Re: OMAP3EVM LCD red tint
+
+Hi Daniel Schaeffer
+
+On Fri, Sep 26, 2008 at 4:20 PM, Daniel Schaeffer
+<daniel.schaeffer@timesys.com> wrote:
+> Has anyone looked into why the LCD display on the OMAP3EVM is always tinted
+> red? I created a couple of color test images that I cat'ed to /dev/fb and it
+> looks like the blue color channel is completely ignored.  I was testing on
+> v2.6.26-omap2 but is doesn't look like there have been any changes to the fb
+> driver since then so I'm assuming the issue is also present in the head of
+> the git tree.
+>
+> Regards,
+>
+> Daniel Schaeffer
+>
+
+Try the patch below(Remember that you may have to manually edit because
+this patch is against current HEAD)
+
+
+diff --git a/drivers/video/omap/lcd_omap3evm.c
+b/drivers/video/omap/lcd_omap3evm.c
+index a564ca5..821bafe 100644
+--- a/drivers/video/omap/lcd_omap3evm.c
++++ b/drivers/video/omap/lcd_omap3evm.c
+@@ -44,6 +44,8 @@
+ #define ENABLE_VDAC_DEV_GRP	0x20
+ #define ENABLE_VPLL2_DEDICATED	0x05
+ #define ENABLE_VPLL2_DEV_GRP	0xE0
++#define TWL4030_VPLL2_DEV_GRP	0x33
++#define TWL4030_VPLL2_DEDICATED	0x36
+
+ #define TWL_LED_LEDEN		0x00
+ #define TWL_PWMA_PWMAON		0x00
+@@ -86,12 +88,24 @@ static void omap3evm_panel_cleanup(struct lcd_panel *panel)
+
+ static int omap3evm_panel_enable(struct lcd_panel *panel)
+ {
++	if (omap_rev > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++			ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
++	}
+ 	omap_set_gpio_dataout(LCD_PANEL_ENABLE_GPIO, 0);
+ 	return 0;
+ }
+
+ static void omap3evm_panel_disable(struct lcd_panel *panel)
+ {
++	if (omap_rev > OMAP3430_REV_ES1_0) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++			TWL4030_VPLL2_DEDICATED);
++		twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++			TWL4030_VPLL2_DEV_GRP);
++	}
+ 	omap_set_gpio_dataout(LCD_PANEL_ENABLE_GPIO, 1);
+ }
+
+
diff --git a/recipes/linux/linux-omap-2.6.28/omap5912osk/defconfig b/recipes/linux/linux-omap-2.6.28/omap5912osk/defconfig
new file mode 100644
index 0000000000..3c334868ea
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/omap5912osk/defconfig
@@ -0,0 +1,1098 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23-rc2-omap1
+# Tue Aug 21 23:22:37 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+CONFIG_ARCH_OMAP1=y
+# CONFIG_ARCH_OMAP2 is not set
+# CONFIG_ARCH_OMAP3 is not set
+
+#
+# OMAP Feature Selections
+#
+CONFIG_OMAP_RESET_CLOCKS=y
+# CONFIG_OMAP_BOOT_TAG is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+# CONFIG_OMAP_DM_TIMER is not set
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_OMAP_DSP is not set
+
+#
+# OMAP Core Type
+#
+# CONFIG_ARCH_OMAP730 is not set
+# CONFIG_ARCH_OMAP15XX is not set
+CONFIG_ARCH_OMAP16XX=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_INNOVATOR is not set
+# CONFIG_MACH_OMAP_H2 is not set
+# CONFIG_MACH_OMAP_H3 is not set
+CONFIG_MACH_OMAP_OSK=y
+# CONFIG_OMAP_OSK_MISTRAL is not set
+# CONFIG_MACH_NOKIA770 is not set
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP CPU Speed
+#
+# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
+# CONFIG_OMAP_ARM_216MHZ is not set
+CONFIG_OMAP_ARM_192MHZ=y
+# CONFIG_OMAP_ARM_168MHZ is not set
+# CONFIG_OMAP_ARM_120MHZ is not set
+# CONFIG_OMAP_ARM_60MHZ is not set
+# CONFIG_OMAP_ARM_30MHZ is not set
+# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+CONFIG_OMAP_CF=y
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_IDE=m
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_OMAP=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_OMAP=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TPS65010=y
+# CONFIG_SENSORS_TLV320AIC23 is not set
+# CONFIG_GPIOEXPANDER_OMAP is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_NEW_LEDS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_FB_OMAP_DMA_TUNE is not set
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-omap-2.6.28/oprofile-0.9.3.armv7.diff b/recipes/linux/linux-omap-2.6.28/oprofile-0.9.3.armv7.diff
new file mode 100644
index 0000000000..1eedbb50ff
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/oprofile-0.9.3.armv7.diff
@@ -0,0 +1,599 @@
+Hi,
+
+This patch adds Oprofile support on ARMv7, using the PMNC unit.
+Tested on OMAP3430 SDP.
+
+Feedback and comments are welcome.
+
+The patch to user space components is attached for reference. It i applies 
+against version 0.9.3 of oprofile source 
+(http://prdownloads.sourceforge.net/oprofile/oprofile-0.9.3.tar.gz).
+
+Regards,
+Jean.
+
+---
+
+From: Jean Pihet <jpihet@mvista.com>
+Date: Tue, 6 May 2008 17:21:44 +0200
+Subject: [PATCH] ARM: Add ARMv7 oprofile support
+
+Add ARMv7 Oprofile support to kernel
+
+Signed-off-by: Jean Pihet <jpihet@mvista.com>
+---
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index c60a27d..60b50a0 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -161,6 +161,11 @@ config OPROFILE_MPCORE
+ config OPROFILE_ARM11_CORE
+ 	bool
+ 
++config OPROFILE_ARMV7
++	def_bool y
++	depends on CPU_V7 && !SMP
++	bool
++
+ endif
+ 
+ config VECTORS_BASE
+diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile
+index e61d0cc..88e31f5 100644
+--- a/arch/arm/oprofile/Makefile
++++ b/arch/arm/oprofile/Makefile
+@@ -11,3 +11,4 @@ oprofile-$(CONFIG_CPU_XSCALE)		+= op_model_xscale.o
+ oprofile-$(CONFIG_OPROFILE_ARM11_CORE)	+= op_model_arm11_core.o
+ oprofile-$(CONFIG_OPROFILE_ARMV6)	+= op_model_v6.o
+ oprofile-$(CONFIG_OPROFILE_MPCORE)	+= op_model_mpcore.o
++oprofile-$(CONFIG_OPROFILE_ARMV7)	+= op_model_v7.o
+diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
+index 0a5cf3a..3fcd752 100644
+--- a/arch/arm/oprofile/common.c
++++ b/arch/arm/oprofile/common.c
+@@ -145,6 +145,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) 
+ 	spec = &op_mpcore_spec;
+ #endif
+ 
++#ifdef CONFIG_OPROFILE_ARMV7
++	spec = &op_armv7_spec;
++#endif
++
+ 	if (spec) {
+ 		ret = spec->init();
+ 		if (ret < 0)
+diff --git a/arch/arm/oprofile/op_arm_model.h 
+b/arch/arm/oprofile/op_arm_model.h
+index 4899c62..8c4e4f6 100644
+--- a/arch/arm/oprofile/op_arm_model.h
++++ b/arch/arm/oprofile/op_arm_model.h
+@@ -26,6 +26,7 @@ extern struct op_arm_model_spec op_xscale_spec;
+ 
+ extern struct op_arm_model_spec op_armv6_spec;
+ extern struct op_arm_model_spec op_mpcore_spec;
++extern struct op_arm_model_spec op_armv7_spec;
+ 
+ extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth);
+ 
+diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c
+new file mode 100644
+index 0000000..a159bc1
+--- /dev/null
++++ b/arch/arm/oprofile/op_model_v7.c
+@@ -0,0 +1,407 @@
++/**
++ * @file op_model_v7.c
++ * ARM V7 (Cortex A8) Event Monitor Driver
++ *
++ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com>
++ * @remark Copyright 2004 ARM SMP Development Team
++ */
++#include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/oprofile.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/smp.h>
++
++#include "op_counter.h"
++#include "op_arm_model.h"
++#include "op_model_v7.h"
++
++/* #define DEBUG */
++
++
++/*
++ * ARM V7 PMNC support
++ */
++
++static u32 cnt_en[CNTMAX];
++
++static inline void armv7_pmnc_write(u32 val)
++{
++	val &= PMNC_MASK;
++	asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
++}
++
++static inline u32 armv7_pmnc_read(void)
++{
++	u32 val;
++
++	asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
++	return val;
++}
++
++static inline u32 armv7_pmnc_enable_counter(unsigned int cnt)
++{
++	u32 val;
++
++	if (cnt >= CNTMAX) {
++		printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
++			" %d\n", smp_processor_id(), cnt);
++		return -1;
++	}
++
++	if (cnt == CCNT)
++		val = CNTENS_C;
++	else
++		val = (1 << (cnt - CNT0));
++
++	val &= CNTENS_MASK;
++	asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
++
++	return cnt;
++}
++
++static inline u32 armv7_pmnc_disable_counter(unsigned int cnt)
++{
++	u32 val;
++
++	if (cnt >= CNTMAX) {
++		printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter"
++			" %d\n", smp_processor_id(), cnt);
++		return -1;
++	}
++
++	if (cnt == CCNT)
++		val = CNTENC_C;
++	else
++		val = (1 << (cnt - CNT0));
++
++	val &= CNTENC_MASK;
++	asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
++
++	return cnt;
++}
++
++static inline u32 armv7_pmnc_enable_intens(unsigned int cnt)
++{
++	u32 val;
++
++	if (cnt >= CNTMAX) {
++		printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
++			" interrupt enable %d\n", smp_processor_id(), cnt);
++		return -1;
++	}
++
++	if (cnt == CCNT)
++		val = INTENS_C;
++	else
++		val = (1 << (cnt - CNT0));
++
++	val &= INTENS_MASK;
++	asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
++
++	return cnt;
++}
++
++static inline u32 armv7_pmnc_getreset_flags(void)
++{
++	u32 val;
++
++	/* Read */
++	asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
++
++	/* Write to clear flags */
++	val &= FLAG_MASK;
++	asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
++
++	return val;
++}
++
++static inline int armv7_pmnc_select_counter(unsigned int cnt)
++{
++	u32 val;
++
++	if ((cnt == CCNT) || (cnt >= CNTMAX)) {
++		printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri"
++			" %d\n", smp_processor_id(), cnt);
++		return -1;
++	}
++
++	val = (cnt - CNT0) & SELECT_MASK;
++	asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
++
++	return cnt;
++}
++
++static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val)
++{
++	if (armv7_pmnc_select_counter(cnt) == cnt) {
++		val &= EVTSEL_MASK;
++		asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
++	}
++}
++
++static void armv7_pmnc_reset_counter(unsigned int cnt)
++{
++	u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
++	u32 val = -(u32)counter_config[cpu_cnt].count;
++
++	switch (cnt) {
++	case CCNT:
++		armv7_pmnc_disable_counter(cnt);
++
++		asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
++
++		if (cnt_en[cnt] != 0)
++		    armv7_pmnc_enable_counter(cnt);
++
++		break;
++
++	case CNT0:
++	case CNT1:
++	case CNT2:
++	case CNT3:
++		armv7_pmnc_disable_counter(cnt);
++
++		if (armv7_pmnc_select_counter(cnt) == cnt)
++		    asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val));
++
++		if (cnt_en[cnt] != 0)
++		    armv7_pmnc_enable_counter(cnt);
++
++		break;
++
++	default:
++		printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter"
++			" %d\n", smp_processor_id(), cnt);
++		break;
++	}
++}
++
++int armv7_setup_pmnc(void)
++{
++	unsigned int cnt;
++
++	if (armv7_pmnc_read() & PMNC_E) {
++		printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup"
++			" new event counter.\n", smp_processor_id());
++		return -EBUSY;
++	}
++
++	/*
++	 * Initialize & Reset PMNC: C bit, D bit and P bit.
++	 *  Note: Using a slower count for CCNT (D bit: divide by 64) results
++	 *   in a more stable system
++	 */
++	armv7_pmnc_write(PMNC_P | PMNC_C | PMNC_D);
++
++
++	for (cnt = CCNT; cnt < CNTMAX; cnt++) {
++		unsigned long event;
++		u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
++
++		/*
++		 * Disable counter
++		 */
++		armv7_pmnc_disable_counter(cnt);
++		cnt_en[cnt] = 0;
++
++		if (!counter_config[cpu_cnt].enabled)
++			continue;
++
++		event = counter_config[cpu_cnt].event & 255;
++
++		/*
++		 * Set event (if destined for PMNx counters)
++		 * We don't need to set the event if it's a cycle count
++		 */
++		if (cnt != CCNT)
++			armv7_pmnc_write_evtsel(cnt, event);
++
++		/*
++		 * Enable interrupt for this counter
++		 */
++		armv7_pmnc_enable_intens(cnt);
++
++		/*
++		 * Reset counter
++		 */
++		armv7_pmnc_reset_counter(cnt);
++
++		/*
++		 * Enable counter
++		 */
++		armv7_pmnc_enable_counter(cnt);
++		cnt_en[cnt] = 1;
++	}
++
++	return 0;
++}
++
++static inline void armv7_start_pmnc(void)
++{
++	armv7_pmnc_write(armv7_pmnc_read() | PMNC_E);
++}
++
++static inline void armv7_stop_pmnc(void)
++{
++	armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E);
++}
++
++/*
++ * CPU counters' IRQ handler (one IRQ per CPU)
++ */
++static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg)
++{
++	struct pt_regs *regs = get_irq_regs();
++	unsigned int cnt;
++	u32 flags;
++
++
++	/*
++	 * Stop IRQ generation
++	 */
++	armv7_stop_pmnc();
++
++	/*
++	 * Get and reset overflow status flags
++	 */
++	flags = armv7_pmnc_getreset_flags();
++
++	/*
++	 * Cycle counter
++	 */
++	if (flags & FLAG_C) {
++		u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT);
++		armv7_pmnc_reset_counter(CCNT);
++		oprofile_add_sample(regs, cpu_cnt);
++	}
++
++	/*
++	 * PMNC counters 0:3
++	 */
++	for (cnt = CNT0; cnt < CNTMAX; cnt++) {
++		if (flags & (1 << (cnt - CNT0))) {
++			u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
++			armv7_pmnc_reset_counter(cnt);
++			oprofile_add_sample(regs, cpu_cnt);
++		}
++	}
++
++	/*
++	 * Allow IRQ generation
++	 */
++	armv7_start_pmnc();
++
++	return IRQ_HANDLED;
++}
++
++int armv7_request_interrupts(int *irqs, int nr)
++{
++	unsigned int i;
++	int ret = 0;
++
++	for (i = 0; i < nr; i++) {
++		ret = request_irq(irqs[i], armv7_pmnc_interrupt,
++				IRQF_DISABLED, "CP15 PMNC", NULL);
++		if (ret != 0) {
++			printk(KERN_ERR "oprofile: unable to request IRQ%u"
++				" for ARMv7\n",
++			       irqs[i]);
++			break;
++		}
++	}
++
++	if (i != nr)
++		while (i-- != 0)
++			free_irq(irqs[i], NULL);
++
++	return ret;
++}
++
++void armv7_release_interrupts(int *irqs, int nr)
++{
++	unsigned int i;
++
++	for (i = 0; i < nr; i++)
++		free_irq(irqs[i], NULL);
++}
++
++#ifdef DEBUG
++static void armv7_pmnc_dump_regs(void)
++{
++	u32 val;
++	unsigned int cnt;
++
++	printk(KERN_INFO "PMNC registers dump:\n");
++
++	asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
++	printk(KERN_INFO "PMNC  =0x%08x\n", val);
++
++	asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
++	printk(KERN_INFO "CNTENS=0x%08x\n", val);
++
++	asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
++	printk(KERN_INFO "INTENS=0x%08x\n", val);
++
++	asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
++	printk(KERN_INFO "FLAGS =0x%08x\n", val);
++
++	asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
++	printk(KERN_INFO "SELECT=0x%08x\n", val);
++
++	asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
++	printk(KERN_INFO "CCNT  =0x%08x\n", val);
++
++	for (cnt = CNT0; cnt < CNTMAX; cnt++) {
++		armv7_pmnc_select_counter(cnt);
++		asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
++		printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val);
++		asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
++		printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val);
++	}
++}
++#endif
++
++
++static int irqs[] = {
++#ifdef CONFIG_ARCH_OMAP3
++	INT_34XX_BENCH_MPU_EMUL,
++#endif
++};
++
++static void armv7_pmnc_stop(void)
++{
++#ifdef DEBUG
++	armv7_pmnc_dump_regs();
++#endif
++	armv7_stop_pmnc();
++	armv7_release_interrupts(irqs, ARRAY_SIZE(irqs));
++}
++
++static int armv7_pmnc_start(void)
++{
++	int ret;
++
++#ifdef DEBUG
++	armv7_pmnc_dump_regs();
++#endif
++	ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs));
++	if (ret >= 0)
++		armv7_start_pmnc();
++
++	return ret;
++}
++
++static int armv7_detect_pmnc(void)
++{
++	return 0;
++}
++
++struct op_arm_model_spec op_armv7_spec = {
++	.init		= armv7_detect_pmnc,
++	.num_counters	= 5,
++	.setup_ctrs	= armv7_setup_pmnc,
++	.start		= armv7_pmnc_start,
++	.stop		= armv7_pmnc_stop,
++	.name		= "arm/armv7",
++};
+diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h
+new file mode 100644
+index 0000000..08f40ea
+--- /dev/null
++++ b/arch/arm/oprofile/op_model_v7.h
+@@ -0,0 +1,101 @@
++/**
++ * @file op_model_v7.h
++ * ARM v7 (Cortex A8) Event Monitor Driver
++ *
++ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com>
++ * @remark Copyright 2004 ARM SMP Development Team
++ * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
++ * @remark Copyright 2000-2004 MontaVista Software Inc
++ * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
++ * @remark Copyright 2004 Intel Corporation
++ * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
++ * @remark Copyright 2004 Oprofile Authors
++ *
++ * @remark Read the file COPYING
++ *
++ * @author Zwane Mwaikambo
++ */
++#ifndef OP_MODEL_V7_H
++#define OP_MODEL_V7_H
++
++/*
++ * Per-CPU PMNC: config reg
++ */
++#define PMNC_E		(1 << 0)	/* Enable all counters */
++#define PMNC_P		(1 << 1)	/* Reset all counters */
++#define PMNC_C		(1 << 2)	/* Cycle counter reset */
++#define PMNC_D		(1 << 3)	/* CCNT counts every 64th cpu cycle */
++#define PMNC_X		(1 << 4)	/* Export to ETM */
++#define PMNC_DP		(1 << 5)	/* Disable CCNT if non-invasive debug*/
++#define	PMNC_MASK	0x3f		/* Mask for writable bits */
++
++/*
++ * Available counters
++ */
++#define CCNT 		0
++#define CNT0 		1
++#define CNT1 		2
++#define CNT2 		3
++#define CNT3 		4
++#define CNTMAX 		5
++
++#define CPU_COUNTER(cpu, counter)	((cpu) * CNTMAX + (counter))
++
++/*
++ * CNTENS: counters enable reg
++ */
++#define CNTENS_P0	(1 << 0)
++#define CNTENS_P1	(1 << 1)
++#define CNTENS_P2	(1 << 2)
++#define CNTENS_P3	(1 << 3)
++#define CNTENS_C	(1 << 31)
++#define	CNTENS_MASK	0x8000000f	/* Mask for writable bits */
++
++/*
++ * CNTENC: counters disable reg
++ */
++#define CNTENC_P0	(1 << 0)
++#define CNTENC_P1	(1 << 1)
++#define CNTENC_P2	(1 << 2)
++#define CNTENC_P3	(1 << 3)
++#define CNTENC_C	(1 << 31)
++#define	CNTENC_MASK	0x8000000f	/* Mask for writable bits */
++
++/*
++ * INTENS: counters overflow interrupt enable reg
++ */
++#define INTENS_P0	(1 << 0)
++#define INTENS_P1	(1 << 1)
++#define INTENS_P2	(1 << 2)
++#define INTENS_P3	(1 << 3)
++#define INTENS_C	(1 << 31)
++#define	INTENS_MASK	0x8000000f	/* Mask for writable bits */
++
++/*
++ * EVTSEL: Event selection reg
++ */
++#define	EVTSEL_MASK	0x7f		/* Mask for writable bits */
++
++/*
++ * SELECT: Counter selection reg
++ */
++#define	SELECT_MASK	0x1f		/* Mask for writable bits */
++
++/*
++ * FLAG: counters overflow flag status reg
++ */
++#define FLAG_P0		(1 << 0)
++#define FLAG_P1		(1 << 1)
++#define FLAG_P2		(1 << 2)
++#define FLAG_P3		(1 << 3)
++#define FLAG_C		(1 << 31)
++#define	FLAG_MASK	0x8000000f	/* Mask for writable bits */
++
++
++int armv7_setup_pmu(void);
++int armv7_start_pmu(void);
++int armv7_stop_pmu(void);
++int armv7_request_interrupts(int *, int);
++void armv7_release_interrupts(int *, int);
++
++#endif
+
diff --git a/recipes/linux/linux-omap-2.6.28/overo/defconfig b/recipes/linux/linux-omap-2.6.28/overo/defconfig
new file mode 100644
index 0000000000..d462085be7
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/overo/defconfig
@@ -0,0 +1,2175 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-omap1
+# Mon Mar  2 14:56:32 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_TICK_GPTIMER=1
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+CONFIG_OMAP2_DSS_RFBI=y
+CONFIG_OMAP2_DSS_VENC=y
+CONFIG_OMAP2_DSS_SDI=y
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_USE_DSI_PLL=y
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+CONFIG_MACH_OVERO=y
+# CONFIG_MACH_OMAP3_PANDORA is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+# CONFIG_ARM_ERRATUM_451034 is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_NF_CONNTRACK_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_IDLETIMER=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_NF_CONNTRACK_IPV6 is not set
+# CONFIG_IP6_NF_QUEUE is not set
+CONFIG_IP6_NF_IPTABLES=m
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_EUI64 is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_TARGET_LOG is not set
+# CONFIG_IP6_NF_FILTER is not set
+# CONFIG_IP6_NF_MANGLE is not set
+# CONFIG_IP6_NF_RAW is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+# CONFIG_BT_HCIUART_LL is not set
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+CONFIG_IEEE80211_CRYPT_CCMP=y
+CONFIG_IEEE80211_CRYPT_TKIP=y
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_EEPROM_93CX6=y
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_MII=y
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+# CONFIG_HOSTAP_FIRMWARE_NVRAM is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_PWRBUTTON=y
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_LP5521 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_POWER is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+# CONFIG_DVB_USB is not set
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+# CONFIG_DVB_SIANO_SMS1XXX is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_SI21XX is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+# CONFIG_DVB_DRX397XD is not set
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_S5H1409=m
+# CONFIG_DVB_AU8522 is not set
+# CONFIG_DVB_S5H1411 is not set
+
+#
+# Digital terrestrial only tuners/PLL
+#
+# CONFIG_DVB_PLL is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+# CONFIG_DVB_LGS8GL5 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# CONFIG_DVB_AF9013 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=8
+CONFIG_FB_OMAP2=y
+CONFIG_FB_OMAP2_DEBUG=y
+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
+CONFIG_FB_OMAP2_NUM_FBS=3
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_GENERIC=y
+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_PANEL_N800 is not set
+# CONFIG_CTRL_BLIZZARD is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_SEQUENCER_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_OVERO=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TWL4030=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_OMAP_EHCI_PHY_MODE=y
+# CONFIG_OMAP_EHCI_TLL_MODE is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+CONFIG_MUSB_PIO_ONLY=y
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=y
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+# CONFIG_USB_BERRY_CHARGE is not set
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SISUSBVGA_CON=y
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+CONFIG_USB_GADGET_OMAP=y
+CONFIG_USB_OMAP=m
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_OMAP_DEBUG is not set
+# CONFIG_LEDS_OMAP is not set
+# CONFIG_LEDS_OMAP_PWM is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=m
+# CONFIG_EXT4DEV_COMPAT is not set
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=m
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=m
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-omap-2.6.28/overo/overo-ehci.patch b/recipes/linux/linux-omap-2.6.28/overo/overo-ehci.patch
new file mode 100644
index 0000000000..ff81d98095
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/overo/overo-ehci.patch
@@ -0,0 +1,113 @@
+diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
+index 489439d..2c6305b 100644
+--- a/arch/arm/mach-omap2/usb-ehci.c
++++ b/arch/arm/mach-omap2/usb-ehci.c
+@@ -152,9 +152,7 @@ static void setup_ehci_io_mux(void)
+ void __init usb_ehci_init(void)
+ {
+ #if     defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
+-	/* Setup Pin IO MUX for EHCI */
+-	if (cpu_is_omap34xx())
+-		setup_ehci_io_mux();
++	/* TODO: Setup Pin IO MUX for EHCI - moved this temporarily to U-boot */
+ 
+ 	if (platform_device_register(&ehci_device) < 0) {
+ 		printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
+
+diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
+index 1b3266c..8472996 100644
+--- a/drivers/usb/host/ehci-omap.c
++++ b/drivers/usb/host/ehci-omap.c
+@@ -48,16 +48,26 @@
+  *		to get the PHY state machine in working state
+  */
+ #define EXTERNAL_PHY_RESET
++#ifdef CONFIG_MACH_OVERO
++#define	EXT_PHY_RESET_GPIO_PORT2	(183)
++#else
+ #define	EXT_PHY_RESET_GPIO_PORT1	(57)
+ #define	EXT_PHY_RESET_GPIO_PORT2	(61)
++#endif
+ #define	EXT_PHY_RESET_DELAY		(10)
+ 
++#define PHY_STP_PULLUP_ENABLE           (0x10)
++#define PHY_STP_PULLUP_DISABLE          (0x90)
++
++
+ /* ISSUE2:
+  * USBHOST supports External charge pump PHYs only
+  * Use the VBUS from Port1 to power VBUS of Port2 externally
+  * So use Port2 as the working ULPI port
+  */
++#ifndef CONFIG_MACH_OVERO
+ #define VBUS_INTERNAL_CHARGEPUMP_HACK
++#endif
+ 
+ #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
+ 
+@@ -225,14 +235,43 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 
+ #ifdef EXTERNAL_PHY_RESET
+ 	/* Refer: ISSUE1 */
++#ifndef CONFIG_MACH_OVERO
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT1, "USB1 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT1, 0);
++#endif
+ 	gpio_request(EXT_PHY_RESET_GPIO_PORT2, "USB2 PHY reset");
+ 	gpio_direction_output(EXT_PHY_RESET_GPIO_PORT2, 0);
++	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 0);
+ 	/* Hold the PHY in RESET for enough time till DIR is high */
+ 	udelay(EXT_PHY_RESET_DELAY);
+ #endif
+ 
++        /*
++         * The PHY register 0x7 - Interface Control register is
++         * configured to disable the integrated STP pull-up resistor
++         * used for interface protection.
++	 *
++	 * May not need to be here.
++         */
++        omap_writel((0x7 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* interface reg */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (PHY_STP_PULLUP_DISABLE),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
++        /* Force PHY to HS */
++        omap_writel((0x4 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* function ctrl */
++                (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
++                (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++                (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++                (0x40),
++                EHCI_INSNREG05_ULPI);
++
++        while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
+ 	/* Configure TLL for 60Mhz clk for ULPI */
+ 	ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
+ 	if (IS_ERR(ehci_clocks->usbtll_fck_clk))
+@@ -307,7 +346,9 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 	 * Hold the PHY in RESET for enough time till PHY is settled and ready
+ 	 */
+ 	udelay(EXT_PHY_RESET_DELAY);
++#ifndef CONFIG_MACH_OVERO
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT1, 1);
++#endif
+ 	gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 1);
+ #endif
+ 
+@@ -393,7 +434,9 @@ static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ 
+ 
+ #ifdef EXTERNAL_PHY_RESET
++#ifndef CONFIG_MACH_OVERO
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT1);
++#endif
+ 	gpio_free(EXT_PHY_RESET_GPIO_PORT2);
+ #endif
+
+--
+1.6.0.4.790.gaa14a 
diff --git a/recipes/linux/linux-omap-2.6.28/read_die_ids.patch b/recipes/linux/linux-omap-2.6.28/read_die_ids.patch
new file mode 100644
index 0000000000..3f6c930cc1
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/read_die_ids.patch
@@ -0,0 +1,23 @@
+OMAP2/3 TAP: enable debug messages
+
+From: Paul Walmsley <paul@pwsan.com>
+
+This patch causes the OMAP2/3 chip ID code to display the full DIE_ID registers at boot.
+
+---
+
+ arch/arm/mach-omap2/id.c |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
+index c7f9ab7..a154b5e 100644
+--- a/arch/arm/mach-omap2/id.c
++++ b/arch/arm/mach-omap2/id.c
+@@ -10,6 +10,7 @@
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
++#define DEBUG
+ 
+ #include <linux/module.h>
+ #include <linux/kernel.h>
diff --git a/recipes/linux/linux-omap-2.6.28/strongly-ordered-memory.diff b/recipes/linux/linux-omap-2.6.28/strongly-ordered-memory.diff
new file mode 100644
index 0000000000..b60e4f4a6b
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/strongly-ordered-memory.diff
@@ -0,0 +1,18 @@
+--- /tmp/irq.c	2008-09-16 10:43:30.000000000 +0200
++++ git/arch/arm/mach-omap2/irq.c	2008-09-16 10:46:18.463198000 +0200
+@@ -64,6 +64,7 @@
+ static void omap_ack_irq(unsigned int irq)
+ {
+ 	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
++	intc_bank_read_reg(&irq_banks[0],INTC_REVISION);
+ }
+ 
+ static void omap_mask_irq(unsigned int irq)
+@@ -73,6 +74,7 @@
+ 	irq &= (IRQ_BITS_PER_REG - 1);
+ 
+ 	intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
++	intc_bank_read_reg(&irq_banks[0],INTC_REVISION);
+ }
+ 
+ static void omap_unmask_irq(unsigned int irq)
diff --git a/recipes/linux/linux-omap-2.6.28/tick-schedc-suppress-needless-timer-reprogramming.patch b/recipes/linux/linux-omap-2.6.28/tick-schedc-suppress-needless-timer-reprogramming.patch
new file mode 100644
index 0000000000..c5cf4ef6ef
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/tick-schedc-suppress-needless-timer-reprogramming.patch
@@ -0,0 +1,81 @@
+From: "Woodruff, Richard" <r-woodruff2@ti.com>
+
+In my device I get many interrupts from a high speed USB device in a very
+short period of time.  The system spends a lot of time reprogramming the
+hardware timer which is in a slower timing domain as compared to the CPU. 
+This results in the CPU spending a huge amount of time waiting for the
+timer posting to be done.  All of this reprogramming is useless as the
+wake up time has not changed.
+
+As measured using ETM trace this drops my reprogramming penalty from
+almost 60% CPU load down to 15% during high interrupt rate.  I can send
+traces to show this.
+
+
+Suppress setting of duplicate timer event when timer already stopped. 
+Timer programming can be very costly and can result in long cpu stall/wait
+times.
+
+[akpm@linux-foundation.org: coding-style fixes]
+Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+
+On Wed, 24 Sep 2008 18:31:29 +0200 (CEST) Thomas Gleixner <tglx@linutronix.de> wrote:
+
+> No, we only fall trrough into raise_softirq() when the reprogram code
+> detects that the event already expired. So you change the flow :)
+>
+> It does also not deal with delta_jiffies >= NEXT_TIMER_MAX_DELTA :(
+>
+> I have a closer look on that.
+
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+---
+
+ kernel/time/tick-sched.c |   19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+diff -puN kernel/time/tick-sched.c~tick-schedc-suppress-needless-timer-reprogramming kernel/time/tick-sched.c
+--- a/kernel/time/tick-sched.c~tick-schedc-suppress-needless-timer-reprogramming
++++ a/kernel/time/tick-sched.c
+@@ -282,6 +282,17 @@ void tick_nohz_stop_sched_tick(int inidl
+ 	/* Schedule the tick, if we are at least one jiffie off */
+ 	if ((long)delta_jiffies >= 1) {
+ 
++		/*
++		* calculate the expiry time for the next timer wheel
++		* timer
++		*/
++		expires = ktime_add_ns(last_update, tick_period.tv64 *
++				   delta_jiffies);
++
++		/* Skip reprogram of event if its not changed */
++		if (ts->tick_stopped && ktime_equal(expires, dev->next_event))
++			goto out2;
++
+ 		if (delta_jiffies > 1)
+ 			cpu_set(cpu, nohz_cpu_mask);
+ 		/*
+@@ -332,12 +343,7 @@ void tick_nohz_stop_sched_tick(int inidl
+ 			goto out;
+ 		}
+ 
+-		/*
+-		 * calculate the expiry time for the next timer wheel
+-		 * timer
+-		 */
+-		expires = ktime_add_ns(last_update, tick_period.tv64 *
+-				       delta_jiffies);
++		/* Mark expiries */
+ 		ts->idle_expires = expires;
+ 
+ 		if (ts->nohz_mode == NOHZ_MODE_HIGHRES) {
+@@ -356,6 +362,7 @@ void tick_nohz_stop_sched_tick(int inidl
+ 		tick_do_update_jiffies64(ktime_get());
+ 		cpu_clear(cpu, nohz_cpu_mask);
+ 	}
++out2:
+ 	raise_softirq_irqoff(TIMER_SOFTIRQ);
+ out:
+ 	ts->next_jiffies = next_jiffies;
+_
diff --git a/recipes/linux/linux-omap-2.6.28/timer-suppression.patch b/recipes/linux/linux-omap-2.6.28/timer-suppression.patch
new file mode 100644
index 0000000000..04362c96e3
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/timer-suppression.patch
@@ -0,0 +1,43 @@
+diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
+index b854a89..26f5569 100644
+--- a/kernel/time/tick-sched.c
++++ b/kernel/time/tick-sched.c
+@@ -253,6 +253,16 @@ void tick_nohz_stop_sched_tick(void)
+ 
+ 	/* Schedule the tick, if we are at least one jiffie off */
+ 	if ((long)delta_jiffies >= 1) {
++		/*
++		 * calculate the expiry time for the next timer wheel
++		 * timer
++		 */
++		expires = ktime_add_ns(last_update, tick_period.tv64 *
++					delta_jiffies);
++
++		/* Skip reprogram of event if its not changed */
++		if(ts->tick_stopped && ktime_equal(expires, dev->next_event))
++		goto out2;
+ 
+ 		if (delta_jiffies > 1)
+ 			cpu_set(cpu, nohz_cpu_mask);
+@@ -304,12 +314,7 @@ void tick_nohz_stop_sched_tick(void)
+ 			goto out;
+ 		}
+ 
+-		/*
+-		 * calculate the expiry time for the next timer wheel
+-		 * timer
+-		 */
+-		expires = ktime_add_ns(last_update, tick_period.tv64 *
+-				       delta_jiffies);
++		/* Mark expiries */
+ 		ts->idle_expires = expires;
+ 
+ 		if (ts->nohz_mode == NOHZ_MODE_HIGHRES) {
+@@ -328,6 +333,7 @@ void tick_nohz_stop_sched_tick(void)
+ 		tick_do_update_jiffies64(ktime_get());
+ 		cpu_clear(cpu, nohz_cpu_mask);
+ 	}
++out2:	
+ 	raise_softirq_irqoff(TIMER_SOFTIRQ);
+ out:
+ 	ts->next_jiffies = next_jiffies;
diff --git a/recipes/linux/linux-omap-2.6.28/touchscreen.patch b/recipes/linux/linux-omap-2.6.28/touchscreen.patch
new file mode 100644
index 0000000000..2325c401e4
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/touchscreen.patch
@@ -0,0 +1,22 @@
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index d8109ae..f8ce669 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -128,8 +128,16 @@ static int ads7846_get_pendown_state(void)
+ }
+ 
+ struct ads7846_platform_data ads7846_config = {
++	.x_max			= 0x0fff,
++	.y_max			= 0x0fff,
++	.x_plate_ohms		= 180,
++	.pressure_max		= 255,
++	.debounce_max		= 10,
++	.debounce_tol		= 3,
++	.debounce_rep		= 1,
+ 	.get_pendown_state	= ads7846_get_pendown_state,
+ 	.keep_vref_on		= 1,
++	.settle_delay_usecs	= 150,
+ };
+ 
+ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+
diff --git a/recipes/linux/linux-omap-2.6.28/twl-asoc-fix-record.diff b/recipes/linux/linux-omap-2.6.28/twl-asoc-fix-record.diff
new file mode 100644
index 0000000000..9c0ceaa2e0
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.28/twl-asoc-fix-record.diff
@@ -0,0 +1,34 @@
+From linux-omap-owner@vger.kernel.org Sat Dec 06 02:14:21 2008
+Date: 	Fri, 5 Dec 2008 16:46:34 -0800
+From: "Steve Sakoman" <sakoman@gmail.com>
+To: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>
+Subject: [FYI PATCH] ASOC:TWL4030 Audio capture fix
+
+A couple of folks have noticed an issue with audio capture -- the
+capture result is always silence.
+
+The patch below is a quick fix for those with this issue.  There are
+substantial changes to the codec driver that will be trickling down
+from ASoC, and they deal with this issue differently.
+
+So consider this as a bandaid for those who don't want to wait for the
+trickle down :-)
+
+Steve
+
+
+diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
+index ee2f0d3..8b4aafb 100644
+--- a/sound/soc/codecs/twl4030.c
++++ b/sound/soc/codecs/twl4030.c
+@@ -45,8 +45,8 @@ static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
+ 	0xc3, /* REG_OPTION		(0x2)	*/
+ 	0x00, /* REG_UNKNOWN		(0x3)	*/
+ 	0x00, /* REG_MICBIAS_CTL	(0x4)	*/
+-	0x24, /* REG_ANAMICL		(0x5)	*/
+-	0x04, /* REG_ANAMICR		(0x6)	*/
++	0x34, /* REG_ANAMICL		(0x5)	*/
++	0x14, /* REG_ANAMICR		(0x6)	*/
+ 	0x0a, /* REG_AVADC_CTL		(0x7)	*/
+ 	0x00, /* REG_ADCMICSEL		(0x8)	*/
+ 	0x00, /* REG_DIGMIXING		(0x9)	*/