u-boot git: add patches from am3517-crane to get expansion board detection working

Signed-off-by: Koen Kooi <koen@openembedded.org>

4 files changed, 1221 insertions, 1 deletions

diff --git a/recipes/u-boot/u-boot-git/0001-OMAP2-3-I2C-Add-support-for-second-and-third-bus.patch b/recipes/u-boot/u-boot-git/0001-OMAP2-3-I2C-Add-support-for-second-and-third-bus.patch
new file mode 100644
index 0000000000..fda0ec5268
--- /dev/null
+++ b/recipes/u-boot/u-boot-git/0001-OMAP2-3-I2C-Add-support-for-second-and-third-bus.patch
@@ -0,0 +1,498 @@
+From de50dd2dd191b82435863a17306cf0bcbf64ac3f Mon Sep 17 00:00:00 2001
+From: Dirk Behme <dirk.behme@googlemail.com>
+Date: Mon, 2 Nov 2009 20:36:26 +0100
+Subject: [PATCH 1/3] OMAP2/3: I2C: Add support for second and third bus
+
+Add support to use second and third I2C bus, too.
+
+Bus 0 is still the default, but by calling i2c_set_bus_num(1/2) before doing
+I2C accesses, code can switch to bus 1 and 2, too. Don't forget to switch
+back afterwards, then.
+
+Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+---
+ drivers/i2c/omap24xx_i2c.c          |  166 +++++++++++++++++++++--------------
+ include/asm-arm/arch-omap24xx/i2c.h |   53 ++++++++----
+ include/asm-arm/arch-omap3/i2c.h    |   49 +++++++---
+ 3 files changed, 170 insertions(+), 98 deletions(-)
+
+diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
+index 1a4c8c9..ff18991 100644
+--- a/drivers/i2c/omap24xx_i2c.c
++++ b/drivers/i2c/omap24xx_i2c.c
+@@ -29,6 +29,11 @@ static void wait_for_bb (void);
+ static u16 wait_for_pin (void);
+ static void flush_fifo(void);
+ 
++static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
++
++static unsigned int bus_initialized[I2C_BUS_MAX];
++static unsigned int current_bus;
++
+ void i2c_init (int speed, int slaveadd)
+ {
+ 	int psc, fsscll, fssclh;
+@@ -95,30 +100,32 @@ void i2c_init (int speed, int slaveadd)
+ 		sclh = (unsigned int)fssclh;
+ 	}
+ 
+-	writew(0x2, I2C_SYSC); /* for ES2 after soft reset */
++	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
+ 	udelay(1000);
+-	writew(0x0, I2C_SYSC); /* will probably self clear but */
++	writew(0x0, &i2c_base->sysc); /* will probably self clear but */
+ 
+-	if (readw (I2C_CON) & I2C_CON_EN) {
+-		writew (0, I2C_CON);
++	if (readw (&i2c_base->con) & I2C_CON_EN) {
++		writew (0, &i2c_base->con);
+ 		udelay (50000);
+ 	}
+ 
+-	writew(psc, I2C_PSC);
+-	writew(scll, I2C_SCLL);
+-	writew(sclh, I2C_SCLH);
++	writew(psc, &i2c_base->psc);
++	writew(scll, &i2c_base->scll);
++	writew(sclh, &i2c_base->sclh);
+ 
+ 	/* own address */
+-	writew (slaveadd, I2C_OA);
+-	writew (I2C_CON_EN, I2C_CON);
++	writew (slaveadd, &i2c_base->oa);
++	writew (I2C_CON_EN, &i2c_base->con);
+ 
+ 	/* have to enable intrrupts or OMAP i2c module doesn't work */
+ 	writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
+-		I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
++		I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
+ 	udelay (1000);
+ 	flush_fifo();
+-	writew (0xFFFF, I2C_STAT);
+-	writew (0, I2C_CNT);
++	writew (0xFFFF, &i2c_base->stat);
++	writew (0, &i2c_base->cnt);
++
++	bus_initialized[current_bus] = 1;
+ }
+ 
+ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+@@ -130,19 +137,19 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+ 	wait_for_bb ();
+ 
+ 	/* one byte only */
+-	writew (1, I2C_CNT);
++	writew (1, &i2c_base->cnt);
+ 	/* set slave address */
+-	writew (devaddr, I2C_SA);
++	writew (devaddr, &i2c_base->sa);
+ 	/* no stop bit needed here */
+-	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
++	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
+ 
+ 	status = wait_for_pin ();
+ 
+ 	if (status & I2C_STAT_XRDY) {
+ 		/* Important: have to use byte access */
+-		writeb (regoffset, I2C_DATA);
++		writeb (regoffset, &i2c_base->data);
+ 		udelay (20000);
+-		if (readw (I2C_STAT) & I2C_STAT_NACK) {
++		if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
+ 			i2c_error = 1;
+ 		}
+ 	} else {
+@@ -151,28 +158,28 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+ 
+ 	if (!i2c_error) {
+ 		/* free bus, otherwise we can't use a combined transction */
+-		writew (0, I2C_CON);
+-		while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) {
++		writew (0, &i2c_base->con);
++		while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) {
+ 			udelay (10000);
+ 			/* Have to clear pending interrupt to clear I2C_STAT */
+-			writew (0xFFFF, I2C_STAT);
++			writew (0xFFFF, &i2c_base->stat);
+ 		}
+ 
+ 		wait_for_bb ();
+ 		/* set slave address */
+-		writew (devaddr, I2C_SA);
++		writew (devaddr, &i2c_base->sa);
+ 		/* read one byte from slave */
+-		writew (1, I2C_CNT);
++		writew (1, &i2c_base->cnt);
+ 		/* need stop bit here */
+ 		writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
+-			I2C_CON);
++			&i2c_base->con);
+ 
+ 		status = wait_for_pin ();
+ 		if (status & I2C_STAT_RRDY) {
+ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+-			*value = readb (I2C_DATA);
++			*value = readb (&i2c_base->data);
+ #else
+-			*value = readw (I2C_DATA);
++			*value = readw (&i2c_base->data);
+ #endif
+ 			udelay (20000);
+ 		} else {
+@@ -180,17 +187,17 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+ 		}
+ 
+ 		if (!i2c_error) {
+-			writew (I2C_CON_EN, I2C_CON);
+-			while (readw (I2C_STAT)
+-			       || (readw (I2C_CON) & I2C_CON_MST)) {
++			writew (I2C_CON_EN, &i2c_base->con);
++			while (readw (&i2c_base->stat)
++			       || (readw (&i2c_base->con) & I2C_CON_MST)) {
+ 				udelay (10000);
+-				writew (0xFFFF, I2C_STAT);
++				writew (0xFFFF, &i2c_base->stat);
+ 			}
+ 		}
+ 	}
+ 	flush_fifo();
+-	writew (0xFFFF, I2C_STAT);
+-	writew (0, I2C_CNT);
++	writew (0xFFFF, &i2c_base->stat);
++	writew (0, &i2c_base->cnt);
+ 	return i2c_error;
+ }
+ 
+@@ -203,12 +210,12 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
+ 	wait_for_bb ();
+ 
+ 	/* two bytes */
+-	writew (2, I2C_CNT);
++	writew (2, &i2c_base->cnt);
+ 	/* set slave address */
+-	writew (devaddr, I2C_SA);
++	writew (devaddr, &i2c_base->sa);
+ 	/* stop bit needed here */
+ 	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+-		I2C_CON_STP, I2C_CON);
++		I2C_CON_STP, &i2c_base->con);
+ 
+ 	/* wait until state change */
+ 	status = wait_for_pin ();
+@@ -216,24 +223,24 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
+ 	if (status & I2C_STAT_XRDY) {
+ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+ 		/* send out 1 byte */
+-		writeb (regoffset, I2C_DATA);
+-		writew (I2C_STAT_XRDY, I2C_STAT);
++		writeb (regoffset, &i2c_base->data);
++		writew (I2C_STAT_XRDY, &i2c_base->stat);
+ 
+ 		status = wait_for_pin ();
+ 		if ((status & I2C_STAT_XRDY)) {
+ 			/* send out next 1 byte */
+-			writeb (value, I2C_DATA);
+-			writew (I2C_STAT_XRDY, I2C_STAT);
++			writeb (value, &i2c_base->data);
++			writew (I2C_STAT_XRDY, &i2c_base->stat);
+ 		} else {
+ 			i2c_error = 1;
+ 		}
+ #else
+ 		/* send out two bytes */
+-		writew ((value << 8) + regoffset, I2C_DATA);
++		writew ((value << 8) + regoffset, &i2c_base->data);
+ #endif
+ 		/* must have enough delay to allow BB bit to go low */
+ 		udelay (50000);
+-		if (readw (I2C_STAT) & I2C_STAT_NACK) {
++		if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
+ 			i2c_error = 1;
+ 		}
+ 	} else {
+@@ -243,18 +250,18 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
+ 	if (!i2c_error) {
+ 		int eout = 200;
+ 
+-		writew (I2C_CON_EN, I2C_CON);
+-		while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) {
++		writew (I2C_CON_EN, &i2c_base->con);
++		while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
+ 			udelay (1000);
+ 			/* have to read to clear intrrupt */
+-			writew (0xFFFF, I2C_STAT);
++			writew (0xFFFF, &i2c_base->stat);
+ 			if(--eout == 0) /* better leave with error than hang */
+ 				break;
+ 		}
+ 	}
+ 	flush_fifo();
+-	writew (0xFFFF, I2C_STAT);
+-	writew (0, I2C_CNT);
++	writew (0xFFFF, &i2c_base->stat);
++	writew (0, &i2c_base->cnt);
+ 	return i2c_error;
+ }
+ 
+@@ -265,14 +272,14 @@ static void flush_fifo(void)
+ 	 * you get a bus error
+ 	 */
+ 	while(1){
+-		stat = readw(I2C_STAT);
++		stat = readw(&i2c_base->stat);
+ 		if(stat == I2C_STAT_RRDY){
+ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+-			readb(I2C_DATA);
++			readb(&i2c_base->data);
+ #else
+-			readw(I2C_DATA);
++			readw(&i2c_base->data);
+ #endif
+-			writew(I2C_STAT_RRDY,I2C_STAT);
++			writew(I2C_STAT_RRDY,&i2c_base->stat);
+ 			udelay(1000);
+ 		}else
+ 			break;
+@@ -283,7 +290,7 @@ int i2c_probe (uchar chip)
+ {
+ 	int res = 1; /* default = fail */
+ 
+-	if (chip == readw (I2C_OA)) {
++	if (chip == readw (&i2c_base->oa)) {
+ 		return res;
+ 	}
+ 
+@@ -291,27 +298,27 @@ int i2c_probe (uchar chip)
+ 	wait_for_bb ();
+ 
+ 	/* try to read one byte */
+-	writew (1, I2C_CNT);
++	writew (1, &i2c_base->cnt);
+ 	/* set slave address */
+-	writew (chip, I2C_SA);
++	writew (chip, &i2c_base->sa);
+ 	/* stop bit needed here */
+-	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
++	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
+ 	/* enough delay for the NACK bit set */
+ 	udelay (50000);
+ 
+-	if (!(readw (I2C_STAT) & I2C_STAT_NACK)) {
++	if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
+ 		res = 0;      /* success case */
+ 		flush_fifo();
+-		writew(0xFFFF, I2C_STAT);
++		writew(0xFFFF, &i2c_base->stat);
+ 	} else {
+-		writew(0xFFFF, I2C_STAT);	 /* failue, clear sources*/
+-		writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */
++		writew(0xFFFF, &i2c_base->stat);	 /* failue, clear sources*/
++		writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
+ 		udelay(20000);
+ 		wait_for_bb ();
+ 	}
+ 	flush_fifo();
+-	writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/
+-	writew(0xFFFF, I2C_STAT);
++	writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
++	writew(0xFFFF, &i2c_base->stat);
+ 	return res;
+ }
+ 
+@@ -370,17 +377,17 @@ static void wait_for_bb (void)
+ 	int timeout = 10;
+ 	u16 stat;
+ 
+-	writew(0xFFFF, I2C_STAT);	 /* clear current interruts...*/
+-	while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
+-		writew (stat, I2C_STAT);
++	writew(0xFFFF, &i2c_base->stat);	 /* clear current interruts...*/
++	while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
++		writew (stat, &i2c_base->stat);
+ 		udelay (50000);
+ 	}
+ 
+ 	if (timeout <= 0) {
+ 		printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
+-			readw (I2C_STAT));
++			readw (&i2c_base->stat));
+ 	}
+-	writew(0xFFFF, I2C_STAT);	 /* clear delayed stuff*/
++	writew(0xFFFF, &i2c_base->stat);	 /* clear delayed stuff*/
+ }
+ 
+ static u16 wait_for_pin (void)
+@@ -390,7 +397,7 @@ static u16 wait_for_pin (void)
+ 
+ 	do {
+ 		udelay (1000);
+-		status = readw (I2C_STAT);
++		status = readw (&i2c_base->stat);
+ 	} while (  !(status &
+ 		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
+ 		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
+@@ -398,8 +405,33 @@ static u16 wait_for_pin (void)
+ 
+ 	if (timeout <= 0) {
+ 		printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
+-			readw (I2C_STAT));
+-			writew(0xFFFF, I2C_STAT);
++			readw (&i2c_base->stat));
++			writew(0xFFFF, &i2c_base->stat);
+ }
+ 	return status;
+ }
++
++int i2c_set_bus_num(unsigned int bus)
++{
++	if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
++		printf("Bad bus: %d\n", bus);
++		return -1;
++	}
++
++#if I2C_BUS_MAX==3
++	if (bus == 2)
++		i2c_base = (struct i2c *)I2C_BASE3;
++	else
++#endif
++	if (bus == 1)
++		i2c_base = (struct i2c *)I2C_BASE2;
++	else
++		i2c_base = (struct i2c *)I2C_BASE1;
++
++	current_bus = bus;
++
++	if(!bus_initialized[current_bus])
++		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
++
++	return 0;
++}
+diff --git a/include/asm-arm/arch-omap24xx/i2c.h b/include/asm-arm/arch-omap24xx/i2c.h
+index 44db7a2..19046aa 100644
+--- a/include/asm-arm/arch-omap24xx/i2c.h
++++ b/include/asm-arm/arch-omap24xx/i2c.h
+@@ -23,24 +23,45 @@
+ #ifndef _OMAP24XX_I2C_H_
+ #define _OMAP24XX_I2C_H_
+ 
+-#define I2C_BASE                0x48070000
++#define I2C_BASE1		0x48070000
+ #define I2C_BASE2               0x48072000 /* nothing hooked up on h4 */
+ 
+-#define I2C_REV                 (I2C_BASE + 0x00)
+-#define I2C_IE                  (I2C_BASE + 0x04)
+-#define I2C_STAT                (I2C_BASE + 0x08)
+-#define I2C_IV                  (I2C_BASE + 0x0c)
+-#define I2C_BUF                 (I2C_BASE + 0x14)
+-#define I2C_CNT                 (I2C_BASE + 0x18)
+-#define I2C_DATA                (I2C_BASE + 0x1c)
+-#define I2C_SYSC                (I2C_BASE + 0x20)
+-#define I2C_CON                 (I2C_BASE + 0x24)
+-#define I2C_OA                  (I2C_BASE + 0x28)
+-#define I2C_SA                  (I2C_BASE + 0x2c)
+-#define I2C_PSC                 (I2C_BASE + 0x30)
+-#define I2C_SCLL                (I2C_BASE + 0x34)
+-#define I2C_SCLH                (I2C_BASE + 0x38)
+-#define I2C_SYSTEST             (I2C_BASE + 0x3c)
++#define I2C_DEFAULT_BASE	I2C_BASE1
++
++struct i2c {
++	unsigned short rev;	/* 0x00 */
++	unsigned short res1;
++	unsigned short ie;	/* 0x04 */
++	unsigned short res2;
++	unsigned short stat;	/* 0x08 */
++	unsigned short res3;
++	unsigned short iv;	/* 0x0C */
++	unsigned short res4[3];
++	unsigned short buf;	/* 0x14 */
++	unsigned short res5;
++	unsigned short cnt;	/* 0x18 */
++	unsigned short res6;
++	unsigned short data;	/* 0x1C */
++	unsigned short res7;
++	unsigned short sysc;	/* 0x20 */
++	unsigned short res8;
++	unsigned short con;	/* 0x24 */
++	unsigned short res9;
++	unsigned short oa;	/* 0x28 */
++	unsigned short res10;
++	unsigned short sa;	/* 0x2C */
++	unsigned short res11;
++	unsigned short psc;	/* 0x30 */
++	unsigned short res12;
++	unsigned short scll;	/* 0x34 */
++	unsigned short res13;
++	unsigned short sclh;	/* 0x38 */
++	unsigned short res14;
++	unsigned short systest;	/* 0x3c */
++	unsigned short res15;
++};
++
++#define I2C_BUS_MAX	2
+ 
+ /* I2C masks */
+ 
+diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h
+index 8b339cc..490e03b 100644
+--- a/include/asm-arm/arch-omap3/i2c.h
++++ b/include/asm-arm/arch-omap3/i2c.h
+@@ -25,21 +25,40 @@
+ 
+ #define I2C_DEFAULT_BASE	I2C_BASE1
+ 
+-#define I2C_REV		(I2C_DEFAULT_BASE + 0x00)
+-#define I2C_IE 		(I2C_DEFAULT_BASE + 0x04)
+-#define I2C_STAT	(I2C_DEFAULT_BASE + 0x08)
+-#define I2C_IV 		(I2C_DEFAULT_BASE + 0x0c)
+-#define I2C_BUF		(I2C_DEFAULT_BASE + 0x14)
+-#define I2C_CNT		(I2C_DEFAULT_BASE + 0x18)
+-#define I2C_DATA	(I2C_DEFAULT_BASE + 0x1c)
+-#define I2C_SYSC	(I2C_DEFAULT_BASE + 0x20)
+-#define I2C_CON		(I2C_DEFAULT_BASE + 0x24)
+-#define I2C_OA 		(I2C_DEFAULT_BASE + 0x28)
+-#define I2C_SA 		(I2C_DEFAULT_BASE + 0x2c)
+-#define I2C_PSC		(I2C_DEFAULT_BASE + 0x30)
+-#define I2C_SCLL	(I2C_DEFAULT_BASE + 0x34)
+-#define I2C_SCLH	(I2C_DEFAULT_BASE + 0x38)
+-#define I2C_SYSTEST	(I2C_DEFAULT_BASE + 0x3c)
++struct i2c {
++	unsigned short rev;	/* 0x00 */
++	unsigned short res1;
++	unsigned short ie;	/* 0x04 */
++	unsigned short res2;
++	unsigned short stat;	/* 0x08 */
++	unsigned short res3;
++	unsigned short iv;	/* 0x0C */
++	unsigned short res4[3];
++	unsigned short buf;	/* 0x14 */
++	unsigned short res5;
++	unsigned short cnt;	/* 0x18 */
++	unsigned short res6;
++	unsigned short data;	/* 0x1C */
++	unsigned short res7;
++	unsigned short sysc;	/* 0x20 */
++	unsigned short res8;
++	unsigned short con;	/* 0x24 */
++	unsigned short res9;
++	unsigned short oa;	/* 0x28 */
++	unsigned short res10;
++	unsigned short sa;	/* 0x2C */
++	unsigned short res11;
++	unsigned short psc;	/* 0x30 */
++	unsigned short res12;
++	unsigned short scll;	/* 0x34 */
++	unsigned short res13;
++	unsigned short sclh;	/* 0x38 */
++	unsigned short res14;
++	unsigned short systest;	/* 0x3c */
++	unsigned short res15;
++};
++
++#define I2C_BUS_MAX	3
+ 
+ /* I2C masks */
+ 
+-- 
+1.6.6.1
+
diff --git a/recipes/u-boot/u-boot-git/0002-ARMV7-Restructure-OMAP-i2c-driver-to-allow-code-shar.patch b/recipes/u-boot/u-boot-git/0002-ARMV7-Restructure-OMAP-i2c-driver-to-allow-code-shar.patch
new file mode 100644
index 0000000000..c0a30f611e
--- /dev/null
+++ b/recipes/u-boot/u-boot-git/0002-ARMV7-Restructure-OMAP-i2c-driver-to-allow-code-shar.patch
@@ -0,0 +1,491 @@
+From c678f89db2968af02f2902f1a187bea7db95f6fb Mon Sep 17 00:00:00 2001
+From: Steve Sakoman <steve@sakoman.com>
+Date: Sat, 12 Jun 2010 06:42:57 -0700
+Subject: [PATCH 2/3] ARMV7: Restructure OMAP i2c driver to allow code sharing between OMAP3 and OMAP4
+
+This patch modifies the omap24xx driver so that it will also work with OMAP4.
+
+Signed-off-by: Steve Sakoman <steve@sakoman.com>
+Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+---
+ arch/arm/include/asm/arch-omap4/i2c.h |   74 +++++++++++++++
+ drivers/i2c/omap24xx_i2c.c            |   17 +++-
+ drivers/i2c/omap24xx_i2c.h            |  166 +++++++++++++++++++++++++++++++++
+ include/asm-arm/arch-omap3/i2c.h      |  149 +----------------------------
+ 4 files changed, 258 insertions(+), 148 deletions(-)
+ create mode 100644 arch/arm/include/asm/arch-omap4/i2c.h
+ create mode 100644 drivers/i2c/omap24xx_i2c.h
+
+diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h
+new file mode 100644
+index 0000000..a91b4c2
+--- /dev/null
++++ b/arch/arm/include/asm/arch-omap4/i2c.h
+@@ -0,0 +1,74 @@
++/*
++ * (C) Copyright 2004-2010
++ * Texas Instruments, <www.ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef _OMAP4_I2C_H_
++#define _OMAP4_I2C_H_
++
++#define I2C_BUS_MAX	3
++#define I2C_DEFAULT_BASE	I2C_BASE1
++
++struct i2c {
++	unsigned short revnb_lo;	/* 0x00 */
++	unsigned short res1;
++	unsigned short revnb_hi;	/* 0x04 */
++	unsigned short res2[13];
++	unsigned short sysc;		/* 0x20 */
++	unsigned short res3;
++	unsigned short irqstatus_raw;	/* 0x24 */
++	unsigned short res4;
++	unsigned short stat;		/* 0x28 */
++	unsigned short res5;
++	unsigned short ie;		/* 0x2C */
++	unsigned short res6;
++	unsigned short irqenable_clr;	/* 0x30 */
++	unsigned short res7;
++	unsigned short iv;		/* 0x34 */
++	unsigned short res8[45];
++	unsigned short syss;		/* 0x90 */
++	unsigned short res9;
++	unsigned short buf;		/* 0x94 */
++	unsigned short res10;
++	unsigned short cnt;		/* 0x98 */
++	unsigned short res11;
++	unsigned short data;		/* 0x9C */
++	unsigned short res13;
++	unsigned short res14;		/* 0xA0 */
++	unsigned short res15;
++	unsigned short con;		/* 0xA4 */
++	unsigned short res16;
++	unsigned short oa;		/* 0xA8 */
++	unsigned short res17;
++	unsigned short sa;		/* 0xAC */
++	unsigned short res18;
++	unsigned short psc;		/* 0xB0 */
++	unsigned short res19;
++	unsigned short scll;		/* 0xB4 */
++	unsigned short res20;
++	unsigned short sclh;		/* 0xB8 */
++	unsigned short res21;
++	unsigned short systest;		/* 0xBC */
++	unsigned short res22;
++	unsigned short bufstat;		/* 0xC0 */
++	unsigned short res23;
++};
++
++#endif /* _OMAP4_I2C_H_ */
+diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
+index ff18991..3256133 100644
+--- a/drivers/i2c/omap24xx_i2c.c
++++ b/drivers/i2c/omap24xx_i2c.c
+@@ -25,6 +25,8 @@
+ #include <asm/arch/i2c.h>
+ #include <asm/io.h>
+ 
++#include "omap24xx_i2c.h"
++
+ static void wait_for_bb (void);
+ static u16 wait_for_pin (void);
+ static void flush_fifo(void);
+@@ -176,7 +178,8 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+ 
+ 		status = wait_for_pin ();
+ 		if (status & I2C_STAT_RRDY) {
+-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
++#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
++    defined(CONFIG_OMAP44XX)
+ 			*value = readb (&i2c_base->data);
+ #else
+ 			*value = readw (&i2c_base->data);
+@@ -221,7 +224,8 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
+ 	status = wait_for_pin ();
+ 
+ 	if (status & I2C_STAT_XRDY) {
+-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
++#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
++    defined(CONFIG_OMAP44XX)
+ 		/* send out 1 byte */
+ 		writeb (regoffset, &i2c_base->data);
+ 		writew (I2C_STAT_XRDY, &i2c_base->stat);
+@@ -274,7 +278,8 @@ static void flush_fifo(void)
+ 	while(1){
+ 		stat = readw(&i2c_base->stat);
+ 		if(stat == I2C_STAT_RRDY){
+-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
++#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
++    defined(CONFIG_OMAP44XX)
+ 			readb(&i2c_base->data);
+ #else
+ 			readw(&i2c_base->data);
+@@ -435,3 +440,9 @@ int i2c_set_bus_num(unsigned int bus)
+ 
+ 	return 0;
+ }
++
++int i2c_get_bus_num(void)
++{
++	return (int) current_bus;
++}
++
+diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
+new file mode 100644
+index 0000000..92a3416
+--- /dev/null
++++ b/drivers/i2c/omap24xx_i2c.h
+@@ -0,0 +1,166 @@
++/*
++ * (C) Copyright 2004-2010
++ * Texas Instruments, <www.ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef _OMAP24XX_I2C_H_
++#define _OMAP24XX_I2C_H_
++
++/* I2C masks */
++
++/* I2C Interrupt Enable Register (I2C_IE): */
++#define I2C_IE_GC_IE	(1 << 5)
++#define I2C_IE_XRDY_IE	(1 << 4) /* Transmit data ready interrupt enable */
++#define I2C_IE_RRDY_IE	(1 << 3) /* Receive data ready interrupt enable */
++#define I2C_IE_ARDY_IE	(1 << 2) /* Register access ready interrupt enable */
++#define I2C_IE_NACK_IE	(1 << 1) /* No acknowledgment interrupt enable */
++#define I2C_IE_AL_IE	(1 << 0) /* Arbitration lost interrupt enable */
++
++/* I2C Status Register (I2C_STAT): */
++
++#define I2C_STAT_SBD	(1 << 15) /* Single byte data */
++#define I2C_STAT_BB	(1 << 12) /* Bus busy */
++#define I2C_STAT_ROVR	(1 << 11) /* Receive overrun */
++#define I2C_STAT_XUDF	(1 << 10) /* Transmit underflow */
++#define I2C_STAT_AAS	(1 << 9)  /* Address as slave */
++#define I2C_STAT_GC	(1 << 5)
++#define I2C_STAT_XRDY	(1 << 4)  /* Transmit data ready */
++#define I2C_STAT_RRDY	(1 << 3)  /* Receive data ready */
++#define I2C_STAT_ARDY	(1 << 2)  /* Register access ready */
++#define I2C_STAT_NACK	(1 << 1)  /* No acknowledgment interrupt enable */
++#define I2C_STAT_AL	(1 << 0)  /* Arbitration lost interrupt enable */
++
++/* I2C Interrupt Code Register (I2C_INTCODE): */
++
++#define I2C_INTCODE_MASK	7
++#define I2C_INTCODE_NONE	0
++#define I2C_INTCODE_AL		1	/* Arbitration lost */
++#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
++#define I2C_INTCODE_ARDY	3	/* Register access ready */
++#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
++#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
++
++/* I2C Buffer Configuration Register (I2C_BUF): */
++
++#define I2C_BUF_RDMA_EN		(1 << 15) /* Receive DMA channel enable */
++#define I2C_BUF_XDMA_EN		(1 << 7)  /* Transmit DMA channel enable */
++
++/* I2C Configuration Register (I2C_CON): */
++
++#define I2C_CON_EN	(1 << 15)  /* I2C module enable */
++#define I2C_CON_BE	(1 << 14)  /* Big endian mode */
++#define I2C_CON_STB	(1 << 11)  /* Start byte mode (master mode only) */
++#define I2C_CON_MST	(1 << 10)  /* Master/slave mode */
++#define I2C_CON_TRX	(1 << 9)   /* Transmitter/receiver mode */
++				   /* (master mode only) */
++#define I2C_CON_XA	(1 << 8)   /* Expand address */
++#define I2C_CON_STP	(1 << 1)   /* Stop condition (master mode only) */
++#define I2C_CON_STT	(1 << 0)   /* Start condition (master mode only) */
++
++/* I2C System Test Register (I2C_SYSTEST): */
++
++#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
++#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
++#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
++#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
++#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
++#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
++#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
++#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
++
++#define I2C_SCLL_SCLL		0
++#define I2C_SCLL_SCLL_M		0xFF
++#define I2C_SCLL_HSSCLL		8
++#define I2C_SCLH_HSSCLL_M	0xFF
++#define I2C_SCLH_SCLH		0
++#define I2C_SCLH_SCLH_M		0xFF
++#define I2C_SCLH_HSSCLH		8
++#define I2C_SCLH_HSSCLH_M	0xFF
++
++#define OMAP_I2C_STANDARD	100000
++#define OMAP_I2C_FAST_MODE	400000
++#define OMAP_I2C_HIGH_SPEED	3400000
++
++#define SYSTEM_CLOCK_12		12000000
++#define SYSTEM_CLOCK_13		13000000
++#define SYSTEM_CLOCK_192	19200000
++#define SYSTEM_CLOCK_96		96000000
++
++/* Use the reference value of 96MHz if not explicitly set by the board */
++#ifndef I2C_IP_CLK
++#define I2C_IP_CLK		SYSTEM_CLOCK_96
++#endif
++
++/*
++ * The reference minimum clock for high speed is 19.2MHz.
++ * The linux 2.6.30 kernel uses this value.
++ * The reference minimum clock for fast mode is 9.6MHz
++ * The reference minimum clock for standard mode is 4MHz
++ * In TRM, the value of 12MHz is used.
++ */
++#ifndef I2C_INTERNAL_SAMPLING_CLK
++#define I2C_INTERNAL_SAMPLING_CLK	19200000
++#endif
++
++/*
++ * The equation for the low and high time is
++ * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
++ * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
++ *
++ * If the duty cycle is 50%
++ *
++ * tlow = scll + scll_trim = sampling clock / (2 * speed)
++ * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
++ *
++ * In TRM
++ * scll_trim = 7
++ * sclh_trim = 5
++ *
++ * The linux 2.6.30 kernel uses
++ * scll_trim = 6
++ * sclh_trim = 6
++ *
++ * These are the trim values for standard and fast speed
++ */
++#ifndef I2C_FASTSPEED_SCLL_TRIM
++#define I2C_FASTSPEED_SCLL_TRIM		6
++#endif
++#ifndef I2C_FASTSPEED_SCLH_TRIM
++#define I2C_FASTSPEED_SCLH_TRIM		6
++#endif
++
++/* These are the trim values for high speed */
++#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
++#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
++#endif
++#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
++#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
++#endif
++#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
++#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
++#endif
++#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
++#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
++#endif
++
++#define I2C_PSC_MAX		0x0f
++#define I2C_PSC_MIN		0x00
++
++#endif /* _OMAP24XX_I2C_H_ */
+diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h
+index 490e03b..7a4a73a 100644
+--- a/include/asm-arm/arch-omap3/i2c.h
++++ b/include/asm-arm/arch-omap3/i2c.h
+@@ -20,9 +20,10 @@
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+  * MA 02111-1307 USA
+  */
+-#ifndef _I2C_H_
+-#define _I2C_H_
++#ifndef _OMAP3_I2C_H_
++#define _OMAP3_I2C_H_
+ 
++#define I2C_BUS_MAX	3
+ #define I2C_DEFAULT_BASE	I2C_BASE1
+ 
+ struct i2c {
+@@ -58,146 +59,4 @@ struct i2c {
+ 	unsigned short res15;
+ };
+ 
+-#define I2C_BUS_MAX	3
+-
+-/* I2C masks */
+-
+-/* I2C Interrupt Enable Register (I2C_IE): */
+-#define I2C_IE_GC_IE	(1 << 5)
+-#define I2C_IE_XRDY_IE	(1 << 4) /* Transmit data ready interrupt enable */
+-#define I2C_IE_RRDY_IE	(1 << 3) /* Receive data ready interrupt enable */
+-#define I2C_IE_ARDY_IE	(1 << 2) /* Register access ready interrupt enable */
+-#define I2C_IE_NACK_IE	(1 << 1) /* No acknowledgment interrupt enable */
+-#define I2C_IE_AL_IE	(1 << 0) /* Arbitration lost interrupt enable */
+-
+-/* I2C Status Register (I2C_STAT): */
+-
+-#define I2C_STAT_SBD	(1 << 15) /* Single byte data */
+-#define I2C_STAT_BB	(1 << 12) /* Bus busy */
+-#define I2C_STAT_ROVR	(1 << 11) /* Receive overrun */
+-#define I2C_STAT_XUDF	(1 << 10) /* Transmit underflow */
+-#define I2C_STAT_AAS	(1 << 9)  /* Address as slave */
+-#define I2C_STAT_GC	(1 << 5)
+-#define I2C_STAT_XRDY	(1 << 4)  /* Transmit data ready */
+-#define I2C_STAT_RRDY	(1 << 3)  /* Receive data ready */
+-#define I2C_STAT_ARDY	(1 << 2)  /* Register access ready */
+-#define I2C_STAT_NACK	(1 << 1)  /* No acknowledgment interrupt enable */
+-#define I2C_STAT_AL	(1 << 0)  /* Arbitration lost interrupt enable */
+-
+-/* I2C Interrupt Code Register (I2C_INTCODE): */
+-
+-#define I2C_INTCODE_MASK	7
+-#define I2C_INTCODE_NONE	0
+-#define I2C_INTCODE_AL		1	/* Arbitration lost */
+-#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
+-#define I2C_INTCODE_ARDY	3	/* Register access ready */
+-#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
+-#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
+-
+-/* I2C Buffer Configuration Register (I2C_BUF): */
+-
+-#define I2C_BUF_RDMA_EN		(1 << 15) /* Receive DMA channel enable */
+-#define I2C_BUF_XDMA_EN		(1 << 7)  /* Transmit DMA channel enable */
+-
+-/* I2C Configuration Register (I2C_CON): */
+-
+-#define I2C_CON_EN	(1 << 15)  /* I2C module enable */
+-#define I2C_CON_BE	(1 << 14)  /* Big endian mode */
+-#define I2C_CON_STB	(1 << 11)  /* Start byte mode (master mode only) */
+-#define I2C_CON_MST	(1 << 10)  /* Master/slave mode */
+-#define I2C_CON_TRX	(1 << 9)   /* Transmitter/receiver mode */
+-				   /* (master mode only) */
+-#define I2C_CON_XA	(1 << 8)   /* Expand address */
+-#define I2C_CON_STP	(1 << 1)   /* Stop condition (master mode only) */
+-#define I2C_CON_STT	(1 << 0)   /* Start condition (master mode only) */
+-
+-/* I2C System Test Register (I2C_SYSTEST): */
+-
+-#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
+-#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
+-#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
+-#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
+-#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
+-#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
+-#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
+-#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
+-
+-#define I2C_SCLL_SCLL		0
+-#define I2C_SCLL_SCLL_M		0xFF
+-#define I2C_SCLL_HSSCLL		8
+-#define I2C_SCLH_HSSCLL_M	0xFF
+-#define I2C_SCLH_SCLH		0
+-#define I2C_SCLH_SCLH_M		0xFF
+-#define I2C_SCLH_HSSCLH		8
+-#define I2C_SCLH_HSSCLH_M	0xFF
+-
+-#define OMAP_I2C_STANDARD	100000
+-#define OMAP_I2C_FAST_MODE	400000
+-#define OMAP_I2C_HIGH_SPEED	3400000
+-
+-#define SYSTEM_CLOCK_12		12000000
+-#define SYSTEM_CLOCK_13		13000000
+-#define SYSTEM_CLOCK_192	19200000
+-#define SYSTEM_CLOCK_96		96000000
+-
+-/* Use the reference value of 96MHz if not explicitly set by the board */
+-#ifndef I2C_IP_CLK
+-#define I2C_IP_CLK		SYSTEM_CLOCK_96
+-#endif
+-
+-/*
+- * The reference minimum clock for high speed is 19.2MHz.
+- * The linux 2.6.30 kernel uses this value.
+- * The reference minimum clock for fast mode is 9.6MHz
+- * The reference minimum clock for standard mode is 4MHz
+- * In TRM, the value of 12MHz is used.
+- */
+-#ifndef I2C_INTERNAL_SAMPLING_CLK
+-#define I2C_INTERNAL_SAMPLING_CLK	19200000
+-#endif
+-
+-/*
+- * The equation for the low and high time is
+- * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
+- * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
+- *
+- * If the duty cycle is 50%
+- *
+- * tlow = scll + scll_trim = sampling clock / (2 * speed)
+- * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
+- *
+- * In TRM
+- * scll_trim = 7
+- * sclh_trim = 5
+- *
+- * The linux 2.6.30 kernel uses
+- * scll_trim = 6
+- * sclh_trim = 6
+- *
+- * These are the trim values for standard and fast speed
+- */
+-#ifndef I2C_FASTSPEED_SCLL_TRIM
+-#define I2C_FASTSPEED_SCLL_TRIM		6
+-#endif
+-#ifndef I2C_FASTSPEED_SCLH_TRIM
+-#define I2C_FASTSPEED_SCLH_TRIM		6
+-#endif
+-
+-/* These are the trim values for high speed */
+-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+-#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
+-#endif
+-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+-#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
+-#endif
+-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+-#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
+-#endif
+-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+-#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
+-#endif
+-
+-#define I2C_PSC_MAX		0x0f
+-#define I2C_PSC_MIN		0x00
+-
+-#endif /* _I2C_H_ */
++#endif /* _OMAP3_I2C_H_ */
+-- 
+1.6.6.1
+
diff --git a/recipes/u-boot/u-boot-git/0003-craneboard-add-expansionboard-support.patch b/recipes/u-boot/u-boot-git/0003-craneboard-add-expansionboard-support.patch
new file mode 100644
index 0000000000..0126f7341e
--- /dev/null
+++ b/recipes/u-boot/u-boot-git/0003-craneboard-add-expansionboard-support.patch
@@ -0,0 +1,227 @@
+From 4727db0f161869a41045e7a52f938a6f88400b73 Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@dominion.thruhere.net>
+Date: Wed, 19 Jan 2011 14:55:22 +0100
+Subject: [PATCH 3/3] craneboard: add expansionboard support
+
+Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
+---
+ board/ti/am3517crane/am3517crane.c |   99 ++++++++++++++++++++++++++++++++++++
+ board/ti/am3517crane/am3517crane.h |   42 +++++++++++++++
+ include/configs/am3517_crane.h     |    6 ++-
+ 3 files changed, 146 insertions(+), 1 deletions(-)
+
+diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
+index 2f525b6..0822503 100644
+--- a/board/ti/am3517crane/am3517crane.c
++++ b/board/ti/am3517crane/am3517crane.c
+@@ -45,6 +45,27 @@
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
++#define TWL4030_I2C_BUS			0
++#define EXPANSION_EEPROM_I2C_BUS	1
++#define EXPANSION_EEPROM_I2C_ADDRESS	0x50
++
++#define TINCANTOOLS_ZIPPY		0x01000100
++#define TINCANTOOLS_ZIPPY2		0x02000100
++#define TINCANTOOLS_TRAINER		0x04000100
++#define TINCANTOOLS_SHOWDOG		0x03000100
++#define KBADC_BEAGLEFPGA		0x01000600
++
++#define BEAGLE_NO_EEPROM		0xffffffff
++
++static struct {
++	unsigned int device_vendor;
++	unsigned char revision;
++	unsigned char content;
++	char fab_revision[8];
++	char env_var[16];
++	char env_setting[64];
++} expansion_config;
++
+ /*
+  * Routine: board_init
+  * Description: Early hardware init.
+@@ -61,6 +82,32 @@ int board_init(void)
+ }
+ 
+ /*
++ * Routine: get_expansion_id
++ * Description: This function checks for expansion board by checking I2C
++ *		bus 1 for the availability of an AT24C01B serial EEPROM.
++ *		returns the device_vendor field from the EEPROM
++ */
++unsigned int get_expansion_id(void)
++{
++	i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
++
++	/* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
++	if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
++		i2c_set_bus_num(TWL4030_I2C_BUS);
++		return BEAGLE_NO_EEPROM;
++	}
++
++	/* read configuration data */
++	i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
++		 sizeof(expansion_config));
++
++	i2c_set_bus_num(TWL4030_I2C_BUS);
++
++	return expansion_config.device_vendor;
++}
++
++
++/*
+  * Routine: misc_init_r
+  * Description: Init ethernet (done here so udelay works)
+  */
+@@ -95,9 +142,61 @@ int misc_init_r(void)
+ 	reset &= (~CPGMACSS_SW_RST);
+ 	writel(reset, AM3517_IP_SW_RESET);
+ #endif
++
++	switch (get_expansion_id()) {
++	case TINCANTOOLS_ZIPPY:
++		printf("Recognized Tincantools Zippy board (rev %d %s)\n",
++			expansion_config.revision,
++			expansion_config.fab_revision);
++		//MUX_TINCANTOOLS_ZIPPY();
++		setenv("buddy", "zippy");
++		break;
++	case TINCANTOOLS_ZIPPY2:
++		printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
++			expansion_config.revision,
++			expansion_config.fab_revision);
++		//MUX_TINCANTOOLS_ZIPPY();
++		setenv("buddy", "zippy2");
++		break;
++	case TINCANTOOLS_TRAINER:
++		printf("Recognized Tincantools Trainer board (rev %d %s)\n",
++			expansion_config.revision,
++			expansion_config.fab_revision);
++		//MUX_TINCANTOOLS_ZIPPY();
++		//MUX_TINCANTOOLS_TRAINER();
++		setenv("buddy", "trainer");
++		break;
++	case TINCANTOOLS_SHOWDOG:
++		printf("Recognized Tincantools Showdow board (rev %d %s)\n",
++			expansion_config.revision,
++			expansion_config.fab_revision);
++		/* Place holder for DSS2 definition for showdog lcd */
++		setenv("defaultdisplay", "showdoglcd");
++		setenv("buddy", "showdog");
++		break;
++	case KBADC_BEAGLEFPGA:
++		printf("Recognized KBADC Beagle FPGA board\n");
++		//MUX_KBADC_BEAGLEFPGA();
++		setenv("buddy", "beaglefpga");
++		break;
++	case BEAGLE_NO_EEPROM:
++		printf("No EEPROM on expansion board\n");
++		setenv("buddy", "none");
++		break;
++	default:
++		printf("Unrecognized expansion board: %x\n",
++			expansion_config.device_vendor);
++		setenv("buddy", "unknown");
++	}
++
++	if (expansion_config.content == 1)
++		setenv(expansion_config.env_var, expansion_config.env_setting);
++
+ 	return 0;
+ }
+ 
++
++
+ /*
+  * Initializes on-chip ethernet controllers.
+  * to override, implement board_eth_init()
+diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h
+index dbe2c34..83fe858 100644
+--- a/board/ti/am3517crane/am3517crane.h
++++ b/board/ti/am3517crane/am3517crane.h
+@@ -336,4 +336,46 @@ const omap3_sysinfo sysinfo = {
+ 	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
+ 	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
+ 
++#define MUX_TINCANTOOLS_ZIPPY() \
++	MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
++	MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
++	MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
++	MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
++	MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
++	MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
++	MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
++	MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
++	MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
++	MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
++	MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | EN  | M1)) /*MCSPI4_CLK*/\
++	MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
++	MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | EN  | M1)) /*MCSPI4_SIMO*/\
++	MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
++	MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | EN  | M1)) /*MCSPI4_CS0*/\
++	MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
++	MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_140*/\
++	MUX_VAL(CP(MCBSP3_DR),      (IEN  | PTD | DIS | M4)) /*GPIO_142*/\
++	MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_141*/
++
++#define MUX_TINCANTOOLS_TRAINER() \
++	MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
++	MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
++	MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
++	MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
++	MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
++	MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
++	MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
++	MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
++	MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
++	MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
++	MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTU | EN  | M4)) /*GPIO_140*/\
++	MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_141*/\
++	MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_162*/
++
++#define MUX_KBADC_BEAGLEFPGA() \
++	MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | DIS | M1)) /*MCSPI4_CLK*/\
++	MUX_VAL(CP(MCBSP1_DX),      (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
++	MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTU | EN  | M1)) /*MCSPI4_SOMI*/\
++	MUX_VAL(CP(MCBSP1_FSX),     (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
++
+ #endif /* _AM3517CRANE_H_ */
+diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
+index 9637e9d..f059dc7 100644
+--- a/include/configs/am3517_crane.h
++++ b/include/configs/am3517_crane.h
+@@ -162,6 +162,7 @@
+ #define CONFIG_SYS_I2C_SLAVE		1
+ #define CONFIG_SYS_I2C_BUS		0
+ #define CONFIG_SYS_I2C_BUS_SELECT	1
++#define CONFIG_I2C_MULTI_BUS           1
+ #define CONFIG_DRIVER_OMAP34XX_I2C	1
+ 
+ #define CONFIG_CMD_NET
+@@ -186,17 +187,20 @@
+ #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+ 
+ /* Environment information */
+-#define CONFIG_BOOTDELAY	10
++#define CONFIG_BOOTDELAY	1
+ 
+ #define CONFIG_BOOTFILE		uImage
+ 
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ 	"loadaddr=0x82000000\0" \
+ 	"console=ttyS2,115200n8\0" \
++	"buddy=none\0" \
+ 	"mmcargs=setenv bootargs console=${console} " \
++		"buddy=${buddy} "\
+ 		"root=/dev/mmcblk0p2 rw " \
+ 		"rootfstype=ext3 rootwait eth=${ethaddr} ip=dhcp\0" \
+ 	"nandargs=setenv bootargs console=${console} " \
++		"buddy=${buddy} "\
+ 		"root=/dev/mtdblock4 rw " \
+ 		"rootfstype=jffs2 eth=${ethaddr} ip=dhcp\0" \
+ 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+-- 
+1.6.6.1
+
diff --git a/recipes/u-boot/u-boot_git.bb b/recipes/u-boot/u-boot_git.bb
index d4dcb8d4bc..7a3a036c93 100644
--- a/recipes/u-boot/u-boot_git.bb
+++ b/recipes/u-boot/u-boot_git.bb
@@ -1,5 +1,5 @@
 require u-boot.inc
-PR ="r68"
+PR ="r69"
 
 FILESPATHPKG =. "u-boot-git:"
 
@@ -167,7 +167,11 @@ PV_dm37x-evm = "2009.11+${PR}+gitr${SRCREV}"
 # ~ TI PSP v2009.11_OMAPPSP_03.00.01.06 (+ couple of commits)
 SRC_URI_am3517-crane = "git://arago-project.org/git/projects/u-boot-omap3.git;protocol=git \
                         file://0001-Added-Support-for-AM3517-05-based-CraneBoard.patch \
+                        file://0001-OMAP2-3-I2C-Add-support-for-second-and-third-bus.patch \
+                        file://0002-ARMV7-Restructure-OMAP-i2c-driver-to-allow-code-shar.patch \
+                        file://0003-craneboard-add-expansionboard-support.patch \
 "
+
 SRCREV_am3517-crane = "c0a8fb217fdca7888d89f9a3dee74a4cec865620"
 PV_am3517-crane = "2009.11+${PR}+gitr${SRCREV}"