diff options
30 files changed, 13707 insertions, 9 deletions
diff --git a/classes/kernel-arch.bbclass b/classes/kernel-arch.bbclass index 8894fa554c..648f50d8b9 100644 --- a/classes/kernel-arch.bbclass +++ b/classes/kernel-arch.bbclass @@ -12,7 +12,7 @@ valid_archs = "alpha cris ia64 \ m32r mips \ sh sh64 um h8300 \ parisc s390 v850 \ - avr32 blackfin" + avr32 blackfin nios2" def map_kernel_arch(a, d): import re diff --git a/classes/module_strip.bbclass b/classes/module_strip.bbclass index 3316e20c80..17409190ed 100644 --- a/classes/module_strip.bbclass +++ b/classes/module_strip.bbclass @@ -2,11 +2,11 @@ do_strip_modules () { for p in ${PACKAGES}; do - if test -e ${WORKDIR}/install/$p/lib/modules; then + if test -e ${PKGDEST}/$p/lib/modules; then if [ "${KERNEL_MAJOR_VERSION}" == "2.6" ]; then - modules="`find ${WORKDIR}/install/$p/lib/modules -name \*.ko`" + modules="`find ${PKGDEST}/${p}/lib/modules -name \*.ko`" else - modules="`find ${WORKDIR}/install/$p/lib/modules -name \*.o`" + modules="`find ${PKGDEST}/${p}/lib/modules -name \*.o`" fi if [ -n "$modules" ]; then for module in $modules ; do diff --git a/conf/distro/shr.conf b/conf/distro/shr.conf index 731f194823..79c07afbe6 100644 --- a/conf/distro/shr.conf +++ b/conf/distro/shr.conf @@ -47,6 +47,7 @@ INHERIT += "angstrom" ANGSTROM_BLACKLIST_pn-bluez-libs = "bluez-libs 3.x has been replaced by bluez4" ANGSTROM_BLACKLIST_pn-bluez-utils = "bluez-utils 3.x has been replaced by bluez4" +ANGSTROM_BLACKLIST_pn-atd = "atd has been replaced by atd-over-fso" CVS_TARBALL_STASH += "http://build.shr-project.org/sources/" diff --git a/conf/machine/include/nios2.inc b/conf/machine/include/nios2.inc new file mode 100644 index 0000000000..53d76e539d --- /dev/null +++ b/conf/machine/include/nios2.inc @@ -0,0 +1,42 @@ +#@TYPE: Machine configuration +#@NAME: nios2 +#@DESCRIPTION: generic machine configuration for nios2 (non-mmu) platforms + +# Set default for common nios2-based machines +MACHINE_FEATURES ?= "kernel26 usbhost pci" +SHARED_LIBRARIES = "no" + +TARGET_LDFLAGS_append = " -Wl,-elf2flt" + +# Select an appropriate default kernel +PREFERRED_PROVIDER_virtual/kernel ?= "linux-nios2" +PREFERRED_VERSION_linux-nios2 ?= "2.6.28" + +# Select the nios2-specific toolchain parts +PREFERRED_VERSION_binutils = "nios2-2.15" +PREFERRED_VERSION_binutils-cross = "nios2-2.15" +PREFERRED_VERSION_linux-libc-headers = "nios2-2.6.28" +PREFERRED_VERSION_elf2flt-cross = "nios2-git" +PREFERRED_VERSION_gcc-cross = "nios2-3.4.6" +PREFERRED_VERSION_gcc-cross-initial = "nios2-3.4.6" +PREFERRED_VERSION_gcc-cross-intermediate = "nios2-3.4.6" +PREFERRED_VERSION_uclibc = "nios2-0.9.27" +PREFERRED_VERSION_uclibc-initial = "nios2-0.9.27" + +# Set default for 16MB machines - can be overridden for more or less flash. +ROOT_FLASH_SIZE ?= "12" + +# Allow for rootfs loaded direct from internal hard disk +IMAGE_FSTYPES ?= "jffs2 tar.gz" + +# Set default +EXTRA_IMAGECMD_jffs2 = "--pad --eraseblock=0x20000 -n" + +#------------------------------------------------------------------------------- +# Board defaults +#------------------------------------------------------------------------------- +# These values are board specific but they seem to be common to a large number +# of boards so are reasonable defaults. +SERIAL_CONSOLE = "115200 ttyS0" +KERNEL_CONSOLE = "ttyS0,115200n8" +USE_VT = "0" diff --git a/recipes/binutils/binutils-cross_nios2-2.15.bb b/recipes/binutils/binutils-cross_nios2-2.15.bb new file mode 100644 index 0000000000..b78a30ac47 --- /dev/null +++ b/recipes/binutils/binutils-cross_nios2-2.15.bb @@ -0,0 +1,4 @@ +FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/binutils-${PV}" +require binutils_${PV}.bb +require binutils-cross.inc + diff --git a/recipes/binutils/binutils_nios2-2.15.bb b/recipes/binutils/binutils_nios2-2.15.bb new file mode 100644 index 0000000000..e7886cc424 --- /dev/null +++ b/recipes/binutils/binutils_nios2-2.15.bb @@ -0,0 +1,118 @@ +DESCRIPTION = "A GNU collection of binary utilities" +HOMEPAGE = "http://www.gnu.org/software/binutils/" +SECTION = "devel" +LICENSE = "GPL" +PR = "r5" + +inherit autotools gettext + +PACKAGES = "${PN} ${PN}-dev ${PN}-doc ${PN}-symlinks" + +FILES_${PN} = " \ + ${bindir}/${TARGET_PREFIX}* \ + ${libdir}/lib*-*.so \ + ${prefix}/${TARGET_SYS}/bin/*" + +FILES_${PN}-dev = " \ + ${includedir} \ + ${libdir}/*.a \ + ${libdir}/*.la \ + ${libdir}/libbfd.so \ + ${libdir}/libopcodes.so" + +FILES_${PN}-symlinks = " \ + ${bindir}/addr2line \ + ${bindir}/ar \ + ${bindir}/as \ + ${bindir}/c++filt \ + ${bindir}/gprof \ + ${bindir}/ld \ + ${bindir}/nm \ + ${bindir}/objcopy \ + ${bindir}/objdump \ + ${bindir}/ranlib \ + ${bindir}/readelf \ + ${bindir}/size \ + ${bindir}/strings \ + ${bindir}/strip" + +#SRC_URI = "http://127.0.0.1/binutils-2.15+nios2.tbz" +#S = "${WORKDIR}/binutils" + +SRC_URI = "git://sopc.et.ntust.edu.tw/git/binutils.git;protocol=git;tag=49396897843c932623b775168c5e6e1f2a43c3c8" +S = "${WORKDIR}/git" + +B = "${S}/build.${HOST_SYS}.${TARGET_SYS}" + +EXTRA_OECONF = "--program-prefix=${TARGET_PREFIX} \ + " + +# This is necessary due to a bug in the binutils Makefiles +EXTRA_OEMAKE = "configure-build-libiberty all" + +export AR = "${HOST_PREFIX}ar" +export AS = "${HOST_PREFIX}as" +export LD = "${HOST_PREFIX}ld" +export NM = "${HOST_PREFIX}nm" +export RANLIB = "${HOST_PREFIX}ranlib" +export OBJCOPY = "${HOST_PREFIX}objcopy" +export OBJDUMP = "${HOST_PREFIX}objdump" + +export AR_FOR_TARGET = "${TARGET_PREFIX}ar" +export AS_FOR_TARGET = "${TARGET_PREFIX}as" +export LD_FOR_TARGET = "${TARGET_PREFIX}ld" +export NM_FOR_TARGET = "${TARGET_PREFIX}nm" +export RANLIB_FOR_TARGET = "${TARGET_PREFIX}ranlib" + +export CC_FOR_HOST = "${CCACHE} ${HOST_PREFIX}gcc ${HOST_CC_ARCH}" +export CXX_FOR_HOST = "${CCACHE} ${HOST_PREFIX}gcc ${HOST_CC_ARCH}" + +export CC_FOR_BUILD = "${BUILD_CC}" +export CPP_FOR_BUILD = "${BUILD_CPP}" +export CFLAGS_FOR_BUILD = "${BUILD_CFLAGS}" + +export CC = "${CCACHE} ${HOST_PREFIX}gcc ${HOST_CC_ARCH}" + +do_configure () { + (cd ${S}; gnu-configize) || die "Failed to run gnu-configize" + oe_runconf +} + +do_stage () { + oe_libinstall -so -a -C opcodes libopcodes ${STAGING_LIBDIR}/ + oe_libinstall -a -C libiberty libiberty ${STAGING_LIBDIR}/ + oe_libinstall -so -a -C bfd libbfd ${STAGING_LIBDIR}/ + install -m 0644 ${S}/include/dis-asm.h ${STAGING_INCDIR}/ + install -m 0644 ${S}/include/symcat.h ${STAGING_INCDIR}/ + install -m 0644 ${S}/include/libiberty.h ${STAGING_INCDIR}/ + install -m 0644 ${S}/include/ansidecl.h ${STAGING_INCDIR}/ + install -m 0644 ${S}/include/bfdlink.h ${STAGING_INCDIR}/ + install -m 0644 bfd/bfd.h ${STAGING_INCDIR}/ +} + +do_install () { + autotools_do_install + + # We don't really need these, so we'll remove them... + rm -rf ${D}${libdir}/ldscripts + + # Fix the /usr/${TARGET_SYS}/bin/* links + for l in ${D}${prefix}/${TARGET_SYS}/bin/*; do + rm -f $l + ln -sf `echo ${prefix}/${TARGET_SYS}/bin \ + | tr -s / \ + | sed -e 's,^/,,' -e 's,[^/]*,..,g'`${bindir}/${TARGET_PREFIX}`basename $l` $l + done + + # Install the libiberty header + install -d ${D}${includedir} + install -m 644 ${S}/include/ansidecl.h ${D}${includedir} + install -m 644 ${S}/include/libiberty.h ${D}${includedir} + + cd ${D}${bindir} + + # Symlinks for ease of running these on the native target + for p in ${TARGET_SYS}-* ; do + ln -sf $p `echo $p | sed -e s,${TARGET_SYS}-,,` + done +} diff --git a/recipes/elf2flt/elf2flt-cross_nios2-git.bb b/recipes/elf2flt/elf2flt-cross_nios2-git.bb new file mode 100644 index 0000000000..c58fe5e2fc --- /dev/null +++ b/recipes/elf2flt/elf2flt-cross_nios2-git.bb @@ -0,0 +1,15 @@ +DESCRIPTION = "Elf2flt is a wrapper around the linker for uclinux platforms" +PV = "0.1" +DEPENDS = "binutils-cross" + +inherit autotools cross + +SRC_URI = "git://sopc.et.ntust.edu.tw/git/elf2flt.git;protocol=git;branch=nios2;tag=7f2f6c6b107fb18b6b6d3692b273a00315948da4" + +S = "${WORKDIR}/git" + +EXTRA_OECONF = " --with-libbfd=/home/walter//nios2-linux/toolchain-build/build/binutils-build/bfd/libbfd.a \ + --with-libiberty=/home/walter/nios2-linux/toolchain-build/build/binutils-build/libiberty/libiberty.a \ + --with-bfd-include-dir=${STAGING_INCDIR} \ + --disable-emit-relocs \ + " diff --git a/recipes/ffalarms/atd-over-fso_0.70.bb b/recipes/ffalarms/atd-over-fso_0.70.bb index 951e10c66d..b042a0356a 100644 --- a/recipes/ffalarms/atd-over-fso_0.70.bb +++ b/recipes/ffalarms/atd-over-fso_0.70.bb @@ -1,9 +1,9 @@ DESCRIPTION = "Lightweight At Daemon working on top of org.freesmartphone.otimed" SECTION = "base" LICENSE = "GPLV2" -RCONFLICTS = "at atd" -RREPLACES = "at atd" -RPROVIDES = "atd" +RCONFLICTS_${PN} = "at atd" +RREPLACES_${PN} = "at atd" +RPROVIDES_${PN} = "atd" DEPENDS = "dbus-glib pkgconfig" RDEPENDS += "dbus dbus-glib frameworkd" diff --git a/recipes/gcc/gcc-cross-initial_nios2-3.4.6.bb b/recipes/gcc/gcc-cross-initial_nios2-3.4.6.bb new file mode 100644 index 0000000000..1639511362 --- /dev/null +++ b/recipes/gcc/gcc-cross-initial_nios2-3.4.6.bb @@ -0,0 +1,2 @@ +require gcc-cross_${PV}.bb +require gcc-cross-initial.inc diff --git a/recipes/gcc/gcc-cross-intermediate_nios2-3.4.6.bb b/recipes/gcc/gcc-cross-intermediate_nios2-3.4.6.bb new file mode 100644 index 0000000000..eb59de9461 --- /dev/null +++ b/recipes/gcc/gcc-cross-intermediate_nios2-3.4.6.bb @@ -0,0 +1,2 @@ +require gcc-cross_${PV}.bb +require gcc-cross-intermediate.inc diff --git a/recipes/gcc/gcc-cross_nios2-3.4.6.bb b/recipes/gcc/gcc-cross_nios2-3.4.6.bb new file mode 100644 index 0000000000..873b85f349 --- /dev/null +++ b/recipes/gcc/gcc-cross_nios2-3.4.6.bb @@ -0,0 +1,6 @@ +PR = "r13" + +require gcc_nios2-3.4.6.inc +require gcc-cross.inc +require gcc-configure-cross.inc +require gcc-package-cross.inc diff --git a/recipes/gcc/gcc_nios2-3.4.6.inc b/recipes/gcc/gcc_nios2-3.4.6.inc new file mode 100644 index 0000000000..c48e652828 --- /dev/null +++ b/recipes/gcc/gcc_nios2-3.4.6.inc @@ -0,0 +1,13 @@ +JAVA = "" +FORTRAN = "" +OBJC = "" +SHARED_LIBRARIES = "no" +DEPENDS += " elf2flt-cross " +EXTRA_OECONF_append_nios2 = " --enable-cxx-flags=-static " +require gcc-common.inc + +BINV = "3.4.6" +PV = "nios2-3.4.6" + +SRC_URI = "git://sopc.et.ntust.edu.tw/git/gcc3.git;protocol=git;branch=nios2-linux;tag=b773f7eccc6cc2ffa8fa2bd201ea62f24ba0bb41" +S = "${WORKDIR}/git" diff --git a/recipes/gnu-config/gnu-config/nios2.patch b/recipes/gnu-config/gnu-config/nios2.patch new file mode 100644 index 0000000000..d790ed19c4 --- /dev/null +++ b/recipes/gnu-config/gnu-config/nios2.patch @@ -0,0 +1,20 @@ +Index: config/config.sub +=================================================================== +--- config.orig/config.sub ++++ config/config.sub +@@ -259,6 +259,7 @@ case $basic_machine in + | mn10200 | mn10300 \ + | ms1 \ + | msp430 \ ++ | nios2 | nios2eb | nios2el \ + | ns16k | ns32k \ + | openrisc | or32 \ + | pdp10 | pdp11 | pj | pjl \ +@@ -338,6 +339,7 @@ case $basic_machine in + | mmix-* \ + | ms1-* \ + | msp430-* \ ++ | nios2-* | nios2eb-* | nios2el-* \ + | none-* | np1-* | ns16k-* | ns32k-* \ + | orion-* \ + | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ diff --git a/recipes/gnu-config/gnu-config_20050701.bb b/recipes/gnu-config/gnu-config_20050701.bb index 8ee0a32120..537d745644 100644 --- a/recipes/gnu-config/gnu-config_20050701.bb +++ b/recipes/gnu-config/gnu-config_20050701.bb @@ -6,11 +6,12 @@ INHIBIT_DEFAULT_DEPS = "1" FIXEDSRCDATE = "${@bb.data.getVar('FILE', d, 1).split('_')[-1].split('.')[0]}" PV = "0.1+cvs${FIXEDSRCDATE}" -PR = "r5" +PR = "r6" SRC_URI = "cvs://anonymous@cvs.sv.gnu.org/cvsroot/config;module=config;method=pserver;date=${FIXEDSRCDATE} \ file://config-guess-uclibc.patch;patch=1 \ file://avr32.patch;patch=1 \ + file://nios2.patch;patch=1 \ file://gnu-configize.in" S = "${WORKDIR}/config" diff --git a/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/procinfo.h b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/procinfo.h new file mode 100644 index 0000000000..8cdf828af8 --- /dev/null +++ b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/procinfo.h @@ -0,0 +1,24 @@ +/* + * linux/include/asm-arm/procinfo.h + * + * Copyright (C) 1996-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROCINFO_H +#define __ASM_PROCINFO_H + +#define HWCAP_SWP 1 +#define HWCAP_HALF 2 +#define HWCAP_THUMB 4 +#define HWCAP_26BIT 8 /* Play it safe */ +#define HWCAP_FAST_MULT 16 +#define HWCAP_FPA 32 +#define HWCAP_VFP 64 +#define HWCAP_EDSP 128 +#define HWCAP_JAVA 256 +#define HWCAP_IWMMXT 512 +#define HWCAP_CRUNCH 1024 +#endif diff --git a/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/system.ptf b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/system.ptf new file mode 100755 index 0000000000..8194067629 --- /dev/null +++ b/recipes/linux-libc-headers/linux-libc-headers-nios2-2.6.28/system.ptf @@ -0,0 +1,3492 @@ +SYSTEM NIOS +{ + System_Wizard_Version = "9.00"; + System_Wizard_Build = "132"; + # + # Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF + # Date: 2009.07.08.11:10:21 + # + # clock_source "clk" + # altera_nios2 "cpu" + # altera_avalon_new_sdram_controller "ext_sdram" + # altera_avalon_timer "timer" + # altera_avalon_sysid "sysid" + # altera_avalon_tri_state_bridge "tristate_bridge" + # altera_avalon_cfi_flash "cfi_flash" + # clock_source "clk_half" + # altera_avalon_remote_update_cycloneiii "cycloneiii" + # altera_nios_custom_instr_floating_point "cpu_fpoint" + # fifoed_avalon_uart_classic "UART_backplane" + # fifoed_avalon_uart_classic "UART_daughter" + # fifoed_avalon_uart_classic "axonbus" + # opencores_i2c_master "I2C_local" + # + # Contains 31 connections. + # + Builder_Application = "sopc_builder_ca"; + #. values for Builder_Application are: + #. sopc_builder_preview --> 6.1p, 7.0p prerelease versions + #. sopc_builder_ca --> 7.1 and later + #. (missing) --> 6.0 or earlier + WIZARD_SCRIPT_ARGUMENTS + { + hdl_language = "vhdl"; + device_family = "CYCLONEIII"; + device_family_id = "CYCLONEIII"; + generate_sdk = "0"; + do_build_sim = "0"; + hardcopy_compatible = "0"; + CLOCKS + { + CLOCK clk + { + frequency = "66660000"; + source = "External"; + Is_Clock_Source = "0"; + display_name = "clk"; + pipeline = "0"; + clock_module_connection_point_for_c2h = "clk.clk"; + } + CLOCK clk_half + { + frequency = "33330000"; + source = "External"; + Is_Clock_Source = "0"; + display_name = "clk_half"; + pipeline = "0"; + clock_module_connection_point_for_c2h = "clk_half.clk"; + } + } + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + clock_freq = "66660000"; + board_class = ""; + view_master_columns = "1"; + view_master_priorities = "0"; + generate_hdl = ""; + bustype_column_width = "0"; + clock_column_width = "80"; + name_column_width = "75"; + desc_column_width = "75"; + base_column_width = "75"; + end_column_width = "75"; + BOARD_INFO + { + altera_avalon_cfi_flash + { + reference_designators = ""; + } + } + } + MODULE cpu + { + MASTER instruction_master + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT i_address + { + type = "address"; + width = "28"; + direction = "output"; + Is_Enabled = "1"; + } + PORT i_read + { + type = "read"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT i_readdata + { + type = "readdata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT i_readdatavalid + { + type = "readdatavalid"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT i_waitrequest + { + type = "waitrequest"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Is_Asynchronous = "0"; + DBS_Big_Endian = "0"; + Adapts_To = ""; + Do_Stream_Reads = "0"; + Do_Stream_Writes = "0"; + Max_Address_Width = "32"; + Data_Width = "32"; + Address_Width = "28"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = ""; + Linewrap_Bursts = ""; + Burst_On_Burst_Boundaries_Only = ""; + Always_Burst_Max_Burst = ""; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Is_Instruction_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "0"; + Address_Group = "0"; + Has_IRQ = "0"; + Irq_Scheme = "individual_requests"; + Interrupt_Range = "0-0"; + } + MEMORY_MAP + { + Entry cpu/jtag_debug_module + { + address = "0x08000800"; + span = "0x00000800"; + is_bridge = "0"; + } + Entry ext_sdram/s1 + { + address = "0x00000000"; + span = "0x04000000"; + is_bridge = "0"; + } + Entry cfi_flash/s1 + { + address = "0x04000000"; + span = "0x02000000"; + is_bridge = "0"; + } + } + } + MASTER custom_instruction_master + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "nios_custom_instruction"; + Data_Width = "32"; + Address_Width = "8"; + Is_Custom_Instruction = "1"; + Is_Enabled = "1"; + Max_Address_Width = "8"; + Base_Address = "N/A"; + Is_Visible = "0"; + } + PORT_WIRING + { + PORT dataa + { + type = "dataa"; + width = "32"; + direction = "output"; + } + PORT datab + { + type = "datab"; + width = "32"; + direction = "output"; + } + PORT result + { + type = "result"; + width = "32"; + direction = "input"; + } + PORT clk_en + { + type = "clk_en"; + width = "1"; + direction = "output"; + } + PORT reset + { + type = "reset"; + width = "1"; + direction = "output"; + } + PORT start + { + type = "start"; + width = "1"; + direction = "output"; + } + PORT done + { + type = "done"; + width = "1"; + direction = "input"; + } + PORT n + { + type = "n"; + width = "8"; + direction = "output"; + } + PORT a + { + type = "a"; + width = "5"; + direction = "output"; + } + PORT b + { + type = "b"; + width = "5"; + direction = "output"; + } + PORT c + { + type = "c"; + width = "5"; + direction = "output"; + } + PORT readra + { + type = "readra"; + width = "1"; + direction = "output"; + } + PORT readrb + { + type = "readrb"; + width = "1"; + direction = "output"; + } + PORT writerc + { + type = "writerc"; + width = "1"; + direction = "output"; + } + } + } + SLAVE jtag_debug_module + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "dynamic"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Address_Span = "2048"; + Read_Latency = "0"; + Is_Memory_Device = "1"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "32"; + Address_Width = "9"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Accepts_External_Connections = "1"; + Requires_Internal_Connections = ""; + MASTERED_BY cpu/instruction_master + { + priority = "1"; + Offset_Address = "0x08000800"; + } + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x08000800"; + } + Base_Address = "0x08000800"; + Is_Readable = "1"; + Is_Writeable = "1"; + Uses_Tri_State_Data_Bus = "0"; + Has_IRQ = "0"; + JTAG_Hub_Base_Id = "1118278"; + JTAG_Hub_Instance_Id = "0"; + Address_Group = "0"; + IRQ_MASTER cpu/data_master + { + IRQ_Number = "NC"; + } + } + PORT_WIRING + { + PORT jtag_debug_module_address + { + type = "address"; + width = "9"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_begintransfer + { + type = "begintransfer"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_byteenable + { + type = "byteenable"; + width = "4"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_debugaccess + { + type = "debugaccess"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_readdata + { + type = "readdata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_resetrequest + { + type = "resetrequest"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_select + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_writedata + { + type = "writedata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + } + } + MASTER data_master + { + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Irq_Scheme = "individual_requests"; + Bus_Type = "avalon"; + Is_Asynchronous = "0"; + DBS_Big_Endian = "0"; + Adapts_To = ""; + Do_Stream_Reads = "0"; + Do_Stream_Writes = "0"; + Max_Address_Width = "32"; + Data_Width = "32"; + Address_Width = "28"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = ""; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Is_Data_Master = "1"; + Address_Group = "0"; + Is_Readable = "1"; + Is_Writeable = "1"; + Interrupt_Range = "0-31"; + } + PORT_WIRING + { + PORT d_irq + { + type = "irq"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT d_address + { + type = "address"; + width = "28"; + direction = "output"; + Is_Enabled = "1"; + } + PORT d_byteenable + { + type = "byteenable"; + width = "4"; + direction = "output"; + Is_Enabled = "1"; + } + PORT d_read + { + type = "read"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT d_readdata + { + type = "readdata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT d_readdatavalid + { + type = "readdatavalid"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT d_waitrequest + { + type = "waitrequest"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT d_write + { + type = "write"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT d_writedata + { + type = "writedata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_debugaccess_to_roms + { + type = "debugaccess"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + MEMORY_MAP + { + Entry cpu/jtag_debug_module + { + address = "0x08000800"; + span = "0x00000800"; + is_bridge = "0"; + } + Entry ext_sdram/s1 + { + address = "0x00000000"; + span = "0x04000000"; + is_bridge = "0"; + } + Entry timer/s1 + { + address = "0x08000000"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry cfi_flash/s1 + { + address = "0x04000000"; + span = "0x02000000"; + is_bridge = "0"; + } + Entry sysid/control_slave + { + address = "0x07000020"; + span = "0x00000008"; + is_bridge = "0"; + } + Entry cycloneiii/s1 + { + address = "0x07010000"; + span = "0x00000100"; + is_bridge = "0"; + } + Entry UART_backplane/s1 + { + address = "0x07001160"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry UART_daughter/s1 + { + address = "0x070011a0"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry axonbus/s1 + { + address = "0x07001140"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry I2C_local/s1 + { + address = "0x07001100"; + span = "0x00000020"; + is_bridge = "0"; + } + } + } + WIZARD_SCRIPT_ARGUMENTS + { + cache_has_dcache = "1"; + cache_dcache_size = "2048"; + cache_dcache_line_size = "32"; + cache_dcache_bursts = "0"; + cache_dcache_ram_block_type = "AUTO"; + num_tightly_coupled_data_masters = "0"; + gui_num_tightly_coupled_data_masters = "0"; + gui_include_tightly_coupled_data_masters = "0"; + gui_omit_avalon_data_master = "0"; + cache_has_icache = "1"; + cache_icache_size = "4096"; + cache_icache_line_size = "32"; + cache_icache_ram_block_type = "AUTO"; + cache_icache_bursts = "0"; + num_tightly_coupled_instruction_masters = "0"; + gui_num_tightly_coupled_instruction_masters = "0"; + gui_include_tightly_coupled_instruction_masters = "0"; + debug_level = "2"; + include_oci = "1"; + oci_num_xbrk = "0"; + oci_num_dbrk = "0"; + oci_dbrk_trace = "0"; + oci_dbrk_pairs = "0"; + oci_onchip_trace = "0"; + oci_offchip_trace = "0"; + oci_data_trace = "0"; + include_third_party_debug_port = "0"; + oci_trace_addr_width = "7"; + oci_debugreq_signals = "0"; + oci_trigger_arming = "1"; + oci_embedded_pll = "0"; + oci_assign_jtag_instance_id = "0"; + oci_jtag_instance_id = "0"; + oci_num_pm = "0"; + oci_pm_width = "32"; + performance_counters_present = "0"; + performance_counters_width = "32"; + always_encrypt = "1"; + debug_simgen = "0"; + activate_model_checker = "0"; + activate_test_end_checker = "0"; + activate_trace = "1"; + activate_monitors = "1"; + clear_x_bits_ld_non_bypass = "1"; + bit_31_bypass_dcache = "1"; + hdl_sim_caches_cleared = "1"; + hbreak_test = "0"; + allow_full_address_range = "0"; + extra_exc_info = "0"; + branch_prediction_type = "Dynamic"; + bht_ptr_sz = "8"; + bht_index_pc_only = "0"; + gui_branch_prediction_type = "Automatic"; + full_waveform_signals = "0"; + export_pcb = "0"; + avalon_debug_port_present = "0"; + illegal_instructions_trap = "0"; + illegal_memory_access_detection = "0"; + illegal_mem_exc = "0"; + slave_access_error_exc = "0"; + division_error_exc = "0"; + eic_present = "0"; + num_shadow_reg_sets = "0"; + gui_mmu_present = "0"; + mmu_present = "0"; + process_id_num_bits = "8"; + tlb_ptr_sz = "7"; + tlb_num_ways = "16"; + udtlb_num_entries = "6"; + uitlb_num_entries = "4"; + fast_tlb_miss_exc_slave = ""; + fast_tlb_miss_exc_offset = "0x00000000"; + mpu_present = "0"; + mpu_num_data_regions = "8"; + mpu_num_inst_regions = "8"; + mpu_min_data_region_size_log2 = "12"; + mpu_min_inst_region_size_log2 = "12"; + mpu_use_limit = "0"; + hardware_divide_present = "0"; + gui_hardware_divide_setting = "0"; + hardware_multiply_present = "1"; + hardware_multiply_impl = "embedded_mul"; + shift_rot_impl = "fast_le_shift"; + gui_hardware_multiply_setting = "embedded_mul_fast_le_shift"; + reset_slave = "cfi_flash/s1"; + break_slave = "cpu/jtag_debug_module"; + exc_slave = "ext_sdram/s1"; + reset_offset = "0x00400000"; + break_offset = "0x00000020"; + exc_offset = "0x00000020"; + cpu_reset = "0"; + CPU_Implementation = "fast"; + cpu_selection = "f"; + device_family_id = "CYCLONEIII"; + address_stall_present = "1"; + dsp_block_supports_shift = "0"; + mrams_present = "0"; + cpuid_value = "0"; + dont_overwrite_cpuid = "1"; + allow_legacy_sdk = "1"; + legacy_sdk_support = "1"; + inst_addr_width = "28"; + data_addr_width = "28"; + CPU_Architecture = "nios2"; + cache_icache_burst_type = "none"; + oci_sync_depth = "2"; + hardware_multiply_omits_msw = "1"; + big_endian = "0"; + break_slave_override = ""; + break_offset_override = "0x20"; + altera_show_unreleased_features = "0"; + altera_show_unpublished_features = "0"; + altera_internal_test = "0"; + alt_log_port_base = ""; + alt_log_port_type = ""; + cpuid_sz = "1"; + gui_illegal_instructions_trap = "0"; + advanced_exc = "0"; + gui_illegal_memory_access_detection = "0"; + cache_omit_dcache = "0"; + cache_omit_icache = "0"; + omit_instruction_master = "0"; + omit_data_master = "0"; + ras_ptr_sz = "4"; + jtb_ptr_sz = "5"; + ibuf_ptr_sz = "4"; + always_bypass_dcache = "0"; + iss_trace_on = "0"; + iss_trace_warning = "1"; + iss_trace_info = "1"; + iss_trace_disassembly = "0"; + iss_trace_registers = "0"; + iss_trace_instr_count = "0"; + iss_software_debug = "0"; + iss_software_debug_port = "9996"; + iss_memory_dump_start = ""; + iss_memory_dump_end = ""; + Boot_Copier = "boot_loader_cfi.srec"; + Boot_Copier_EPCS = "boot_loader_epcs.srec"; + Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec"; + Boot_Copier_BE = "boot_loader_cfi_be.srec"; + Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec"; + Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec"; + CONSTANTS + { + CONSTANT __nios_catch_irqs__ + { + value = "1"; + comment = "Include panic handler for all irqs (needs uart)"; + } + CONSTANT __nios_use_constructors__ + { + value = "1"; + comment = "Call c++ static constructors"; + } + CONSTANT __nios_use_small_printf__ + { + value = "1"; + comment = "Smaller non-ANSI printf, with no floating point"; + } + CONSTANT nasys_has_icache + { + value = "1"; + comment = "True if instruction cache present"; + } + CONSTANT nasys_icache_size + { + value = "4096"; + comment = "Size in bytes of instruction cache"; + } + CONSTANT nasys_icache_line_size + { + value = "32"; + comment = "Size in bytes of each icache line"; + } + CONSTANT nasys_icache_line_size_log2 + { + value = "5"; + comment = "Log2 size in bytes of each icache line"; + } + CONSTANT nasys_has_dcache + { + value = "1"; + comment = "True if instruction cache present"; + } + CONSTANT nasys_dcache_size + { + value = "2048"; + comment = "Size in bytes of data cache"; + } + CONSTANT nasys_dcache_line_size + { + value = "32"; + comment = "Size in bytes of each dcache line"; + } + CONSTANT nasys_dcache_line_size_log2 + { + value = "5"; + comment = "Log2 size in bytes of each dcache line"; + } + } + license_status = ""; + mainmem_slave = "cfi_flash/s1"; + datamem_slave = "cfi_flash/s1"; + maincomm_slave = "axonbus/s1"; + germs_monitor_id = ""; + } + class = "altera_nios2"; + class_version = "7.080900"; + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + Parameters_Signature = ""; + Is_CPU = "1"; + Instantiate_In_System_Module = "1"; + Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII,HARDCOPYIII,ARRIAII,TARPON,HARDCOPYIV"; + Default_Module_Name = "cpu"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + Settings_Summary = "Nios II/f + <br> 4-Kbyte Instruction Cache + <br> 2-Kbyte Data Cache + <br> JTAG Debug Module + "; + MESSAGES + { + } + } + } + iss_model_name = "altera_nios2"; + HDL_INFO + { + # The list of files associated with this module (for synthesis + # and other purposes) depends on the users' wizard-choices. + # This section will be filled-in by the Generator_Program + # after the module logic has been created and the + # various filenames are known. + } + MASTER tightly_coupled_instruction_master_0 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Is_Instruction_Master = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_instruction_master_1 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Instruction_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "0"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_instruction_master_2 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Instruction_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "0"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_instruction_master_3 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Instruction_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "0"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER data_master2 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "1"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + } + } + MASTER tightly_coupled_data_master_0 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_data_master_1 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_data_master_2 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_data_master_3 + { + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program after + # the module logic has been created and the ports are known. + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + PORT_WIRING + { + PORT jtag_debug_trigout + { + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT jtag_debug_offchip_trace_clk + { + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT jtag_debug_offchip_trace_data + { + width = "18"; + direction = "output"; + Is_Enabled = "0"; + } + PORT clkx2 + { + width = "1"; + direction = "input"; + Is_Enabled = "0"; + visible = "0"; + } + } + } + MODULE ext_sdram + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT az_addr + { + type = "address"; + width = "24"; + direction = "input"; + Is_Enabled = "1"; + } + PORT az_be_n + { + type = "byteenable_n"; + width = "4"; + direction = "input"; + Is_Enabled = "1"; + } + PORT az_cs + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT az_data + { + type = "writedata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT az_rd_n + { + type = "read_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT az_wr_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT za_data + { + type = "readdata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + PORT za_valid + { + type = "readdatavalid"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT za_waitrequest + { + type = "waitrequest"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT zs_addr + { + direction = "output"; + width = "13"; + Is_Enabled = "0"; + } + PORT zs_ba + { + direction = "output"; + width = "2"; + Is_Enabled = "0"; + } + PORT zs_cas_n + { + direction = "output"; + width = "1"; + Is_Enabled = "0"; + } + PORT zs_cke + { + direction = "output"; + width = "1"; + Is_Enabled = "0"; + } + PORT zs_cs_n + { + direction = "output"; + width = "1"; + Is_Enabled = "0"; + } + PORT zs_dq + { + direction = "inout"; + width = "32"; + Is_Enabled = "0"; + } + PORT zs_dqm + { + direction = "output"; + width = "4"; + Is_Enabled = "0"; + } + PORT zs_ras_n + { + direction = "output"; + width = "1"; + Is_Enabled = "0"; + } + PORT zs_we_n + { + direction = "output"; + width = "1"; + Is_Enabled = "0"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Read_Wait_States = "peripheral_controlled"; + Write_Wait_States = "peripheral_controlled"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "dynamic"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Address_Span = "67108864"; + Read_Latency = "0"; + Is_Memory_Device = "1"; + Maximum_Pending_Read_Transactions = "9"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "32"; + Address_Width = "24"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/instruction_master + { + priority = "1"; + Offset_Address = "0x00000000"; + } + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x00000000"; + } + Base_Address = "0x00000000"; + Has_IRQ = "0"; + Simulation_Num_Lanes = "1"; + Address_Group = "0"; + IRQ_MASTER cpu/data_master + { + IRQ_Number = "NC"; + } + } + } + iss_model_name = "altera_memory"; + WIZARD_SCRIPT_ARGUMENTS + { + register_data_in = "1"; + sim_model_base = "0"; + sdram_data_width = "32"; + sdram_addr_width = "13"; + sdram_row_width = "13"; + sdram_col_width = "9"; + sdram_num_chipselects = "1"; + sdram_num_banks = "4"; + refresh_period = "15.625"; + powerup_delay = "200.0"; + cas_latency = "3"; + t_rfc = "70.0"; + t_rp = "20.0"; + t_mrd = "3"; + t_rcd = "20.0"; + t_ac = "5.5"; + t_wr = "14.0"; + init_refresh_commands = "2"; + init_nop_delay = "0.0"; + shared_data = "1"; + sdram_bank_width = "2"; + tristate_bridge_slave = "tristate_bridge/avalon_slave"; + starvation_indicator = "0"; + is_initialized = "1"; + } + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = "az_addr"; + radix = "hexadecimal"; + } + SIGNAL b + { + name = "az_be_n"; + radix = "hexadecimal"; + } + SIGNAL c + { + name = "az_cs"; + } + SIGNAL d + { + name = "az_data"; + radix = "hexadecimal"; + } + SIGNAL e + { + name = "az_rd_n"; + } + SIGNAL f + { + name = "az_wr_n"; + } + SIGNAL h + { + name = "za_data"; + radix = "hexadecimal"; + } + SIGNAL i + { + name = "za_valid"; + } + SIGNAL j + { + name = "za_waitrequest"; + } + SIGNAL l + { + name = "CODE"; + radix = "ascii"; + } + SIGNAL g + { + name = "clk"; + } + SIGNAL k + { + name = "za_cannotrefresh"; + suppress = "1"; + } + SIGNAL m + { + name = "zs_addr"; + radix = "hexadecimal"; + suppress = "1"; + } + SIGNAL n + { + name = "zs_ba"; + radix = "hexadecimal"; + suppress = "1"; + } + SIGNAL o + { + name = "zs_cs_n"; + radix = "hexadecimal"; + suppress = "1"; + } + SIGNAL p + { + name = "zs_ras_n"; + suppress = "1"; + } + SIGNAL q + { + name = "zs_cas_n"; + suppress = "1"; + } + SIGNAL r + { + name = "zs_we_n"; + suppress = "1"; + } + SIGNAL s + { + name = "zs_dq"; + radix = "hexadecimal"; + suppress = "1"; + } + SIGNAL t + { + name = "zs_dqm"; + radix = "hexadecimal"; + suppress = "1"; + } + SIGNAL u + { + name = "zt_addr"; + radix = "hexadecimal"; + suppress = "0"; + } + SIGNAL v + { + name = "zt_ba"; + radix = "hexadecimal"; + suppress = "0"; + } + SIGNAL w + { + name = "zt_oe"; + suppress = "0"; + } + SIGNAL x + { + name = "zt_cke"; + suppress = "0"; + } + SIGNAL y + { + name = "zt_chipselect"; + suppress = "0"; + } + SIGNAL z0 + { + name = "zt_lock_n"; + suppress = "0"; + } + SIGNAL z1 + { + name = "zt_ras_n"; + suppress = "0"; + } + SIGNAL z2 + { + name = "zt_cas_n"; + suppress = "0"; + } + SIGNAL z3 + { + name = "zt_we_n"; + suppress = "0"; + } + SIGNAL z4 + { + name = "zt_cs_n"; + radix = "hexadecimal"; + suppress = "0"; + } + SIGNAL z5 + { + name = "zt_dqm"; + radix = "hexadecimal"; + suppress = "0"; + } + SIGNAL z6 + { + name = "zt_data"; + radix = "hexadecimal"; + suppress = "0"; + } + SIGNAL z7 + { + name = "tz_data"; + radix = "hexadecimal"; + suppress = "0"; + } + SIGNAL z8 + { + name = "tz_waitrequest"; + suppress = "0"; + } + } + Fix_Me_Up = ""; + } + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + Default_Module_Name = "sdram"; + Top_Level_Ports_Are_Enumerated = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + Disable_Simulation_Port_Wiring = "1"; + View + { + MESSAGES + { + } + Settings_Summary = "16777216 x 32<br> + Memory size: 64 MBytes<br> + 512 MBits + <br>Sharing Pins Via Tristate Bridge"; + } + } + class = "altera_avalon_new_sdram_controller"; + class_version = "7.080900"; + } + MODULE timer + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "16"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x08000000"; + } + IRQ_MASTER cpu/data_master + { + IRQ_Number = "6"; + } + Base_Address = "0x08000000"; + Address_Group = "0"; + } + } + class = "altera_avalon_timer"; + class_version = "7.080900"; + iss_model_name = "altera_avalon_timer"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + Settings_Summary = "Timer with 1 ms timeout period."; + Is_Collapsed = "1"; + MESSAGES + { + } + } + Clock_Source = "clk"; + Has_Clock = "1"; + } + WIZARD_SCRIPT_ARGUMENTS + { + always_run = "0"; + fixed_period = "0"; + snapshot = "1"; + period = "1"; + period_units = "ms"; + reset_output = "0"; + timeout_pulse_output = "0"; + load_value = "66659"; + counter_size = "32"; + mult = "0.0010"; + ticks_per_sec = "1000"; + } + } + MODULE sysid + { + SLAVE control_slave + { + PORT_WIRING + { + PORT clock + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "32"; + Address_Width = "1"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x07000020"; + } + Base_Address = "0x07000020"; + Has_IRQ = "0"; + Address_Group = "0"; + IRQ_MASTER cpu/data_master + { + IRQ_Number = "NC"; + } + } + } + class = "altera_avalon_sysid"; + class_version = "7.080900"; + SYSTEM_BUILDER_INFO + { + Date_Modified = ""; + Is_Enabled = "1"; + Instantiate_In_System_Module = "1"; + Fixed_Module_Name = "sysid"; + Top_Level_Ports_Are_Enumerated = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + View + { + Settings_Summary = "No system ID yet. <br> + A unique ID is assigned every time <br> + the system is generated."; + MESSAGES + { + } + } + } + WIZARD_SCRIPT_ARGUMENTS + { + id = "1371320681"; + timestamp = "1247051407"; + regenerate_values = "0"; + } + HDL_INFO + { + # The list of files associated with this module (for synthesis + # and other purposes) depends on the users' wizard-choices. + # This section will be filled-in by the Generator_Program + # after the module logic has been created and the + # various filenames are known. + } + PORT_WIRING + { + # The number and kind of ports that appear on this module + # depends on the user's wizard-choices. + # This section will be filled-in by the Generator_Program + # after the module logic has been created and the ports are known. + # + } + } + MODULE tristate_bridge + { + SLAVE avalon_slave + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "dynamic"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Address_Span = "1"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "1"; + Register_Outgoing_Signals = "1"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/instruction_master + { + priority = "1"; + Offset_Address = "N/A"; + Base_Address = "N/A"; + } + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "N/A"; + Base_Address = "N/A"; + } + Bridges_To = "tristate_master"; + Base_Address = "N/A"; + Has_IRQ = "0"; + IRQ = "N/A"; + Address_Group = "0"; + IRQ_MASTER cpu/data_master + { + IRQ_Number = "NC"; + } + } + } + MASTER tristate_master + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon_tristate"; + Is_Asynchronous = "0"; + DBS_Big_Endian = "0"; + Adapts_To = ""; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Bridges_To = "avalon_slave"; + } + PORT_WIRING + { + } + MEMORY_MAP + { + Entry cfi_flash/s1 + { + address = "0x04000000"; + span = "0x02000000"; + is_bridge = "0"; + } + } + } + WIZARD_SCRIPT_ARGUMENTS + { + } + class = "altera_avalon_tri_state_bridge"; + class_version = "7.080900"; + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "1"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + MESSAGES + { + } + } + } + } + MODULE cfi_flash + { + SLAVE s1 + { + PORT_WIRING + { + PORT data + { + type = "data"; + width = "16"; + direction = "inout"; + Is_Enabled = "1"; + is_shared = "1"; + } + PORT address + { + type = "address"; + width = "24"; + direction = "input"; + Is_Enabled = "1"; + is_shared = "1"; + } + PORT read_n + { + type = "read_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + is_shared = "0"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + is_shared = "0"; + } + PORT select_n + { + type = "chipselect_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + is_shared = "0"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon_tristate"; + Write_Wait_States = "100ns"; + Read_Wait_States = "100ns"; + Hold_Time = "20ns"; + Setup_Time = "25ns"; + Is_Printable_Device = "0"; + Address_Alignment = "dynamic"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "1"; + Address_Span = "33554432"; + Read_Latency = "0"; + Is_Memory_Device = "1"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "1"; + Active_CS_Through_Read_Latency = "0"; + Data_Width = "16"; + Address_Width = "24"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY tristate_bridge/tristate_master + { + priority = "1"; + Offset_Address = "0x04000000"; + } + Base_Address = "0x04000000"; + Has_IRQ = "0"; + Simulation_Num_Lanes = "1"; + Convert_Xs_To_0 = "1"; + Address_Group = "0"; + IRQ_MASTER cpu/data_master + { + IRQ_Number = "NC"; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + class = "altera_avalon_cfi_flash"; + Supports_Flash_File_System = "1"; + flash_reference_designator = ""; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + Setup_Value = "25"; + Wait_Value = "100"; + Hold_Value = "20"; + Timing_Units = "ns"; + Unit_Multiplier = "1"; + Size = "33554432"; + } + SYSTEM_BUILDER_INFO + { + Simulation_Num_Lanes = "2"; + Is_Enabled = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + Make_Memory_Model = "1"; + Instantiate_In_System_Module = "0"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + MESSAGES + { + } + } + } + class = "altera_avalon_cfi_flash"; + class_version = "7.080900"; + iss_model_name = "altera_avalon_flash"; + HDL_INFO + { + } + } + MODULE cycloneiii + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset + { + type = "reset"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "6"; + direction = "input"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT read + { + type = "read"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT waitrequest + { + type = "waitrequest"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Read_Wait_States = "peripheral_controlled"; + Write_Wait_States = "peripheral_controlled"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "2"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "32"; + Address_Width = "6"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x07010000"; + ADAPTER_MASTER NIOS_clock_0/out + { + priority = "1"; + } + } + Base_Address = "0x07010000"; + Address_Group = "0"; + IRQ_MASTER cpu/data_master + { + IRQ_Number = "NC"; + } + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "altera_avalon_remote_update_cycloneiii"; + gtf_class_version = "9.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_half"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "/home/walter/VHDL/SYGEG1-080630/VHDL/Quartus_Altera/Prj/cycloneiii.vho"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE cpu_fpoint + { + SLAVE s1 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "nios_custom_instruction"; + Data_Width = "32"; + Address_Width = "2"; + Is_Custom_Instruction = "1"; + Is_Enabled = "1"; + ci_operands = "2"; + ci_cycles = "1"; + ci_inst_type = "variable multicycle"; + Has_Base_Address = "1"; + Base_Address = "0x000000fc"; + ci_macro_name = "fpoint"; + MASTERED_BY cpu/custom_instruction_master + { + priority = "1"; + } + IRQ_MASTER cpu/custom_instruction_master + { + IRQ_Number = "NC"; + } + Is_Base_Locked = "1"; + Is_Visible = "0"; + Address_Group = "0"; + } + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + } + PORT clk_en + { + type = "clk_en"; + width = "1"; + direction = "input"; + } + PORT reset + { + type = "reset"; + width = "1"; + direction = "input"; + } + PORT start + { + type = "start"; + width = "1"; + direction = "input"; + } + PORT n + { + type = "n"; + width = "2"; + direction = "input"; + } + PORT dataa + { + type = "dataa"; + width = "32"; + direction = "input"; + } + PORT datab + { + type = "datab"; + width = "32"; + direction = "input"; + } + PORT result + { + type = "result"; + width = "32"; + direction = "output"; + } + PORT done + { + type = "done"; + width = "1"; + direction = "output"; + } + } + } + WIZARD_SCRIPT_ARGUMENTS + { + Use_Divider = "0"; + ci_macro_name = "fpoint"; + ci_cycles = "1"; + ci_instr_format = "RR"; + ci_has_prefix = "0"; + ci_inst_type = "variable multicycle"; + ci_operands = "2"; + Precision = "1"; + Reduced_Operation = "0"; + } + SYSTEM_BUILDER_INFO + { + Is_Custom_Instruction = "1"; + Is_Enabled = "1"; + Date_Modified = ""; + Is_Visible = "0"; + Instantiate_In_System_Module = "1"; + Clock_Source = "clk"; + View + { + MESSAGES + { + } + } + } + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = "clk"; + } + SIGNAL b + { + name = "clk_en"; + } + SIGNAL c + { + name = "reset"; + } + SIGNAL d + { + name = "start"; + } + SIGNAL e + { + name = "n"; + radix = "hexadecimal"; + } + SIGNAL f + { + name = "dataa"; + radix = "hexadecimal"; + } + SIGNAL g + { + name = "datab"; + radix = "hexadecimal"; + } + SIGNAL h + { + name = "result"; + radix = "hexadecimal"; + } + SIGNAL i + { + name = "done"; + } + } + } + class = "altera_nios_custom_instr_floating_point"; + class_version = "7.080900"; + } + MODULE UART_backplane + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + PORT begintransfer + { + type = "begintransfer"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT read_n + { + type = "read_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT dataavailable + { + type = "dataavailable"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readyfordata + { + type = "readyfordata"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "1cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "1"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "16"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x07001160"; + } + IRQ_MASTER cpu/data_master + { + IRQ_Number = "4"; + } + Base_Address = "0x07001160"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT txd + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT rxd + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT rxused + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT txused + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT transmitting + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT cts_n + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "0"; + } + PORT rts_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT irqexport + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + } + class = "fifoed_avalon_uart"; + class_version = "7.1"; + WIZARD_SCRIPT_ARGUMENTS + { + use_tx_fifo = "1"; + use_rx_fifo = "1"; + baud = "115200"; + data_bits = "8"; + fixed_baud = "1"; + parity = "N"; + stop_bits = "1"; + use_cts_rts = "0"; + use_eop_register = "0"; + sim_true_baud = "0"; + sim_char_stream = ""; + use_fifo = "0"; + fifo_size = "16"; + fifo_export_used = "0"; + export_irq = "0"; + hw_cts = "0"; + trans_pin = "0"; + fifo_size_tx = "8"; + fifo_size_rx = "8"; + tx_fifo_LE = "0"; + rx_fifo_LE = "0"; + combine_fifo = "0"; + } + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + Instantiate_In_System_Module = "1"; + View + { + MESSAGES + { + } + Settings_Summary = "8-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity"; + } + } + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = " Bus Interface"; + format = "Divider"; + } + SIGNAL b + { + name = "chipselect"; + } + SIGNAL c + { + name = "address"; + radix = "hexadecimal"; + } + SIGNAL d + { + name = "writedata"; + radix = "hexadecimal"; + } + SIGNAL e + { + name = "readdata"; + radix = "hexadecimal"; + } + SIGNAL f + { + name = " Internals"; + format = "Divider"; + } + SIGNAL g + { + name = "tx_ready"; + } + SIGNAL h + { + name = "tx_data"; + radix = "ascii"; + } + SIGNAL i + { + name = "rx_char_ready"; + } + SIGNAL j + { + name = "rx_data"; + radix = "ascii"; + } + } + INTERACTIVE_OUT log + { + enable = "0"; + file = "_log_module.txt"; + # suffix to $module_name in em_uart.pl + radix = "ascii"; + signals = "temp,list"; + exe = "perl -- tail-f.pl"; + } + INTERACTIVE_IN drive + { + enable = "0"; + # file descriptors are really just suffixes used by perl... + file = "_input_data_stream.dat"; + mutex = "_input_data_mutex.dat"; + log = "_in.log"; + rate = "100"; + signals = "temp,list"; + exe = "perl -- uart.pl"; + } + } + } + MODULE UART_daughter + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + PORT begintransfer + { + type = "begintransfer"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT read_n + { + type = "read_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT dataavailable + { + type = "dataavailable"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readyfordata + { + type = "readyfordata"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "1cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "1"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "16"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x070011a0"; + } + IRQ_MASTER cpu/data_master + { + IRQ_Number = "5"; + } + Base_Address = "0x070011a0"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT txd + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT rxd + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT rxused + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT txused + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT transmitting + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT cts_n + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "0"; + } + PORT rts_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT irqexport + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + } + class = "fifoed_avalon_uart"; + class_version = "7.1"; + WIZARD_SCRIPT_ARGUMENTS + { + use_tx_fifo = "1"; + use_rx_fifo = "1"; + baud = "115200"; + data_bits = "8"; + fixed_baud = "0"; + parity = "N"; + stop_bits = "1"; + use_cts_rts = "0"; + use_eop_register = "0"; + sim_true_baud = "0"; + sim_char_stream = ""; + use_fifo = "0"; + fifo_size = "16"; + fifo_export_used = "0"; + export_irq = "0"; + hw_cts = "0"; + trans_pin = "0"; + fifo_size_tx = "8"; + fifo_size_rx = "8"; + tx_fifo_LE = "0"; + rx_fifo_LE = "0"; + combine_fifo = "0"; + } + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + Instantiate_In_System_Module = "1"; + View + { + MESSAGES + { + } + Settings_Summary = "8-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity"; + } + } + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = " Bus Interface"; + format = "Divider"; + } + SIGNAL b + { + name = "chipselect"; + } + SIGNAL c + { + name = "address"; + radix = "hexadecimal"; + } + SIGNAL d + { + name = "writedata"; + radix = "hexadecimal"; + } + SIGNAL e + { + name = "readdata"; + radix = "hexadecimal"; + } + SIGNAL f + { + name = " Internals"; + format = "Divider"; + } + SIGNAL g + { + name = "tx_ready"; + } + SIGNAL h + { + name = "tx_data"; + radix = "ascii"; + } + SIGNAL i + { + name = "rx_char_ready"; + } + SIGNAL j + { + name = "rx_data"; + radix = "ascii"; + } + } + INTERACTIVE_OUT log + { + enable = "0"; + file = "_log_module.txt"; + # suffix to $module_name in em_uart.pl + radix = "ascii"; + signals = "temp,list"; + exe = "perl -- tail-f.pl"; + } + INTERACTIVE_IN drive + { + enable = "0"; + # file descriptors are really just suffixes used by perl... + file = "_input_data_stream.dat"; + mutex = "_input_data_mutex.dat"; + log = "_in.log"; + rate = "100"; + signals = "temp,list"; + exe = "perl -- uart.pl"; + } + } + } + MODULE axonbus + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + PORT begintransfer + { + type = "begintransfer"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT read_n + { + type = "read_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT dataavailable + { + type = "dataavailable"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readyfordata + { + type = "readyfordata"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "1cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "1"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "16"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x07001140"; + } + IRQ_MASTER cpu/data_master + { + IRQ_Number = "7"; + } + Base_Address = "0x07001140"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT txd + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT rxd + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT transmitting + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT rxused + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT txused + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT cts_n + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "0"; + } + PORT rts_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT irqexport + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + } + class = "fifoed_avalon_uart"; + class_version = "7.1"; + WIZARD_SCRIPT_ARGUMENTS + { + use_tx_fifo = "1"; + use_rx_fifo = "1"; + baud = "115200"; + data_bits = "9"; + fixed_baud = "1"; + parity = "N"; + stop_bits = "1"; + use_cts_rts = "0"; + use_eop_register = "0"; + sim_true_baud = "0"; + sim_char_stream = ""; + use_fifo = "0"; + fifo_size = "16"; + fifo_export_used = "0"; + export_irq = "0"; + hw_cts = "0"; + trans_pin = "1"; + fifo_size_tx = "32"; + fifo_size_rx = "32"; + tx_fifo_LE = "0"; + rx_fifo_LE = "0"; + combine_fifo = "0"; + } + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + Instantiate_In_System_Module = "1"; + View + { + MESSAGES + { + } + Settings_Summary = "9-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity"; + } + } + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = " Bus Interface"; + format = "Divider"; + } + SIGNAL b + { + name = "chipselect"; + } + SIGNAL c + { + name = "address"; + radix = "hexadecimal"; + } + SIGNAL d + { + name = "writedata"; + radix = "hexadecimal"; + } + SIGNAL e + { + name = "readdata"; + radix = "hexadecimal"; + } + SIGNAL f + { + name = " Internals"; + format = "Divider"; + } + SIGNAL g + { + name = "tx_ready"; + } + SIGNAL h + { + name = "tx_data"; + radix = "ascii"; + } + SIGNAL i + { + name = "rx_char_ready"; + } + SIGNAL j + { + name = "rx_data"; + radix = "ascii"; + } + } + INTERACTIVE_OUT log + { + enable = "0"; + file = "_log_module.txt"; + # suffix to $module_name in em_uart.pl + radix = "ascii"; + signals = "temp,list"; + exe = "perl -- tail-f.pl"; + } + INTERACTIVE_IN drive + { + enable = "0"; + # file descriptors are really just suffixes used by perl... + file = "_input_data_stream.dat"; + mutex = "_input_data_mutex.dat"; + log = "_in.log"; + rate = "100"; + signals = "temp,list"; + exe = "perl -- uart.pl"; + } + } + } + MODULE I2C_local + { + SLAVE s1 + { + PORT_WIRING + { + PORT csi_s1clk_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT csi_s1clk_reset + { + type = "reset"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT ins_intout_irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_waitrequest_n + { + type = "waitrequest_n"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_writedata + { + type = "writedata"; + width = "8"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_readdata + { + type = "readdata"; + width = "8"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Read_Wait_States = "peripheral_controlled"; + Write_Wait_States = "peripheral_controlled"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "8"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x07001100"; + } + IRQ_MASTER cpu/data_master + { + IRQ_Number = "1"; + } + Base_Address = "0x07001100"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT coe_ext_export_scl + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT coe_ext_export_sda + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "opencores_i2c_master"; + gtf_class_version = "2.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_bit_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_byte_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_top.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/oc_i2c_master.vhd,/home/walter/VHDL/SYGEG1-080630/VHDL/Quartus_Altera/Prj/I2C_local.vhd"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE NIOS_clock_0 + { + class = "altera_avalon_clock_adapter"; + class_version = "7.080900"; + SYSTEM_BUILDER_INFO + { + Is_Adapter = "1"; + Rank_Order = "50"; + Has_Clock = "0"; + Is_Enabled = "1"; + Instantiate_In_System_Module = "1"; + Maximum_Pending_Read_Transactions_Multiplicand = "0"; + View + { + Settings_Summary = "<i>altera_avalon_clock_adapter</i> is crossing 66.66MHz to 33.33MHz."; + MESSAGES + { + } + } + Clock_Source = "clk_half"; + } + SLAVE in + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Clock_Source = "clk"; + Has_IRQ = "0"; + Read_Wait_States = "peripheral_controlled"; + Write_Wait_States = "peripheral_controlled"; + MASTERED_BY cpu/data_master + { + priority = "1"; + Offset_Address = "0x07010000"; + } + Address_Alignment = "native"; + Base_Address = "0x07010000"; + Maximum_Pending_Read_Transactions = "0"; + Address_Width = "8"; + Data_Width = "32"; + Maximum_Burst_Size = "1"; + } + } + MASTER out + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Clock_Source = "clk_half"; + Address_Width = "8"; + Data_Width = "32"; + Do_Stream_Reads = "0"; + Do_Stream_Writes = "0"; + Is_Readable = "1"; + Maximum_Burst_Size = "1"; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + asp_debug = "0"; + } + } +} diff --git a/recipes/linux-libc-headers/linux-libc-headers_nios2-2.6.28.bb b/recipes/linux-libc-headers/linux-libc-headers_nios2-2.6.28.bb new file mode 100644 index 0000000000..aa57e06420 --- /dev/null +++ b/recipes/linux-libc-headers/linux-libc-headers_nios2-2.6.28.bb @@ -0,0 +1,73 @@ +require linux-libc-headers.inc + +INHIBIT_DEFAULT_DEPS = "1" +DEPENDS += "unifdef-native" +PR = "r3" + +SRC_URI = "git://sopc.et.ntust.edu.tw/git/linux-2.6.git;branch=test-nios2;tags=3146b39c185f8a436d430132457e84fa1d8f8208 \ + file://procinfo.h \ + file://system.ptf" +S = "${WORKDIR}/git" + +#SRC_URI = "http://127.0.0.1/linux-nios2-2.6.28-git.tbz \ +# file://procinfo.h \ +# file://system.ptf" +#S = "${WORKDIR}/linux-2.6" + +set_arch() { + case ${TARGET_ARCH} in + alpha*) ARCH=alpha ;; + arm*) ARCH=arm ;; + cris*) ARCH=cris ;; + hppa*) ARCH=parisc ;; + i*86*) ARCH=i386 ;; + ia64*) ARCH=ia64 ;; + mips*) ARCH=mips ;; + m68k*) ARCH=m68k ;; + powerpc*) ARCH=powerpc ;; + s390*) ARCH=s390 ;; + sh*) ARCH=sh ;; + sparc64*) ARCH=sparc64 ;; + sparc*) ARCH=sparc ;; + x86_64*) ARCH=x86_64 ;; + avr32*) ARCH=avr32 ;; + bfin*) ARCH=blackfin ;; + nios2*) ARCH=nios2 ;; + esac +} + +do_configure() { + set_arch + oe_runmake hwselect SYSPTF=../system.ptf CPU_SELECTION=1 MEM_SELECTION=2 ARCH=$ARCH + oe_runmake allnoconfig ARCH=$ARCH +} + +do_compile () { +} + +do_install() { + set_arch + oe_runmake headers_install INSTALL_HDR_PATH=${D}${exec_prefix} ARCH=$ARCH +} + +do_install_append_arm() { + cp ${WORKDIR}/procinfo.h ${D}${includedir}/asm/ +} + +STAGE_TEMP="${WORKDIR}/temp-staging" + +do_stage () { + set_arch + echo $ARCH + rm -rf ${STAGE_TEMP} + mkdir -p ${STAGE_TEMP} + oe_runmake headers_install INSTALL_HDR_PATH=${STAGE_TEMP}${exec_prefix} ARCH=$ARCH + if [ "$ARCH" = "arm" ]; then + cp ${WORKDIR}/procinfo.h ${STAGE_TEMP}${includedir}/asm/ + fi + install -d ${STAGING_INCDIR} + rm -rf ${STAGING_INCDIR}/linux ${STAGING_INCDIR}/asm ${STAGING_INCDIR}/asm-generic + cp -pfLR ${STAGE_TEMP}${includedir}/linux ${STAGING_INCDIR}/ + cp -pfLR ${STAGE_TEMP}${includedir}/asm ${STAGING_INCDIR}/ + cp -pfLR ${STAGE_TEMP}${includedir}/asm-generic ${STAGING_INCDIR}/ +} diff --git a/recipes/linux/linux-nios2/2.6.28+nios2/defconfig b/recipes/linux/linux-nios2/2.6.28+nios2/defconfig new file mode 100644 index 0000000000..d8bfbf8056 --- /dev/null +++ b/recipes/linux/linux-nios2/2.6.28+nios2/defconfig @@ -0,0 +1,554 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28 +# Tue Nov 3 10:21:38 2009 +# +# CONFIG_FPU is not set +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_NO_IOPORT=y +# CONFIG_HOTPLUG_CPU is not set +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="/home/walter/sandbox/SYGEG1/angstrom-dev//deploy/uclibc/images/sygeg1/initramfs_root.cpio" +CONFIG_INITRAMFS_ROOT_UID=500 +CONFIG_INITRAMFS_ROOT_GID=500 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +# CONFIG_EPOLL is not set +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +# CONFIG_BLOCK is not set +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set + +# +# Processor type and features +# + +# +# Platform dependant setup +# +CONFIG_NIOS2=y +# CONFIG_MMU is not set +CONFIG_AXON_CARD=y +# CONFIG_MICROTRONIX_UKIT is not set +# CONFIG_MICROTRONIX_STRATIX is not set +# CONFIG_MICROTRONIX_CYCLONE is not set +# CONFIG_MICROTRONIX_PSK is not set +# CONFIG_ALTERA_STRATIX is not set +# CONFIG_ALTERA_STRATIX_PRO is not set +# CONFIG_ALTERA_STRATIX_II is not set +# CONFIG_ALTERA_CYCLONE is not set +# CONFIG_ALTERA_CYCLONE_II is not set +# CONFIG_ALTERA_CYCLONE_1C12_EVAL is not set +# CONFIG_ALTERA_DE2 is not set +# CONFIG_ALTERA_NEEK_C3 is not set +CONFIG_AXON_SYGEG1=y +# CONFIG_NIOS2_HW_MUL_OFF is not set +CONFIG_NIOS2_HW_MUL=y +# CONFIG_NIOS2_HW_MULX is not set + +# +# Platform drivers Options +# +# CONFIG_AVALON_DMA is not set +# CONFIG_PCI_ALTPCI is not set +# CONFIG_I2C_NIOS2_GPIO is not set +CONFIG_ALTERA_REMOTE_UPDATE=y + +# +# Miscellaneous Options +# +CONFIG_EXCALIBUR=y +# CONFIG_BREAK_ON_START is not set +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_RAMKERNEL=y +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_CMDLINE="" +# CONFIG_PASS_CMDLINE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +CONFIG_BOOT_LINK_OFFSET=0x00500000 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x8000000 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AXON_AXONBUS is not set +CONFIG_AXON_AXONBUS_HWA=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# SCSI device support +# +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NIOS_LCD_16207 is not set +# CONFIG_NIOS_BUTTON is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +CONFIG_SERIAL_ALTERA_UART=y +CONFIG_SERIAL_ALTERA_UART_MAXPORTS=1 +CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 +CONFIG_SERIAL_ALTERA_UART_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=10 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_OCORES=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_AT24=y +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +CONFIG_SENSORS_MAX7311=y +CONFIG_SENSORS_MAX7311_NUMCLIENTS=1 +CONFIG_SENSORS_MAX7311_ADDRESSES="0x24" +# CONFIG_SENSORS_LMH1982 is not set +# CONFIG_SENSORS_ADM1178 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_W1=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_DS2482=y + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +CONFIG_W1_SLAVE_SMEM=y +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_ALTERA_REMOTE_UPDATE_WATCHDOG=y +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_SYSCTL is not set +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_FAULT_INJECTION is not set + +# +# Tracers +# +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff --git a/recipes/linux/linux-nios2/2.6.28+nios2/procinfo.h b/recipes/linux/linux-nios2/2.6.28+nios2/procinfo.h new file mode 100644 index 0000000000..8cdf828af8 --- /dev/null +++ b/recipes/linux/linux-nios2/2.6.28+nios2/procinfo.h @@ -0,0 +1,24 @@ +/* + * linux/include/asm-arm/procinfo.h + * + * Copyright (C) 1996-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROCINFO_H +#define __ASM_PROCINFO_H + +#define HWCAP_SWP 1 +#define HWCAP_HALF 2 +#define HWCAP_THUMB 4 +#define HWCAP_26BIT 8 /* Play it safe */ +#define HWCAP_FAST_MULT 16 +#define HWCAP_FPA 32 +#define HWCAP_VFP 64 +#define HWCAP_EDSP 128 +#define HWCAP_JAVA 256 +#define HWCAP_IWMMXT 512 +#define HWCAP_CRUNCH 1024 +#endif diff --git a/recipes/linux/linux-nios2/2.6.28+nios2/system.ptf b/recipes/linux/linux-nios2/2.6.28+nios2/system.ptf new file mode 100644 index 0000000000..1a6198448b --- /dev/null +++ b/recipes/linux/linux-nios2/2.6.28+nios2/system.ptf @@ -0,0 +1,4416 @@ +SYSTEM sys +{ + System_Wizard_Version = "9.00"; + System_Wizard_Build = "132"; + Builder_Application = "sopc_builder_ca"; + WIZARD_SCRIPT_ARGUMENTS + { + hdl_language = "verilog"; + device_family = "CYCLONEIII"; + device_family_id = "CYCLONEIII"; + generate_sdk = "0"; + do_build_sim = "0"; + hardcopy_compatible = "0"; + CLOCKS + { + CLOCK clk_66 + { + frequency = "66667000"; + source = "External"; + Is_Clock_Source = "0"; + display_name = "clk_66"; + pipeline = "0"; + clock_module_connection_point_for_c2h = "clk_66.clk"; + } + CLOCK altmemddr_0_phy_clk + { + frequency = "66665000"; + source = ""; + Is_Clock_Source = "1"; + display_name = "phy_clk from altmemddr_0"; + pipeline = "0"; + clock_module_connection_point_for_c2h = "altmemddr_0.sysclk"; + } + CLOCK altmemddr_0_phy_clk_out + { + frequency = "66665000"; + source = "altmemddr_0_phy_clk"; + Is_Clock_Source = "0"; + display_name = "altmemddr_0_phy_clk_out"; + } + CLOCK altmemddr_0_aux_full_rate_clk + { + frequency = "133330000"; + source = ""; + Is_Clock_Source = "1"; + display_name = "aux_full_rate_clk from altmemddr_0"; + pipeline = "0"; + clock_module_connection_point_for_c2h = "altmemddr_0.auxfull"; + } + CLOCK altmemddr_0_aux_full_rate_clk_out + { + frequency = "133330000"; + source = "altmemddr_0_aux_full_rate_clk"; + Is_Clock_Source = "0"; + display_name = "altmemddr_0_aux_full_rate_clk_out"; + } + CLOCK altmemddr_0_aux_half_rate_clk + { + frequency = "66665000"; + source = ""; + Is_Clock_Source = "1"; + display_name = "aux_half_rate_clk from altmemddr_0"; + pipeline = "0"; + clock_module_connection_point_for_c2h = "altmemddr_0.auxhalf"; + } + CLOCK altmemddr_0_aux_half_rate_clk_out + { + frequency = "66665000"; + source = "altmemddr_0_aux_half_rate_clk"; + Is_Clock_Source = "0"; + display_name = "altmemddr_0_aux_half_rate_clk_out"; + } + CLOCK clk_33 + { + frequency = "33330000"; + source = "External"; + Is_Clock_Source = "0"; + display_name = "clk_33"; + pipeline = "0"; + clock_module_connection_point_for_c2h = "clk_33.clk"; + } + } + clock_freq = "66667000"; + clock_freq = "66667000"; + board_class = ""; + view_master_columns = "1"; + view_master_priorities = "0"; + generate_hdl = ""; + bustype_column_width = "0"; + clock_column_width = "80"; + name_column_width = "75"; + desc_column_width = "75"; + base_column_width = "75"; + end_column_width = "75"; + BOARD_INFO + { + altera_avalon_cfi_flash + { + reference_designators = ""; + } + } + do_log_history = "0"; + } + MODULE cpu_0 + { + MASTER instruction_master + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "0"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "0"; + } + PORT i_address + { + type = "address"; + width = "29"; + direction = "output"; + Is_Enabled = "1"; + } + PORT i_read + { + type = "read"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT i_readdata + { + type = "readdata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT i_readdatavalid + { + type = "readdatavalid"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT i_waitrequest + { + type = "waitrequest"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Is_Asynchronous = "0"; + DBS_Big_Endian = "0"; + Adapts_To = ""; + Do_Stream_Reads = "0"; + Do_Stream_Writes = "0"; + Max_Address_Width = "32"; + Data_Width = "32"; + Address_Width = "29"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = ""; + Linewrap_Bursts = ""; + Burst_On_Burst_Boundaries_Only = ""; + Always_Burst_Max_Burst = ""; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Is_Instruction_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "0"; + Address_Group = "0"; + Has_IRQ = "0"; + Irq_Scheme = "individual_requests"; + Interrupt_Range = "0-0"; + } + MEMORY_MAP + { + Entry cpu_0/jtag_debug_module + { + address = "0x10001000"; + span = "0x00000800"; + is_bridge = "0"; + } + Entry cfi_flash_0/s1 + { + address = "0x00000000"; + span = "0x04000000"; + is_bridge = "0"; + } + Entry altmemddr_0/s1 + { + address = "0x08000000"; + span = "0x08000000"; + is_bridge = "0"; + } + } + } + MASTER custom_instruction_master + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "nios_custom_instruction"; + Data_Width = "32"; + Address_Width = "8"; + Is_Custom_Instruction = "1"; + Is_Enabled = "0"; + Max_Address_Width = "8"; + Base_Address = "N/A"; + Is_Visible = "0"; + } + PORT_WIRING + { + PORT dataa + { + type = "dataa"; + width = "32"; + direction = "output"; + } + PORT datab + { + type = "datab"; + width = "32"; + direction = "output"; + } + PORT result + { + type = "result"; + width = "32"; + direction = "input"; + } + PORT clk_en + { + type = "clk_en"; + width = "1"; + direction = "output"; + } + PORT reset + { + type = "reset"; + width = "1"; + direction = "output"; + } + PORT start + { + type = "start"; + width = "1"; + direction = "output"; + } + PORT done + { + type = "done"; + width = "1"; + direction = "input"; + } + PORT n + { + type = "n"; + width = "8"; + direction = "output"; + } + PORT a + { + type = "a"; + width = "5"; + direction = "output"; + } + PORT b + { + type = "b"; + width = "5"; + direction = "output"; + } + PORT c + { + type = "c"; + width = "5"; + direction = "output"; + } + PORT readra + { + type = "readra"; + width = "1"; + direction = "output"; + } + PORT readrb + { + type = "readrb"; + width = "1"; + direction = "output"; + } + PORT writerc + { + type = "writerc"; + width = "1"; + direction = "output"; + } + } + } + SLAVE jtag_debug_module + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "dynamic"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Address_Span = "2048"; + Read_Latency = "0"; + Is_Memory_Device = "1"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "32"; + Address_Width = "9"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Accepts_External_Connections = "1"; + Requires_Internal_Connections = ""; + MASTERED_BY cpu_0/instruction_master + { + priority = "1"; + Offset_Address = "0x10001000"; + } + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x10001000"; + } + Base_Address = "0x10001000"; + Is_Readable = "1"; + Is_Writeable = "1"; + Uses_Tri_State_Data_Bus = "0"; + Has_IRQ = "0"; + JTAG_Hub_Base_Id = "1118278"; + JTAG_Hub_Instance_Id = "0"; + Address_Group = "0"; + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + PORT_WIRING + { + PORT jtag_debug_module_address + { + type = "address"; + width = "9"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_begintransfer + { + type = "begintransfer"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_byteenable + { + type = "byteenable"; + width = "4"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_debugaccess + { + type = "debugaccess"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_readdata + { + type = "readdata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_resetrequest + { + type = "resetrequest"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_select + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_writedata + { + type = "writedata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_clk + { + Is_Enabled = "1"; + direction = "input"; + type = "clk"; + width = "1"; + } + PORT jtag_debug_module_reset + { + Is_Enabled = "1"; + direction = "input"; + type = "reset"; + width = "1"; + } + PORT reset_n + { + Is_Enabled = "1"; + direction = "input"; + type = "reset_n"; + width = "1"; + } + } + } + MASTER data_master + { + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Irq_Scheme = "individual_requests"; + Bus_Type = "avalon"; + Is_Asynchronous = "0"; + DBS_Big_Endian = "0"; + Adapts_To = ""; + Do_Stream_Reads = "0"; + Do_Stream_Writes = "0"; + Max_Address_Width = "32"; + Data_Width = "32"; + Address_Width = "29"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = ""; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Is_Data_Master = "1"; + Address_Group = "0"; + Is_Readable = "1"; + Is_Writeable = "1"; + Interrupt_Range = "0-31"; + } + PORT_WIRING + { + PORT d_irq + { + type = "irq"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT d_address + { + type = "address"; + width = "29"; + direction = "output"; + Is_Enabled = "1"; + } + PORT d_byteenable + { + type = "byteenable"; + width = "4"; + direction = "output"; + Is_Enabled = "1"; + } + PORT d_read + { + type = "read"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT d_readdata + { + type = "readdata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT d_readdatavalid + { + type = "readdatavalid"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT d_waitrequest + { + type = "waitrequest"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT d_write + { + type = "write"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT d_writedata + { + type = "writedata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + PORT jtag_debug_module_debugaccess_to_roms + { + type = "debugaccess"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT clk + { + Is_Enabled = "1"; + direction = "input"; + type = "clk"; + width = "1"; + } + } + MEMORY_MAP + { + Entry cpu_0/jtag_debug_module + { + address = "0x10001000"; + span = "0x00000800"; + is_bridge = "0"; + } + Entry cfi_flash_0/s1 + { + address = "0x00000000"; + span = "0x04000000"; + is_bridge = "0"; + } + Entry timer_0/s1 + { + address = "0x10000080"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry uart_0/s1 + { + address = "0x10000000"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry altmemddr_0/s1 + { + address = "0x08000000"; + span = "0x08000000"; + is_bridge = "0"; + } + Entry opencores_i2c_master_0/s1 + { + address = "0x1c100000"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry opencores_i2c_master_1/s1 + { + address = "0x1c200000"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry opencores_i2c_master_2/s1 + { + address = "0x1c300000"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry opencores_i2c_master_3/s1 + { + address = "0x1c400000"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry opencores_i2c_master_4/s1 + { + address = "0x1c500000"; + span = "0x00000020"; + is_bridge = "0"; + } + Entry axonbus_0/ctrl + { + address = "0x1c600000"; + span = "0x00000040"; + is_bridge = "0"; + } + Entry remote_update_cycloneiii_0/s1 + { + address = "0x11000000"; + span = "0x00000100"; + is_bridge = "0"; + } + Entry avalon_bus_contents_0/s1 + { + address = "0x1c000000"; + span = "0x00000800"; + is_bridge = "0"; + } + } + } + WIZARD_SCRIPT_ARGUMENTS + { + cache_has_dcache = "1"; + cache_dcache_size = "2048"; + cache_dcache_line_size = "32"; + cache_dcache_bursts = "0"; + cache_dcache_ram_block_type = "AUTO"; + num_tightly_coupled_data_masters = "0"; + gui_num_tightly_coupled_data_masters = "0"; + gui_include_tightly_coupled_data_masters = "0"; + gui_omit_avalon_data_master = "0"; + cache_has_icache = "1"; + cache_icache_size = "4096"; + cache_icache_line_size = "32"; + cache_icache_ram_block_type = "AUTO"; + cache_icache_bursts = "0"; + num_tightly_coupled_instruction_masters = "0"; + gui_num_tightly_coupled_instruction_masters = "0"; + gui_include_tightly_coupled_instruction_masters = "0"; + debug_level = "2"; + include_oci = "1"; + oci_num_xbrk = "0"; + oci_num_dbrk = "0"; + oci_dbrk_trace = "0"; + oci_dbrk_pairs = "0"; + oci_onchip_trace = "0"; + oci_offchip_trace = "0"; + oci_data_trace = "0"; + include_third_party_debug_port = "0"; + oci_trace_addr_width = "7"; + oci_debugreq_signals = "0"; + oci_trigger_arming = "1"; + oci_embedded_pll = "0"; + oci_assign_jtag_instance_id = "0"; + oci_jtag_instance_id = "0"; + oci_num_pm = "0"; + oci_pm_width = "32"; + performance_counters_present = "0"; + performance_counters_width = "32"; + always_encrypt = "1"; + debug_simgen = "0"; + activate_model_checker = "0"; + activate_test_end_checker = "0"; + activate_trace = "1"; + activate_monitors = "1"; + clear_x_bits_ld_non_bypass = "1"; + bit_31_bypass_dcache = "1"; + hdl_sim_caches_cleared = "1"; + hbreak_test = "0"; + allow_full_address_range = "0"; + extra_exc_info = "0"; + branch_prediction_type = "Dynamic"; + bht_ptr_sz = "8"; + bht_index_pc_only = "0"; + gui_branch_prediction_type = "Automatic"; + full_waveform_signals = "0"; + export_pcb = "0"; + avalon_debug_port_present = "0"; + illegal_instructions_trap = "0"; + illegal_memory_access_detection = "0"; + illegal_mem_exc = "0"; + slave_access_error_exc = "0"; + division_error_exc = "0"; + eic_present = "0"; + num_shadow_reg_sets = "0"; + gui_mmu_present = "0"; + mmu_present = "0"; + process_id_num_bits = "8"; + tlb_ptr_sz = "7"; + tlb_num_ways = "16"; + udtlb_num_entries = "6"; + uitlb_num_entries = "4"; + fast_tlb_miss_exc_slave = ""; + fast_tlb_miss_exc_offset = "0x00000000"; + mpu_present = "0"; + mpu_num_data_regions = "8"; + mpu_num_inst_regions = "8"; + mpu_min_data_region_size_log2 = "12"; + mpu_min_inst_region_size_log2 = "12"; + mpu_use_limit = "0"; + hardware_divide_present = "1"; + gui_hardware_divide_setting = "1"; + hardware_multiply_present = "1"; + hardware_multiply_impl = "embedded_mul"; + shift_rot_impl = "fast_le_shift"; + gui_hardware_multiply_setting = "embedded_mul_fast_le_shift"; + reset_slave = "cfi_flash_0/s1"; + break_slave = "cpu_0/jtag_debug_module"; + exc_slave = "altmemddr_0/s1"; + reset_offset = "0x00400000"; + break_offset = "0x00000020"; + exc_offset = "0x00000020"; + cpu_reset = "0"; + CPU_Implementation = "fast"; + cpu_selection = "f"; + device_family_id = "CYCLONEIII"; + address_stall_present = "1"; + dsp_block_supports_shift = "0"; + mrams_present = "0"; + cpuid_value = "0"; + dont_overwrite_cpuid = "1"; + allow_legacy_sdk = "1"; + legacy_sdk_support = "1"; + inst_addr_width = "29"; + data_addr_width = "29"; + CPU_Architecture = "nios2"; + cache_icache_burst_type = "none"; + oci_sync_depth = "2"; + hardware_multiply_omits_msw = "1"; + big_endian = "0"; + break_slave_override = ""; + break_offset_override = "0x20"; + altera_show_unreleased_features = "0"; + altera_show_unpublished_features = "0"; + altera_internal_test = "0"; + alt_log_port_base = ""; + alt_log_port_type = ""; + cpuid_sz = "1"; + gui_illegal_instructions_trap = "0"; + advanced_exc = "0"; + gui_illegal_memory_access_detection = "0"; + cache_omit_dcache = "0"; + cache_omit_icache = "0"; + omit_instruction_master = "0"; + omit_data_master = "0"; + ras_ptr_sz = "4"; + jtb_ptr_sz = "5"; + ibuf_ptr_sz = "4"; + always_bypass_dcache = "0"; + iss_trace_on = "0"; + iss_trace_warning = "1"; + iss_trace_info = "1"; + iss_trace_disassembly = "0"; + iss_trace_registers = "0"; + iss_trace_instr_count = "0"; + iss_software_debug = "0"; + iss_software_debug_port = "9996"; + iss_memory_dump_start = ""; + iss_memory_dump_end = ""; + Boot_Copier = "boot_loader_cfi.srec"; + Boot_Copier_EPCS = "boot_loader_epcs.srec"; + Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec"; + Boot_Copier_BE = "boot_loader_cfi_be.srec"; + Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec"; + Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec"; + CONSTANTS + { + CONSTANT __nios_catch_irqs__ + { + value = "1"; + comment = "Include panic handler for all irqs (needs uart)"; + } + CONSTANT __nios_use_constructors__ + { + value = "1"; + comment = "Call c++ static constructors"; + } + CONSTANT __nios_use_small_printf__ + { + value = "1"; + comment = "Smaller non-ANSI printf, with no floating point"; + } + CONSTANT nasys_has_icache + { + value = "1"; + comment = "True if instruction cache present"; + } + CONSTANT nasys_icache_size + { + value = "4096"; + comment = "Size in bytes of instruction cache"; + } + CONSTANT nasys_icache_line_size + { + value = "32"; + comment = "Size in bytes of each icache line"; + } + CONSTANT nasys_icache_line_size_log2 + { + value = "5"; + comment = "Log2 size in bytes of each icache line"; + } + CONSTANT nasys_has_dcache + { + value = "1"; + comment = "True if instruction cache present"; + } + CONSTANT nasys_dcache_size + { + value = "2048"; + comment = "Size in bytes of data cache"; + } + CONSTANT nasys_dcache_line_size + { + value = "32"; + comment = "Size in bytes of each dcache line"; + } + CONSTANT nasys_dcache_line_size_log2 + { + value = "5"; + comment = "Log2 size in bytes of each dcache line"; + } + } + license_status = "encrypted"; + mainmem_slave = "altmemddr_0/s1"; + datamem_slave = "altmemddr_0/s1"; + maincomm_slave = "uart_0/s1"; + germs_monitor_id = ""; + } + class = "altera_nios2"; + class_version = "7.080900"; + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + Parameters_Signature = ""; + Is_CPU = "1"; + Instantiate_In_System_Module = "1"; + Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII,HARDCOPYIII,ARRIAII,TARPON,HARDCOPYIV"; + Default_Module_Name = "cpu"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + Settings_Summary = "Nios II/f + <br> 4-Kbyte Instruction Cache + <br> 2-Kbyte Data Cache + <br> JTAG Debug Module + "; + MESSAGES + { + } + } + } + iss_model_name = "altera_nios2"; + HDL_INFO + { + PLI_Files = ""; + Precompiled_Simulation_Library_Files = ""; + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.v, __PROJECT_DIRECTORY__/cpu_0_mult_cell.v, __PROJECT_DIRECTORY__/cpu_0_oci_test_bench.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_tck.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_sysclk.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu_0.v"; + Synthesis_Only_Files = ""; + } + MASTER tightly_coupled_instruction_master_0 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Is_Instruction_Master = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_instruction_master_1 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Instruction_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "0"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_instruction_master_2 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Instruction_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "0"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_instruction_master_3 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Instruction_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "0"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER data_master2 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "1"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + } + } + MASTER tightly_coupled_data_master_0 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_data_master_1 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_data_master_2 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + MASTER tightly_coupled_data_master_3 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Address_Group = "0"; + Is_Data_Master = "1"; + Is_Readable = "1"; + Is_Writeable = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + Is_Big_Endian = "0"; + Connection_Limit = "1"; + Is_Channel = "1"; + } + } + PORT_WIRING + { + PORT jtag_debug_trigout + { + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT jtag_debug_offchip_trace_clk + { + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT jtag_debug_offchip_trace_data + { + width = "18"; + direction = "output"; + Is_Enabled = "0"; + } + PORT clkx2 + { + width = "1"; + direction = "input"; + Is_Enabled = "0"; + visible = "0"; + } + } + SIMULATION + { + DISPLAY + { + SIGNAL aaa + { + format = "Logic"; + name = "i_readdata"; + radix = "hexadecimal"; + } + SIGNAL aab + { + format = "Logic"; + name = "i_readdatavalid"; + radix = "hexadecimal"; + } + SIGNAL aac + { + format = "Logic"; + name = "i_waitrequest"; + radix = "hexadecimal"; + } + SIGNAL aad + { + format = "Logic"; + name = "i_address"; + radix = "hexadecimal"; + } + SIGNAL aae + { + format = "Logic"; + name = "i_read"; + radix = "hexadecimal"; + } + SIGNAL aaf + { + format = "Logic"; + name = "clk"; + radix = "hexadecimal"; + } + SIGNAL aag + { + format = "Logic"; + name = "reset_n"; + radix = "hexadecimal"; + } + SIGNAL aah + { + format = "Logic"; + name = "d_readdata"; + radix = "hexadecimal"; + } + SIGNAL aai + { + format = "Logic"; + name = "d_waitrequest"; + radix = "hexadecimal"; + } + SIGNAL aaj + { + format = "Logic"; + name = "d_irq"; + radix = "hexadecimal"; + } + SIGNAL aak + { + format = "Logic"; + name = "d_address"; + radix = "hexadecimal"; + } + SIGNAL aal + { + format = "Logic"; + name = "d_byteenable"; + radix = "hexadecimal"; + } + SIGNAL aam + { + format = "Logic"; + name = "d_read"; + radix = "hexadecimal"; + } + SIGNAL aan + { + format = "Logic"; + name = "d_write"; + radix = "hexadecimal"; + } + SIGNAL aao + { + format = "Logic"; + name = "d_writedata"; + radix = "hexadecimal"; + } + SIGNAL aap + { + format = "Logic"; + name = "d_readdatavalid"; + radix = "hexadecimal"; + } + SIGNAL aaq + { + format = "Divider"; + name = "base pipeline"; + radix = ""; + } + SIGNAL aar + { + format = "Logic"; + name = "clk"; + radix = "hexadecimal"; + } + SIGNAL aas + { + format = "Logic"; + name = "reset_n"; + radix = "hexadecimal"; + } + SIGNAL aat + { + format = "Logic"; + name = "D_stall"; + radix = "hexadecimal"; + } + SIGNAL aau + { + format = "Logic"; + name = "A_stall"; + radix = "hexadecimal"; + } + SIGNAL aav + { + format = "Logic"; + name = "F_pcb_nxt"; + radix = "hexadecimal"; + } + SIGNAL aaw + { + format = "Logic"; + name = "F_pcb"; + radix = "hexadecimal"; + } + SIGNAL aax + { + format = "Logic"; + name = "D_pcb"; + radix = "hexadecimal"; + } + SIGNAL aay + { + format = "Logic"; + name = "E_pcb"; + radix = "hexadecimal"; + } + SIGNAL aaz + { + format = "Logic"; + name = "M_pcb"; + radix = "hexadecimal"; + } + SIGNAL aba + { + format = "Logic"; + name = "A_pcb"; + radix = "hexadecimal"; + } + SIGNAL abb + { + format = "Logic"; + name = "W_pcb"; + radix = "hexadecimal"; + } + SIGNAL abc + { + format = "Logic"; + name = "F_vinst"; + radix = "ascii"; + } + SIGNAL abd + { + format = "Logic"; + name = "D_vinst"; + radix = "ascii"; + } + SIGNAL abe + { + format = "Logic"; + name = "E_vinst"; + radix = "ascii"; + } + SIGNAL abf + { + format = "Logic"; + name = "M_vinst"; + radix = "ascii"; + } + SIGNAL abg + { + format = "Logic"; + name = "A_vinst"; + radix = "ascii"; + } + SIGNAL abh + { + format = "Logic"; + name = "W_vinst"; + radix = "ascii"; + } + SIGNAL abi + { + format = "Logic"; + name = "F_inst_ram_hit"; + radix = "hexadecimal"; + } + SIGNAL abj + { + format = "Logic"; + name = "F_issue"; + radix = "hexadecimal"; + } + SIGNAL abk + { + format = "Logic"; + name = "F_kill"; + radix = "hexadecimal"; + } + SIGNAL abl + { + format = "Logic"; + name = "D_kill"; + radix = "hexadecimal"; + } + SIGNAL abm + { + format = "Logic"; + name = "D_refetch"; + radix = "hexadecimal"; + } + SIGNAL abn + { + format = "Logic"; + name = "D_issue"; + radix = "hexadecimal"; + } + SIGNAL abo + { + format = "Logic"; + name = "D_valid"; + radix = "hexadecimal"; + } + SIGNAL abp + { + format = "Logic"; + name = "E_valid"; + radix = "hexadecimal"; + } + SIGNAL abq + { + format = "Logic"; + name = "M_valid"; + radix = "hexadecimal"; + } + SIGNAL abr + { + format = "Logic"; + name = "A_valid"; + radix = "hexadecimal"; + } + SIGNAL abs + { + format = "Logic"; + name = "W_valid"; + radix = "hexadecimal"; + } + SIGNAL abt + { + format = "Logic"; + name = "W_wr_dst_reg"; + radix = "hexadecimal"; + } + SIGNAL abu + { + format = "Logic"; + name = "W_dst_regnum"; + radix = "hexadecimal"; + } + SIGNAL abv + { + format = "Logic"; + name = "W_wr_data"; + radix = "hexadecimal"; + } + SIGNAL abw + { + format = "Logic"; + name = "D_en"; + radix = "hexadecimal"; + } + SIGNAL abx + { + format = "Logic"; + name = "E_en"; + radix = "hexadecimal"; + } + SIGNAL aby + { + format = "Logic"; + name = "M_en"; + radix = "hexadecimal"; + } + SIGNAL abz + { + format = "Logic"; + name = "A_en"; + radix = "hexadecimal"; + } + SIGNAL aca + { + format = "Logic"; + name = "F_iw"; + radix = "hexadecimal"; + } + SIGNAL acb + { + format = "Logic"; + name = "D_iw"; + radix = "hexadecimal"; + } + SIGNAL acc + { + format = "Logic"; + name = "E_iw"; + radix = "hexadecimal"; + } + SIGNAL acd + { + format = "Logic"; + name = "M_pipe_flush"; + radix = "hexadecimal"; + } + SIGNAL ace + { + format = "Logic"; + name = "M_pipe_flush_baddr"; + radix = "hexadecimal"; + } + SIGNAL acf + { + format = "Logic"; + name = "intr_req"; + radix = "hexadecimal"; + } + SIGNAL acg + { + format = "Logic"; + name = "A_status_reg"; + radix = "hexadecimal"; + } + SIGNAL ach + { + format = "Logic"; + name = "A_status_reg_pie"; + radix = "hexadecimal"; + } + SIGNAL aci + { + format = "Logic"; + name = "A_estatus_reg"; + radix = "hexadecimal"; + } + SIGNAL acj + { + format = "Logic"; + name = "A_estatus_reg_pie"; + radix = "hexadecimal"; + } + SIGNAL ack + { + format = "Logic"; + name = "A_bstatus_reg"; + radix = "hexadecimal"; + } + SIGNAL acl + { + format = "Logic"; + name = "A_bstatus_reg_pie"; + radix = "hexadecimal"; + } + SIGNAL acm + { + format = "Logic"; + name = "A_ienable_reg"; + radix = "hexadecimal"; + } + SIGNAL acn + { + format = "Logic"; + name = "A_ienable_reg_irq2"; + radix = "hexadecimal"; + } + SIGNAL aco + { + format = "Logic"; + name = "A_ienable_reg_irq3"; + radix = "hexadecimal"; + } + SIGNAL acp + { + format = "Logic"; + name = "A_ienable_reg_irq6"; + radix = "hexadecimal"; + } + SIGNAL acq + { + format = "Logic"; + name = "A_ienable_reg_irq7"; + radix = "hexadecimal"; + } + SIGNAL acr + { + format = "Logic"; + name = "A_ienable_reg_irq8"; + radix = "hexadecimal"; + } + SIGNAL acs + { + format = "Logic"; + name = "A_ienable_reg_irq9"; + radix = "hexadecimal"; + } + SIGNAL act + { + format = "Logic"; + name = "A_ienable_reg_irq10"; + radix = "hexadecimal"; + } + SIGNAL acu + { + format = "Logic"; + name = "A_ienable_reg_irq11"; + radix = "hexadecimal"; + } + SIGNAL acv + { + format = "Logic"; + name = "A_ipending_reg"; + radix = "hexadecimal"; + } + SIGNAL acw + { + format = "Logic"; + name = "A_ipending_reg_irq2"; + radix = "hexadecimal"; + } + SIGNAL acx + { + format = "Logic"; + name = "A_ipending_reg_irq3"; + radix = "hexadecimal"; + } + SIGNAL acy + { + format = "Logic"; + name = "A_ipending_reg_irq6"; + radix = "hexadecimal"; + } + SIGNAL acz + { + format = "Logic"; + name = "A_ipending_reg_irq7"; + radix = "hexadecimal"; + } + SIGNAL ada + { + format = "Logic"; + name = "A_ipending_reg_irq8"; + radix = "hexadecimal"; + } + SIGNAL adb + { + format = "Logic"; + name = "A_ipending_reg_irq9"; + radix = "hexadecimal"; + } + SIGNAL adc + { + format = "Logic"; + name = "A_ipending_reg_irq10"; + radix = "hexadecimal"; + } + SIGNAL add + { + format = "Logic"; + name = "A_ipending_reg_irq11"; + radix = "hexadecimal"; + } + SIGNAL ade + { + format = "Logic"; + name = "A_cpuid_reg"; + radix = "hexadecimal"; + } + SIGNAL adf + { + format = "Logic"; + name = "E_valid_prior_to_hbreak"; + radix = "hexadecimal"; + } + } + } + } + MODULE cfi_flash_0 + { + SLAVE s1 + { + PORT_WIRING + { + PORT data + { + type = "data"; + width = "16"; + direction = "inout"; + Is_Enabled = "1"; + is_shared = "1"; + } + PORT address + { + type = "address"; + width = "25"; + direction = "input"; + Is_Enabled = "1"; + is_shared = "1"; + } + PORT read_n + { + type = "read_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + is_shared = "1"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + is_shared = "1"; + } + PORT select_n + { + type = "chipselect_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + is_shared = "0"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon_tristate"; + Write_Wait_States = "120ns"; + Read_Wait_States = "120ns"; + Hold_Time = "20ns"; + Setup_Time = "20ns"; + Is_Printable_Device = "0"; + Address_Alignment = "dynamic"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "1"; + Address_Span = "67108864"; + Read_Latency = "0"; + Is_Memory_Device = "1"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "1"; + Active_CS_Through_Read_Latency = "0"; + Data_Width = "16"; + Address_Width = "25"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY tri_state_bridge_0/tristate_master + { + priority = "1"; + Offset_Address = "0x00000000"; + } + Base_Address = "0x00000000"; + Has_IRQ = "0"; + Simulation_Num_Lanes = "1"; + Convert_Xs_To_0 = "1"; + Address_Group = "0"; + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + class = "altera_avalon_cfi_flash"; + Supports_Flash_File_System = "1"; + flash_reference_designator = ""; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + Setup_Value = "20"; + Wait_Value = "120"; + Hold_Value = "20"; + Timing_Units = "ns"; + Unit_Multiplier = "1"; + Size = "67108864"; + MAKE + { + MACRO + { + CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_0_FLASHTARGET_TMP1:0=)"; + CFI_FLASH_0_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)"; + } + MASTER cpu_0 + { + MACRO + { + BOOT_COPIER = "boot_loader_cfi.srec"; + CPU_CLASS = "altera_nios2"; + CPU_RESET_ADDRESS = "0x400000"; + } + } + TARGET delete_placeholder_warning + { + cfi_flash_0 + { + Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt"; + Is_Phony = "1"; + Target_File = "do_delete_placeholder_warning"; + } + } + TARGET flashfiles + { + cfi_flash_0 + { + Command1 = "@echo Post-processing to create $(notdir $@)"; + Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x3FFFFFF --reset=$(CPU_RESET_ADDRESS) "; + Dependency = "$(ELF)"; + Target_File = "$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash"; + } + } + TARGET sim + { + cfi_flash_0 + { + Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi"; + Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)"; + Command3 = "touch $(SIMDIR)/dummy_file"; + Dependency = "$(ELF)"; + Target_File = "$(SIMDIR)/dummy_file"; + } + } + } + } + SYSTEM_BUILDER_INFO + { + Simulation_Num_Lanes = "2"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + Make_Memory_Model = "1"; + Instantiate_In_System_Module = "0"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + MESSAGES + { + } + } + } + class = "altera_avalon_cfi_flash"; + class_version = "7.080900"; + iss_model_name = "altera_avalon_flash"; + HDL_INFO + { + } + } + MODULE tri_state_bridge_0 + { + SLAVE avalon_slave + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "dynamic"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Address_Span = "1"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "1"; + Register_Outgoing_Signals = "1"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/instruction_master + { + priority = "1"; + Offset_Address = "N/A"; + Base_Address = "N/A"; + } + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "N/A"; + Base_Address = "N/A"; + } + Bridges_To = "tristate_master"; + Base_Address = "N/A"; + Has_IRQ = "0"; + IRQ = "N/A"; + Address_Group = "0"; + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + } + MASTER tristate_master + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon_tristate"; + Is_Asynchronous = "0"; + DBS_Big_Endian = "0"; + Adapts_To = ""; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Bridges_To = "avalon_slave"; + } + PORT_WIRING + { + } + MEMORY_MAP + { + Entry cfi_flash_0/s1 + { + address = "0x00000000"; + span = "0x04000000"; + is_bridge = "0"; + } + } + } + WIZARD_SCRIPT_ARGUMENTS + { + } + class = "altera_avalon_tri_state_bridge"; + class_version = "7.080900"; + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "1"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + MESSAGES + { + } + } + } + } + MODULE timer_0 + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "16"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x10000080"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "2"; + } + Base_Address = "0x10000080"; + Address_Group = "0"; + } + } + class = "altera_avalon_timer"; + class_version = "7.080900"; + iss_model_name = "altera_avalon_timer"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + Settings_Summary = "Timer with 1 ms timeout period."; + Is_Collapsed = "1"; + MESSAGES + { + } + } + Clock_Source = "clk_66"; + Has_Clock = "1"; + } + WIZARD_SCRIPT_ARGUMENTS + { + always_run = "0"; + fixed_period = "0"; + snapshot = "1"; + period = "1"; + period_units = "ms"; + reset_output = "0"; + timeout_pulse_output = "0"; + load_value = "66666"; + counter_size = "32"; + mult = "0.0010"; + ticks_per_sec = "1000"; + } + HDL_INFO + { + Precompiled_Simulation_Library_Files = ""; + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_0.v"; + Synthesis_Only_Files = ""; + } + PORT_WIRING + { + } + } + MODULE uart_0 + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + PORT begintransfer + { + type = "begintransfer"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT read_n + { + type = "read_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT dataavailable + { + type = "dataavailable"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readyfordata + { + type = "readyfordata"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "1cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "1"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "16"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x10000000"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "3"; + } + Base_Address = "0x10000000"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT txd + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT rxd + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT rxused + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT txused + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT transmitting + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT cts_n + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "0"; + } + PORT rts_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + PORT irqexport + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "0"; + } + } + class = "fifoed_avalon_uart"; + class_version = "7.1"; + WIZARD_SCRIPT_ARGUMENTS + { + use_tx_fifo = "1"; + use_rx_fifo = "1"; + baud = "115200"; + data_bits = "8"; + fixed_baud = "1"; + parity = "N"; + stop_bits = "1"; + use_cts_rts = "0"; + use_eop_register = "0"; + sim_true_baud = "0"; + sim_char_stream = ""; + use_fifo = "0"; + fifo_size = "16"; + fifo_export_used = "0"; + export_irq = "0"; + hw_cts = "0"; + trans_pin = "0"; + fifo_size_tx = "8"; + fifo_size_rx = "64"; + tx_fifo_LE = "0"; + rx_fifo_LE = "0"; + combine_fifo = "0"; + } + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + Instantiate_In_System_Module = "1"; + View + { + MESSAGES + { + } + Settings_Summary = "8-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity"; + } + } + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = " Bus Interface"; + format = "Divider"; + } + SIGNAL b + { + name = "chipselect"; + } + SIGNAL c + { + name = "address"; + radix = "hexadecimal"; + } + SIGNAL d + { + name = "writedata"; + radix = "hexadecimal"; + } + SIGNAL e + { + name = "readdata"; + radix = "hexadecimal"; + } + SIGNAL f + { + name = " Internals"; + format = "Divider"; + } + SIGNAL g + { + name = "tx_ready"; + } + SIGNAL h + { + name = "tx_data"; + radix = "ascii"; + } + SIGNAL i + { + name = "rx_char_ready"; + } + SIGNAL j + { + name = "rx_data"; + radix = "ascii"; + } + } + INTERACTIVE_OUT log + { + enable = "0"; + file = "_log_module.txt"; + radix = "ascii"; + signals = "temp,list"; + exe = "perl -- tail-f.pl"; + } + INTERACTIVE_IN drive + { + enable = "0"; + file = "_input_data_stream.dat"; + mutex = "_input_data_mutex.dat"; + log = "_in.log"; + rate = "100"; + signals = "temp,list"; + exe = "perl -- uart.pl"; + } + } + HDL_INFO + { + Precompiled_Simulation_Library_Files = ""; + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart_0.v"; + Synthesis_Only_Files = ""; + } + } + MODULE altmemddr_0 + { + PORT_WIRING + { + PORT pll_ref_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT soft_reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT aux_full_rate_clk + { + type = "out_clk"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT aux_half_rate_clk + { + type = "out_clk"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT mem_odt + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + declare_one_bit_as_std_logic_vector = "1"; + } + PORT mem_clk + { + type = "export"; + width = "2"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT mem_clk_n + { + type = "export"; + width = "2"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT mem_cs_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + declare_one_bit_as_std_logic_vector = "1"; + } + PORT mem_cke + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + declare_one_bit_as_std_logic_vector = "1"; + } + PORT mem_addr + { + type = "export"; + width = "13"; + direction = "output"; + Is_Enabled = "1"; + } + PORT mem_ba + { + type = "export"; + width = "2"; + direction = "output"; + Is_Enabled = "1"; + } + PORT mem_ras_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT mem_cas_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT mem_we_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT mem_dq + { + type = "export"; + width = "32"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT mem_dqs + { + type = "export"; + width = "4"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT mem_dm + { + type = "export"; + width = "4"; + direction = "output"; + Is_Enabled = "1"; + } + PORT local_refresh_ack + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT local_wdata_req + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT local_init_done + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT reset_phy_clk_n + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT global_reset_n + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + } + SLAVE s1 + { + PORT_WIRING + { + PORT phy_clk + { + type = "out_clk"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT local_address + { + type = "address"; + width = "23"; + direction = "input"; + Is_Enabled = "1"; + } + PORT local_write_req + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT local_read_req + { + type = "read"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT local_burstbegin + { + type = "beginbursttransfer"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT local_ready + { + type = "waitrequest_n"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT local_rdata + { + type = "readdata"; + width = "128"; + direction = "output"; + Is_Enabled = "1"; + } + PORT local_rdata_valid + { + type = "readdatavalid"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT local_wdata + { + type = "writedata"; + width = "128"; + direction = "input"; + Is_Enabled = "1"; + } + PORT local_be + { + type = "byteenable"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT local_size + { + type = "burstcount"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_request_n + { + type = "resetrequest_n"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Read_Wait_States = "peripheral_controlled"; + Write_Wait_States = "peripheral_controlled"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "dynamic"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Address_Span = "134217728"; + Read_Latency = "0"; + Is_Memory_Device = "1"; + Maximum_Pending_Read_Transactions = "32"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "128"; + Address_Width = "23"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "1"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + Clock_Source = "altmemddr_0_phy_clk_out"; + Has_Clock = "1"; + MASTERED_BY cpu_0/instruction_master + { + priority = "1"; + Offset_Address = "0x08000000"; + } + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x08000000"; + } + Base_Address = "0x08000000"; + Address_Group = "0"; + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + } + iss_model_name = "altera_memory"; + class = "ddr2_high_perf"; + WIZARD_SCRIPT_ARGUMENTS + { + device_family = "Cyclone III"; + datawidth = "32"; + memtype = "DDR2 SDRAM"; + local_burst_length = "1"; + num_chipselects = "1"; + cas_latency = "4.0"; + addr_width = "13"; + ba_width = "2"; + row_width = "13"; + col_width = "10"; + clockspeed = "7500"; + data_width_ratio = "4"; + reg_dimm = "false"; + dq_per_dqs = "8"; + phy_if_type_afi = "true"; + } + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + Default_Module_Name = "ddr2_sdram"; + Required_Device_Family = "STRATIXIIGXLITE,STRATIXIIGX,STRATIXII,STRATIXIII,CYCLONEIII,STRATIXIV,ARRIAII,TARPON,HARDCOPYIII,HARDCOPYIV"; + Pins_Assigned_Automatically = "1"; + View + { + MESSAGES + { + } + } + } + class_version = "8.1"; + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = "pll_ref_clk"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL b + { + name = "soft_reset_n"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL c + { + name = "global_reset_n"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL d + { + name = "reset_phy_clk_n"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL e + { + name = "reset_request_n"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL f + { + name = "phy_clk"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL g + { + name = "local_address"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL h + { + name = "local_size"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL i + { + name = "local_burstbegin"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL j + { + name = "local_read_req"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL k + { + name = "local_write_req"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL l + { + name = "local_ready"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL m + { + name = "local_wdata"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL n + { + name = "local_be"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL o + { + name = "local_rdata_valid"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL p + { + name = "local_rdata"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL q + { + name = "mem_clk"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL r + { + name = "mem_cs_n"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL s + { + name = "mem_addr"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL t + { + name = "mem_ba"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL u + { + name = "mem_ras_n"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL v + { + name = "mem_cas_n"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL w + { + name = "mem_we_n"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL x + { + name = "mem_dm"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL y + { + name = "mem_dq"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL z + { + name = "mem_dqs"; + radix = "hexadecimal"; + format = "Logic"; + } + SIGNAL aa + { + name = "mem_cke"; + radix = "hexadecimal"; + format = "Logic"; + } + } + } + } + MODULE opencores_i2c_master_0 + { + SLAVE s1 + { + PORT_WIRING + { + PORT csi_s1clk_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT csi_s1clk_reset + { + type = "reset"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT ins_intout_irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_writedata + { + type = "writedata"; + width = "8"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_readdata + { + type = "readdata"; + width = "8"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "8"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x1c100000"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "11"; + } + Base_Address = "0x1c100000"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT coe_ext_export_scl + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT coe_ext_export_sda + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "opencores_i2c_master"; + gtf_class_version = "2.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_bit_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_byte_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_top.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/oc_i2c_master.vhd,__PROJECT_DIRECTORY__/opencores_i2c_master_0.vhd"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE opencores_i2c_master_1 + { + SLAVE s1 + { + PORT_WIRING + { + PORT csi_s1clk_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT csi_s1clk_reset + { + type = "reset"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT ins_intout_irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_writedata + { + type = "writedata"; + width = "8"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_readdata + { + type = "readdata"; + width = "8"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "8"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x1c200000"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "6"; + } + Base_Address = "0x1c200000"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT coe_ext_export_scl + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT coe_ext_export_sda + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "opencores_i2c_master"; + gtf_class_version = "2.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_bit_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_byte_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_top.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/oc_i2c_master.vhd,__PROJECT_DIRECTORY__/opencores_i2c_master_1.vhd"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE opencores_i2c_master_2 + { + SLAVE s1 + { + PORT_WIRING + { + PORT csi_s1clk_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT csi_s1clk_reset + { + type = "reset"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT ins_intout_irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_writedata + { + type = "writedata"; + width = "8"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_readdata + { + type = "readdata"; + width = "8"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "8"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x1c300000"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "7"; + } + Base_Address = "0x1c300000"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT coe_ext_export_scl + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT coe_ext_export_sda + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "opencores_i2c_master"; + gtf_class_version = "2.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_bit_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_byte_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_top.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/oc_i2c_master.vhd,__PROJECT_DIRECTORY__/opencores_i2c_master_2.vhd"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE opencores_i2c_master_3 + { + SLAVE s1 + { + PORT_WIRING + { + PORT csi_s1clk_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT csi_s1clk_reset + { + type = "reset"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT ins_intout_irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_writedata + { + type = "writedata"; + width = "8"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_readdata + { + type = "readdata"; + width = "8"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "8"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x1c400000"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "8"; + } + Base_Address = "0x1c400000"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT coe_ext_export_scl + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT coe_ext_export_sda + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "opencores_i2c_master"; + gtf_class_version = "2.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_bit_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_byte_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_top.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/oc_i2c_master.vhd,__PROJECT_DIRECTORY__/opencores_i2c_master_3.vhd"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE opencores_i2c_master_4 + { + SLAVE s1 + { + PORT_WIRING + { + PORT csi_s1clk_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT csi_s1clk_reset + { + type = "reset"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT ins_intout_irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_writedata + { + type = "writedata"; + width = "8"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_readdata + { + type = "readdata"; + width = "8"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "8"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x1c500000"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "9"; + } + Base_Address = "0x1c500000"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT coe_ext_export_scl + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + PORT coe_ext_export_sda + { + type = "export"; + width = "1"; + direction = "inout"; + Is_Enabled = "1"; + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "opencores_i2c_master"; + gtf_class_version = "2.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_bit_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_byte_ctrl.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/i2c_master_top.vhd,/home/walter/Libs/VHDL/sopc/opencores/i2c_master/oc_i2c_master.vhd,__PROJECT_DIRECTORY__/opencores_i2c_master_4.vhd"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE axonbus_0 + { + SLAVE ctrl + { + PORT_WIRING + { + PORT csi_ctrlclk_reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT csi_ctrlclk_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT ins_ctrlirq_irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_ctrl_read + { + type = "read"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_ctrl_write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_ctrl_readdata + { + type = "readdata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_ctrl_writedata + { + type = "writedata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_ctrl_address + { + type = "address"; + width = "4"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "16"; + Address_Width = "4"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x1c600000"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "10"; + } + Base_Address = "0x1c600000"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT coe_export_txena + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + MASTER uartm + { + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Irq_Scheme = "individual_requests"; + Bus_Type = "avalon"; + Is_Asynchronous = "0"; + DBS_Big_Endian = "0"; + Adapts_To = ""; + Do_Stream_Reads = "0"; + Do_Stream_Writes = "0"; + Max_Address_Width = "32"; + Data_Width = "16"; + Address_Width = "8"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + } + PORT_WIRING + { + PORT avm_uartm_irq + { + type = "irq"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avm_uartm_waitrequest + { + type = "waitrequest"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avm_uartm_address + { + type = "address"; + width = "8"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avm_uartm_read + { + type = "read"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avm_uartm_readdata + { + type = "readdata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avm_uartm_write + { + type = "write"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avm_uartm_writedata + { + type = "writedata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + } + MEMORY_MAP + { + Entry uart_1/s1 + { + address = "0x00000000"; + span = "0x00000020"; + is_bridge = "0"; + } + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "axonbus"; + gtf_class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "/home/walter/Libs/VHDL/sopc/axon/axonbus/axonbus.vhd,__PROJECT_DIRECTORY__/axonbus_0.vhd"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE uart_1 + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset_n + { + type = "reset_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT irq + { + type = "irq"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "3"; + direction = "input"; + Is_Enabled = "1"; + } + PORT begintransfer + { + type = "begintransfer"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT read_n + { + type = "read_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write_n + { + type = "write_n"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "16"; + direction = "input"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "16"; + direction = "output"; + Is_Enabled = "1"; + } + PORT dataavailable + { + type = "dataavailable"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT readyfordata + { + type = "readyfordata"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Has_IRQ = "1"; + Bus_Type = "avalon"; + Write_Wait_States = "1cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "1"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "16"; + Address_Width = "3"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY axonbus_0/uartm + { + priority = "1"; + Offset_Address = "0x00000000"; + } + IRQ_MASTER axonbus_0/uartm + { + IRQ_Number = "0"; + } + Base_Address = "0x00000000"; + Address_Group = "0"; + } + } + PORT_WIRING + { + PORT rxd + { + type = "export"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT txd + { + type = "export"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + PORT cts_n + { + direction = "input"; + width = "1"; + Is_Enabled = "0"; + } + PORT rts_n + { + direction = "output"; + width = "1"; + Is_Enabled = "0"; + } + } + class = "altera_avalon_uart"; + class_version = "7.080900"; + iss_model_name = "altera_avalon_uart"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + Iss_Launch_Telnet = "0"; + Top_Level_Ports_Are_Enumerated = "1"; + View + { + Settings_Summary = "9-bit UART with 115200 baud, <br> + 1 stop bits and N parity"; + Is_Collapsed = "1"; + MESSAGES + { + } + } + Clock_Source = "clk_66"; + Has_Clock = "1"; + } + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = " Bus Interface"; + format = "Divider"; + } + SIGNAL b + { + name = "chipselect"; + } + SIGNAL c + { + name = "address"; + radix = "hexadecimal"; + } + SIGNAL d + { + name = "writedata"; + radix = "hexadecimal"; + } + SIGNAL e + { + name = "readdata"; + radix = "hexadecimal"; + } + SIGNAL f + { + name = " Internals"; + format = "Divider"; + } + SIGNAL g + { + name = "tx_ready"; + } + SIGNAL h + { + name = "tx_data"; + radix = "ascii"; + } + SIGNAL i + { + name = "rx_char_ready"; + } + SIGNAL j + { + name = "rx_data"; + radix = "ascii"; + } + } + INTERACTIVE_OUT log + { + enable = "0"; + file = "_log_module.txt"; + radix = "ascii"; + signals = "temp,list"; + exe = "perl -- tail-f.pl"; + } + INTERACTIVE_IN drive + { + enable = "0"; + file = "_input_data_stream.dat"; + mutex = "_input_data_mutex.dat"; + log = "_in.log"; + rate = "100"; + signals = "temp,list"; + exe = "perl -- uart.pl"; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + baud = "115200"; + data_bits = "9"; + fixed_baud = "1"; + parity = "N"; + stop_bits = "1"; + sync_reg_depth = "2"; + use_cts_rts = "0"; + use_eop_register = "0"; + sim_true_baud = "0"; + sim_char_stream = ""; + } + HDL_INFO + { + Precompiled_Simulation_Library_Files = ""; + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart_1.v"; + Synthesis_Only_Files = ""; + } + } + MODULE remote_update_cycloneiii_0 + { + SLAVE s1 + { + PORT_WIRING + { + PORT clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT reset + { + type = "reset"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT writedata + { + type = "writedata"; + width = "32"; + direction = "input"; + Is_Enabled = "1"; + } + PORT readdata + { + type = "readdata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + PORT address + { + type = "address"; + width = "6"; + direction = "input"; + Is_Enabled = "1"; + } + PORT chipselect + { + type = "chipselect"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT write + { + type = "write"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT read + { + type = "read"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT waitrequest + { + type = "waitrequest"; + width = "1"; + direction = "output"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Read_Wait_States = "peripheral_controlled"; + Write_Wait_States = "peripheral_controlled"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "2"; + Is_Memory_Device = "0"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "32"; + Address_Width = "6"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x11000000"; + } + Base_Address = "0x11000000"; + Address_Group = "0"; + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "altera_avalon_remote_update_cycloneiii"; + gtf_class_version = "9.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_33"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "__PROJECT_DIRECTORY__/remote_update_cycloneiii_0.vo"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } + MODULE avalon_bus_contents_0 + { + SLAVE s1 + { + PORT_WIRING + { + PORT csi_s1clk_clk + { + type = "clk"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_read + { + type = "read"; + width = "1"; + direction = "input"; + Is_Enabled = "1"; + } + PORT avs_s1_readdata + { + type = "readdata"; + width = "32"; + direction = "output"; + Is_Enabled = "1"; + } + PORT avs_s1_address + { + type = "address"; + width = "9"; + direction = "input"; + Is_Enabled = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Write_Wait_States = "0cycles"; + Read_Wait_States = "1cycles"; + Hold_Time = "0cycles"; + Setup_Time = "0cycles"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Well_Behaved_Waitrequest = "0"; + Is_Nonvolatile_Storage = "0"; + Read_Latency = "0"; + Is_Memory_Device = "1"; + Maximum_Pending_Read_Transactions = "0"; + Minimum_Uninterrupted_Run_Length = "1"; + Accepts_Internal_Connections = "1"; + Write_Latency = "0"; + Is_Flash = "0"; + Data_Width = "32"; + Address_Width = "9"; + Maximum_Burst_Size = "1"; + Register_Incoming_Signals = "0"; + Register_Outgoing_Signals = "0"; + Interleave_Bursts = "0"; + Linewrap_Bursts = "0"; + Burst_On_Burst_Boundaries_Only = "0"; + Always_Burst_Max_Burst = "0"; + Is_Big_Endian = "0"; + Is_Enabled = "1"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + Offset_Address = "0x1c000000"; + } + Base_Address = "0x1c000000"; + Address_Group = "0"; + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + } + class = "no_legacy_module"; + class_version = "7.080900"; + gtf_class_name = "avalon_bus_contents"; + gtf_class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Do_Not_Generate = "1"; + Instantiate_In_System_Module = "1"; + Is_Bridge = "0"; + Is_Enabled = "1"; + Clock_Source = "clk_66"; + Has_Clock = "1"; + View + { + MESSAGES + { + } + } + } + HDL_INFO + { + Simulation_HDL_Files = "__PROJECT_DIRECTORY__/avalon_bus_contents_0.vhd"; + } + WIZARD_SCRIPT_ARGUMENTS + { + terminated_ports + { + } + } + } +} diff --git a/recipes/linux/linux-nios2_2.6.28.bb b/recipes/linux/linux-nios2_2.6.28.bb new file mode 100644 index 0000000000..031f4f5592 --- /dev/null +++ b/recipes/linux/linux-nios2_2.6.28.bb @@ -0,0 +1,36 @@ +INHIBIT_DEFAULT_DEPS = "1" +DEPENDS += "unifdef-native" +PR = "r3" + +FILESPATH = "${FILE_DIRNAME}/${PN}/${PV}" + +#SRC_URI = "git://sopc.et.ntust.edu.tw/git/linux-2.6.git;branch=test-nios2;tags=3146b39c185f8a436d430132457e84fa1d8f8208 \ +SRC_URI = "http://127.0.0.1/linux-nios2-2.6.28-git.tbz \ + file://procinfo.h \ + file://system.ptf" +SRC_URI += "file://defconfig" + +S = "${WORKDIR}/linux-2.6" + +COMPATIBLE_HOST = 'nios2.*-linux.*' +COMPATIBLE_MACHINE = '(nios2|sygeg1)' + +inherit kernel + +ARCH = "nios2" +KERNEL_IMAGETYPE = "zImage" + + +do_configure() { + rm -f ${S}/.config + + if [ ! -e ${WORKDIR}/defconfig ]; then + die "No default configuration for ${MACHINE} available." + fi + + echo "CONFIG_INITRAMFS_SOURCE=\"${DEPLOY_DIR_IMAGE}/initramfs_root.cpio\"" >> ${S}/.config + sed -e '/CONFIG_INITRAMFS_SOURCE/d' '${WORKDIR}/defconfig' >>'${S}/.config' + + oe_runmake hwselect SYSPTF=../system.ptf CPU_SELECTION=1 MEM_SELECTION=2 ARCH=$ARCH + yes '' | oe_runmake oldconfig +} diff --git a/recipes/linux/linux-openmoko-2.6.31/0001-DRM-for-platform-devices.patch b/recipes/linux/linux-openmoko-2.6.31/0001-DRM-for-platform-devices.patch new file mode 100644 index 0000000000..2c9b611165 --- /dev/null +++ b/recipes/linux/linux-openmoko-2.6.31/0001-DRM-for-platform-devices.patch @@ -0,0 +1,458 @@ +From da270cf61e67d912b38e314719511efc4c2ea085 Mon Sep 17 00:00:00 2001 +From: Thomas White <taw@bitwiz.org.uk> +Date: Tue, 20 Oct 2009 15:52:30 +0200 +Subject: [PATCH 1/4] DRM for platform devices + +This modifies the DRM core in a small number of places to allow platform +devices to be used for direct rendering, alongside PCI devices. + +Signed-off-by: Thomas White <taw@bitwiz.org.uk> +--- + drivers/gpu/drm/Kconfig | 2 +- + drivers/gpu/drm/drm_bufs.c | 2 +- + drivers/gpu/drm/drm_drv.c | 27 ++++++++++ + drivers/gpu/drm/drm_info.c | 27 ++++++++-- + drivers/gpu/drm/drm_ioctl.c | 118 ++++++++++++++++++++++++++++++------------- + drivers/gpu/drm/drm_stub.c | 76 +++++++++++++++++++++++++++- + drivers/gpu/drm/drm_sysfs.c | 6 ++- + include/drm/drmP.h | 13 +++++ + 8 files changed, 224 insertions(+), 47 deletions(-) + +diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig +index 39b393d..cef3d2c 100644 +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -6,7 +6,7 @@ + # + menuconfig DRM + tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)" +- depends on (AGP || AGP=n) && PCI && !EMULATED_CMPXCHG && MMU ++ depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU + select I2C + select I2C_ALGOBIT + help +diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c +index 6246e3f..b9f15bf 100644 +--- a/drivers/gpu/drm/drm_bufs.c ++++ b/drivers/gpu/drm/drm_bufs.c +@@ -188,7 +188,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset, + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +-#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__) ++#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__arm__) + if (map->offset + (map->size-1) < map->offset || + map->offset < virt_to_phys(high_memory)) { + kfree(map); +diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c +index b39d7bf..a7861e8 100644 +--- a/drivers/gpu/drm/drm_drv.c ++++ b/drivers/gpu/drm/drm_drv.c +@@ -247,6 +247,7 @@ int drm_lastclose(struct drm_device * dev) + */ + int drm_init(struct drm_driver *driver) + { ++#ifdef CONFIG_PCI + struct pci_dev *pdev = NULL; + const struct pci_device_id *pid; + int i; +@@ -280,11 +281,37 @@ int drm_init(struct drm_driver *driver) + drm_get_dev(pdev, pid, driver); + } + } ++#endif + return 0; + } + + EXPORT_SYMBOL(drm_init); + ++/** ++ * Call this to associate a drm_driver with a platform_device. ++ * ++ * \return zero on success or a negative number on failure. ++ * ++ * This is a replacement for drm_init(), but for platform drivers. ++ * In this case, the caller must provide the matching platform_device ++ * ++ * since there is no physical bus to scan through. ++ * ++ * \sa drm_init ++ * ++ */ ++int drm_platform_init(struct drm_driver *driver, struct platform_device *pdev, ++ void *priv) ++{ ++ DRM_DEBUG("\n"); ++ ++ INIT_LIST_HEAD(&driver->device_list); ++ ++ return drm_get_platform_dev(pdev, driver, priv); ++} ++ ++EXPORT_SYMBOL(drm_platform_init); ++ + void drm_exit(struct drm_driver *driver) + { + struct drm_device *dev, *tmp; +diff --git a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c +index f0f6c6b..838c2ee 100644 +--- a/drivers/gpu/drm/drm_info.c ++++ b/drivers/gpu/drm/drm_info.c +@@ -52,12 +52,28 @@ int drm_name_info(struct seq_file *m, void *data) + return 0; + + if (master->unique) { +- seq_printf(m, "%s %s %s\n", +- dev->driver->pci_driver.name, +- pci_name(dev->pdev), master->unique); ++ ++ if (drm_core_is_platform(dev)) { ++ seq_printf(m, "%s %s %s\n", ++ dev->driver->name, ++ dev_name(&dev->platform_dev->dev), ++ master->unique); ++ } else { ++ seq_printf(m, "%s %s %s\n", ++ dev->driver->pci_driver.name, ++ pci_name(dev->pdev), master->unique); ++ } ++ + } else { +- seq_printf(m, "%s %s\n", dev->driver->pci_driver.name, +- pci_name(dev->pdev)); ++ ++ if (drm_core_is_platform(dev)) { ++ seq_printf(m, "%s %s\n", dev->driver->name, ++ dev_name(&dev->platform_dev->dev)); ++ } else { ++ seq_printf(m, "%s %s\n", dev->driver->pci_driver.name, ++ pci_name(dev->pdev)); ++ } ++ + } + + return 0; +@@ -325,4 +341,3 @@ int drm_vma_info(struct seq_file *m, void *data) + } + + #endif +- +diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c +index 9b9ff46..133ef29 100644 +--- a/drivers/gpu/drm/drm_ioctl.c ++++ b/drivers/gpu/drm/drm_ioctl.c +@@ -83,7 +83,6 @@ int drm_setunique(struct drm_device *dev, void *data, + { + struct drm_unique *u = data; + struct drm_master *master = file_priv->master; +- int domain, bus, slot, func, ret; + + if (master->unique_len || master->unique) + return -EBUSY; +@@ -101,28 +100,46 @@ int drm_setunique(struct drm_device *dev, void *data, + + master->unique[master->unique_len] = '\0'; + +- dev->devname = kmalloc(strlen(dev->driver->pci_driver.name) + +- strlen(master->unique) + 2, GFP_KERNEL); +- if (!dev->devname) +- return -ENOMEM; ++ if ( !drm_core_is_platform(dev) ) { + +- sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, +- master->unique); ++ int domain, bus, slot, func, ret; + +- /* Return error if the busid submitted doesn't match the device's actual +- * busid. +- */ +- ret = sscanf(master->unique, "PCI:%d:%d:%d", &bus, &slot, &func); +- if (ret != 3) +- return -EINVAL; +- domain = bus >> 8; +- bus &= 0xff; ++ /* PCI device */ ++ dev->devname = kmalloc(strlen(dev->driver->pci_driver.name) + ++ strlen(master->unique) + 2, GFP_KERNEL); ++ if (!dev->devname) ++ return -ENOMEM; + +- if ((domain != drm_get_pci_domain(dev)) || +- (bus != dev->pdev->bus->number) || +- (slot != PCI_SLOT(dev->pdev->devfn)) || +- (func != PCI_FUNC(dev->pdev->devfn))) +- return -EINVAL; ++ sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, ++ master->unique); ++ ++ /* Return error if the busid submitted doesn't match the ++ * device's actual busid. ++ */ ++ ret = sscanf(master->unique, "PCI:%d:%d:%d", &bus, &slot, &func); ++ if (ret != 3) ++ return -EINVAL; ++ domain = bus >> 8; ++ bus &= 0xff; ++ ++ if ((domain != drm_get_pci_domain(dev)) || ++ (bus != dev->pdev->bus->number) || ++ (slot != PCI_SLOT(dev->pdev->devfn)) || ++ (func != PCI_FUNC(dev->pdev->devfn))) ++ return -EINVAL; ++ ++ } else { ++ ++ /* Platform device */ ++ dev->devname = kmalloc(strlen(dev->driver->name) + ++ strlen(master->unique) + 2, GFP_KERNEL); ++ if (!dev->devname) ++ return -ENOMEM; ++ ++ sprintf(dev->devname, "%s@%s", dev->driver->name, ++ master->unique); ++ ++ } + + return 0; + } +@@ -141,23 +158,52 @@ static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv) + if (master->unique == NULL) + return -ENOMEM; + +- len = snprintf(master->unique, master->unique_len, "pci:%04x:%02x:%02x.%d", +- drm_get_pci_domain(dev), +- dev->pdev->bus->number, +- PCI_SLOT(dev->pdev->devfn), +- PCI_FUNC(dev->pdev->devfn)); +- if (len >= master->unique_len) +- DRM_ERROR("buffer overflow"); +- else +- master->unique_len = len; +- +- dev->devname = kmalloc(strlen(dev->driver->pci_driver.name) + +- master->unique_len + 2, GFP_KERNEL); +- if (dev->devname == NULL) +- return -ENOMEM; ++ if ( !drm_core_is_platform(dev) ) { ++ ++ /* PCI device */ + +- sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, +- master->unique); ++ len = snprintf(master->unique, master->unique_len, ++ "pci:%04x:%02x:%02x.%d", ++ drm_get_pci_domain(dev), ++ dev->pdev->bus->number, ++ PCI_SLOT(dev->pdev->devfn), ++ PCI_FUNC(dev->pdev->devfn)); ++ if (len >= master->unique_len) ++ DRM_ERROR("buffer overflow"); ++ else ++ master->unique_len = len; ++ ++ dev->devname = kmalloc(strlen(dev->driver->pci_driver.name) + ++ master->unique_len + 2, GFP_KERNEL); ++ if (dev->devname == NULL) ++ return -ENOMEM; ++ ++ sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, ++ master->unique); ++ ++ } else { ++ ++ /* Platform device */ ++ ++ int len; ++ ++ len = snprintf(master->unique, master->unique_len, ++ "platform:%s", dev->platform_dev->name); ++ ++ if (len >= master->unique_len) ++ DRM_ERROR("buffer overflow"); ++ else ++ master->unique_len = len; ++ ++ dev->devname = kmalloc(strlen(dev->driver->name) ++ + master->unique_len + 2, GFP_KERNEL); ++ if (dev->devname == NULL) ++ return -ENOMEM; ++ ++ sprintf(dev->devname, "%s@%s", dev->driver->name, ++ master->unique); ++ ++ } + + return 0; + } +diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c +index 55bb8a8..a7069ad 100644 +--- a/drivers/gpu/drm/drm_stub.c ++++ b/drivers/gpu/drm/drm_stub.c +@@ -230,8 +230,10 @@ static int drm_fill_in_dev(struct drm_device * dev, struct pci_dev *pdev, + idr_init(&dev->drw_idr); + + dev->pdev = pdev; +- dev->pci_device = pdev->device; +- dev->pci_vendor = pdev->vendor; ++ if (pdev) { ++ dev->pci_device = pdev->device; ++ dev->pci_vendor = pdev->vendor; ++ } + + #ifdef __alpha__ + dev->hose = pdev->sysdata; +@@ -449,6 +451,76 @@ err_g1: + EXPORT_SYMBOL(drm_get_dev); + + /** ++ * ++ * Register a platform device as a DRM device ++ * ++ * \param pdev - platform device structure ++ * \param driver - the matching drm_driver structure ++ * \return zero on success or a negative number on failure. ++ * ++ * Attempt to gets inter module "drm" information. If we are first ++ * then register the character device and inter module information. ++ * Try and register, if we fail to register, backout previous work. ++ * ++ * \sa drm_get_dev ++ */ ++int drm_get_platform_dev(struct platform_device *pdev, ++ struct drm_driver *driver, void *priv) ++{ ++ struct drm_device *dev; ++ int ret; ++ DRM_DEBUG("\n"); ++ ++ dev = kmalloc(sizeof(*dev), GFP_KERNEL); ++ if (!dev) ++ return -ENOMEM; ++ dev->dev_private = priv; ++ ++ if ((ret = drm_fill_in_dev(dev, NULL, NULL, driver))) { ++ printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); ++ goto err_g1; ++ } ++ dev->platform_dev = pdev; ++ ++ if (drm_core_check_feature(dev, DRIVER_MODESET)) { ++ ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL); ++ if (ret) ++ goto err_g2; ++ } ++ ++ if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY))) ++ goto err_g3; ++ ++ if (dev->driver->load) { ++ ret = dev->driver->load(dev, 0); ++ if (ret) ++ goto err_g3; ++ } ++ ++ /* setup the grouping for the legacy output */ ++ if (drm_core_check_feature(dev, DRIVER_MODESET)) { ++ ret = drm_mode_group_init_legacy_group(dev, &dev->primary->mode_group); ++ if (ret) ++ goto err_g3; ++ } ++ ++ list_add_tail(&dev->driver_item, &driver->device_list); ++ ++ DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", ++ driver->name, driver->major, driver->minor, driver->patchlevel, ++ driver->date, dev->primary->index); ++ ++ return 0; ++ ++err_g3: ++ drm_put_minor(&dev->primary); ++err_g2: ++err_g1: ++ kfree(dev); ++ return ret; ++} ++ ++/** + * Put a secondary minor number. + * + * \param sec_minor - structure to be released +diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c +index f7a615b..fea2b71 100644 +--- a/drivers/gpu/drm/drm_sysfs.c ++++ b/drivers/gpu/drm/drm_sysfs.c +@@ -482,7 +482,11 @@ int drm_sysfs_device_add(struct drm_minor *minor) + int err; + char *minor_str; + +- minor->kdev.parent = &minor->dev->pdev->dev; ++ if (minor->dev->pdev) { ++ minor->kdev.parent = &minor->dev->pdev->dev; ++ } else { ++ minor->kdev.parent = &minor->dev->platform_dev->dev; ++ } + minor->kdev.class = drm_class; + minor->kdev.release = drm_sysfs_device_release; + minor->kdev.devt = minor->device; +diff --git a/include/drm/drmP.h b/include/drm/drmP.h +index 45b67d9..66253f9 100644 +--- a/include/drm/drmP.h ++++ b/include/drm/drmP.h +@@ -55,6 +55,7 @@ + #include <linux/mm.h> + #include <linux/cdev.h> + #include <linux/mutex.h> ++#include <linux/platform_device.h> + #if defined(__alpha__) || defined(__powerpc__) + #include <asm/pgtable.h> /* For pte_wrprotect */ + #endif +@@ -113,6 +114,7 @@ extern void drm_ut_debug_printk(unsigned int request_level, + #define DRIVER_IRQ_VBL2 0x800 + #define DRIVER_GEM 0x1000 + #define DRIVER_MODESET 0x2000 ++#define DRIVER_IS_PLATFORM 0x4000 + + /***********************************************************************/ + /** \name Begin the DRM... */ +@@ -981,6 +983,7 @@ struct drm_device { + wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */ + + struct drm_agp_head *agp; /**< AGP data */ ++ struct platform_device *platform_dev; /**< platform device structure */ + + struct pci_dev *pdev; /**< PCI device structure */ + int pci_vendor; /**< PCI vendor id */ +@@ -1091,12 +1094,20 @@ static inline int drm_mtrr_del(int handle, unsigned long offset, + } + #endif + ++static inline int drm_core_is_platform(struct drm_device *dev) ++{ ++ return drm_core_check_feature(dev, DRIVER_IS_PLATFORM); ++} ++ + /******************************************************************/ + /** \name Internal function definitions */ + /*@{*/ + + /* Driver support (drm_drv.h) */ + extern int drm_init(struct drm_driver *driver); ++extern int drm_platform_init(struct drm_driver *driver, ++ struct platform_device *pdev, ++ void *dev_private); + extern void drm_exit(struct drm_driver *driver); + extern int drm_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +@@ -1314,6 +1325,8 @@ extern int drm_dropmaster_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); + struct drm_master *drm_master_create(struct drm_minor *minor); + extern struct drm_master *drm_master_get(struct drm_master *master); ++extern int drm_get_platform_dev(struct platform_device *pdev, ++ struct drm_driver *driver, void *priv); + extern void drm_master_put(struct drm_master **master); + extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, + struct drm_driver *driver); +-- +1.6.5.3 + diff --git a/recipes/linux/linux-openmoko-2.6.31/0001-gta02_defconfig-Enable-GLAMO_DRM.patch b/recipes/linux/linux-openmoko-2.6.31/0001-gta02_defconfig-Enable-GLAMO_DRM.patch new file mode 100644 index 0000000000..94fced1741 --- /dev/null +++ b/recipes/linux/linux-openmoko-2.6.31/0001-gta02_defconfig-Enable-GLAMO_DRM.patch @@ -0,0 +1,37 @@ +From 6cc1ca971b357db4760a40729728c05e403857d7 Mon Sep 17 00:00:00 2001 +From: Martin Jansa <Martin.Jansa@gmail.com> +Date: Thu, 19 Nov 2009 11:39:51 +0100 +Subject: [PATCH] gta02_defconfig: Enable GLAMO_DRM + +--- + arch/arm/configs/gta02_defconfig | 7 ++++++- + 1 files changed, 6 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/configs/gta02_defconfig b/arch/arm/configs/gta02_defconfig +index 0f53baf..1cce709 100644 +--- a/arch/arm/configs/gta02_defconfig ++++ b/arch/arm/configs/gta02_defconfig +@@ -1000,14 +1000,19 @@ CONFIG_PCF50633_GPIO=y + # CONFIG_EZX_PCAP is not set + # CONFIG_MFD_PCF50606 is not set + CONFIG_MFD_GLAMO=y +-CONFIG_MFD_GLAMO_FB=y ++# CONFIG_MFD_GLAMO_FB is not set + CONFIG_MFD_GLAMO_GPIO=y + CONFIG_MFD_GLAMO_MCI=y ++CONFIG_MFD_GLAMO_DRM=y + # CONFIG_MEDIA_SUPPORT is not set + + # + # Graphics support + # ++CONFIG_DRM=y ++# CONFIG_DRM_MGA is not set ++# CONFIG_DRM_VIA is not set ++# CONFIG_DRM_SAVAGE is not set + # CONFIG_VGASTATE is not set + CONFIG_VIDEO_OUTPUT_CONTROL=y + CONFIG_FB=y +-- +1.6.5.3 + diff --git a/recipes/linux/linux-openmoko-2.6.31/0002-Glamo-DRM-and-KMS-driver.patch b/recipes/linux/linux-openmoko-2.6.31/0002-Glamo-DRM-and-KMS-driver.patch new file mode 100644 index 0000000000..4a837e9b08 --- /dev/null +++ b/recipes/linux/linux-openmoko-2.6.31/0002-Glamo-DRM-and-KMS-driver.patch @@ -0,0 +1,3818 @@ +From 01435b6f8fba2031e6941756a6a4e42be553f4a0 Mon Sep 17 00:00:00 2001 +From: Thomas White <taw@bitwiz.org.uk> +Date: Tue, 20 Oct 2009 16:14:55 +0200 +Subject: [PATCH 2/4] Glamo DRM and KMS driver + +This adds the Glamo DRM and KMS driver, but not the modifications needed +elsewhere to support it. + +Signed-off-by: Thomas White <taw@bitwiz.org.uk> +--- + drivers/gpu/drm/drm_stub.c | 2 +- + drivers/mfd/glamo/Kconfig | 15 + + drivers/mfd/glamo/Makefile | 5 +- + drivers/mfd/glamo/glamo-buffer.c | 372 ++++++++++++++ + drivers/mfd/glamo/glamo-buffer.h | 60 +++ + drivers/mfd/glamo/glamo-cmdq.c | 528 ++++++++++++++++++++ + drivers/mfd/glamo/glamo-cmdq.h | 49 ++ + drivers/mfd/glamo/glamo-display.c | 875 +++++++++++++++++++++++++++++++++ + drivers/mfd/glamo/glamo-display.h | 39 ++ + drivers/mfd/glamo/glamo-drm-drv.c | 453 +++++++++++++++++ + drivers/mfd/glamo/glamo-drm-private.h | 156 ++++++ + drivers/mfd/glamo/glamo-fence.c | 329 +++++++++++++ + drivers/mfd/glamo/glamo-fence.h | 36 ++ + drivers/mfd/glamo/glamo-kms-fb.c | 540 ++++++++++++++++++++ + drivers/mfd/glamo/glamo-kms-fb.h | 41 ++ + include/drm/Kbuild | 1 + + include/drm/glamo_drm.h | 153 ++++++ + 17 files changed, 3652 insertions(+), 2 deletions(-) + create mode 100644 drivers/mfd/glamo/glamo-buffer.c + create mode 100644 drivers/mfd/glamo/glamo-buffer.h + create mode 100644 drivers/mfd/glamo/glamo-cmdq.c + create mode 100644 drivers/mfd/glamo/glamo-cmdq.h + create mode 100644 drivers/mfd/glamo/glamo-display.c + create mode 100644 drivers/mfd/glamo/glamo-display.h + create mode 100644 drivers/mfd/glamo/glamo-drm-drv.c + create mode 100644 drivers/mfd/glamo/glamo-drm-private.h + create mode 100644 drivers/mfd/glamo/glamo-fence.c + create mode 100644 drivers/mfd/glamo/glamo-fence.h + create mode 100644 drivers/mfd/glamo/glamo-kms-fb.c + create mode 100644 drivers/mfd/glamo/glamo-kms-fb.h + create mode 100644 include/drm/glamo_drm.h + +diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c +index a7069ad..5e3d65a 100644 +--- a/drivers/gpu/drm/drm_stub.c ++++ b/drivers/gpu/drm/drm_stub.c +@@ -471,7 +471,7 @@ int drm_get_platform_dev(struct platform_device *pdev, + int ret; + DRM_DEBUG("\n"); + +- dev = kmalloc(sizeof(*dev), GFP_KERNEL); ++ dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + dev->dev_private = priv; +diff --git a/drivers/mfd/glamo/Kconfig b/drivers/mfd/glamo/Kconfig +index 8c93bcb..375e5db 100644 +--- a/drivers/mfd/glamo/Kconfig ++++ b/drivers/mfd/glamo/Kconfig +@@ -39,3 +39,18 @@ config MFD_GLAMO_MCI + neo1973 GTA-02. + + If unsure, say N. ++ ++config MFD_GLAMO_DRM ++ tristate "Glamo direct rendering and kernel modesetting support" ++ depends on MFD_GLAMO && DRM ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ help ++ Direct Rendering Manager interface for the S-Media Glamo chip, as ++ used in Openmoko FreeRunner (GTA02). ++ ++ This DRM driver includes kernel modesetting (KMS) support. As such, ++ do not select MFD_GLAMO_FB above if you choose to enable this option. ++ ++ If unsure, say N. +diff --git a/drivers/mfd/glamo/Makefile b/drivers/mfd/glamo/Makefile +index ebf26f7..d5ebf8f 100644 +--- a/drivers/mfd/glamo/Makefile ++++ b/drivers/mfd/glamo/Makefile +@@ -1,5 +1,5 @@ + # +-# Makefile for the Smedia Glamo framebuffer driver ++# Makefile for the Smedia Glamo driver(s) + # + + obj-$(CONFIG_MFD_GLAMO) += glamo-core.o +@@ -8,4 +8,7 @@ obj-$(CONFIG_MFD_GLAMO_SPI) += glamo-spi.o + + obj-$(CONFIG_MFD_GLAMO_FB) += glamo-fb.o + obj-$(CONFIG_MFD_GLAMO_MCI) += glamo-mci.o ++obj-$(CONFIG_MFD_GLAMO_DRM) += glamo-drm.o + ++glamo-drm-objs := glamo-drm-drv.o glamo-cmdq.o glamo-buffer.o \ ++ glamo-display.o glamo-kms-fb.o glamo-fence.o +diff --git a/drivers/mfd/glamo/glamo-buffer.c b/drivers/mfd/glamo/glamo-buffer.c +new file mode 100644 +index 0000000..45500d3 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-buffer.c +@@ -0,0 +1,372 @@ ++/* ++ * SMedia Glamo 336x/337x memory management ++ * ++ * Copyright (c) 2009 Thomas White <taw@bitwiz.org.uk> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see <http://www.gnu.org/licenses/>. ++ * ++ * ++ * Memory mapping functions based on i915_gem.c, to which the following ++ * notice applies: ++ * ++ * Copyright © 2008 Intel Corporation ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++ * IN THE SOFTWARE. ++ * ++ * Authors: ++ * Eric Anholt <eric@anholt.net> ++ */ ++ ++ ++#include <drm/drmP.h> ++#include <drm/glamo_drm.h> ++ ++#include "glamo-drm-private.h" ++#include "glamo-cmdq.h" /* For glamo_cmdq_blank() */ ++ ++ ++struct drm_gem_object *glamo_gem_object_alloc(struct drm_device *dev, int size, ++ int alignment) ++{ ++ struct drm_gem_object *obj; ++ struct glamodrm_handle *gdrm; ++ struct drm_glamo_gem_object *gobj; ++ ++ gdrm = dev->dev_private; ++ ++ size = roundup(size, PAGE_SIZE); ++ ++ obj = drm_gem_object_alloc(dev, size); ++ if (obj == NULL) return NULL; ++ ++ /* See glamodrm_gem_init_object() below */ ++ gobj = obj->driver_private; ++ ++ /* Allocate memory for this object in VRAM */ ++ gobj->block = drm_mm_search_free(gdrm->mmgr, size, alignment, 1); ++ if (!gobj->block) { ++ goto fail; ++ } ++ gobj->block = drm_mm_get_block(gobj->block, size, alignment); ++ if (!gobj->block) { ++ goto fail; ++ } ++ ++ /* Arrange for the contents to be set to zero */ ++ glamo_cmdq_blank(gdrm, obj); ++ ++ return obj; ++ ++fail: ++ mutex_lock(&dev->struct_mutex); ++ drm_gem_object_unreference(obj); ++ mutex_unlock(&dev->struct_mutex); ++ printk(KERN_INFO "[glamo-drm] Failed to allocate object\n"); ++ ++ return NULL; ++} ++ ++ ++int glamo_ioctl_gem_create(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ struct drm_glamo_gem_create *args = data; ++ struct drm_gem_object *obj; ++ int handle, ret, alignment, size; ++ ++ /* Alignment must be a non-zero multiple of 2 */ ++ alignment = args->alignment; ++ if ( alignment < 2 ) alignment = 2; ++ if ( alignment % 2 ) alignment *= 2; ++ ++ /* Size must be similarly sanitised */ ++ size = args->size; ++ if ( size < 2 ) size = 2; ++ if ( size % 2 ) size += 1; ++ ++ /* Create an object */ ++ obj = glamo_gem_object_alloc(dev, size, alignment); ++ if ( obj == NULL ) return -ENOMEM; ++ ++ /* Create a handle for it */ ++ ret = drm_gem_handle_create(file_priv, obj, &handle); ++ mutex_lock(&dev->struct_mutex); ++ drm_gem_object_handle_unreference(obj); ++ mutex_unlock(&dev->struct_mutex); ++ if (ret) goto fail; ++ ++ /* Return */ ++ args->handle = handle; ++ return 0; ++ ++fail: ++ mutex_lock(&dev->struct_mutex); ++ drm_gem_object_unreference(obj); ++ mutex_unlock(&dev->struct_mutex); ++ printk(KERN_INFO "[glamo-drm] Failed to allocate object\n"); ++ return ret; ++} ++ ++ ++int glamodrm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) ++{ ++ struct drm_gem_object *obj = vma->vm_private_data; ++ struct drm_device *dev = obj->dev; ++ struct drm_glamo_gem_object *gobj = obj->driver_private; ++ struct glamodrm_handle *gdrm = dev->dev_private; ++ pgoff_t page_offset; ++ unsigned long pfn; ++ int ret = 0; ++ ++ /* We don't use vmf->pgoff since that has the fake offset */ ++ page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> ++ PAGE_SHIFT; ++ ++ mutex_lock(&dev->struct_mutex); ++ pfn = ((gdrm->vram->start + GLAMO_OFFSET_FB + gobj->block->start) ++ >> PAGE_SHIFT) + page_offset; ++ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); ++ mutex_unlock(&dev->struct_mutex); ++ ++ switch (ret) { ++ case -ENOMEM: ++ case -EAGAIN: ++ return VM_FAULT_OOM; ++ case -EFAULT: ++ case -EBUSY: ++ DRM_ERROR("can't insert pfn?? fault or busy...\n"); ++ return VM_FAULT_SIGBUS; ++ default: ++ return VM_FAULT_NOPAGE; ++ } ++} ++ ++ ++static int glamo_gem_create_mmap_offset(struct drm_gem_object *obj) ++{ ++ struct drm_device *dev = obj->dev; ++ struct drm_gem_mm *mm = dev->mm_private; ++ struct drm_glamo_gem_object *gobj = obj->driver_private; ++ struct drm_map_list *list; ++ struct drm_local_map *map; ++ int ret = 0; ++ ++ /* Set the object up for mmap'ing */ ++ list = &obj->map_list; ++ list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); ++ if (!list->map) ++ return -ENOMEM; ++ ++ map = list->map; ++ map->type = _DRM_GEM; ++ map->size = obj->size; ++ map->handle = obj; ++ ++ /* Get a DRM GEM mmap offset allocated... */ ++ list->file_offset_node = drm_mm_search_free(&mm->offset_manager, ++ obj->size / PAGE_SIZE, 0, 0); ++ if (!list->file_offset_node) { ++ DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); ++ ret = -ENOMEM; ++ goto out_free_list; ++ } ++ ++ list->file_offset_node = drm_mm_get_block(list->file_offset_node, ++ obj->size / PAGE_SIZE, 0); ++ if (!list->file_offset_node) { ++ ret = -ENOMEM; ++ goto out_free_list; ++ } ++ ++ list->hash.key = list->file_offset_node->start; ++ if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { ++ DRM_ERROR("failed to add to map hash\n"); ++ goto out_free_mm; ++ } ++ ++ /* By now we should be all set, any drm_mmap request on the offset ++ * below will get to our mmap & fault handler */ ++ gobj->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; ++ ++ return 0; ++ ++out_free_mm: ++ drm_mm_put_block(list->file_offset_node); ++out_free_list: ++ kfree(list->map); ++ ++ return ret; ++} ++ ++ ++int glamo_ioctl_gem_mmap(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ struct drm_glamo_gem_mmap *args = data; ++ struct drm_gem_object *obj; ++ struct drm_glamo_gem_object *gobj; ++ int ret; ++ ++ obj = drm_gem_object_lookup(dev, file_priv, args->handle); ++ if (obj == NULL) ++ return -EBADF; ++ ++ mutex_lock(&dev->struct_mutex); ++ ++ gobj = obj->driver_private; ++ if (!gobj->mmap_offset) { ++ ret = glamo_gem_create_mmap_offset(obj); ++ if (ret) { ++ mutex_unlock(&dev->struct_mutex); ++ return ret; ++ } ++ } ++ ++ args->offset = gobj->mmap_offset; ++ ++ drm_gem_object_unreference(obj); ++ mutex_unlock(&dev->struct_mutex); ++ ++ return 0; ++} ++ ++ ++int glamo_ioctl_gem_pin(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ printk(KERN_INFO "glamo_ioctl_gem_pin\n"); ++ return 0; ++} ++ ++ ++int glamo_ioctl_gem_unpin(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ printk(KERN_INFO "glamo_ioctl_gem_unpin\n"); ++ return 0; ++} ++ ++ ++int glamo_ioctl_gem_pread(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ printk(KERN_INFO "glamo_ioctl_gem_pread\n"); ++ return 0; ++} ++ ++ ++int glamo_ioctl_gem_pwrite(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ printk(KERN_INFO "glamo_ioctl_gem_pwrite\n"); ++ return 0; ++} ++ ++ ++int glamodrm_gem_init_object(struct drm_gem_object *obj) ++{ ++ struct drm_glamo_gem_object *gobj; ++ ++ /* Allocate a private structure */ ++ gobj = kzalloc(sizeof(*gobj), GFP_KERNEL); ++ if (!gobj) return -ENOMEM; ++ ++ obj->driver_private = gobj; ++ gobj->obj = obj; ++ ++ return 0; ++} ++ ++ ++void glamodrm_gem_free_object(struct drm_gem_object *obj) ++{ ++ struct drm_glamo_gem_object *gobj; ++ struct drm_map_list *list; ++ struct drm_device *dev; ++ struct drm_gem_mm *mm; ++ struct drm_local_map *map; ++ ++ dev = obj->dev; ++ mm = dev->mm_private; ++ gobj = obj->driver_private; ++ ++ /* Free the VRAM */ ++ if ( gobj->block != NULL ) { ++ drm_mm_put_block(gobj->block); ++ } ++ ++ /* Release mappings */ ++ list = &obj->map_list; ++ drm_ht_remove_item(&mm->offset_hash, &list->hash); ++ if (list->file_offset_node) { ++ drm_mm_put_block(list->file_offset_node); ++ list->file_offset_node = NULL; ++ } ++ map = list->map; ++ if (map) { ++ kfree(map); ++ list->map = NULL; ++ } ++ ++ /* Free the private structure */ ++ kfree(obj->driver_private); ++} ++ ++ ++/* Memory management initialisation */ ++int glamo_buffer_init(struct glamodrm_handle *gdrm) ++{ ++ gdrm->mmgr = kzalloc(sizeof(struct drm_mm), GFP_KERNEL); ++ drm_mm_init(gdrm->mmgr, 0, gdrm->vram_size); ++ ++ /* Reserve a scratch buffer. We do this outside the protections ++ * of the other GEM code. To do this safely, the allocation must ++ * be a multiple of PAGE_SIZE. */ ++ gdrm->scratch = drm_mm_search_free(gdrm->mmgr, PAGE_SIZE, 4, 1); ++ if ( gdrm->scratch ) { ++ gdrm->scratch = drm_mm_get_block(gdrm->scratch, PAGE_SIZE, 4); ++ } ++ if ( !gdrm->scratch ) { ++ printk(KERN_WARNING "[glamo-drm] Couldn't allocate" ++ " scratch buffer!\n"); ++ } ++ ++ return 0; ++} ++ ++ ++/* Memory management finalisation */ ++int glamo_buffer_final(struct glamodrm_handle *gdrm) ++{ ++ drm_mm_takedown(gdrm->mmgr); ++ kfree(gdrm->mmgr); ++ return 0; ++} +diff --git a/drivers/mfd/glamo/glamo-buffer.h b/drivers/mfd/glamo/glamo-buffer.h +new file mode 100644 +index 0000000..41f18fd +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-buffer.h +@@ -0,0 +1,60 @@ ++/* ++ * SMedia Glamo 336x/337x memory management ++ * ++ * Copyright (c) 2009 Thomas White <taw@bitwiz.org.uk> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __GLAMO_BUFFER_H ++#define __GLAMO_BUFFER_H ++ ++#include <drm/drmP.h> ++ ++#include "glamo-drm-private.h" ++ ++extern int glamo_buffer_init(struct glamodrm_handle *gdrm); ++extern int glamo_buffer_final(struct glamodrm_handle *gdrm); ++ ++extern int glamodrm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); ++ ++extern int glamodrm_gem_init_object(struct drm_gem_object *obj); ++ ++extern void glamodrm_gem_free_object(struct drm_gem_object *obj); ++ ++extern struct drm_gem_object *glamo_gem_object_alloc(struct drm_device *dev, ++ int size, int alignment); ++ ++extern int glamo_ioctl_gem_create(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++ ++extern int glamo_ioctl_gem_mmap(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++ ++extern int glamo_ioctl_gem_pin(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++ ++extern int glamo_ioctl_gem_unpin(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++ ++extern int glamo_ioctl_gem_pread(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++ ++extern int glamo_ioctl_gem_pwrite(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++ ++#endif /* __GLAMO_BUFFER_H */ +diff --git a/drivers/mfd/glamo/glamo-cmdq.c b/drivers/mfd/glamo/glamo-cmdq.c +new file mode 100644 +index 0000000..caedc27 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-cmdq.c +@@ -0,0 +1,528 @@ ++/* ++ * SMedia Glamo 336x/337x command queue handling ++ * ++ * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk> ++ * Copyright (C) 2009 Andreas Pokorny <andreas.pokorny@gmail.com> ++ * Based on xf86-video-glamo (see below for details) ++ * ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Command queue handling functions based on those from xf86-video-glamo, to ++ * which the following licence applies: ++ * ++ * Copyright 2007 OpenMoko, Inc. ++ * Copyright © 2009 Lars-Peter Clausen <lars@metafoo.de> ++ * ++ * This driver is based on Xati, ++ * Copyright 2004 Eric Anholt ++ * ++ * Permission to use, copy, modify, distribute, and sell this software and its ++ * documentation for any purpose is hereby granted without fee, provided that ++ * the above copyright notice appear in all copies and that both that copyright ++ * notice and this permission notice appear in supporting documentation, and ++ * that the name of the copyright holders not be used in advertising or ++ * publicity pertaining to distribution of the software without specific, ++ * written prior permission. The copyright holders make no representations ++ * about the suitability of this software for any purpose. It is provided "as ++ * is" without express or implied warranty. ++ * ++ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, ++ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO ++ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR ++ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, ++ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER ++ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE ++ * OF THIS SOFTWARE. ++ */ ++ ++ ++#include <drm/drmP.h> ++#include <drm/glamo_drm.h> ++ ++#include "glamo-core.h" ++#include "glamo-drm-private.h" ++#include "glamo-regs.h" ++ ++ ++static inline void reg_write(struct glamodrm_handle *gdrm, ++ u_int16_t reg, u_int16_t val) ++{ ++ iowrite16(val, gdrm->reg_base + reg); ++} ++ ++ ++static inline u16 reg_read(struct glamodrm_handle *gdrm, u_int16_t reg) ++{ ++ return ioread16(gdrm->reg_base + reg); ++} ++ ++ ++static u32 glamo_get_read(struct glamodrm_handle *gdrm) ++{ ++ /* we could turn off clock here */ ++ u32 ring_read = reg_read(gdrm, GLAMO_REG_CMDQ_READ_ADDRL); ++ ring_read |= (reg_read(gdrm, GLAMO_REG_CMDQ_READ_ADDRH) & 0x7) << 16; ++ ++ return ring_read; ++} ++ ++ ++static u32 glamo_get_write(struct glamodrm_handle *gdrm) ++{ ++ u32 ring_write = reg_read(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRL); ++ ring_write |= (reg_read(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRH) & 0x7) << 16; ++ ++ return ring_write; ++} ++ ++ ++/* Add commands to the ring buffer */ ++int glamo_add_to_ring(struct glamodrm_handle *gdrm, u16 *addr, ++ unsigned int count) ++{ ++ size_t ring_write, ring_read; ++ size_t new_ring_write; ++ ++ if ( count >= GLAMO_CMDQ_SIZE ) { ++ printk(KERN_WARNING "[glamo-drm] CmdQ submission too large\n"); ++ return -EINVAL; ++ } ++ ++ down(&gdrm->add_to_ring); ++ ++ ring_write = glamo_get_write(gdrm); ++ ++ /* Calculate where we'll end up */ ++ new_ring_write = (ring_write + count) % GLAMO_CMDQ_SIZE; ++ ++ /* Wait until there is enough space to queue the cmd buffer */ ++ if (new_ring_write > ring_write) { ++ /* Loop while the read pointer is between the old and new ++ * positions */ ++ do { ++ ring_read = glamo_get_read(gdrm); ++ } while (ring_read > ring_write && ring_read < new_ring_write); ++ } else { ++ /* Same, but kind of inside-out */ ++ do { ++ ring_read = glamo_get_read(gdrm); ++ } while (ring_read > ring_write || ring_read < new_ring_write); ++ } ++ ++ /* Are we about to wrap around? */ ++ if (ring_write >= new_ring_write) { ++ ++ u32 rest_size; ++ ++ /* Wrap around */ ++ rest_size = GLAMO_CMDQ_SIZE - ring_write; /* Space left */ ++ ++ /* Write from current position to end */ ++ memcpy_toio(gdrm->cmdq_base+ring_write, addr, rest_size); ++ ++ /* Write from start */ ++ memcpy_toio(gdrm->cmdq_base, addr+(rest_size>>1), ++ count - rest_size); ++ ++ /* ring_write being 0 will result in a deadlock because the ++ * cmdq read will never stop. To avoid such an behaviour insert ++ * an empty instruction. */ ++ if (new_ring_write == 0) { ++ iowrite16(0x0000, gdrm->cmdq_base); ++ iowrite16(0x0000, gdrm->cmdq_base + 2); ++ new_ring_write = 4; ++ } ++ ++ } else { ++ ++ memcpy_toio(gdrm->cmdq_base+ring_write, addr, count); ++ ++ } ++ ++ reg_write(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRH, ++ (new_ring_write >> 16) & 0x7f); ++ reg_write(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRL, ++ new_ring_write & 0xffff); ++ ++ if ( !(reg_read(gdrm, GLAMO_REG_CMDQ_STATUS) & 1<<3) ) { ++ printk(KERN_ERR "[glamo-drm] CmdQ decode failure.\n"); ++ } ++ ++ up(&gdrm->add_to_ring); ++ ++ return 0; ++} ++ ++ ++/* Return true for a legal sequence of commands, otherwise false */ ++static int glamo_sanitize_buffer(u16 *cmds, unsigned int count) ++{ ++ /* XXX FIXME TODO: Implementation... */ ++ return 1; ++} ++ ++ ++/* Substitute the real addresses in VRAM for any required buffer objects */ ++static int glamo_do_relocation(struct glamodrm_handle *gdrm, ++ drm_glamo_cmd_buffer_t *cbuf, u16 *cmds, ++ struct drm_device *dev, ++ struct drm_file *file_priv) ++{ ++ u32 *handles; ++ int *offsets; ++ int nobjs = cbuf->nobjs; ++ int i; ++ ++ if ( nobjs > 32 ) return -EINVAL; /* Get real... */ ++ ++ handles = kmalloc(nobjs*sizeof(u32), GFP_KERNEL); ++ if ( handles == NULL ) return -1; ++ if ( copy_from_user(handles, cbuf->objs, nobjs*sizeof(u32)) ) ++ return -1; ++ ++ offsets = kmalloc(nobjs*sizeof(int), GFP_KERNEL); ++ if ( offsets == NULL ) return -1; ++ if ( copy_from_user(offsets, cbuf->obj_pos, nobjs*sizeof(int)) ) ++ return -1; ++ ++ for ( i=0; i<nobjs; i++ ) { ++ ++ u32 handle = handles[i]; ++ int offset = offsets[i]; ++ struct drm_gem_object *obj; ++ struct drm_glamo_gem_object *gobj; ++ u32 addr; ++ u16 addr_low, addr_high; ++ ++ if ( offset > cbuf->bufsz ) { ++ printk(KERN_WARNING "[glamo-drm] Offset out of range" ++ " for this relocation!\n"); ++ goto fail; ++ } ++ ++ obj = drm_gem_object_lookup(dev, file_priv, handle); ++ if ( obj == NULL ) return -1; ++ ++ /* Unref the object now, or it'll never get freed. ++ * This should really happen after the GPU has finished ++ * the commands which are about to be submitted. */ ++ drm_gem_object_unreference(obj); ++ ++ gobj = obj->driver_private; ++ if ( gobj == NULL ) { ++ printk(KERN_WARNING "[glamo-drm] This object has no" ++ " private data!\n"); ++ goto fail; ++ } ++ ++ addr = GLAMO_OFFSET_FB + gobj->block->start; ++ addr_low = addr & 0xffff; ++ addr_high = (addr >> 16) & 0x7f; ++ ++ /* FIXME: Should really check that the register is a ++ * valid one for this relocation. */ ++ ++ *(cmds+(offset/2)+1) = addr_low; ++ *(cmds+(offset/2)+3) = addr_high; ++ ++ } ++ ++ kfree(handles); ++ kfree(offsets); ++ return 0; ++ ++fail: ++ kfree(handles); ++ kfree(offsets); ++ return -1; ++} ++ ++ ++/* This is DRM_IOCTL_GLAMO_CMDBUF */ ++int glamo_ioctl_cmdbuf(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ int ret = 0; ++ struct glamodrm_handle *gdrm; ++ unsigned int count; ++ drm_glamo_cmd_buffer_t *cbuf = data; ++ u16 *cmds; ++ ++ gdrm = dev->dev_private; ++ ++ count = cbuf->bufsz; ++ ++ if ( count > PAGE_SIZE ) return -EINVAL; ++ ++ cmds = kmalloc(count, GFP_KERNEL); ++ if ( cmds == NULL ) return -ENOMEM; ++ if ( copy_from_user(cmds, cbuf->buf, count) ) { ++ printk(KERN_WARNING "[glamo-drm] copy from user failed\n"); ++ ret = -EINVAL; ++ goto cleanup; ++ } ++ ++ /* Check the buffer isn't going to tell Glamo to enact naughtiness */ ++ if ( !glamo_sanitize_buffer(cmds, count) ) { ++ printk(KERN_WARNING "[glamo-drm] sanitize buffer failed\n"); ++ ret = -EINVAL; ++ goto cleanup; ++ } ++ ++ /* Perform relocation, if necessary */ ++ if ( cbuf->nobjs ) { ++ if ( glamo_do_relocation(gdrm, cbuf, cmds, dev, file_priv) ) ++ { ++ printk(KERN_WARNING "[glamo-drm] Relocation failed\n"); ++ ret = -EINVAL; ++ goto cleanup; ++ } ++ } ++ ++ glamo_add_to_ring(gdrm, cmds, count); ++ ++cleanup: ++ kfree(cmds); ++ ++ return ret; ++} ++ ++ ++/* Return true for a legal sequence of commands, otherwise false */ ++static int glamo_sanitize_burst(u16 base, u16 *cmds, unsigned int count) ++{ ++ /* XXX FIXME TODO: Implementation... */ ++ return 1; ++} ++ ++ ++static int glamo_relocate_burst(struct glamodrm_handle *gdrm, ++ drm_glamo_cmd_burst_t *cbuf, u16 *data, ++ struct drm_device *dev, ++ struct drm_file *file_priv) ++{ ++ u32 *handles; ++ int *offsets; ++ int nobjs = cbuf->nobjs; ++ int i; ++ ++ if ( nobjs > 32 ) return -EINVAL; /* Get real... */ ++ ++ handles = kmalloc(nobjs*sizeof(u32), GFP_KERNEL); ++ if ( handles == NULL ) return -1; ++ if ( copy_from_user(handles, cbuf->objs, nobjs*sizeof(u32)) ) ++ return -1; ++ ++ offsets = kmalloc(nobjs*sizeof(int), GFP_KERNEL); ++ if ( offsets == NULL ) return -1; ++ if ( copy_from_user(offsets, cbuf->obj_pos, nobjs*sizeof(int)) ) ++ return -1; ++ ++ for ( i=0; i<nobjs; i++ ) { ++ ++ u32 handle = handles[i]; ++ int offset = offsets[i]; ++ struct drm_gem_object *obj; ++ struct drm_glamo_gem_object *gobj; ++ u32 addr; ++ u16 addr_low, addr_high; ++ ++ if ( offset > cbuf->bufsz ) { ++ printk(KERN_WARNING "[glamo-drm] Offset out of range" ++ " for this relocation!\n"); ++ goto fail; ++ } ++ ++ obj = drm_gem_object_lookup(dev, file_priv, handle); ++ if ( obj == NULL ) return -1; ++ ++ /* Unref the object now, or it'll never get freed. ++ * FIXME: This should really happen after the GPU has ++ * finished executing these commands. */ ++ drm_gem_object_unreference(obj); ++ ++ gobj = obj->driver_private; ++ if ( gobj == NULL ) { ++ printk(KERN_WARNING "[glamo-drm] This object has no" ++ " private data!\n"); ++ goto fail; ++ } ++ ++ addr = GLAMO_OFFSET_FB + gobj->block->start; ++ addr_low = addr & 0xffff; ++ addr_high = (addr >> 16) & 0x7f; ++ ++ /* FIXME: Should really check that the register is a ++ * valid one for this relocation. */ ++ ++ *(data+(offset/2)+0) = addr_low; ++ *(data+(offset/2)+1) = addr_high; ++ ++ } ++ ++ kfree(handles); ++ kfree(offsets); ++ return 0; ++ ++fail: ++ kfree(handles); ++ kfree(offsets); ++ return -1; ++} ++ ++ ++/* This is DRM_IOCTL_GLAMO_CMDBURST */ ++int glamo_ioctl_cmdburst(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ int ret = 0; ++ struct glamodrm_handle *gdrm; ++ drm_glamo_cmd_burst_t *cbuf = data; ++ u16 *burst; ++ size_t burst_size; ++ size_t data_size; ++ ++ gdrm = dev->dev_private; ++ ++ data_size = cbuf->bufsz; ++ if ( data_size % 4 ) data_size += 2; ++ if ( data_size % 4 ) return -EINVAL; ++ burst_size = data_size + 4; /* Add space for header */ ++ if ( burst_size > PAGE_SIZE ) return -EINVAL; ++ ++ burst = kmalloc(burst_size, GFP_KERNEL); ++ if ( burst == NULL ) return -ENOMEM; ++ ++ /* Get data from userspace */ ++ if ( copy_from_user(burst+2, cbuf->data, cbuf->bufsz) ) { ++ printk(KERN_WARNING "[glamo-drm] copy from user failed\n"); ++ ret = -EINVAL; ++ goto cleanup; ++ } ++ ++ /* Sanitise */ ++ if ( !glamo_sanitize_burst(cbuf->base, burst+2, cbuf->bufsz) ) { ++ printk(KERN_WARNING "[glamo-drm] sanitize buffer failed\n"); ++ ret = -EINVAL; ++ goto cleanup; ++ } ++ ++ /* Relocate */ ++ if ( cbuf->nobjs ) { ++ if ( glamo_relocate_burst(gdrm, cbuf, burst+2, dev, file_priv) ) ++ { ++ printk(KERN_WARNING "[glamo-drm] Relocation failed\n"); ++ ret = -EINVAL; ++ goto cleanup; ++ } ++ } ++ ++ /* Add burst header */ ++ burst[0] = 1<<15 | cbuf->base; ++ burst[1] = data_size / 2; /* -> 2-byte words */ ++ if ( burst[1] & 0x01 ) { ++ printk(KERN_CRIT "Burst not aligned!\n"); ++ goto cleanup; ++ } ++ ++ /* Zero-pad if necessary */ ++ if ( data_size % 4 ) { ++ burst[burst_size-1] = 0x0000; ++ } ++ ++ /* Add to command queue */ ++ glamo_add_to_ring(gdrm, burst, burst_size); ++ ++cleanup: ++ kfree(burst); ++ ++ return ret; ++} ++ ++ ++int glamo_cmdq_init(struct glamodrm_handle *gdrm) ++{ ++ unsigned int i; ++ ++ init_MUTEX(&gdrm->add_to_ring); ++ ++ /* Enable 2D and 3D */ ++ glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_2D); ++ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_2D); ++ ++ /* Start by zeroing the command queue memory */ ++ for ( i=0; i<GLAMO_CMDQ_SIZE; i+=2 ) { ++ iowrite16(0x0000, gdrm->cmdq_base+i); ++ } ++ ++ glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_CMDQ); ++ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_CMDQ); ++ ++ /* Set up command queue location */ ++ reg_write(gdrm, GLAMO_REG_CMDQ_BASE_ADDRL, ++ GLAMO_OFFSET_CMDQ & 0xffff); ++ reg_write(gdrm, GLAMO_REG_CMDQ_BASE_ADDRH, ++ (GLAMO_OFFSET_CMDQ >> 16) & 0x7f); ++ ++ /* Length of command queue in 1k blocks, minus one */ ++ reg_write(gdrm, GLAMO_REG_CMDQ_LEN, (GLAMO_CMDQ_SIZE >> 10)-1); ++ reg_write(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRH, 0); ++ reg_write(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRL, 0); ++ reg_write(gdrm, GLAMO_REG_CMDQ_CONTROL, ++ 1 << 12 | /* Turbo flip (?) */ ++ 5 << 8 | /* no interrupt */ ++ 8 << 4); /* HQ threshold */ ++ ++ return 0; ++} ++ ++ ++int glamo_cmdq_shutdown(struct glamodrm_handle *gdrm) ++{ ++ return 0; ++} ++ ++ ++void glamo_cmdq_suspend(struct glamodrm_handle *gdrm) ++{ ++ /* Placeholder... */ ++} ++ ++ ++void glamo_cmdq_resume(struct glamodrm_handle *gdrm) ++{ ++ glamo_cmdq_init(gdrm); ++} ++ ++ ++/* Initialise an object's contents to zero. ++ * This is in glamo-cmdq.c in the hope that we can accelerate it later. */ ++void glamo_cmdq_blank(struct glamodrm_handle *gdrm, struct drm_gem_object *obj) ++{ ++ char __iomem *cookie; ++ struct drm_glamo_gem_object *gobj; ++ int i; ++ ++ gobj = obj->driver_private; ++ ++ cookie = ioremap(gdrm->vram->start + gobj->block->start, obj->size); ++ for ( i=0; i<obj->size; i+=2 ) { ++ iowrite16(0, cookie+i); ++ } ++ iounmap(cookie); ++} +diff --git a/drivers/mfd/glamo/glamo-cmdq.h b/drivers/mfd/glamo/glamo-cmdq.h +new file mode 100644 +index 0000000..510d195 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-cmdq.h +@@ -0,0 +1,49 @@ ++/* Smedia Glamo 336x/337x command queue handling ++ * ++ * Copyright (c) 2008-2009 Thomas White <taw@bitwiz.org.uk> ++ * Copyright (c) 2009 Andreas Pokorny <andreas.pokorny@gmail.com> ++ * Based on xf86-video-glamo ++ * Copyright 2007 OpenMoko, Inc. ++ * Copyright © 2009 Lars-Peter Clausen <lars@metafoo.de> ++ * ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __GLAMO_CMDQ_H ++#define __GLAMO_CMDQ_H ++ ++#include <drm/drmP.h> ++ ++#include "glamo-drm-private.h" ++ ++extern int glamo_ioctl_cmdbuf(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++extern int glamo_ioctl_cmdburst(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++extern void glamo_cmdq_blank(struct glamodrm_handle *gdrm, ++ struct drm_gem_object *obj); ++ ++extern int glamo_cmdq_init(struct glamodrm_handle *gdrm); ++extern int glamo_cmdq_shutdown(struct glamodrm_handle *gdrm); ++extern void glamo_cmdq_suspend(struct glamodrm_handle *gdrm); ++extern void glamo_cmdq_resume(struct glamodrm_handle *gdrm); ++ ++extern int glamo_add_to_ring(struct glamodrm_handle *gdrm, u16 *addr, ++ unsigned int count); ++ ++#endif /* __GLAMO_CMDQ_H */ +diff --git a/drivers/mfd/glamo/glamo-display.c b/drivers/mfd/glamo/glamo-display.c +new file mode 100644 +index 0000000..93aa917 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-display.c +@@ -0,0 +1,875 @@ ++/* ++ * SMedia Glamo 336x/337x display ++ * ++ * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk> ++ * ++ * Based on glamo-fb.c (C) 2007-2008 by Openmoko, Inc. ++ * Author: Harald Welte <laforge@openmoko.org> ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * ++ * Based on intel_display.c and intel_crt.c from drivers/gpu/drm/i915 ++ * to which the following licence applies: ++ * ++ * Copyright © 2006-2007 Intel Corporation ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Eric Anholt <eric@anholt.net> ++ * ++ */ ++ ++#define DEBUG 1 ++ ++#include <drm/drmP.h> ++#include <drm/glamo_drm.h> ++#include <drm/drm_crtc_helper.h> ++#include <drm/drm_crtc.h> ++ ++#include "glamo-core.h" ++#include "glamo-drm-private.h" ++#include "glamo-regs.h" ++#include "glamo-kms-fb.h" ++#include "glamo-display.h" ++#include <linux/glamofb.h> ++ ++ ++#define GLAMO_LCD_WIDTH_MASK 0x03FF ++#define GLAMO_LCD_HEIGHT_MASK 0x03FF ++#define GLAMO_LCD_PITCH_MASK 0x07FE ++#define GLAMO_LCD_HV_TOTAL_MASK 0x03FF ++#define GLAMO_LCD_HV_RETR_START_MASK 0x03FF ++#define GLAMO_LCD_HV_RETR_END_MASK 0x03FF ++#define GLAMO_LCD_HV_RETR_DISP_START_MASK 0x03FF ++#define GLAMO_LCD_HV_RETR_DISP_END_MASK 0x03FF ++ ++ ++struct glamofb_par { ++ struct drm_device *dev; ++ struct drm_display_mode *our_mode; ++ struct glamo_framebuffer *glamo_fb; ++ int crtc_count; ++ /* crtc currently bound to this */ ++ uint32_t crtc_ids[2]; ++}; ++ ++ ++static int reg_read_lcd(struct glamodrm_handle *gdrm, u_int16_t reg) ++{ ++ int i = 0; ++ ++ for (i = 0; i != 2; i++) ++ nop(); ++ ++ return ioread16(gdrm->lcd_base + reg); ++} ++ ++ ++static void reg_write_lcd(struct glamodrm_handle *gdrm, ++ u_int16_t reg, u_int16_t val) ++{ ++ int i = 0; ++ ++ for (i = 0; i != 2; i++) ++ nop(); ++ ++ iowrite16(val, gdrm->lcd_base + reg); ++} ++ ++ ++static void reg_set_bit_mask_lcd(struct glamodrm_handle *gdrm, ++ u_int16_t reg, u_int16_t mask, ++ u_int16_t val) ++{ ++ u_int16_t tmp; ++ ++ val &= mask; ++ ++ tmp = reg_read_lcd(gdrm, reg); ++ tmp &= ~mask; ++ tmp |= val; ++ reg_write_lcd(gdrm, reg, tmp); ++} ++ ++ ++/* Note that this has nothing at all to do with the engine command queue ++ * in glamo-cmdq.c */ ++static inline int glamo_lcd_cmdq_empty(struct glamodrm_handle *gdrm) ++{ ++ /* DGCMdQempty -- 1 == command queue is empty */ ++ return reg_read_lcd(gdrm, GLAMO_REG_LCD_STATUS1) & (1 << 15); ++} ++ ++ ++/* call holding gfb->lock_cmd when locking, until you unlock */ ++int glamo_lcd_cmd_mode(struct glamodrm_handle *gdrm, int on) ++{ ++ int timeout = 2000000; ++ ++ dev_dbg(gdrm->dev, "glamofb_cmd_mode(on=%d)\n", on); ++ if (on) { ++ ++ while ((!glamo_lcd_cmdq_empty(gdrm)) && (timeout--)) ++ /* yield() */; ++ if (timeout < 0) { ++ printk(KERN_ERR "*************" ++ " LCD command queue never got empty " ++ "*************\n"); ++ return -EIO; ++ } ++ ++ /* display the entire frame then switch to command */ ++ reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1, ++ GLAMO_LCD_CMD_TYPE_DISP | ++ GLAMO_LCD_CMD_DATA_FIRE_VSYNC); ++ ++ /* wait until lcd idle */ ++ timeout = 2000000; ++ while ((!reg_read_lcd(gdrm, GLAMO_REG_LCD_STATUS2) & (1 << 12)) ++ && (timeout--)) ++ /* yield() */; ++ if (timeout < 0) { ++ printk(KERN_ERR"*************" ++ " LCD never idle " ++ "*************\n"); ++ return -EIO; ++ } ++ ++ mdelay(100); ++ ++ } else { ++ /* RGB interface needs vsync/hsync */ ++ int mode; ++ mode = reg_read_lcd(gdrm, GLAMO_REG_LCD_MODE3); ++ if ( mode & GLAMO_LCD_MODE3_RGB) ++ reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1, ++ GLAMO_LCD_CMD_TYPE_DISP | ++ GLAMO_LCD_CMD_DATA_DISP_SYNC); ++ ++ reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1, ++ GLAMO_LCD_CMD_TYPE_DISP | ++ GLAMO_LCD_CMD_DATA_DISP_FIRE); ++ } ++ ++ return 0; ++} ++ ++ ++static struct glamo_script lcd_init_script[] = { ++ { GLAMO_REG_LCD_MODE1, 0x0020 }, ++ /* no display rotation, no hardware cursor, no dither, no gamma, ++ * no retrace flip, vsync low-active, hsync low active, ++ * no TVCLK, no partial display, hw dest color from fb, ++ * no partial display mode, LCD1, software flip, */ ++ { GLAMO_REG_LCD_MODE2, 0x9020 }, ++ /* video flip, no ptr, no ptr, dhclk off, ++ * normal mode, no cpuif, ++ * res, serial msb first, single fb, no fr ctrl, ++ * cpu if bits all zero, no crc ++ * 0000 0000 0010 0000 */ ++ { GLAMO_REG_LCD_MODE3, 0x0b40 }, ++ /* src data rgb565, res, 18bit rgb666 ++ * 000 01 011 0100 0000 */ ++ { GLAMO_REG_LCD_POLARITY, 0x440c }, ++ /* DE high active, no cpu/lcd if, cs0 force low, a0 low active, ++ * np cpu if, 9bit serial data, sclk rising edge latch data ++ * 01 00 0 100 0 000 01 0 0 */ ++ /* The following values assume 640*480@16bpp */ ++ /* FIXME: fb0 has not yet been allocated! */ ++ { GLAMO_REG_LCD_A_BASE1, PAGE_SIZE }, /* display A base address 15:0 */ ++ { GLAMO_REG_LCD_A_BASE2, 0x0000 }, /* display A base address 22:16 */ ++ { GLAMO_REG_LCD_B_BASE1, 0x6000 }, /* display B base address 15:0 */ ++ { GLAMO_REG_LCD_B_BASE2, 0x0009 }, /* display B base address 22:16 */ ++ { GLAMO_REG_LCD_CURSOR_BASE1, 0xC000 }, /* cursor base address 15:0 */ ++ { GLAMO_REG_LCD_CURSOR_BASE2, 0x0012 }, /* cursor base address 22:16 */ ++ { GLAMO_REG_LCD_COMMAND2, 0x0000 }, /* display page A */ ++}; ++ ++ ++static int glamo_run_lcd_script(struct glamodrm_handle *gdrm, ++ struct glamo_script *script, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ struct glamo_script *line = &script[i]; ++ ++ if (line->reg == 0xffff) ++ return 0; ++ else if (line->reg == 0xfffe) ++ msleep(line->val); ++ else ++ reg_write_lcd(gdrm, script[i].reg, script[i].val); ++ } ++ ++ return 0; ++} ++ ++ ++extern void jbt6k74_action(int val); ++ ++/* Power on/off */ ++static void glamo_crtc_dpms(struct drm_crtc *crtc, int mode) ++{ ++} ++ ++ ++static bool glamo_crtc_mode_fixup(struct drm_crtc *crtc, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ return true; ++} ++ ++ ++static int glamo_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, ++ struct drm_framebuffer *old_fb) ++{ ++ struct glamodrm_handle *gdrm; ++ struct glamo_crtc *gcrtc; ++ struct glamo_framebuffer *gfb; ++ struct drm_gem_object *obj; ++ struct drm_glamo_gem_object *gobj; ++ u32 addr; ++ u16 addr_low, addr_high; ++ ++ if (!crtc->fb) { ++ DRM_DEBUG("No FB bound\n"); ++ return -EINVAL; ++ } ++ ++ /* Dig out our handle */ ++ gcrtc = to_glamo_crtc(crtc); ++ gdrm = gcrtc->gdrm; /* Here it is! */ ++ ++ gfb = to_glamo_framebuffer(crtc->fb); ++ obj = gfb->obj; ++ gobj = obj->driver_private; ++ ++ addr = GLAMO_OFFSET_FB + gobj->block->start; ++ addr_low = addr & 0xffff; ++ addr_high = ((addr >> 16) & 0x7f) | 0x4000; ++ ++ glamo_lcd_cmd_mode(gdrm, 1); ++ reg_write_lcd(gdrm, GLAMO_REG_LCD_A_BASE1, addr_low); ++ reg_write_lcd(gdrm, GLAMO_REG_LCD_A_BASE2, addr_high); ++ glamo_lcd_cmd_mode(gdrm, 0); ++ ++ return 0; ++} ++ ++ ++static int glamo_crtc_mode_set(struct drm_crtc *crtc, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode, ++ int x, int y, ++ struct drm_framebuffer *old_fb) ++{ ++ struct glamodrm_handle *gdrm; ++ struct glamo_crtc *gcrtc; ++ int retr_start, retr_end, disp_start, disp_end; ++ ++ /* Dig out our handle */ ++ gcrtc = to_glamo_crtc(crtc); ++ gdrm = gcrtc->gdrm; /* Here it is! */ ++ ++ glamo_lcd_cmd_mode(gdrm, 1); ++ ++ glamo_engine_reclock(gdrm->glamo_core, GLAMO_ENGINE_LCD, mode->clock); ++ gdrm->saved_clock = mode->clock; ++ ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_WIDTH, ++ GLAMO_LCD_WIDTH_MASK, mode->hdisplay); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HEIGHT, ++ GLAMO_LCD_HEIGHT_MASK, mode->vdisplay); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_PITCH, ++ GLAMO_LCD_PITCH_MASK, mode->hdisplay*2); ++ ++ /* Convert "X modeline timings" into "Glamo timings" */ ++ retr_start = 0; ++ retr_end = retr_start + mode->hsync_end - mode->hsync_start; ++ disp_start = mode->htotal - mode->hsync_start; ++ disp_end = disp_start + mode->hdisplay; ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL, ++ GLAMO_LCD_HV_TOTAL_MASK, mode->htotal); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START, ++ GLAMO_LCD_HV_RETR_START_MASK, retr_start); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END, ++ GLAMO_LCD_HV_RETR_END_MASK, retr_end); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START, ++ GLAMO_LCD_HV_RETR_DISP_START_MASK, disp_start); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END, ++ GLAMO_LCD_HV_RETR_DISP_END_MASK, disp_end); ++ ++ /* The same in the vertical direction */ ++ retr_start = 0; ++ retr_end = retr_start + mode->vsync_end - mode->vsync_start; ++ disp_start = mode->vtotal - mode->vsync_start; ++ disp_end = disp_start + mode->vdisplay; ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL, ++ GLAMO_LCD_HV_TOTAL_MASK, mode->vtotal); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START, ++ GLAMO_LCD_HV_RETR_START_MASK, retr_start); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END, ++ GLAMO_LCD_HV_RETR_END_MASK, retr_end); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START, ++ GLAMO_LCD_HV_RETR_DISP_START_MASK, disp_start); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END, ++ GLAMO_LCD_HV_RETR_DISP_END_MASK, disp_end); ++ ++ glamo_lcd_cmd_mode(gdrm, 0); ++ ++ glamo_crtc_mode_set_base(crtc, 0, 0, old_fb); ++ ++ return 0; ++} ++ ++ ++static void glamo_crtc_prepare(struct drm_crtc *crtc) ++{ ++} ++ ++ ++static void glamo_crtc_commit(struct drm_crtc *crtc) ++{ ++} ++ ++ ++static int glamo_crtc_cursor_set(struct drm_crtc *crtc, ++ struct drm_file *file_priv, ++ uint32_t handle, ++ uint32_t width, uint32_t height) ++{ ++ return 0; ++} ++ ++ ++static int glamo_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) ++{ ++ return 0; ++} ++ ++ ++static void glamo_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, ++ u16 *blue, uint32_t size) ++{ ++} ++ ++ ++static void glamo_crtc_destroy(struct drm_crtc *crtc) ++{ ++ struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc); ++ drm_crtc_cleanup(crtc); ++ kfree(glamo_crtc); ++} ++ ++ ++static enum drm_connector_status ++glamo_connector_detect(struct drm_connector *connector) ++{ ++ /* One hopes it hasn't been de-soldered... */ ++ return connector_status_connected; ++} ++ ++ ++static void glamo_connector_destroy(struct drm_connector *connector) ++{ ++ drm_sysfs_connector_remove(connector); ++ drm_connector_cleanup(connector); ++ kfree(connector); ++} ++ ++ ++static int glamo_connector_get_modes(struct drm_connector *connector) ++{ ++ struct drm_display_mode *mode; ++ struct glamo_fb_platform_data *fb_info; ++ struct glamo_output *goutput = to_glamo_output(connector); ++ struct glamodrm_handle *gdrm = goutput->gdrm; ++ ++ /* Dig out the record which will tell us about the hardware */ ++ fb_info = gdrm->glamo_core->pdata->fb_data; ++ ++ mode = drm_mode_create(connector->dev); ++ if (!mode) ++ return 0; ++ /* Fill in 'mode' here */ ++ mode->type = DRM_MODE_TYPE_DEFAULT | DRM_MODE_TYPE_PREFERRED; ++ ++ /* Convert framebuffer timings into KMS timings */ ++ mode->clock = 1000000000UL / fb_info->modes[0].pixclock; /* ps -> kHz */ ++ mode->clock *= 1000; /* kHz -> Hz */ ++ mode->hdisplay = fb_info->modes[0].xres; ++ mode->hsync_start = fb_info->modes[0].right_margin + mode->hdisplay; ++ mode->hsync_end = mode->hsync_start + fb_info->modes[0].hsync_len; ++ mode->htotal = mode->hsync_end + fb_info->modes[0].left_margin; ++ mode->hskew = 0; ++ ++ mode->vdisplay = fb_info->modes[0].yres; ++ mode->vsync_start = fb_info->modes[0].lower_margin + mode->vdisplay; ++ mode->vsync_end = mode->vsync_start + fb_info->modes[0].vsync_len; ++ mode->vtotal = mode->vsync_end + fb_info->modes[0].upper_margin; ++ mode->vscan = 0; ++ ++ /* Physical size */ ++ mode->width_mm = fb_info->width; ++ mode->height_mm = fb_info->height; ++ ++ drm_mode_set_name(mode); ++ drm_mode_probed_add(connector, mode); ++ ++ return 1; /* one mode, for now */ ++} ++ ++ ++static int glamo_connector_set_property(struct drm_connector *connector, ++ struct drm_property *property, ++ uint64_t value) ++{ ++ return 0; ++} ++ ++ ++static int glamo_connector_mode_valid(struct drm_connector *connector, ++ struct drm_display_mode *mode) ++{ ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ ++ return MODE_OK; ++} ++ ++ ++struct drm_encoder * ++glamo_connector_best_encoder(struct drm_connector *connector) ++{ ++ struct glamo_output *glamo_output = to_glamo_output(connector); ++ return &glamo_output->enc; ++} ++ ++ ++static void glamo_encoder_dpms(struct drm_encoder *encoder, int mode) ++{ ++} ++ ++ ++static bool glamo_encoder_mode_fixup(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ return true; ++} ++ ++ ++void glamo_encoder_prepare(struct drm_encoder *encoder) ++{ ++} ++ ++ ++void glamo_encoder_commit(struct drm_encoder *encoder) ++{ ++} ++ ++ ++static void glamo_encoder_mode_set(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++} ++ ++ ++static void glamo_encoder_destroy(struct drm_encoder *encoder) ++{ ++ drm_encoder_cleanup(encoder); ++} ++ ++ ++static void glamo_framebuffer_destroy(struct drm_framebuffer *fb) ++{ ++ struct glamo_framebuffer *glamo_fb = to_glamo_framebuffer(fb); ++ struct drm_device *dev = fb->dev; ++ ++ drm_framebuffer_cleanup(fb); ++ mutex_lock(&dev->struct_mutex); ++ drm_gem_object_unreference(glamo_fb->obj); ++ mutex_unlock(&dev->struct_mutex); ++ ++ kfree(glamo_fb); ++} ++ ++static int glamo_framebuffer_create_handle(struct drm_framebuffer *fb, ++ struct drm_file *file_priv, ++ unsigned int *handle) ++{ ++ struct glamo_framebuffer *glamo_fb = to_glamo_framebuffer(fb); ++ struct drm_gem_object *object = glamo_fb->obj; ++ ++ return drm_gem_handle_create(file_priv, object, handle); ++} ++ ++ ++static const struct drm_framebuffer_funcs glamo_fb_funcs = { ++ .destroy = glamo_framebuffer_destroy, ++ .create_handle = glamo_framebuffer_create_handle, ++}; ++ ++ ++int glamo_framebuffer_create(struct drm_device *dev, ++ struct drm_mode_fb_cmd *mode_cmd, ++ struct drm_framebuffer **fb, ++ struct drm_gem_object *obj) ++{ ++ struct glamo_framebuffer *glamo_fb; ++ int ret; ++ ++ glamo_fb = kzalloc(sizeof(*glamo_fb), GFP_KERNEL); ++ if (!glamo_fb) ++ return -ENOMEM; ++ ++ ret = drm_framebuffer_init(dev, &glamo_fb->base, &glamo_fb_funcs); ++ if (ret) { ++ DRM_ERROR("framebuffer init failed %d\n", ret); ++ return ret; ++ } ++ ++ drm_helper_mode_fill_fb_struct(&glamo_fb->base, mode_cmd); ++ ++ glamo_fb->obj = obj; ++ ++ *fb = &glamo_fb->base; ++ ++ return 0; ++} ++ ++ ++static struct drm_framebuffer * ++glamo_user_framebuffer_create(struct drm_device *dev, ++ struct drm_file *filp, ++ struct drm_mode_fb_cmd *mode_cmd) ++{ ++ struct drm_gem_object *obj; ++ struct drm_framebuffer *fb; ++ int ret; ++ ++ obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); ++ if (!obj) ++ return NULL; ++ ++ ret = glamo_framebuffer_create(dev, mode_cmd, &fb, obj); ++ if (ret) { ++ drm_gem_object_unreference(obj); ++ return NULL; ++ } ++ ++ return fb; ++} ++ ++ ++int glamo_fbchanged(struct drm_device *dev) ++{ ++ return 0; ++} ++ ++ ++/* CRTC functions */ ++static const struct drm_crtc_funcs glamo_crtc_funcs = { ++ .cursor_set = glamo_crtc_cursor_set, ++ .cursor_move = glamo_crtc_cursor_move, ++ .gamma_set = glamo_crtc_gamma_set, ++ .set_config = drm_crtc_helper_set_config, ++ .destroy = glamo_crtc_destroy, ++}; ++ ++ ++/* CRTC helper functions */ ++static const struct drm_crtc_helper_funcs glamo_crtc_helper_funcs = { ++ .dpms = glamo_crtc_dpms, ++ .mode_fixup = glamo_crtc_mode_fixup, ++ .mode_set = glamo_crtc_mode_set, ++ .mode_set_base = glamo_crtc_mode_set_base, ++ .prepare = glamo_crtc_prepare, ++ .commit = glamo_crtc_commit, ++}; ++ ++ ++/* Connector functions */ ++static const struct drm_connector_funcs glamo_connector_funcs = { ++ .detect = glamo_connector_detect, ++ .fill_modes = drm_helper_probe_single_connector_modes, ++ .destroy = glamo_connector_destroy, ++ .set_property = glamo_connector_set_property, ++}; ++ ++ ++/* Connector helper functions */ ++static const struct drm_connector_helper_funcs glamo_connector_helper_funcs = { ++ .mode_valid = glamo_connector_mode_valid, ++ .get_modes = glamo_connector_get_modes, ++ .best_encoder = glamo_connector_best_encoder, ++}; ++ ++ ++/* Encoder functions */ ++static const struct drm_encoder_funcs glamo_encoder_funcs = { ++ .destroy = glamo_encoder_destroy, ++}; ++ ++ ++/* Encoder helper functions */ ++static const struct drm_encoder_helper_funcs glamo_encoder_helper_funcs = { ++ .dpms = glamo_encoder_dpms, ++ .mode_fixup = glamo_encoder_mode_fixup, ++ .prepare = glamo_encoder_prepare, ++ .commit = glamo_encoder_commit, ++ .mode_set = glamo_encoder_mode_set, ++}; ++ ++ ++/* Mode functions */ ++static const struct drm_mode_config_funcs glamo_mode_funcs = { ++ .fb_create = glamo_user_framebuffer_create, ++ .fb_changed = glamo_fbchanged ++}; ++ ++ ++static struct drm_mode_set kernelfb_mode; ++ ++ ++/* Restore's the kernel's fbcon mode, used for panic path */ ++void glamo_display_restore(void) ++{ ++ drm_crtc_helper_set_config(&kernelfb_mode); ++} ++ ++ ++static int glamo_display_panic(struct notifier_block *n, unsigned long ununsed, ++ void *panic_str) ++{ ++ DRM_ERROR("panic occurred, switching back to text console\n"); ++ ++ glamo_display_restore(); ++ return 0; ++} ++ ++ ++static struct notifier_block paniced = { ++ .notifier_call = glamo_display_panic, ++}; ++ ++ ++int glamo_display_init(struct drm_device *dev) ++{ ++ struct glamodrm_handle *gdrm; ++ struct glamo_crtc *glamo_crtc; ++ struct glamo_output *glamo_output; ++ struct drm_connector *connector; ++ struct glamo_framebuffer *glamo_fb; ++ struct fb_info *info; ++ struct glamofb_par *par; ++ struct drm_mode_set *modeset; ++ ++ gdrm = dev->dev_private; ++ ++ /* Initial setup of the LCD controller */ ++ glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_LCD); ++ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_LCD); ++ ++ glamo_run_lcd_script(gdrm, lcd_init_script, ++ ARRAY_SIZE(lcd_init_script)); ++ ++ drm_mode_config_init(dev); ++ ++ dev->mode_config.min_width = 240; ++ dev->mode_config.min_height = 320; ++ dev->mode_config.max_width = 480; ++ dev->mode_config.max_height = 640; ++ ++ dev->mode_config.funcs = (void *)&glamo_mode_funcs; ++ ++ /* Initialise our CRTC object. ++ * Only one connector per CRTC. We know this: it's kind of soldered. */ ++ glamo_crtc = kzalloc(sizeof(struct glamo_crtc) ++ + sizeof(struct drm_connector *), GFP_KERNEL); ++ if (glamo_crtc == NULL) return 1; ++ glamo_crtc->gdrm = gdrm; ++ glamo_crtc->blank_mode = DRM_MODE_DPMS_OFF; ++ drm_crtc_init(dev, &glamo_crtc->base, &glamo_crtc_funcs); ++ drm_crtc_helper_add(&glamo_crtc->base, &glamo_crtc_helper_funcs); ++ ++ glamo_crtc->mode_set.crtc = &glamo_crtc->base; ++ glamo_crtc->mode_set.connectors = ++ (struct drm_connector **)(glamo_crtc + 1); ++ glamo_crtc->mode_set.num_connectors = 0; ++ ++ /* Create our "output" object: consists of an output and an encoder */ ++ glamo_output = kzalloc(sizeof(struct glamo_output), GFP_KERNEL); ++ if (glamo_output == NULL) return 1; ++ connector = &glamo_output->base; ++ glamo_output->gdrm = gdrm; ++ ++ /* Initialise the connector */ ++ drm_connector_init(dev, connector, &glamo_connector_funcs, ++ DRM_MODE_CONNECTOR_Unknown); ++ drm_sysfs_connector_add(connector); ++ connector->interlace_allowed = 0; ++ connector->doublescan_allowed = 0; ++ ++ /* Initialise the encoder */ ++ drm_encoder_init(dev, &glamo_output->enc, &glamo_encoder_funcs, ++ DRM_MODE_ENCODER_DAC); ++ glamo_output->enc.possible_crtcs = 1 << 0; ++ drm_mode_connector_attach_encoder(&glamo_output->base, ++ &glamo_output->enc); ++ ++ drm_encoder_helper_add(&glamo_output->enc, &glamo_encoder_helper_funcs); ++ drm_connector_helper_add(connector, &glamo_connector_helper_funcs); ++ ++ drm_helper_initial_config(dev); ++ ++ if (list_empty(&dev->mode_config.fb_kernel_list)) { ++ int ret, cols, cols_g; ++ cols_g = reg_read_lcd(gdrm, GLAMO_REG_LCD_MODE3) & 0xc000; ++ switch ( cols_g ) { ++ case GLAMO_LCD_SRC_RGB565 : ++ cols = GLAMO_FB_RGB565; break; ++ case GLAMO_LCD_SRC_ARGB1555 : ++ cols = GLAMO_FB_ARGB1555; break; ++ case GLAMO_LCD_SRC_ARGB4444 : ++ cols = GLAMO_FB_ARGB4444; break; ++ default : ++ printk(KERN_WARNING "Unrecognised LCD colour mode\n"); ++ cols = GLAMO_FB_RGB565; break; /* Take a guess */ ++ } ++ ret = glamofb_create(dev, 480, 640, 480, 640, cols, &glamo_fb); ++ if (ret) return -EINVAL; ++ } ++ ++ info = glamo_fb->base.fbdev; ++ par = info->par; ++ ++ modeset = &glamo_crtc->mode_set; ++ modeset->fb = &glamo_fb->base; ++ modeset->connectors[0] = connector; ++ ++ par->crtc_ids[0] = glamo_crtc->base.base.id; ++ ++ modeset->num_connectors = 1; ++ modeset->mode = modeset->crtc->desired_mode; ++ ++ par->crtc_count = 1; ++ ++ if (register_framebuffer(info) < 0) ++ return -EINVAL; ++ ++ printk(KERN_INFO "[glamo-drm] fb%d: %s frame buffer device\n", ++ info->node, info->fix.id); ++ ++ /* Switch back to kernel console on panic */ ++ kernelfb_mode = *modeset; ++ atomic_notifier_chain_register(&panic_notifier_list, &paniced); ++ printk(KERN_INFO "[glamo-drm] Registered panic notifier\n"); ++ ++ return 0; ++} ++ ++ ++void glamo_display_suspend(struct glamodrm_handle *gdrm) ++{ ++ gdrm->saved_width = reg_read_lcd(gdrm, GLAMO_REG_LCD_WIDTH); ++ gdrm->saved_height = reg_read_lcd(gdrm, GLAMO_REG_LCD_HEIGHT); ++ gdrm->saved_pitch = reg_read_lcd(gdrm, GLAMO_REG_LCD_PITCH); ++ gdrm->saved_htotal = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL); ++ gdrm->saved_hrtrst = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START); ++ gdrm->saved_hrtren = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END); ++ gdrm->saved_hdspst = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START); ++ gdrm->saved_hdspen = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END); ++ gdrm->saved_vtotal = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL); ++ gdrm->saved_vrtrst = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START); ++ gdrm->saved_vrtren = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END); ++ gdrm->saved_vdspst = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START); ++ gdrm->saved_vdspen = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END); ++} ++ ++ ++void glamo_display_resume(struct glamodrm_handle *gdrm) ++{ ++ glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_LCD); ++ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_LCD); ++ glamo_run_lcd_script(gdrm, lcd_init_script, ++ ARRAY_SIZE(lcd_init_script)); ++ ++ /* Enable pixel clock */ ++ glamo_engine_clkreg_set(gdrm->glamo_core, ++ GLAMO_ENGINE_LCD, ++ GLAMO_CLOCK_LCD_EN_DCLK, ++ GLAMO_CLOCK_LCD_EN_DCLK); ++ ++ /* Restore timings */ ++ glamo_lcd_cmd_mode(gdrm, 1); ++ glamo_engine_reclock(gdrm->glamo_core, GLAMO_ENGINE_LCD, ++ gdrm->saved_clock); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_WIDTH, GLAMO_LCD_WIDTH_MASK, ++ gdrm->saved_width); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HEIGHT, GLAMO_LCD_HEIGHT_MASK, ++ gdrm->saved_height); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_PITCH, GLAMO_LCD_PITCH_MASK, ++ gdrm->saved_pitch); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL, ++ GLAMO_LCD_HV_TOTAL_MASK, gdrm->saved_htotal); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START, ++ GLAMO_LCD_HV_RETR_START_MASK, gdrm->saved_hrtrst); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END, ++ GLAMO_LCD_HV_RETR_END_MASK, gdrm->saved_hrtren); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START, ++ GLAMO_LCD_HV_RETR_DISP_START_MASK, ++ gdrm->saved_hdspst); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END, ++ GLAMO_LCD_HV_RETR_DISP_END_MASK, ++ gdrm->saved_hdspen); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL, ++ GLAMO_LCD_HV_TOTAL_MASK, gdrm->saved_vtotal); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START, ++ GLAMO_LCD_HV_RETR_START_MASK, gdrm->saved_vrtrst); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END, ++ GLAMO_LCD_HV_RETR_END_MASK, gdrm->saved_vrtren); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START, ++ GLAMO_LCD_HV_RETR_DISP_START_MASK, ++ gdrm->saved_vdspst); ++ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END, ++ GLAMO_LCD_HV_RETR_DISP_END_MASK, ++ gdrm->saved_vdspen); ++ glamo_lcd_cmd_mode(gdrm, 0); ++} +diff --git a/drivers/mfd/glamo/glamo-display.h b/drivers/mfd/glamo/glamo-display.h +new file mode 100644 +index 0000000..d6f21bc +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-display.h +@@ -0,0 +1,39 @@ ++/* Smedia Glamo 336x/337x Display ++ * ++ * Copyright (c) 2008-2009 Thomas White <taw@bitwiz.org.uk> ++ * ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __GLAMO_DISPLAY_H ++#define __GLAMO_DISPLAY_H ++ ++#include <drm/drmP.h> ++#include "glamo-drm-private.h" ++ ++extern int glamo_display_init(struct drm_device *dev); ++ ++extern int glamo_framebuffer_create(struct drm_device *dev, ++ struct drm_mode_fb_cmd *mode_cmd, ++ struct drm_framebuffer **fb, ++ struct drm_gem_object *obj); ++ ++extern void glamo_display_suspend(struct glamodrm_handle *gdrm); ++extern void glamo_display_resume(struct glamodrm_handle *gdrm); ++ ++#endif /* __GLAMO_DISPLAY_H */ +diff --git a/drivers/mfd/glamo/glamo-drm-drv.c b/drivers/mfd/glamo/glamo-drm-drv.c +new file mode 100644 +index 0000000..81215f4 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-drm-drv.c +@@ -0,0 +1,453 @@ ++/* Smedia Glamo 336x/337x Graphics Driver ++ * ++ * Copyright (C) 2009 Openmoko, Inc. Jorge Luis Zapata <turran@openmoko.com> ++ * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk> ++ * Copyright (C) 2009 Andreas Pokorny <andreas.pokorny@gmail.com> ++ * ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <drm/drmP.h> ++#include <drm/glamo_drm.h> ++#include <linux/glamofb.h> ++ ++#include "glamo-core.h" ++#include "glamo-cmdq.h" ++#include "glamo-buffer.h" ++#include "glamo-drm-private.h" ++#include "glamo-display.h" ++#include "glamo-kms-fb.h" ++#include "glamo-fence.h" ++ ++#define DRIVER_AUTHOR "Openmoko, Inc." ++#define DRIVER_NAME "glamo-drm" ++#define DRIVER_DESC "SMedia Glamo 3362" ++#define DRIVER_DATE "20090614" ++ ++ ++static int glamo_ioctl_swap(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ printk(KERN_INFO "glamo_ioctl_swap\n"); ++ return 0; ++} ++ ++ ++static int glamo_ioctl_gem_info(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ printk(KERN_INFO "glamo_ioctl_gem_info\n"); ++ return 0; ++} ++ ++ ++struct drm_ioctl_desc glamo_ioctls[] = { ++ DRM_IOCTL_DEF(DRM_GLAMO_CMDBUF, glamo_ioctl_cmdbuf, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_SWAP, glamo_ioctl_swap, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_CMDBURST, glamo_ioctl_cmdburst, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_GEM_INFO, glamo_ioctl_gem_info, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_GEM_CREATE, glamo_ioctl_gem_create, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_GEM_MMAP, glamo_ioctl_gem_mmap, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_GEM_PIN, glamo_ioctl_gem_pin, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_GEM_UNPIN, glamo_ioctl_gem_unpin, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_GEM_PREAD, glamo_ioctl_gem_pread, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_GEM_PWRITE, glamo_ioctl_gem_pwrite, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_GLAMO_GEM_WAIT_RENDERING, ++ glamo_ioctl_wait_rendering, DRM_AUTH), ++}; ++ ++ ++static int glamodrm_firstopen(struct drm_device *dev) ++{ ++ DRM_DEBUG("\n"); ++ return 0; ++} ++ ++ ++static int glamodrm_open(struct drm_device *dev, struct drm_file *fh) ++{ ++ DRM_DEBUG("\n"); ++ return 0; ++} ++ ++ ++static void glamodrm_preclose(struct drm_device *dev, struct drm_file *fh) ++{ ++ DRM_DEBUG("\n"); ++} ++ ++static void glamodrm_postclose(struct drm_device *dev, struct drm_file *fh) ++{ ++ DRM_DEBUG("\n"); ++} ++ ++ ++static void glamodrm_lastclose(struct drm_device *dev) ++{ ++ DRM_DEBUG("\n"); ++} ++ ++ ++static int glamodrm_master_create(struct drm_device *dev, ++ struct drm_master *master) ++{ ++ DRM_DEBUG("\n"); ++ ++ return 0; ++} ++ ++ ++static void glamodrm_master_destroy(struct drm_device *dev, ++ struct drm_master *master) ++{ ++ DRM_DEBUG("\n"); ++} ++ ++ ++static int glamodrm_load(struct drm_device *dev, unsigned long flags) ++{ ++ struct glamodrm_handle *gdrm; ++ gdrm = dev->dev_private; ++ ++ glamo_buffer_init(gdrm); ++ glamo_cmdq_init(gdrm); ++ glamo_fence_init(gdrm); ++ glamo_display_init(dev); ++ ++ return 0; ++} ++ ++ ++static int glamodrm_unload(struct drm_device *dev) ++{ ++ struct glamodrm_handle *gdrm; ++ ++ gdrm = dev->dev_private; ++ ++ glamo_engine_disable(gdrm->glamo_core, GLAMO_ENGINE_2D); ++ glamo_engine_disable(gdrm->glamo_core, GLAMO_ENGINE_3D); ++ glamo_buffer_final(gdrm); ++ glamo_fence_shutdown(gdrm); ++ ++ return 0; ++} ++ ++ ++static struct vm_operations_struct glamodrm_gem_vm_ops = { ++ .fault = glamodrm_gem_fault, ++}; ++ ++static struct drm_driver glamodrm_drm_driver = { ++ .driver_features = DRIVER_IS_PLATFORM | DRIVER_GEM | DRIVER_MODESET, ++ .firstopen = glamodrm_firstopen, ++ .load = glamodrm_load, ++ .unload = glamodrm_unload, ++ .open = glamodrm_open, ++ .preclose = glamodrm_preclose, ++ .postclose = glamodrm_postclose, ++ .lastclose = glamodrm_lastclose, ++ .reclaim_buffers = drm_core_reclaim_buffers, ++ .get_map_ofs = drm_core_get_map_ofs, ++ .get_reg_ofs = drm_core_get_reg_ofs, ++ .master_create = glamodrm_master_create, ++ .master_destroy = glamodrm_master_destroy, ++ .gem_init_object = glamodrm_gem_init_object, ++ .gem_free_object = glamodrm_gem_free_object, ++ .gem_vm_ops = &glamodrm_gem_vm_ops, ++ .ioctls = glamo_ioctls, ++ .fops = { ++ .owner = THIS_MODULE, ++ .open = drm_open, ++ .release = drm_release, ++ .ioctl = drm_ioctl, ++ .mmap = drm_gem_mmap, ++ .poll = drm_poll, ++ .fasync = drm_fasync, ++ }, ++ .major = 0, ++ .minor = 1, ++ .patchlevel = 0, ++ .name = DRIVER_NAME, ++ .desc = DRIVER_DESC, ++ .date = DRIVER_DATE, ++}; ++ ++ ++static int glamodrm_probe(struct platform_device *pdev) ++{ ++ int rc; ++ struct glamodrm_handle *gdrm; ++ struct glamo_core *core = dev_get_drvdata(pdev->dev.parent); ++ ++ printk(KERN_INFO "[glamo-drm] SMedia Glamo Direct Rendering Support\n"); ++ ++ gdrm = kzalloc(sizeof(*gdrm), GFP_KERNEL); ++ if ( !gdrm ) ++ return -ENOMEM; ++ platform_set_drvdata(pdev, gdrm); ++ gdrm->glamo_core = core; ++ gdrm->dev = &pdev->dev; ++ ++ /* Find the command queue registers */ ++ gdrm->reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "glamo-cmdq-regs"); ++ if ( !gdrm->reg ) { ++ dev_err(&pdev->dev, "Unable to find cmdq registers.\n"); ++ rc = -ENOENT; ++ goto out_free; ++ } ++ gdrm->reg = request_mem_region(gdrm->reg->start, ++ resource_size(gdrm->reg), pdev->name); ++ if ( !gdrm->reg ) { ++ dev_err(&pdev->dev, "failed to request MMIO region\n"); ++ rc = -ENOENT; ++ goto out_free; ++ } ++ gdrm->reg_base = ioremap_nocache(gdrm->reg->start, ++ resource_size(gdrm->reg)); ++ if ( !gdrm->reg_base ) { ++ dev_err(&pdev->dev, "failed to ioremap() MMIO registers\n"); ++ rc = -ENOENT; ++ goto out_release_regs; ++ } ++ ++ /* Find the command queue itself */ ++ gdrm->cmdq = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "glamo-command-queue"); ++ if ( !gdrm->cmdq ) { ++ dev_err(&pdev->dev, "Unable to find command queue.\n"); ++ rc = -ENOENT; ++ goto out_unmap_regs; ++ } ++ gdrm->cmdq = request_mem_region(gdrm->cmdq->start, ++ resource_size(gdrm->cmdq), pdev->name); ++ if ( !gdrm->cmdq ) { ++ dev_err(&pdev->dev, "failed to request command queue region\n"); ++ rc = -ENOENT; ++ goto out_unmap_regs; ++ } ++ gdrm->cmdq_base = ioremap_nocache(gdrm->cmdq->start, ++ resource_size(gdrm->cmdq)); ++ if ( !gdrm->cmdq_base ) { ++ dev_err(&pdev->dev, "failed to ioremap() command queue\n"); ++ rc = -ENOENT; ++ goto out_release_cmdq; ++ } ++ ++ /* Find the VRAM */ ++ gdrm->vram = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "glamo-fb-mem"); ++ if ( !gdrm->vram ) { ++ dev_err(&pdev->dev, "Unable to find VRAM.\n"); ++ rc = -ENOENT; ++ goto out_unmap_cmdq; ++ } ++ gdrm->vram = request_mem_region(gdrm->vram->start, ++ resource_size(gdrm->vram), pdev->name); ++ if ( !gdrm->vram ) { ++ dev_err(&pdev->dev, "failed to request VRAM region\n"); ++ rc = -ENOENT; ++ goto out_unmap_cmdq; ++ } ++ ++ /* Find the LCD controller */ ++ gdrm->lcd_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "glamo-fb-regs"); ++ if ( !gdrm->lcd_regs ) { ++ dev_err(&pdev->dev, "Unable to find LCD registers.\n"); ++ rc = -ENOENT; ++ goto out_release_vram; ++ } ++ gdrm->lcd_regs = request_mem_region(gdrm->lcd_regs->start, ++ resource_size(gdrm->lcd_regs), ++ pdev->name); ++ if ( !gdrm->lcd_regs ) { ++ dev_err(&pdev->dev, "failed to request LCD registers\n"); ++ rc = -ENOENT; ++ goto out_release_vram; ++ } ++ gdrm->lcd_base = ioremap_nocache(gdrm->lcd_regs->start, ++ resource_size(gdrm->lcd_regs)); ++ if ( !gdrm->lcd_base ) { ++ dev_err(&pdev->dev, "failed to ioremap() LCD registers\n"); ++ rc = -ENOENT; ++ goto out_release_lcd; ++ } ++ ++ /* Find the 2D engine */ ++ gdrm->twod_regs = platform_get_resource(pdev, IORESOURCE_MEM, 4); ++ if ( !gdrm->twod_regs ) { ++ dev_err(&pdev->dev, "Unable to find 2D registers.\n"); ++ rc = -ENOENT; ++ goto out_unmap_lcd; ++ } ++ gdrm->twod_regs = request_mem_region(gdrm->twod_regs->start, ++ resource_size(gdrm->twod_regs), ++ pdev->name); ++ if ( !gdrm->twod_regs ) { ++ dev_err(&pdev->dev, "failed to request 2D registers\n"); ++ rc = -ENOENT; ++ goto out_unmap_lcd; ++ } ++ gdrm->twod_base = ioremap(gdrm->twod_regs->start, ++ resource_size(gdrm->twod_regs)); ++ if ( !gdrm->twod_base ) { ++ dev_err(&pdev->dev, "failed to ioremap() 2D registers\n"); ++ rc = -ENOENT; ++ goto out_release_2d; ++ } ++ ++ /* Hook up IRQ handle for fence processing */ ++ gdrm->twod_irq = platform_get_irq_byname(pdev, "glamo-2d-irq"); ++ rc = request_irq(gdrm->twod_irq, glamo_fence_irq_handler, ++ IRQF_SHARED, pdev->name, gdrm); ++ if ( rc ) { ++ dev_err(&pdev->dev, "failed to register irq.\n"); ++ goto out_unmap_2d; ++ } ++ ++ gdrm->vram_size = GLAMO_FB_SIZE; ++ printk(KERN_INFO "[glamo-drm] %lli bytes of VRAM\n", ++ (long long int)gdrm->vram_size); ++ ++ /* Initialise DRM */ ++ drm_platform_init(&glamodrm_drm_driver, pdev, (void *)gdrm); ++ ++ return 0; ++ ++out_unmap_2d: ++ iounmap(gdrm->twod_base); ++out_release_2d: ++ release_mem_region(gdrm->twod_regs->start, ++ resource_size(gdrm->twod_regs)); ++out_unmap_lcd: ++ iounmap(gdrm->lcd_base); ++out_release_lcd: ++ release_mem_region(gdrm->lcd_regs->start, ++ resource_size(gdrm->lcd_regs)); ++out_release_vram: ++ release_mem_region(gdrm->vram->start, resource_size(gdrm->vram)); ++out_unmap_cmdq: ++ iounmap(gdrm->cmdq_base); ++out_release_cmdq: ++ release_mem_region(gdrm->cmdq->start, resource_size(gdrm->cmdq)); ++out_unmap_regs: ++ iounmap(gdrm->reg_base); ++out_release_regs: ++ release_mem_region(gdrm->reg->start, resource_size(gdrm->reg)); ++out_free: ++ kfree(gdrm); ++ pdev->dev.driver_data = NULL; ++ return rc; ++} ++ ++ ++static int glamodrm_remove(struct platform_device *pdev) ++{ ++ struct glamodrm_handle *gdrm = platform_get_drvdata(pdev); ++ ++ glamo_buffer_final(gdrm); ++ glamo_cmdq_shutdown(gdrm); ++ ++ drm_exit(&glamodrm_drm_driver); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ /* Release registers */ ++ iounmap(gdrm->reg_base); ++ release_mem_region(gdrm->reg->start, resource_size(gdrm->reg)); ++ ++ /* Release VRAM */ ++ release_mem_region(gdrm->vram->start, resource_size(gdrm->vram)); ++ ++ /* Release command queue */ ++ iounmap(gdrm->cmdq_base); ++ release_mem_region(gdrm->cmdq->start, resource_size(gdrm->cmdq)); ++ ++ /* Release 2D engine */ ++ free_irq(gdrm->twod_irq, gdrm); ++ iounmap(gdrm->twod_base); ++ release_mem_region(gdrm->twod_regs->start, ++ resource_size(gdrm->twod_regs)); ++ ++ kfree(gdrm); ++ ++ return 0; ++} ++ ++ ++static int glamodrm_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct glamodrm_handle *gdrm = platform_get_drvdata(pdev); ++ ++ glamo_kmsfb_suspend(gdrm); ++ glamo_display_suspend(gdrm); ++ glamo_cmdq_suspend(gdrm); ++ ++ /* glamo_core.c will suspend the engines for us */ ++ ++ return 0; ++} ++ ++ ++static int glamodrm_resume(struct platform_device *pdev) ++{ ++ struct glamodrm_handle *gdrm = platform_get_drvdata(pdev); ++ ++ glamo_cmdq_resume(gdrm); ++ glamo_display_resume(gdrm); ++ glamo_kmsfb_resume(gdrm); ++ ++ return 0; ++} ++ ++ ++static struct platform_driver glamodrm_driver = { ++ .probe = glamodrm_probe, ++ .remove = glamodrm_remove, ++ .suspend = glamodrm_suspend, ++ .resume = glamodrm_resume, ++ .driver = { ++ .name = "glamo-fb", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++ ++static int __devinit glamodrm_init(void) ++{ ++ glamodrm_drm_driver.num_ioctls = DRM_ARRAY_SIZE(glamo_ioctls); ++ return platform_driver_register(&glamodrm_driver); ++} ++ ++ ++static void __exit glamodrm_exit(void) ++{ ++ platform_driver_unregister(&glamodrm_driver); ++} ++ ++ ++module_init(glamodrm_init); ++module_exit(glamodrm_exit); ++ ++MODULE_AUTHOR(DRIVER_AUTHOR); ++MODULE_DESCRIPTION(DRIVER_DESC); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mfd/glamo/glamo-drm-private.h b/drivers/mfd/glamo/glamo-drm-private.h +new file mode 100644 +index 0000000..7949a2e +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-drm-private.h +@@ -0,0 +1,156 @@ ++/* Smedia Glamo 336x/337x DRM private bits ++ * ++ * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk> ++ * Copyright (C) 2009 Andreas Pokorny <andreas.pokorny@gmail.com> ++ * Based on xf86-video-glamo ++ * Copyright 2007 OpenMoko, Inc. ++ * Copyright © 2009 Lars-Peter Clausen <lars@metafoo.de> ++ * ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __GLAMO_DRMPRIV_H ++#define __GLAMO_DRMPRIV_H ++ ++ ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <linux/semaphore.h> ++#include <linux/spinlock.h> ++#include <linux/wait.h> ++ ++#include "glamo-core.h" ++ ++ ++/* Memory to allocate for the framebuffer. ++ * The rest is reserved for the DRM memory manager */ ++#define GLAMO_FRAMEBUFFER_ALLOCATION (2*480*640) ++ ++ ++struct glamodrm_handle { ++ ++ /* This device */ ++ struct device *dev; ++ ++ /* The parent device handle */ ++ struct glamo_core *glamo_core; ++ ++ /* Framebuffer handle for the console (i.e. /dev/fb0) */ ++ struct fb_info *fb; ++ ++ /* Command queue registers */ ++ struct resource *reg; ++ char __iomem *reg_base; ++ ++ /* VRAM region */ ++ struct resource *vram; ++ ++ /* Command queue region */ ++ struct resource *cmdq; ++ char __iomem *cmdq_base; ++ ++ /* LCD controller registers */ ++ struct resource *lcd_regs; ++ char __iomem *lcd_base; ++ ++ /* 2D engine registers and IRQ */ ++ struct resource *twod_regs; ++ char __iomem *twod_base; ++ unsigned int twod_irq; ++ ++ ssize_t vram_size; ++ ++ /* Memory management */ ++ struct drm_mm *mmgr; ++ ++ /* semaphore against concurrent ioctl */ ++ struct semaphore add_to_ring; ++ ++ /* Saved state */ ++ u_int16_t saved_clock; ++ u_int16_t saved_width; ++ u_int16_t saved_height; ++ u_int16_t saved_pitch; ++ u_int16_t saved_htotal; ++ u_int16_t saved_hrtrst; ++ u_int16_t saved_hrtren; ++ u_int16_t saved_hdspst; ++ u_int16_t saved_hdspen; ++ u_int16_t saved_vtotal; ++ u_int16_t saved_vrtrst; ++ u_int16_t saved_vrtren; ++ u_int16_t saved_vdspst; ++ u_int16_t saved_vdspen; ++ ++ /* Fencing */ ++ atomic_t curr_seq; /* The last used stamp number */ ++ struct list_head fence_list; /* List of active fences */ ++ rwlock_t fence_list_lock; /* Lock to protect fence_list */ ++ wait_queue_head_t fence_queue; /* Waitqueue */ ++ struct tasklet_struct fence_tl; /* Tasklet for fence IRQ */ ++ ++ /* A scratch block */ ++ struct drm_mm_node *scratch; ++}; ++ ++ ++/* Private data. This is where we keep our memory management bits */ ++struct drm_glamo_gem_object { ++ struct drm_gem_object *obj; /* The GEM object this refers to */ ++ struct drm_mm_node *block; /* Block handle for drm_mm */ ++ uint64_t mmap_offset; ++}; ++ ++ ++struct glamo_crtc { ++ struct drm_crtc base; ++ struct glamodrm_handle *gdrm; ++ /* a mode_set for fbdev users on this crtc */ ++ struct drm_mode_set mode_set; ++ int blank_mode; ++}; ++ ++ ++struct glamo_framebuffer { ++ struct drm_framebuffer base; ++ struct drm_gem_object *obj; ++}; ++ ++ ++struct glamo_output { ++ struct drm_connector base; ++ struct drm_encoder enc; ++ struct glamodrm_handle *gdrm; ++}; ++ ++ ++/* Colour mode for KMS framebuffer */ ++enum { ++ GLAMO_FB_RGB565, ++ GLAMO_FB_ARGB1555, ++ GLAMO_FB_ARGB4444 ++}; ++ ++ ++#define to_glamo_crtc(x) container_of(x, struct glamo_crtc, base) ++#define to_glamo_output(x) container_of(x, struct glamo_output, base) ++#define enc_to_glamo_output(x) container_of(x, struct glamo_output, enc) ++#define to_glamo_framebuffer(x) container_of(x, struct glamo_framebuffer, base) ++ ++ ++#endif /* __GLAMO_DRMPRIV_H */ +diff --git a/drivers/mfd/glamo/glamo-fence.c b/drivers/mfd/glamo/glamo-fence.c +new file mode 100644 +index 0000000..ab77241 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-fence.c +@@ -0,0 +1,329 @@ ++/* ++ * SMedia Glamo 336x/337x fence objects ++ * ++ * Copyright (c) 2009 Thomas White <taw@bitwiz.org.uk> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see <http://www.gnu.org/licenses/>. ++ * ++ * ++ * Loosely based on radeon_fence.c, to which the following notice applies: ++ * ++ * Copyright 2009 Jerome Glisse. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sub license, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, ++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR ++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE ++ * USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ */ ++/* ++ * Authors: ++ * Jerome Glisse <glisse@freedesktop.org> ++ * Dave Airlie ++ */ ++ ++ ++#include <drm/drmP.h> ++#include <drm/glamo_drm.h> ++#include <linux/kernel.h> ++#include <linux/irq.h> ++#include <linux/interrupt.h> ++#include <linux/spinlock.h> ++#include <linux/lockdep.h> ++ ++#include "glamo-drm-private.h" ++#include "glamo-regs.h" ++#include "glamo-core.h" ++#include "glamo-cmdq.h" ++ ++ ++static struct lock_class_key glamo_fence_lock_key; ++ ++ ++struct glamo_fence ++{ ++ struct list_head list; ++ uint16_t seq; /* Wait for at least this ID */ ++ int signalled; /* Non-zero when fence has passed */ ++ struct glamodrm_handle *gdrm; ++}; ++ ++ ++static void glamo_fence_emit(struct glamo_fence *fence) ++{ ++ u16 fring[6]; ++ ++ fring[0] = 0x8000 | GLAMO_REG_2D_ID1; ++ fring[1] = 3; ++ fence->seq = atomic_inc_return(&fence->gdrm->curr_seq); ++ if ( fence->seq > 1<<14 ) { ++ atomic_set(&fence->gdrm->curr_seq, 0); ++ fence->seq = atomic_inc_return(&fence->gdrm->curr_seq); ++ } ++ fring[2] = 1<<15 | fence->seq; ++ fring[3] = 0; /* Unused */ ++ fring[4] = 0; /* Unused */ ++ fring[5] = 0; /* Padding */ ++ ++ glamo_add_to_ring(fence->gdrm, fring, 12); ++} ++ ++ ++static void glamo_fence_enable(struct glamodrm_handle *gdrm) ++{ ++ glamo_enable_irq(gdrm->glamo_core, GLAMO_IRQ_2D); ++} ++ ++ ++static inline u16 reg_read_2d(struct glamodrm_handle *gdrm, u_int16_t reg) ++{ ++ /* For command queue, the address is given relative to ++ * the overall base of Glamo. This isn't the case here. */ ++ return ioread16(gdrm->twod_base + reg-GLAMO_REGOFS_2D); ++} ++ ++ ++static inline u16 reg_read_cmdq(struct glamodrm_handle *gdrm, u_int16_t reg) ++{ ++ return ioread16(gdrm->reg_base + reg); ++} ++ ++ ++static void glamo_cmdq_wait(struct glamodrm_handle *gdrm, ++ enum glamo_engine engine) ++{ ++ u16 mask, val, status; ++ int i; ++ ++ switch (engine) ++ { ++ case GLAMO_ENGINE_ALL: ++ mask = 1 << 2; ++ val = mask; ++ break; ++ default: ++ return; ++ } ++ ++ for ( i=0; i<1000; i++ ) { ++ status = reg_read_cmdq(gdrm, GLAMO_REG_CMDQ_STATUS); ++ if ((status & mask) == val) break; ++ mdelay(1); ++ } ++ if ( i == 1000 ) { ++ size_t ring_read; ++ printk(KERN_WARNING "[glamo-drm] CmdQ timeout!\n"); ++ printk(KERN_WARNING "[glamo-drm] status = %x\n", status); ++ ring_read = reg_read_cmdq(gdrm, GLAMO_REG_CMDQ_READ_ADDRL); ++ ring_read |= ((reg_read_cmdq(gdrm, GLAMO_REG_CMDQ_READ_ADDRH) ++ & 0x7) << 16); ++ printk(KERN_INFO "[glamo-drm] ring_read now 0x%x\n", ++ ring_read); ++ } ++} ++ ++ ++irqreturn_t glamo_fence_irq_handler(unsigned int irq, void *data) ++{ ++ struct glamodrm_handle *gdrm = data; ++ ++ if (!gdrm) { ++ printk(KERN_ERR "[glamo-drm] 2D IRQ called with no data\n"); ++ return IRQ_NONE; ++ } ++ glamo_clear_irq(gdrm->glamo_core, GLAMO_IRQ_2D); ++ ++ tasklet_schedule(&gdrm->fence_tl); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++/* This is nasty. I'm sorry. */ ++static void glamo_fence_debodge(struct glamodrm_handle *gdrm) ++{ ++ struct list_head *tmp; ++ ++ printk(KERN_ERR "[glamo-drm] Attempting to recover...\n"); ++ ++ glamo_cmdq_wait(gdrm, GLAMO_ENGINE_ALL); ++ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_2D); ++ ++ read_lock(&gdrm->fence_list_lock); ++ list_for_each(tmp, &gdrm->fence_list) { ++ ++ struct glamo_fence *fence; ++ ++ fence = list_entry(tmp, struct glamo_fence, list); ++ ++ if ( fence->signalled != 1 ) { ++ printk(KERN_ERR "[glamo-drm] Fence seq#%i was not" ++ " signalled\n", fence->seq); ++ } ++ fence->signalled = 1; ++ ++ } ++ read_unlock(&gdrm->fence_list_lock); ++ ++ wake_up_all(&gdrm->fence_queue); ++} ++ ++ ++static void glamo_fence_tl(unsigned long data) ++{ ++ struct glamodrm_handle *gdrm = (struct glamodrm_handle *)data; ++ int wake = 0; ++ u16 seq; ++ struct list_head *tmp; ++ ++ seq = reg_read_2d(gdrm, GLAMO_REG_2D_ID1) & 0x7fff; ++ ++ read_lock(&gdrm->fence_list_lock); ++ list_for_each(tmp, &gdrm->fence_list) { ++ ++ struct glamo_fence *fence; ++ ++ fence = list_entry(tmp, struct glamo_fence, list); ++ if ( seq >= fence->seq ) { ++ fence->signalled = 1; ++ wake = 1; ++ } ++ ++ } ++ read_unlock(&gdrm->fence_list_lock); ++ ++ if ( wake ) wake_up_all(&gdrm->fence_queue); ++} ++ ++ ++static struct glamo_fence *glamo_fence_new(struct glamodrm_handle *gdrm) ++{ ++ struct glamo_fence *fence; ++ unsigned long irq_flags; ++ ++ fence = kmalloc(sizeof(*fence), GFP_KERNEL); ++ fence->signalled = 0; ++ fence->gdrm = gdrm; ++ ++ /* Add to list */ ++ write_lock_irqsave(&gdrm->fence_list_lock, irq_flags); ++ list_add(&fence->list, &gdrm->fence_list); ++ write_unlock_irqrestore(&gdrm->fence_list_lock, irq_flags); ++ ++ return fence; ++} ++ ++ ++static struct glamo_fence *glamo_fence_destroy(struct glamo_fence *fence) ++{ ++ unsigned long irq_flags; ++ struct glamodrm_handle *gdrm = fence->gdrm; ++ ++ /* Remove from list */ ++ write_lock_irqsave(&gdrm->fence_list_lock, irq_flags); ++ list_del(&fence->list); ++ write_unlock_irqrestore(&gdrm->fence_list_lock, irq_flags); ++ ++ kfree(fence); ++ ++ return fence; ++} ++ ++ ++int glamo_ioctl_wait_rendering(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ struct glamodrm_handle *gdrm; ++ struct drm_glamo_gem_wait_rendering *args = data; ++ struct glamo_fence *fence; ++ int r; ++ ++ gdrm = dev->dev_private; ++ ++ if ( !args->have_handle ) { ++ glamo_cmdq_wait(gdrm, GLAMO_ENGINE_ALL); ++ return 0; ++ } ++ ++ fence = glamo_fence_new(gdrm); ++ if ( fence == NULL ) { ++ printk(KERN_WARNING "[glamo-drm] Couldn't allocate fence -" ++ " falling back to busy wait.\n"); ++ glamo_cmdq_wait(gdrm, GLAMO_ENGINE_ALL); ++ return 0; ++ } ++ ++ glamo_fence_emit(fence); ++ ++ /* Wait... */ ++ r = wait_event_interruptible_timeout(gdrm->fence_queue, ++ fence->signalled, HZ); ++ if ( r == 0 ) { ++ printk(KERN_ERR "[glamo-drm] Timeout!\n"); ++ glamo_fence_debodge(gdrm); ++ } ++ ++ glamo_fence_destroy(fence); ++ ++ return 0; ++} ++ ++ ++void glamo_fence_init(struct glamodrm_handle *gdrm) ++{ ++ unsigned long irq_flags; ++ ++ if ( gdrm->twod_irq == 0 ) { ++ printk(KERN_ERR "[glamo-drm] Attempted to initialise fence" ++ " system before 2D IRQ registered\n"); ++ return; ++ } ++ ++ gdrm->fence_list_lock = __RW_LOCK_UNLOCKED(gdrm->fence_list_lock); ++ lockdep_set_class(&gdrm->fence_list_lock, &glamo_fence_lock_key); ++ init_waitqueue_head(&gdrm->fence_queue); ++ ++ atomic_set(&gdrm->curr_seq, 0); ++ ++ write_lock_irqsave(&gdrm->fence_list_lock, irq_flags); ++ INIT_LIST_HEAD(&gdrm->fence_list); ++ write_unlock_irqrestore(&gdrm->fence_list_lock, irq_flags); ++ ++ tasklet_init(&gdrm->fence_tl, glamo_fence_tl, (unsigned long)gdrm); ++ ++ glamo_fence_enable(gdrm); ++} ++ ++ ++void glamo_fence_shutdown(struct glamodrm_handle *gdrm) ++{ ++ wake_up_all(&gdrm->fence_queue); ++ tasklet_kill(&gdrm->fence_tl); ++} +diff --git a/drivers/mfd/glamo/glamo-fence.h b/drivers/mfd/glamo/glamo-fence.h +new file mode 100644 +index 0000000..948fae3 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-fence.h +@@ -0,0 +1,36 @@ ++/* ++ * SMedia Glamo 336x/337x fence objects ++ * ++ * Copyright (c) 2009 Thomas White <taw@bitwiz.org.uk> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see <http://www.gnu.org/licenses/>. ++ * ++ */ ++ ++#ifndef __GLAMO_FENCE_H ++#define __GLAMO_FENCE_H ++ ++#include <drm/drmP.h> ++ ++#include "glamo-drm-private.h" ++ ++extern void glamo_fence_irq_handler(unsigned int irq, struct irq_desc *desc); ++ ++extern void glamo_fence_init(struct glamodrm_handle *gdrm); ++extern void glamo_fence_shutdown(struct glamodrm_handle *gdrm); ++ ++extern int glamo_ioctl_wait_rendering(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++ ++#endif /* __GLAMO_FENCE_H */ +diff --git a/drivers/mfd/glamo/glamo-kms-fb.c b/drivers/mfd/glamo/glamo-kms-fb.c +new file mode 100644 +index 0000000..61cd605 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-kms-fb.c +@@ -0,0 +1,540 @@ ++/* ++ * SMedia Glamo 336x/337x KMS Framebuffer ++ * ++ * Copyright (C) 2009 Thomas White <taw@bitwiz.org.uk> ++ * ++ * Based on glamo-fb.c (C) 2007-2008 by Openmoko, Inc. ++ * Author: Harald Welte <laforge@openmoko.org> ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * ++ * Based on intel_fb.c from drivers/gpu/drm/i915 ++ * to which the following licence applies: ++ * ++ * Copyright © 2006-2007 Intel Corporation ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Eric Anholt <eric@anholt.net> ++ * ++ */ ++ ++ ++#include <drm/drmP.h> ++#include <drm/glamo_drm.h> ++#include <drm/drm_crtc_helper.h> ++#include <drm/drm_crtc.h> ++ ++#include "glamo-core.h" ++#include "glamo-drm-private.h" ++#include "glamo-display.h" ++#include "glamo-buffer.h" ++ ++ ++struct glamofb_par { ++ struct drm_device *dev; ++ struct drm_display_mode *our_mode; ++ struct glamo_framebuffer *glamo_fb; ++ int crtc_count; ++ /* crtc currently bound to this */ ++ uint32_t crtc_ids[2]; ++}; ++ ++ ++static int glamofb_setcolreg(unsigned regno, unsigned red, unsigned green, ++ unsigned blue, unsigned transp, ++ struct fb_info *info) ++{ ++ struct glamofb_par *par = info->par; ++ struct drm_device *dev = par->dev; ++ struct drm_crtc *crtc; ++ int i; ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc); ++ struct drm_mode_set *modeset = &glamo_crtc->mode_set; ++ struct drm_framebuffer *fb = modeset->fb; ++ ++ for (i = 0; i < par->crtc_count; i++) ++ if (crtc->base.id == par->crtc_ids[i]) ++ break; ++ ++ if (i == par->crtc_count) ++ continue; ++ ++ ++ if (regno > 255) ++ return 1; ++ ++ if (regno < 16) { ++ switch (fb->depth) { ++ case 15: ++ fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | ++ ((green & 0xf800) >> 6) | ++ ((blue & 0xf800) >> 11); ++ break; ++ case 16: ++ fb->pseudo_palette[regno] = (red & 0xf800) | ++ ((green & 0xfc00) >> 5) | ++ ((blue & 0xf800) >> 11); ++ break; ++ case 24: ++ case 32: ++ fb->pseudo_palette[regno] = ((red & 0xff00) << 8) | ++ (green & 0xff00) | ++ ((blue & 0xff00) >> 8); ++ break; ++ } ++ } ++ } ++ return 0; ++} ++ ++static int glamofb_check_var(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ struct glamofb_par *par = info->par; ++ struct glamo_framebuffer *glamo_fb = par->glamo_fb; ++ struct drm_framebuffer *fb = &glamo_fb->base; ++ int depth; ++ ++ /* Need to resize the fb object !!! */ ++ if (var->xres > fb->width || var->yres > fb->height) { ++ DRM_ERROR("Cannot resize framebuffer object (%dx%d > %dx%d)\n", ++ var->xres,var->yres,fb->width,fb->height); ++ DRM_ERROR("Need resizing code.\n"); ++ return -EINVAL; ++ } ++ ++ switch (var->bits_per_pixel) { ++ case 16: ++ depth = (var->green.length == 6) ? 16 : 15; ++ break; ++ case 32: ++ depth = (var->transp.length > 0) ? 32 : 24; ++ break; ++ default: ++ depth = var->bits_per_pixel; ++ break; ++ } ++ ++ switch (depth) { ++ case 16: ++ var->red.offset = 11; ++ var->green.offset = 5; ++ var->blue.offset = 0; ++ var->red.length = 5; ++ var->green.length = 6; ++ var->blue.length = 5; ++ var->transp.length = 0; ++ var->transp.offset = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* this will let fbcon do the mode init */ ++/* FIXME: take mode config lock? */ ++static int glamofb_set_par(struct fb_info *info) ++{ ++ struct glamofb_par *par = info->par; ++ struct drm_device *dev = par->dev; ++ struct fb_var_screeninfo *var = &info->var; ++ int i; ++ ++ DRM_DEBUG("%d %d\n", var->xres, var->pixclock); ++ ++ if (var->pixclock != -1) { ++ ++ DRM_ERROR("PIXEL CLOCK SET\n"); ++ return -EINVAL; ++ } else { ++ struct drm_crtc *crtc; ++ int ret; ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc); ++ ++ for (i = 0; i < par->crtc_count; i++) ++ if (crtc->base.id == par->crtc_ids[i]) ++ break; ++ ++ if (i == par->crtc_count) ++ continue; ++ ++ if (crtc->fb == glamo_crtc->mode_set.fb) { ++ mutex_lock(&dev->mode_config.mutex); ++ ret = crtc->funcs->set_config(&glamo_crtc->mode_set); ++ mutex_unlock(&dev->mode_config.mutex); ++ if (ret) ++ return ret; ++ } ++ } ++ return 0; ++ } ++} ++ ++static int glamofb_pan_display(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ struct glamofb_par *par = info->par; ++ struct drm_device *dev = par->dev; ++ struct drm_mode_set *modeset; ++ struct drm_crtc *crtc; ++ struct glamo_crtc *glamo_crtc; ++ int ret = 0; ++ int i; ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ for (i = 0; i < par->crtc_count; i++) ++ if (crtc->base.id == par->crtc_ids[i]) ++ break; ++ ++ if (i == par->crtc_count) ++ continue; ++ ++ glamo_crtc = to_glamo_crtc(crtc); ++ modeset = &glamo_crtc->mode_set; ++ ++ modeset->x = var->xoffset; ++ modeset->y = var->yoffset; ++ ++ if (modeset->num_connectors) { ++ mutex_lock(&dev->mode_config.mutex); ++ ret = crtc->funcs->set_config(modeset); ++ mutex_unlock(&dev->mode_config.mutex); ++ if (!ret) { ++ info->var.xoffset = var->xoffset; ++ info->var.yoffset = var->yoffset; ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++static void glamofb_on(struct fb_info *info) ++{ ++ struct glamofb_par *par = info->par; ++ struct drm_device *dev = par->dev; ++ struct drm_crtc *crtc; ++ struct drm_encoder *encoder; ++ int i; ++ ++ /* ++ * For each CRTC in this fb, find all associated encoders ++ * and turn them off, then turn off the CRTC. ++ */ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; ++ ++ for (i = 0; i < par->crtc_count; i++) ++ if (crtc->base.id == par->crtc_ids[i]) ++ break; ++ ++ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); ++ ++ /* Found a CRTC on this fb, now find encoders */ ++ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ++ if (encoder->crtc == crtc) { ++ struct drm_encoder_helper_funcs *encoder_funcs; ++ encoder_funcs = encoder->helper_private; ++ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); ++ } ++ } ++ } ++} ++ ++static void glamofb_off(struct fb_info *info, int dpms_mode) ++{ ++ struct glamofb_par *par = info->par; ++ struct drm_device *dev = par->dev; ++ struct drm_crtc *crtc; ++ struct drm_encoder *encoder; ++ int i; ++ ++ /* ++ * For each CRTC in this fb, find all associated encoders ++ * and turn them off, then turn off the CRTC. ++ */ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; ++ ++ for (i = 0; i < par->crtc_count; i++) ++ if (crtc->base.id == par->crtc_ids[i]) ++ break; ++ ++ /* Found a CRTC on this fb, now find encoders */ ++ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ++ if (encoder->crtc == crtc) { ++ struct drm_encoder_helper_funcs *encoder_funcs; ++ encoder_funcs = encoder->helper_private; ++ encoder_funcs->dpms(encoder, dpms_mode); ++ } ++ } ++ if (dpms_mode == DRM_MODE_DPMS_OFF) ++ crtc_funcs->dpms(crtc, dpms_mode); ++ } ++} ++ ++static int glamofb_blank(int blank, struct fb_info *info) ++{ ++ switch (blank) { ++ case FB_BLANK_UNBLANK: ++ glamofb_on(info); ++ break; ++ case FB_BLANK_NORMAL: ++ glamofb_off(info, DRM_MODE_DPMS_STANDBY); ++ break; ++ case FB_BLANK_HSYNC_SUSPEND: ++ glamofb_off(info, DRM_MODE_DPMS_STANDBY); ++ break; ++ case FB_BLANK_VSYNC_SUSPEND: ++ glamofb_off(info, DRM_MODE_DPMS_SUSPEND); ++ break; ++ case FB_BLANK_POWERDOWN: ++ glamofb_off(info, DRM_MODE_DPMS_OFF); ++ break; ++ } ++ return 0; ++} ++ ++static struct fb_ops glamofb_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = glamofb_check_var, ++ .fb_set_par = glamofb_set_par, ++ .fb_setcolreg = glamofb_setcolreg, ++ .fb_fillrect = cfb_fillrect, ++ .fb_copyarea = cfb_copyarea, ++ .fb_imageblit = cfb_imageblit, ++ .fb_pan_display = glamofb_pan_display, ++ .fb_blank = glamofb_blank, ++}; ++ ++ ++#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1) ++ ++ ++/* Here, we create a GEM object of the correct size, and then turn it into ++ * /dev/fbX so that the kernel can put a console on it. */ ++int glamofb_create(struct drm_device *dev, uint32_t fb_width, ++ uint32_t fb_height, uint32_t surface_width, ++ uint32_t surface_height, int colour_mode, ++ struct glamo_framebuffer **glamo_fb_p) ++{ ++ struct fb_info *info; ++ struct glamofb_par *par; ++ struct drm_framebuffer *fb; ++ struct glamo_framebuffer *glamo_fb; ++ struct drm_mode_fb_cmd mode_cmd; ++ struct drm_gem_object *fbo = NULL; ++ struct drm_glamo_gem_object *gobj; ++ struct device *device = &dev->platform_dev->dev; ++ struct glamodrm_handle *gdrm; ++ int size, ret; ++ unsigned long offs; ++ ++ gdrm = dev->dev_private; ++ ++ mode_cmd.width = surface_width; ++ mode_cmd.height = surface_height; ++ ++ mode_cmd.bpp = 16; ++ mode_cmd.pitch = ALIGN(mode_cmd.width * ((mode_cmd.bpp + 1) / 8), 64); ++ mode_cmd.depth = 16; ++ ++ size = mode_cmd.pitch * mode_cmd.height; ++ size = ALIGN(size, PAGE_SIZE); ++ if ( size > GLAMO_FRAMEBUFFER_ALLOCATION ) { ++ printk(KERN_ERR "[glamo-drm] Not enough memory for fb\n"); ++ ret = -ENOMEM; ++ goto out; ++ } ++ fbo = glamo_gem_object_alloc(dev, GLAMO_FRAMEBUFFER_ALLOCATION, 2); ++ if (!fbo) { ++ printk(KERN_ERR "[glamo-drm] Failed to allocate framebuffer\n"); ++ ret = -ENOMEM; ++ goto out; ++ } ++ gobj = fbo->driver_private; ++ ++ mutex_lock(&dev->struct_mutex); ++ ++ ret = glamo_framebuffer_create(dev, &mode_cmd, &fb, fbo); ++ if (ret) { ++ DRM_ERROR("failed to allocate fb.\n"); ++ goto out_unref; ++ } ++ ++ list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list); ++ ++ glamo_fb = to_glamo_framebuffer(fb); ++ *glamo_fb_p = glamo_fb; ++ ++ info = framebuffer_alloc(sizeof(struct glamofb_par), device); ++ if (!info) { ++ ret = -ENOMEM; ++ goto out_unref; ++ } ++ ++ par = info->par; ++ ++ strcpy(info->fix.id, "glamodrmfb"); ++ info->fix.type = FB_TYPE_PACKED_PIXELS; ++ info->fix.visual = FB_VISUAL_TRUECOLOR; ++ info->fix.type_aux = 0; ++ info->fix.xpanstep = 1; /* doing it in hw */ ++ info->fix.ypanstep = 1; /* doing it in hw */ ++ info->fix.ywrapstep = 0; ++ info->fix.accel = FB_ACCEL_GLAMO; ++ info->fix.type_aux = 0; ++ info->flags = FBINFO_DEFAULT; ++ ++ info->fbops = &glamofb_ops; ++ ++ info->fix.line_length = fb->pitch; ++ info->fix.smem_start = dev->mode_config.fb_base ++ + (unsigned long) gdrm->vram->start; ++ info->fix.smem_len = size; ++ ++ info->flags = FBINFO_DEFAULT; ++ ++ offs = gobj->block->start; ++ info->screen_base = ioremap(gdrm->vram->start + offs + GLAMO_OFFSET_FB, ++ GLAMO_FRAMEBUFFER_ALLOCATION); ++ if (!info->screen_base) { ++ printk(KERN_ERR "[glamo-drm] Couldn't map framebuffer!\n"); ++ ret = -ENOSPC; ++ goto out_unref; ++ } ++ info->screen_size = size; ++ ++ info->pseudo_palette = fb->pseudo_palette; ++ info->var.xres_virtual = fb->width; ++ info->var.yres_virtual = fb->height; ++ info->var.bits_per_pixel = fb->bits_per_pixel; ++ info->var.xoffset = 0; ++ info->var.yoffset = 0; ++ info->var.activate = FB_ACTIVATE_NOW; ++ info->var.height = -1; ++ info->var.width = -1; ++ info->var.xres = fb_width; ++ info->var.yres = fb_height; ++ ++ info->fix.mmio_start = 0; ++ info->fix.mmio_len = 0; ++ ++ info->pixmap.size = 64*1024; ++ info->pixmap.buf_align = 8; ++ info->pixmap.access_align = 32; ++ info->pixmap.flags = FB_PIXMAP_SYSTEM; ++ info->pixmap.scan_align = 1; ++ ++ switch (fb->depth) { ++ case 16: ++ switch ( colour_mode ) { ++ case GLAMO_FB_RGB565: ++ info->var.red.offset = 11; ++ info->var.green.offset = 5; ++ info->var.blue.offset = 0; ++ info->var.red.length = 5; ++ info->var.green.length = 6; ++ info->var.blue.length = 5; ++ info->var.transp.length = 0; ++ break; ++ case GLAMO_FB_ARGB1555: ++ info->var.transp.offset = 15; ++ info->var.red.offset = 10; ++ info->var.green.offset = 5; ++ info->var.blue.offset = 0; ++ info->var.transp.length = 1; ++ info->var.red.length = 5; ++ info->var.green.length = 5; ++ info->var.blue.length = 5; ++ break; ++ case GLAMO_FB_ARGB4444: ++ info->var.transp.offset = 12; ++ info->var.red.offset = 8; ++ info->var.green.offset = 4; ++ info->var.blue.offset = 0; ++ info->var.transp.length = 4; ++ info->var.red.length = 4; ++ info->var.green.length = 4; ++ info->var.blue.length = 4; ++ break; ++ } ++ break; ++ case 24: ++ case 32: ++ default: ++ /* The Smedia Glamo doesn't support anything but 16bit color */ ++ printk(KERN_ERR "[glamo-drm] Only 16bpp is supported.\n"); ++ return -EINVAL; ++ } ++ ++ fb->fbdev = info; ++ par->glamo_fb = glamo_fb; ++ par->dev = dev; ++ gdrm->fb = info; ++ ++ info->var.pixclock = -1; ++ ++ printk(KERN_INFO "[glamo-drm] Allocated %dx%d fb: bo %p\n", ++ glamo_fb->base.width, glamo_fb->base.height, fbo); ++ mutex_unlock(&dev->struct_mutex); ++ return 0; ++ ++out_unref: ++ drm_gem_object_unreference(fbo); ++ mutex_unlock(&dev->struct_mutex); ++out: ++ return ret; ++} ++ ++ ++void glamo_kmsfb_suspend(struct glamodrm_handle *gdrm) ++{ ++ fb_set_suspend(gdrm->fb, 1); ++} ++ ++ ++void glamo_kmsfb_resume(struct glamodrm_handle *gdrm) ++{ ++ fb_set_suspend(gdrm->fb, 0); ++} +diff --git a/drivers/mfd/glamo/glamo-kms-fb.h b/drivers/mfd/glamo/glamo-kms-fb.h +new file mode 100644 +index 0000000..1960e76 +--- /dev/null ++++ b/drivers/mfd/glamo/glamo-kms-fb.h +@@ -0,0 +1,41 @@ ++/* ++ * SMedia Glamo 336x/337x KMS framebuffer ++ * ++ * Copyright (C) 2009 Thomas White <taw@bitwiz.org.uk> ++ * ++ * Based on glamo-fb.c (C) 2007-2008 by Openmoko, Inc. ++ * Author: Harald Welte <laforge@openmoko.org> ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __GLAMO_KMS_FB_H ++#define __GLAMO_KMS_FB_H ++ ++#include <drm/drmP.h> ++#include "glamo-drm-private.h" ++ ++extern int glamofb_create(struct drm_device *dev, uint32_t fb_width, ++ uint32_t fb_height, uint32_t surface_width, ++ uint32_t surface_height, int colour_mode, ++ struct glamo_framebuffer **glamo_fb_p); ++ ++extern void glamo_kmsfb_suspend(struct glamodrm_handle *gdrm); ++extern void glamo_kmsfb_resume(struct glamodrm_handle *gdrm); ++ ++#endif /* __GLAMO_KMS_FB_H */ +diff --git a/include/drm/Kbuild b/include/drm/Kbuild +index b940fdf..48b7b55 100644 +--- a/include/drm/Kbuild ++++ b/include/drm/Kbuild +@@ -8,3 +8,4 @@ unifdef-y += radeon_drm.h + unifdef-y += sis_drm.h + unifdef-y += savage_drm.h + unifdef-y += via_drm.h ++unifdef-y += glamo_drm.h +diff --git a/include/drm/glamo_drm.h b/include/drm/glamo_drm.h +new file mode 100644 +index 0000000..4c194dc +--- /dev/null ++++ b/include/drm/glamo_drm.h +@@ -0,0 +1,153 @@ ++/* glamo_drm.h -- Public header for the Glamo driver ++ * ++ * Copyright 2009 Thomas White ++ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. ++ * Copyright 2000 VA Linux Systems, Inc., Fremont, California. ++ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. ++ * All rights reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Thomas White <taw@bitwiz.org.uk> ++ * Kevin E. Martin <martin@valinux.com> ++ * Gareth Hughes <gareth@valinux.com> ++ * Keith Whitwell <keith@tungstengraphics.com> ++ */ ++ ++#ifndef __GLAMO_DRM_H__ ++#define __GLAMO_DRM_H__ ++ ++#include "drm.h" ++ ++#define GLAMO_GEM_DOMAIN_VRAM (0x1) ++ ++/* Glamo specific ioctls */ ++#define DRM_GLAMO_CMDBUF 0x01 ++#define DRM_GLAMO_SWAP 0x02 ++#define DRM_GLAMO_CMDBURST 0x03 ++ ++#define DRM_GLAMO_GEM_INFO 0x1c ++#define DRM_GLAMO_GEM_CREATE 0x1d ++#define DRM_GLAMO_GEM_MMAP 0x1e ++#define DRM_GLAMO_GEM_PIN 0x1f ++#define DRM_GLAMO_GEM_UNPIN 0x20 ++#define DRM_GLAMO_GEM_PREAD 0x21 ++#define DRM_GLAMO_GEM_PWRITE 0x22 ++#define DRM_GLAMO_GEM_WAIT_RENDERING 0x24 ++ ++#define DRM_IOCTL_GLAMO_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_GLAMO_CMDBUF, drm_glamo_cmd_buffer_t) ++#define DRM_IOCTL_GLAMO_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_GLAMO_SWAP) ++#define DRM_IOCTL_GLAMO_CMDBURST DRM_IOW(DRM_COMMAND_BASE + DRM_GLAMO_CMDBURST, drm_glamo_cmd_burst_t) ++ ++#define DRM_IOCTL_GLAMO_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_INFO, struct drm_glamo_gem_info) ++#define DRM_IOCTL_GLAMO_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_CREATE, struct drm_glamo_gem_create) ++#define DRM_IOCTL_GLAMO_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_MMAP, struct drm_glamo_gem_mmap) ++#define DRM_IOCTL_GLAMO_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_PIN, struct drm_glamo_gem_pin) ++#define DRM_IOCTL_GLAMO_GEM_UNPIN DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_UNPIN, struct drm_glamo_gem_unpin) ++#define DRM_IOCTL_GLAMO_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_PREAD, struct drm_glamo_gem_pread) ++#define DRM_IOCTL_GLAMO_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_PWRITE, struct drm_glamo_gem_pwrite) ++#define DRM_IOCTL_GLAMO_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_GLAMO_GEM_WAIT_RENDERING, struct drm_glamo_gem_wait_rendering) ++ ++ ++/* Simple command submission - a list of 16-bit address-data pairs */ ++typedef struct drm_glamo_cmd_buffer { ++ unsigned int bufsz; /* Size of buffer, in bytes */ ++ char __user *buf; /* Buffer of stuff to go onto the ring buffer */ ++ unsigned int *obj_pos; /* Offsets (in bytes) at which to put objs */ ++ uint32_t *objs; /* List of buffer object (handles) to use */ ++ unsigned int nobjs; /* Number of objects referenced */ ++ int nbox; ++ struct drm_clip_rect __user *boxes; ++} drm_glamo_cmd_buffer_t; ++ ++ ++/* Burst command submission - base address and data: ++ * - Data can be 32-bit (more easily) ++ * - Easier for the kernel to validate */ ++typedef struct drm_glamo_cmd_burst { ++ uint16_t base; /* Base address (command) */ ++ int bufsz; /* Size of data, in bytes */ ++ uint16_t *data; /* Pointer to data */ ++ unsigned int *obj_pos; /* Offsets (in bytes) at which to put objs */ ++ uint32_t *objs; /* List of buffer object (handles) to use */ ++ unsigned int nobjs; /* Number of objects referenced */ ++} drm_glamo_cmd_burst_t; ++ ++struct drm_glamo_gem_info { ++ uint64_t vram_start; ++ uint64_t vram_size; ++}; ++ ++struct drm_glamo_gem_create { ++ uint64_t size; ++ uint64_t alignment; ++ uint32_t handle; ++ uint32_t initial_domain; // to allow VRAM to be created ++ uint32_t no_backing_store; ++}; ++ ++struct drm_glamo_gem_mmap { ++ uint32_t handle; /* Handle goes in... */ ++ uint64_t offset; /* ...offset comes out */ ++}; ++ ++struct drm_glamo_gem_wait_rendering { ++ uint32_t handle; ++ int have_handle; ++}; ++ ++struct drm_glamo_gem_pin { ++ uint32_t handle; ++ uint32_t pin_domain; ++ uint64_t alignment; ++ uint64_t offset; ++}; ++ ++struct drm_glamo_gem_unpin { ++ uint32_t handle; ++ uint32_t pad; ++}; ++ ++struct drm_glamo_gem_pread { ++ /** Handle for the object being read. */ ++ uint32_t handle; ++ uint32_t pad; ++ /** Offset into the object to read from */ ++ uint64_t offset; ++ /** Length of data to read */ ++ uint64_t size; ++ /** Pointer to write the data into. */ ++ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ ++}; ++ ++struct drm_glamo_gem_pwrite { ++ /** Handle for the object being written to. */ ++ uint32_t handle; ++ uint32_t pad; ++ /** Offset into the object to write to */ ++ uint64_t offset; ++ /** Length of data to write */ ++ uint64_t size; ++ /** Pointer to read the data from. */ ++ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ ++}; ++ ++#endif +-- +1.6.5.3 + diff --git a/recipes/linux/linux-openmoko-2.6.31/0003-Work-on-Glamo-core-for-DRM.patch b/recipes/linux/linux-openmoko-2.6.31/0003-Work-on-Glamo-core-for-DRM.patch new file mode 100644 index 0000000000..76223ed136 --- /dev/null +++ b/recipes/linux/linux-openmoko-2.6.31/0003-Work-on-Glamo-core-for-DRM.patch @@ -0,0 +1,252 @@ +From 50c9919c9bc7d3e1db72dcbdd62d73efad409720 Mon Sep 17 00:00:00 2001 +From: Thomas White <taw@bitwiz.org.uk> +Date: Tue, 17 Nov 2009 23:45:29 +0100 +Subject: [PATCH 3/4] Work on Glamo-core for DRM + +This adds modifications to the core of the Glamo driver to expose functionality +to support DRM and KMS. + +Signed-off-by: Thomas White <taw@bitwiz.org.uk> +--- + drivers/mfd/glamo/glamo-core.c | 85 +++++++++++++++++++++++++++++++++++++--- + drivers/mfd/glamo/glamo-core.h | 45 ++++++++++++++++----- + drivers/mfd/glamo/glamo-regs.h | 24 +++++++++++ + include/linux/mfd/glamo.h | 7 +-- + 4 files changed, 140 insertions(+), 21 deletions(-) + +diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c +index e0e3940..32aeff1 100644 +--- a/drivers/mfd/glamo/glamo-core.c ++++ b/drivers/mfd/glamo/glamo-core.c +@@ -221,10 +221,31 @@ static struct resource glamo_fb_resources[] = { + .flags = IORESOURCE_MEM, + }, { + .name = "glamo-fb-mem", +- .start = GLAMO_OFFSET_FB, +- .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1, ++ .start = GLAMO_MEM_BASE + GLAMO_OFFSET_FB, ++ .end = GLAMO_MEM_BASE + GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1, + .flags = IORESOURCE_MEM, +- }, ++ }, { ++ .name = "glamo-cmdq-regs", ++ .start = GLAMO_REGOFS_CMDQUEUE, ++ .end = GLAMO_REGOFS_RISC - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .name = "glamo-command-queue", ++ .start = GLAMO_MEM_BASE + GLAMO_OFFSET_CMDQ, ++ .end = GLAMO_MEM_BASE + GLAMO_OFFSET_CMDQ + ++ GLAMO_CMDQ_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .name = "glamo-2d-regs", ++ .start = GLAMO_REGOFS_2D, ++ .end = GLAMO_REGOFS_3D- 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .name = "glamo-2d-irq", ++ .start = GLAMO_IRQ_2D, ++ .end = GLAMO_IRQ_2D, ++ .flags = IORESOURCE_IRQ, ++ } + }; + + static struct resource glamo_mmc_resources[] = { +@@ -235,9 +256,9 @@ static struct resource glamo_mmc_resources[] = { + .flags = IORESOURCE_MEM + }, { + .name = "glamo-mmc-mem", +- .start = GLAMO_OFFSET_FB + GLAMO_FB_SIZE, +- .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE + +- GLAMO_MMC_BUFFER_SIZE - 1, ++ .start = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC, ++ .end = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC ++ + GLAMO_MMC_BUFFER_SIZE - 1, + .flags = IORESOURCE_MEM + }, { + .start = GLAMO_IRQ_MMC, +@@ -354,6 +375,24 @@ static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc) + sysfs + */ + ++void glamo_clear_irq(struct glamo_core *glamo, unsigned int irq) ++{ ++ /* set interrupt source */ ++ __reg_write(glamo, GLAMO_REG_IRQ_CLEAR, irq); ++} ++ ++ ++void glamo_enable_irq(struct glamo_core *glamo, unsigned int irq) ++{ ++ u_int16_t tmp; ++ ++ /* set bit in enable register */ ++ tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE); ++ tmp |= irq; ++ __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp); ++} ++ ++ + static ssize_t regs_write(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) + { +@@ -579,6 +618,40 @@ int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine) + } + EXPORT_SYMBOL_GPL(glamo_engine_disable); + ++ ++static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = { ++ [GLAMO_ENGINE_LCD] = GLAMO_REG_CLOCK_LCD, ++ [GLAMO_ENGINE_MMC] = GLAMO_REG_CLOCK_MMC, ++ [GLAMO_ENGINE_ISP] = GLAMO_REG_CLOCK_ISP, ++ [GLAMO_ENGINE_JPEG] = GLAMO_REG_CLOCK_JPEG, ++ [GLAMO_ENGINE_3D] = GLAMO_REG_CLOCK_3D, ++ [GLAMO_ENGINE_2D] = GLAMO_REG_CLOCK_2D, ++ [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG, ++ [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG, ++}; ++ ++void glamo_engine_clkreg_set(struct glamo_core *glamo, ++ enum glamo_engine engine, ++ u_int16_t mask, u_int16_t val) ++{ ++ reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val); ++} ++EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set); ++ ++u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo, ++ enum glamo_engine engine) ++{ ++ u_int16_t val; ++ ++ spin_lock(&glamo->lock); ++ val = __reg_read(glamo, engine_clock_regs[engine]); ++ spin_unlock(&glamo->lock); ++ ++ return val; ++} ++EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get); ++ ++ + int __glamo_engine_suspend(struct glamo_core *glamo, enum glamo_engine engine) + { + int i; +diff --git a/drivers/mfd/glamo/glamo-core.h b/drivers/mfd/glamo/glamo-core.h +index e5b1a35..ea6caa3 100644 +--- a/drivers/mfd/glamo/glamo-core.h ++++ b/drivers/mfd/glamo/glamo-core.h +@@ -3,18 +3,33 @@ + + #include <linux/mfd/glamo.h> + ++/* Amount of Glamo memory */ ++#define GLAMO_INTERNAL_RAM_SIZE 0x800000 ++ ++/* Arbitrarily determined amount for the hardware cursor */ ++#define GLAMO_CURSOR_SIZE (4096) ++#define GLAMO_MMC_BUFFER_SIZE (64 * 1024) /* 64k MMC buffer */ ++#define GLAMO_CMDQ_SIZE (128 * 1024) /* 128k ring buffer */ ++/* Remaining memory will be used for 2D and 3D graphics */ ++#define GLAMO_FB_SIZE (GLAMO_INTERNAL_RAM_SIZE \ ++ - GLAMO_CURSOR_SIZE \ ++ - GLAMO_MMC_BUFFER_SIZE \ ++ - GLAMO_CMDQ_SIZE) ++/* A 640x480, 16bpp, double-buffered framebuffer */ ++#if (GLAMO_FB_SIZE < (640 * 480 * 4)) /* == 0x12c000 */ ++#error Not enough Glamo VRAM for framebuffer! ++#endif ++ + /* for the time being, we put the on-screen framebuffer into the lowest + * VRAM space. This should make the code easily compatible with the various +- * 2MB/4MB/8MB variants of the Smedia chips */ +-#define GLAMO_OFFSET_VRAM 0x800000 +-#define GLAMO_OFFSET_FB (GLAMO_OFFSET_VRAM) +- +-/* we only allocate the minimum possible size for the framebuffer to make +- * sure we have sufficient memory for other functions of the chip */ +-/*#define GLAMO_FB_SIZE (640*480*4) *//* == 0x12c000 */ +-#define GLAMO_INTERNAL_RAM_SIZE 0x800000 +-#define GLAMO_MMC_BUFFER_SIZE (64 * 1024) +-#define GLAMO_FB_SIZE (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE) ++ * 2MB/4MB/8MB variants of the Smedia chips ++ * glamo-fb.c assumes FB comes first, followed by cursor, so DON'T MOVE THEM ++ * (see glamo_regs[] in glamo-fb.c for more information) */ ++#define GLAMO_MEM_BASE (0x800000) ++#define GLAMO_OFFSET_FB (0x000000) ++#define GLAMO_OFFSET_CURSOR (GLAMO_OFFSET_FB + GLAMO_FB_SIZE) ++#define GLAMO_OFFSET_MMC (GLAMO_OFFSET_CURSOR + GLAMO_CURSOR_SIZE) ++#define GLAMO_OFFSET_CMDQ (GLAMO_OFFSET_MMC + GLAMO_MMC_BUFFER_SIZE) + + enum glamo_pll { + GLAMO_PLL1, +@@ -57,4 +72,14 @@ void glamo_reg_read_batch(struct glamo_core *glamo, uint16_t reg, + uint16_t count, uint16_t *values); + void glamo_reg_write_batch(struct glamo_core *glamo, uint16_t reg, + uint16_t count, uint16_t *values); ++void glamo_engine_clkreg_set(struct glamo_core *glamo, ++ enum glamo_engine engine, ++ u_int16_t mask, u_int16_t val); ++ ++extern void glamo_clear_irq(struct glamo_core *glamo, unsigned int irq); ++extern void glamo_enable_irq(struct glamo_core *glamo, unsigned int irq); ++ ++u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo, ++ enum glamo_engine engine); ++ + #endif /* __GLAMO_CORE_H */ +diff --git a/drivers/mfd/glamo/glamo-regs.h b/drivers/mfd/glamo/glamo-regs.h +index 59848e1..8b2fd47 100644 +--- a/drivers/mfd/glamo/glamo-regs.h ++++ b/drivers/mfd/glamo/glamo-regs.h +@@ -627,4 +627,28 @@ enum glamo_core_revisions { + GLAMO_CORE_REV_A3 = 0x0003, + }; + ++enum glamo_register_cq { ++ GLAMO_REG_CMDQ_BASE_ADDRL = 0x00, ++ GLAMO_REG_CMDQ_BASE_ADDRH = 0x02, ++ GLAMO_REG_CMDQ_LEN = 0x04, ++ GLAMO_REG_CMDQ_WRITE_ADDRL = 0x06, ++ GLAMO_REG_CMDQ_WRITE_ADDRH = 0x08, ++ GLAMO_REG_CMDQ_FLIP = 0x0a, ++ GLAMO_REG_CMDQ_CONTROL = 0x0c, ++ GLAMO_REG_CMDQ_READ_ADDRL = 0x0e, ++ GLAMO_REG_CMDQ_READ_ADDRH = 0x10, ++ GLAMO_REG_CMDQ_STATUS = 0x12, ++}; ++ ++#define REG_2D(x) (GLAMO_REGOFS_2D+(x)) ++ ++enum glamo_register_2d { ++ GLAMO_REG_2D_DST_X = REG_2D(0x0a), ++ GLAMO_REG_2D_COMMAND1 = REG_2D(0x3a), ++ GLAMO_REG_2D_STATUS = REG_2D(0x42), ++ GLAMO_REG_2D_ID1 = REG_2D(0x44), ++ GLAMO_REG_2D_ID2 = REG_2D(0x46), ++ GLAMO_REG_2D_ID3 = REG_2D(0x48), ++}; ++ + #endif /* _GLAMO_REGS_H */ +diff --git a/include/linux/mfd/glamo.h b/include/linux/mfd/glamo.h +index 529d4f0..ea91a06 100644 +--- a/include/linux/mfd/glamo.h ++++ b/include/linux/mfd/glamo.h +@@ -41,12 +41,9 @@ enum glamo_engine { + GLAMO_ENGINE_RISC = 11, + GLAMO_ENGINE_MICROP1_MPEG_ENC = 12, + GLAMO_ENGINE_MICROP1_MPEG_DEC = 13, +-#if 0 +- GLAMO_ENGINE_H264_DEC = 14, +- GLAMO_ENGINE_RISC1 = 15, +- GLAMO_ENGINE_SPI = 16, +-#endif + __NUM_GLAMO_ENGINES + }; + ++#define GLAMO_ENGINE_ALL (__NUM_GLAMO_ENGINES) ++ + #endif +-- +1.6.5.3 + diff --git a/recipes/linux/linux-openmoko-2.6.31/0004-Add-JBT6k74-hook-for-use-by-KMS.patch b/recipes/linux/linux-openmoko-2.6.31/0004-Add-JBT6k74-hook-for-use-by-KMS.patch new file mode 100644 index 0000000000..a223f5b7a9 --- /dev/null +++ b/recipes/linux/linux-openmoko-2.6.31/0004-Add-JBT6k74-hook-for-use-by-KMS.patch @@ -0,0 +1,49 @@ +From 6035b76b940c71e30824921271e8c3da8047f869 Mon Sep 17 00:00:00 2001 +From: Thomas White <taw@bitwiz.org.uk> +Date: Sat, 21 Nov 2009 21:42:16 +0100 +Subject: [PATCH 4/4] Add JBT6k74 hook for use by KMS + +Signed-off-by: Thomas White <taw@bitwiz.org.uk> +--- + drivers/video/backlight/jbt6k74.c | 18 ++++++++++++++++++ + 1 files changed, 18 insertions(+), 0 deletions(-) + +diff --git a/drivers/video/backlight/jbt6k74.c b/drivers/video/backlight/jbt6k74.c +index b1aacb7..b9d02f2 100644 +--- a/drivers/video/backlight/jbt6k74.c ++++ b/drivers/video/backlight/jbt6k74.c +@@ -688,6 +688,22 @@ static int jbt6k74_get_power(struct lcd_device *ld) + } + } + ++/* This is utterly, totally horrible. I'm REALLY sorry... */ ++struct jbt_info *jbt_global; ++void jbt6k74_action(int val) ++{ ++ if ( !jbt_global ) { ++ printk(KERN_CRIT "JBT not initialised!!!\n"); ++ return; ++ } ++ if ( val == 0 ) { ++ jbt6k74_enter_power_mode(jbt_global, JBT_POWER_MODE_SLEEP); ++ } else { ++ jbt6k74_enter_power_mode(jbt_global, JBT_POWER_MODE_NORMAL); ++ } ++} ++EXPORT_SYMBOL_GPL(jbt6k74_action); ++ + struct lcd_ops jbt6k74_lcd_ops = { + .set_power = jbt6k74_set_power, + .get_power = jbt6k74_get_power, +@@ -718,6 +734,8 @@ static int __devinit jbt_probe(struct spi_device *spi) + if (!jbt) + return -ENOMEM; + ++ jbt_global = jbt; ++ + jbt->spi = spi; + + jbt->lcd_dev = lcd_device_register("jbt6k74-lcd", &spi->dev, jbt, +-- +1.6.5.3 + diff --git a/recipes/linux/linux-openmoko-2.6.31_git.bb b/recipes/linux/linux-openmoko-2.6.31_git.bb index d65c964a08..d4622e1345 100644 --- a/recipes/linux/linux-openmoko-2.6.31_git.bb +++ b/recipes/linux/linux-openmoko-2.6.31_git.bb @@ -8,13 +8,21 @@ KERNEL_VERSION = "${KERNEL_RELEASE}" OEV = "oe1" PV = "${KERNEL_RELEASE}-${OEV}+gitr${SRCREV}" -PR = "r1" +PR = "r2" SRC_URI = "\ git://git.openmoko.org/git/kernel.git;protocol=git;branch=om-2.6.31 \ +# build fix file://0001-wm8753-fix-build-with-gcc-4.4.2-which-works-ok-with-.patch;patch=1 \ +# patches from Weiss's gdrm-2.6.31 branch + file://0001-DRM-for-platform-devices.patch;patch=1 \ + file://0002-Glamo-DRM-and-KMS-driver.patch;patch=1 \ + file://0003-Work-on-Glamo-core-for-DRM.patch;patch=1 \ + file://0004-Add-JBT6k74-hook-for-use-by-KMS.patch;patch=1 \ +# enable UBI+DRM file://0004-gta02_defconfig-Enable-UBI-support.patch;patch=1 \ file://0005-gta02_defconfig-Enable-UBI-debug.patch;patch=1 \ + file://0001-gta02_defconfig-Enable-GLAMO_DRM.patch;patch=1 \ " S = "${WORKDIR}/git" diff --git a/recipes/uclibc/uclibc-initial_nios2-0.9.27.bb b/recipes/uclibc/uclibc-initial_nios2-0.9.27.bb new file mode 100644 index 0000000000..f4bab53b4e --- /dev/null +++ b/recipes/uclibc/uclibc-initial_nios2-0.9.27.bb @@ -0,0 +1,37 @@ +SECTION = "base" +require uclibc_${PV}.bb + +FILESPATH = "${@base_set_filespath([ '${FILE_DIRNAME}/uclibc-${PV}', '${FILE_DIRNAME}/uclibc', '${FILE_DIRNAME}/files', '${FILE_DIRNAME}' ], d)}" + +DEPENDS = "linux-libc-headers virtual/${TARGET_PREFIX}gcc-initial" +PROVIDES = "virtual/${TARGET_PREFIX}libc-initial" +PACKAGES = "" + +do_stage() { + # Install initial headers into the cross dir + make -j1 PREFIX= DEVEL_PREFIX=${UCLIBC_STAGE_PREFIX}/ \ + RUNTIME_PREFIX=${UCLIBC_STAGE_PREFIX}/ \ + pregen install_dev + make -j1 PREFIX= DEVEL_PREFIX=${UCLIBC_STAGE_PREFIX}/ \ + RUNTIME_PREFIX=${UCLIBC_STAGE_PREFIX}/ \ + libc/sysdeps/linux/${TARGET_ARCH}/crt1.o \ + libc/sysdeps/linux/${TARGET_ARCH}/crti.o \ + libc/sysdeps/linux/${TARGET_ARCH}/crtn.o + + ln -sf include ${CROSS_DIR}/${TARGET_SYS}/sys-include + + # This conflicts with the c++ version of this header + rm -f ${UCLIBC_STAGE_PREFIX}/include/bits/atomicity.h + install -m 644 libc/sysdeps/linux/${TARGET_ARCH}/crt[0in].o ${UCLIBC_STAGE_PREFIX}/lib + ${CC} -nostdlib -nostartfiles -shared -x c /dev/null \ + -o ${UCLIBC_STAGE_PREFIX}/lib/libc.so + +} + +do_install() { + : +} + +do_compile () { + : +} diff --git a/recipes/uclibc/uclibc-nios-0.9.27/nios2/uClibc.config b/recipes/uclibc/uclibc-nios-0.9.27/nios2/uClibc.config new file mode 100644 index 0000000000..d180532464 --- /dev/null +++ b/recipes/uclibc/uclibc-nios-0.9.27/nios2/uClibc.config @@ -0,0 +1,186 @@ +# +# Automatically generated make config: don't edit +# Wed Feb 4 08:55:49 2009 +# +# TARGET_alpha is not set +# TARGET_arm is not set +# TARGET_bfin is not set +# TARGET_cris is not set +# TARGET_e1 is not set +# TARGET_frv is not set +# TARGET_h8300 is not set +# TARGET_hppa is not set +# TARGET_i386 is not set +# TARGET_i960 is not set +# TARGET_ia64 is not set +# TARGET_m68k is not set +# TARGET_microblaze is not set +# TARGET_mips is not set +# TARGET_nios is not set +TARGET_nios2=y +# TARGET_powerpc is not set +# TARGET_sh is not set +# TARGET_sh64 is not set +# TARGET_sparc is not set +# TARGET_v850 is not set +# TARGET_vax is not set +# TARGET_x86_64 is not set + +# +# Target Architecture Features and Options +# +TARGET_ARCH="nios2" +FORCE_OPTIONS_FOR_ARCH=y +TARGET_SUBARCH="" +# UCLIBC_FORMAT_ELF is not set +# UCLIBC_FORMAT_FDPIC_ELF is not set +UCLIBC_FORMAT_FLAT=y +# UCLIBC_FORMAT_FLAT_SEP_DATA is not set +# UCLIBC_FORMAT_SHARED_FLAT is not set +ARCH_LITTLE_ENDIAN=y + +# +# Using Little Endian +# +ARCH_HAS_NO_MMU=y + +# +# Target CPU lacks a memory management unit (MMU) +# +UCLIBC_HAS_FLOATS=y +# UCLIBC_HAS_FPU is not set +UCLIBC_HAS_SOFT_FLOAT=y +DO_C99_MATH=y +KERNEL_HEADERS="" +UCLIBC_UCLINUX_BROKEN_MUNMAP=y +EXCLUDE_BRK=y +HAVE_DOT_CONFIG=y + +# +# General Library Settings +# +HAVE_NO_PIC=y +HAVE_NO_SHARED=y +ARCH_HAS_NO_LDSO=y +UCLIBC_CTOR_DTOR=y +# HAS_NO_THREADS is not set +UCLIBC_HAS_THREADS=y +# PTHREADS_DEBUG_SUPPORT is not set +LINUXTHREADS_OLD=y +UCLIBC_HAS_LFS=y +MALLOC=y +# MALLOC_SIMPLE is not set +# MALLOC_STANDARD is not set +MALLOC_GLIBC_COMPAT=y +UCLIBC_DYNAMIC_ATEXIT=y +# COMPAT_ATEXIT is not set +# UCLIBC_SUSV3_LEGACY is not set +# UCLIBC_SUSV3_LEGACY_MACROS is not set +UCLIBC_HAS_SHADOW=y +# UCLIBC_HAS_PROGRAM_INVOCATION_NAME is not set +UCLIBC_HAS___PROGNAME=y +# UNIX98PTY_ONLY is not set +ASSUME_DEVPTS=y +UCLIBC_HAS_TM_EXTENSIONS=y +UCLIBC_HAS_TZ_CACHING=y +UCLIBC_HAS_TZ_FILE=y +UCLIBC_HAS_TZ_FILE_READ_MANY=y +UCLIBC_TZ_FILE_PATH="/etc/TZ" + +# +# Advanced Library Settings +# +UCLIBC_PWD_BUFFER_SIZE=256 +UCLIBC_GRP_BUFFER_SIZE=256 + +# +# Networking Support +# +# UCLIBC_HAS_IPV6 is not set +UCLIBC_HAS_RPC=y +UCLIBC_HAS_FULL_RPC=y +UCLIBC_HAS_REENTRANT_RPC=y +# UCLIBC_USE_NETLINK is not set +# UCLIBC_HAS_BSD_RES_CLOSE is not set + +# +# String and Stdio Support +# +UCLIBC_HAS_STRING_GENERIC_OPT=y +UCLIBC_HAS_STRING_ARCH_OPT=y +UCLIBC_HAS_CTYPE_TABLES=y +UCLIBC_HAS_CTYPE_SIGNED=y +# UCLIBC_HAS_CTYPE_UNSAFE is not set +UCLIBC_HAS_CTYPE_CHECKED=y +# UCLIBC_HAS_CTYPE_ENFORCED is not set +UCLIBC_HAS_WCHAR=y +# UCLIBC_HAS_LOCALE is not set +UCLIBC_HAS_HEXADECIMAL_FLOATS=y +UCLIBC_HAS_GLIBC_CUSTOM_PRINTF=y +UCLIBC_PRINTF_SCANF_POSITIONAL_ARGS=9 +UCLIBC_HAS_SCANF_GLIBC_A_FLAG=y +# UCLIBC_HAS_STDIO_BUFSIZ_NONE is not set +# UCLIBC_HAS_STDIO_BUFSIZ_256 is not set +# UCLIBC_HAS_STDIO_BUFSIZ_512 is not set +# UCLIBC_HAS_STDIO_BUFSIZ_1024 is not set +# UCLIBC_HAS_STDIO_BUFSIZ_2048 is not set +UCLIBC_HAS_STDIO_BUFSIZ_4096=y +# UCLIBC_HAS_STDIO_BUFSIZ_8192 is not set +UCLIBC_HAS_STDIO_BUILTIN_BUFFER_NONE=y +# UCLIBC_HAS_STDIO_BUILTIN_BUFFER_4 is not set +# UCLIBC_HAS_STDIO_BUILTIN_BUFFER_8 is not set +# UCLIBC_HAS_STDIO_SHUTDOWN_ON_ABORT is not set +UCLIBC_HAS_STDIO_GETC_MACRO=y +UCLIBC_HAS_STDIO_PUTC_MACRO=y +UCLIBC_HAS_STDIO_AUTO_RW_TRANSITION=y +# UCLIBC_HAS_FOPEN_LARGEFILE_MODE is not set +UCLIBC_HAS_FOPEN_EXCLUSIVE_MODE=y +UCLIBC_HAS_GLIBC_CUSTOM_STREAMS=y +UCLIBC_HAS_PRINTF_M_SPEC=y +UCLIBC_HAS_ERRNO_MESSAGES=y +# UCLIBC_HAS_SYS_ERRLIST is not set +UCLIBC_HAS_SIGNUM_MESSAGES=y +# UCLIBC_HAS_SYS_SIGLIST is not set +UCLIBC_HAS_GNU_GETOPT=y +UCLIBC_HAS_GNU_GETSUBOPT=y + +# +# Big and Tall +# +UCLIBC_HAS_REGEX=y +UCLIBC_HAS_REGEX_OLD=y +UCLIBC_HAS_FNMATCH=y +UCLIBC_HAS_FNMATCH_OLD=y +# UCLIBC_HAS_WORDEXP is not set +UCLIBC_HAS_FTW=y +UCLIBC_HAS_GLOB=y +UCLIBC_HAS_GNU_GLOB=y + +# +# Library Installation Options +# +RUNTIME_PREFIX="/" +DEVEL_PREFIX="/usr/" + +# +# Security options +# +# UCLIBC_HAS_ARC4RANDOM is not set +# HAVE_NO_SSP is not set +# UCLIBC_HAS_SSP is not set +# UCLIBC_BUILD_NOEXECSTACK is not set + +# +# uClibc development/debugging options +# +CROSS_COMPILER_PREFIX="" +UCLIBC_EXTRA_CFLAGS="" +# DODEBUG is not set +# DODEBUG_PT is not set +DOSTRIP=y +# DOASSERTS is not set +# UCLIBC_MALLOC_DEBUGGING is not set +WARNINGS="-Wall" +# EXTRA_WARNINGS is not set +# DOMULTI is not set +# UCLIBC_MJN3_ONLY is not set diff --git a/recipes/uclibc/uclibc_nios2-0.9.27.bb b/recipes/uclibc/uclibc_nios2-0.9.27.bb new file mode 100644 index 0000000000..c56194699d --- /dev/null +++ b/recipes/uclibc/uclibc_nios2-0.9.27.bb @@ -0,0 +1,10 @@ +DEFAULT_PREFERENCE = "1" +PR = "r1" + +require uclibc.inc + +SRC_URI += "http://127.0.0.1/uClibc-${PV}.tar.bz2" +S = "${WORKDIR}/uClibc" + +#SRC_URI += "http://127.0.0.1/uClibc-${PV}.tar.bz2" +#S = "${WORKDIR}/git" |