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-rw-r--r--recipes/glibc/glibc_cvs.bb32
1 files changed, 16 insertions, 16 deletions
diff --git a/recipes/glibc/glibc_cvs.bb b/recipes/glibc/glibc_cvs.bb
index 22f48d29fc..1c7a785931 100644
--- a/recipes/glibc/glibc_cvs.bb
+++ b/recipes/glibc/glibc_cvs.bb
@@ -27,29 +27,29 @@ python __anonymous () {
RDEPENDS_${PN}-dev = "linux-libc-headers-dev"
RPROVIDES_${PN}-dev += "libc-dev virtual-libc-dev"
-# file://noinfo.patch;patch=1
-# file://ldconfig.patch;patch=1;pnum=0
-# file://arm-no-hwcap.patch;patch=1;pnum=0 \
-# file://arm-memcpy.patch;patch=1;pnum=0 \
-# file://arm-machine-gmon.patch;patch=1;pnum=0 \
+# file://noinfo.patch
+# file://ldconfig.patch;striplevel=0
+# file://arm-no-hwcap.patch;striplevel=0 \
+# file://arm-memcpy.patch;striplevel=0 \
+# file://arm-machine-gmon.patch;striplevel=0 \
# \
-# file://arm-ioperm.patch;patch=1;pnum=0 \
-# file://ldd.patch;patch=1;pnum=0 \
+# file://arm-ioperm.patch;striplevel=0 \
+# file://ldd.patch;striplevel=0 \
SRC_URI = "cvs://anoncvs@sources.redhat.com/cvs/glibc;module=libc \
cvs://anoncvs@sources.redhat.com/cvs/glibc;module=ports \
- file://nscd-init.patch;patch=1;pnum=0 \
- file://arm-audit.patch;patch=1 \
- file://arm-audit2.patch;patch=1 \
- file://arm-memcpy.patch;patch=1 \
- file://arm-longlong.patch;patch=1;pnum=0 \
- file://fhs-linux-paths.patch;patch=1 \
- file://dl-cache-libcmp.patch;patch=1 \
- file://ldsocache-varrun.patch;patch=1 \
+ file://nscd-init.patch;striplevel=0 \
+ file://arm-audit.patch \
+ file://arm-audit2.patch \
+ file://arm-memcpy.patch \
+ file://arm-longlong.patch;striplevel=0 \
+ file://fhs-linux-paths.patch \
+ file://dl-cache-libcmp.patch \
+ file://ldsocache-varrun.patch \
file://etc/ld.so.conf \
file://generate-supported.mk"
# seems to fail on tls platforms
-SRC_URI_append_arm = " file://dyn-ldconfig-20041128.patch;patch=1"
+SRC_URI_append_arm = " file://dyn-ldconfig-20041128.patch"
S = "${WORKDIR}/libc"
B = "${WORKDIR}/build-${TARGET_SYS}"