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-rw-r--r--recipes/llvm/llvm2.7/r104558-VFPmisc.patch58
1 files changed, 58 insertions, 0 deletions
diff --git a/recipes/llvm/llvm2.7/r104558-VFPmisc.patch b/recipes/llvm/llvm2.7/r104558-VFPmisc.patch
new file mode 100644
index 0000000000..471ff71a44
--- /dev/null
+++ b/recipes/llvm/llvm2.7/r104558-VFPmisc.patch
@@ -0,0 +1,58 @@
+--- llvm/lib/Target/ARM/ARMCodeEmitter.cpp 2010/05/25 08:42:45 104587
++++ llvm/lib/Target/ARM/ARMCodeEmitter.cpp 2010/05/25 10:23:52 104588
+@@ -1465,12 +1465,55 @@
+ }
+
+ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
++ unsigned Opcode = MI.getDesc().Opcode;
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
++ switch(Opcode) {
++ default:
++ llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
++
++ case ARM::FMSTAT:
++ // No further encoding needed.
++ break;
++
++ case ARM::VMRS:
++ case ARM::VMSR: {
++ const MachineOperand &MO0 = MI.getOperand(0);
++ // Encode Rt.
++ Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
++ << ARMII::RegRdShift;
++ break;
++ }
++
++ case ARM::FCONSTD:
++ case ARM::FCONSTS: {
++ // Encode Dd / Sd.
++ Binary |= encodeVFPRd(MI, 0);
++
++ // Encode imm., Table A7-18 VFP modified immediate constants
++ const MachineOperand &MO1 = MI.getOperand(1);
++ unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
++ .bitcastToAPInt().getHiBits(32).getLimitedValue());
++ unsigned ModifiedImm;
++
++ if(Opcode == ARM::FCONSTS)
++ ModifiedImm = (Imm & 0x80000000) >> 24 | // a
++ (Imm & 0x03F80000) >> 19; // bcdefgh
++ else // Opcode == ARM::FCONSTD
++ ModifiedImm = (Imm & 0x80000000) >> 24 | // a
++ (Imm & 0x007F0000) >> 16; // bcdefgh
++
++ // Insts{19-16} = abcd, Insts{3-0} = efgh
++ Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
++ Binary |= (ModifiedImm & 0xF);
++ break;
++ }
++ }
++
+ emitWordLE(Binary);
+ }
+