From b42902fe8ab2160cb9b01c468a7670fd88ce9238 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Fri, 24 Sep 2010 13:49:18 -0700 Subject: gcc-4.5: Import Linaro patches * Tested gcc on efikamx. Signed-off-by: Khem Raj --- recipes/gcc/gcc-4.5.inc | 90 +- .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch | 207 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch | 26644 +++++++++++++++++++ .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch | 62 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch | 3094 +++ .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch | 675 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch | 244 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch | 131 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch | 81 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch | 52 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch | 1401 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch | 138 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch | 112 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch | 36 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch | 714 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch | 37 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch | 433 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch | 57 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch | 76 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch | 118 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch | 197 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch | 138 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch | 28 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch | 53 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch | 688 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch | 109 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch | 174 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch | 86 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch | 132 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch | 68 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch | 138 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch | 95 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch | 36 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch | 111 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch | 236 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch | 43 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch | 28 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch | 76 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch | 132 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch | 30 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch | 30 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch | 170 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch | 83 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch | 37 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch | 401 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch | 184 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch | 552 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch | 121 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch | 298 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch | 384 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch | 181 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch | 376 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch | 27 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch | 38 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch | 27 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch | 1759 ++ .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch | 17586 ++++++++++++ .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99362.patch | 25 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch | 95 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch | 511 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch | 38 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch | 26 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch | 49 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch | 341 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch | 53 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch | 663 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch | 380 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch | 360 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch | 72 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch | 146 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch | 35 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch | 28 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch | 159 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch | 2011 ++ .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch | 2997 +++ .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch | 512 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch | 369 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch | 1202 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch | 151 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch | 191 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch | 43 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch | 33 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch | 45 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch | 26 + .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch | 1760 ++ .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch | 3565 +++ .../gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch | 76 + 87 files changed, 75214 insertions(+), 2 deletions(-) create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99362.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch create mode 100644 recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch diff --git a/recipes/gcc/gcc-4.5.inc b/recipes/gcc/gcc-4.5.inc index b7bd87bb3c..c5f996b4e2 100644 --- a/recipes/gcc/gcc-4.5.inc +++ b/recipes/gcc/gcc-4.5.inc @@ -8,9 +8,9 @@ DEPENDS = "mpfr gmp libmpc libelf" NATIVEDEPS = "mpfr-native gmp-native libmpc-native" -INC_PR = "r9" +INC_PR = "r10" -SRCREV = "163322" +SRCREV = "164562" PV = "4.5" # BINV should be incremented after updating to a revision # after a minor gcc release (e.g. 4.5.1 or 4.5.2) has been made @@ -31,6 +31,92 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \ file://libstdc++-emit-__cxa_end_cleanup-in-text.patch \ file://arm-bswapsi2.patch \ file://Makefile.in.patch \ + file://linaro/gcc-4.5-linaro-r99297.patch \ + file://linaro/gcc-4.5-linaro-r99298.patch \ + file://linaro/gcc-4.5-linaro-r99299.patch \ + file://linaro/gcc-4.5-linaro-r99300.patch \ + file://linaro/gcc-4.5-linaro-r99301.patch \ + file://linaro/gcc-4.5-linaro-r99302.patch \ + file://linaro/gcc-4.5-linaro-r99303.patch \ + file://linaro/gcc-4.5-linaro-r99304.patch \ + file://linaro/gcc-4.5-linaro-r99305.patch \ + file://linaro/gcc-4.5-linaro-r99306.patch \ + file://linaro/gcc-4.5-linaro-r99307.patch \ + file://linaro/gcc-4.5-linaro-r99308.patch \ + file://linaro/gcc-4.5-linaro-r99310.patch \ + file://linaro/gcc-4.5-linaro-r99312.patch \ + file://linaro/gcc-4.5-linaro-r99313.patch \ + file://linaro/gcc-4.5-linaro-r99314.patch \ + file://linaro/gcc-4.5-linaro-r99315.patch \ + file://linaro/gcc-4.5-linaro-r99316.patch \ + file://linaro/gcc-4.5-linaro-r99318.patch \ + file://linaro/gcc-4.5-linaro-r99319.patch \ + file://linaro/gcc-4.5-linaro-r99320.patch \ + file://linaro/gcc-4.5-linaro-r99321.patch \ + file://linaro/gcc-4.5-linaro-r99322.patch \ + file://linaro/gcc-4.5-linaro-r99323.patch \ + file://linaro/gcc-4.5-linaro-r99324.patch \ + file://linaro/gcc-4.5-linaro-r99325.patch \ + file://linaro/gcc-4.5-linaro-r99326.patch \ + file://linaro/gcc-4.5-linaro-r99327.patch \ + file://linaro/gcc-4.5-linaro-r99332.patch \ + file://linaro/gcc-4.5-linaro-r99335.patch \ + file://linaro/gcc-4.5-linaro-r99336.patch \ + file://linaro/gcc-4.5-linaro-r99337.patch \ + file://linaro/gcc-4.5-linaro-r99338.patch \ + file://linaro/gcc-4.5-linaro-r99339.patch \ + file://linaro/gcc-4.5-linaro-r99340.patch \ + file://linaro/gcc-4.5-linaro-r99341.patch \ + file://linaro/gcc-4.5-linaro-r99342.patch \ + file://linaro/gcc-4.5-linaro-r99343.patch \ + file://linaro/gcc-4.5-linaro-r99344.patch \ + file://linaro/gcc-4.5-linaro-r99345.patch \ + file://linaro/gcc-4.5-linaro-r99346.patch \ + file://linaro/gcc-4.5-linaro-r99347.patch \ + file://linaro/gcc-4.5-linaro-r99348.patch \ + file://linaro/gcc-4.5-linaro-r99349.patch \ + file://linaro/gcc-4.5-linaro-r99350.patch \ + file://linaro/gcc-4.5-linaro-r99351.patch \ + file://linaro/gcc-4.5-linaro-r99352.patch \ + file://linaro/gcc-4.5-linaro-r99353.patch \ + file://linaro/gcc-4.5-linaro-r99354.patch \ + file://linaro/gcc-4.5-linaro-r99355.patch \ + file://linaro/gcc-4.5-linaro-r99356.patch \ + file://linaro/gcc-4.5-linaro-r99357.patch \ + file://linaro/gcc-4.5-linaro-r99358.patch \ + file://linaro/gcc-4.5-linaro-r99359.patch \ + file://linaro/gcc-4.5-linaro-r99360.patch \ + file://linaro/gcc-4.5-linaro-r99361.patch \ + file://linaro/gcc-4.5-linaro-r99362.patch \ + file://linaro/gcc-4.5-linaro-r99363.patch \ + file://linaro/gcc-4.5-linaro-r99364.patch \ + file://linaro/gcc-4.5-linaro-r99365.patch \ + file://linaro/gcc-4.5-linaro-r99366.patch \ + file://linaro/gcc-4.5-linaro-r99367.patch \ + file://linaro/gcc-4.5-linaro-r99368.patch \ + file://linaro/gcc-4.5-linaro-r99369.patch \ + file://linaro/gcc-4.5-linaro-r99371.patch \ + file://linaro/gcc-4.5-linaro-r99372.patch \ + file://linaro/gcc-4.5-linaro-r99373.patch \ + file://linaro/gcc-4.5-linaro-r99374.patch \ + file://linaro/gcc-4.5-linaro-r99375.patch \ + file://linaro/gcc-4.5-linaro-r99376.patch \ + file://linaro/gcc-4.5-linaro-r99377.patch \ + file://linaro/gcc-4.5-linaro-r99378.patch \ + file://linaro/gcc-4.5-linaro-r99379.patch \ + file://linaro/gcc-4.5-linaro-r99380.patch \ + file://linaro/gcc-4.5-linaro-r99381.patch \ + file://linaro/gcc-4.5-linaro-r99383.patch \ + file://linaro/gcc-4.5-linaro-r99384.patch \ + file://linaro/gcc-4.5-linaro-r99385.patch \ + file://linaro/gcc-4.5-linaro-r99388.patch \ + file://linaro/gcc-4.5-linaro-r99391.patch \ + file://linaro/gcc-4.5-linaro-r99392.patch \ + file://linaro/gcc-4.5-linaro-r99393.patch \ + file://linaro/gcc-4.5-linaro-r99395.patch \ + file://linaro/gcc-4.5-linaro-r99396.patch \ + file://linaro/gcc-4.5-linaro-r99397.patch \ + file://linaro/gcc-4.5-linaro-r99398.patch \ " # Language Overrides diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch new file mode 100644 index 0000000000..bff745dae0 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch @@ -0,0 +1,207 @@ +2010-06-28 Julian Brown + + Merge from Sourcery G++ 4.4: + + Daniel Jacobowitz + Joseph Myers + + gcc/ + * doc/invoke.texi (-Wno-poison-system-directories): Document. + * gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories + if -Wno-poison-system-directories and --error-poison-system-directories + if -Werror=poison-system-directories to linker. + * incpath.c: Include flags.h. Include toplev.h. + (merge_include_chains): If ENABLE_POISON_SYSTEM_DIRECTORIES defined + and flag_poison_system_directories is true, warn for use of + /usr/include, /usr/local/include or /usr/X11R6/include. + * Makefile.in (incpath.o): Depend on $(FLAGS_H) and toplev.h. + * common.opt (--Wno-poison-system-directories): New. + * configure.ac (--enable-poison-system-directories): New option. + * configure: Regenerate. + * config.in: Regenerate. + +Index: gcc-4.5/gcc/Makefile.in +=================================================================== +--- gcc-4.5.orig/gcc/Makefile.in 2010-09-23 16:44:12.000000000 -0700 ++++ gcc-4.5/gcc/Makefile.in 2010-09-23 16:46:33.552416860 -0700 +@@ -1969,7 +1969,7 @@ gcc.srcextra: gengtype-lex.c + + incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \ + intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ +- $(MACHMODE_H) ++ $(MACHMODE_H) $(FLAGS_H) toplev.h + + c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \ + $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \ +Index: gcc-4.5/gcc/common.opt +=================================================================== +--- gcc-4.5.orig/gcc/common.opt 2010-07-11 16:14:47.000000000 -0700 ++++ gcc-4.5/gcc/common.opt 2010-09-23 16:46:33.556418045 -0700 +@@ -152,6 +152,10 @@ Wpadded + Common Var(warn_padded) Warning + Warn when padding is required to align structure members + ++Wpoison-system-directories ++Common Var(flag_poison_system_directories) Init(1) ++Warn for -I and -L options using system directories if cross compiling ++ + Wshadow + Common Var(warn_shadow) Warning + Warn when one local variable shadows another +Index: gcc-4.5/gcc/config.in +=================================================================== +--- gcc-4.5.orig/gcc/config.in 2010-07-11 16:14:46.000000000 -0700 ++++ gcc-4.5/gcc/config.in 2010-09-23 16:46:33.556418045 -0700 +@@ -132,6 +132,12 @@ + #endif + + ++/* Define to warn for use of native system header directories */ ++#ifndef USED_FOR_TARGET ++#undef ENABLE_POISON_SYSTEM_DIRECTORIES ++#endif ++ ++ + /* Define if you want all operations on RTL (the basic data structure of the + optimizer and back end) to be checked for dynamic type safety at runtime. + This is quite expensive. */ +Index: gcc-4.5/gcc/configure +=================================================================== +--- gcc-4.5.orig/gcc/configure 2010-09-23 16:44:11.000000000 -0700 ++++ gcc-4.5/gcc/configure 2010-09-23 16:46:33.572415719 -0700 +@@ -913,6 +913,7 @@ with_system_zlib + enable_maintainer_mode + enable_version_specific_runtime_libs + with_slibdir ++enable_poison_system_directories + enable_plugin + ' + ac_precious_vars='build_alias +@@ -1620,6 +1621,8 @@ Optional Features: + --enable-version-specific-runtime-libs + specify that runtime libraries should be + installed in a compiler-specific directory ++ --enable-poison-system-directories ++ warn for use of native system header directories + --enable-plugin enable plugin support + + Optional Packages: +@@ -25345,6 +25348,19 @@ fi + + + ++# Check whether --enable-poison-system-directories was given. ++if test "${enable_poison_system_directories+set}" = set; then : ++ enableval=$enable_poison_system_directories; ++else ++ enable_poison_system_directories=no ++fi ++ ++if test "x${enable_poison_system_directories}" = "xyes"; then ++ ++$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h ++ ++fi ++ + # Substitute configuration variables + + +Index: gcc-4.5/gcc/configure.ac +=================================================================== +--- gcc-4.5.orig/gcc/configure.ac 2010-09-23 16:44:11.000000000 -0700 ++++ gcc-4.5/gcc/configure.ac 2010-09-23 16:46:33.576417624 -0700 +@@ -4439,6 +4439,16 @@ else + fi) + AC_SUBST(slibdir) + ++AC_ARG_ENABLE([poison-system-directories], ++ AS_HELP_STRING([--enable-poison-system-directories], ++ [warn for use of native system header directories]),, ++ [enable_poison_system_directories=no]) ++if test "x${enable_poison_system_directories}" = "xyes"; then ++ AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES], ++ [1], ++ [Define to warn for use of native system header directories]) ++fi ++ + # Substitute configuration variables + AC_SUBST(subdirs) + AC_SUBST(srcdir) +Index: gcc-4.5/gcc/doc/invoke.texi +=================================================================== +--- gcc-4.5.orig/gcc/doc/invoke.texi 2010-09-23 15:33:28.000000000 -0700 ++++ gcc-4.5/gcc/doc/invoke.texi 2010-09-23 16:46:33.584416934 -0700 +@@ -252,6 +252,7 @@ Objective-C and Objective-C++ Dialects}. + -Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol + -Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol + -Wpointer-arith -Wno-pointer-to-int-cast @gol ++-Wno-poison-system-directories @gol + -Wredundant-decls @gol + -Wreturn-type -Wsequence-point -Wshadow @gol + -Wsign-compare -Wsign-conversion -Wstack-protector @gol +@@ -3603,6 +3604,14 @@ code. However, note that using @option{ + option will @emph{not} warn about unknown pragmas in system + headers---for that, @option{-Wunknown-pragmas} must also be used. + ++@item -Wno-poison-system-directories ++@opindex Wno-poison-system-directories ++Do not warn for @option{-I} or @option{-L} options using system ++directories such as @file{/usr/include} when cross compiling. This ++option is intended for use in chroot environments when such ++directories contain the correct headers and libraries for the target ++system rather than the host. ++ + @item -Wfloat-equal + @opindex Wfloat-equal + @opindex Wno-float-equal +Index: gcc-4.5/gcc/gcc.c +=================================================================== +--- gcc-4.5.orig/gcc/gcc.c 2010-07-11 16:14:46.000000000 -0700 ++++ gcc-4.5/gcc/gcc.c 2010-09-23 16:46:33.588417920 -0700 +@@ -792,6 +792,8 @@ proper position among the other output f + %{flto} %{fwhopr} %l " LINK_PIE_SPEC \ + "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ + %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\ ++ %{Wno-poison-system-directories:--no-poison-system-directories}\ ++ %{Werror=poison-system-directories:--error-poison-system-directories}\ + %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\ + %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\ + %{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\ +Index: gcc-4.5/gcc/incpath.c +=================================================================== +--- gcc-4.5.orig/gcc/incpath.c 2010-07-11 16:14:44.000000000 -0700 ++++ gcc-4.5/gcc/incpath.c 2010-09-23 16:46:33.588417920 -0700 +@@ -30,6 +30,8 @@ + #include "intl.h" + #include "incpath.h" + #include "cppdefault.h" ++#include "flags.h" ++#include "toplev.h" + + /* Microsoft Windows does not natively support inodes. + VMS has non-numeric inodes. */ +@@ -353,6 +355,24 @@ merge_include_chains (const char *sysroo + } + fprintf (stderr, _("End of search list.\n")); + } ++ ++#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES ++ if (flag_poison_system_directories) ++ { ++ struct cpp_dir *p; ++ ++ for (p = heads[QUOTE]; p; p = p->next) ++ { ++ if ((!strncmp (p->name, "/usr/include", 12)) ++ || (!strncmp (p->name, "/usr/local/include", 18)) ++ || (!strncmp (p->name, "/usr/X11R6/include", 18))) ++ warning (OPT_Wpoison_system_directories, ++ "include location \"%s\" is unsafe for " ++ "cross-compilation", ++ p->name); ++ } ++ } ++#endif + } + + /* Use given -I paths for #include "..." but not #include <...>, and diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch new file mode 100644 index 0000000000..1bab3e67f1 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch @@ -0,0 +1,26644 @@ +2010-07-07 Sandra Loosemore + + Backport from mainline (originally from Sourcery G++ 4.4): + + 2010-05-24 Daniel Jacobowitz + Sandra Loosemore + + gcc/ + * config/arm/neon-testgen.ml: Use dg-add-options arm_neon. + * doc/sourcebuild.texi (Effective-Target Keywords): Update arm_neon_ok + description. Add arm_neon_fp16_ok. + (Add Options): Add arm_neon and arm_neon_fp16. + + gcc/testsuite/ + * gcc.target/arm/neon/: Regenerated test cases. + + * gcc.target/arm/neon/polytypes.c, + gcc.target/arm/neon-vmla-1.c, gcc.target/arm/neon-vmls-1.c, + gcc.target/arm/neon-cond-1.c, gcc.target/arm/neon/vfp-shift-a2t2.c, + gcc.target/arm/neon-thumb2-move.c, gcc.dg/torture/arm-fp16-ops-8.c, + gcc.dg/torture/arm-fp16-ops-7.c, g++.dg/ext/arm-fp16/arm-fp16-ops-7.C, + g++.dg/ext/arm-fp16/arm-fp16-ops-8.C, g++.dg/abi/mangle-neon.C: Use + dg-add-options arm_neon. + + * gcc.target/arm/fp16-compile-vcvt.c, gcc.dg/torture/arm-fp16-ops-5.c, + gcc.dg/torture/arm-fp16-ops-6.c, g++.dg/ext/arm-fp16/arm-fp16-ops-5.C, + g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Use dg-add-options arm_neon_fp16 + and arm_neon_fp16_ok. + + * gcc.dg/vect/vect.exp, g++.dg/vect/vect.exp, + gfortran.dg/vect/vect.exp: Use add_options_for_arm_neon. + + * lib/target-supports.exp (add_options_for_arm_neon): New. + (check_effective_target_arm_neon_ok_nocache): New, from + check_effective_target_arm_neon_ok. Check multiple possibilities. + (check_effective_target_arm_neon_ok): Use + check_effective_target_arm_neon_ok_nocache. + (add_options_for_arm_neon_fp16) + (check_effective_target_arm_neon_fp16_ok) + check_effective_target_arm_neon_fp16_ok_nocache): New. + (check_effective_target_arm_neon_hw): Use add_options_for_arm_neon. + + +=== modified file 'gcc/config/arm/neon-testgen.ml' +--- old/gcc/config/arm/neon-testgen.ml 2010-01-19 14:21:14 +0000 ++++ new/gcc/config/arm/neon-testgen.ml 2010-07-29 15:38:15 +0000 +@@ -51,8 +51,8 @@ + Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n"; + Printf.fprintf chan "/* { dg-do assemble } */\n"; + Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n"; +- Printf.fprintf chan +- "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n"; ++ Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n"; ++ Printf.fprintf chan "/* { dg-add-options arm_neon } */\n"; + Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"; + Printf.fprintf chan "void test_%s (void)\n{\n" test_name + + +=== modified file 'gcc/doc/sourcebuild.texi' +--- old/gcc/doc/sourcebuild.texi 2010-04-07 19:48:12 +0000 ++++ new/gcc/doc/sourcebuild.texi 2010-07-29 15:38:15 +0000 +@@ -1497,8 +1497,14 @@ + Test system supports executing NEON instructions. + + @item arm_neon_ok +-ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp}. +-Some multilibs may be incompatible with these options. ++@anchor{arm_neon_ok} ++ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible ++options. Some multilibs may be incompatible with these options. ++ ++@item arm_neon_fp16_ok ++@anchor{arm_neon_fp16_ok} ++ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible ++options. Some multilibs may be incompatible with these options. + + @item arm_thumb1_ok + ARM target generates Thumb-1 code for @code{-mthumb}. +@@ -1863,6 +1869,16 @@ + @item mips16_attribute + @code{mips16} function attributes. + Only MIPS targets support this feature, and only then in certain modes. ++ ++@item arm_neon ++NEON support. Only ARM targets support this feature, and only then ++in certain modes; see the @ref{arm_neon_ok,,arm_neon_ok effective target ++keyword}. ++ ++@item arm_neon_fp16 ++NEON and half-precision floating point support. Only ARM targets ++support this feature, and only then in certain modes; see ++the @ref{arm_neon_ok,,arm_neon_fp16_ok effective target keyword}. + @end table + + @node Require Support + +=== modified file 'gcc/testsuite/g++.dg/abi/mangle-neon.C' +--- old/gcc/testsuite/g++.dg/abi/mangle-neon.C 2008-08-29 21:19:24 +0000 ++++ new/gcc/testsuite/g++.dg/abi/mangle-neon.C 2010-07-29 15:38:15 +0000 +@@ -2,7 +2,7 @@ + + // { dg-do compile } + // { dg-require-effective-target arm_neon_ok } +-// { dg-options "-mfpu=neon -mfloat-abi=softfp" } ++// { dg-add-options arm_neon } + + #include + + +=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C' +--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C 2010-07-29 15:38:15 +0000 +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + #include "arm-fp16-ops.h" + + +=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C' +--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C 2010-07-29 15:38:15 +0000 +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee -ffast-math" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + #include "arm-fp16-ops.h" + + +=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C' +--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C 2010-07-29 15:38:15 +0000 +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm-fp16-ops.h" + + +=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C' +--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C 2010-07-29 15:38:15 +0000 +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-mfp16-format=ieee -ffast-math" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm-fp16-ops.h" + + +=== modified file 'gcc/testsuite/g++.dg/vect/vect.exp' +--- old/gcc/testsuite/g++.dg/vect/vect.exp 2009-09-25 04:52:46 +0000 ++++ new/gcc/testsuite/g++.dg/vect/vect.exp 2010-07-29 15:38:15 +0000 +@@ -109,7 +109,7 @@ + } elseif [istarget "ia64-*-*"] { + set dg-do-what-default run + } elseif [is-effective-target arm_neon_ok] { +- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" ++ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] + if [is-effective-target arm_neon_hw] { + set dg-do-what-default run + } else { + +=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c' +--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c 2010-07-29 15:38:15 +0000 +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + #include "arm-fp16-ops.h" + + +=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c' +--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c 2010-07-29 15:38:15 +0000 +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee -ffast-math" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + #include "arm-fp16-ops.h" + + +=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c' +--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c 2010-07-29 15:38:15 +0000 +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm-fp16-ops.h" + + +=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c' +--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c 2010-07-29 15:38:15 +0000 +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-mfp16-format=ieee -ffast-math" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm-fp16-ops.h" + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp' +--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2009-09-25 17:53:06 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 15:38:15 +0000 +@@ -101,7 +101,7 @@ + } elseif [istarget "ia64-*-*"] { + set dg-do-what-default run + } elseif [is-effective-target arm_neon_ok] { +- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" ++ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] + if [is-effective-target arm_neon_hw] { + set dg-do-what-default run + } else { + +=== modified file 'gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c' +--- old/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c 2009-06-18 11:30:19 +0000 ++++ new/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c 2010-07-29 15:38:15 +0000 +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + /* Test generation of VFP __fp16 instructions. */ + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon-cond-1.c' +--- old/gcc/testsuite/gcc.target/arm/neon-cond-1.c 2009-01-27 16:14:13 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-cond-1.c 2010-07-29 15:38:15 +0000 +@@ -1,6 +1,7 @@ + /* { dg-do run } */ + /* { dg-require-effective-target arm_neon_hw } */ +-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ + /* Check that the arm_final_prescan_insn ccfsm code does not try to + * conditionally execute NEON instructions. */ + #include + +=== modified file 'gcc/testsuite/gcc.target/arm/neon-thumb2-move.c' +--- old/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c 2009-10-19 14:22:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c 2010-07-29 15:38:15 +0000 +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-O2 -mthumb -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ ++/* { dg-options "-O2 -mthumb -march=armv7-a" } */ ++/* { dg-add-options arm_neon } */ + + #include + #include + +=== modified file 'gcc/testsuite/gcc.target/arm/neon-vmla-1.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vmla-1.c 2009-05-21 15:53:48 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vmla-1.c 2010-07-29 15:38:15 +0000 +@@ -1,5 +1,6 @@ + /* { dg-require-effective-target arm_neon_hw } */ +-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ ++/* { dg-options "-O2 -ftree-vectorize" } */ ++/* { dg-add-options arm_neon } */ + /* { dg-final { scan-assembler "vmla\\.f32" } } */ + + /* Verify that VMLA is used. */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon-vmls-1.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vmls-1.c 2009-05-21 15:53:48 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vmls-1.c 2010-07-29 15:38:15 +0000 +@@ -1,5 +1,6 @@ + /* { dg-require-effective-target arm_neon_hw } */ +-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ ++/* { dg-options "-O2 -ftree-vectorize" } */ ++/* { dg-add-options arm_neon } */ + /* { dg-final { scan-assembler "vmls\\.f32" } } */ + + /* Verify that VMLS is used. */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/polytypes.c' +--- old/gcc/testsuite/gcc.target/arm/neon/polytypes.c 2009-07-30 23:17:46 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/polytypes.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,7 @@ + + /* { dg-do compile } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-add-options arm_neon } */ + + #include + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshls64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabals16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabals16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabals32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabals32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabals8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabals8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabalu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabalu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabalu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabas16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabas16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabas32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabas32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabas8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabas8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabau16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabau16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabau32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabau32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabau8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabau8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabds16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabds16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabds32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabds32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabds8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabds8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabss16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabss16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabss32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabss32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabss8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabss8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vadds16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vadds16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vadds32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vadds32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vadds64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vadds64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vadds8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vadds8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddws16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddws32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddws8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vands16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vands16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vands32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vands32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vands64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vands64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vands8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vands8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbics16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbics16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbics32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbics32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbics64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbics64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbics8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbics8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbsls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbsls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbsls64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbsls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcageQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcagef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcagef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagtf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcalef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcalef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcalef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaltf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcequ16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcequ32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcequ8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcges16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcges16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcges32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcges32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcges8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcges8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgts16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgts32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgts8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcles16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcles16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcles32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcles32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcles8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcles8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclss16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclss16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclss32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclss32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclss8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclss8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclts16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclts16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclts32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclts32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclts8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclts8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcnts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcnts8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcnts8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombinef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombinep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombinep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombines16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombines16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombines16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombines32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombines32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombines32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombines64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombines64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombines64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombines8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombines8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombines8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombineu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombineu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombineu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcombineu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreatef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreatep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreatep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreates16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreates16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreates16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreates32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreates32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreates32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreates64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreates64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreates64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreates8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreates8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreates8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreateu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreateu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreateu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcreateu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veors16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veors16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veors32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veors32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veors64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veors64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veors8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veors8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veoru16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veoru16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veoru32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veoru32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veoru64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veoru64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veoru8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veoru8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vexts16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vexts16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vexts32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vexts32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vexts64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vexts64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vexts8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vexts8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c 2009-10-14 18:18:20 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c 2010-07-29 15:38:15 +0000 +@@ -2,7 +2,8 @@ + + /* { dg-do compile } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps" } */ ++/* { dg-add-options arm_neon } */ + + #include + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c 2007-07-30 12:48:43 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c 2007-07-30 12:48:43 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c 2007-07-30 12:48:43 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_highu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c 2007-07-30 12:48:43 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c 2007-07-30 12:48:43 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c 2007-07-30 12:48:43 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c 2010-01-19 14:21:14 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhadds16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhadds32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhadds8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmins16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmins16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmins32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmins32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmins8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmins8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlals16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlals32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlals8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlas16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlas32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlas8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlau16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlau32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlau8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlss16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlss32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlss8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c 2009-11-11 14:23:03 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmullp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmullp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmullu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmullu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmullu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmuls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmuls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmuls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorru16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorru16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorru32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorru32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorru64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorru64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorru8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorru8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadals16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadals32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadals8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadds16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadds32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadds8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpminf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpminf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmins16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmins32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmins8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpminu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpminu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpminu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabss16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabss32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabss8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqadds16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqadds32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqadds64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqadds8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshls64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshls64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshls64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubls16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubls32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubls8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsublu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsublu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsublu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubs64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubu64.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu64.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubws16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubws32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubws8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrns16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrns32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrns8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtsts16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtsts32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtsts8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzps16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzps32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzps8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipf32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipf32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipp16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipp16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipp8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipp8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzips16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzips16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzips32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzips32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzips8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzips8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipu16.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu16.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipu32.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu32.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipu8.c 2007-07-25 11:28:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu8.c 2010-07-29 15:38:15 +0000 +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + + +=== modified file 'gcc/testsuite/gfortran.dg/vect/vect.exp' +--- old/gcc/testsuite/gfortran.dg/vect/vect.exp 2009-09-25 04:52:46 +0000 ++++ new/gcc/testsuite/gfortran.dg/vect/vect.exp 2010-07-29 15:38:15 +0000 +@@ -102,7 +102,7 @@ + } elseif [istarget "ia64-*-*"] { + set dg-do-what-default run + } elseif [is-effective-target arm_neon_ok] { +- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" ++ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] + if [is-effective-target arm_neon_hw] { + set dg-do-what-default run + } else { + +=== modified file 'gcc/testsuite/lib/target-supports.exp' +--- old/gcc/testsuite/lib/target-supports.exp 2010-03-24 22:51:08 +0000 ++++ new/gcc/testsuite/lib/target-supports.exp 2010-07-29 15:38:15 +0000 +@@ -1603,19 +1603,87 @@ + } + } + ++# Add the options needed for NEON. We need either -mfloat-abi=softfp ++# or -mfloat-abi=hard, but if one is already specified by the ++# multilib, use it. Similarly, if a -mfpu option already enables ++# NEON, do not add -mfpu=neon. ++ ++proc add_options_for_arm_neon { flags } { ++ if { ! [check_effective_target_arm_neon_ok] } { ++ return "$flags" ++ } ++ global et_arm_neon_flags ++ return "$flags $et_arm_neon_flags" ++} ++ + # Return 1 if this is an ARM target supporting -mfpu=neon +-# -mfloat-abi=softfp. Some multilibs may be incompatible with these +-# options. ++# -mfloat-abi=softfp or equivalent options. Some multilibs may be ++# incompatible with these options. Also set et_arm_neon_flags to the ++# best options to add. ++ ++proc check_effective_target_arm_neon_ok_nocache { } { ++ global et_arm_neon_flags ++ set et_arm_neon_flags "" ++ if { [check_effective_target_arm32] } { ++ foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} { ++ if { [check_no_compiler_messages_nocache arm_neon_ok object { ++ #include "arm_neon.h" ++ int dummy; ++ } "$flags"] } { ++ set et_arm_neon_flags $flags ++ return 1 ++ } ++ } ++ } ++ ++ return 0 ++} + + proc check_effective_target_arm_neon_ok { } { ++ return [check_cached_effective_target arm_neon_ok \ ++ check_effective_target_arm_neon_ok_nocache] ++} ++ ++# Add the options needed for NEON. We need either -mfloat-abi=softfp ++# or -mfloat-abi=hard, but if one is already specified by the ++# multilib, use it. ++ ++proc add_options_for_arm_neon_fp16 { flags } { ++ if { ! [check_effective_target_arm_neon_fp16_ok] } { ++ return "$flags" ++ } ++ global et_arm_neon_fp16_flags ++ return "$flags $et_arm_neon_fp16_flags" ++} ++ ++# Return 1 if this is an ARM target supporting -mfpu=neon-fp16 ++# -mfloat-abi=softfp or equivalent options. Some multilibs may be ++# incompatible with these options. Also set et_arm_neon_flags to the ++# best options to add. ++ ++proc check_effective_target_arm_neon_fp16_ok_nocache { } { ++ global et_arm_neon_fp16_flags ++ set et_arm_neon_fp16_flags "" + if { [check_effective_target_arm32] } { +- return [check_no_compiler_messages arm_neon_ok object { +- #include "arm_neon.h" +- int dummy; +- } "-mfpu=neon -mfloat-abi=softfp"] +- } else { +- return 0 ++ # Always add -mfpu=neon-fp16, since there is no preprocessor ++ # macro for FP16 support. ++ foreach flags {"-mfpu=neon-fp16" "-mfpu=neon-fp16 -mfloat-abi=softfp"} { ++ if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object { ++ #include "arm_neon.h" ++ int dummy; ++ } "$flags"] } { ++ set et_arm_neon_fp16_flags $flags ++ return 1 ++ } ++ } + } ++ ++ return 0 ++} ++ ++proc check_effective_target_arm_neon_fp16_ok { } { ++ return [check_cached_effective_target arm_neon_fp16_ok \ ++ check_effective_target_arm_neon_fp16_ok_nocache] + } + + # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be +@@ -1654,7 +1722,7 @@ + : "0" (a), "w" (b)); + return (a != 1); + } +- } "-mfpu=neon -mfloat-abi=softfp"] ++ } [add_options_for_arm_neon ""]] + } + + # Return 1 if this is a ARM target with NEON enabled. + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch new file mode 100644 index 0000000000..7dea4303a9 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch @@ -0,0 +1,62 @@ +2010-07-07 Sandra Loosemore + + Merge from Sourcery G++ 4.4: + + 2010-03-08 Paul Brook + + gcc/ + * doc/invoke.texi: Document ARM -mcpu=cortex-m4. + * config/arm/arm.c (all_architectures): Change v7e-m default to + cortexm4. + * config/arm/arm-cores.def: Add cortex-m4. + * config/arm/arm-tune.md: Regenerate. + +=== modified file 'gcc/config/arm/arm-cores.def' +--- old/gcc/config/arm/arm-cores.def 2009-11-20 17:37:30 +0000 ++++ new/gcc/config/arm/arm-cores.def 2010-07-29 15:53:39 +0000 +@@ -123,6 +123,7 @@ + ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e) + ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) + ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) ++ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e) + ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e) + ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e) + ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e) + +=== modified file 'gcc/config/arm/arm-tune.md' +--- old/gcc/config/arm/arm-tune.md 2009-11-20 17:37:30 +0000 ++++ new/gcc/config/arm/arm-tune.md 2010-07-29 15:53:39 +0000 +@@ -1,5 +1,5 @@ + ;; -*- buffer-read-only: t -*- + ;; Generated automatically by gentune.sh from arm-cores.def + (define_attr "tune" +- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0" ++ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" + (const (symbol_ref "((enum attr_tune) arm_tune)"))) + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-04-02 07:32:00 +0000 ++++ new/gcc/config/arm/arm.c 2010-07-29 15:53:39 +0000 +@@ -782,7 +782,7 @@ + {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, + {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, + {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, +- {"armv7e-m", cortexm3, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL}, ++ {"armv7e-m", cortexm4, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL}, + {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, + {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, + {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, + +=== modified file 'gcc/doc/invoke.texi' +--- old/gcc/doc/invoke.texi 2010-07-29 14:59:35 +0000 ++++ new/gcc/doc/invoke.texi 2010-07-29 15:53:39 +0000 +@@ -9826,7 +9826,7 @@ + @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, + @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, + @samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, +-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3}, ++@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3}, + @samp{cortex-m1}, + @samp{cortex-m0}, + @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch new file mode 100644 index 0000000000..ae417a18f5 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch @@ -0,0 +1,3094 @@ +2010-07-08 Sandra Loosemore + + Backport from upstream (originally from Sourcery G++ 4.4): + + 2010-07-02 Sandra Loosemore + + gcc/ + * config/arm/neon.md (vec_extractv2di): Correct error in register + numbering to reconcile with neon_vget_lanev2di. + + 2010-07-02 Sandra Loosemore + + gcc/ + * config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL + instead of an unspec. + (neon_expand_vector_init): Likewise. + * config/arm/neon.md (UNSPEC_VCOMBINE): Delete. + (UNSPEC_VDUP_LANE): Delete. + (UNSPEC VDUP_N): Delete. + (UNSPEC_VGET_HIGH): Delete. + (UNSPEC_VGET_LANE): Delete. + (UNSPEC_VGET_LOW): Delete. + (UNSPEC_VMVN): Delete. + (UNSPEC_VSET_LANE): Delete. + (V_double_vector_mode): New. + (vec_set_internal): Make code emitted match that for the + corresponding intrinsics. + (vec_setv2di_internal): Likewise. + (neon_vget_lanedi): Rewrite to expand into emit_move_insn. + (neon_vget_lanev2di): Rewrite to expand into vec_extractv2di. + (neon_vset_lane): Combine double and quad patterns and + expand into vec_set_internal instead of UNSPEC_VSET_LANE. + (neon_vset_lanedi): Rewrite to expand into emit_move_insn. + (neon_vdup_n): Rewrite RTL without unspec. + (neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn. + (neon_vdup_nv2di): Rewrite RTL without unspec and merge with + with neon_vdup_lanev2di, adjusting the pattern from the latter + to be predicable for consistency. + (neon_vdup_lane_internal): New. + (neon_vdup_lane): Turn into a define_expand and rewrite + to avoid using an unspec. + (neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec. + (neon_vdup_lanev2di): Turn into a define_expand. + (neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE. + (neon_vget_high): Replace with.... + (neon_vget_highv16qi): New pattern using canonical RTL. + (neon_vget_highv8hi): Likewise. + (neon_vget_highv4si): Likewise. + (neon_vget_highv4sf): Likewise. + (neon_vget_highv2di): Likewise. + (neon_vget_low): Replace with.... + (neon_vget_lowv16qi): New pattern using canonical RTL. + (neon_vget_lowv8hi): Likewise. + (neon_vget_lowv4si): Likewise. + (neon_vget_lowv4sf): Likewise. + (neon_vget_lowv2di): Likewise. + + * config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress + test for this emitting vmov. + (Vset_lane): Likewise. + (Vdup_n): Likewise. + (Vmov_n): Likewise. + + * doc/arm-neon-intrinsics.texi: Regenerated. + + gcc/testsuite/ + * gcc.target/arm/neon/vdup_ns64.c: Regenerated. + * gcc.target/arm/neon/vdup_nu64.c: Regenerated. + * gcc.target/arm/neon/vdupQ_ns64.c: Regenerated. + * gcc.target/arm/neon/vdupQ_nu64.c: Regenerated. + * gcc.target/arm/neon/vmov_ns64.c: Regenerated. + * gcc.target/arm/neon/vmov_nu64.c: Regenerated. + * gcc.target/arm/neon/vmovQ_ns64.c: Regenerated. + * gcc.target/arm/neon/vmovQ_nu64.c: Regenerated. + * gcc.target/arm/neon/vget_lanes64.c: Regenerated. + * gcc.target/arm/neon/vget_laneu64.c: Regenerated. + * gcc.target/arm/neon/vset_lanes64.c: Regenerated. + * gcc.target/arm/neon/vset_laneu64.c: Regenerated. + * gcc.target/arm/neon-vdup_ns64.c: New. + * gcc.target/arm/neon-vdup_nu64.c: New. + * gcc.target/arm/neon-vdupQ_ns64.c: New. + * gcc.target/arm/neon-vdupQ_nu64.c: New. + * gcc.target/arm/neon-vdupQ_lanes64.c: New. + * gcc.target/arm/neon-vdupQ_laneu64.c: New. + * gcc.target/arm/neon-vmov_ns64.c: New. + * gcc.target/arm/neon-vmov_nu64.c: New. + * gcc.target/arm/neon-vmovQ_ns64.c: New. + * gcc.target/arm/neon-vmovQ_nu64.c: New. + * gcc.target/arm/neon-vget_lanes64.c: New. + * gcc.target/arm/neon-vget_laneu64.c: New. + * gcc.target/arm/neon-vset_lanes64.c: New. + * gcc.target/arm/neon-vset_laneu64.c: New. + + 2010-07-02 Sandra Loosemore + Julian Brown + + gcc/ + * config/arm/neon.md (UNSPEC_VABA): Delete. + (UNSPEC_VABAL): Delete. + (UNSPEC_VABS): Delete. + (UNSPEC_VMUL_N): Delete. + (adddi3_neon): New. + (subdi3_neon): New. + (mul3add_neon): Make the pattern named. + (mul3negadd_neon): Likewise. + (neon_vadd): Replace with define_expand, and move the remaining + unspec parts... + (neon_vadd_unspec): ...to this. + (neon_vmla, neon_vmla_unspec): Likewise. + (neon_vlms, neon_vmls_unspec): Likewise. + (neon_vsub, neon_vsub_unspec): Likewise. + (neon_vaba): Rewrite in terms of vabd. + (neon_vabal): Rewrite in terms of vabdl. + (neon_vabs): Rewrite without unspec. + * config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON. + (*arm_subdi3): Likewise. + * config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add + No_op attribute to disable assembly output checks. + * config/arm/arm_neon.h: Regenerated. + * doc/arm-neon-intrinsics.texi: Regenerated. + + gcc/testsuite/ + * gcc.target/arm/neon/vadds64.c: Regenerated. + * gcc.target/arm/neon/vaddu64.c: Regenerated. + * gcc.target/arm/neon/vsubs64.c: Regenerated. + * gcc.target/arm/neon/vsubu64.c: Regenerated. + * gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options. + * gcc.target/arm/neon-vmls-1.c: Likewise. + * gcc.target/arm/neon-vsubs64.c: New execution test. + * gcc.target/arm/neon-vsubu64.c: New execution test. + * gcc.target/arm/neon-vadds64.c: New execution test. + * gcc.target/arm/neon-vaddu64.c: New execution test. + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-07-29 15:53:39 +0000 ++++ new/gcc/config/arm/arm.c 2010-07-29 15:59:12 +0000 +@@ -8110,8 +8110,7 @@ + load. */ + + x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); +- return gen_rtx_UNSPEC (mode, gen_rtvec (1, x), +- UNSPEC_VDUP_N); ++ return gen_rtx_VEC_DUPLICATE (mode, x); + } + + /* Generate code to load VALS, which is a PARALLEL containing only +@@ -8207,8 +8206,7 @@ + { + x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); + emit_insn (gen_rtx_SET (VOIDmode, target, +- gen_rtx_UNSPEC (mode, gen_rtvec (1, x), +- UNSPEC_VDUP_N))); ++ gen_rtx_VEC_DUPLICATE (mode, x))); + return; + } + +@@ -8217,7 +8215,7 @@ + if (n_var == 1) + { + rtx copy = copy_rtx (vals); +- rtvec ops; ++ rtx index = GEN_INT (one_var); + + /* Load constant part of vector, substitute neighboring value for + varying element. */ +@@ -8226,9 +8224,38 @@ + + /* Insert variable. */ + x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var)); +- ops = gen_rtvec (3, x, target, GEN_INT (one_var)); +- emit_insn (gen_rtx_SET (VOIDmode, target, +- gen_rtx_UNSPEC (mode, ops, UNSPEC_VSET_LANE))); ++ switch (mode) ++ { ++ case V8QImode: ++ emit_insn (gen_neon_vset_lanev8qi (target, x, target, index)); ++ break; ++ case V16QImode: ++ emit_insn (gen_neon_vset_lanev16qi (target, x, target, index)); ++ break; ++ case V4HImode: ++ emit_insn (gen_neon_vset_lanev4hi (target, x, target, index)); ++ break; ++ case V8HImode: ++ emit_insn (gen_neon_vset_lanev8hi (target, x, target, index)); ++ break; ++ case V2SImode: ++ emit_insn (gen_neon_vset_lanev2si (target, x, target, index)); ++ break; ++ case V4SImode: ++ emit_insn (gen_neon_vset_lanev4si (target, x, target, index)); ++ break; ++ case V2SFmode: ++ emit_insn (gen_neon_vset_lanev2sf (target, x, target, index)); ++ break; ++ case V4SFmode: ++ emit_insn (gen_neon_vset_lanev4sf (target, x, target, index)); ++ break; ++ case V2DImode: ++ emit_insn (gen_neon_vset_lanev2di (target, x, target, index)); ++ break; ++ default: ++ gcc_unreachable (); ++ } + return; + } + + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-04-02 18:54:46 +0000 ++++ new/gcc/config/arm/arm.md 2010-07-29 15:59:12 +0000 +@@ -497,9 +497,10 @@ + (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") + (match_operand:DI 2 "s_register_operand" "r, 0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON" + "#" +- "TARGET_32BIT && reload_completed" ++ "TARGET_32BIT && reload_completed ++ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))" + [(parallel [(set (reg:CC_C CC_REGNUM) + (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) + (match_dup 1))) +@@ -997,7 +998,7 @@ + (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") + (match_operand:DI 2 "s_register_operand" "r,0,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT" ++ "TARGET_32BIT && !TARGET_NEON" + "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" + [(set_attr "conds" "clob") + (set_attr "length" "8")] +@@ -1784,6 +1785,7 @@ + [(match_operand:DI 1 "s_register_operand" "") + (match_operand:DI 2 "s_register_operand" "")]))] + "TARGET_32BIT && reload_completed ++ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0]))) + && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" + [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) + (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))] +@@ -1857,11 +1859,19 @@ + }" + ) + +-(define_insn "anddi3" ++(define_expand "anddi3" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (and:DI (match_operand:DI 1 "s_register_operand" "") ++ (match_operand:DI 2 "neon_inv_logic_op2" "")))] ++ "TARGET_32BIT" ++ "" ++) ++ ++(define_insn "*anddi3_insn" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (and:DI (match_operand:DI 1 "s_register_operand" "%0,r") + (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && ! TARGET_IWMMXT" ++ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" + "#" + [(set_attr "length" "8")] + ) +@@ -2461,7 +2471,9 @@ + (match_operand:DI 2 "s_register_operand" "r,0")))] + "TARGET_32BIT" + "#" +- "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" ++ "TARGET_32BIT && reload_completed ++ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0]))) ++ && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" + [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) + (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))] + " +@@ -2585,11 +2597,19 @@ + [(set_attr "conds" "set")] + ) + +-(define_insn "iordi3" ++(define_expand "iordi3" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (ior:DI (match_operand:DI 1 "s_register_operand" "") ++ (match_operand:DI 2 "neon_logic_op2" "")))] ++ "TARGET_32BIT" ++ "" ++) ++ ++(define_insn "*iordi3_insn" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r") + (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && ! TARGET_IWMMXT" ++ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" + "#" + [(set_attr "length" "8") + (set_attr "predicable" "yes")] +@@ -2715,11 +2735,19 @@ + [(set_attr "conds" "set")] + ) + +-(define_insn "xordi3" ++(define_expand "xordi3" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (xor:DI (match_operand:DI 1 "s_register_operand" "") ++ (match_operand:DI 2 "s_register_operand" "")))] ++ "TARGET_32BIT" ++ "" ++) ++ ++(define_insn "*xordi3_insn" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r") + (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && !TARGET_IWMMXT" ++ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" + "#" + [(set_attr "length" "8") + (set_attr "predicable" "yes")] + +=== modified file 'gcc/config/arm/arm_neon.h' +--- old/gcc/config/arm/arm_neon.h 2009-11-03 17:58:59 +0000 ++++ new/gcc/config/arm/arm_neon.h 2010-07-29 15:59:12 +0000 +@@ -414,12 +414,6 @@ + return (int32x2_t)__builtin_neon_vaddv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vadd_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1); +-} +- + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vadd_f32 (float32x2_t __a, float32x2_t __b) + { +@@ -444,6 +438,12 @@ + return (uint32x2_t)__builtin_neon_vaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vadd_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vadd_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -1368,12 +1368,6 @@ + return (int32x2_t)__builtin_neon_vsubv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vsub_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1); +-} +- + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vsub_f32 (float32x2_t __a, float32x2_t __b) + { +@@ -1398,6 +1392,12 @@ + return (uint32x2_t)__builtin_neon_vsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vsub_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vsub_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -5808,12 +5808,6 @@ + return (int32x2_t)__builtin_neon_vget_lowv4si (__a); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vget_low_s64 (int64x2_t __a) +-{ +- return (int64x1_t)__builtin_neon_vget_lowv2di (__a); +-} +- + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vget_low_f32 (float32x4_t __a) + { +@@ -5838,12 +5832,6 @@ + return (uint32x2_t)__builtin_neon_vget_lowv4si ((int32x4_t) __a); + } + +-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +-vget_low_u64 (uint64x2_t __a) +-{ +- return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a); +-} +- + __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) + vget_low_p8 (poly8x16_t __a) + { +@@ -5856,6 +5844,18 @@ + return (poly16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vget_low_s64 (int64x2_t __a) ++{ ++ return (int64x1_t)__builtin_neon_vget_lowv2di (__a); ++} ++ ++__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) ++vget_low_u64 (uint64x2_t __a) ++{ ++ return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a); ++} ++ + __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) + vcvt_s32_f32 (float32x2_t __a) + { +@@ -10386,12 +10386,6 @@ + return (int32x2_t)__builtin_neon_vandv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vand_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + vand_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10410,6 +10404,12 @@ + return (uint32x2_t)__builtin_neon_vandv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vand_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vand_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -10482,12 +10482,6 @@ + return (int32x2_t)__builtin_neon_vorrv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vorr_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + vorr_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10506,6 +10500,12 @@ + return (uint32x2_t)__builtin_neon_vorrv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vorr_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vorr_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -10578,12 +10578,6 @@ + return (int32x2_t)__builtin_neon_veorv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-veor_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_veordi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + veor_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10602,6 +10596,12 @@ + return (uint32x2_t)__builtin_neon_veorv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++veor_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_veordi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + veor_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -10674,12 +10674,6 @@ + return (int32x2_t)__builtin_neon_vbicv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vbic_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + vbic_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10698,6 +10692,12 @@ + return (uint32x2_t)__builtin_neon_vbicv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vbic_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vbic_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -10770,12 +10770,6 @@ + return (int32x2_t)__builtin_neon_vornv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vorn_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + vorn_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10794,6 +10788,12 @@ + return (uint32x2_t)__builtin_neon_vornv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vorn_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vorn_u64 (uint64x1_t __a, uint64x1_t __b) + { + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2009-11-11 14:23:03 +0000 ++++ new/gcc/config/arm/neon.md 2010-07-29 15:59:12 +0000 +@@ -22,17 +22,12 @@ + (define_constants + [(UNSPEC_ASHIFT_SIGNED 65) + (UNSPEC_ASHIFT_UNSIGNED 66) +- (UNSPEC_VABA 67) +- (UNSPEC_VABAL 68) + (UNSPEC_VABD 69) + (UNSPEC_VABDL 70) +- (UNSPEC_VABS 71) + (UNSPEC_VADD 72) + (UNSPEC_VADDHN 73) + (UNSPEC_VADDL 74) + (UNSPEC_VADDW 75) +- (UNSPEC_VAND 76) +- (UNSPEC_VBIC 77) + (UNSPEC_VBSL 78) + (UNSPEC_VCAGE 79) + (UNSPEC_VCAGT 80) +@@ -40,18 +35,9 @@ + (UNSPEC_VCGE 82) + (UNSPEC_VCGT 83) + (UNSPEC_VCLS 84) +- (UNSPEC_VCLZ 85) +- (UNSPEC_VCNT 86) +- (UNSPEC_VCOMBINE 87) + (UNSPEC_VCVT 88) + (UNSPEC_VCVT_N 89) +- (UNSPEC_VDUP_LANE 90) +- (UNSPEC_VDUP_N 91) +- (UNSPEC_VEOR 92) + (UNSPEC_VEXT 93) +- (UNSPEC_VGET_HIGH 94) +- (UNSPEC_VGET_LANE 95) +- (UNSPEC_VGET_LOW 96) + (UNSPEC_VHADD 97) + (UNSPEC_VHSUB 98) + (UNSPEC_VLD1 99) +@@ -86,10 +72,6 @@ + (UNSPEC_VMULL 128) + (UNSPEC_VMUL_LANE 129) + (UNSPEC_VMULL_LANE 130) +- (UNSPEC_VMUL_N 131) +- (UNSPEC_VMVN 132) +- (UNSPEC_VORN 133) +- (UNSPEC_VORR 134) + (UNSPEC_VPADAL 135) + (UNSPEC_VPADD 136) + (UNSPEC_VPADDL 137) +@@ -125,7 +107,6 @@ + (UNSPEC_VREV64 167) + (UNSPEC_VRSQRTE 168) + (UNSPEC_VRSQRTS 169) +- (UNSPEC_VSET_LANE 170) + (UNSPEC_VSHL 171) + (UNSPEC_VSHLL_N 172) + (UNSPEC_VSHL_N 173) +@@ -335,6 +316,14 @@ + (V4HI "V2SI") (V8HI "V4SI") + (V2SI "DI") (V4SI "V2DI")]) + ++;; Double-sized modes with the same element size. ++;; Used for neon_vdup_lane, where the second operand is double-sized ++;; even when the first one is quad. ++(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") ++ (V4SI "V2SI") (V4SF "V2SF") ++ (V8QI "V8QI") (V4HI "V4HI") ++ (V2SI "V2SI") (V2SF "V2SF")]) ++ + ;; Mode of result of comparison operations (and bit-select operand 1). + (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") + (V4HI "V4HI") (V8HI "V8HI") +@@ -688,7 +677,7 @@ + elt = GET_MODE_NUNITS (mode) - 1 - elt; + operands[2] = GEN_INT (elt); + +- return "vmov%?.\t%P0[%c2], %1"; ++ return "vmov%?.\t%P0[%c2], %1"; + } + [(set_attr "predicable" "yes") + (set_attr "neon_type" "neon_mcr")]) +@@ -714,7 +703,7 @@ + operands[0] = gen_rtx_REG (mode, regno + hi); + operands[2] = GEN_INT (elt); + +- return "vmov%?.\t%P0[%c2], %1"; ++ return "vmov%?.\t%P0[%c2], %1"; + } + [(set_attr "predicable" "yes") + (set_attr "neon_type" "neon_mcr")] +@@ -734,7 +723,7 @@ + + operands[0] = gen_rtx_REG (DImode, regno); + +- return "vmov%?.64\t%P0, %Q1, %R1"; ++ return "vmov%?\t%P0, %Q1, %R1"; + } + [(set_attr "predicable" "yes") + (set_attr "neon_type" "neon_mcr_2_mcrr")] +@@ -802,11 +791,11 @@ + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] + "TARGET_NEON" + { +- int regno = REGNO (operands[1]) + INTVAL (operands[2]); ++ int regno = REGNO (operands[1]) + 2 * INTVAL (operands[2]); + + operands[1] = gen_rtx_REG (DImode, regno); + +- return "vmov%?.64\t%Q0, %R0, %P1"; ++ return "vmov%?\t%Q0, %R0, %P1 @ v2di"; + } + [(set_attr "predicable" "yes") + (set_attr "neon_type" "neon_int_1")] +@@ -823,11 +812,8 @@ + + ;; Doubleword and quadword arithmetic. + +-;; NOTE: vadd/vsub and some other instructions also support 64-bit integer +-;; element size, which we could potentially use for "long long" operations. We +-;; don't want to do this at present though, because moving values from the +-;; vector unit to the ARM core is currently slow and 64-bit addition (etc.) is +-;; easy to do with ARM instructions anyway. ++;; NOTE: some other instructions also support 64-bit integer ++;; element size, which we could potentially use for "long long" operations. + + (define_insn "*add3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") +@@ -843,6 +829,26 @@ + (const_string "neon_int_1")))] + ) + ++(define_insn "adddi3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r") ++ (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0") ++ (match_operand:DI 2 "s_register_operand" "w,r,0"))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_NEON" ++{ ++ switch (which_alternative) ++ { ++ case 0: return "vadd.i64\t%P0, %P1, %P2"; ++ case 1: return "#"; ++ case 2: return "#"; ++ default: gcc_unreachable (); ++ } ++} ++ [(set_attr "neon_type" "neon_int_1,*,*") ++ (set_attr "conds" "*,clob,clob") ++ (set_attr "length" "*,8,8")] ++) ++ + (define_insn "*sub3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") +@@ -857,6 +863,27 @@ + (const_string "neon_int_2")))] + ) + ++(define_insn "subdi3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r") ++ (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0") ++ (match_operand:DI 2 "s_register_operand" "w,r,0,0"))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_NEON" ++{ ++ switch (which_alternative) ++ { ++ case 0: return "vsub.i64\t%P0, %P1, %P2"; ++ case 1: /* fall through */ ++ case 2: /* fall through */ ++ case 3: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"; ++ default: gcc_unreachable (); ++ } ++} ++ [(set_attr "neon_type" "neon_int_2,*,*,*") ++ (set_attr "conds" "*,clob,clob,clob") ++ (set_attr "length" "*,8,8,8")] ++) ++ + (define_insn "*mul3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w") +@@ -878,7 +905,7 @@ + (const_string "neon_mul_qqq_8_16_32_ddd_32")))))] + ) + +-(define_insn "*mul3add_neon" ++(define_insn "mul3add_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") + (match_operand:VDQ 3 "s_register_operand" "w")) +@@ -900,7 +927,7 @@ + (const_string "neon_mla_qqq_32_qqd_32_scalar")))))] + ) + +-(define_insn "*mul3negadd_neon" ++(define_insn "mul3negadd_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0") + (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") +@@ -940,10 +967,9 @@ + ) + + (define_insn "iordi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0") +- (match_operand:DI 2 "neon_logic_op2" "w,Dl")] +- UNSPEC_VORR))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r") ++ (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r") ++ (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r")))] + "TARGET_NEON" + { + switch (which_alternative) +@@ -951,10 +977,13 @@ + case 0: return "vorr\t%P0, %P1, %P2"; + case 1: return neon_output_logic_immediate ("vorr", &operands[2], + DImode, 0, VALID_NEON_QREG_MODE (DImode)); ++ case 2: return "#"; ++ case 3: return "#"; + default: gcc_unreachable (); + } + } +- [(set_attr "neon_type" "neon_int_1")] ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") ++ (set_attr "length" "*,*,8,8")] + ) + + ;; The concrete forms of the Neon immediate-logic instructions are vbic and +@@ -980,10 +1009,9 @@ + ) + + (define_insn "anddi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0") +- (match_operand:DI 2 "neon_inv_logic_op2" "w,DL")] +- UNSPEC_VAND))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r") ++ (and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r") ++ (match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r")))] + "TARGET_NEON" + { + switch (which_alternative) +@@ -991,10 +1019,13 @@ + case 0: return "vand\t%P0, %P1, %P2"; + case 1: return neon_output_logic_immediate ("vand", &operands[2], + DImode, 1, VALID_NEON_QREG_MODE (DImode)); ++ case 2: return "#"; ++ case 3: return "#"; + default: gcc_unreachable (); + } + } +- [(set_attr "neon_type" "neon_int_1")] ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") ++ (set_attr "length" "*,*,8,8")] + ) + + (define_insn "orn3_neon" +@@ -1007,13 +1038,16 @@ + ) + + (define_insn "orndi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:DI 2 "s_register_operand" "w")] +- UNSPEC_VORN))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") ++ (ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0") ++ (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))] + "TARGET_NEON" +- "vorn\t%P0, %P1, %P2" +- [(set_attr "neon_type" "neon_int_1")] ++ "@ ++ vorn\t%P0, %P1, %P2 ++ # ++ #" ++ [(set_attr "neon_type" "neon_int_1,*,*") ++ (set_attr "length" "*,8,8")] + ) + + (define_insn "bic3_neon" +@@ -1025,14 +1059,18 @@ + [(set_attr "neon_type" "neon_int_1")] + ) + ++;; Compare to *anddi_notdi_di. + (define_insn "bicdi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:DI 2 "s_register_operand" "w")] +- UNSPEC_VBIC))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") ++ (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,r,0")) ++ (match_operand:DI 1 "s_register_operand" "w,0,r")))] + "TARGET_NEON" +- "vbic\t%P0, %P1, %P2" +- [(set_attr "neon_type" "neon_int_1")] ++ "@ ++ vbic\t%P0, %P1, %P2 ++ # ++ #" ++ [(set_attr "neon_type" "neon_int_1,*,*") ++ (set_attr "length" "*,8,8")] + ) + + (define_insn "xor3" +@@ -1045,13 +1083,16 @@ + ) + + (define_insn "xordi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:DI 2 "s_register_operand" "w")] +- UNSPEC_VEOR))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r") ++ (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r") ++ (match_operand:DI 2 "s_register_operand" "w,r,r")))] + "TARGET_NEON" +- "veor\t%P0, %P1, %P2" +- [(set_attr "neon_type" "neon_int_1")] ++ "@ ++ veor\t%P0, %P1, %P2 ++ # ++ #" ++ [(set_attr "neon_type" "neon_int_1,*,*") ++ (set_attr "length" "*,8,8")] + ) + + (define_insn "one_cmpl2" +@@ -1711,11 +1752,37 @@ + + ; good for plain vadd, vaddq. + +-(define_insn "neon_vadd" ++(define_expand "neon_vadd" ++ [(match_operand:VDQX 0 "s_register_operand" "=w") ++ (match_operand:VDQX 1 "s_register_operand" "w") ++ (match_operand:VDQX 2 "s_register_operand" "w") ++ (match_operand:SI 3 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ if (! || flag_unsafe_math_optimizations) ++ emit_insn (gen_add3 (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_neon_vadd_unspec (operands[0], operands[1], ++ operands[2])); ++ DONE; ++}) ++ ++; Note that NEON operations don't support the full IEEE 754 standard: in ++; particular, denormal values are flushed to zero. This means that GCC cannot ++; use those instructions for autovectorization, etc. unless ++; -funsafe-math-optimizations is in effect (in which case flush-to-zero ++; behaviour is permissible). Intrinsic operations (provided by the arm_neon.h ++; header) must work in either case: if -funsafe-math-optimizations is given, ++; intrinsics expand to "canonical" RTL where possible, otherwise intrinsics ++; expand to unspecs (which may potentially limit the extent to which they might ++; be optimized by generic code). ++ ++; Used for intrinsics when flag_unsafe_math_optimizations is false. ++ ++(define_insn "neon_vadd_unspec" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") +- (match_operand:VDQX 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] ++ (match_operand:VDQX 2 "s_register_operand" "w")] + UNSPEC_VADD))] + "TARGET_NEON" + "vadd.\t%0, %1, %2" +@@ -1788,6 +1855,8 @@ + [(set_attr "neon_type" "neon_int_4")] + ) + ++;; We cannot replace this unspec with mul3 because of the odd ++;; polynomial multiplication case that can specified by operand 3. + (define_insn "neon_vmul" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") +@@ -1811,13 +1880,31 @@ + (const_string "neon_mul_qqq_8_16_32_ddd_32")))))] + ) + +-(define_insn "neon_vmla" +- [(set (match_operand:VDQW 0 "s_register_operand" "=w") +- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:VDQW 3 "s_register_operand" "w") +- (match_operand:SI 4 "immediate_operand" "i")] +- UNSPEC_VMLA))] ++(define_expand "neon_vmla" ++ [(match_operand:VDQW 0 "s_register_operand" "=w") ++ (match_operand:VDQW 1 "s_register_operand" "0") ++ (match_operand:VDQW 2 "s_register_operand" "w") ++ (match_operand:VDQW 3 "s_register_operand" "w") ++ (match_operand:SI 4 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ if (! || flag_unsafe_math_optimizations) ++ emit_insn (gen_mul3add_neon (operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ emit_insn (gen_neon_vmla_unspec (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}) ++ ++; Used for intrinsics when flag_unsafe_math_optimizations is false. ++ ++(define_insn "neon_vmla_unspec" ++ [(set (match_operand:VDQ 0 "s_register_operand" "=w") ++ (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0") ++ (match_operand:VDQ 2 "s_register_operand" "w") ++ (match_operand:VDQ 3 "s_register_operand" "w")] ++ UNSPEC_VMLA))] + "TARGET_NEON" + "vmla.\t%0, %2, %3" + [(set (attr "neon_type") +@@ -1850,13 +1937,31 @@ + (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] + ) + +-(define_insn "neon_vmls" +- [(set (match_operand:VDQW 0 "s_register_operand" "=w") +- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:VDQW 3 "s_register_operand" "w") +- (match_operand:SI 4 "immediate_operand" "i")] +- UNSPEC_VMLS))] ++(define_expand "neon_vmls" ++ [(match_operand:VDQW 0 "s_register_operand" "=w") ++ (match_operand:VDQW 1 "s_register_operand" "0") ++ (match_operand:VDQW 2 "s_register_operand" "w") ++ (match_operand:VDQW 3 "s_register_operand" "w") ++ (match_operand:SI 4 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ if (! || flag_unsafe_math_optimizations) ++ emit_insn (gen_mul3negadd_neon (operands[0], ++ operands[1], operands[2], operands[3])); ++ else ++ emit_insn (gen_neon_vmls_unspec (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}) ++ ++; Used for intrinsics when flag_unsafe_math_optimizations is false. ++ ++(define_insn "neon_vmls_unspec" ++ [(set (match_operand:VDQ 0 "s_register_operand" "=w") ++ (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0") ++ (match_operand:VDQ 2 "s_register_operand" "w") ++ (match_operand:VDQ 3 "s_register_operand" "w")] ++ UNSPEC_VMLS))] + "TARGET_NEON" + "vmls.\t%0, %2, %3" + [(set (attr "neon_type") +@@ -1966,11 +2071,27 @@ + (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))] + ) + +-(define_insn "neon_vsub" ++(define_expand "neon_vsub" ++ [(match_operand:VDQX 0 "s_register_operand" "=w") ++ (match_operand:VDQX 1 "s_register_operand" "w") ++ (match_operand:VDQX 2 "s_register_operand" "w") ++ (match_operand:SI 3 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ if (! || flag_unsafe_math_optimizations) ++ emit_insn (gen_sub3 (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_neon_vsub_unspec (operands[0], operands[1], ++ operands[2])); ++ DONE; ++}) ++ ++; Used for intrinsics when flag_unsafe_math_optimizations is false. ++ ++(define_insn "neon_vsub_unspec" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") +- (match_operand:VDQX 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] ++ (match_operand:VDQX 2 "s_register_operand" "w")] + UNSPEC_VSUB))] + "TARGET_NEON" + "vsub.\t%0, %1, %2" +@@ -2153,11 +2274,11 @@ + + (define_insn "neon_vaba" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") +- (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "0") +- (match_operand:VDQIW 2 "s_register_operand" "w") +- (match_operand:VDQIW 3 "s_register_operand" "w") +- (match_operand:SI 4 "immediate_operand" "i")] +- UNSPEC_VABA))] ++ (plus:VDQIW (match_operand:VDQIW 1 "s_register_operand" "0") ++ (unspec:VDQIW [(match_operand:VDQIW 2 "s_register_operand" "w") ++ (match_operand:VDQIW 3 "s_register_operand" "w") ++ (match_operand:SI 4 "immediate_operand" "i")] ++ UNSPEC_VABD)))] + "TARGET_NEON" + "vaba.%T4%#\t%0, %2, %3" + [(set (attr "neon_type") +@@ -2167,11 +2288,11 @@ + + (define_insn "neon_vabal" + [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand: 1 "s_register_operand" "0") +- (match_operand:VW 2 "s_register_operand" "w") +- (match_operand:VW 3 "s_register_operand" "w") +- (match_operand:SI 4 "immediate_operand" "i")] +- UNSPEC_VABAL))] ++ (plus: (match_operand: 1 "s_register_operand" "0") ++ (unspec: [(match_operand:VW 2 "s_register_operand" "w") ++ (match_operand:VW 3 "s_register_operand" "w") ++ (match_operand:SI 4 "immediate_operand" "i")] ++ UNSPEC_VABDL)))] + "TARGET_NEON" + "vabal.%T4%#\t%q0, %P2, %P3" + [(set_attr "neon_type" "neon_vaba")] +@@ -2302,22 +2423,15 @@ + (const_string "neon_fp_vrecps_vrsqrts_qqq")))] + ) + +-(define_insn "neon_vabs" +- [(set (match_operand:VDQW 0 "s_register_operand" "=w") +- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VABS))] ++(define_expand "neon_vabs" ++ [(match_operand:VDQW 0 "s_register_operand" "") ++ (match_operand:VDQW 1 "s_register_operand" "") ++ (match_operand:SI 2 "immediate_operand" "")] + "TARGET_NEON" +- "vabs.\t%0, %1" +- [(set (attr "neon_type") +- (if_then_else (ior (ne (symbol_ref "") (const_int 0)) +- (ne (symbol_ref "") (const_int 0))) +- (if_then_else +- (ne (symbol_ref "") (const_int 0)) +- (const_string "neon_fp_vadd_ddd_vabs_dd") +- (const_string "neon_fp_vadd_qqq_vabs_qq")) +- (const_string "neon_vqneg_vqabs")))] +-) ++{ ++ emit_insn (gen_abs2 (operands[0], operands[1])); ++ DONE; ++}) + + (define_insn "neon_vqabs" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") +@@ -2359,26 +2473,42 @@ + [(set_attr "neon_type" "neon_int_1")] + ) + +-(define_insn "neon_vclz" ++(define_insn "clz2" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") +- (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VCLZ))] ++ (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vclz.\t%0, %1" + [(set_attr "neon_type" "neon_int_1")] + ) + +-(define_insn "neon_vcnt" ++(define_expand "neon_vclz" ++ [(match_operand:VDQIW 0 "s_register_operand" "") ++ (match_operand:VDQIW 1 "s_register_operand" "") ++ (match_operand:SI 2 "immediate_operand" "")] ++ "TARGET_NEON" ++{ ++ emit_insn (gen_clz2 (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_insn "popcount2" + [(set (match_operand:VE 0 "s_register_operand" "=w") +- (unspec:VE [(match_operand:VE 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VCNT))] ++ (popcount:VE (match_operand:VE 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vcnt.\t%0, %1" + [(set_attr "neon_type" "neon_int_1")] + ) + ++(define_expand "neon_vcnt" ++ [(match_operand:VE 0 "s_register_operand" "=w") ++ (match_operand:VE 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ emit_insn (gen_popcount2 (operands[0], operands[1])); ++ DONE; ++}) ++ + (define_insn "neon_vrecpe" + [(set (match_operand:V32 0 "s_register_operand" "=w") + (unspec:V32 [(match_operand:V32 1 "s_register_operand" "w") +@@ -2555,126 +2685,65 @@ + ; Operand 3 (info word) is ignored because it does nothing useful with 64-bit + ; elements. + +-(define_insn "neon_vget_lanedi" +- [(set (match_operand:DI 0 "s_register_operand" "=r") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VGET_LANE))] ++(define_expand "neon_vget_lanedi" ++ [(match_operand:DI 0 "s_register_operand" "=r") ++ (match_operand:DI 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i") ++ (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" + { + neon_lane_bounds (operands[2], 0, 1); +- return "vmov%?\t%Q0, %R0, %P1 @ di"; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) ++ emit_move_insn (operands[0], operands[1]); ++ DONE; ++}) + +-(define_insn "neon_vget_lanev2di" +- [(set (match_operand:DI 0 "s_register_operand" "=r") +- (unspec:DI [(match_operand:V2DI 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VGET_LANE))] ++(define_expand "neon_vget_lanev2di" ++ [(match_operand:DI 0 "s_register_operand" "=r") ++ (match_operand:V2DI 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i") ++ (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" + { +- rtx ops[2]; +- unsigned int regno = REGNO (operands[1]); +- unsigned int elt = INTVAL (operands[2]); +- + neon_lane_bounds (operands[2], 0, 2); +- +- ops[0] = operands[0]; +- ops[1] = gen_rtx_REG (DImode, regno + 2 * elt); +- output_asm_insn ("vmov%?\t%Q0, %R0, %P1 @ v2di", ops); +- +- return ""; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) +- +-(define_insn "neon_vset_lane" +- [(set (match_operand:VD 0 "s_register_operand" "=w") +- (unspec:VD [(match_operand: 1 "s_register_operand" "r") +- (match_operand:VD 2 "s_register_operand" "0") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VSET_LANE))] ++ emit_insn (gen_vec_extractv2di (operands[0], operands[1], operands[2])); ++ DONE; ++}) ++ ++(define_expand "neon_vset_lane" ++ [(match_operand:VDQ 0 "s_register_operand" "=w") ++ (match_operand: 1 "s_register_operand" "r") ++ (match_operand:VDQ 2 "s_register_operand" "0") ++ (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" + { ++ unsigned int elt = INTVAL (operands[3]); + neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); +- return "vmov%?.\t%P0[%c3], %1"; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) ++ ++ if (BYTES_BIG_ENDIAN) ++ { ++ unsigned int reg_nelts ++ = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (mode)); ++ elt ^= reg_nelts - 1; ++ } ++ ++ emit_insn (gen_vec_set_internal (operands[0], operands[1], ++ GEN_INT (1 << elt), operands[2])); ++ DONE; ++}) + + ; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored. + +-(define_insn "neon_vset_lanedi" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "r") +- (match_operand:DI 2 "s_register_operand" "0") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VSET_LANE))] ++(define_expand "neon_vset_lanedi" ++ [(match_operand:DI 0 "s_register_operand" "=w") ++ (match_operand:DI 1 "s_register_operand" "r") ++ (match_operand:DI 2 "s_register_operand" "0") ++ (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" + { + neon_lane_bounds (operands[3], 0, 1); +- return "vmov%?\t%P0, %Q1, %R1 @ di"; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) +- +-(define_insn "neon_vset_lane" +- [(set (match_operand:VQ 0 "s_register_operand" "=w") +- (unspec:VQ [(match_operand: 1 "s_register_operand" "r") +- (match_operand:VQ 2 "s_register_operand" "0") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VSET_LANE))] +- "TARGET_NEON" +-{ +- rtx ops[4]; +- unsigned int regno = REGNO (operands[0]); +- unsigned int halfelts = GET_MODE_NUNITS (mode) / 2; +- unsigned int elt = INTVAL (operands[3]); +- +- neon_lane_bounds (operands[3], 0, halfelts * 2); +- +- ops[0] = gen_rtx_REG (mode, regno + 2 * (elt / halfelts)); +- ops[1] = operands[1]; +- ops[2] = GEN_INT (elt % halfelts); +- output_asm_insn ("vmov%?.\t%P0[%c2], %1", ops); +- +- return ""; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) +- +-(define_insn "neon_vset_lanev2di" +- [(set (match_operand:V2DI 0 "s_register_operand" "=w") +- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r") +- (match_operand:V2DI 2 "s_register_operand" "0") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VSET_LANE))] +- "TARGET_NEON" +-{ +- rtx ops[2]; +- unsigned int regno = REGNO (operands[0]); +- unsigned int elt = INTVAL (operands[3]); +- +- neon_lane_bounds (operands[3], 0, 2); +- +- ops[0] = gen_rtx_REG (DImode, regno + 2 * elt); +- ops[1] = operands[1]; +- output_asm_insn ("vmov%?\t%P0, %Q1, %R1 @ v2di", ops); +- +- return ""; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) ++ emit_move_insn (operands[0], operands[1]); ++ DONE; ++}) + + (define_expand "neon_vcreate" + [(match_operand:VDX 0 "s_register_operand" "") +@@ -2688,8 +2757,7 @@ + + (define_insn "neon_vdup_n" + [(set (match_operand:VX 0 "s_register_operand" "=w") +- (unspec:VX [(match_operand: 1 "s_register_operand" "r")] +- UNSPEC_VDUP_N))] ++ (vec_duplicate:VX (match_operand: 1 "s_register_operand" "r")))] + "TARGET_NEON" + "vdup%?.\t%0, %1" + ;; Assume this schedules like vmov. +@@ -2699,8 +2767,7 @@ + + (define_insn "neon_vdup_n" + [(set (match_operand:V32 0 "s_register_operand" "=w,w") +- (unspec:V32 [(match_operand: 1 "s_register_operand" "r,t")] +- UNSPEC_VDUP_N))] ++ (vec_duplicate:V32 (match_operand: 1 "s_register_operand" "r,t")))] + "TARGET_NEON" + "@ + vdup%?.\t%0, %1 +@@ -2710,61 +2777,76 @@ + (set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vdup_ndi" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")] +- UNSPEC_VDUP_N))] ++(define_expand "neon_vdup_ndi" ++ [(match_operand:DI 0 "s_register_operand" "=w") ++ (match_operand:DI 1 "s_register_operand" "r")] + "TARGET_NEON" +- "vmov%?\t%P0, %Q1, %R1" +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] ++{ ++ emit_move_insn (operands[0], operands[1]); ++ DONE; ++} + ) + + (define_insn "neon_vdup_nv2di" +- [(set (match_operand:V2DI 0 "s_register_operand" "=w") +- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")] +- UNSPEC_VDUP_N))] ++ [(set (match_operand:V2DI 0 "s_register_operand" "=w,w") ++ (vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))] + "TARGET_NEON" +- "vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1" ++ "@ ++ vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1 ++ vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1" + [(set_attr "predicable" "yes") + (set_attr "length" "8") + (set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vdup_lane" +- [(set (match_operand:VD 0 "s_register_operand" "=w") +- (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VDUP_LANE))] ++(define_insn "neon_vdup_lane_internal" ++ [(set (match_operand:VDQW 0 "s_register_operand" "=w") ++ (vec_duplicate:VDQW ++ (vec_select: ++ (match_operand: 1 "s_register_operand" "w") ++ (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_NEON" + { +- neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (mode)); +- return "vdup.\t%P0, %P1[%c2]"; ++ if (BYTES_BIG_ENDIAN) ++ { ++ int elt = INTVAL (operands[2]); ++ elt = GET_MODE_NUNITS (mode) - 1 - elt; ++ operands[2] = GEN_INT (elt); ++ } ++ if () ++ return "vdup.\t%P0, %P1[%c2]"; ++ else ++ return "vdup.\t%q0, %P1[%c2]"; + } + ;; Assume this schedules like vmov. + [(set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vdup_lane" +- [(set (match_operand:VQ 0 "s_register_operand" "=w") +- (unspec:VQ [(match_operand: 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VDUP_LANE))] ++(define_expand "neon_vdup_lane" ++ [(match_operand:VDQW 0 "s_register_operand" "=w") ++ (match_operand: 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] + "TARGET_NEON" + { +- neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (mode)); +- return "vdup.\t%q0, %P1[%c2]"; +-} +- ;; Assume this schedules like vmov. +- [(set_attr "neon_type" "neon_bp_simple")] +-) ++ neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (mode)); ++ if (BYTES_BIG_ENDIAN) ++ { ++ unsigned int elt = INTVAL (operands[2]); ++ unsigned int reg_nelts ++ = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (mode)); ++ elt ^= reg_nelts - 1; ++ operands[2] = GEN_INT (elt); ++ } ++ emit_insn (gen_neon_vdup_lane_internal (operands[0], operands[1], ++ operands[2])); ++ DONE; ++}) + + ; Scalar index is ignored, since only zero is valid here. + (define_expand "neon_vdup_lanedi" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VDUP_LANE))] ++ [(match_operand:DI 0 "s_register_operand" "=w") ++ (match_operand:DI 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] + "TARGET_NEON" + { + neon_lane_bounds (operands[2], 0, 1); +@@ -2772,20 +2854,17 @@ + DONE; + }) + +-; Likewise. +-(define_insn "neon_vdup_lanev2di" +- [(set (match_operand:V2DI 0 "s_register_operand" "=w") +- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VDUP_LANE))] ++; Likewise for v2di, as the DImode second operand has only a single element. ++(define_expand "neon_vdup_lanev2di" ++ [(match_operand:V2DI 0 "s_register_operand" "=w") ++ (match_operand:DI 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] + "TARGET_NEON" + { + neon_lane_bounds (operands[2], 0, 1); +- return "vmov\t%e0, %P1\;vmov\t%f0, %P1"; +-} +- [(set_attr "length" "8") +- (set_attr "neon_type" "neon_bp_simple")] +-) ++ emit_insn (gen_neon_vdup_nv2di (operands[0], operands[1])); ++ DONE; ++}) + + ;; In this insn, operand 1 should be low, and operand 2 the high part of the + ;; dest vector. +@@ -2796,9 +2875,8 @@ + + (define_insn "neon_vcombine" + [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VDX 1 "s_register_operand" "w") +- (match_operand:VDX 2 "s_register_operand" "w")] +- UNSPEC_VCOMBINE))] ++ (vec_concat: (match_operand:VDX 1 "s_register_operand" "w") ++ (match_operand:VDX 2 "s_register_operand" "w")))] + "TARGET_NEON" + { + int dest = REGNO (operands[0]); +@@ -2838,27 +2916,171 @@ + (set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vget_high" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VQX 1 "s_register_operand" "w")] +- UNSPEC_VGET_HIGH))] +- "TARGET_NEON" +-{ +- int dest = REGNO (operands[0]); +- int src = REGNO (operands[1]); +- +- if (dest != src + 2) +- return "vmov\t%P0, %f1"; +- else +- return ""; +-} +- [(set_attr "neon_type" "neon_bp_simple")] +-) +- +-(define_insn "neon_vget_low" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VQX 1 "s_register_operand" "w")] +- UNSPEC_VGET_LOW))] ++(define_insn "neon_vget_highv16qi" ++ [(set (match_operand:V8QI 0 "s_register_operand" "=w") ++ (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w") ++ (parallel [(const_int 8) (const_int 9) ++ (const_int 10) (const_int 11) ++ (const_int 12) (const_int 13) ++ (const_int 14) (const_int 15)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_highv8hi" ++ [(set (match_operand:V4HI 0 "s_register_operand" "=w") ++ (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w") ++ (parallel [(const_int 4) (const_int 5) ++ (const_int 6) (const_int 7)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_highv4si" ++ [(set (match_operand:V2SI 0 "s_register_operand" "=w") ++ (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w") ++ (parallel [(const_int 2) (const_int 3)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_highv4sf" ++ [(set (match_operand:V2SF 0 "s_register_operand" "=w") ++ (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w") ++ (parallel [(const_int 2) (const_int 3)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_highv2di" ++ [(set (match_operand:DI 0 "s_register_operand" "=w") ++ (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w") ++ (parallel [(const_int 1)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv16qi" ++ [(set (match_operand:V8QI 0 "s_register_operand" "=w") ++ (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w") ++ (parallel [(const_int 0) (const_int 1) ++ (const_int 2) (const_int 3) ++ (const_int 4) (const_int 5) ++ (const_int 6) (const_int 7)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src) ++ return "vmov\t%P0, %e1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv8hi" ++ [(set (match_operand:V4HI 0 "s_register_operand" "=w") ++ (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w") ++ (parallel [(const_int 0) (const_int 1) ++ (const_int 2) (const_int 3)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src) ++ return "vmov\t%P0, %e1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv4si" ++ [(set (match_operand:V2SI 0 "s_register_operand" "=w") ++ (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w") ++ (parallel [(const_int 0) (const_int 1)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src) ++ return "vmov\t%P0, %e1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv4sf" ++ [(set (match_operand:V2SF 0 "s_register_operand" "=w") ++ (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w") ++ (parallel [(const_int 0) (const_int 1)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src) ++ return "vmov\t%P0, %e1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv2di" ++ [(set (match_operand:DI 0 "s_register_operand" "=w") ++ (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w") ++ (parallel [(const_int 0)])))] + "TARGET_NEON" + { + int dest = REGNO (operands[0]); + +=== modified file 'gcc/config/arm/neon.ml' +--- old/gcc/config/arm/neon.ml 2010-01-19 14:21:14 +0000 ++++ new/gcc/config/arm/neon.ml 2010-07-29 15:59:12 +0000 +@@ -709,7 +709,8 @@ + let ops = + [ + (* Addition. *) +- Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64; ++ Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32; ++ Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64]; + Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64; + Vadd, [], Long, "vaddl", elts_same_2, su_8_32; + Vadd, [], Wide, "vaddw", elts_same_2, su_8_32; +@@ -758,7 +759,8 @@ + Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32]; + + (* Subtraction. *) +- Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64; ++ Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32; ++ Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2, [S64; U64]; + Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64; + Vsub, [], Long, "vsubl", elts_same_2, su_8_32; + Vsub, [], Wide, "vsubw", elts_same_2, su_8_32; +@@ -967,7 +969,8 @@ + Use_operands [| Corereg; Dreg; Immed |], + "vget_lane", get_lane, pf_su_8_32; + Vget_lane, +- [InfoWord; ++ [No_op; ++ InfoWord; + Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]]; + Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], + Use_operands [| Corereg; Dreg; Immed |], +@@ -989,7 +992,8 @@ + Instruction_name ["vmov"]], + Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", + set_lane, pf_su_8_32; +- Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; ++ Vset_lane, [No_op; ++ Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; + Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], + Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", + set_lane_notype, [S64; U64]; +@@ -1017,7 +1021,8 @@ + Use_operands [| Dreg; Corereg |], "vdup_n", bits_1, + pf_su_8_32; + Vdup_n, +- [Instruction_name ["vmov"]; ++ [No_op; ++ Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Dreg; Corereg |], "vdup_n", notype_1, + [S64; U64]; +@@ -1028,7 +1033,8 @@ + Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1, + pf_su_8_32; + Vdup_n, +- [Instruction_name ["vmov"]; ++ [No_op; ++ Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; + Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1, +@@ -1043,7 +1049,8 @@ + Use_operands [| Dreg; Corereg |], + "vmov_n", bits_1, pf_su_8_32; + Vmov_n, +- [Builtin_name "vdup_n"; ++ [No_op; ++ Builtin_name "vdup_n"; + Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Dreg; Corereg |], +@@ -1056,7 +1063,8 @@ + Use_operands [| Qreg; Corereg |], + "vmovQ_n", bits_1, pf_su_8_32; + Vmov_n, +- [Builtin_name "vdupQ_n"; ++ [No_op; ++ Builtin_name "vdupQ_n"; + Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; + Use_operands [| Dreg; Corereg; Corereg |]]], +@@ -1613,23 +1621,28 @@ + store_3, [P16; F32; U16; U32; S16; S32]; + + (* Logical operations. And. *) +- Vand, [], All (3, Dreg), "vand", notype_2, su_8_64; ++ Vand, [], All (3, Dreg), "vand", notype_2, su_8_32; ++ Vand, [No_op], All (3, Dreg), "vand", notype_2, [S64; U64]; + Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64; + + (* Or. *) +- Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_64; ++ Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_32; ++ Vorr, [No_op], All (3, Dreg), "vorr", notype_2, [S64; U64]; + Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64; + + (* Eor. *) +- Veor, [], All (3, Dreg), "veor", notype_2, su_8_64; ++ Veor, [], All (3, Dreg), "veor", notype_2, su_8_32; ++ Veor, [No_op], All (3, Dreg), "veor", notype_2, [S64; U64]; + Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64; + + (* Bic (And-not). *) +- Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_64; ++ Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_32; ++ Vbic, [No_op], All (3, Dreg), "vbic", notype_2, [S64; U64]; + Vbic, [], All (3, Qreg), "vbicQ", notype_2, su_8_64; + + (* Or-not. *) +- Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_64; ++ Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_32; ++ Vorn, [No_op], All (3, Dreg), "vorn", notype_2, [S64; U64]; + Vorn, [], All (3, Qreg), "vornQ", notype_2, su_8_64; + ] + + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2009-07-15 09:12:22 +0000 ++++ new/gcc/config/arm/predicates.md 2010-07-29 15:59:12 +0000 +@@ -499,13 +499,15 @@ + (define_predicate "imm_for_neon_logic_operand" + (match_code "const_vector") + { +- return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL); ++ return (TARGET_NEON ++ && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); + }) + + (define_predicate "imm_for_neon_inv_logic_operand" + (match_code "const_vector") + { +- return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL); ++ return (TARGET_NEON ++ && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); + }) + + (define_predicate "neon_logic_op2" + +=== modified file 'gcc/doc/arm-neon-intrinsics.texi' +--- old/gcc/doc/arm-neon-intrinsics.texi 2009-11-18 17:06:46 +0000 ++++ new/gcc/doc/arm-neon-intrinsics.texi 2010-07-29 15:59:12 +0000 +@@ -43,20 +43,18 @@ + + + @itemize @bullet ++@item float32x2_t vadd_f32 (float32x2_t, float32x2_t) ++@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}} ++@end itemize ++ ++ ++@itemize @bullet + @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vadd_s64 (int64x1_t, int64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}} +-@end itemize +- +- +-@itemize @bullet +-@item float32x2_t vadd_f32 (float32x2_t, float32x2_t) +-@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}} + @end itemize + + +@@ -1013,20 +1011,18 @@ + + + @itemize @bullet ++@item float32x2_t vsub_f32 (float32x2_t, float32x2_t) ++@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}} ++@end itemize ++ ++ ++@itemize @bullet + @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vsub_s64 (int64x1_t, int64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}} +-@end itemize +- +- +-@itemize @bullet +-@item float32x2_t vsub_f32 (float32x2_t, float32x2_t) +-@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}} + @end itemize + + +@@ -4750,13 +4746,11 @@ + + @itemize @bullet + @item uint64_t vget_lane_u64 (uint64x1_t, const int) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} + @end itemize + + + @itemize @bullet + @item int64_t vget_lane_s64 (int64x1_t, const int) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} + @end itemize + + +@@ -4886,13 +4880,11 @@ + + @itemize @bullet + @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + +@@ -5081,13 +5073,11 @@ + + @itemize @bullet + @item uint64x1_t vdup_n_u64 (uint64_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vdup_n_s64 (int64_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + +@@ -5147,13 +5137,11 @@ + + @itemize @bullet + @item uint64x2_t vdupq_n_u64 (uint64_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + + @itemize @bullet + @item int64x2_t vdupq_n_s64 (int64_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + +@@ -5213,13 +5201,11 @@ + + @itemize @bullet + @item uint64x1_t vmov_n_u64 (uint64_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vmov_n_s64 (int64_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + +@@ -5279,13 +5265,11 @@ + + @itemize @bullet + @item uint64x2_t vmovq_n_u64 (uint64_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + + @itemize @bullet + @item int64x2_t vmovq_n_s64 (int64_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} + @end itemize + + +@@ -5572,18 +5556,6 @@ + + + @itemize @bullet +-@item uint64x1_t vget_low_u64 (uint64x2_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +-@end itemize +- +- +-@itemize @bullet +-@item int64x1_t vget_low_s64 (int64x2_t) +-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} +-@end itemize +- +- +-@itemize @bullet + @item float32x2_t vget_low_f32 (float32x4_t) + @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} + @end itemize +@@ -5601,6 +5573,16 @@ + @end itemize + + ++@itemize @bullet ++@item uint64x1_t vget_low_u64 (uint64x2_t) ++@end itemize ++ ++ ++@itemize @bullet ++@item int64x1_t vget_low_s64 (int64x2_t) ++@end itemize ++ ++ + + + @subsubsection Conversions +@@ -9727,13 +9709,11 @@ + + @itemize @bullet + @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vand_s64 (int64x1_t, int64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} + @end itemize + + +@@ -9827,13 +9807,11 @@ + + @itemize @bullet + @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vorr_s64 (int64x1_t, int64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} + @end itemize + + +@@ -9927,13 +9905,11 @@ + + @itemize @bullet + @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t) +-@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} + @end itemize + + + @itemize @bullet + @item int64x1_t veor_s64 (int64x1_t, int64x1_t) +-@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} + @end itemize + + +@@ -10027,13 +10003,11 @@ + + @itemize @bullet + @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vbic_s64 (int64x1_t, int64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} + @end itemize + + +@@ -10127,13 +10101,11 @@ + + @itemize @bullet + @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} + @end itemize + + + @itemize @bullet + @item int64x1_t vorn_s64 (int64x1_t, int64x1_t) +-@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} + @end itemize + + + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vadds64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vadds64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vadds64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vadd_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL; ++ ++ out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vaddu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vaddu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vaddu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vadd_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL; ++ ++ out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vands64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vands64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vands64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vand_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; ++ ++ out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vandu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vandu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vandu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vand_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; ++ ++ out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vbics64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vbics64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vbics64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vbic_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); ++ ++ out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vbicu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vbicu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vbicu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vbic_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); ++ ++ out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,22 @@ ++/* Test the `vdupq_lanes64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x2_t out_int64x2_t = {0, 0}; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0); ++ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) ++ abort(); ++ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,22 @@ ++/* Test the `vdupq_laneu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x2_t out_uint64x2_t = {0, 0}; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0); ++ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) ++ abort(); ++ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,22 @@ ++/* Test the `vdupq_ns64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x2_t out_int64x2_t = {0, 0}; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x2_t = vdupq_n_s64 (arg0_int64_t); ++ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) ++ abort(); ++ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,22 @@ ++/* Test the `vdupq_nu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x2_t out_uint64x2_t = {0, 0}; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); ++ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) ++ abort(); ++ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,20 @@ ++/* Test the `vdup_ns64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x1_t = vdup_n_s64 (arg0_int64_t); ++ if ((int64_t)out_int64x1_t != arg0_int64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,20 @@ ++/* Test the `vdup_nu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); ++ if ((uint64_t)out_uint64x1_t != arg0_uint64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-veors64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-veors64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-veors64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `veor_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; ++ ++ out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0x0000beef0000beefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-veoru64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-veoru64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-veoru64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `veor_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; ++ ++ out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0x0000beef0000beefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,20 @@ ++/* Test the `vget_lane_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64_t out_int64_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; ++ ++ out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); ++ if (out_int64_t != (int64_t)arg0_int64x1_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,20 @@ ++/* Test the `vget_lane_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64_t out_uint64_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; ++ ++ out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); ++ if (out_uint64_t != (uint64_t)arg0_uint64x1_t) ++ abort(); ++ return 0; ++} + +=== modified file 'gcc/testsuite/gcc.target/arm/neon-vmla-1.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vmla-1.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vmla-1.c 2010-07-29 15:59:12 +0000 +@@ -1,5 +1,5 @@ + /* { dg-require-effective-target arm_neon_hw } */ +-/* { dg-options "-O2 -ftree-vectorize" } */ ++/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + /* { dg-add-options arm_neon } */ + /* { dg-final { scan-assembler "vmla\\.f32" } } */ + + +=== modified file 'gcc/testsuite/gcc.target/arm/neon-vmls-1.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vmls-1.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vmls-1.c 2010-07-29 15:59:12 +0000 +@@ -1,5 +1,5 @@ + /* { dg-require-effective-target arm_neon_hw } */ +-/* { dg-options "-O2 -ftree-vectorize" } */ ++/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ + /* { dg-add-options arm_neon } */ + /* { dg-final { scan-assembler "vmls\\.f32" } } */ + + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,22 @@ ++/* Test the `vmovq_ns64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x2_t out_int64x2_t = {0, 0}; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x2_t = vmovq_n_s64 (arg0_int64_t); ++ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) ++ abort(); ++ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,23 @@ ++/* Test the `vmovq_nu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x2_t out_uint64x2_t = {0, 0}; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); ++ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) ++ abort(); ++ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) ++ abort(); ++ return 0; ++} ++ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,20 @@ ++/* Test the `vmov_ns64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x1_t = vmov_n_s64 (arg0_int64_t); ++ if ((int64_t)out_int64x1_t != arg0_int64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,20 @@ ++/* Test the `vmov_nu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); ++ if ((uint64_t)out_uint64x1_t != arg0_uint64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vorns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vorns64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vorns64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vorn_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); ++ ++ out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vornu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vornu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vornu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vorn_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); ++ ++ out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vorrs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vorrs64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vorrs64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vorr_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; ++ ++ out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vorru64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vorru64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vorru64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vorr_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; ++ ++ out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vset_lane_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64_t arg0_int64_t = 0xf00f00f00LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; ++ ++ out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); ++ if ((int64_t)out_int64x1_t != arg0_int64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vset_lane_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64_t arg0_uint64_t = 0xf00f00f00LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; ++ ++ out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); ++ if ((uint64_t)out_uint64x1_t != arg0_uint64_t) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vsubs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vsubs64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vsubs64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vsub_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL; ++ ++ out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL) ++ abort(); ++ return 0; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vsubu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vsubu64.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vsubu64.c 2010-07-29 15:59:12 +0000 +@@ -0,0 +1,21 @@ ++/* Test the `vsub_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL; ++ ++ out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL) ++ abort(); ++ return 0; ++} + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vadds64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vadds64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vands64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vands64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandu64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbics64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbics64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c 2010-07-29 15:59:12 +0000 +@@ -16,6 +16,4 @@ + out_int64x2_t = vdupq_n_s64 (arg0_int64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c 2010-07-29 15:59:12 +0000 +@@ -16,6 +16,4 @@ + out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c 2010-07-29 15:59:12 +0000 +@@ -16,5 +16,4 @@ + out_int64x1_t = vdup_n_s64 (arg0_int64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c 2010-07-29 15:59:12 +0000 +@@ -16,5 +16,4 @@ + out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veors64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veors64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veoru64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veoru64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c 2010-07-29 15:59:12 +0000 +@@ -16,5 +16,4 @@ + out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c 2010-07-29 15:59:12 +0000 +@@ -16,5 +16,4 @@ + out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c 2010-07-29 15:59:12 +0000 +@@ -16,6 +16,4 @@ + out_int64x2_t = vmovq_n_s64 (arg0_int64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c 2010-07-29 15:59:12 +0000 +@@ -16,6 +16,4 @@ + out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c 2010-07-29 15:59:12 +0000 +@@ -16,5 +16,4 @@ + out_int64x1_t = vmov_n_s64 (arg0_int64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c 2010-07-29 15:59:12 +0000 +@@ -16,5 +16,4 @@ + out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorns64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornu64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorru64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorru64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu64.c 2010-07-29 15:59:12 +0000 +@@ -17,5 +17,4 @@ + out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch new file mode 100644 index 0000000000..95907eeb87 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch @@ -0,0 +1,675 @@ + 2010-07-02 Daniel Jacobowitz + Julian Brown + Sandra Loosemore + + gcc/ + * config/arm/arm.c (arm_canonicalize_comparison): Canonicalize DImode + comparisons. Adjust to take both operands. + (arm_select_cc_mode): Handle DImode comparisons. + (arm_gen_compare_reg): Generate a scratch register for DImode + comparisons which require one. Use xor for Thumb equality checks. + (arm_const_double_by_immediates): New. + (arm_print_operand): Allow 'Q' and 'R' for constants. + (get_arm_condition_code): Handle new CC_CZmode and CC_NCVmode. + * config/arm/arm.h (CANONICALIZE_COMPARISON): Always use + arm_canonicalize_comparison. + * config/arm/arm-modes.def: Add CC_CZmode and CC_NCVmode. + * config/arm/arm-protos.h (arm_canonicalize_comparison): Update + prototype. + (arm_const_double_by_immediates): Declare. + * config/arm/constraints.md (Di): New constraint. + * config/arm/predicates.md (arm_immediate_di_operand) + (arm_di_operand, cmpdi_operand): New. + * config/arm/arm.md (cbranchdi4): Handle non-Cirrus also. + (*arm_cmpdi_insn, *arm_cmpdi_unsigned) + (*arm_cmpdi_zero, *thumb_cmpdi_zero): New insns. + (cstoredi4): Handle non-Cirrus also. + + gcc/testsuite/ + * gcc.c-torture/execute/20100416-1.c: New test case. + +2010-07-08 Sandra Loosemore + + Backport from upstream (originally from Sourcery G++ 4.4): + + 2010-07-02 Sandra Loosemore + + gcc/ + +=== modified file 'gcc/config/arm/arm-modes.def' +--- old/gcc/config/arm/arm-modes.def 2009-06-18 11:24:10 +0000 ++++ new/gcc/config/arm/arm-modes.def 2010-07-29 16:58:56 +0000 +@@ -35,10 +35,16 @@ + CC_NOOVmode should be used with SImode integer equalities. + CC_Zmode should be used if only the Z flag is set correctly + CC_Nmode should be used if only the N (sign) flag is set correctly ++ CC_CZmode should be used if only the C and Z flags are correct ++ (used for DImode unsigned comparisons). ++ CC_NCVmode should be used if only the N, C, and V flags are correct ++ (used for DImode signed comparisons). + CCmode should be used otherwise. */ + + CC_MODE (CC_NOOV); + CC_MODE (CC_Z); ++CC_MODE (CC_CZ); ++CC_MODE (CC_NCV); + CC_MODE (CC_SWP); + CC_MODE (CCFP); + CC_MODE (CCFPE); + +=== modified file 'gcc/config/arm/arm-protos.h' +--- old/gcc/config/arm/arm-protos.h 2009-11-11 14:23:03 +0000 ++++ new/gcc/config/arm/arm-protos.h 2010-07-29 16:58:56 +0000 +@@ -49,8 +49,7 @@ + extern int const_ok_for_arm (HOST_WIDE_INT); + extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, + HOST_WIDE_INT, rtx, rtx, int); +-extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, enum machine_mode, +- rtx *); ++extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *); + extern int legitimate_pic_operand_p (rtx); + extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx); + extern rtx legitimize_tls_address (rtx, rtx); +@@ -116,6 +115,7 @@ + extern void arm_reload_out_hi (rtx *); + extern int arm_const_double_inline_cost (rtx); + extern bool arm_const_double_by_parts (rtx); ++extern bool arm_const_double_by_immediates (rtx); + extern const char *fp_immediate_constant (rtx); + extern void arm_emit_call_insn (rtx, rtx); + extern const char *output_call (rtx *); + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-07-29 15:59:12 +0000 ++++ new/gcc/config/arm/arm.c 2010-07-29 16:58:56 +0000 +@@ -3190,13 +3190,82 @@ + immediate value easier to load. */ + + enum rtx_code +-arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, +- rtx * op1) ++arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) + { +- unsigned HOST_WIDE_INT i = INTVAL (*op1); +- unsigned HOST_WIDE_INT maxval; ++ enum machine_mode mode; ++ unsigned HOST_WIDE_INT i, maxval; ++ ++ mode = GET_MODE (*op0); ++ if (mode == VOIDmode) ++ mode = GET_MODE (*op1); ++ + maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; + ++ /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode ++ we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either ++ reversed or (for constant OP1) adjusted to GE/LT. Similarly ++ for GTU/LEU in Thumb mode. */ ++ if (mode == DImode) ++ { ++ rtx tem; ++ ++ /* To keep things simple, always use the Cirrus cfcmp64 if it is ++ available. */ ++ if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ return code; ++ ++ if (code == GT || code == LE ++ || (!TARGET_ARM && (code == GTU || code == LEU))) ++ { ++ /* Missing comparison. First try to use an available ++ comparison. */ ++ if (GET_CODE (*op1) == CONST_INT) ++ { ++ i = INTVAL (*op1); ++ switch (code) ++ { ++ case GT: ++ case LE: ++ if (i != maxval ++ && arm_const_double_by_immediates (GEN_INT (i + 1))) ++ { ++ *op1 = GEN_INT (i + 1); ++ return code == GT ? GE : LT; ++ } ++ break; ++ case GTU: ++ case LEU: ++ if (i != ~((unsigned HOST_WIDE_INT) 0) ++ && arm_const_double_by_immediates (GEN_INT (i + 1))) ++ { ++ *op1 = GEN_INT (i + 1); ++ return code == GTU ? GEU : LTU; ++ } ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ } ++ ++ /* If that did not work, reverse the condition. */ ++ tem = *op0; ++ *op0 = *op1; ++ *op1 = tem; ++ return swap_condition (code); ++ } ++ ++ return code; ++ } ++ ++ /* Comparisons smaller than DImode. Only adjust comparisons against ++ an out-of-range constant. */ ++ if (GET_CODE (*op1) != CONST_INT ++ || const_ok_for_arm (INTVAL (*op1)) ++ || const_ok_for_arm (- INTVAL (*op1))) ++ return code; ++ ++ i = INTVAL (*op1); ++ + switch (code) + { + case EQ: +@@ -9912,6 +9981,55 @@ + && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) + return CC_Cmode; + ++ if (GET_MODE (x) == DImode || GET_MODE (y) == DImode) ++ { ++ /* To keep things simple, always use the Cirrus cfcmp64 if it is ++ available. */ ++ if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ return CCmode; ++ ++ switch (op) ++ { ++ case EQ: ++ case NE: ++ /* A DImode comparison against zero can be implemented by ++ or'ing the two halves together. */ ++ if (y == const0_rtx) ++ return CC_Zmode; ++ ++ /* We can do an equality test in three Thumb instructions. */ ++ if (!TARGET_ARM) ++ return CC_Zmode; ++ ++ /* FALLTHROUGH */ ++ ++ case LTU: ++ case LEU: ++ case GTU: ++ case GEU: ++ /* DImode unsigned comparisons can be implemented by cmp + ++ cmpeq without a scratch register. Not worth doing in ++ Thumb-2. */ ++ if (TARGET_ARM) ++ return CC_CZmode; ++ ++ /* FALLTHROUGH */ ++ ++ case LT: ++ case LE: ++ case GT: ++ case GE: ++ /* DImode signed and unsigned comparisons can be implemented ++ by cmp + sbcs with a scratch register, but that does not ++ set the Z flag - we must reverse GT/LE/GTU/LEU. */ ++ gcc_assert (op != EQ && op != NE); ++ return CC_NCVmode; ++ ++ default: ++ gcc_unreachable (); ++ } ++ } ++ + return CCmode; + } + +@@ -9921,10 +10039,39 @@ + rtx + arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) + { +- enum machine_mode mode = SELECT_CC_MODE (code, x, y); +- rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); +- +- emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); ++ enum machine_mode mode; ++ rtx cc_reg; ++ int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode; ++ ++ /* We might have X as a constant, Y as a register because of the predicates ++ used for cmpdi. If so, force X to a register here. */ ++ if (dimode_comparison && !REG_P (x)) ++ x = force_reg (DImode, x); ++ ++ mode = SELECT_CC_MODE (code, x, y); ++ cc_reg = gen_rtx_REG (mode, CC_REGNUM); ++ ++ if (dimode_comparison ++ && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ && mode != CC_CZmode) ++ { ++ rtx clobber, set; ++ ++ /* To compare two non-zero values for equality, XOR them and ++ then compare against zero. Not used for ARM mode; there ++ CC_CZmode is cheaper. */ ++ if (mode == CC_Zmode && y != const0_rtx) ++ { ++ x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN); ++ y = const0_rtx; ++ } ++ /* A scratch register is required. */ ++ clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)); ++ set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)); ++ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); ++ } ++ else ++ emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); + + return cc_reg; + } +@@ -11253,6 +11400,34 @@ + return false; + } + ++/* Return true if it is possible to inline both the high and low parts ++ of a 64-bit constant into 32-bit data processing instructions. */ ++bool ++arm_const_double_by_immediates (rtx val) ++{ ++ enum machine_mode mode = GET_MODE (val); ++ rtx part; ++ ++ if (mode == VOIDmode) ++ mode = DImode; ++ ++ part = gen_highpart_mode (SImode, mode, val); ++ ++ gcc_assert (GET_CODE (part) == CONST_INT); ++ ++ if (!const_ok_for_arm (INTVAL (part))) ++ return false; ++ ++ part = gen_lowpart (SImode, val); ++ ++ gcc_assert (GET_CODE (part) == CONST_INT); ++ ++ if (!const_ok_for_arm (INTVAL (part))) ++ return false; ++ ++ return true; ++} ++ + /* Scan INSN and note any of its operands that need fixing. + If DO_PUSHES is false we do not actually push any of the fixups + needed. The function returns TRUE if any fixups were needed/pushed. +@@ -15097,8 +15272,18 @@ + the value being loaded is big-wordian or little-wordian. The + order of the two register loads can matter however, if the address + of the memory location is actually held in one of the registers +- being overwritten by the load. */ ++ being overwritten by the load. ++ ++ The 'Q' and 'R' constraints are also available for 64-bit ++ constants. */ + case 'Q': ++ if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) ++ { ++ rtx part = gen_lowpart (SImode, x); ++ fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); ++ return; ++ } ++ + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); +@@ -15109,6 +15294,18 @@ + return; + + case 'R': ++ if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) ++ { ++ enum machine_mode mode = GET_MODE (x); ++ rtx part; ++ ++ if (mode == VOIDmode) ++ mode = DImode; ++ part = gen_highpart_mode (SImode, mode, x); ++ fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); ++ return; ++ } ++ + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); +@@ -15801,6 +15998,28 @@ + default: gcc_unreachable (); + } + ++ case CC_CZmode: ++ switch (comp_code) ++ { ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case GEU: return ARM_CS; ++ case GTU: return ARM_HI; ++ case LEU: return ARM_LS; ++ case LTU: return ARM_CC; ++ default: gcc_unreachable (); ++ } ++ ++ case CC_NCVmode: ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case LT: return ARM_LT; ++ case GEU: return ARM_CS; ++ case LTU: return ARM_CC; ++ default: gcc_unreachable (); ++ } ++ + case CCmode: + switch (comp_code) + { + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2009-12-23 16:36:40 +0000 ++++ new/gcc/config/arm/arm.h 2010-07-29 16:58:56 +0000 +@@ -2253,19 +2253,7 @@ + : reverse_condition (code)) + + #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ +- do \ +- { \ +- if (GET_CODE (OP1) == CONST_INT \ +- && ! (const_ok_for_arm (INTVAL (OP1)) \ +- || (const_ok_for_arm (- INTVAL (OP1))))) \ +- { \ +- rtx const_op = OP1; \ +- CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \ +- &const_op); \ +- OP1 = const_op; \ +- } \ +- } \ +- while (0) ++ (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1)) + + /* The arm5 clz instruction returns 32. */ + #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-07-29 15:59:12 +0000 ++++ new/gcc/config/arm/arm.md 2010-07-29 16:58:56 +0000 +@@ -6718,17 +6718,45 @@ + operands[3])); DONE;" + ) + +-;; this uses the Cirrus DI compare instruction + (define_expand "cbranchdi4" + [(set (pc) (if_then_else + (match_operator 0 "arm_comparison_operator" +- [(match_operand:DI 1 "cirrus_fp_register" "") +- (match_operand:DI 2 "cirrus_fp_register" "")]) ++ [(match_operand:DI 1 "cmpdi_operand" "") ++ (match_operand:DI 2 "cmpdi_operand" "")]) + (label_ref (match_operand 3 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2], +- operands[3])); DONE;" ++ "TARGET_32BIT" ++ "{ ++ rtx swap = NULL_RTX; ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ /* We should not have two constants. */ ++ gcc_assert (GET_MODE (operands[1]) == DImode ++ || GET_MODE (operands[2]) == DImode); ++ ++ /* Flip unimplemented DImode comparisons to a form that ++ arm_gen_compare_reg can handle. */ ++ switch (code) ++ { ++ case GT: ++ swap = gen_rtx_LT (VOIDmode, operands[2], operands[1]); break; ++ case LE: ++ swap = gen_rtx_GE (VOIDmode, operands[2], operands[1]); break; ++ case GTU: ++ swap = gen_rtx_LTU (VOIDmode, operands[2], operands[1]); break; ++ case LEU: ++ swap = gen_rtx_GEU (VOIDmode, operands[2], operands[1]); break; ++ default: ++ break; ++ } ++ if (swap) ++ emit_jump_insn (gen_cbranch_cc (swap, operands[2], operands[1], ++ operands[3])); ++ else ++ emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2], ++ operands[3])); ++ DONE; ++ }" + ) + + (define_insn "*cbranchsi4_insn" +@@ -7880,6 +7908,52 @@ + (const_string "alu_shift_reg")))] + ) + ++;; DImode comparisons. The generic code generates branches that ++;; if-conversion can not reduce to a conditional compare, so we do ++;; that directly. ++ ++(define_insn "*arm_cmpdi_insn" ++ [(set (reg:CC_NCV CC_REGNUM) ++ (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r") ++ (match_operand:DI 1 "arm_di_operand" "rDi"))) ++ (clobber (match_scratch:SI 2 "=r"))] ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1" ++ [(set_attr "conds" "set") ++ (set_attr "length" "8")] ++) ++ ++(define_insn "*arm_cmpdi_unsigned" ++ [(set (reg:CC_CZ CC_REGNUM) ++ (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r") ++ (match_operand:DI 1 "arm_di_operand" "rDi")))] ++ "TARGET_ARM" ++ "cmp%?\\t%R0, %R1\;cmpeq\\t%Q0, %Q1" ++ [(set_attr "conds" "set") ++ (set_attr "length" "8")] ++) ++ ++(define_insn "*arm_cmpdi_zero" ++ [(set (reg:CC_Z CC_REGNUM) ++ (compare:CC_Z (match_operand:DI 0 "s_register_operand" "r") ++ (const_int 0))) ++ (clobber (match_scratch:SI 1 "=r"))] ++ "TARGET_32BIT" ++ "orr%.\\t%1, %Q0, %R0" ++ [(set_attr "conds" "set")] ++) ++ ++(define_insn "*thumb_cmpdi_zero" ++ [(set (reg:CC_Z CC_REGNUM) ++ (compare:CC_Z (match_operand:DI 0 "s_register_operand" "l") ++ (const_int 0))) ++ (clobber (match_scratch:SI 1 "=l"))] ++ "TARGET_THUMB1" ++ "orr\\t%1, %Q0, %R0" ++ [(set_attr "conds" "set") ++ (set_attr "length" "2")] ++) ++ + ;; Cirrus SF compare instruction + (define_insn "*cirrus_cmpsf" + [(set (reg:CCFP CC_REGNUM) +@@ -8183,18 +8257,45 @@ + operands[2], operands[3])); DONE;" + ) + +-;; this uses the Cirrus DI compare instruction + (define_expand "cstoredi4" + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand:DI 2 "cirrus_fp_register" "") +- (match_operand:DI 3 "cirrus_fp_register" "")]))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "emit_insn (gen_cstore_cc (operands[0], operands[1], +- operands[2], operands[3])); DONE;" ++ [(match_operand:DI 2 "cmpdi_operand" "") ++ (match_operand:DI 3 "cmpdi_operand" "")]))] ++ "TARGET_32BIT" ++ "{ ++ rtx swap = NULL_RTX; ++ enum rtx_code code = GET_CODE (operands[1]); ++ ++ /* We should not have two constants. */ ++ gcc_assert (GET_MODE (operands[2]) == DImode ++ || GET_MODE (operands[3]) == DImode); ++ ++ /* Flip unimplemented DImode comparisons to a form that ++ arm_gen_compare_reg can handle. */ ++ switch (code) ++ { ++ case GT: ++ swap = gen_rtx_LT (VOIDmode, operands[3], operands[2]); break; ++ case LE: ++ swap = gen_rtx_GE (VOIDmode, operands[3], operands[2]); break; ++ case GTU: ++ swap = gen_rtx_LTU (VOIDmode, operands[3], operands[2]); break; ++ case LEU: ++ swap = gen_rtx_GEU (VOIDmode, operands[3], operands[2]); break; ++ default: ++ break; ++ } ++ if (swap) ++ emit_insn (gen_cstore_cc (operands[0], swap, operands[3], ++ operands[2])); ++ else ++ emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2], ++ operands[3])); ++ DONE; ++ }" + ) + +- + (define_expand "cstoresi_eq0_thumb1" + [(parallel + [(set (match_operand:SI 0 "s_register_operand" "") + +=== modified file 'gcc/config/arm/constraints.md' +--- old/gcc/config/arm/constraints.md 2009-12-07 20:34:53 +0000 ++++ new/gcc/config/arm/constraints.md 2010-07-29 16:58:56 +0000 +@@ -29,7 +29,7 @@ + ;; in Thumb-1 state: I, J, K, L, M, N, O + + ;; The following multi-letter normal constraints have been used: +-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy ++;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di + ;; in Thumb-1 state: Pa, Pb + ;; in Thumb-2 state: Ps, Pt + +@@ -191,6 +191,13 @@ + (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4 + && !(optimize_size || arm_ld_sched)"))) + ++(define_constraint "Di" ++ "@internal ++ In ARM/Thumb-2 state a const_int or const_double where both the high ++ and low SImode words can be generated as immediates in 32-bit instructions." ++ (and (match_code "const_double,const_int") ++ (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)"))) ++ + (define_constraint "Dn" + "@internal + In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2010-07-29 15:59:12 +0000 ++++ new/gcc/config/arm/predicates.md 2010-07-29 16:58:56 +0000 +@@ -86,6 +86,12 @@ + (and (match_code "const_int") + (match_test "const_ok_for_arm (INTVAL (op))"))) + ++;; A constant value which fits into two instructions, each taking ++;; an arithmetic constant operand for one of the words. ++(define_predicate "arm_immediate_di_operand" ++ (and (match_code "const_int,const_double") ++ (match_test "arm_const_double_by_immediates (op)"))) ++ + (define_predicate "arm_neg_immediate_operand" + (and (match_code "const_int") + (match_test "const_ok_for_arm (-INTVAL (op))"))) +@@ -115,6 +121,10 @@ + (ior (match_operand 0 "arm_rhs_operand") + (match_operand 0 "arm_not_immediate_operand"))) + ++(define_predicate "arm_di_operand" ++ (ior (match_operand 0 "s_register_operand") ++ (match_operand 0 "arm_immediate_di_operand"))) ++ + ;; True if the operand is a memory reference which contains an + ;; offsettable address. + (define_predicate "offsettable_memory_operand" +@@ -522,4 +532,12 @@ + (define_predicate "neon_lane_number" + (and (match_code "const_int") + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) ++;; Predicates for named expanders that overlap multiple ISAs. ++ ++(define_predicate "cmpdi_operand" ++ (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK") ++ (and (match_test "TARGET_ARM") ++ (match_operand 0 "cirrus_fp_register")) ++ (and (match_test "TARGET_32BIT") ++ (match_operand 0 "arm_di_operand")))) + + +=== added file 'gcc/testsuite/gcc.c-torture/execute/20100416-1.c' +--- old/gcc/testsuite/gcc.c-torture/execute/20100416-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.c-torture/execute/20100416-1.c 2010-07-29 16:58:56 +0000 +@@ -0,0 +1,40 @@ ++void abort(void); ++ ++int ++movegt(int x, int y, long long a) ++{ ++ int i; ++ int ret = 0; ++ for (i = 0; i < y; i++) ++ { ++ if (a >= (long long) 0xf000000000000000LL) ++ ret = x; ++ else ++ ret = y; ++ } ++ return ret; ++} ++ ++struct test ++{ ++ long long val; ++ int ret; ++} tests[] = { ++ { 0xf000000000000000LL, -1 }, ++ { 0xefffffffffffffffLL, 1 }, ++ { 0xf000000000000001LL, -1 }, ++ { 0x0000000000000000LL, -1 }, ++ { 0x8000000000000000LL, 1 }, ++}; ++ ++int ++main() ++{ ++ int i; ++ for (i = 0; i < sizeof (tests) / sizeof (tests[0]); i++) ++ { ++ if (movegt (-1, 1, tests[i].val) != tests[i].ret) ++ abort (); ++ } ++ return 0; ++} + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch new file mode 100644 index 0000000000..635d3f8bd5 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch @@ -0,0 +1,244 @@ +2010-07-09 Sandra Loosemore + + Backport from mainline (originally on Sourcery G++ 4.4): + + 2010-07-02 Julian Brown + Sandra Loosemore + + PR target/43703 + + gcc/ + * config/arm/vec-common.md (add3, sub3, smin3) + (smax3): Disable for NEON float modes when + flag_unsafe_math_optimizations is false. + * config/arm/neon.md (*add3_neon, *sub3_neon) + (*mul3_neon) + (mul3add_neon, mul3negadd_neon) + (reduc_splus_, reduc_smin_, reduc_smax_): Disable + for NEON float modes when flag_unsafe_math_optimizations is false. + (quad_halves_v4sf): Only enable if flag_unsafe_math_optimizations + is true. + * doc/invoke.texi (ARM Options): Add note about floating point + vectorization requiring -funsafe-math-optimizations. + + gcc/testsuite/ + * gcc.dg/vect/vect.exp: Add -ffast-math for NEON. + * gcc.dg/vect/vect-reduc-6.c: Add XFAIL for NEON. + + 2010-07-08 Sandra Loosemore + + Backport from upstream (originally from Sourcery G++ 4.4): + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2010-07-29 15:59:12 +0000 ++++ new/gcc/config/arm/neon.md 2010-07-29 17:03:20 +0000 +@@ -819,7 +819,7 @@ + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vadd.\t%0, %1, %2" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -853,7 +853,7 @@ + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vsub.\t%0, %1, %2" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -888,7 +888,7 @@ + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vmul.\t%0, %1, %2" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -910,7 +910,7 @@ + (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") + (match_operand:VDQ 3 "s_register_operand" "w")) + (match_operand:VDQ 1 "s_register_operand" "0")))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vmla.\t%0, %2, %3" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -932,7 +932,7 @@ + (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0") + (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") + (match_operand:VDQ 3 "s_register_operand" "w"))))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vmls.\t%0, %2, %3" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -1361,7 +1361,7 @@ + (parallel [(const_int 0) (const_int 1)])) + (vec_select:V2SF (match_dup 1) + (parallel [(const_int 2) (const_int 3)]))))] +- "TARGET_NEON" ++ "TARGET_NEON && flag_unsafe_math_optimizations" + ".f32\t%P0, %e1, %f1" + [(set_attr "vqh_mnem" "") + (set (attr "neon_type") +@@ -1496,7 +1496,7 @@ + (define_expand "reduc_splus_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpadd_internal); +@@ -1506,7 +1506,7 @@ + (define_expand "reduc_splus_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); +@@ -1541,7 +1541,7 @@ + (define_expand "reduc_smin_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpsmin); +@@ -1551,7 +1551,7 @@ + (define_expand "reduc_smin_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); +@@ -1566,7 +1566,7 @@ + (define_expand "reduc_smax_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpsmax); +@@ -1576,7 +1576,7 @@ + (define_expand "reduc_smax_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); + +=== modified file 'gcc/config/arm/vec-common.md' +--- old/gcc/config/arm/vec-common.md 2009-11-11 14:23:03 +0000 ++++ new/gcc/config/arm/vec-common.md 2010-07-29 17:03:20 +0000 +@@ -57,7 +57,8 @@ + [(set (match_operand:VALL 0 "s_register_operand" "") + (plus:VALL (match_operand:VALL 1 "s_register_operand" "") + (match_operand:VALL 2 "s_register_operand" "")))] +- "TARGET_NEON ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" + { + }) +@@ -66,7 +67,8 @@ + [(set (match_operand:VALL 0 "s_register_operand" "") + (minus:VALL (match_operand:VALL 1 "s_register_operand" "") + (match_operand:VALL 2 "s_register_operand" "")))] +- "TARGET_NEON ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" + { + }) +@@ -75,7 +77,9 @@ + [(set (match_operand:VALLW 0 "s_register_operand" "") + (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] +- "TARGET_NEON || (mode == V4HImode && TARGET_REALLY_IWMMXT)" ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) ++ || (mode == V4HImode && TARGET_REALLY_IWMMXT)" + { + }) + +@@ -83,7 +87,8 @@ + [(set (match_operand:VALLW 0 "s_register_operand" "") + (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] +- "TARGET_NEON ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" + { + }) +@@ -101,7 +106,8 @@ + [(set (match_operand:VALLW 0 "s_register_operand" "") + (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] +- "TARGET_NEON ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" + { + }) + +=== modified file 'gcc/doc/invoke.texi' +--- old/gcc/doc/invoke.texi 2010-07-29 15:53:39 +0000 ++++ new/gcc/doc/invoke.texi 2010-07-29 17:03:20 +0000 +@@ -9874,6 +9874,14 @@ + If @option{-msoft-float} is specified this specifies the format of + floating point values. + ++If the selected floating-point hardware includes the NEON extension ++(e.g. @option{-mfpu}=@samp{neon}), note that floating-point ++operations will not be used by GCC's auto-vectorization pass unless ++@option{-funsafe-math-optimizations} is also specified. This is ++because NEON hardware does not fully implement the IEEE 754 standard for ++floating-point arithmetic (in particular denormal values are treated as ++zero), so the use of NEON instructions may lead to a loss of precision. ++ + @item -mfp16-format=@var{name} + @opindex mfp16-format + Specify the format of the @code{__fp16} half-precision floating-point type. + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-reduc-6.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c 2010-07-29 17:03:20 +0000 +@@ -49,5 +49,6 @@ + } + + /* need -ffast-math to vectorizer these loops. */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */ ++/* ARM NEON passes -ffast-math to these tests, so expect this to fail. */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail arm_neon_ok } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp' +--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 17:03:20 +0000 +@@ -102,6 +102,10 @@ + set dg-do-what-default run + } elseif [is-effective-target arm_neon_ok] { + eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] ++ # NEON does not support denormals, so is not used for vectorization by ++ # default to avoid loss of precision. We must pass -ffast-math to test ++ # vectorization of float operations. ++ lappend DEFAULT_VECTCFLAGS "-ffast-math" + if [is-effective-target arm_neon_hw] { + set dg-do-what-default run + } else { + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch new file mode 100644 index 0000000000..53d1d08d52 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch @@ -0,0 +1,131 @@ + Merge from Sourcery G++ 4.4: + + 2009-05-21 Sandra Loosemore + + Merge from Sourcery G++ 4.3: + + 2009-04-04 Sandra Loosemore + + Issue #5104 + PR tree-optimization/39604 + + gcc/testsuite + * g++.dg/tree-ssa/sink-1.C: New. + + gcc/ + * tree_ssa-sink.c (sink_code_in_bb): Do not sink statements out + of a lexical block containing variable definitions. + +2010-07-09 Sandra Loosemore + + Backport from mainline (originally on Sourcery G++ 4.4): + + 2010-07-02 Julian Brown + +=== added file 'gcc/testsuite/g++.dg/tree-ssa/sink-1.C' +--- old/gcc/testsuite/g++.dg/tree-ssa/sink-1.C 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/g++.dg/tree-ssa/sink-1.C 2010-07-30 12:14:18 +0000 +@@ -0,0 +1,50 @@ ++/* { dg-do run } */ ++/* { dg-options "-O1" } */ ++ ++class A { ++ public: ++ A() {} ++ virtual ~A() {} ++ void * dostuff(); ++ ++ virtual int dovirtual() = 0; ++}; ++ ++ ++class B : public A { ++ public: ++ B() {} ++ int dovirtual() { return 0;} ++ virtual ~B() {}; ++}; ++ ++class C : public B { ++ public: ++ C() {} ++ virtual ~C() {}; ++}; ++ ++void* A::dostuff() ++{ ++ return (void*)dovirtual(); ++} ++ ++/* tree-ssa-sink was sinking the inlined destructor for STUFF out of ++ the first inner block and into the second one, where it was ending up ++ after the inlined constructor for STUFF2. This is bad because ++ cfgexpand aliases STUFF and STUFF2 to the same storage at -O1 ++ (i.e., without -fstrict-aliasing), with the result that STUFF2's ++ vtable was getting trashed. */ ++ ++int main() { ++ { ++ B stuff; ++ stuff.dostuff(); ++ } ++ { ++ C stuff2; ++ stuff2.dostuff(); ++ } ++ return 0; ++} ++ + +=== modified file 'gcc/tree-ssa-sink.c' +--- old/gcc/tree-ssa-sink.c 2009-11-28 16:21:00 +0000 ++++ new/gcc/tree-ssa-sink.c 2010-07-30 12:14:18 +0000 +@@ -470,6 +470,47 @@ + last = false; + continue; + } ++ ++ /* We cannot move statements that contain references to block-scope ++ variables out of that block, as this may lead to incorrect aliasing ++ when we lay out the stack frame in cfgexpand.c. ++ In lieu of more sophisticated analysis, be very conservative here ++ and prohibit moving any statement that references memory out of a ++ block with variables. */ ++ if (gimple_references_memory_p (stmt)) ++ { ++ tree fromblock = gimple_block (stmt); ++ while (fromblock ++ && fromblock != current_function_decl ++ && !BLOCK_VARS (fromblock)) ++ fromblock = BLOCK_SUPERCONTEXT (fromblock); ++ if (fromblock && fromblock != current_function_decl) ++ { ++ gimple tostmt; ++ tree toblock; ++ ++ if (gsi_end_p (togsi)) ++ tostmt = gimple_seq_last_stmt (gsi_seq (togsi)); ++ else ++ tostmt = gsi_stmt (togsi); ++ if (tostmt) ++ toblock = gimple_block (tostmt); ++ else ++ toblock = NULL; ++ while (toblock ++ && toblock != current_function_decl ++ && toblock != fromblock) ++ toblock = BLOCK_SUPERCONTEXT (toblock); ++ if (!toblock || toblock != fromblock) ++ { ++ if (!gsi_end_p (gsi)) ++ gsi_prev (&gsi); ++ last = false; ++ continue; ++ } ++ } ++ } ++ + if (dump_file) + { + fprintf (dump_file, "Sinking "); + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch new file mode 100644 index 0000000000..ab1296347b --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch @@ -0,0 +1,81 @@ +2010-07-10 Yao Qi + + Merge from Sourcery G++ 4.4: + + 2009-05-28 Julian Brown + + Merged from Sourcery G++ 4.3: + + libgcc/ + * config.host (arm*-*-linux*, arm*-*-uclinux*, arm*-*-eabi*) + (arm*-*-symbianelf): Add arm/t-divmod-ef to tmake_file. + * Makefile.in (LIB2_DIVMOD_EXCEPTION_FLAGS): Set to previous + default if not set by a target-specific Makefile fragment. + (lib2-divmod-o, lib2-divmod-s-o): Use above. + * config/arm/t-divmod-ef: New. + + 2010-07-09 Sandra Loosemore + + Merge from Sourcery G++ 4.4: + +=== modified file 'libgcc/Makefile.in' +--- old/libgcc/Makefile.in 2010-03-30 12:08:52 +0000 ++++ new/libgcc/Makefile.in 2010-07-30 12:21:02 +0000 +@@ -400,18 +400,24 @@ + endif + endif + ++ifeq ($(LIB2_DIVMOD_EXCEPTION_FLAGS),) ++# Provide default flags for compiling divmod functions, if they haven't been ++# set already by a target-specific Makefile fragment. ++LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions -fnon-call-exceptions ++endif ++ + # Build LIB2_DIVMOD_FUNCS. + lib2-divmod-o = $(patsubst %,%$(objext),$(LIB2_DIVMOD_FUNCS)) + $(lib2-divmod-o): %$(objext): $(gcc_srcdir)/libgcc2.c + $(gcc_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \ +- -fexceptions -fnon-call-exceptions $(vis_hide) ++ $(LIB2_DIVMOD_EXCEPTION_FLAGS) $(vis_hide) + libgcc-objects += $(lib2-divmod-o) + + ifeq ($(enable_shared),yes) + lib2-divmod-s-o = $(patsubst %,%_s$(objext),$(LIB2_DIVMOD_FUNCS)) + $(lib2-divmod-s-o): %_s$(objext): $(gcc_srcdir)/libgcc2.c + $(gcc_s_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \ +- -fexceptions -fnon-call-exceptions ++ $(LIB2_DIVMOD_EXCEPTION_FLAGS) + libgcc-s-objects += $(lib2-divmod-s-o) + endif + + +=== modified file 'libgcc/config.host' +--- old/libgcc/config.host 2010-04-02 02:02:18 +0000 ++++ new/libgcc/config.host 2010-07-30 12:21:02 +0000 +@@ -208,12 +208,15 @@ + arm*-*-netbsd*) + ;; + arm*-*-linux*) # ARM GNU/Linux with ELF ++ tmake_file="${tmake_file} arm/t-divmod-ef" + ;; + arm*-*-uclinux*) # ARM ucLinux ++ tmake_file="${tmake_file} arm/t-divmod-ef" + ;; + arm*-*-ecos-elf) + ;; + arm*-*-eabi* | arm*-*-symbianelf* ) ++ tmake_file="${tmake_file} arm/t-divmod-ef" + ;; + arm*-*-rtems*) + ;; + +=== added directory 'libgcc/config/arm' +=== added file 'libgcc/config/arm/t-divmod-ef' +--- old/libgcc/config/arm/t-divmod-ef 1970-01-01 00:00:00 +0000 ++++ new/libgcc/config/arm/t-divmod-ef 2010-07-30 12:21:02 +0000 +@@ -0,0 +1,4 @@ ++# On ARM, specifying -fnon-call-exceptions will needlessly pull in ++# the unwinder in simple programs which use 64-bit division. Omitting ++# the option is safe. ++LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch new file mode 100644 index 0000000000..ed25334dfb --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch @@ -0,0 +1,52 @@ + 2009-09-02 Daniel Jacobowitz + + libgcc/ + * shared-object.mk (c_flags-$(base)$(objext)): New. + ($(base)$(objext)): Use above. + ($(base)_s$(objext)): Likewise. + * static-object.mk (c_flags-$(base)$(objext)): New. + ($(base)$(objext)): Use above. + +2010-07-10 Yao Qi + + Merge from Sourcery G++ 4.4: + + 2009-05-28 Julian Brown + + Merged from Sourcery G++ 4.3: + +=== modified file 'libgcc/shared-object.mk' +--- old/libgcc/shared-object.mk 2008-07-03 18:22:00 +0000 ++++ new/libgcc/shared-object.mk 2010-07-30 13:11:02 +0000 +@@ -8,11 +8,13 @@ + + ifeq ($(suffix $o),.c) + ++c_flags-$(base)$(objext) := $(c_flags) + $(base)$(objext): $o +- $(gcc_compile) $(c_flags) -c $< $(vis_hide) ++ $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide) + ++c_flags-$(base)_s$(objext) := $(c_flags) + $(base)_s$(objext): $o +- $(gcc_s_compile) $(c_flags) -c $< ++ $(gcc_s_compile) $(c_flags-$@) -c $< + + else + + +=== modified file 'libgcc/static-object.mk' +--- old/libgcc/static-object.mk 2007-01-04 04:22:37 +0000 ++++ new/libgcc/static-object.mk 2010-07-30 13:11:02 +0000 +@@ -8,8 +8,9 @@ + + ifeq ($(suffix $o),.c) + ++c_flags-$(base)$(objext) := $(c_flags) + $(base)$(objext): $o +- $(gcc_compile) $(c_flags) -c $< $(vis_hide) ++ $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide) + + else + + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch new file mode 100644 index 0000000000..423cd56528 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch @@ -0,0 +1,1401 @@ +2010-07-10 Sandra Loosemore + + Backport from mainline: + + 2010-05-08 Sandra Loosemore + + PR middle-end/28685 + + gcc/ + * tree-ssa-reassoc.c (eliminate_redundant_comparison): New function. + (optimize_ops_list): Call it. + + gcc/testsuite/ + * gcc.dg/pr28685-1.c: New file. + + 2010-06-08 Sandra Loosemore + + PR tree-optimization/39874 + PR middle-end/28685 + + gcc/ + * gimple.h (maybe_fold_and_comparisons, maybe_fold_or_comparisons): + Declare. + * gimple-fold.c (canonicalize_bool, same_bool_comparison_p, + same_bool_result_p): New. + (and_var_with_comparison, and_var_with_comparison_1, + and_comparisons_1, and_comparisons, maybe_fold_and_comparisons): New. + (or_var_with_comparison, or_var_with_comparison_1, + or_comparisons_1, or_comparisons, maybe_fold_or_comparisons): New. + * tree-ssa-reassoc.c (eliminate_redundant_comparison): Use + maybe_fold_and_comparisons or maybe_fold_or_comparisons instead + of combine_comparisons. + * tree-ssa-ifcombine.c (ifcombine_ifandif, ifcombine_iforif): Likewise. + + gcc/testsuite/ + * gcc.dg/pr39874.c: New file. + + 2010-07-10 Yao Qi + + Merge from Sourcery G++ 4.4: + +=== modified file 'gcc/gimple.h' +--- old/gcc/gimple.h 2010-04-02 18:54:46 +0000 ++++ new/gcc/gimple.h 2010-07-30 13:21:51 +0000 +@@ -4743,4 +4743,9 @@ + + extern void dump_gimple_statistics (void); + ++extern tree maybe_fold_and_comparisons (enum tree_code, tree, tree, ++ enum tree_code, tree, tree); ++extern tree maybe_fold_or_comparisons (enum tree_code, tree, tree, ++ enum tree_code, tree, tree); ++ + #endif /* GCC_GIMPLE_H */ + +=== added file 'gcc/testsuite/gcc.dg/pr28685-1.c' +--- old/gcc/testsuite/gcc.dg/pr28685-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/pr28685-1.c 2010-07-30 13:21:51 +0000 +@@ -0,0 +1,50 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++/* Should produce <=. */ ++int test1 (int a, int b) ++{ ++ return (a < b || a == b); ++} ++ ++/* Should produce <=. */ ++int test2 (int a, int b) ++{ ++ int lt = a < b; ++ int eq = a == b; ++ ++ return (lt || eq); ++} ++ ++/* Should produce <= (just deleting redundant test). */ ++int test3 (int a, int b) ++{ ++ int lt = a <= b; ++ int eq = a == b; ++ ++ return (lt || eq); ++} ++ ++/* Should produce <= (operands reversed to test the swap logic). */ ++int test4 (int a, int b) ++{ ++ int lt = a < b; ++ int eq = b == a; ++ ++ return (lt || eq); ++} ++ ++/* Should produce constant 0. */ ++int test5 (int a, int b) ++{ ++ int lt = a < b; ++ int eq = a == b; ++ ++ return (lt && eq); ++} ++ ++/* { dg-final { scan-tree-dump-times " <= " 4 "optimized" } } */ ++/* { dg-final { scan-tree-dump-times "return 0" 1 "optimized" } } */ ++/* { dg-final { scan-tree-dump-not " < " "optimized" } } */ ++/* { dg-final { scan-tree-dump-not " == " "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ + +=== added file 'gcc/testsuite/gcc.dg/pr39874.c' +--- old/gcc/testsuite/gcc.dg/pr39874.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/pr39874.c 2010-07-30 13:21:51 +0000 +@@ -0,0 +1,29 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++extern void func(); ++ ++void test1(char *signature) ++{ ++ char ch = signature[0]; ++ if (ch == 15 || ch == 3) ++ { ++ if (ch == 15) func(); ++ } ++} ++ ++ ++void test2(char *signature) ++{ ++ char ch = signature[0]; ++ if (ch == 15 || ch == 3) ++ { ++ if (ch > 14) func(); ++ } ++} ++ ++/* { dg-final { scan-tree-dump-times " == 15" 2 "optimized" } } */ ++/* { dg-final { scan-tree-dump-not " == 3" "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ ++ ++ + +=== modified file 'gcc/tree-ssa-ccp.c' +--- old/gcc/tree-ssa-ccp.c 2010-04-02 15:50:04 +0000 ++++ new/gcc/tree-ssa-ccp.c 2010-07-30 13:21:51 +0000 +@@ -3176,6 +3176,1056 @@ + return changed; + } + ++/* Canonicalize and possibly invert the boolean EXPR; return NULL_TREE ++ if EXPR is null or we don't know how. ++ If non-null, the result always has boolean type. */ ++ ++static tree ++canonicalize_bool (tree expr, bool invert) ++{ ++ if (!expr) ++ return NULL_TREE; ++ else if (invert) ++ { ++ if (integer_nonzerop (expr)) ++ return boolean_false_node; ++ else if (integer_zerop (expr)) ++ return boolean_true_node; ++ else if (TREE_CODE (expr) == SSA_NAME) ++ return fold_build2 (EQ_EXPR, boolean_type_node, expr, ++ build_int_cst (TREE_TYPE (expr), 0)); ++ else if (TREE_CODE_CLASS (TREE_CODE (expr)) == tcc_comparison) ++ return fold_build2 (invert_tree_comparison (TREE_CODE (expr), false), ++ boolean_type_node, ++ TREE_OPERAND (expr, 0), ++ TREE_OPERAND (expr, 1)); ++ else ++ return NULL_TREE; ++ } ++ else ++ { ++ if (TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE) ++ return expr; ++ if (integer_nonzerop (expr)) ++ return boolean_true_node; ++ else if (integer_zerop (expr)) ++ return boolean_false_node; ++ else if (TREE_CODE (expr) == SSA_NAME) ++ return fold_build2 (NE_EXPR, boolean_type_node, expr, ++ build_int_cst (TREE_TYPE (expr), 0)); ++ else if (TREE_CODE_CLASS (TREE_CODE (expr)) == tcc_comparison) ++ return fold_build2 (TREE_CODE (expr), ++ boolean_type_node, ++ TREE_OPERAND (expr, 0), ++ TREE_OPERAND (expr, 1)); ++ else ++ return NULL_TREE; ++ } ++} ++ ++/* Check to see if a boolean expression EXPR is logically equivalent to the ++ comparison (OP1 CODE OP2). Check for various identities involving ++ SSA_NAMEs. */ ++ ++static bool ++same_bool_comparison_p (const_tree expr, enum tree_code code, ++ const_tree op1, const_tree op2) ++{ ++ gimple s; ++ ++ /* The obvious case. */ ++ if (TREE_CODE (expr) == code ++ && operand_equal_p (TREE_OPERAND (expr, 0), op1, 0) ++ && operand_equal_p (TREE_OPERAND (expr, 1), op2, 0)) ++ return true; ++ ++ /* Check for comparing (name, name != 0) and the case where expr ++ is an SSA_NAME with a definition matching the comparison. */ ++ if (TREE_CODE (expr) == SSA_NAME ++ && TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE) ++ { ++ if (operand_equal_p (expr, op1, 0)) ++ return ((code == NE_EXPR && integer_zerop (op2)) ++ || (code == EQ_EXPR && integer_nonzerop (op2))); ++ s = SSA_NAME_DEF_STMT (expr); ++ if (is_gimple_assign (s) ++ && gimple_assign_rhs_code (s) == code ++ && operand_equal_p (gimple_assign_rhs1 (s), op1, 0) ++ && operand_equal_p (gimple_assign_rhs2 (s), op2, 0)) ++ return true; ++ } ++ ++ /* If op1 is of the form (name != 0) or (name == 0), and the definition ++ of name is a comparison, recurse. */ ++ if (TREE_CODE (op1) == SSA_NAME ++ && TREE_CODE (TREE_TYPE (op1)) == BOOLEAN_TYPE) ++ { ++ s = SSA_NAME_DEF_STMT (op1); ++ if (is_gimple_assign (s) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison) ++ { ++ enum tree_code c = gimple_assign_rhs_code (s); ++ if ((c == NE_EXPR && integer_zerop (op2)) ++ || (c == EQ_EXPR && integer_nonzerop (op2))) ++ return same_bool_comparison_p (expr, c, ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s)); ++ if ((c == EQ_EXPR && integer_zerop (op2)) ++ || (c == NE_EXPR && integer_nonzerop (op2))) ++ return same_bool_comparison_p (expr, ++ invert_tree_comparison (c, false), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s)); ++ } ++ } ++ return false; ++} ++ ++/* Check to see if two boolean expressions OP1 and OP2 are logically ++ equivalent. */ ++ ++static bool ++same_bool_result_p (const_tree op1, const_tree op2) ++{ ++ /* Simple cases first. */ ++ if (operand_equal_p (op1, op2, 0)) ++ return true; ++ ++ /* Check the cases where at least one of the operands is a comparison. ++ These are a bit smarter than operand_equal_p in that they apply some ++ identifies on SSA_NAMEs. */ ++ if (TREE_CODE_CLASS (TREE_CODE (op2)) == tcc_comparison ++ && same_bool_comparison_p (op1, TREE_CODE (op2), ++ TREE_OPERAND (op2, 0), ++ TREE_OPERAND (op2, 1))) ++ return true; ++ if (TREE_CODE_CLASS (TREE_CODE (op1)) == tcc_comparison ++ && same_bool_comparison_p (op2, TREE_CODE (op1), ++ TREE_OPERAND (op1, 0), ++ TREE_OPERAND (op1, 1))) ++ return true; ++ ++ /* Default case. */ ++ return false; ++} ++ ++/* Forward declarations for some mutually recursive functions. */ ++ ++static tree ++and_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++and_var_with_comparison (tree var, bool invert, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++and_var_with_comparison_1 (gimple stmt, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++or_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++or_var_with_comparison (tree var, bool invert, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++or_var_with_comparison_1 (gimple stmt, ++ enum tree_code code2, tree op2a, tree op2b); ++ ++/* Helper function for and_comparisons_1: try to simplify the AND of the ++ ssa variable VAR with the comparison specified by (OP2A CODE2 OP2B). ++ If INVERT is true, invert the value of the VAR before doing the AND. ++ Return NULL_EXPR if we can't simplify this to a single expression. */ ++ ++static tree ++and_var_with_comparison (tree var, bool invert, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree t; ++ gimple stmt = SSA_NAME_DEF_STMT (var); ++ ++ /* We can only deal with variables whose definitions are assignments. */ ++ if (!is_gimple_assign (stmt)) ++ return NULL_TREE; ++ ++ /* If we have an inverted comparison, apply DeMorgan's law and rewrite ++ !var AND (op2a code2 op2b) => !(var OR !(op2a code2 op2b)) ++ Then we only have to consider the simpler non-inverted cases. */ ++ if (invert) ++ t = or_var_with_comparison_1 (stmt, ++ invert_tree_comparison (code2, false), ++ op2a, op2b); ++ else ++ t = and_var_with_comparison_1 (stmt, code2, op2a, op2b); ++ return canonicalize_bool (t, invert); ++} ++ ++/* Try to simplify the AND of the ssa variable defined by the assignment ++ STMT with the comparison specified by (OP2A CODE2 OP2B). ++ Return NULL_EXPR if we can't simplify this to a single expression. */ ++ ++static tree ++and_var_with_comparison_1 (gimple stmt, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree var = gimple_assign_lhs (stmt); ++ tree true_test_var = NULL_TREE; ++ tree false_test_var = NULL_TREE; ++ enum tree_code innercode = gimple_assign_rhs_code (stmt); ++ ++ /* Check for identities like (var AND (var == 0)) => false. */ ++ if (TREE_CODE (op2a) == SSA_NAME ++ && TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE) ++ { ++ if ((code2 == NE_EXPR && integer_zerop (op2b)) ++ || (code2 == EQ_EXPR && integer_nonzerop (op2b))) ++ { ++ true_test_var = op2a; ++ if (var == true_test_var) ++ return var; ++ } ++ else if ((code2 == EQ_EXPR && integer_zerop (op2b)) ++ || (code2 == NE_EXPR && integer_nonzerop (op2b))) ++ { ++ false_test_var = op2a; ++ if (var == false_test_var) ++ return boolean_false_node; ++ } ++ } ++ ++ /* If the definition is a comparison, recurse on it. */ ++ if (TREE_CODE_CLASS (innercode) == tcc_comparison) ++ { ++ tree t = and_comparisons_1 (innercode, ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ code2, ++ op2a, ++ op2b); ++ if (t) ++ return t; ++ } ++ ++ /* If the definition is an AND or OR expression, we may be able to ++ simplify by reassociating. */ ++ if (innercode == TRUTH_AND_EXPR ++ || innercode == TRUTH_OR_EXPR ++ || (TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE ++ && (innercode == BIT_AND_EXPR || innercode == BIT_IOR_EXPR))) ++ { ++ tree inner1 = gimple_assign_rhs1 (stmt); ++ tree inner2 = gimple_assign_rhs2 (stmt); ++ gimple s; ++ tree t; ++ tree partial = NULL_TREE; ++ bool is_and = (innercode == TRUTH_AND_EXPR || innercode == BIT_AND_EXPR); ++ ++ /* Check for boolean identities that don't require recursive examination ++ of inner1/inner2: ++ inner1 AND (inner1 AND inner2) => inner1 AND inner2 => var ++ inner1 AND (inner1 OR inner2) => inner1 ++ !inner1 AND (inner1 AND inner2) => false ++ !inner1 AND (inner1 OR inner2) => !inner1 AND inner2 ++ Likewise for similar cases involving inner2. */ ++ if (inner1 == true_test_var) ++ return (is_and ? var : inner1); ++ else if (inner2 == true_test_var) ++ return (is_and ? var : inner2); ++ else if (inner1 == false_test_var) ++ return (is_and ++ ? boolean_false_node ++ : and_var_with_comparison (inner2, false, code2, op2a, op2b)); ++ else if (inner2 == false_test_var) ++ return (is_and ++ ? boolean_false_node ++ : and_var_with_comparison (inner1, false, code2, op2a, op2b)); ++ ++ /* Next, redistribute/reassociate the AND across the inner tests. ++ Compute the first partial result, (inner1 AND (op2a code op2b)) */ ++ if (TREE_CODE (inner1) == SSA_NAME ++ && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner1)) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison ++ && (t = maybe_fold_and_comparisons (gimple_assign_rhs_code (s), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s), ++ code2, op2a, op2b))) ++ { ++ /* Handle the AND case, where we are reassociating: ++ (inner1 AND inner2) AND (op2a code2 op2b) ++ => (t AND inner2) ++ If the partial result t is a constant, we win. Otherwise ++ continue on to try reassociating with the other inner test. */ ++ if (is_and) ++ { ++ if (integer_onep (t)) ++ return inner2; ++ else if (integer_zerop (t)) ++ return boolean_false_node; ++ } ++ ++ /* Handle the OR case, where we are redistributing: ++ (inner1 OR inner2) AND (op2a code2 op2b) ++ => (t OR (inner2 AND (op2a code2 op2b))) */ ++ else ++ { ++ if (integer_onep (t)) ++ return boolean_true_node; ++ else ++ /* Save partial result for later. */ ++ partial = t; ++ } ++ } ++ ++ /* Compute the second partial result, (inner2 AND (op2a code op2b)) */ ++ if (TREE_CODE (inner2) == SSA_NAME ++ && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner2)) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison ++ && (t = maybe_fold_and_comparisons (gimple_assign_rhs_code (s), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s), ++ code2, op2a, op2b))) ++ { ++ /* Handle the AND case, where we are reassociating: ++ (inner1 AND inner2) AND (op2a code2 op2b) ++ => (inner1 AND t) */ ++ if (is_and) ++ { ++ if (integer_onep (t)) ++ return inner1; ++ else if (integer_zerop (t)) ++ return boolean_false_node; ++ } ++ ++ /* Handle the OR case. where we are redistributing: ++ (inner1 OR inner2) AND (op2a code2 op2b) ++ => (t OR (inner1 AND (op2a code2 op2b))) ++ => (t OR partial) */ ++ else ++ { ++ if (integer_onep (t)) ++ return boolean_true_node; ++ else if (partial) ++ { ++ /* We already got a simplification for the other ++ operand to the redistributed OR expression. The ++ interesting case is when at least one is false. ++ Or, if both are the same, we can apply the identity ++ (x OR x) == x. */ ++ if (integer_zerop (partial)) ++ return t; ++ else if (integer_zerop (t)) ++ return partial; ++ else if (same_bool_result_p (t, partial)) ++ return t; ++ } ++ } ++ } ++ } ++ return NULL_TREE; ++} ++ ++/* Try to simplify the AND of two comparisons defined by ++ (OP1A CODE1 OP1B) and (OP2A CODE2 OP2B), respectively. ++ If this can be done without constructing an intermediate value, ++ return the resulting tree; otherwise NULL_TREE is returned. ++ This function is deliberately asymmetric as it recurses on SSA_DEFs ++ in the first comparison but not the second. */ ++ ++static tree ++and_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ /* First check for ((x CODE1 y) AND (x CODE2 y)). */ ++ if (operand_equal_p (op1a, op2a, 0) ++ && operand_equal_p (op1b, op2b, 0)) ++ { ++ tree t = combine_comparisons (UNKNOWN_LOCATION, ++ TRUTH_ANDIF_EXPR, code1, code2, ++ boolean_type_node, op1a, op1b); ++ if (t) ++ return t; ++ } ++ ++ /* Likewise the swapped case of the above. */ ++ if (operand_equal_p (op1a, op2b, 0) ++ && operand_equal_p (op1b, op2a, 0)) ++ { ++ tree t = combine_comparisons (UNKNOWN_LOCATION, ++ TRUTH_ANDIF_EXPR, code1, ++ swap_tree_comparison (code2), ++ boolean_type_node, op1a, op1b); ++ if (t) ++ return t; ++ } ++ ++ /* If both comparisons are of the same value against constants, we might ++ be able to merge them. */ ++ if (operand_equal_p (op1a, op2a, 0) ++ && TREE_CODE (op1b) == INTEGER_CST ++ && TREE_CODE (op2b) == INTEGER_CST) ++ { ++ int cmp = tree_int_cst_compare (op1b, op2b); ++ ++ /* If we have (op1a == op1b), we should either be able to ++ return that or FALSE, depending on whether the constant op1b ++ also satisfies the other comparison against op2b. */ ++ if (code1 == EQ_EXPR) ++ { ++ bool done = true; ++ bool val; ++ switch (code2) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp < 0); break; ++ case GT_EXPR: val = (cmp > 0); break; ++ case LE_EXPR: val = (cmp <= 0); break; ++ case GE_EXPR: val = (cmp >= 0); break; ++ default: done = false; ++ } ++ if (done) ++ { ++ if (val) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ else ++ return boolean_false_node; ++ } ++ } ++ /* Likewise if the second comparison is an == comparison. */ ++ else if (code2 == EQ_EXPR) ++ { ++ bool done = true; ++ bool val; ++ switch (code1) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp > 0); break; ++ case GT_EXPR: val = (cmp < 0); break; ++ case LE_EXPR: val = (cmp >= 0); break; ++ case GE_EXPR: val = (cmp <= 0); break; ++ default: done = false; ++ } ++ if (done) ++ { ++ if (val) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ else ++ return boolean_false_node; ++ } ++ } ++ ++ /* Same business with inequality tests. */ ++ else if (code1 == NE_EXPR) ++ { ++ bool val; ++ switch (code2) ++ { ++ case EQ_EXPR: val = (cmp != 0); break; ++ case NE_EXPR: val = (cmp == 0); break; ++ case LT_EXPR: val = (cmp >= 0); break; ++ case GT_EXPR: val = (cmp <= 0); break; ++ case LE_EXPR: val = (cmp > 0); break; ++ case GE_EXPR: val = (cmp < 0); break; ++ default: ++ val = false; ++ } ++ if (val) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ else if (code2 == NE_EXPR) ++ { ++ bool val; ++ switch (code1) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp <= 0); break; ++ case GT_EXPR: val = (cmp >= 0); break; ++ case LE_EXPR: val = (cmp < 0); break; ++ case GE_EXPR: val = (cmp > 0); break; ++ default: ++ val = false; ++ } ++ if (val) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ ++ /* Chose the more restrictive of two < or <= comparisons. */ ++ else if ((code1 == LT_EXPR || code1 == LE_EXPR) ++ && (code2 == LT_EXPR || code2 == LE_EXPR)) ++ { ++ if ((cmp < 0) || (cmp == 0 && code1 == LT_EXPR)) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ else ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ ++ /* Likewise chose the more restrictive of two > or >= comparisons. */ ++ else if ((code1 == GT_EXPR || code1 == GE_EXPR) ++ && (code2 == GT_EXPR || code2 == GE_EXPR)) ++ { ++ if ((cmp > 0) || (cmp == 0 && code1 == GT_EXPR)) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ else ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ ++ /* Check for singleton ranges. */ ++ else if (cmp == 0 ++ && ((code1 == LE_EXPR && code2 == GE_EXPR) ++ || (code1 == GE_EXPR && code2 == LE_EXPR))) ++ return fold_build2 (EQ_EXPR, boolean_type_node, op1a, op2b); ++ ++ /* Check for disjoint ranges. */ ++ else if (cmp <= 0 ++ && (code1 == LT_EXPR || code1 == LE_EXPR) ++ && (code2 == GT_EXPR || code2 == GE_EXPR)) ++ return boolean_false_node; ++ else if (cmp >= 0 ++ && (code1 == GT_EXPR || code1 == GE_EXPR) ++ && (code2 == LT_EXPR || code2 == LE_EXPR)) ++ return boolean_false_node; ++ } ++ ++ /* Perhaps the first comparison is (NAME != 0) or (NAME == 1) where ++ NAME's definition is a truth value. See if there are any simplifications ++ that can be done against the NAME's definition. */ ++ if (TREE_CODE (op1a) == SSA_NAME ++ && (code1 == NE_EXPR || code1 == EQ_EXPR) ++ && (integer_zerop (op1b) || integer_onep (op1b))) ++ { ++ bool invert = ((code1 == EQ_EXPR && integer_zerop (op1b)) ++ || (code1 == NE_EXPR && integer_onep (op1b))); ++ gimple stmt = SSA_NAME_DEF_STMT (op1a); ++ switch (gimple_code (stmt)) ++ { ++ case GIMPLE_ASSIGN: ++ /* Try to simplify by copy-propagating the definition. */ ++ return and_var_with_comparison (op1a, invert, code2, op2a, op2b); ++ ++ case GIMPLE_PHI: ++ /* If every argument to the PHI produces the same result when ++ ANDed with the second comparison, we win. ++ Do not do this unless the type is bool since we need a bool ++ result here anyway. */ ++ if (TREE_CODE (TREE_TYPE (op1a)) == BOOLEAN_TYPE) ++ { ++ tree result = NULL_TREE; ++ unsigned i; ++ for (i = 0; i < gimple_phi_num_args (stmt); i++) ++ { ++ tree arg = gimple_phi_arg_def (stmt, i); ++ ++ /* If this PHI has itself as an argument, ignore it. ++ If all the other args produce the same result, ++ we're still OK. */ ++ if (arg == gimple_phi_result (stmt)) ++ continue; ++ else if (TREE_CODE (arg) == INTEGER_CST) ++ { ++ if (invert ? integer_nonzerop (arg) : integer_zerop (arg)) ++ { ++ if (!result) ++ result = boolean_false_node; ++ else if (!integer_zerop (result)) ++ return NULL_TREE; ++ } ++ else if (!result) ++ result = fold_build2 (code2, boolean_type_node, ++ op2a, op2b); ++ else if (!same_bool_comparison_p (result, ++ code2, op2a, op2b)) ++ return NULL_TREE; ++ } ++ else if (TREE_CODE (arg) == SSA_NAME) ++ { ++ tree temp = and_var_with_comparison (arg, invert, ++ code2, op2a, op2b); ++ if (!temp) ++ return NULL_TREE; ++ else if (!result) ++ result = temp; ++ else if (!same_bool_result_p (result, temp)) ++ return NULL_TREE; ++ } ++ else ++ return NULL_TREE; ++ } ++ return result; ++ } ++ ++ default: ++ break; ++ } ++ } ++ return NULL_TREE; ++} ++ ++/* Try to simplify the AND of two comparisons, specified by ++ (OP1A CODE1 OP1B) and (OP2B CODE2 OP2B), respectively. ++ If this can be simplified to a single expression (without requiring ++ introducing more SSA variables to hold intermediate values), ++ return the resulting tree. Otherwise return NULL_TREE. ++ If the result expression is non-null, it has boolean type. */ ++ ++tree ++maybe_fold_and_comparisons (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree t = and_comparisons_1 (code1, op1a, op1b, code2, op2a, op2b); ++ if (t) ++ return t; ++ else ++ return and_comparisons_1 (code2, op2a, op2b, code1, op1a, op1b); ++} ++ ++/* Helper function for or_comparisons_1: try to simplify the OR of the ++ ssa variable VAR with the comparison specified by (OP2A CODE2 OP2B). ++ If INVERT is true, invert the value of VAR before doing the OR. ++ Return NULL_EXPR if we can't simplify this to a single expression. */ ++ ++static tree ++or_var_with_comparison (tree var, bool invert, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree t; ++ gimple stmt = SSA_NAME_DEF_STMT (var); ++ ++ /* We can only deal with variables whose definitions are assignments. */ ++ if (!is_gimple_assign (stmt)) ++ return NULL_TREE; ++ ++ /* If we have an inverted comparison, apply DeMorgan's law and rewrite ++ !var OR (op2a code2 op2b) => !(var AND !(op2a code2 op2b)) ++ Then we only have to consider the simpler non-inverted cases. */ ++ if (invert) ++ t = and_var_with_comparison_1 (stmt, ++ invert_tree_comparison (code2, false), ++ op2a, op2b); ++ else ++ t = or_var_with_comparison_1 (stmt, code2, op2a, op2b); ++ return canonicalize_bool (t, invert); ++} ++ ++/* Try to simplify the OR of the ssa variable defined by the assignment ++ STMT with the comparison specified by (OP2A CODE2 OP2B). ++ Return NULL_EXPR if we can't simplify this to a single expression. */ ++ ++static tree ++or_var_with_comparison_1 (gimple stmt, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree var = gimple_assign_lhs (stmt); ++ tree true_test_var = NULL_TREE; ++ tree false_test_var = NULL_TREE; ++ enum tree_code innercode = gimple_assign_rhs_code (stmt); ++ ++ /* Check for identities like (var OR (var != 0)) => true . */ ++ if (TREE_CODE (op2a) == SSA_NAME ++ && TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE) ++ { ++ if ((code2 == NE_EXPR && integer_zerop (op2b)) ++ || (code2 == EQ_EXPR && integer_nonzerop (op2b))) ++ { ++ true_test_var = op2a; ++ if (var == true_test_var) ++ return var; ++ } ++ else if ((code2 == EQ_EXPR && integer_zerop (op2b)) ++ || (code2 == NE_EXPR && integer_nonzerop (op2b))) ++ { ++ false_test_var = op2a; ++ if (var == false_test_var) ++ return boolean_true_node; ++ } ++ } ++ ++ /* If the definition is a comparison, recurse on it. */ ++ if (TREE_CODE_CLASS (innercode) == tcc_comparison) ++ { ++ tree t = or_comparisons_1 (innercode, ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ code2, ++ op2a, ++ op2b); ++ if (t) ++ return t; ++ } ++ ++ /* If the definition is an AND or OR expression, we may be able to ++ simplify by reassociating. */ ++ if (innercode == TRUTH_AND_EXPR ++ || innercode == TRUTH_OR_EXPR ++ || (TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE ++ && (innercode == BIT_AND_EXPR || innercode == BIT_IOR_EXPR))) ++ { ++ tree inner1 = gimple_assign_rhs1 (stmt); ++ tree inner2 = gimple_assign_rhs2 (stmt); ++ gimple s; ++ tree t; ++ tree partial = NULL_TREE; ++ bool is_or = (innercode == TRUTH_OR_EXPR || innercode == BIT_IOR_EXPR); ++ ++ /* Check for boolean identities that don't require recursive examination ++ of inner1/inner2: ++ inner1 OR (inner1 OR inner2) => inner1 OR inner2 => var ++ inner1 OR (inner1 AND inner2) => inner1 ++ !inner1 OR (inner1 OR inner2) => true ++ !inner1 OR (inner1 AND inner2) => !inner1 OR inner2 ++ */ ++ if (inner1 == true_test_var) ++ return (is_or ? var : inner1); ++ else if (inner2 == true_test_var) ++ return (is_or ? var : inner2); ++ else if (inner1 == false_test_var) ++ return (is_or ++ ? boolean_true_node ++ : or_var_with_comparison (inner2, false, code2, op2a, op2b)); ++ else if (inner2 == false_test_var) ++ return (is_or ++ ? boolean_true_node ++ : or_var_with_comparison (inner1, false, code2, op2a, op2b)); ++ ++ /* Next, redistribute/reassociate the OR across the inner tests. ++ Compute the first partial result, (inner1 OR (op2a code op2b)) */ ++ if (TREE_CODE (inner1) == SSA_NAME ++ && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner1)) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison ++ && (t = maybe_fold_or_comparisons (gimple_assign_rhs_code (s), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s), ++ code2, op2a, op2b))) ++ { ++ /* Handle the OR case, where we are reassociating: ++ (inner1 OR inner2) OR (op2a code2 op2b) ++ => (t OR inner2) ++ If the partial result t is a constant, we win. Otherwise ++ continue on to try reassociating with the other inner test. */ ++ if (innercode == TRUTH_OR_EXPR) ++ { ++ if (integer_onep (t)) ++ return boolean_true_node; ++ else if (integer_zerop (t)) ++ return inner2; ++ } ++ ++ /* Handle the AND case, where we are redistributing: ++ (inner1 AND inner2) OR (op2a code2 op2b) ++ => (t AND (inner2 OR (op2a code op2b))) */ ++ else ++ { ++ if (integer_zerop (t)) ++ return boolean_false_node; ++ else ++ /* Save partial result for later. */ ++ partial = t; ++ } ++ } ++ ++ /* Compute the second partial result, (inner2 OR (op2a code op2b)) */ ++ if (TREE_CODE (inner2) == SSA_NAME ++ && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner2)) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison ++ && (t = maybe_fold_or_comparisons (gimple_assign_rhs_code (s), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s), ++ code2, op2a, op2b))) ++ { ++ /* Handle the OR case, where we are reassociating: ++ (inner1 OR inner2) OR (op2a code2 op2b) ++ => (inner1 OR t) */ ++ if (innercode == TRUTH_OR_EXPR) ++ { ++ if (integer_zerop (t)) ++ return inner1; ++ else if (integer_onep (t)) ++ return boolean_true_node; ++ } ++ ++ /* Handle the AND case, where we are redistributing: ++ (inner1 AND inner2) OR (op2a code2 op2b) ++ => (t AND (inner1 OR (op2a code2 op2b))) ++ => (t AND partial) */ ++ else ++ { ++ if (integer_zerop (t)) ++ return boolean_false_node; ++ else if (partial) ++ { ++ /* We already got a simplification for the other ++ operand to the redistributed AND expression. The ++ interesting case is when at least one is true. ++ Or, if both are the same, we can apply the identity ++ (x AND x) == true. */ ++ if (integer_onep (partial)) ++ return t; ++ else if (integer_onep (t)) ++ return partial; ++ else if (same_bool_result_p (t, partial)) ++ return boolean_true_node; ++ } ++ } ++ } ++ } ++ return NULL_TREE; ++} ++ ++/* Try to simplify the OR of two comparisons defined by ++ (OP1A CODE1 OP1B) and (OP2A CODE2 OP2B), respectively. ++ If this can be done without constructing an intermediate value, ++ return the resulting tree; otherwise NULL_TREE is returned. ++ This function is deliberately asymmetric as it recurses on SSA_DEFs ++ in the first comparison but not the second. */ ++ ++static tree ++or_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ /* First check for ((x CODE1 y) OR (x CODE2 y)). */ ++ if (operand_equal_p (op1a, op2a, 0) ++ && operand_equal_p (op1b, op2b, 0)) ++ { ++ tree t = combine_comparisons (UNKNOWN_LOCATION, ++ TRUTH_ORIF_EXPR, code1, code2, ++ boolean_type_node, op1a, op1b); ++ if (t) ++ return t; ++ } ++ ++ /* Likewise the swapped case of the above. */ ++ if (operand_equal_p (op1a, op2b, 0) ++ && operand_equal_p (op1b, op2a, 0)) ++ { ++ tree t = combine_comparisons (UNKNOWN_LOCATION, ++ TRUTH_ORIF_EXPR, code1, ++ swap_tree_comparison (code2), ++ boolean_type_node, op1a, op1b); ++ if (t) ++ return t; ++ } ++ ++ /* If both comparisons are of the same value against constants, we might ++ be able to merge them. */ ++ if (operand_equal_p (op1a, op2a, 0) ++ && TREE_CODE (op1b) == INTEGER_CST ++ && TREE_CODE (op2b) == INTEGER_CST) ++ { ++ int cmp = tree_int_cst_compare (op1b, op2b); ++ ++ /* If we have (op1a != op1b), we should either be able to ++ return that or TRUE, depending on whether the constant op1b ++ also satisfies the other comparison against op2b. */ ++ if (code1 == NE_EXPR) ++ { ++ bool done = true; ++ bool val; ++ switch (code2) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp < 0); break; ++ case GT_EXPR: val = (cmp > 0); break; ++ case LE_EXPR: val = (cmp <= 0); break; ++ case GE_EXPR: val = (cmp >= 0); break; ++ default: done = false; ++ } ++ if (done) ++ { ++ if (val) ++ return boolean_true_node; ++ else ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ } ++ /* Likewise if the second comparison is a != comparison. */ ++ else if (code2 == NE_EXPR) ++ { ++ bool done = true; ++ bool val; ++ switch (code1) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp > 0); break; ++ case GT_EXPR: val = (cmp < 0); break; ++ case LE_EXPR: val = (cmp >= 0); break; ++ case GE_EXPR: val = (cmp <= 0); break; ++ default: done = false; ++ } ++ if (done) ++ { ++ if (val) ++ return boolean_true_node; ++ else ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ } ++ ++ /* See if an equality test is redundant with the other comparison. */ ++ else if (code1 == EQ_EXPR) ++ { ++ bool val; ++ switch (code2) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp < 0); break; ++ case GT_EXPR: val = (cmp > 0); break; ++ case LE_EXPR: val = (cmp <= 0); break; ++ case GE_EXPR: val = (cmp >= 0); break; ++ default: ++ val = false; ++ } ++ if (val) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ else if (code2 == EQ_EXPR) ++ { ++ bool val; ++ switch (code1) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp > 0); break; ++ case GT_EXPR: val = (cmp < 0); break; ++ case LE_EXPR: val = (cmp >= 0); break; ++ case GE_EXPR: val = (cmp <= 0); break; ++ default: ++ val = false; ++ } ++ if (val) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ ++ /* Chose the less restrictive of two < or <= comparisons. */ ++ else if ((code1 == LT_EXPR || code1 == LE_EXPR) ++ && (code2 == LT_EXPR || code2 == LE_EXPR)) ++ { ++ if ((cmp < 0) || (cmp == 0 && code1 == LT_EXPR)) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ else ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ ++ /* Likewise chose the less restrictive of two > or >= comparisons. */ ++ else if ((code1 == GT_EXPR || code1 == GE_EXPR) ++ && (code2 == GT_EXPR || code2 == GE_EXPR)) ++ { ++ if ((cmp > 0) || (cmp == 0 && code1 == GT_EXPR)) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ else ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ ++ /* Check for singleton ranges. */ ++ else if (cmp == 0 ++ && ((code1 == LT_EXPR && code2 == GT_EXPR) ++ || (code1 == GT_EXPR && code2 == LT_EXPR))) ++ return fold_build2 (NE_EXPR, boolean_type_node, op1a, op2b); ++ ++ /* Check for less/greater pairs that don't restrict the range at all. */ ++ else if (cmp >= 0 ++ && (code1 == LT_EXPR || code1 == LE_EXPR) ++ && (code2 == GT_EXPR || code2 == GE_EXPR)) ++ return boolean_true_node; ++ else if (cmp <= 0 ++ && (code1 == GT_EXPR || code1 == GE_EXPR) ++ && (code2 == LT_EXPR || code2 == LE_EXPR)) ++ return boolean_true_node; ++ } ++ ++ /* Perhaps the first comparison is (NAME != 0) or (NAME == 1) where ++ NAME's definition is a truth value. See if there are any simplifications ++ that can be done against the NAME's definition. */ ++ if (TREE_CODE (op1a) == SSA_NAME ++ && (code1 == NE_EXPR || code1 == EQ_EXPR) ++ && (integer_zerop (op1b) || integer_onep (op1b))) ++ { ++ bool invert = ((code1 == EQ_EXPR && integer_zerop (op1b)) ++ || (code1 == NE_EXPR && integer_onep (op1b))); ++ gimple stmt = SSA_NAME_DEF_STMT (op1a); ++ switch (gimple_code (stmt)) ++ { ++ case GIMPLE_ASSIGN: ++ /* Try to simplify by copy-propagating the definition. */ ++ return or_var_with_comparison (op1a, invert, code2, op2a, op2b); ++ ++ case GIMPLE_PHI: ++ /* If every argument to the PHI produces the same result when ++ ORed with the second comparison, we win. ++ Do not do this unless the type is bool since we need a bool ++ result here anyway. */ ++ if (TREE_CODE (TREE_TYPE (op1a)) == BOOLEAN_TYPE) ++ { ++ tree result = NULL_TREE; ++ unsigned i; ++ for (i = 0; i < gimple_phi_num_args (stmt); i++) ++ { ++ tree arg = gimple_phi_arg_def (stmt, i); ++ ++ /* If this PHI has itself as an argument, ignore it. ++ If all the other args produce the same result, ++ we're still OK. */ ++ if (arg == gimple_phi_result (stmt)) ++ continue; ++ else if (TREE_CODE (arg) == INTEGER_CST) ++ { ++ if (invert ? integer_zerop (arg) : integer_nonzerop (arg)) ++ { ++ if (!result) ++ result = boolean_true_node; ++ else if (!integer_onep (result)) ++ return NULL_TREE; ++ } ++ else if (!result) ++ result = fold_build2 (code2, boolean_type_node, ++ op2a, op2b); ++ else if (!same_bool_comparison_p (result, ++ code2, op2a, op2b)) ++ return NULL_TREE; ++ } ++ else if (TREE_CODE (arg) == SSA_NAME) ++ { ++ tree temp = or_var_with_comparison (arg, invert, ++ code2, op2a, op2b); ++ if (!temp) ++ return NULL_TREE; ++ else if (!result) ++ result = temp; ++ else if (!same_bool_result_p (result, temp)) ++ return NULL_TREE; ++ } ++ else ++ return NULL_TREE; ++ } ++ return result; ++ } ++ ++ default: ++ break; ++ } ++ } ++ return NULL_TREE; ++} ++ ++/* Try to simplify the OR of two comparisons, specified by ++ (OP1A CODE1 OP1B) and (OP2B CODE2 OP2B), respectively. ++ If this can be simplified to a single expression (without requiring ++ introducing more SSA variables to hold intermediate values), ++ return the resulting tree. Otherwise return NULL_TREE. ++ If the result expression is non-null, it has boolean type. */ ++ ++tree ++maybe_fold_or_comparisons (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree t = or_comparisons_1 (code1, op1a, op1b, code2, op2a, op2b); ++ if (t) ++ return t; ++ else ++ return or_comparisons_1 (code2, op2a, op2b, code1, op1a, op1b); ++} ++ + /* Try to optimize out __builtin_stack_restore. Optimize it out + if there is another __builtin_stack_restore in the same basic + block and no calls or ASM_EXPRs are in between, or if this block's + +=== modified file 'gcc/tree-ssa-ifcombine.c' +--- old/gcc/tree-ssa-ifcombine.c 2009-11-25 10:55:54 +0000 ++++ new/gcc/tree-ssa-ifcombine.c 2010-07-30 13:21:51 +0000 +@@ -366,21 +366,16 @@ + + /* See if we have two comparisons that we can merge into one. */ + else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison +- && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison +- && operand_equal_p (gimple_cond_lhs (inner_cond), +- gimple_cond_lhs (outer_cond), 0) +- && operand_equal_p (gimple_cond_rhs (inner_cond), +- gimple_cond_rhs (outer_cond), 0)) ++ && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison) + { +- enum tree_code code1 = gimple_cond_code (inner_cond); +- enum tree_code code2 = gimple_cond_code (outer_cond); + tree t; + +- if (!(t = combine_comparisons (UNKNOWN_LOCATION, +- TRUTH_ANDIF_EXPR, code1, code2, +- boolean_type_node, +- gimple_cond_lhs (outer_cond), +- gimple_cond_rhs (outer_cond)))) ++ if (!(t = maybe_fold_and_comparisons (gimple_cond_code (inner_cond), ++ gimple_cond_lhs (inner_cond), ++ gimple_cond_rhs (inner_cond), ++ gimple_cond_code (outer_cond), ++ gimple_cond_lhs (outer_cond), ++ gimple_cond_rhs (outer_cond)))) + return false; + t = canonicalize_cond_expr_cond (t); + if (!t) +@@ -518,22 +513,17 @@ + /* See if we have two comparisons that we can merge into one. + This happens for C++ operator overloading where for example + GE_EXPR is implemented as GT_EXPR || EQ_EXPR. */ +- else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison +- && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison +- && operand_equal_p (gimple_cond_lhs (inner_cond), +- gimple_cond_lhs (outer_cond), 0) +- && operand_equal_p (gimple_cond_rhs (inner_cond), +- gimple_cond_rhs (outer_cond), 0)) ++ else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison ++ && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison) + { +- enum tree_code code1 = gimple_cond_code (inner_cond); +- enum tree_code code2 = gimple_cond_code (outer_cond); + tree t; + +- if (!(t = combine_comparisons (UNKNOWN_LOCATION, +- TRUTH_ORIF_EXPR, code1, code2, +- boolean_type_node, +- gimple_cond_lhs (outer_cond), +- gimple_cond_rhs (outer_cond)))) ++ if (!(t = maybe_fold_or_comparisons (gimple_cond_code (inner_cond), ++ gimple_cond_lhs (inner_cond), ++ gimple_cond_rhs (inner_cond), ++ gimple_cond_code (outer_cond), ++ gimple_cond_lhs (outer_cond), ++ gimple_cond_rhs (outer_cond)))) + return false; + t = canonicalize_cond_expr_cond (t); + if (!t) + +=== modified file 'gcc/tree-ssa-reassoc.c' +--- old/gcc/tree-ssa-reassoc.c 2010-01-13 15:04:38 +0000 ++++ new/gcc/tree-ssa-reassoc.c 2010-07-30 13:21:51 +0000 +@@ -1159,6 +1159,117 @@ + return changed; + } + ++/* If OPCODE is BIT_IOR_EXPR or BIT_AND_EXPR and CURR is a comparison ++ expression, examine the other OPS to see if any of them are comparisons ++ of the same values, which we may be able to combine or eliminate. ++ For example, we can rewrite (a < b) | (a == b) as (a <= b). */ ++ ++static bool ++eliminate_redundant_comparison (enum tree_code opcode, ++ VEC (operand_entry_t, heap) **ops, ++ unsigned int currindex, ++ operand_entry_t curr) ++{ ++ tree op1, op2; ++ enum tree_code lcode, rcode; ++ gimple def1, def2; ++ int i; ++ operand_entry_t oe; ++ ++ if (opcode != BIT_IOR_EXPR && opcode != BIT_AND_EXPR) ++ return false; ++ ++ /* Check that CURR is a comparison. */ ++ if (TREE_CODE (curr->op) != SSA_NAME) ++ return false; ++ def1 = SSA_NAME_DEF_STMT (curr->op); ++ if (!is_gimple_assign (def1)) ++ return false; ++ lcode = gimple_assign_rhs_code (def1); ++ if (TREE_CODE_CLASS (lcode) != tcc_comparison) ++ return false; ++ op1 = gimple_assign_rhs1 (def1); ++ op2 = gimple_assign_rhs2 (def1); ++ ++ /* Now look for a similar comparison in the remaining OPS. */ ++ for (i = currindex + 1; ++ VEC_iterate (operand_entry_t, *ops, i, oe); ++ i++) ++ { ++ tree t; ++ ++ if (TREE_CODE (oe->op) != SSA_NAME) ++ continue; ++ def2 = SSA_NAME_DEF_STMT (oe->op); ++ if (!is_gimple_assign (def2)) ++ continue; ++ rcode = gimple_assign_rhs_code (def2); ++ if (TREE_CODE_CLASS (rcode) != tcc_comparison) ++ continue; ++ ++ /* If we got here, we have a match. See if we can combine the ++ two comparisons. */ ++ if (opcode == BIT_IOR_EXPR) ++ t = maybe_fold_or_comparisons (lcode, op1, op2, ++ rcode, gimple_assign_rhs1 (def2), ++ gimple_assign_rhs2 (def2)); ++ else ++ t = maybe_fold_and_comparisons (lcode, op1, op2, ++ rcode, gimple_assign_rhs1 (def2), ++ gimple_assign_rhs2 (def2)); ++ if (!t) ++ continue; ++ ++ /* maybe_fold_and_comparisons and maybe_fold_or_comparisons ++ always give us a boolean_type_node value back. If the original ++ BIT_AND_EXPR or BIT_IOR_EXPR was of a wider integer type, ++ we need to convert. */ ++ if (!useless_type_conversion_p (TREE_TYPE (curr->op), TREE_TYPE (t))) ++ t = fold_convert (TREE_TYPE (curr->op), t); ++ ++ if (dump_file && (dump_flags & TDF_DETAILS)) ++ { ++ fprintf (dump_file, "Equivalence: "); ++ print_generic_expr (dump_file, curr->op, 0); ++ fprintf (dump_file, " %s ", op_symbol_code (opcode)); ++ print_generic_expr (dump_file, oe->op, 0); ++ fprintf (dump_file, " -> "); ++ print_generic_expr (dump_file, t, 0); ++ fprintf (dump_file, "\n"); ++ } ++ ++ /* Now we can delete oe, as it has been subsumed by the new combined ++ expression t. */ ++ VEC_ordered_remove (operand_entry_t, *ops, i); ++ reassociate_stats.ops_eliminated ++; ++ ++ /* If t is the same as curr->op, we're done. Otherwise we must ++ replace curr->op with t. Special case is if we got a constant ++ back, in which case we add it to the end instead of in place of ++ the current entry. */ ++ if (TREE_CODE (t) == INTEGER_CST) ++ { ++ VEC_ordered_remove (operand_entry_t, *ops, currindex); ++ add_to_ops_vec (ops, t); ++ } ++ else if (!operand_equal_p (t, curr->op, 0)) ++ { ++ tree tmpvar; ++ gimple sum; ++ enum tree_code subcode; ++ tree newop1; ++ tree newop2; ++ tmpvar = create_tmp_var (TREE_TYPE (t), NULL); ++ add_referenced_var (tmpvar); ++ extract_ops_from_tree (t, &subcode, &newop1, &newop2); ++ sum = build_and_add_sum (tmpvar, newop1, newop2, subcode); ++ curr->op = gimple_get_lhs (sum); ++ } ++ return true; ++ } ++ ++ return false; ++} + + /* Perform various identities and other optimizations on the list of + operand entries, stored in OPS. The tree code for the binary +@@ -1220,7 +1331,8 @@ + if (eliminate_not_pairs (opcode, ops, i, oe)) + return; + if (eliminate_duplicate_pair (opcode, ops, &done, i, oe, oelast) +- || (!done && eliminate_plus_minus_pair (opcode, ops, i, oe))) ++ || (!done && eliminate_plus_minus_pair (opcode, ops, i, oe)) ++ || (!done && eliminate_redundant_comparison (opcode, ops, i, oe))) + { + if (done) + return; + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch new file mode 100644 index 0000000000..9c936d4fad --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch @@ -0,0 +1,138 @@ +2010-07-12 Yao Qi + + Merge from Sourcery G++ 4.4: + + 2009-10-06 Paul Brook + Issue #3869 + gcc/ + * target.h (gcc_target): Add warn_func_result. + * target-def.h (TARGET_WARN_FUNC_RESULT): Define and use. + * tree-cfg.h (execute_warn_function_return): Use + targetm.warn_func_result. + * config/arm/arm.c (TARGET_WARN_FUNC_RESULT): Define. + (arm_warn_func_result): New function. + + gcc/testuite/ + * gcc.target/arm/naked-3.c: New test. + + 2010-07-10 Sandra Loosemore + + Backport from mainline: + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-07-29 16:58:56 +0000 ++++ new/gcc/config/arm/arm.c 2010-07-30 13:58:02 +0000 +@@ -214,6 +214,7 @@ + static int arm_issue_rate (void); + static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; + static bool arm_allocate_stack_slots_for_args (void); ++static bool arm_warn_func_result (void); + static const char *arm_invalid_parameter_type (const_tree t); + static const char *arm_invalid_return_type (const_tree t); + static tree arm_promoted_type (const_tree t); +@@ -378,6 +379,9 @@ + #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS + #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address + ++#undef TARGET_WARN_FUNC_RESULT ++#define TARGET_WARN_FUNC_RESULT arm_warn_func_result ++ + #undef TARGET_DEFAULT_SHORT_ENUMS + #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums + +@@ -2008,6 +2012,14 @@ + return !IS_NAKED (arm_current_func_type ()); + } + ++static bool ++arm_warn_func_result (void) ++{ ++ /* Naked functions are implemented entirely in assembly, including the ++ return sequence, so suppress warnings about this. */ ++ return !IS_NAKED (arm_current_func_type ()); ++} ++ + + /* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. + +=== modified file 'gcc/target-def.h' +--- old/gcc/target-def.h 2010-03-24 20:44:48 +0000 ++++ new/gcc/target-def.h 2010-07-30 13:58:02 +0000 +@@ -212,6 +212,10 @@ + #define TARGET_EXTRA_LIVE_ON_ENTRY hook_void_bitmap + #endif + ++#ifndef TARGET_WARN_FUNC_RESULT ++#define TARGET_WARN_FUNC_RESULT hook_bool_void_true ++#endif ++ + #ifndef TARGET_ASM_FILE_START_APP_OFF + #define TARGET_ASM_FILE_START_APP_OFF false + #endif +@@ -1020,6 +1024,7 @@ + TARGET_EMUTLS, \ + TARGET_OPTION_HOOKS, \ + TARGET_EXTRA_LIVE_ON_ENTRY, \ ++ TARGET_WARN_FUNC_RESULT, \ + TARGET_UNWIND_TABLES_DEFAULT, \ + TARGET_HAVE_NAMED_SECTIONS, \ + TARGET_HAVE_SWITCHABLE_BSS_SECTIONS, \ + +=== modified file 'gcc/target.h' +--- old/gcc/target.h 2010-03-27 10:27:39 +0000 ++++ new/gcc/target.h 2010-07-30 13:58:02 +0000 +@@ -1171,6 +1171,10 @@ + bits in the bitmap passed in. */ + void (*live_on_entry) (bitmap); + ++ /* Return false if warnings about missing return statements or suspect ++ noreturn attributes should be suppressed for the current function. */ ++ bool (*warn_func_result) (void); ++ + /* True if unwinding tables should be generated by default. */ + bool unwind_tables_default; + + +=== added file 'gcc/testsuite/gcc.target/arm/naked-3.c' +--- old/gcc/testsuite/gcc.target/arm/naked-3.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/naked-3.c 2010-07-30 13:58:02 +0000 +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -Wall" } */ ++/* Check that we do not get warnings about missing return statements ++ or bogus looking noreturn functions. */ ++int __attribute__((naked)) ++foo(void) ++{ ++ __asm__ volatile ("mov r0, #1\r\nbx lr\n"); ++} ++ ++int __attribute__((naked,noreturn)) ++bar(void) ++{ ++ __asm__ volatile ("frob r0\n"); ++} + +=== modified file 'gcc/tree-cfg.c' +--- old/gcc/tree-cfg.c 2010-03-16 12:31:38 +0000 ++++ new/gcc/tree-cfg.c 2010-07-30 13:58:02 +0000 +@@ -47,6 +47,7 @@ + #include "value-prof.h" + #include "pointer-set.h" + #include "tree-inline.h" ++#include "target.h" + + /* This file contains functions for building the Control Flow Graph (CFG) + for a function tree. */ +@@ -7092,6 +7093,9 @@ + edge e; + edge_iterator ei; + ++ if (!targetm.warn_func_result()) ++ return 0; ++ + /* If we have a path to EXIT, then we do return. */ + if (TREE_THIS_VOLATILE (cfun->decl) + && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch new file mode 100644 index 0000000000..bf35a2ed4e --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch @@ -0,0 +1,112 @@ +2010-07-15 Jie Zhang + + Backport from mainline (originally from Sourcery G++ 4.4): + + gcc/cp/ + 2010-04-07 Jie Zhang + + PR c++/42556 + * typeck2.c (split_nonconstant_init_1): Drop empty CONSTRUCTOR + when all of its elements are non-constant and have been split out. + + gcc/testsuite/ + 2010-04-07 Jie Zhang + + PR c++/42556 + * g++.dg/init/pr42556.C: New test. + + 2010-07-12 Yao Qi + + Merge from Sourcery G++ 4.4: + +=== modified file 'gcc/cp/typeck2.c' +--- old/gcc/cp/typeck2.c 2010-02-23 18:32:20 +0000 ++++ new/gcc/cp/typeck2.c 2010-07-30 14:05:57 +0000 +@@ -549,13 +549,15 @@ + expression to which INIT should be assigned. INIT is a CONSTRUCTOR. */ + + static void +-split_nonconstant_init_1 (tree dest, tree init) ++split_nonconstant_init_1 (tree dest, tree *initp) + { + unsigned HOST_WIDE_INT idx; ++ tree init = *initp; + tree field_index, value; + tree type = TREE_TYPE (dest); + tree inner_type = NULL; + bool array_type_p = false; ++ HOST_WIDE_INT num_type_elements, num_initialized_elements; + + switch (TREE_CODE (type)) + { +@@ -567,6 +569,7 @@ + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: ++ num_initialized_elements = 0; + FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx, + field_index, value) + { +@@ -589,12 +592,13 @@ + sub = build3 (COMPONENT_REF, inner_type, dest, field_index, + NULL_TREE); + +- split_nonconstant_init_1 (sub, value); ++ split_nonconstant_init_1 (sub, &value); + } + else if (!initializer_constant_valid_p (value, inner_type)) + { + tree code; + tree sub; ++ HOST_WIDE_INT inner_elements; + + /* FIXME: Ordered removal is O(1) so the whole function is + worst-case quadratic. This could be fixed using an aside +@@ -617,9 +621,22 @@ + code = build2 (INIT_EXPR, inner_type, sub, value); + code = build_stmt (input_location, EXPR_STMT, code); + add_stmt (code); ++ ++ inner_elements = count_type_elements (inner_type, true); ++ if (inner_elements < 0) ++ num_initialized_elements = -1; ++ else if (num_initialized_elements >= 0) ++ num_initialized_elements += inner_elements; + continue; + } + } ++ ++ num_type_elements = count_type_elements (type, true); ++ /* If all elements of the initializer are non-constant and ++ have been split out, we don't need the empty CONSTRUCTOR. */ ++ if (num_type_elements > 0 ++ && num_type_elements == num_initialized_elements) ++ *initp = NULL; + break; + + case VECTOR_TYPE: +@@ -655,7 +672,7 @@ + if (TREE_CODE (init) == CONSTRUCTOR) + { + code = push_stmt_list (); +- split_nonconstant_init_1 (dest, init); ++ split_nonconstant_init_1 (dest, &init); + code = pop_stmt_list (code); + DECL_INITIAL (dest) = init; + TREE_READONLY (dest) = 0; + +=== added file 'gcc/testsuite/g++.dg/init/pr42556.C' +--- old/gcc/testsuite/g++.dg/init/pr42556.C 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/g++.dg/init/pr42556.C 2010-07-30 14:05:57 +0000 +@@ -0,0 +1,10 @@ ++// { dg-do compile } ++// { dg-options "-fdump-tree-gimple" } ++ ++void foo (int a, int b, int c, int d) ++{ ++ int v[4] = {a, b, c, d}; ++} ++ ++// { dg-final { scan-tree-dump-not "v = {}" "gimple" } } ++// { dg-final { cleanup-tree-dump "gimple" } } + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch new file mode 100644 index 0000000000..da95fba790 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch @@ -0,0 +1,36 @@ + Backport from mainline (originally from Sourcery G++ 4.4): + + gcc/ + 2010-07-07 Jie Zhang + * genautomata.c (output_automata_list_min_issue_delay_code): + Correctly decompress min_issue_delay. + +2010-07-15 Jie Zhang + + Issue #8980 + + Backport from mainline (originally from Sourcery G++ 4.4): + +=== modified file 'gcc/genautomata.c' +--- old/gcc/genautomata.c 2009-11-25 10:55:54 +0000 ++++ new/gcc/genautomata.c 2010-07-30 14:21:58 +0000 +@@ -7865,12 +7865,15 @@ + { + fprintf (output_file, ") / %d];\n", + automaton->min_issue_delay_table_compression_factor); +- fprintf (output_file, " %s = (%s >> (8 - (", ++ fprintf (output_file, " %s = (%s >> (8 - ((", + TEMPORARY_VARIABLE_NAME, TEMPORARY_VARIABLE_NAME); + output_translate_vect_name (output_file, automaton); ++ fprintf (output_file, " [%s] + ", INTERNAL_INSN_CODE_NAME); ++ fprintf (output_file, "%s->", CHIP_PARAMETER_NAME); ++ output_chip_member_name (output_file, automaton); ++ fprintf (output_file, " * %d)", automaton->insn_equiv_classes_num); + fprintf +- (output_file, " [%s] %% %d + 1) * %d)) & %d;\n", +- INTERNAL_INSN_CODE_NAME, ++ (output_file, " %% %d + 1) * %d)) & %d;\n", + automaton->min_issue_delay_table_compression_factor, + 8 / automaton->min_issue_delay_table_compression_factor, + (1 << (8 / automaton->min_issue_delay_table_compression_factor)) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch new file mode 100644 index 0000000000..9f0c98e9c9 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch @@ -0,0 +1,714 @@ +2010-07-15 Sandra Loosemore + + Backport from mainline: + + 2010-06-09 Sandra Loosemore + + gcc/ + * tree-ssa-loop-ivopts.c (adjust_setup_cost): New function. + (get_computation_cost_at): Use it. + (determine_use_iv_cost_condition): Likewise. + (determine_iv_cost): Likewise. + + 2010-07-05 Sandra Loosemore + + PR middle-end/42505 + + gcc/ + * tree-ssa-loop-ivopts.c (determine_set_costs): Delete obsolete + comments about cost model. + (try_add_cand_for): Add second strategy for choosing initial set + based on original IVs, controlled by ORIGINALP argument. + (get_initial_solution): Add ORIGINALP argument. + (find_optimal_iv_set_1): New function, split from find_optimal_iv_set. + (find_optimal_iv_set): Try two different strategies for choosing + the IV set, and return the one with lower cost. + + gcc/testsuite/ + * gcc.target/arm/pr42505.c: New test case. + + 2010-07-10 Sandra Loosemore + + PR middle-end/42505 + + gcc/ + * tree-inline.c (estimate_num_insns): Refactor builtin complexity + lookup code into.... + * builtins.c (is_simple_builtin, is_inexpensive_builtin): ...these + new functions. + * tree.h (is_simple_builtin, is_inexpensive_builtin): Declare. + * cfgloopanal.c (target_clobbered_regs): Define. + (init_set_costs): Initialize target_clobbered_regs. + (estimate_reg_pressure_cost): Add call_p argument. When true, + adjust the number of available registers to exclude the + call-clobbered registers. + * cfgloop.h (target_clobbered_regs): Declare. + (estimate_reg_pressure_cost): Adjust declaration. + * tree-ssa-loop-ivopts.c (struct ivopts_data): Add body_includes_call. + (ivopts_global_cost_for_size): Pass it to estimate_reg_pressure_cost. + (determine_set_costs): Dump target_clobbered_regs. + (loop_body_includes_call): New function. + (tree_ssa_iv_optimize_loop): Use it to initialize new field. + * loop-invariant.c (gain_for_invariant): Adjust arguments to pass + call_p flag through. + (best_gain_for_invariant): Likewise. + (find_invariants_to_move): Likewise. + (move_single_loop_invariants): Likewise, using already-computed + has_call field. + + 2010-07-15 Jie Zhang + + Issue #8497, #8893 + +=== modified file 'gcc/builtins.c' +--- old/gcc/builtins.c 2010-04-13 12:47:11 +0000 ++++ new/gcc/builtins.c 2010-08-02 13:51:23 +0000 +@@ -13624,3 +13624,123 @@ + break; + } + } ++ ++/* Return true if DECL is a builtin that expands to a constant or similarly ++ simple code. */ ++bool ++is_simple_builtin (tree decl) ++{ ++ if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) ++ switch (DECL_FUNCTION_CODE (decl)) ++ { ++ /* Builtins that expand to constants. */ ++ case BUILT_IN_CONSTANT_P: ++ case BUILT_IN_EXPECT: ++ case BUILT_IN_OBJECT_SIZE: ++ case BUILT_IN_UNREACHABLE: ++ /* Simple register moves or loads from stack. */ ++ case BUILT_IN_RETURN_ADDRESS: ++ case BUILT_IN_EXTRACT_RETURN_ADDR: ++ case BUILT_IN_FROB_RETURN_ADDR: ++ case BUILT_IN_RETURN: ++ case BUILT_IN_AGGREGATE_INCOMING_ADDRESS: ++ case BUILT_IN_FRAME_ADDRESS: ++ case BUILT_IN_VA_END: ++ case BUILT_IN_STACK_SAVE: ++ case BUILT_IN_STACK_RESTORE: ++ /* Exception state returns or moves registers around. */ ++ case BUILT_IN_EH_FILTER: ++ case BUILT_IN_EH_POINTER: ++ case BUILT_IN_EH_COPY_VALUES: ++ return true; ++ ++ default: ++ return false; ++ } ++ ++ return false; ++} ++ ++/* Return true if DECL is a builtin that is not expensive, i.e., they are ++ most probably expanded inline into reasonably simple code. This is a ++ superset of is_simple_builtin. */ ++bool ++is_inexpensive_builtin (tree decl) ++{ ++ if (!decl) ++ return false; ++ else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD) ++ return true; ++ else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) ++ switch (DECL_FUNCTION_CODE (decl)) ++ { ++ case BUILT_IN_ABS: ++ case BUILT_IN_ALLOCA: ++ case BUILT_IN_BSWAP32: ++ case BUILT_IN_BSWAP64: ++ case BUILT_IN_CLZ: ++ case BUILT_IN_CLZIMAX: ++ case BUILT_IN_CLZL: ++ case BUILT_IN_CLZLL: ++ case BUILT_IN_CTZ: ++ case BUILT_IN_CTZIMAX: ++ case BUILT_IN_CTZL: ++ case BUILT_IN_CTZLL: ++ case BUILT_IN_FFS: ++ case BUILT_IN_FFSIMAX: ++ case BUILT_IN_FFSL: ++ case BUILT_IN_FFSLL: ++ case BUILT_IN_IMAXABS: ++ case BUILT_IN_FINITE: ++ case BUILT_IN_FINITEF: ++ case BUILT_IN_FINITEL: ++ case BUILT_IN_FINITED32: ++ case BUILT_IN_FINITED64: ++ case BUILT_IN_FINITED128: ++ case BUILT_IN_FPCLASSIFY: ++ case BUILT_IN_ISFINITE: ++ case BUILT_IN_ISINF_SIGN: ++ case BUILT_IN_ISINF: ++ case BUILT_IN_ISINFF: ++ case BUILT_IN_ISINFL: ++ case BUILT_IN_ISINFD32: ++ case BUILT_IN_ISINFD64: ++ case BUILT_IN_ISINFD128: ++ case BUILT_IN_ISNAN: ++ case BUILT_IN_ISNANF: ++ case BUILT_IN_ISNANL: ++ case BUILT_IN_ISNAND32: ++ case BUILT_IN_ISNAND64: ++ case BUILT_IN_ISNAND128: ++ case BUILT_IN_ISNORMAL: ++ case BUILT_IN_ISGREATER: ++ case BUILT_IN_ISGREATEREQUAL: ++ case BUILT_IN_ISLESS: ++ case BUILT_IN_ISLESSEQUAL: ++ case BUILT_IN_ISLESSGREATER: ++ case BUILT_IN_ISUNORDERED: ++ case BUILT_IN_VA_ARG_PACK: ++ case BUILT_IN_VA_ARG_PACK_LEN: ++ case BUILT_IN_VA_COPY: ++ case BUILT_IN_TRAP: ++ case BUILT_IN_SAVEREGS: ++ case BUILT_IN_POPCOUNTL: ++ case BUILT_IN_POPCOUNTLL: ++ case BUILT_IN_POPCOUNTIMAX: ++ case BUILT_IN_POPCOUNT: ++ case BUILT_IN_PARITYL: ++ case BUILT_IN_PARITYLL: ++ case BUILT_IN_PARITYIMAX: ++ case BUILT_IN_PARITY: ++ case BUILT_IN_LABS: ++ case BUILT_IN_LLABS: ++ case BUILT_IN_PREFETCH: ++ return true; ++ ++ default: ++ return is_simple_builtin (decl); ++ } ++ ++ return false; ++} ++ + +=== modified file 'gcc/cfgloop.h' +--- old/gcc/cfgloop.h 2009-11-25 10:55:54 +0000 ++++ new/gcc/cfgloop.h 2010-08-02 13:51:23 +0000 +@@ -622,13 +622,14 @@ + /* The properties of the target. */ + + extern unsigned target_avail_regs; ++extern unsigned target_clobbered_regs; + extern unsigned target_res_regs; + extern unsigned target_reg_cost [2]; + extern unsigned target_spill_cost [2]; + + /* Register pressure estimation for induction variable optimizations & loop + invariant motion. */ +-extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool); ++extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool, bool); + extern void init_set_costs (void); + + /* Loop optimizer initialization. */ + +=== modified file 'gcc/cfgloopanal.c' +--- old/gcc/cfgloopanal.c 2009-09-30 08:57:56 +0000 ++++ new/gcc/cfgloopanal.c 2010-08-02 13:51:23 +0000 +@@ -320,6 +320,8 @@ + /* The properties of the target. */ + + unsigned target_avail_regs; /* Number of available registers. */ ++unsigned target_clobbered_regs; /* Number of available registers that are ++ call-clobbered. */ + unsigned target_res_regs; /* Number of registers reserved for temporary + expressions. */ + unsigned target_reg_cost[2]; /* The cost for register when there still +@@ -342,10 +344,15 @@ + unsigned i; + + target_avail_regs = 0; ++ target_clobbered_regs = 0; + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i) + && !fixed_regs[i]) +- target_avail_regs++; ++ { ++ target_avail_regs++; ++ if (call_used_regs[i]) ++ target_clobbered_regs++; ++ } + + target_res_regs = 3; + +@@ -379,20 +386,29 @@ + + /* Estimates cost of increased register pressure caused by making N_NEW new + registers live around the loop. N_OLD is the number of registers live +- around the loop. */ ++ around the loop. If CALL_P is true, also take into account that ++ call-used registers may be clobbered in the loop body, reducing the ++ number of available registers before we spill. */ + + unsigned +-estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed) ++estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed, ++ bool call_p) + { + unsigned cost; + unsigned regs_needed = n_new + n_old; ++ unsigned available_regs = target_avail_regs; ++ ++ /* If there is a call in the loop body, the call-clobbered registers ++ are not available for loop invariants. */ ++ if (call_p) ++ available_regs = available_regs - target_clobbered_regs; + + /* If we have enough registers, we should use them and not restrict + the transformations unnecessarily. */ +- if (regs_needed + target_res_regs <= target_avail_regs) ++ if (regs_needed + target_res_regs <= available_regs) + return 0; + +- if (regs_needed <= target_avail_regs) ++ if (regs_needed <= available_regs) + /* If we are close to running out of registers, try to preserve + them. */ + cost = target_reg_cost [speed] * n_new; + +=== modified file 'gcc/loop-invariant.c' +--- old/gcc/loop-invariant.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/loop-invariant.c 2010-08-02 13:51:23 +0000 +@@ -1173,11 +1173,13 @@ + /* Calculates gain for eliminating invariant INV. REGS_USED is the number + of registers used in the loop, NEW_REGS is the number of new variables + already added due to the invariant motion. The number of registers needed +- for it is stored in *REGS_NEEDED. */ ++ for it is stored in *REGS_NEEDED. SPEED and CALL_P are flags passed ++ through to estimate_reg_pressure_cost. */ + + static int + gain_for_invariant (struct invariant *inv, unsigned *regs_needed, +- unsigned *new_regs, unsigned regs_used, bool speed) ++ unsigned *new_regs, unsigned regs_used, ++ bool speed, bool call_p) + { + int comp_cost, size_cost; + +@@ -1188,9 +1190,9 @@ + if (! flag_ira_loop_pressure) + { + size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0], +- regs_used, speed) ++ regs_used, speed, call_p) + - estimate_reg_pressure_cost (new_regs[0], +- regs_used, speed)); ++ regs_used, speed, call_p)); + } + else + { +@@ -1245,7 +1247,8 @@ + + static int + best_gain_for_invariant (struct invariant **best, unsigned *regs_needed, +- unsigned *new_regs, unsigned regs_used, bool speed) ++ unsigned *new_regs, unsigned regs_used, ++ bool speed, bool call_p) + { + struct invariant *inv; + int i, gain = 0, again; +@@ -1261,7 +1264,7 @@ + continue; + + again = gain_for_invariant (inv, aregs_needed, new_regs, regs_used, +- speed); ++ speed, call_p); + if (again > gain) + { + gain = again; +@@ -1314,7 +1317,7 @@ + /* Determines which invariants to move. */ + + static void +-find_invariants_to_move (bool speed) ++find_invariants_to_move (bool speed, bool call_p) + { + int gain; + unsigned i, regs_used, regs_needed[N_REG_CLASSES], new_regs[N_REG_CLASSES]; +@@ -1353,7 +1356,8 @@ + new_regs[ira_reg_class_cover[i]] = 0; + } + while ((gain = best_gain_for_invariant (&inv, regs_needed, +- new_regs, regs_used, speed)) > 0) ++ new_regs, regs_used, ++ speed, call_p)) > 0) + { + set_move_mark (inv->invno, gain); + if (! flag_ira_loop_pressure) +@@ -1554,7 +1558,8 @@ + init_inv_motion_data (); + + find_invariants (loop); +- find_invariants_to_move (optimize_loop_for_speed_p (loop)); ++ find_invariants_to_move (optimize_loop_for_speed_p (loop), ++ LOOP_DATA (loop)->has_call); + move_invariants (loop); + + free_inv_motion_data (); + +=== added file 'gcc/testsuite/gcc.target/arm/pr42505.c' +--- old/gcc/testsuite/gcc.target/arm/pr42505.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr42505.c 2010-08-02 13:51:23 +0000 +@@ -0,0 +1,23 @@ ++/* { dg-options "-mthumb -Os -march=armv5te" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ ++ ++struct A { ++ int f1; ++ int f2; ++}; ++ ++int func(int c); ++ ++/* This function should not need to spill anything to the stack. */ ++int test(struct A* src, struct A* dst, int count) ++{ ++ while (count--) { ++ if (!func(src->f2)) { ++ return 0; ++ } ++ *dst++ = *src++; ++ } ++ ++ return 1; ++} + +=== modified file 'gcc/tree-inline.c' +--- old/gcc/tree-inline.c 2010-03-18 20:07:13 +0000 ++++ new/gcc/tree-inline.c 2010-08-02 13:51:23 +0000 +@@ -3246,34 +3246,13 @@ + if (POINTER_TYPE_P (funtype)) + funtype = TREE_TYPE (funtype); + +- if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD) ++ if (is_simple_builtin (decl)) ++ return 0; ++ else if (is_inexpensive_builtin (decl)) + cost = weights->target_builtin_call_cost; + else + cost = weights->call_cost; + +- if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) +- switch (DECL_FUNCTION_CODE (decl)) +- { +- case BUILT_IN_CONSTANT_P: +- return 0; +- case BUILT_IN_EXPECT: +- return 0; +- +- /* Prefetch instruction is not expensive. */ +- case BUILT_IN_PREFETCH: +- cost = weights->target_builtin_call_cost; +- break; +- +- /* Exception state returns or moves registers around. */ +- case BUILT_IN_EH_FILTER: +- case BUILT_IN_EH_POINTER: +- case BUILT_IN_EH_COPY_VALUES: +- return 0; +- +- default: +- break; +- } +- + if (decl) + funtype = TREE_TYPE (decl); + + +=== modified file 'gcc/tree-ssa-loop-ivopts.c' +--- old/gcc/tree-ssa-loop-ivopts.c 2010-04-01 15:18:07 +0000 ++++ new/gcc/tree-ssa-loop-ivopts.c 2010-08-02 13:51:23 +0000 +@@ -257,6 +257,9 @@ + + /* Are we optimizing for speed? */ + bool speed; ++ ++ /* Whether the loop body includes any function calls. */ ++ bool body_includes_call; + }; + + /* An assignment of iv candidates to uses. */ +@@ -2926,6 +2929,20 @@ + return get_computation_at (loop, use, cand, use->stmt); + } + ++/* Adjust the cost COST for being in loop setup rather than loop body. ++ If we're optimizing for space, the loop setup overhead is constant; ++ if we're optimizing for speed, amortize it over the per-iteration cost. */ ++static unsigned ++adjust_setup_cost (struct ivopts_data *data, unsigned cost) ++{ ++ if (cost == INFTY) ++ return cost; ++ else if (optimize_loop_for_speed_p (data->current_loop)) ++ return cost / AVG_LOOP_NITER (data->current_loop); ++ else ++ return cost; ++} ++ + /* Returns cost of addition in MODE. */ + + static unsigned +@@ -3838,8 +3855,8 @@ + /* Symbol + offset should be compile-time computable so consider that they + are added once to the variable, if present. */ + if (var_present && (symbol_present || offset)) +- cost.cost += add_cost (TYPE_MODE (ctype), speed) +- / AVG_LOOP_NITER (data->current_loop); ++ cost.cost += adjust_setup_cost (data, ++ add_cost (TYPE_MODE (ctype), speed)); + + /* Having offset does not affect runtime cost in case it is added to + symbol, but it increases complexity. */ +@@ -4104,7 +4121,7 @@ + elim_cost = force_var_cost (data, bound, &depends_on_elim); + /* The bound is a loop invariant, so it will be only computed + once. */ +- elim_cost.cost /= AVG_LOOP_NITER (data->current_loop); ++ elim_cost.cost = adjust_setup_cost (data, elim_cost.cost); + } + else + elim_cost = infinite_cost; +@@ -4351,7 +4368,7 @@ + cost_base = force_var_cost (data, base, NULL); + cost_step = add_cost (TYPE_MODE (TREE_TYPE (base)), data->speed); + +- cost = cost_step + cost_base.cost / AVG_LOOP_NITER (current_loop); ++ cost = cost_step + adjust_setup_cost (data, cost_base.cost); + + /* Prefer the original ivs unless we may gain something by replacing it. + The reason is to make debugging simpler; so this is not relevant for +@@ -4404,7 +4421,8 @@ + { + /* We add size to the cost, so that we prefer eliminating ivs + if possible. */ +- return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed); ++ return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed, ++ data->body_includes_call); + } + + /* For each size of the induction variable set determine the penalty. */ +@@ -4419,30 +4437,11 @@ + struct loop *loop = data->current_loop; + bitmap_iterator bi; + +- /* We use the following model (definitely improvable, especially the +- cost function -- TODO): +- +- We estimate the number of registers available (using MD data), name it A. +- +- We estimate the number of registers used by the loop, name it U. This +- number is obtained as the number of loop phi nodes (not counting virtual +- registers and bivs) + the number of variables from outside of the loop. +- +- We set a reserve R (free regs that are used for temporary computations, +- etc.). For now the reserve is a constant 3. +- +- Let I be the number of induction variables. +- +- -- if U + I + R <= A, the cost is I * SMALL_COST (just not to encourage +- make a lot of ivs without a reason). +- -- if A - R < U + I <= A, the cost is I * PRES_COST +- -- if U + I > A, the cost is I * PRES_COST and +- number of uses * SPILL_COST * (U + I - A) / (U + I) is added. */ +- + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Global costs:\n"); + fprintf (dump_file, " target_avail_regs %d\n", target_avail_regs); ++ fprintf (dump_file, " target_clobbered_regs %d\n", target_clobbered_regs); + fprintf (dump_file, " target_reg_cost %d\n", target_reg_cost[data->speed]); + fprintf (dump_file, " target_spill_cost %d\n", target_spill_cost[data->speed]); + } +@@ -5062,11 +5061,13 @@ + } + + /* Tries to extend the sets IVS in the best possible way in order +- to express the USE. */ ++ to express the USE. If ORIGINALP is true, prefer candidates from ++ the original set of IVs, otherwise favor important candidates not ++ based on any memory object. */ + + static bool + try_add_cand_for (struct ivopts_data *data, struct iv_ca *ivs, +- struct iv_use *use) ++ struct iv_use *use, bool originalp) + { + comp_cost best_cost, act_cost; + unsigned i; +@@ -5085,7 +5086,8 @@ + iv_ca_set_no_cp (data, ivs, use); + } + +- /* First try important candidates not based on any memory object. Only if ++ /* If ORIGINALP is true, try to find the original IV for the use. Otherwise ++ first try important candidates not based on any memory object. Only if + this fails, try the specific ones. Rationale -- in loops with many + variables the best choice often is to use just one generic biv. If we + added here many ivs specific to the uses, the optimization algorithm later +@@ -5097,7 +5099,10 @@ + { + cand = iv_cand (data, i); + +- if (cand->iv->base_object != NULL_TREE) ++ if (originalp && cand->pos !=IP_ORIGINAL) ++ continue; ++ ++ if (!originalp && cand->iv->base_object != NULL_TREE) + continue; + + if (iv_ca_cand_used_p (ivs, cand)) +@@ -5133,8 +5138,13 @@ + continue; + + /* Already tried this. */ +- if (cand->important && cand->iv->base_object == NULL_TREE) +- continue; ++ if (cand->important) ++ { ++ if (originalp && cand->pos == IP_ORIGINAL) ++ continue; ++ if (!originalp && cand->iv->base_object == NULL_TREE) ++ continue; ++ } + + if (iv_ca_cand_used_p (ivs, cand)) + continue; +@@ -5168,13 +5178,13 @@ + /* Finds an initial assignment of candidates to uses. */ + + static struct iv_ca * +-get_initial_solution (struct ivopts_data *data) ++get_initial_solution (struct ivopts_data *data, bool originalp) + { + struct iv_ca *ivs = iv_ca_new (data); + unsigned i; + + for (i = 0; i < n_iv_uses (data); i++) +- if (!try_add_cand_for (data, ivs, iv_use (data, i))) ++ if (!try_add_cand_for (data, ivs, iv_use (data, i), originalp)) + { + iv_ca_free (&ivs); + return NULL; +@@ -5246,14 +5256,12 @@ + solution and remove the unused ivs while this improves the cost. */ + + static struct iv_ca * +-find_optimal_iv_set (struct ivopts_data *data) ++find_optimal_iv_set_1 (struct ivopts_data *data, bool originalp) + { +- unsigned i; + struct iv_ca *set; +- struct iv_use *use; + + /* Get the initial solution. */ +- set = get_initial_solution (data); ++ set = get_initial_solution (data, originalp); + if (!set) + { + if (dump_file && (dump_flags & TDF_DETAILS)) +@@ -5276,11 +5284,46 @@ + } + } + ++ return set; ++} ++ ++static struct iv_ca * ++find_optimal_iv_set (struct ivopts_data *data) ++{ ++ unsigned i; ++ struct iv_ca *set, *origset; ++ struct iv_use *use; ++ comp_cost cost, origcost; ++ ++ /* Determine the cost based on a strategy that starts with original IVs, ++ and try again using a strategy that prefers candidates not based ++ on any IVs. */ ++ origset = find_optimal_iv_set_1 (data, true); ++ set = find_optimal_iv_set_1 (data, false); ++ ++ if (!origset && !set) ++ return NULL; ++ ++ origcost = origset ? iv_ca_cost (origset) : infinite_cost; ++ cost = set ? iv_ca_cost (set) : infinite_cost; ++ + if (dump_file && (dump_flags & TDF_DETAILS)) + { +- comp_cost cost = iv_ca_cost (set); +- fprintf (dump_file, "Final cost %d (complexity %d)\n\n", cost.cost, cost.complexity); +- } ++ fprintf (dump_file, "Original cost %d (complexity %d)\n\n", ++ origcost.cost, origcost.complexity); ++ fprintf (dump_file, "Final cost %d (complexity %d)\n\n", ++ cost.cost, cost.complexity); ++ } ++ ++ /* Choose the one with the best cost. */ ++ if (compare_costs (origcost, cost) <= 0) ++ { ++ if (set) ++ iv_ca_free (&set); ++ set = origset; ++ } ++ else if (origset) ++ iv_ca_free (&origset); + + for (i = 0; i < n_iv_uses (data); i++) + { +@@ -5768,6 +5811,25 @@ + VEC_free (iv_cand_p, heap, data->iv_candidates); + } + ++/* Returns true if the loop body BODY includes any function calls. */ ++ ++static bool ++loop_body_includes_call (basic_block *body, unsigned num_nodes) ++{ ++ gimple_stmt_iterator gsi; ++ unsigned i; ++ ++ for (i = 0; i < num_nodes; i++) ++ for (gsi = gsi_start_bb (body[i]); !gsi_end_p (gsi); gsi_next (&gsi)) ++ { ++ gimple stmt = gsi_stmt (gsi); ++ if (is_gimple_call (stmt) ++ && !is_inexpensive_builtin (gimple_call_fndecl (stmt))) ++ return true; ++ } ++ return false; ++} ++ + /* Optimizes the LOOP. Returns true if anything changed. */ + + static bool +@@ -5799,6 +5861,7 @@ + } + + body = get_loop_body (loop); ++ data->body_includes_call = loop_body_includes_call (body, loop->num_nodes); + renumber_gimple_stmt_uids_in_blocks (body, loop->num_nodes); + free (body); + + +=== modified file 'gcc/tree.h' +--- old/gcc/tree.h 2010-04-02 18:54:46 +0000 ++++ new/gcc/tree.h 2010-08-02 13:51:23 +0000 +@@ -4962,6 +4962,8 @@ + extern bool merge_ranges (int *, tree *, tree *, int, tree, tree, int, + tree, tree); + extern void set_builtin_user_assembler_name (tree decl, const char *asmspec); ++extern bool is_simple_builtin (tree); ++extern bool is_inexpensive_builtin (tree); + + /* In convert.c */ + extern tree strip_float_extensions (tree); + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch new file mode 100644 index 0000000000..eadce6ec6c --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch @@ -0,0 +1,37 @@ +2010-07-15 Yao Qi + + Merge from Sourcery G++ 4.4: + + 2010-02-25 Maxim Kuvyrkov + + gcc/ + * tree.c (initializer_zerop): Handle STRING_CST. + + 2010-07-15 Sandra Loosemore + + Backport from mainline: + +=== modified file 'gcc/tree.c' +--- old/gcc/tree.c 2010-04-01 15:18:07 +0000 ++++ new/gcc/tree.c 2010-08-02 16:32:37 +0000 +@@ -9335,6 +9335,19 @@ + return true; + } + ++ case STRING_CST: ++ { ++ int i; ++ ++ /* We need to loop through all elements to handle cases like ++ "\0" and "\0foobar". */ ++ for (i = 0; i < TREE_STRING_LENGTH (init); ++i) ++ if (TREE_STRING_POINTER (init)[i] != '\0') ++ return false; ++ ++ return true; ++ } ++ + default: + return false; + } + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch new file mode 100644 index 0000000000..216fcac723 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch @@ -0,0 +1,433 @@ +2010-07-16 Jie Zhang + + Issue #7688 + + Backport from mainline: + + gcc/ + 2010-07-12 Jie Zhang + * postreload.c (reg_symbol_ref[]): New. + (move2add_use_add2_insn): New. + (move2add_use_add3_insn): New. + (reload_cse_move2add): Handle SYMBOL + OFFSET case. + (move2add_note_store): Likewise. + + 2010-07-15 Yao Qi + + Merge from Sourcery G++ 4.4: + +=== modified file 'gcc/postreload.c' +--- old/gcc/postreload.c 2010-03-16 10:50:42 +0000 ++++ new/gcc/postreload.c 2010-08-02 16:55:34 +0000 +@@ -1160,17 +1160,19 @@ + information about register contents we have would be costly, so we + use move2add_last_label_luid to note where the label is and then + later disable any optimization that would cross it. +- reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if +- reg_set_luid[n] is greater than move2add_last_label_luid. */ ++ reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] ++ are only valid if reg_set_luid[n] is greater than ++ move2add_last_label_luid. */ + static int reg_set_luid[FIRST_PSEUDO_REGISTER]; + + /* If reg_base_reg[n] is negative, register n has been set to +- reg_offset[n] in mode reg_mode[n] . ++ reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. + If reg_base_reg[n] is non-negative, register n has been set to the + sum of reg_offset[n] and the value of register reg_base_reg[n] + before reg_set_luid[n], calculated in mode reg_mode[n] . */ + static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; + static int reg_base_reg[FIRST_PSEUDO_REGISTER]; ++static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; + static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; + + /* move2add_luid is linearly increased while scanning the instructions +@@ -1190,6 +1192,151 @@ + && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \ + GET_MODE_BITSIZE (INMODE)))) + ++/* This function is called with INSN that sets REG to (SYM + OFF), ++ while REG is known to already have value (SYM + offset). ++ This function tries to change INSN into an add instruction ++ (set (REG) (plus (REG) (OFF - offset))) using the known value. ++ It also updates the information about REG's known value. */ ++ ++static void ++move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) ++{ ++ rtx pat = PATTERN (insn); ++ rtx src = SET_SRC (pat); ++ int regno = REGNO (reg); ++ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], ++ GET_MODE (reg)); ++ bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); ++ ++ /* (set (reg) (plus (reg) (const_int 0))) is not canonical; ++ use (set (reg) (reg)) instead. ++ We don't delete this insn, nor do we convert it into a ++ note, to avoid losing register notes or the return ++ value flag. jump2 already knows how to get rid of ++ no-op moves. */ ++ if (new_src == const0_rtx) ++ { ++ /* If the constants are different, this is a ++ truncation, that, if turned into (set (reg) ++ (reg)), would be discarded. Maybe we should ++ try a truncMN pattern? */ ++ if (INTVAL (off) == reg_offset [regno]) ++ validate_change (insn, &SET_SRC (pat), reg, 0); ++ } ++ else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) ++ && have_add2_insn (reg, new_src)) ++ { ++ rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); ++ validate_change (insn, &SET_SRC (pat), tem, 0); ++ } ++ else if (sym == NULL_RTX && GET_MODE (reg) != BImode) ++ { ++ enum machine_mode narrow_mode; ++ for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); ++ narrow_mode != VOIDmode ++ && narrow_mode != GET_MODE (reg); ++ narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) ++ { ++ if (have_insn_for (STRICT_LOW_PART, narrow_mode) ++ && ((reg_offset[regno] ++ & ~GET_MODE_MASK (narrow_mode)) ++ == (INTVAL (off) ++ & ~GET_MODE_MASK (narrow_mode)))) ++ { ++ rtx narrow_reg = gen_rtx_REG (narrow_mode, ++ REGNO (reg)); ++ rtx narrow_src = gen_int_mode (INTVAL (off), ++ narrow_mode); ++ rtx new_set = ++ gen_rtx_SET (VOIDmode, ++ gen_rtx_STRICT_LOW_PART (VOIDmode, ++ narrow_reg), ++ narrow_src); ++ if (validate_change (insn, &PATTERN (insn), ++ new_set, 0)) ++ break; ++ } ++ } ++ } ++ reg_set_luid[regno] = move2add_luid; ++ reg_base_reg[regno] = -1; ++ reg_mode[regno] = GET_MODE (reg); ++ reg_symbol_ref[regno] = sym; ++ reg_offset[regno] = INTVAL (off); ++} ++ ++ ++/* This function is called with INSN that sets REG to (SYM + OFF), ++ but REG doesn't have known value (SYM + offset). This function ++ tries to find another register which is known to already have ++ value (SYM + offset) and change INSN into an add instruction ++ (set (REG) (plus (the found register) (OFF - offset))) if such ++ a register is found. It also updates the information about ++ REG's known value. */ ++ ++static void ++move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) ++{ ++ rtx pat = PATTERN (insn); ++ rtx src = SET_SRC (pat); ++ int regno = REGNO (reg); ++ int min_cost = INT_MAX; ++ int min_regno; ++ bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); ++ int i; ++ ++ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ++ if (reg_set_luid[i] > move2add_last_label_luid ++ && reg_mode[i] == GET_MODE (reg) ++ && reg_base_reg[i] < 0 ++ && reg_symbol_ref[i] != NULL_RTX ++ && rtx_equal_p (sym, reg_symbol_ref[i])) ++ { ++ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i], ++ GET_MODE (reg)); ++ /* (set (reg) (plus (reg) (const_int 0))) is not canonical; ++ use (set (reg) (reg)) instead. ++ We don't delete this insn, nor do we convert it into a ++ note, to avoid losing register notes or the return ++ value flag. jump2 already knows how to get rid of ++ no-op moves. */ ++ if (new_src == const0_rtx) ++ { ++ min_cost = 0; ++ min_regno = i; ++ break; ++ } ++ else ++ { ++ int cost = rtx_cost (new_src, PLUS, speed); ++ if (cost < min_cost) ++ { ++ min_cost = cost; ++ min_regno = i; ++ } ++ } ++ } ++ ++ if (min_cost < rtx_cost (src, SET, speed)) ++ { ++ rtx tem; ++ ++ tem = gen_rtx_REG (GET_MODE (reg), min_regno); ++ if (i != min_regno) ++ { ++ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno], ++ GET_MODE (reg)); ++ tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); ++ } ++ validate_change (insn, &SET_SRC (pat), tem, 0); ++ } ++ reg_set_luid[regno] = move2add_luid; ++ reg_base_reg[regno] = -1; ++ reg_mode[regno] = GET_MODE (reg); ++ reg_symbol_ref[regno] = sym; ++ reg_offset[regno] = INTVAL (off); ++} ++ + static void + reload_cse_move2add (rtx first) + { +@@ -1197,7 +1344,13 @@ + rtx insn; + + for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) +- reg_set_luid[i] = 0; ++ { ++ reg_set_luid[i] = 0; ++ reg_offset[i] = 0; ++ reg_base_reg[i] = 0; ++ reg_symbol_ref[i] = NULL_RTX; ++ reg_mode[i] = VOIDmode; ++ } + + move2add_last_label_luid = 0; + move2add_luid = 2; +@@ -1245,65 +1398,11 @@ + (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) + */ + +- if (CONST_INT_P (src) && reg_base_reg[regno] < 0) ++ if (CONST_INT_P (src) ++ && reg_base_reg[regno] < 0 ++ && reg_symbol_ref[regno] == NULL_RTX) + { +- rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno], +- GET_MODE (reg)); +- bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); +- +- /* (set (reg) (plus (reg) (const_int 0))) is not canonical; +- use (set (reg) (reg)) instead. +- We don't delete this insn, nor do we convert it into a +- note, to avoid losing register notes or the return +- value flag. jump2 already knows how to get rid of +- no-op moves. */ +- if (new_src == const0_rtx) +- { +- /* If the constants are different, this is a +- truncation, that, if turned into (set (reg) +- (reg)), would be discarded. Maybe we should +- try a truncMN pattern? */ +- if (INTVAL (src) == reg_offset [regno]) +- validate_change (insn, &SET_SRC (pat), reg, 0); +- } +- else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) +- && have_add2_insn (reg, new_src)) +- { +- rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); +- validate_change (insn, &SET_SRC (pat), tem, 0); +- } +- else if (GET_MODE (reg) != BImode) +- { +- enum machine_mode narrow_mode; +- for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); +- narrow_mode != VOIDmode +- && narrow_mode != GET_MODE (reg); +- narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) +- { +- if (have_insn_for (STRICT_LOW_PART, narrow_mode) +- && ((reg_offset[regno] +- & ~GET_MODE_MASK (narrow_mode)) +- == (INTVAL (src) +- & ~GET_MODE_MASK (narrow_mode)))) +- { +- rtx narrow_reg = gen_rtx_REG (narrow_mode, +- REGNO (reg)); +- rtx narrow_src = gen_int_mode (INTVAL (src), +- narrow_mode); +- rtx new_set = +- gen_rtx_SET (VOIDmode, +- gen_rtx_STRICT_LOW_PART (VOIDmode, +- narrow_reg), +- narrow_src); +- if (validate_change (insn, &PATTERN (insn), +- new_set, 0)) +- break; +- } +- } +- } +- reg_set_luid[regno] = move2add_luid; +- reg_mode[regno] = GET_MODE (reg); +- reg_offset[regno] = INTVAL (src); ++ move2add_use_add2_insn (reg, NULL_RTX, src, insn); + continue; + } + +@@ -1373,6 +1472,51 @@ + } + } + } ++ ++ /* Try to transform ++ (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) ++ ... ++ (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) ++ to ++ (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) ++ ... ++ (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ ++ if ((GET_CODE (src) == SYMBOL_REF ++ || (GET_CODE (src) == CONST ++ && GET_CODE (XEXP (src, 0)) == PLUS ++ && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF ++ && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) ++ && dbg_cnt (cse2_move2add)) ++ { ++ rtx sym, off; ++ ++ if (GET_CODE (src) == SYMBOL_REF) ++ { ++ sym = src; ++ off = const0_rtx; ++ } ++ else ++ { ++ sym = XEXP (XEXP (src, 0), 0); ++ off = XEXP (XEXP (src, 0), 1); ++ } ++ ++ /* If the reg already contains the value which is sum of ++ sym and some constant value, we can use an add2 insn. */ ++ if (reg_set_luid[regno] > move2add_last_label_luid ++ && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]) ++ && reg_base_reg[regno] < 0 ++ && reg_symbol_ref[regno] != NULL_RTX ++ && rtx_equal_p (sym, reg_symbol_ref[regno])) ++ move2add_use_add2_insn (reg, sym, off, insn); ++ ++ /* Otherwise, we have to find a register whose value is sum ++ of sym and some constant value. */ ++ else ++ move2add_use_add3_insn (reg, sym, off, insn); ++ ++ continue; ++ } + } + + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) +@@ -1386,7 +1530,7 @@ + reg_set_luid[regno] = 0; + } + } +- note_stores (PATTERN (insn), move2add_note_store, NULL); ++ note_stores (PATTERN (insn), move2add_note_store, insn); + + /* If INSN is a conditional branch, we try to extract an + implicit set out of it. */ +@@ -1408,7 +1552,7 @@ + { + rtx implicit_set = + gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1)); +- move2add_note_store (SET_DEST (implicit_set), implicit_set, 0); ++ move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); + } + } + +@@ -1426,13 +1570,15 @@ + } + } + +-/* SET is a SET or CLOBBER that sets DST. ++/* SET is a SET or CLOBBER that sets DST. DATA is the insn which ++ contains SET. + Update reg_set_luid, reg_offset and reg_base_reg accordingly. + Called from reload_cse_move2add via note_stores. */ + + static void +-move2add_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) ++move2add_note_store (rtx dst, const_rtx set, void *data) + { ++ rtx insn = (rtx) data; + unsigned int regno = 0; + unsigned int nregs = 0; + unsigned int i; +@@ -1466,6 +1612,38 @@ + nregs = hard_regno_nregs[regno][mode]; + + if (SCALAR_INT_MODE_P (GET_MODE (dst)) ++ && nregs == 1 && GET_CODE (set) == SET) ++ { ++ rtx note, sym = NULL_RTX; ++ HOST_WIDE_INT off; ++ ++ note = find_reg_equal_equiv_note (insn); ++ if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) ++ { ++ sym = XEXP (note, 0); ++ off = 0; ++ } ++ else if (note && GET_CODE (XEXP (note, 0)) == CONST ++ && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS ++ && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF ++ && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) ++ { ++ sym = XEXP (XEXP (XEXP (note, 0), 0), 0); ++ off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1)); ++ } ++ ++ if (sym != NULL_RTX) ++ { ++ reg_base_reg[regno] = -1; ++ reg_symbol_ref[regno] = sym; ++ reg_offset[regno] = off; ++ reg_mode[regno] = mode; ++ reg_set_luid[regno] = move2add_luid; ++ return; ++ } ++ } ++ ++ if (SCALAR_INT_MODE_P (GET_MODE (dst)) + && nregs == 1 && GET_CODE (set) == SET + && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT + && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) +@@ -1525,6 +1703,7 @@ + case CONST_INT: + /* Start tracking the register as a constant. */ + reg_base_reg[regno] = -1; ++ reg_symbol_ref[regno] = NULL_RTX; + reg_offset[regno] = INTVAL (SET_SRC (set)); + /* We assign the same luid to all registers set to constants. */ + reg_set_luid[regno] = move2add_last_label_luid + 1; +@@ -1545,6 +1724,7 @@ + if (reg_set_luid[base_regno] <= move2add_last_label_luid) + { + reg_base_reg[base_regno] = base_regno; ++ reg_symbol_ref[base_regno] = NULL_RTX; + reg_offset[base_regno] = 0; + reg_set_luid[base_regno] = move2add_luid; + reg_mode[base_regno] = mode; +@@ -1558,6 +1738,7 @@ + /* Copy base information from our base register. */ + reg_set_luid[regno] = reg_set_luid[base_regno]; + reg_base_reg[regno] = reg_base_reg[base_regno]; ++ reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; + + /* Compute the sum of the offsets or constants. */ + reg_offset[regno] = trunc_int_for_mode (offset + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch new file mode 100644 index 0000000000..3d5dd5f9ab --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch @@ -0,0 +1,57 @@ +2010-08-03 Chung-Lin Tang + + Backport from mainline: + + gcc/ + 2010-07-28 Chung-Lin Tang + * config/arm/arm.c (arm_pcs_default): Remove static. + * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_PCS or + __ARM_PCS_VFP to indicate soft/hard-float calling convention. + (arm_pcs_default): Declare. + + 2010-07-16 Jie Zhang + + Issue #7688 + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-02 13:42:24 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-03 13:55:46 +0000 +@@ -704,7 +704,7 @@ + /* The maximum number of insns to be used when loading a constant. */ + static int arm_constant_limit = 3; + +-static enum arm_pcs arm_pcs_default; ++enum arm_pcs arm_pcs_default; + + /* For an explanation of these variables, see final_prescan_insn below. */ + int arm_ccfsm_state; + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-07-29 16:58:56 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-03 10:40:56 +0000 +@@ -94,7 +94,13 @@ + if (arm_arch_iwmmxt) \ + builtin_define ("__IWMMXT__"); \ + if (TARGET_AAPCS_BASED) \ +- builtin_define ("__ARM_EABI__"); \ ++ { \ ++ if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ ++ builtin_define ("__ARM_PCS_VFP"); \ ++ else if (arm_pcs_default == ARM_PCS_AAPCS) \ ++ builtin_define ("__ARM_PCS"); \ ++ builtin_define ("__ARM_EABI__"); \ ++ } \ + } while (0) + + /* The various ARM cores. */ +@@ -1648,6 +1654,9 @@ + ARM_PCS_UNKNOWN + }; + ++/* Default procedure calling standard of current compilation unit. */ ++extern enum arm_pcs arm_pcs_default; ++ + /* A C type for declaring a variable that is used as the first argument of + `FUNCTION_ARG' and other related values. */ + typedef struct + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch new file mode 100644 index 0000000000..c7f92b6fcb --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch @@ -0,0 +1,76 @@ +2010-07-20 Yao Qi + + Merge from Sourcery G++ 4.4: + 2010-06-07 Kazu Hirata + + Issue #8535 + + Backport from mainline: + gcc/ + 2010-06-07 Kazu Hirata + PR rtl-optimization/44404 + * auto-inc-dec.c (find_inc): Use reg_overlap_mentioned_p instead + of count_occurrences to see if it's safe to modify mem_insn.insn. + + gcc/testsuite/ + 2010-06-07 Kazu Hirata + PR rtl-optimization/44404 + * gcc.dg/pr44404.c: New. + + 2010-08-03 Chung-Lin Tang + + Backport from mainline: + +=== modified file 'gcc/auto-inc-dec.c' +--- old/gcc/auto-inc-dec.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/auto-inc-dec.c 2010-08-05 11:30:21 +0000 +@@ -1068,7 +1068,7 @@ + /* For the post_add to work, the result_reg of the inc must not be + used in the mem insn since this will become the new index + register. */ +- if (count_occurrences (PATTERN (mem_insn.insn), inc_insn.reg_res, 1) != 0) ++ if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn))) + { + if (dump_file) + fprintf (dump_file, "base reg replacement failure.\n"); + +=== added file 'gcc/testsuite/gcc.dg/pr44404.c' +--- old/gcc/testsuite/gcc.dg/pr44404.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/pr44404.c 2010-08-05 11:30:21 +0000 +@@ -0,0 +1,35 @@ ++/* PR rtl-optimization/44404 ++ foo() used to be miscompiled on ARM due to a bug in auto-inc-dec.c, ++ which resulted in "strb r1, [r1], #-36". */ ++ ++/* { dg-do run } */ ++/* { dg-options "-O2 -fno-unroll-loops" } */ ++ ++extern char *strcpy (char *, const char *); ++extern int strcmp (const char*, const char*); ++extern void abort (void); ++ ++char buf[128]; ++ ++void __attribute__((noinline)) ++bar (int a, const char *p) ++{ ++ if (strcmp (p, "0123456789abcdefghijklmnopqrstuvwxyz") != 0) ++ abort (); ++} ++ ++void __attribute__((noinline)) ++foo (int a) ++{ ++ if (a) ++ bar (0, buf); ++ strcpy (buf, "0123456789abcdefghijklmnopqrstuvwxyz"); ++ bar (0, buf); ++} ++ ++int ++main (void) ++{ ++ foo (0); ++ return 0; ++} + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch new file mode 100644 index 0000000000..ad4943a0a9 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch @@ -0,0 +1,118 @@ +2010-07-24 Jie Zhang + + Issue #9079 + + Backport from mainline: + + gcc/ + 2010-07-23 Jie Zhang + PR target/44290 + * attribs.c (decl_attributes): Insert "noinline" and "noclone" + if "naked". + * tree-sra.c (ipa_sra_preliminary_function_checks): Return + false if ! tree_versionable_function_p. + + gcc/testsuite/ + 2010-07-23 Jie Zhang + PR target/44290 + * gcc.dg/pr44290-1.c: New test. + * gcc.dg/pr44290-2.c: New test. + + 2010-07-22 Maxim Kuvyrkov + + Backport from FSF GCC 4.5 branch to fix PR45015: + +=== modified file 'gcc/attribs.c' +--- old/gcc/attribs.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/attribs.c 2010-08-05 11:39:36 +0000 +@@ -278,6 +278,19 @@ + TREE_VALUE (cur_attr) = chainon (opts, TREE_VALUE (cur_attr)); + } + ++ /* A "naked" function attribute implies "noinline" and "noclone" for ++ those targets that support it. */ ++ if (TREE_CODE (*node) == FUNCTION_DECL ++ && lookup_attribute_spec (get_identifier ("naked")) ++ && lookup_attribute ("naked", attributes) != NULL) ++ { ++ if (lookup_attribute ("noinline", attributes) == NULL) ++ attributes = tree_cons (get_identifier ("noinline"), NULL, attributes); ++ ++ if (lookup_attribute ("noclone", attributes) == NULL) ++ attributes = tree_cons (get_identifier ("noclone"), NULL, attributes); ++ } ++ + targetm.insert_attributes (*node, &attributes); + + for (a = attributes; a; a = TREE_CHAIN (a)) + +=== added file 'gcc/testsuite/gcc.dg/pr44290-1.c' +--- old/gcc/testsuite/gcc.dg/pr44290-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/pr44290-1.c 2010-08-05 11:39:36 +0000 +@@ -0,0 +1,18 @@ ++/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++static void __attribute__((naked)) ++foo(void *from, void *to) ++{ ++ asm volatile("dummy"::"r"(from), "r"(to)); ++} ++ ++unsigned int fie[2]; ++ ++void fum(void *to) ++{ ++ foo(fie, to); ++} ++ ++/* { dg-final { scan-tree-dump "foo \\\(void \\\* from, void \\\* to\\\)" "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ + +=== added file 'gcc/testsuite/gcc.dg/pr44290-2.c' +--- old/gcc/testsuite/gcc.dg/pr44290-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/pr44290-2.c 2010-08-05 11:39:36 +0000 +@@ -0,0 +1,24 @@ ++/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++static unsigned long __attribute__((naked)) ++foo (unsigned long base) ++{ ++ asm volatile ("dummy"); ++} ++unsigned long ++bar (void) ++{ ++ static int start, set; ++ ++ if (!set) ++ { ++ set = 1; ++ start = foo (0); ++ } ++ ++ return foo (start); ++} ++ ++/* { dg-final { scan-tree-dump "foo \\\(long unsigned int base\\\)" "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ + +=== modified file 'gcc/tree-sra.c' +--- old/gcc/tree-sra.c 2010-03-17 12:02:35 +0000 ++++ new/gcc/tree-sra.c 2010-08-05 11:39:36 +0000 +@@ -4096,6 +4096,13 @@ + static bool + ipa_sra_preliminary_function_checks (struct cgraph_node *node) + { ++ if (!tree_versionable_function_p (current_function_decl)) ++ { ++ if (dump_file) ++ fprintf (dump_file, "Function isn't allowed to be versioned.\n"); ++ return false; ++ } ++ + if (!cgraph_node_can_be_local_p (node)) + { + if (dump_file) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch new file mode 100644 index 0000000000..a649c9542a --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch @@ -0,0 +1,197 @@ +2010-07-24 Sandra Loosemore + + Backport from mainline: + + 2010-04-10 Wei Guozhi + + PR target/42601 + gcc/ + * config/arm/arm.c (arm_pic_static_addr): New function. + (legitimize_pic_address): Call arm_pic_static_addr when it detects + a static symbol. + (arm_output_addr_const_extra): Output expression for new pattern. + * config/arm/arm.md (UNSPEC_SYMBOL_OFFSET): New unspec symbol. + + 2010-07-22 Sandra Loosemore + + PR tree-optimization/39839 + gcc/testsuite/ + * gcc.target/arm/pr39839.c: New test case. + + 2010-07-24 Jie Zhang + + Issue #9079 + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-03 13:55:46 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-05 12:06:40 +0000 +@@ -225,6 +225,7 @@ + static void arm_asm_trampoline_template (FILE *); + static void arm_trampoline_init (rtx, tree, rtx); + static rtx arm_trampoline_adjust_address (rtx); ++static rtx arm_pic_static_addr (rtx orig, rtx reg); + + + /* Table of machine attributes. */ +@@ -4986,29 +4987,16 @@ + { + rtx pic_ref, address; + rtx insn; +- int subregs = 0; +- +- /* If this function doesn't have a pic register, create one now. */ +- require_pic_register (); + + if (reg == 0) + { + gcc_assert (can_create_pseudo_p ()); + reg = gen_reg_rtx (Pmode); +- +- subregs = 1; ++ address = gen_reg_rtx (Pmode); + } +- +- if (subregs) +- address = gen_reg_rtx (Pmode); + else + address = reg; + +- if (TARGET_32BIT) +- emit_insn (gen_pic_load_addr_32bit (address, orig)); +- else /* TARGET_THUMB1 */ +- emit_insn (gen_pic_load_addr_thumb1 (address, orig)); +- + /* VxWorks does not impose a fixed gap between segments; the run-time + gap can be different from the object-file gap. We therefore can't + use GOTOFF unless we are absolutely sure that the symbol is in the +@@ -5020,16 +5008,23 @@ + SYMBOL_REF_LOCAL_P (orig))) + && NEED_GOT_RELOC + && !TARGET_VXWORKS_RTP) +- pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); ++ insn = arm_pic_static_addr (orig, reg); + else + { ++ /* If this function doesn't have a pic register, create one now. */ ++ require_pic_register (); ++ ++ if (TARGET_32BIT) ++ emit_insn (gen_pic_load_addr_32bit (address, orig)); ++ else /* TARGET_THUMB1 */ ++ emit_insn (gen_pic_load_addr_thumb1 (address, orig)); ++ + pic_ref = gen_const_mem (Pmode, + gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, + address)); ++ insn = emit_move_insn (reg, pic_ref); + } + +- insn = emit_move_insn (reg, pic_ref); +- + /* Put a REG_EQUAL note on this insn, so that it can be optimized + by loop. */ + set_unique_reg_note (insn, REG_EQUAL, orig); +@@ -5236,6 +5231,43 @@ + emit_use (pic_reg); + } + ++/* Generate code to load the address of a static var when flag_pic is set. */ ++static rtx ++arm_pic_static_addr (rtx orig, rtx reg) ++{ ++ rtx l1, labelno, offset_rtx, insn; ++ ++ gcc_assert (flag_pic); ++ ++ /* We use an UNSPEC rather than a LABEL_REF because this label ++ never appears in the code stream. */ ++ labelno = GEN_INT (pic_labelno++); ++ l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); ++ l1 = gen_rtx_CONST (VOIDmode, l1); ++ ++ /* On the ARM the PC register contains 'dot + 8' at the time of the ++ addition, on the Thumb it is 'dot + 4'. */ ++ offset_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); ++ offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx), ++ UNSPEC_SYMBOL_OFFSET); ++ offset_rtx = gen_rtx_CONST (Pmode, offset_rtx); ++ ++ if (TARGET_32BIT) ++ { ++ emit_insn (gen_pic_load_addr_32bit (reg, offset_rtx)); ++ if (TARGET_ARM) ++ insn = emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); ++ else ++ insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); ++ } ++ else /* TARGET_THUMB1 */ ++ { ++ emit_insn (gen_pic_load_addr_thumb1 (reg, offset_rtx)); ++ insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); ++ } ++ ++ return insn; ++} + + /* Return nonzero if X is valid as an ARM state addressing register. */ + static int +@@ -21461,6 +21493,16 @@ + fputc (')', fp); + return TRUE; + } ++ else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET) ++ { ++ output_addr_const (fp, XVECEXP (x, 0, 0)); ++ if (GOT_PCREL) ++ fputs ("+.", fp); ++ fputs ("-(", fp); ++ output_addr_const (fp, XVECEXP (x, 0, 1)); ++ fputc (')', fp); ++ return TRUE; ++ } + else if (GET_CODE (x) == CONST_VECTOR) + return arm_emit_vector_const (fp, x); + + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-07-30 14:17:05 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-05 12:06:40 +0000 +@@ -101,6 +101,8 @@ + ; a given symbolic address. + (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call. + (UNSPEC_RBIT 26) ; rbit operation. ++ (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from ++ ; another symbolic address. + ] + ) + + +=== added file 'gcc/testsuite/gcc.target/arm/pr39839.c' +--- old/gcc/testsuite/gcc.target/arm/pr39839.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr39839.c 2010-08-05 12:06:40 +0000 +@@ -0,0 +1,24 @@ ++/* { dg-options "-mthumb -Os -march=armv5te -mthumb-interwork -fpic" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ ++ ++struct S ++{ ++ int count; ++ char *addr; ++}; ++ ++void func(const char*, const char*, int, const char*); ++ ++/* This function should not need to spill to the stack. */ ++void test(struct S *p) ++{ ++ int off = p->count; ++ while (p->count >= 0) ++ { ++ const char *s = "xyz"; ++ if (*p->addr) s = "pqr"; ++ func("abcde", p->addr + off, off, s); ++ p->count--; ++ } ++} + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch new file mode 100644 index 0000000000..669523218c --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch @@ -0,0 +1,138 @@ +2010-08-05 Andrew Stubbs + + gcc/testsuite/ + * gcc.dg/vect/vect-shift-2.c: Revert all previous changes. + * gcc.dg/vect/vect-shift-4.c: New file. + + 2010-07-20 Yao Qi + + Merge from Sourcery G++ 4.4: + 2009-06-16 Daniel Jacobowitz + + Merge from Sourcery G++ 4.3: + 2008-12-03 Daniel Jacobowitz + + gcc/testsuite/ + * gcc.dg/vect/vect-shift-2.c, gcc.dg/vect/vect-shift-3.c: New. + * lib/target-supports.exp (check_effective_target_vect_shift_char): New + function. + + 2010-07-24 Sandra Loosemore + + Backport from mainline: + +=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-3.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 2010-08-05 14:13:43 +0000 +@@ -0,0 +1,37 @@ ++/* { dg-require-effective-target vect_shift } */ ++/* { dg-require-effective-target vect_int } */ ++ ++#include "tree-vect.h" ++ ++#define N 32 ++ ++unsigned short dst[N] __attribute__((aligned(N))); ++unsigned short src[N] __attribute__((aligned(N))); ++ ++__attribute__ ((noinline)) ++void array_shift(void) ++{ ++ int i; ++ for (i = 0; i < N; i++) ++ dst[i] = src[i] >> 3; ++} ++ ++int main() ++{ ++ volatile int i; ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ src[i] = i << 3; ++ ++ array_shift (); ++ ++ for (i = 0; i < N; i++) ++ if (dst[i] != i) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-4.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 2010-08-05 14:13:43 +0000 +@@ -0,0 +1,37 @@ ++/* { dg-require-effective-target vect_shift_char } */ ++/* { dg-require-effective-target vect_int } */ ++ ++#include "tree-vect.h" ++ ++#define N 32 ++ ++unsigned char dst[N] __attribute__((aligned(N))); ++unsigned char src[N] __attribute__((aligned(N))); ++ ++__attribute__ ((noinline)) ++void array_shift(void) ++{ ++ int i; ++ for (i = 0; i < N; i++) ++ dst[i] = src[i] >> 3; ++} ++ ++int main() ++{ ++ volatile int i; ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ src[i] = i << 3; ++ ++ array_shift (); ++ ++ for (i = 0; i < N; i++) ++ if (dst[i] != i) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/lib/target-supports.exp' +--- old/gcc/testsuite/lib/target-supports.exp 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/lib/target-supports.exp 2010-08-05 14:13:43 +0000 +@@ -2001,6 +2001,26 @@ + return $et_vect_shift_saved + } + ++# Return 1 if the target supports hardware vector shift operation for char. ++ ++proc check_effective_target_vect_shift_char { } { ++ global et_vect_shift_char_saved ++ ++ if [info exists et_vect_shift_char_saved] { ++ verbose "check_effective_target_vect_shift_char: using cached result" 2 ++ } else { ++ set et_vect_shift_char_saved 0 ++ if { ([istarget powerpc*-*-*] ++ && ![istarget powerpc-*-linux*paired*]) ++ || [check_effective_target_arm32] } { ++ set et_vect_shift_char_saved 1 ++ } ++ } ++ ++ verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2 ++ return $et_vect_shift_char_saved ++} ++ + # Return 1 if the target supports hardware vectors of long, 0 otherwise. + # + # This can change for different subtargets so do not cache the result. + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch new file mode 100644 index 0000000000..b122ab10f8 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch @@ -0,0 +1,28 @@ +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2007-07-05 Mark Shinwell + + gcc/ + * config/arm/arm.h (BRANCH_COST): Set to 1 when optimizing for size + on Thumb-2. + + 2010-08-05 Andrew Stubbs + + gcc/testsuite/ + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-03 10:40:56 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-05 14:29:52 +0000 +@@ -2210,7 +2210,8 @@ + /* Try to generate sequences that don't involve branches, we can then use + conditional instructions */ + #define BRANCH_COST(speed_p, predictable_p) \ +- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) ++ (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \ ++ : (optimize > 0 ? 2 : 0)) + + /* Position Independent Code. */ + /* We decide which register to use based on the compilation options and + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch new file mode 100644 index 0000000000..6962c1cecf --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch @@ -0,0 +1,53 @@ + 2007-06-06 Joseph Myers + + gcc/ + * config/arm/arm.h (VALID_IWMMXT_REG_MODE): Allow SImode. + (ARM_LEGITIMIZE_RELOAD_ADDRESS): Reduce range allowed for SImode + offsets with iWMMXt. + * config/arm/arm.c (arm_hard_regno_mode_ok): Update for change to + VALID_IWMMXT_REG_MODE. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2007-07-05 Mark Shinwell + + gcc/ + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-05 12:06:40 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-05 14:33:31 +0000 +@@ -16538,7 +16538,7 @@ + return mode == SImode; + + if (IS_IWMMXT_REGNUM (regno)) +- return VALID_IWMMXT_REG_MODE (mode); ++ return VALID_IWMMXT_REG_MODE (mode) && mode != SImode; + } + + /* We allow almost any value to be stored in the general registers. + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-05 14:29:52 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-05 14:33:31 +0000 +@@ -1077,7 +1077,7 @@ + (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) + + #define VALID_IWMMXT_REG_MODE(MODE) \ +- (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) ++ (arm_vector_mode_supported_p (MODE) || (MODE) == DImode || (MODE) == SImode) + + /* Modes valid for Neon D registers. */ + #define VALID_NEON_DREG_MODE(MODE) \ +@@ -1364,6 +1364,9 @@ + else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ + /* Need to be careful, -256 is not a valid offset. */ \ + low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ ++ else if (TARGET_REALLY_IWMMXT && MODE == SImode) \ ++ /* Need to be careful, -1024 is not a valid offset. */ \ ++ low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ + else if (MODE == SImode \ + || (MODE == SFmode && TARGET_SOFT_FLOAT) \ + || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch new file mode 100644 index 0000000000..38b6fa3f0e --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch @@ -0,0 +1,688 @@ + Vladimir Prus + Julian Brown + + gcc/ + * config/arm/arm.c (arm_override_options): Warn if mlow-irq-latency is + specified in Thumb mode. + (load_multiple_sequence): Return 0 if low irq latency is requested. + (store_multiple_sequence): Likewise. + (arm_gen_load_multiple): Load registers one-by-one if low irq latency + is requested. + (arm_gen_store_multiple): Likewise. + (vfp_output_fldmd): When low_irq_latency is non zero, pop each + register separately. + (vfp_emit_fstmd): When low_irq_latency is non zero, save each register + separately. + (arm_get_vfp_saved_size): Adjust saved register size calculation for + the above changes. + (print_pop_reg_by_ldr): New. + (arm_output_epilogue): Use print_pop_reg_by_ldr when low irq latency + is requested. + (emit_multi_reg_push): Push registers separately if low irq latency + is requested. + * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set __low_irq_latency__. + (low_irq_latency): Define. + (USE_RETURN_INSN): Don't use return insn when low irq latency is + requested. + * config/arm/lib1funcs.asm (do_pop, do_push): Define as variadic + macros. When __low_irq_latency__ is defined, push and pop registers + individually. + (div0): Use correct punctuation. + * config/arm/ieee754-df.S: Adjust syntax of using do_push. + * config/arm/ieee754-sf.S: Likewise. + * config/arm/bpabi.S: Likewise. + * config/arm/arm.opt (mlow-irq-latency): New option. + * config/arm/predicates.md (load_multiple_operation): Return false is + low irq latency is requested. + (store_multiple_operation): Likewise. + * config/arm/arm.md (movmemqi): Don't use it if low irq latency is + requested. + * doc/invoke.texi (-mlow-irq-latency): Add documentation. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2007-06-06 Joseph Myers + + gcc/ + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-05 14:33:31 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-05 15:20:54 +0000 +@@ -1884,6 +1884,13 @@ + + /* Register global variables with the garbage collector. */ + arm_add_gc_roots (); ++ ++ if (low_irq_latency && TARGET_THUMB) ++ { ++ warning (0, ++ "-mlow-irq-latency has no effect when compiling for Thumb"); ++ low_irq_latency = 0; ++ } + } + + static void +@@ -9053,6 +9060,9 @@ + int base_reg = -1; + int i; + ++ if (low_irq_latency) ++ return 0; ++ + /* Can only handle 2, 3, or 4 insns at present, + though could be easily extended if required. */ + gcc_assert (nops >= 2 && nops <= 4); +@@ -9282,6 +9292,9 @@ + int base_reg = -1; + int i; + ++ if (low_irq_latency) ++ return 0; ++ + /* Can only handle 2, 3, or 4 insns at present, though could be easily + extended if required. */ + gcc_assert (nops >= 2 && nops <= 4); +@@ -9489,7 +9502,7 @@ + + As a compromise, we use ldr for counts of 1 or 2 regs, and ldm + for counts of 3 or 4 regs. */ +- if (arm_tune_xscale && count <= 2 && ! optimize_size) ++ if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) + { + rtx seq; + +@@ -9552,7 +9565,7 @@ + + /* See arm_gen_load_multiple for discussion of + the pros/cons of ldm/stm usage for XScale. */ +- if (arm_tune_xscale && count <= 2 && ! optimize_size) ++ if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) + { + rtx seq; + +@@ -11795,6 +11808,21 @@ + vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) + { + int i; ++ int offset; ++ ++ if (low_irq_latency) ++ { ++ /* Output a sequence of FLDD instructions. */ ++ offset = 0; ++ for (i = reg; i < reg + count; ++i, offset += 8) ++ { ++ fputc ('\t', stream); ++ asm_fprintf (stream, "fldd\td%d, [%r,#%d]\n", i, base, offset); ++ } ++ asm_fprintf (stream, "\tadd\tsp, sp, #%d\n", count * 8); ++ return; ++ } ++ + + /* Workaround ARM10 VFPr1 bug. */ + if (count == 2 && !arm_arch6) +@@ -11865,6 +11893,56 @@ + rtx tmp, reg; + int i; + ++ if (low_irq_latency) ++ { ++ int saved_size; ++ rtx sp_insn; ++ ++ if (!count) ++ return 0; ++ ++ saved_size = count * GET_MODE_SIZE (DFmode); ++ ++ /* Since fstd does not have postdecrement addressing mode, ++ we first decrement stack pointer and then use base+offset ++ stores for VFP registers. The ARM EABI unwind information ++ can't easily describe base+offset loads, so we attach ++ a note for the effects of the whole block in the first insn, ++ and avoid marking the subsequent instructions ++ with RTX_FRAME_RELATED_P. */ ++ sp_insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ GEN_INT (-saved_size)); ++ sp_insn = emit_insn (sp_insn); ++ RTX_FRAME_RELATED_P (sp_insn) = 1; ++ ++ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); ++ XVECEXP (dwarf, 0, 0) = ++ gen_rtx_SET (VOIDmode, stack_pointer_rtx, ++ plus_constant (stack_pointer_rtx, -saved_size)); ++ ++ /* push double VFP registers to stack */ ++ for (i = 0; i < count; ++i ) ++ { ++ rtx reg; ++ rtx mem; ++ rtx addr; ++ rtx insn; ++ reg = gen_rtx_REG (DFmode, base_reg + 2*i); ++ addr = (i == 0) ? stack_pointer_rtx ++ : gen_rtx_PLUS (SImode, stack_pointer_rtx, ++ GEN_INT (i * GET_MODE_SIZE (DFmode))); ++ mem = gen_frame_mem (DFmode, addr); ++ insn = emit_move_insn (mem, reg); ++ XVECEXP (dwarf, 0, i+1) = ++ gen_rtx_SET (VOIDmode, mem, reg); ++ } ++ ++ REG_NOTES (sp_insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, ++ REG_NOTES (sp_insn)); ++ ++ return saved_size; ++ } ++ + /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two + register pairs are stored by a store multiple insn. We avoid this + by pushing an extra pair. */ +@@ -13307,7 +13385,7 @@ + if (count > 0) + { + /* Workaround ARM10 VFPr1 bug. */ +- if (count == 2 && !arm_arch6) ++ if (count == 2 && !arm_arch6 && !low_irq_latency) + count++; + saved += count * 8; + } +@@ -13645,6 +13723,41 @@ + + } + ++/* Generate to STREAM a code sequence that pops registers identified ++ in REGS_MASK from SP. SP is incremented as the result. ++*/ ++static void ++print_pop_reg_by_ldr (FILE *stream, int regs_mask, int rfe) ++{ ++ int reg; ++ ++ gcc_assert (! (regs_mask & (1 << SP_REGNUM))); ++ ++ for (reg = 0; reg < PC_REGNUM; ++reg) ++ if (regs_mask & (1 << reg)) ++ asm_fprintf (stream, "\tldr\t%r, [%r], #4\n", ++ reg, SP_REGNUM); ++ ++ if (regs_mask & (1 << PC_REGNUM)) ++ { ++ if (rfe) ++ /* When returning from exception, we need to ++ copy SPSR to CPSR. There are two ways to do ++ that: the ldm instruction with "^" suffix, ++ and movs instruction. The latter would ++ require that we load from stack to some ++ scratch register, and then move to PC. ++ Therefore, we'd need extra instruction and ++ have to make sure we actually have a spare ++ register. Using ldm with a single register ++ is simler. */ ++ asm_fprintf (stream, "\tldm\tsp!, {pc}^\n"); ++ else ++ asm_fprintf (stream, "\tldr\t%r, [%r], #4\n", ++ PC_REGNUM, SP_REGNUM); ++ } ++} ++ + const char * + arm_output_epilogue (rtx sibling) + { +@@ -14018,22 +14131,19 @@ + to load use the LDR instruction - it is faster. For Thumb-2 + always use pop and the assembler will pick the best instruction.*/ + if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) +- && !IS_INTERRUPT(func_type)) ++ && !IS_INTERRUPT (func_type)) + { + asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); + } + else if (saved_regs_mask) + { +- if (saved_regs_mask & (1 << SP_REGNUM)) +- /* Note - write back to the stack register is not enabled +- (i.e. "ldmfd sp!..."). We know that the stack pointer is +- in the list of registers and if we add writeback the +- instruction becomes UNPREDICTABLE. */ +- print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, +- rfe); +- else if (TARGET_ARM) +- print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, +- rfe); ++ gcc_assert ( ! (saved_regs_mask & (1 << SP_REGNUM))); ++ if (TARGET_ARM) ++ if (low_irq_latency) ++ print_pop_reg_by_ldr (f, saved_regs_mask, rfe); ++ else ++ print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, ++ rfe); + else + print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); + } +@@ -14154,6 +14264,32 @@ + + gcc_assert (num_regs && num_regs <= 16); + ++ if (low_irq_latency) ++ { ++ rtx insn = 0; ++ ++ /* Emit a series of ldr instructions rather rather than a single ldm. */ ++ /* TODO: Use ldrd where possible. */ ++ gcc_assert (! (mask & (1 << SP_REGNUM))); ++ ++ for (i = LAST_ARM_REGNUM; i >= 0; --i) ++ { ++ if (mask & (1 << i)) ++ ++ { ++ rtx reg, where, mem; ++ ++ reg = gen_rtx_REG (SImode, i); ++ where = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); ++ mem = gen_rtx_MEM (SImode, where); ++ insn = emit_move_insn (mem, reg); ++ RTX_FRAME_RELATED_P (insn) = 1; ++ } ++ } ++ ++ return insn; ++ } ++ + /* We don't record the PC in the dwarf frame information. */ + num_dwarf_regs = num_regs; + if (mask & (1 << PC_REGNUM)) + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-05 14:33:31 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-05 15:20:54 +0000 +@@ -101,6 +101,8 @@ + builtin_define ("__ARM_PCS"); \ + builtin_define ("__ARM_EABI__"); \ + } \ ++ if (low_irq_latency) \ ++ builtin_define ("__low_irq_latency__"); \ + } while (0) + + /* The various ARM cores. */ +@@ -449,6 +451,10 @@ + /* Nonzero if chip supports integer division instruction. */ + extern int arm_arch_hwdiv; + ++/* Nonzero if we should minimize interrupt latency of the ++ generated code. */ ++extern int low_irq_latency; ++ + #ifndef TARGET_DEFAULT + #define TARGET_DEFAULT (MASK_APCS_FRAME) + #endif +@@ -1823,9 +1829,10 @@ + /* Determine if the epilogue should be output as RTL. + You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ + /* This is disabled for Thumb-2 because it will confuse the +- conditional insn counter. */ ++ conditional insn counter. ++ Do not use a return insn if we're avoiding ldm/stm instructions. */ + #define USE_RETURN_INSN(ISCOND) \ +- (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) ++ ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0) + + /* Definitions for register eliminations. + + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-05 12:06:40 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-05 15:20:54 +0000 +@@ -6587,7 +6587,7 @@ + (match_operand:BLK 1 "general_operand" "") + (match_operand:SI 2 "const_int_operand" "") + (match_operand:SI 3 "const_int_operand" "")] +- "TARGET_EITHER" ++ "TARGET_EITHER && !low_irq_latency" + " + if (TARGET_32BIT) + { + +=== modified file 'gcc/config/arm/arm.opt' +--- old/gcc/config/arm/arm.opt 2009-06-18 11:24:10 +0000 ++++ new/gcc/config/arm/arm.opt 2010-08-05 15:20:54 +0000 +@@ -161,6 +161,10 @@ + Target Report Mask(NEON_VECTORIZE_QUAD) + Use Neon quad-word (rather than double-word) registers for vectorization + ++mlow-irq-latency ++Target Report Var(low_irq_latency) ++Try to reduce interrupt latency of the generated code ++ + mword-relocations + Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) + Only generate absolute relocations on word sized values. + +=== modified file 'gcc/config/arm/bpabi.S' +--- old/gcc/config/arm/bpabi.S 2009-12-17 15:37:23 +0000 ++++ new/gcc/config/arm/bpabi.S 2010-08-05 15:20:54 +0000 +@@ -116,16 +116,17 @@ + test_div_by_zero signed + + sub sp, sp, #8 +-#if defined(__thumb2__) ++/* Low latency and Thumb-2 do_push implementations can't push sp directly. */ ++#if defined(__thumb2__) || defined(__irq_low_latency__) + mov ip, sp +- push {ip, lr} ++ do_push (ip, lr) + #else +- do_push {sp, lr} ++ stmfd sp!, {sp, lr} + #endif + bl SYM(__gnu_ldivmod_helper) __PLT__ + ldr lr, [sp, #4] + add sp, sp, #8 +- do_pop {r2, r3} ++ do_pop (r2, r3) + RET + + #endif /* L_aeabi_ldivmod */ +@@ -136,16 +137,17 @@ + test_div_by_zero unsigned + + sub sp, sp, #8 +-#if defined(__thumb2__) ++/* Low latency and Thumb-2 do_push implementations can't push sp directly. */ ++#if defined(__thumb2__) || defined(__irq_low_latency__) + mov ip, sp +- push {ip, lr} ++ do_push (ip, lr) + #else +- do_push {sp, lr} ++ stmfd sp!, {sp, lr} + #endif + bl SYM(__gnu_uldivmod_helper) __PLT__ + ldr lr, [sp, #4] + add sp, sp, #8 +- do_pop {r2, r3} ++ do_pop (r2, r3) + RET + + #endif /* L_aeabi_divmod */ + +=== modified file 'gcc/config/arm/ieee754-df.S' +--- old/gcc/config/arm/ieee754-df.S 2009-06-05 12:52:36 +0000 ++++ new/gcc/config/arm/ieee754-df.S 2010-08-05 15:20:54 +0000 +@@ -83,7 +83,7 @@ + ARM_FUNC_START adddf3 + ARM_FUNC_ALIAS aeabi_dadd adddf3 + +-1: do_push {r4, r5, lr} ++1: do_push (r4, r5, lr) + + @ Look for zeroes, equal values, INF, or NAN. + shift1 lsl, r4, xh, #1 +@@ -427,7 +427,7 @@ + do_it eq, t + moveq r1, #0 + RETc(eq) +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + mov r4, #0x400 @ initial exponent + add r4, r4, #(52-1 - 1) + mov r5, #0 @ sign bit is 0 +@@ -447,7 +447,7 @@ + do_it eq, t + moveq r1, #0 + RETc(eq) +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + mov r4, #0x400 @ initial exponent + add r4, r4, #(52-1 - 1) + ands r5, r0, #0x80000000 @ sign bit in r5 +@@ -481,7 +481,7 @@ + RETc(eq) @ we are done already. + + @ value was denormalized. We can normalize it now. +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + mov r4, #0x380 @ setup corresponding exponent + and r5, xh, #0x80000000 @ move sign bit in r5 + bic xh, xh, #0x80000000 +@@ -508,9 +508,9 @@ + @ compatibility. + adr ip, LSYM(f0_ret) + @ Push pc as well so that RETLDM works correctly. +- do_push {r4, r5, ip, lr, pc} ++ do_push (r4, r5, ip, lr, pc) + #else +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + #endif + + mov r5, #0 +@@ -534,9 +534,9 @@ + @ compatibility. + adr ip, LSYM(f0_ret) + @ Push pc as well so that RETLDM works correctly. +- do_push {r4, r5, ip, lr, pc} ++ do_push (r4, r5, ip, lr, pc) + #else +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + #endif + + ands r5, ah, #0x80000000 @ sign bit in r5 +@@ -585,7 +585,7 @@ + @ Legacy code expects the result to be returned in f0. Copy it + @ there as well. + LSYM(f0_ret): +- do_push {r0, r1} ++ do_push (r0, r1) + ldfd f0, [sp], #8 + RETLDM + +@@ -602,7 +602,7 @@ + + ARM_FUNC_START muldf3 + ARM_FUNC_ALIAS aeabi_dmul muldf3 +- do_push {r4, r5, r6, lr} ++ do_push (r4, r5, r6, lr) + + @ Mask out exponents, trap any zero/denormal/INF/NAN. + mov ip, #0xff +@@ -910,7 +910,7 @@ + ARM_FUNC_START divdf3 + ARM_FUNC_ALIAS aeabi_ddiv divdf3 + +- do_push {r4, r5, r6, lr} ++ do_push (r4, r5, r6, lr) + + @ Mask out exponents, trap any zero/denormal/INF/NAN. + mov ip, #0xff +@@ -1195,7 +1195,7 @@ + + @ The status-returning routines are required to preserve all + @ registers except ip, lr, and cpsr. +-6: do_push {r0, lr} ++6: do_push (r0, lr) + ARM_CALL cmpdf2 + @ Set the Z flag correctly, and the C flag unconditionally. + cmp r0, #0 + +=== modified file 'gcc/config/arm/ieee754-sf.S' +--- old/gcc/config/arm/ieee754-sf.S 2009-06-05 12:52:36 +0000 ++++ new/gcc/config/arm/ieee754-sf.S 2010-08-05 15:20:54 +0000 +@@ -481,7 +481,7 @@ + and r3, ip, #0x80000000 + + @ Well, no way to make it shorter without the umull instruction. +- do_push {r3, r4, r5} ++ do_push (r3, r4, r5) + mov r4, r0, lsr #16 + mov r5, r1, lsr #16 + bic r0, r0, r4, lsl #16 +@@ -492,7 +492,7 @@ + mla r0, r4, r1, r0 + adds r3, r3, r0, lsl #16 + adc r1, ip, r0, lsr #16 +- do_pop {r0, r4, r5} ++ do_pop (r0, r4, r5) + + #else + +@@ -882,7 +882,7 @@ + + @ The status-returning routines are required to preserve all + @ registers except ip, lr, and cpsr. +-6: do_push {r0, r1, r2, r3, lr} ++6: do_push (r0, r1, r2, r3, lr) + ARM_CALL cmpsf2 + @ Set the Z flag correctly, and the C flag unconditionally. + cmp r0, #0 + +=== modified file 'gcc/config/arm/lib1funcs.asm' +--- old/gcc/config/arm/lib1funcs.asm 2010-04-02 18:54:46 +0000 ++++ new/gcc/config/arm/lib1funcs.asm 2010-08-05 15:20:54 +0000 +@@ -254,8 +254,8 @@ + .macro shift1 op, arg0, arg1, arg2 + \op \arg0, \arg1, \arg2 + .endm +-#define do_push push +-#define do_pop pop ++#define do_push(...) push {__VA_ARGS__} ++#define do_pop(...) pop {__VA_ARGS__} + #define COND(op1, op2, cond) op1 ## op2 ## cond + /* Perform an arithmetic operation with a variable shift operand. This + requires two instructions and a scratch register on Thumb-2. */ +@@ -269,8 +269,42 @@ + .macro shift1 op, arg0, arg1, arg2 + mov \arg0, \arg1, \op \arg2 + .endm +-#define do_push stmfd sp!, +-#define do_pop ldmfd sp!, ++#if defined(__low_irq_latency__) ++#define do_push(...) \ ++ _buildN1(do_push, _buildC1(__VA_ARGS__))( __VA_ARGS__) ++#define _buildN1(BASE, X) _buildN2(BASE, X) ++#define _buildN2(BASE, X) BASE##X ++#define _buildC1(...) _buildC2(__VA_ARGS__,9,8,7,6,5,4,3,2,1) ++#define _buildC2(a1,a2,a3,a4,a5,a6,a7,a8,a9,c,...) c ++ ++#define do_push1(r1) str r1, [sp, #-4]! ++#define do_push2(r1, r2) str r2, [sp, #-4]! ; str r1, [sp, #-4]! ++#define do_push3(r1, r2, r3) str r3, [sp, #-4]! ; str r2, [sp, #-4]!; str r1, [sp, #-4]! ++#define do_push4(r1, r2, r3, r4) \ ++ do_push3 (r2, r3, r4);\ ++ do_push1 (r1) ++#define do_push5(r1, r2, r3, r4, r5) \ ++ do_push4 (r2, r3, r4, r5);\ ++ do_push1 (r1) ++ ++#define do_pop(...) \ ++_buildN1(do_pop, _buildC1(__VA_ARGS__))( __VA_ARGS__) ++ ++#define do_pop1(r1) ldr r1, [sp], #4 ++#define do_pop2(r1, r2) ldr r1, [sp], #4 ; ldr r2, [sp], #4 ++#define do_pop3(r1, r2, r3) ldr r1, [sp], #4 ; str r2, [sp], #4; str r3, [sp], #4 ++#define do_pop4(r1, r2, r3, r4) \ ++ do_pop1 (r1);\ ++ do_pup3 (r2, r3, r4) ++#define do_pop5(r1, r2, r3, r4, r5) \ ++ do_pop1 (r1);\ ++ do_pop4 (r2, r3, r4, r5) ++#else ++#define do_push(...) stmfd sp!, { __VA_ARGS__} ++#define do_pop(...) ldmfd sp!, {__VA_ARGS__} ++#endif ++ ++ + #define COND(op1, op2, cond) op1 ## cond ## op2 + .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp + \name \dest, \src1, \src2, \shiftop \shiftreg +@@ -1260,7 +1294,7 @@ + ARM_FUNC_START div0 + #endif + +- do_push {r1, lr} ++ do_push (r1, lr) + mov r0, #SIGFPE + bl SYM(raise) __PLT__ + RETLDM r1 +@@ -1277,7 +1311,7 @@ + #if defined __ARM_EABI__ && defined __linux__ + @ EABI GNU/Linux call to cacheflush syscall. + ARM_FUNC_START clear_cache +- do_push {r7} ++ do_push (r7) + #if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) + movw r7, #2 + movt r7, #0xf +@@ -1287,7 +1321,7 @@ + #endif + mov r2, #0 + swi 0 +- do_pop {r7} ++ do_pop (r7) + RET + FUNC_END clear_cache + #else +@@ -1490,7 +1524,7 @@ + push {r4, lr} + # else + ARM_FUNC_START clzdi2 +- do_push {r4, lr} ++ do_push (r4, lr) + # endif + cmp xxh, #0 + bne 1f + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2010-07-30 14:17:05 +0000 ++++ new/gcc/config/arm/predicates.md 2010-08-05 15:20:54 +0000 +@@ -328,6 +328,9 @@ + HOST_WIDE_INT i = 1, base = 0; + rtx elt; + ++ if (low_irq_latency) ++ return false; ++ + if (count <= 1 + || GET_CODE (XVECEXP (op, 0, 0)) != SET) + return false; +@@ -385,6 +388,9 @@ + HOST_WIDE_INT i = 1, base = 0; + rtx elt; + ++ if (low_irq_latency) ++ return false; ++ + if (count <= 1 + || GET_CODE (XVECEXP (op, 0, 0)) != SET) + return false; + +=== modified file 'gcc/doc/invoke.texi' +--- old/gcc/doc/invoke.texi 2010-07-29 17:03:20 +0000 ++++ new/gcc/doc/invoke.texi 2010-08-05 15:20:54 +0000 +@@ -469,6 +469,7 @@ + -mtpcs-frame -mtpcs-leaf-frame @gol + -mcaller-super-interworking -mcallee-super-interworking @gol + -mtp=@var{name} @gol ++-mlow-irq-latency @gol + -mword-relocations @gol + -mfix-cortex-m3-ldrd} + +@@ -9489,6 +9490,12 @@ + @code{,}, @code{!}, @code{|}, and @code{*} as needed. + + ++@item -mlow-irq-latency ++@opindex mlow-irq-latency ++Avoid instructions with high interrupt latency when generating ++code. This can increase code size and reduce performance. ++The option is off by default. ++ + @end table + + The conditional text @code{X} in a %@{@code{S}:@code{X}@} or similar + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch new file mode 100644 index 0000000000..40b368862d --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch @@ -0,0 +1,109 @@ + Julian Brown + Mark Shinwell + + gcc/ + * regrename.c (addresses.h): Move include of addresses.h after + include of flags.h. + * recog.c: Likewise. + * regcprop.c: Likewise. + * config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Check against + LO_REGS only for Thumb-1. + (MODE_BASE_REG_CLASS): Restrict base registers to those which can + be used in short instructions when optimising for size on Thumb-2. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + Vladimir Prus + Julian Brown + + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-05 15:20:54 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-05 15:28:47 +0000 +@@ -1254,11 +1254,14 @@ + || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ + : 0) + +-/* We need to define this for LO_REGS on thumb. Otherwise we can end up +- using r0-r4 for function arguments, r7 for the stack frame and don't +- have enough left over to do doubleword arithmetic. */ ++/* We need to define this for LO_REGS on Thumb-1. Otherwise we can end up ++ using r0-r4 for function arguments, r7 for the stack frame and don't have ++ enough left over to do doubleword arithmetic. For Thumb-2 all the ++ potentially problematic instructions accept high registers so this is not ++ necessary. Care needs to be taken to avoid adding new Thumb-2 patterns ++ that require many low registers. */ + #define CLASS_LIKELY_SPILLED_P(CLASS) \ +- ((TARGET_THUMB && (CLASS) == LO_REGS) \ ++ ((TARGET_THUMB1 && (CLASS) == LO_REGS) \ + || (CLASS) == CC_REG) + + /* The class value for index registers, and the one for base regs. */ +@@ -1269,7 +1272,7 @@ + when addressing quantities in QI or HI mode; if we don't know the + mode, then we must be conservative. */ + #define MODE_BASE_REG_CLASS(MODE) \ +- (TARGET_32BIT ? CORE_REGS : \ ++ (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ + (((MODE) == SImode) ? BASE_REGS : LO_REGS)) + + /* For Thumb we can not support SP+reg addressing, so we return LO_REGS + +=== modified file 'gcc/recog.c' +--- old/gcc/recog.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/recog.c 2010-08-05 15:28:47 +0000 +@@ -31,10 +31,10 @@ + #include "hard-reg-set.h" + #include "recog.h" + #include "regs.h" +-#include "addresses.h" + #include "expr.h" + #include "function.h" + #include "flags.h" ++#include "addresses.h" + #include "real.h" + #include "toplev.h" + #include "basic-block.h" + +=== modified file 'gcc/regcprop.c' +--- old/gcc/regcprop.c 2010-02-26 11:01:28 +0000 ++++ new/gcc/regcprop.c 2010-08-05 15:28:47 +0000 +@@ -26,7 +26,6 @@ + #include "tm_p.h" + #include "insn-config.h" + #include "regs.h" +-#include "addresses.h" + #include "hard-reg-set.h" + #include "basic-block.h" + #include "reload.h" +@@ -34,6 +33,7 @@ + #include "function.h" + #include "recog.h" + #include "flags.h" ++#include "addresses.h" + #include "toplev.h" + #include "obstack.h" + #include "timevar.h" + +=== modified file 'gcc/regrename.c' +--- old/gcc/regrename.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/regrename.c 2010-08-05 15:28:47 +0000 +@@ -26,7 +26,6 @@ + #include "tm_p.h" + #include "insn-config.h" + #include "regs.h" +-#include "addresses.h" + #include "hard-reg-set.h" + #include "basic-block.h" + #include "reload.h" +@@ -34,6 +33,7 @@ + #include "function.h" + #include "recog.h" + #include "flags.h" ++#include "addresses.h" + #include "toplev.h" + #include "obstack.h" + #include "timevar.h" + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch new file mode 100644 index 0000000000..0dbb3dbf7f --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch @@ -0,0 +1,174 @@ + http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html + + Kazu Hirata + + gcc/testsuite/ + * gcc.target/arm/vfp-ldmdbd.c, gcc.target/arm/vfp-ldmdbs.c, + gcc.target/arm/vfp-ldmiad.c, gcc.target/arm/vfp-ldmias.c, + gcc.target/arm/vfp-stmdbd.c, gcc.target/arm/vfp-stmdbs.c, + gcc.target/arm/vfp-stmiad.c, gcc.target/arm/vfp-stmias.c: New. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + Julian Brown + Mark Shinwell + + +=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c' +--- old/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c 2010-08-05 15:37:24 +0000 +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++extern void bar (double); ++ ++void ++foo (double *p, double a, int n) ++{ ++ do ++ bar (*--p + a); ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fldmdbd" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c' +--- old/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c 2010-08-05 15:37:24 +0000 +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++extern void baz (float); ++ ++void ++foo (float *p, float a, int n) ++{ ++ do ++ bar (*--p + a); ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fldmdbs" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmiad.c' +--- old/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c 2010-08-05 15:37:24 +0000 +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++extern void bar (double); ++ ++void ++foo (double *p, double a, int n) ++{ ++ do ++ bar (*p++ + a); ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fldmiad" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmias.c' +--- old/gcc/testsuite/gcc.target/arm/vfp-ldmias.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/vfp-ldmias.c 2010-08-05 15:37:24 +0000 +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++extern void baz (float); ++ ++void ++foo (float *p, float a, int n) ++{ ++ do ++ bar (*p++ + a); ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fldmias" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmdbd.c' +--- old/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c 2010-08-05 15:37:24 +0000 +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++void ++foo (double *p, double a, double b, int n) ++{ ++ double c = a + b; ++ do ++ *--p = c; ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fstmdbd" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmdbs.c' +--- old/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c 2010-08-05 15:37:24 +0000 +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++void ++foo (float *p, float a, float b, int n) ++{ ++ float c = a + b; ++ do ++ *--p = c; ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fstmdbs" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmiad.c' +--- old/gcc/testsuite/gcc.target/arm/vfp-stmiad.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/vfp-stmiad.c 2010-08-05 15:37:24 +0000 +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++void ++foo (double *p, double a, double b, int n) ++{ ++ double c = a + b; ++ do ++ *p++ = c; ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fstmiad" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmias.c' +--- old/gcc/testsuite/gcc.target/arm/vfp-stmias.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/vfp-stmias.c 2010-08-05 15:37:24 +0000 +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++void ++foo (float *p, float a, float b, int n) ++{ ++ float c = a + b; ++ do ++ *p++ = c; ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fstmias" } } */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch new file mode 100644 index 0000000000..59b598ba70 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch @@ -0,0 +1,86 @@ + + http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html + + * g++.dg/other/armv7m-1.C: New. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html + + +=== added file 'gcc/testsuite/g++.dg/other/armv7m-1.C' +--- old/gcc/testsuite/g++.dg/other/armv7m-1.C 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/g++.dg/other/armv7m-1.C 2010-08-05 16:23:43 +0000 +@@ -0,0 +1,69 @@ ++/* { dg-do run { target arm*-*-* } } */ ++/* Test Armv7m interrupt routines. */ ++#include ++ ++#ifdef __ARM_ARCH_7M__ ++void __attribute__((interrupt)) ++foo(void) ++{ ++ long long n; ++ long p; ++ asm volatile ("" : "=r" (p) : "0" (&n)); ++ if (p & 4) ++ abort (); ++ return; ++} ++ ++void __attribute__((interrupt)) ++bar(void) ++{ ++ throw 42; ++} ++ ++int main() ++{ ++ int a; ++ int before; ++ int after; ++ volatile register int sp asm("sp"); ++ ++ asm volatile ("mov %0, sp\n" ++ "blx %2\n" ++ "mov %1, sp\n" ++ : "=&r" (before), "=r" (after) : "r" (foo) ++ : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr"); ++ if (before != after) ++ abort(); ++ asm volatile ("mov %0, sp\n" ++ "sub sp, sp, #4\n" ++ "blx %2\n" ++ "add sp, sp, #4\n" ++ "mov %1, sp\n" ++ : "=&r" (before), "=r" (after) : "r" (foo) ++ : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr"); ++ if (before != after) ++ abort(); ++ before = sp; ++ try ++ { ++ bar(); ++ } ++ catch (int i) ++ { ++ if (i != 42) ++ abort(); ++ } ++ catch (...) ++ { ++ abort(); ++ } ++ if (before != sp) ++ abort(); ++ exit(0); ++} ++#else ++int main() ++{ ++ exit (0); ++} ++#endif + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch new file mode 100644 index 0000000000..5d489aab69 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch @@ -0,0 +1,132 @@ + Backport from FSF mainline: + + Mark Shinwell + Julian Brown + + gcc/ + * config/arm/thumb2.md (thumb2_movsi_insn): Split ldr and str + alternatives according to use of high and low regs. + * config/arm/vfp.md (thumb2_movsi_vfp): Likewise. + * config/arm/arm.h (CONDITIONAL_REGISTER_USAGE): Use high regs when + optimizing for size on Thumb-2. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-05 15:28:47 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-05 16:34:46 +0000 +@@ -783,12 +783,11 @@ + fixed_regs[regno] = call_used_regs[regno] = 1; \ + } \ + \ +- if (TARGET_THUMB && optimize_size) \ +- { \ +- /* When optimizing for size, it's better not to use \ +- the HI regs, because of the overhead of stacking \ +- them. */ \ +- /* ??? Is this still true for thumb2? */ \ ++ if (TARGET_THUMB1 && optimize_size) \ ++ { \ ++ /* When optimizing for size on Thumb-1, it's better not \ ++ to use the HI regs, because of the overhead of \ ++ stacking them. */ \ + for (regno = FIRST_HI_REGNUM; \ + regno <= LAST_HI_REGNUM; ++regno) \ + fixed_regs[regno] = call_used_regs[regno] = 1; \ + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2010-04-02 07:32:00 +0000 ++++ new/gcc/config/arm/thumb2.md 2010-08-05 16:34:46 +0000 +@@ -223,9 +223,14 @@ + (set_attr "neg_pool_range" "*,*,*,0,*")] + ) + ++;; We have two alternatives here for memory loads (and similarly for stores) ++;; to reflect the fact that the permissible constant pool ranges differ ++;; between ldr instructions taking low regs and ldr instructions taking high ++;; regs. The high register alternatives are not taken into account when ++;; choosing register preferences in order to reflect their expense. + (define_insn "*thumb2_movsi_insn" +- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m") +- (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,rk"))] ++ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l, *hk,m,*m") ++ (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))] + "TARGET_THUMB2 && ! TARGET_IWMMXT + && !(TARGET_HARD_FLOAT && TARGET_VFP) + && ( register_operand (operands[0], SImode) +@@ -236,11 +241,13 @@ + mvn%?\\t%0, #%B1 + movw%?\\t%0, %1 + ldr%?\\t%0, %1 ++ ldr%?\\t%0, %1 ++ str%?\\t%1, %0 + str%?\\t%1, %0" +- [(set_attr "type" "*,*,*,*,load1,store1") ++ [(set_attr "type" "*,*,*,*,load1,load1,store1,store1") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "*,*,*,*,4096,*") +- (set_attr "neg_pool_range" "*,*,*,*,0,*")] ++ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*") ++ (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")] + ) + + (define_insn "tls_load_dot_plus_four" + +=== modified file 'gcc/config/arm/vfp.md' +--- old/gcc/config/arm/vfp.md 2010-07-30 14:17:05 +0000 ++++ new/gcc/config/arm/vfp.md 2010-08-05 16:34:46 +0000 +@@ -86,9 +86,11 @@ + (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] + ) + ++;; See thumb2.md:thumb2_movsi_insn for an explanation of the split ++;; high/low register alternatives for loads and stores here. + (define_insn "*thumb2_movsi_vfp" +- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv") +- (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))] ++ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l,*hk,m,*m,*t,r, *t,*t, *Uv") ++ (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,*mi,l,*hk,r,*t,*t,*Uvi,*t"))] + "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT + && ( s_register_operand (operands[0], SImode) + || s_register_operand (operands[1], SImode))" +@@ -102,25 +104,27 @@ + case 3: + return \"movw%?\\t%0, %1\"; + case 4: ++ case 5: + return \"ldr%?\\t%0, %1\"; +- case 5: ++ case 6: ++ case 7: + return \"str%?\\t%1, %0\"; +- case 6: ++ case 8: + return \"fmsr%?\\t%0, %1\\t%@ int\"; +- case 7: ++ case 9: + return \"fmrs%?\\t%0, %1\\t%@ int\"; +- case 8: ++ case 10: + return \"fcpys%?\\t%0, %1\\t%@ int\"; +- case 9: case 10: ++ case 11: case 12: + return output_move_vfp (operands); + default: + gcc_unreachable (); + } + " + [(set_attr "predicable" "yes") +- (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store") +- (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") +- (set_attr "neg_pool_range" "*,*,*,*, 0,*,*,*,*,1008,*")] ++ (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store") ++ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") ++ (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] + ) + + + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch new file mode 100644 index 0000000000..3e63611305 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch @@ -0,0 +1,68 @@ +2010-08-06 Yao Qi + + LP: #612011 + gcc/ + * config/arm/arm.c (output_move_double): Fix typo generating + instructions ('ldr'->'str'). + + gcc/testsuite/ + * gcc.target/arm/pr45094.c: New test. + + 2010-08-02 Ulrich Weigand + + LP: #604874 + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-10 13:31:21 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-10 14:03:02 +0000 +@@ -12506,13 +12506,13 @@ + { + if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) + { +- output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); +- output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); ++ output_asm_insn ("str%?\t%0, [%1, %2]!", otherops); ++ output_asm_insn ("str%?\t%H0, [%1, #4]", otherops); + } + else + { +- output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); +- output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); ++ output_asm_insn ("str%?\t%H0, [%1, #4]", otherops); ++ output_asm_insn ("str%?\t%0, [%1], %2", otherops); + } + } + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) + +=== added file 'gcc/testsuite/gcc.target/arm/pr45094.c' +--- old/gcc/testsuite/gcc.target/arm/pr45094.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr45094.c 2010-08-06 05:10:03 +0000 +@@ -0,0 +1,27 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O2 -mcpu=cortex-a8" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++long long buffer[32]; ++ ++void __attribute__((noinline)) f(long long *p, int n) ++{ ++ while (--n >= 0) ++ { ++ *p = 1; ++ p += 32; ++ } ++} ++ ++int main(void) ++{ ++ f(buffer, 1); ++ ++ if (!buffer[0]) ++ abort(); ++ ++ return 0; ++} + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch new file mode 100644 index 0000000000..f75a74091f --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch @@ -0,0 +1,138 @@ +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + Mark Shinwell + + gcc/ + * config/arm/vfp.md (*arm_movsi_vfp, *thumb2_movsi_vfp) + (*arm_movdi_vfp, *thumb2_movdi_vfp, *movsf_vfp, *thumb2_movsf_vfp) + (*movdf_vfp, *thumb2_movdf_vfp, *movsfcc_vfp, *thumb2_movsfcc_vfp) + (*movdfcc_vfp, *thumb2_movdfcc_vfp): Add neon_type. + * config/arm/arm.md (neon_type): Update comment. + + 2010-08-10 Andrew Stubbs + + gcc/ + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-10 13:31:21 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-12 11:29:02 +0000 +@@ -255,8 +255,6 @@ + (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))) + + ;; Classification of NEON instructions for scheduling purposes. +-;; Do not set this attribute and the "type" attribute together in +-;; any one instruction pattern. + (define_attr "neon_type" + "neon_int_1,\ + neon_int_2,\ + +=== modified file 'gcc/config/arm/vfp.md' +--- old/gcc/config/arm/vfp.md 2010-08-10 13:31:21 +0000 ++++ new/gcc/config/arm/vfp.md 2010-08-12 11:29:02 +0000 +@@ -82,6 +82,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") ++ (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") + (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] + ) +@@ -123,6 +124,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store") ++ (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") + (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] + ) +@@ -160,6 +162,7 @@ + } + " + [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") ++ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") + (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) + (eq_attr "alternative" "5") + (if_then_else +@@ -198,6 +201,7 @@ + } + " + [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store") ++ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") + (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) + (eq_attr "alternative" "5") + (if_then_else +@@ -352,6 +356,7 @@ + [(set_attr "predicable" "yes") + (set_attr "type" + "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") ++ (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") + (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") + (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] + ) +@@ -388,6 +393,7 @@ + [(set_attr "predicable" "yes") + (set_attr "type" + "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*") ++ (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") + (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*") + (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] + ) +@@ -430,6 +436,7 @@ + " + [(set_attr "type" + "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") ++ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") + (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) + (eq_attr "alternative" "7") + (if_then_else +@@ -474,6 +481,7 @@ + " + [(set_attr "type" + "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*") ++ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") + (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) + (eq_attr "alternative" "7") + (if_then_else +@@ -509,7 +517,8 @@ + fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" + [(set_attr "conds" "use") + (set_attr "length" "4,4,8,4,4,8,4,4,8") +- (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] ++ (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") ++ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")] + ) + + (define_insn "*thumb2_movsfcc_vfp" +@@ -532,7 +541,8 @@ + ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" + [(set_attr "conds" "use") + (set_attr "length" "6,6,10,6,6,10,6,6,10") +- (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] ++ (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") ++ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")] + ) + + (define_insn "*movdfcc_vfp" +@@ -555,7 +565,8 @@ + fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" + [(set_attr "conds" "use") + (set_attr "length" "4,4,8,4,4,8,4,4,8") +- (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] ++ (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") ++ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")] + ) + + (define_insn "*thumb2_movdfcc_vfp" +@@ -578,7 +589,8 @@ + ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" + [(set_attr "conds" "use") + (set_attr "length" "6,6,10,6,6,10,6,6,10") +- (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] ++ (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") ++ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")] + ) + + + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch new file mode 100644 index 0000000000..9b56560942 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch @@ -0,0 +1,95 @@ + gcc/ + * config/arm/arm.c (arm_override_options): Override alignments if + tuning for Cortex-A8. + (create_fix_barrier, arm_reorg): If aligning to jumps or loops, + make labels have a size. + * config/arm/arm.md (VUNSPEC_ALIGN16, VUNSPEC_ALIGN32): New constants. + (align_16, align_32): New patterns. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + Mark Shinwell + + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-10 14:03:02 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-12 11:33:54 +0000 +@@ -1449,6 +1449,16 @@ + chosen. */ + gcc_assert (arm_tune != arm_none); + ++ if (arm_tune == cortexa8 && optimize >= 3) ++ { ++ /* These alignments were experimentally determined to improve SPECint ++ performance on SPECCPU 2000. */ ++ if (align_functions <= 0) ++ align_functions = 16; ++ if (align_jumps <= 0) ++ align_jumps = 16; ++ } ++ + tune_flags = all_cores[(int)arm_tune].flags; + + if (target_fp16_format_name) +@@ -11263,7 +11273,10 @@ + gcc_assert (GET_CODE (from) != BARRIER); + + /* Count the length of this insn. */ +- count += get_attr_length (from); ++ if (LABEL_P (from) && (align_jumps > 0 || align_loops > 0)) ++ count += MAX (align_jumps, align_loops); ++ else ++ count += get_attr_length (from); + + /* If there is a jump table, add its length. */ + tmp = is_jump_table (from); +@@ -11603,6 +11616,8 @@ + insn = table; + } + } ++ else if (LABEL_P (insn) && (align_jumps > 0 || align_loops > 0)) ++ address += MAX (align_jumps, align_loops); + } + + fix = minipool_fix_head; + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-12 11:29:02 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-12 11:33:54 +0000 +@@ -135,6 +135,8 @@ + (VUNSPEC_WCMP_EQ 12) ; Used by the iWMMXt WCMPEQ instructions + (VUNSPEC_WCMP_GTU 13) ; Used by the iWMMXt WCMPGTU instructions + (VUNSPEC_WCMP_GT 14) ; Used by the iwMMXT WCMPGT instructions ++ (VUNSPEC_ALIGN16 15) ; Used to force 16-byte alignment. ++ (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment. + (VUNSPEC_EH_RETURN 20); Use to override the return address for exception + ; handling. + ] +@@ -11042,6 +11044,24 @@ + " + ) + ++(define_insn "align_16" ++ [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN16)] ++ "TARGET_EITHER" ++ "* ++ assemble_align (128); ++ return \"\"; ++ " ++) ++ ++(define_insn "align_32" ++ [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN32)] ++ "TARGET_EITHER" ++ "* ++ assemble_align (256); ++ return \"\"; ++ " ++) ++ + (define_insn "consttable_end" + [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)] + "TARGET_EITHER" + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch new file mode 100644 index 0000000000..850acb31b0 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch @@ -0,0 +1,36 @@ + 2008-09-08 Daniel Jacobowitz + + gcc/ + * config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test + for barrier handlers. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + gcc/ + * config/arm/arm.c (arm_override_options): Override alignments if + tuning for Cortex-A8. + +=== modified file 'gcc/config/arm/unwind-arm.c' +--- old/gcc/config/arm/unwind-arm.c 2009-10-30 14:55:10 +0000 ++++ new/gcc/config/arm/unwind-arm.c 2010-08-12 12:39:35 +0000 +@@ -1196,8 +1196,6 @@ + ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1]; + + if (data[0] & uint32_highbit) +- phase2_call_unexpected_after_unwind = 1; +- else + { + data += rtti_count + 1; + /* Setup for entry to the handler. */ +@@ -1207,6 +1205,8 @@ + _Unwind_SetGR (context, 0, (_uw) ucbp); + return _URC_INSTALL_CONTEXT; + } ++ else ++ phase2_call_unexpected_after_unwind = 1; + } + if (data[0] & uint32_highbit) + data++; + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch new file mode 100644 index 0000000000..632e80caf7 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch @@ -0,0 +1,111 @@ + 2009-06-23 Kazu Hirata + + Issue #4613 + gcc/ + * config/arm/arm.c (arm_rtx_costs_1): Teach that the cost of MLS + is the same as its underlying multiplication. + * config/arm/arm.md (two splitters): New. + * config/arm/predicates.md (binary_operator): New. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2008-09-08 Daniel Jacobowitz + + gcc/ + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-12 11:33:54 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-12 13:35:39 +0000 +@@ -6604,6 +6604,19 @@ + return true; + } + ++ /* MLS is just as expensive as its underlying multiplication. ++ Exclude a shift by a constant, which is expressed as a ++ multiplication. */ ++ if (TARGET_32BIT && arm_arch_thumb2 ++ && GET_CODE (XEXP (x, 1)) == MULT ++ && ! (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT ++ && ((INTVAL (XEXP (XEXP (x, 1), 1)) & ++ (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) ++ { ++ /* The cost comes from the cost of the multiply. */ ++ return false; ++ } ++ + /* Fall through */ + + case PLUS: + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-12 11:33:54 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-12 13:35:39 +0000 +@@ -1355,6 +1355,49 @@ + (set_attr "predicable" "yes")] + ) + ++; The combiner cannot combine the first and last insns in the ++; following sequence because of the intervening insn, so help the ++; combiner with this splitter. The combiner does attempt to split ++; this particular combination but does not know this exact split. ++; Note that the combiner puts the constant at the outermost operation ++; as a part of canonicalization. ++; ++; mul r3, r2, r1 ++; r3, r3, ++; add r3, r3, r4 ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operator:SI 1 "plusminus_operator" ++ [(plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 3 "s_register_operand" "")) ++ (match_operand:SI 4 "s_register_operand" "")) ++ (match_operand:SI 5 "arm_immediate_operand" "")]))] ++ "TARGET_32BIT" ++ [(set (match_dup 0) ++ (plus:SI (mult:SI (match_dup 2) (match_dup 3)) ++ (match_dup 4))) ++ (set (match_dup 0) ++ (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))] ++ "") ++ ++; Likewise for MLS. MLS is available only on select architectures. ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operator:SI 1 "plusminus_operator" ++ [(minus:SI (match_operand:SI 2 "s_register_operand" "") ++ (mult:SI (match_operand:SI 3 "s_register_operand" "") ++ (match_operand:SI 4 "s_register_operand" ""))) ++ (match_operand:SI 5 "arm_immediate_operand" "")]))] ++ "TARGET_32BIT && arm_arch_thumb2" ++ [(set (match_dup 0) ++ (minus:SI (match_dup 2) ++ (mult:SI (match_dup 3) (match_dup 4)))) ++ (set (match_dup 0) ++ (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))] ++ "") ++ + (define_insn "*mulsi3addsi_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2010-08-10 13:31:21 +0000 ++++ new/gcc/config/arm/predicates.md 2010-08-12 13:35:39 +0000 +@@ -197,6 +197,11 @@ + (and (match_code "plus,minus,ior,xor,and") + (match_test "mode == GET_MODE (op)"))) + ++;; True for plus/minus operators ++(define_special_predicate "plusminus_operator" ++ (and (match_code "plus,minus") ++ (match_test "mode == GET_MODE (op)"))) ++ + ;; True for logical binary operators. + (define_special_predicate "logical_binary_operator" + (and (match_code "ior,xor,and") + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch new file mode 100644 index 0000000000..f4a8e80ab7 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch @@ -0,0 +1,236 @@ + Backport from FSF mainline: + + gcc/ + * gengtype-lex.l: Add HARD_REG_SET. + * expr.c (expand_expr_real_1): Record writes to hard registers. + * function.h (rtl_data): Add asm_clobbers. + * ira.c (compute_regs_asm_clobbered): Use crtl->asm_clobbers. + (ira_setup_eliminable_regset): Remove regs_asm_clobbered. + Use crtl->asm_clobbers. + + gcc/testsuite/ + * gcc.target/arm/frame-pointer-1.c: New test. + * gcc.target/i386/pr9771-1.c: Move code out of main to allow frame + pointer elimination. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2009-06-23 Kazu Hirata + +=== modified file 'gcc/expr.c' +--- old/gcc/expr.c 2010-05-31 14:45:06 +0000 ++++ new/gcc/expr.c 2010-08-12 13:51:16 +0000 +@@ -8458,6 +8458,19 @@ + expand_decl_rtl: + gcc_assert (decl_rtl); + decl_rtl = copy_rtx (decl_rtl); ++ /* Record writes to register variables. */ ++ if (modifier == EXPAND_WRITE && REG_P (decl_rtl) ++ && REGNO (decl_rtl) < FIRST_PSEUDO_REGISTER) ++ { ++ int i = REGNO (decl_rtl); ++ int nregs = hard_regno_nregs[i][GET_MODE (decl_rtl)]; ++ while (nregs) ++ { ++ SET_HARD_REG_BIT (crtl->asm_clobbers, i); ++ i++; ++ nregs--; ++ } ++ } + + /* Ensure variable marked as used even if it doesn't go through + a parser. If it hasn't be used yet, write out an external + +=== modified file 'gcc/function.h' +--- old/gcc/function.h 2009-11-25 10:55:54 +0000 ++++ new/gcc/function.h 2010-08-12 13:51:16 +0000 +@@ -25,6 +25,7 @@ + #include "tree.h" + #include "hashtab.h" + #include "vecprim.h" ++#include "hard-reg-set.h" + + /* Stack of pending (incomplete) sequences saved by `start_sequence'. + Each element describes one pending sequence. +@@ -433,6 +434,12 @@ + TREE_NOTHROW (current_function_decl) it is set even for overwritable + function where currently compiled version of it is nothrow. */ + bool nothrow; ++ ++ /* Like regs_ever_live, but 1 if a reg is set or clobbered from an ++ asm. Unlike regs_ever_live, elements of this array corresponding ++ to eliminable regs (like the frame pointer) are set if an asm ++ sets them. */ ++ HARD_REG_SET asm_clobbers; + }; + + #define return_label (crtl->x_return_label) + +=== modified file 'gcc/gengtype-lex.l' +--- old/gcc/gengtype-lex.l 2009-11-21 10:24:25 +0000 ++++ new/gcc/gengtype-lex.l 2010-08-12 13:51:16 +0000 +@@ -49,7 +49,7 @@ + ID [[:alpha:]_][[:alnum:]_]* + WS [[:space:]]+ + HWS [ \t\r\v\f]* +-IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t ++IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t|HARD_REG_SET + ITYPE {IWORD}({WS}{IWORD})* + EOID [^[:alnum:]_] + + +=== modified file 'gcc/ira.c' +--- old/gcc/ira.c 2010-03-31 01:44:10 +0000 ++++ new/gcc/ira.c 2010-08-12 13:51:16 +0000 +@@ -1385,14 +1385,12 @@ + return for_each_rtx (&insn, insn_contains_asm_1, NULL); + } + +-/* Set up regs_asm_clobbered. */ ++/* Add register clobbers from asm statements. */ + static void +-compute_regs_asm_clobbered (char *regs_asm_clobbered) ++compute_regs_asm_clobbered (void) + { + basic_block bb; + +- memset (regs_asm_clobbered, 0, sizeof (char) * FIRST_PSEUDO_REGISTER); +- + FOR_EACH_BB (bb) + { + rtx insn; +@@ -1413,7 +1411,7 @@ + + hard_regno_nregs[dregno][mode] - 1; + + for (i = dregno; i <= end; ++i) +- regs_asm_clobbered[i] = 1; ++ SET_HARD_REG_BIT(crtl->asm_clobbers, i); + } + } + } +@@ -1425,12 +1423,6 @@ + void + ira_setup_eliminable_regset (void) + { +- /* Like regs_ever_live, but 1 if a reg is set or clobbered from an +- asm. Unlike regs_ever_live, elements of this array corresponding +- to eliminable regs (like the frame pointer) are set if an asm +- sets them. */ +- char *regs_asm_clobbered +- = (char *) alloca (FIRST_PSEUDO_REGISTER * sizeof (char)); + #ifdef ELIMINABLE_REGS + int i; + static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; +@@ -1454,7 +1446,8 @@ + COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); + CLEAR_HARD_REG_SET (eliminable_regset); + +- compute_regs_asm_clobbered (regs_asm_clobbered); ++ compute_regs_asm_clobbered (); ++ + /* Build the regset of all eliminable registers and show we can't + use those that we already know won't be eliminated. */ + #ifdef ELIMINABLE_REGS +@@ -1464,7 +1457,7 @@ + = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) + || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp)); + +- if (! regs_asm_clobbered[eliminables[i].from]) ++ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) + { + SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); + +@@ -1478,7 +1471,7 @@ + df_set_regs_ever_live (eliminables[i].from, true); + } + #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM +- if (! regs_asm_clobbered[HARD_FRAME_POINTER_REGNUM]) ++ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) + { + SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); + if (need_fp) +@@ -1492,7 +1485,7 @@ + #endif + + #else +- if (! regs_asm_clobbered[FRAME_POINTER_REGNUM]) ++ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) + { + SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); + if (need_fp) + +=== added file 'gcc/testsuite/gcc.target/arm/frame-pointer-1.c' +--- old/gcc/testsuite/gcc.target/arm/frame-pointer-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/frame-pointer-1.c 2010-08-12 13:51:16 +0000 +@@ -0,0 +1,42 @@ ++/* Check local register variables using a register conventionally ++ used as the frame pointer aren't clobbered under high register pressure. */ ++/* { dg-do run } */ ++/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */ ++ ++#include ++ ++int global=5; ++ ++void __attribute__((noinline)) foo(int p1, int p2, int p3, int p4) ++{ ++ if (global != 5 || p1 != 1 || p2 != 2 || p3 != 3 || p4 != 4) ++ abort(); ++} ++ ++int __attribute__((noinline)) test(int a, int b, int c, int d) ++{ ++ register unsigned long r __asm__("r7") = 0xdeadbeef; ++ int e; ++ ++ /* ABCD are live after the call which should be enough ++ to cause r7 to be used if it weren't for the register variable. */ ++ foo(a,b,c,d); ++ ++ e = 0; ++ __asm__ __volatile__ ("mov %0, %2" ++ : "=r" (e) ++ : "0" (e), "r" (r)); ++ ++ global = a+b+c+d; ++ ++ return e; ++} ++ ++int main() ++{ ++ if (test(1, 2, 3, 4) != 0xdeadbeef) ++ abort(); ++ if (global != 10) ++ abort(); ++ return 0; ++} + +=== modified file 'gcc/testsuite/gcc.target/i386/pr9771-1.c' +--- old/gcc/testsuite/gcc.target/i386/pr9771-1.c 2007-08-22 08:59:14 +0000 ++++ new/gcc/testsuite/gcc.target/i386/pr9771-1.c 2010-08-12 13:51:16 +0000 +@@ -28,7 +28,10 @@ + *adr = save; + } + +-int main() ++/* This must not be inlined becuase main() requires the frame pointer ++ for stack alignment. */ ++void test(void) __attribute__((noinline)); ++void test(void) + { + B = &x; + +@@ -42,3 +45,9 @@ + exit(0); + } + ++int main() ++{ ++ test(); ++ return 0; ++ ++} + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch new file mode 100644 index 0000000000..31fa99a2e3 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch @@ -0,0 +1,43 @@ + Merge from Sourcery G++ 4.4: + + 2009-08-26 Kazu Hirata + + Issue #6089 + gcc/ + * config/arm/arm.c (arm_rtx_costs_1): Don't special case for + Thumb-2 in the MINUS case. + +2010-07-26 Julian Brown + + Backport from FSF mainline: + + gcc/ + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-12 13:35:39 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-12 14:08:29 +0000 +@@ -6494,23 +6494,6 @@ + return true; + + case MINUS: +- if (TARGET_THUMB2) +- { +- if (GET_MODE_CLASS (mode) == MODE_FLOAT) +- { +- if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) +- *total = COSTS_N_INSNS (1); +- else +- *total = COSTS_N_INSNS (20); +- } +- else +- *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); +- /* Thumb2 does not have RSB, so all arguments must be +- registers (subtracting a constant is canonicalized as +- addition of the negated constant). */ +- return false; +- } +- + if (mode == DImode) + { + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch new file mode 100644 index 0000000000..d9073123c4 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch @@ -0,0 +1,28 @@ + 2009-08-26 Julian Brown + + gcc/config/arm/ + * uclinux-eabi.h (LINK_GCC_C_SEQUENCE_SPEC): Override definition + for uclinux. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2009-08-26 Kazu Hirata + + +=== modified file 'gcc/config/arm/uclinux-eabi.h' +--- old/gcc/config/arm/uclinux-eabi.h 2009-02-20 15:20:38 +0000 ++++ new/gcc/config/arm/uclinux-eabi.h 2010-08-12 15:23:21 +0000 +@@ -50,6 +50,10 @@ + #undef ARM_DEFAULT_ABI + #define ARM_DEFAULT_ABI ARM_ABI_AAPCS_LINUX + ++#undef LINK_GCC_C_SEQUENCE_SPEC ++#define LINK_GCC_C_SEQUENCE_SPEC \ ++ "--start-group %G %L --end-group" ++ + /* Clear the instruction cache from `beg' to `end'. This makes an + inline system call to SYS_cacheflush. */ + #undef CLEAR_INSN_CACHE + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch new file mode 100644 index 0000000000..02db2b4e7e --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch @@ -0,0 +1,76 @@ + 2010-05-25 Julian Brown + + gcc/ + * config/arm/arm.c (arm_tune_cortex_a5): New. + (arm_override_options): Set above. Set max_insns_skipped to 1 for + Cortex-A5. + * config/arm/arm.h (arm_tune_cortex_a5): Add declaration. + (BRANCH_COST): Set to zero for Cortex-A5 unless optimising for + size. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2009-08-26 Julian Brown + + gcc/config/arm/ + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-12 14:08:29 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-12 16:18:41 +0000 +@@ -671,6 +671,9 @@ + This typically means an ARM6 or ARM7 with MMU or MPU. */ + int arm_tune_wbuf = 0; + ++/* Nonzero if tuning for Cortex-A5. */ ++int arm_tune_cortex_a5 = 0; ++ + /* Nonzero if tuning for Cortex-A9. */ + int arm_tune_cortex_a9 = 0; + +@@ -1582,6 +1585,7 @@ + arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; + arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; + arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; ++ arm_tune_cortex_a5 = (arm_tune == cortexa5) != 0; + arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; + + /* If we are not using the default (ARM mode) section anchor offset +@@ -1880,6 +1884,11 @@ + that is worth skipping is shorter. */ + if (arm_tune_strongarm) + max_insns_skipped = 3; ++ ++ /* Branches can be dual-issued on Cortex-A5, so conditional execution is ++ less appealing. */ ++ if (arm_tune_cortex_a5) ++ max_insns_skipped = 1; + } + + /* Hot/Cold partitioning is not currently supported, since we can't + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-05 16:34:46 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-12 16:18:41 +0000 +@@ -435,6 +435,9 @@ + /* Nonzero if tuning for stores via the write buffer. */ + extern int arm_tune_wbuf; + ++/* Nonzero if tuning for Cortex-A5. */ ++extern int arm_tune_cortex_a5; ++ + /* Nonzero if tuning for Cortex-A9. */ + extern int arm_tune_cortex_a9; + +@@ -2222,7 +2225,8 @@ + /* Try to generate sequences that don't involve branches, we can then use + conditional instructions */ + #define BRANCH_COST(speed_p, predictable_p) \ +- (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \ ++ (TARGET_32BIT ? ((arm_tune_cortex_a5 && !optimize_size) ? 0 \ ++ : (TARGET_THUMB2 && optimize_size ? 1 : 4)) \ + : (optimize > 0 ? 2 : 0)) + + /* Position Independent Code. */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch new file mode 100644 index 0000000000..86b2d81093 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch @@ -0,0 +1,132 @@ + Backport from FSF mainline: + + gcc/ + * config/arm/thumb2.md (*thumb2_addsi3_compare0): New. + (*thumb2_addsi3_compare0_scratch): New. + * config/arm/constraints.md (Pv): New. + * config/arm/arm.md (*addsi3_compare0): Remove FIXME comment. Use + for ARM mode only. + (*addsi3_compare0_scratch): Likewise. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-05-25 Julian Brown + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-12 13:35:39 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-12 16:47:21 +0000 +@@ -701,7 +701,6 @@ + "" + ) + +-;; ??? Make Thumb-2 variants which prefer low regs + (define_insn "*addsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +@@ -710,7 +709,7 @@ + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r,r") + (plus:SI (match_dup 1) (match_dup 2)))] +- "TARGET_32BIT" ++ "TARGET_ARM" + "@ + add%.\\t%0, %1, %2 + sub%.\\t%0, %1, #%n2" +@@ -723,7 +722,7 @@ + (plus:SI (match_operand:SI 0 "s_register_operand" "r, r") + (match_operand:SI 1 "arm_add_operand" "rI,L")) + (const_int 0)))] +- "TARGET_32BIT" ++ "TARGET_ARM" + "@ + cmn%?\\t%0, %1 + cmp%?\\t%0, #%n1" + +=== modified file 'gcc/config/arm/constraints.md' +--- old/gcc/config/arm/constraints.md 2010-07-29 16:58:56 +0000 ++++ new/gcc/config/arm/constraints.md 2010-08-12 16:47:21 +0000 +@@ -31,7 +31,7 @@ + ;; The following multi-letter normal constraints have been used: + ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di + ;; in Thumb-1 state: Pa, Pb +-;; in Thumb-2 state: Ps, Pt ++;; in Thumb-2 state: Ps, Pt, Pv + + ;; The following memory constraints have been used: + ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us +@@ -158,6 +158,11 @@ + (and (match_code "const_int") + (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7"))) + ++(define_constraint "Pv" ++ "@internal In Thumb-2 state a constant in the range -255 to 0" ++ (and (match_code "const_int") ++ (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0"))) ++ + (define_constraint "G" + "In ARM/Thumb-2 state a valid FPA immediate constant." + (and (match_code "const_double") + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2010-08-05 16:34:46 +0000 ++++ new/gcc/config/arm/thumb2.md 2010-08-12 16:47:21 +0000 +@@ -1241,6 +1241,56 @@ + (set_attr "length" "2")] + ) + ++(define_insn "*thumb2_addsi3_compare0" ++ [(set (reg:CC_NOOV CC_REGNUM) ++ (compare:CC_NOOV ++ (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r") ++ (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL")) ++ (const_int 0))) ++ (set (match_operand:SI 0 "s_register_operand" "=l,l,r") ++ (plus:SI (match_dup 1) (match_dup 2)))] ++ "TARGET_THUMB2" ++ "* ++ HOST_WIDE_INT val; ++ ++ if (GET_CODE (operands[2]) == CONST_INT) ++ val = INTVAL (operands[2]); ++ else ++ val = 0; ++ ++ if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val))) ++ return \"subs\\t%0, %1, #%n2\"; ++ else ++ return \"adds\\t%0, %1, %2\"; ++ " ++ [(set_attr "conds" "set") ++ (set_attr "length" "2,2,4")] ++) ++ ++(define_insn "*thumb2_addsi3_compare0_scratch" ++ [(set (reg:CC_NOOV CC_REGNUM) ++ (compare:CC_NOOV ++ (plus:SI (match_operand:SI 0 "s_register_operand" "l, r") ++ (match_operand:SI 1 "arm_add_operand" "lPv,rIL")) ++ (const_int 0)))] ++ "TARGET_THUMB2" ++ "* ++ HOST_WIDE_INT val; ++ ++ if (GET_CODE (operands[1]) == CONST_INT) ++ val = INTVAL (operands[1]); ++ else ++ val = 0; ++ ++ if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val))) ++ return \"cmp\\t%0, #%n1\"; ++ else ++ return \"cmn\\t%0, %1\"; ++ " ++ [(set_attr "conds" "set") ++ (set_attr "length" "2,4")] ++) ++ + ;; 16-bit encodings of "muls" and "mul". We only use these when + ;; optimizing for size since "muls" is slow on all known + ;; implementations and since "mul" will be generated by + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch new file mode 100644 index 0000000000..d03ee9406e --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch @@ -0,0 +1,30 @@ + 2010-02-03 Daniel Gutson + + Issue #6472 + + gcc/ + * config/arm/lib1funcs.asm (__ARM_ARCH__): __ARM_ARCH_7EM__ + added to the preprocessor condition. + +2010-07-26 Julian Brown + + Backport from FSF mainline: + + gcc/ + * config/arm/thumb2.md (*thumb2_addsi3_compare0): New. + (*thumb2_addsi3_compare0_scratch): New. + +=== modified file 'gcc/config/arm/lib1funcs.asm' +--- old/gcc/config/arm/lib1funcs.asm 2010-08-05 15:20:54 +0000 ++++ new/gcc/config/arm/lib1funcs.asm 2010-08-12 16:49:44 +0000 +@@ -104,7 +104,8 @@ + #endif + + #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ +- || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) ++ || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ ++ || defined(__ARM_ARCH_7EM__) + # define __ARM_ARCH__ 7 + #endif + + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch new file mode 100644 index 0000000000..757e66c8b4 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch @@ -0,0 +1,30 @@ + Merge from Sourcery G++ 4.4: + + 2010-02-04 Daniel Jacobowitz + + Issue #7197 - backtrace() through throw() + + libstdc++-v3/ + * libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): For + ARM EABI, skip handlers for _US_VIRTUAL_UNWIND_FRAME + | _US_FORCE_UNWIND. + +2010-07-26 Julian Brown + + Backport from FSF mainline: + + 2010-02-03 Daniel Gutson + +=== modified file 'libstdc++-v3/libsupc++/eh_personality.cc' +--- old/libstdc++-v3/libsupc++/eh_personality.cc 2010-02-17 05:43:24 +0000 ++++ new/libstdc++-v3/libsupc++/eh_personality.cc 2010-08-12 16:53:10 +0000 +@@ -383,6 +383,8 @@ + switch (state & _US_ACTION_MASK) + { + case _US_VIRTUAL_UNWIND_FRAME: ++ if (state & _US_FORCE_UNWIND) ++ CONTINUE_UNWINDING; + actions = _UA_SEARCH_PHASE; + break; + + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch new file mode 100644 index 0000000000..4807195158 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch @@ -0,0 +1,170 @@ + Backport from FSF mainline: + + Julian Brown + Mark Mitchell + + gcc/ + * config/arm/arm.c (arm_function_ok_for_sibcall): Only forbid + sibling calls for Thumb-1. + * config/arm/arm.h (USE_RETURN_INSN): Enable for Thumb-2. + * config/arm/arm.md (*call_symbol, *call_value_symbol): Use for + Thumb-2. + (*call_insn, *call_value_insn): Don't use for Thumb-2. + (sibcall, sibcall_value, *sibcall_insn, *sibcall_value_insn): Use + for Thumb-2. + (return): New expander. + (*arm_return): New name for ARM return insn. + * config/arm/thumb2.md (*thumb2_return): New insn pattern. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-02-04 Daniel Jacobowitz + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-12 16:18:41 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-13 10:30:35 +0000 +@@ -4886,8 +4886,8 @@ + return false; + + /* Never tailcall something for which we have no decl, or if we +- are in Thumb mode. */ +- if (decl == NULL || TARGET_THUMB) ++ are generating code for Thumb-1. */ ++ if (decl == NULL || TARGET_THUMB1) + return false; + + /* The PIC register is live on entry to VxWorks PLT entries, so we + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-12 16:18:41 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-13 10:30:35 +0000 +@@ -1833,11 +1833,8 @@ + + /* Determine if the epilogue should be output as RTL. + You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ +-/* This is disabled for Thumb-2 because it will confuse the +- conditional insn counter. +- Do not use a return insn if we're avoiding ldm/stm instructions. */ + #define USE_RETURN_INSN(ISCOND) \ +- ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0) ++ ((TARGET_32BIT && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0) + + /* Definitions for register eliminations. + + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-12 16:47:21 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-13 10:30:35 +0000 +@@ -8798,7 +8798,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM ++ "TARGET_32BIT + && (GET_CODE (operands[0]) == SYMBOL_REF) + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" + "* +@@ -8814,7 +8814,7 @@ + (match_operand:SI 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM ++ "TARGET_32BIT + && (GET_CODE (operands[1]) == SYMBOL_REF) + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" + "* +@@ -8829,7 +8829,7 @@ + (match_operand:SI 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_THUMB ++ "TARGET_THUMB1 + && GET_CODE (operands[0]) == SYMBOL_REF + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" + "bl\\t%a0" +@@ -8843,7 +8843,7 @@ + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_THUMB ++ "TARGET_THUMB1 + && GET_CODE (operands[1]) == SYMBOL_REF + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" + "bl\\t%a1" +@@ -8857,7 +8857,7 @@ + (match_operand 1 "general_operand" "")) + (return) + (use (match_operand 2 "" ""))])] +- "TARGET_ARM" ++ "TARGET_32BIT" + " + { + if (operands[2] == NULL_RTX) +@@ -8871,7 +8871,7 @@ + (match_operand 2 "general_operand" ""))) + (return) + (use (match_operand 3 "" ""))])] +- "TARGET_ARM" ++ "TARGET_32BIT" + " + { + if (operands[3] == NULL_RTX) +@@ -8884,7 +8884,7 @@ + (match_operand 1 "" "")) + (return) + (use (match_operand 2 "" ""))] +- "TARGET_ARM && GET_CODE (operands[0]) == SYMBOL_REF" ++ "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF" + "* + return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; + " +@@ -8897,15 +8897,20 @@ + (match_operand 2 "" ""))) + (return) + (use (match_operand 3 "" ""))] +- "TARGET_ARM && GET_CODE (operands[1]) == SYMBOL_REF" ++ "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF" + "* + return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; + " + [(set_attr "type" "call")] + ) + ++(define_expand "return" ++ [(return)] ++ "TARGET_32BIT && USE_RETURN_INSN (FALSE)" ++ "") ++ + ;; Often the return insn will be the same as loading from memory, so set attr +-(define_insn "return" ++(define_insn "*arm_return" + [(return)] + "TARGET_ARM && USE_RETURN_INSN (FALSE)" + "* + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2010-08-12 16:47:21 +0000 ++++ new/gcc/config/arm/thumb2.md 2010-08-13 10:30:35 +0000 +@@ -1054,6 +1054,19 @@ + (set_attr "length" "20")] + ) + ++;; Note: this is not predicable, to avoid issues with linker-generated ++;; interworking stubs. ++(define_insn "*thumb2_return" ++ [(return)] ++ "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)" ++ "* ++ { ++ return output_return_instruction (const_true_rtx, TRUE, FALSE); ++ }" ++ [(set_attr "type" "load1") ++ (set_attr "length" "12")] ++) ++ + (define_insn_and_split "thumb2_eh_return" + [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")] + VUNSPEC_EH_RETURN) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch new file mode 100644 index 0000000000..57b8605e55 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch @@ -0,0 +1,83 @@ + Merge from Sourcery G++ 4.4: + + 2010-02-15 Julian Brown + + Issue #7486 + + gcc/ + * config/arm/arm.c (arm_libcall_uses_aapcs_base) + (arm_init_cumulative_args): Use correct ABI for double-precision + helper functions in hard-float mode if only single-precision + arithmetic is supported in hardware. + +2010-07-26 Julian Brown + + Backport from FSF mainline: + + Julian Brown + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-13 10:30:35 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-13 10:43:42 +0000 +@@ -3453,6 +3453,28 @@ + convert_optab_libfunc (sfix_optab, DImode, SFmode)); + add_libcall (libcall_htab, + convert_optab_libfunc (ufix_optab, DImode, SFmode)); ++ ++ /* Values from double-precision helper functions are returned in core ++ registers if the selected core only supports single-precision ++ arithmetic, even if we are using the hard-float ABI. */ ++ if (TARGET_VFP) ++ { ++ add_libcall (libcall_htab, optab_libfunc (add_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (sdiv_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (smul_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (neg_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (sub_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (eq_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (lt_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (le_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (ge_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (gt_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (unord_optab, DFmode)); ++ add_libcall (libcall_htab, ++ convert_optab_libfunc (sext_optab, DFmode, SFmode)); ++ add_libcall (libcall_htab, ++ convert_optab_libfunc (trunc_optab, SFmode, DFmode)); ++ } + } + + return libcall && htab_find (libcall_htab, libcall) != NULL; +@@ -4406,6 +4428,31 @@ + if (arm_libcall_uses_aapcs_base (libname)) + pcum->pcs_variant = ARM_PCS_AAPCS; + ++ /* We must pass arguments to double-precision helper functions in core ++ registers if we only have hardware support for single-precision ++ arithmetic, even if we are using the hard-float ABI. */ ++ if (TARGET_VFP ++ && (rtx_equal_p (libname, optab_libfunc (add_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (sdiv_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (smul_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (neg_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (sub_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (eq_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (lt_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (le_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (ge_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (gt_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (unord_optab, DFmode)) ++ || rtx_equal_p (libname, convert_optab_libfunc (sext_optab, ++ DFmode, SFmode)) ++ || rtx_equal_p (libname, convert_optab_libfunc (trunc_optab, ++ SFmode, DFmode)) ++ || rtx_equal_p (libname, convert_optab_libfunc (sfix_optab, ++ SImode, DFmode)) ++ || rtx_equal_p (libname, convert_optab_libfunc (ufix_optab, ++ SImode, DFmode)))) ++ pcum->pcs_variant = ARM_PCS_AAPCS; ++ + pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0; + pcum->aapcs_reg = NULL_RTX; + pcum->aapcs_partial = 0; + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch new file mode 100644 index 0000000000..f99938a7f1 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch @@ -0,0 +1,37 @@ + 2010-02-23 Julian Brown + + gcc/ + * calls.c (precompute_register_parameters): Avoid generating a + register move if optimizing for size. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-02-15 Julian Brown + + Issue #7486 + +=== modified file 'gcc/calls.c' +--- old/gcc/calls.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/calls.c 2010-08-13 10:50:45 +0000 +@@ -703,7 +703,9 @@ + + For small register classes, also do this if this call uses + register parameters. This is to avoid reload conflicts while +- loading the parameters registers. */ ++ loading the parameters registers. ++ ++ Avoid creating the extra move if optimizing for size. */ + + else if ((! (REG_P (args[i].value) + || (GET_CODE (args[i].value) == SUBREG +@@ -711,6 +713,7 @@ + && args[i].mode != BLKmode + && rtx_cost (args[i].value, SET, optimize_insn_for_speed_p ()) + > COSTS_N_INSNS (1) ++ && !optimize_size + && ((SMALL_REGISTER_CLASSES && *reg_parm_seen) + || optimize)) + args[i].value = copy_to_mode_reg (args[i].mode, args[i].value); + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch new file mode 100644 index 0000000000..a95b649e43 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch @@ -0,0 +1,401 @@ + * config/arm/arm.c (thumb2_size_rtx_costs): New. + (arm_rtx_costs): Call above for Thumb-2. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-02-23 Julian Brown + + gcc/ + * calls.c (precompute_register_parameters): Avoid generating a + register move if optimizing for size. + + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-13 10:43:42 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-13 10:55:28 +0000 +@@ -141,6 +141,7 @@ + static bool arm_have_conditional_execution (void); + static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); + static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); ++static bool thumb2_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); + static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); + static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); + static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); +@@ -7316,14 +7317,372 @@ + } + } + ++static bool ++thumb2_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ++ int *total) ++{ ++ /* Attempt to give a lower cost to RTXs which can optimistically be ++ represented as short insns, assuming that the right conditions will hold ++ later (e.g. low registers will be chosen if a short insn requires them). ++ ++ Note that we don't make wide insns cost twice as much as narrow insns, ++ because we can't prove that a particular RTX will actually use a narrow ++ insn, because not enough information is available (e.g., we don't know ++ which hard registers pseudos will be assigned). Consider these to be ++ "expected" sizes/weightings. ++ ++ (COSTS_NARROW_INSNS has the same weight as COSTS_N_INSNS.) */ ++ ++#define COSTS_NARROW_INSNS(N) ((N) * 4) ++#define COSTS_WIDE_INSNS(N) ((N) * 6) ++#define THUMB2_LIBCALL_COST COSTS_WIDE_INSNS (2) ++ enum machine_mode mode = GET_MODE (x); ++ ++ switch (code) ++ { ++ case MEM: ++ if (REG_P (XEXP (x, 0))) ++ { ++ /* Hopefully this will use a narrow ldm/stm insn. */ ++ *total = COSTS_NARROW_INSNS (1); ++ return true; ++ } ++ else if ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF ++ && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))) ++ || reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0)) ++ || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0))) ++ { ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); ++ return true; ++ } ++ else if (GET_CODE (XEXP (x, 0)) == PLUS) ++ { ++ rtx plus = XEXP (x, 0); ++ ++ if (GET_CODE (XEXP (plus, 1)) == CONST_INT) ++ { ++ HOST_WIDE_INT cst = INTVAL (XEXP (plus, 1)); ++ ++ if (cst >= 0 && cst < 256) ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); ++ else ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ ++ *total += rtx_cost (XEXP (plus, 0), code, false); ++ ++ return true; ++ } ++ } ++ ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case DIV: ++ case MOD: ++ case UDIV: ++ case UMOD: ++ if (arm_arch_hwdiv) ++ *total = COSTS_WIDE_INSNS (1); ++ else ++ *total = THUMB2_LIBCALL_COST; ++ return false; ++ ++ case ROTATE: ++ if (mode == SImode && REG_P (XEXP (x, 1))) ++ { ++ *total = COSTS_WIDE_INSNS (1) + COSTS_NARROW_INSNS (1) ++ + rtx_cost (XEXP (x, 0), code, false); ++ return true; ++ } ++ /* Fall through */ ++ ++ case ASHIFT: ++ case LSHIFTRT: ++ case ASHIFTRT: ++ if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) ++ { ++ *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); ++ return true; ++ } ++ else if (mode == SImode) ++ { ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ } ++ ++ /* Needs a libcall. */ ++ *total = THUMB2_LIBCALL_COST; ++ return false; ++ ++ case ROTATERT: ++ if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) ++ { ++ *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); ++ return true; ++ } ++ else if (mode == SImode) ++ { ++ if (GET_CODE (XEXP (x, 1)) == CONST_INT) ++ *total = COSTS_WIDE_INSNS (1) + rtx_cost (XEXP (x, 0), code, false); ++ else ++ *total = COSTS_NARROW_INSNS (1) ++ + rtx_cost (XEXP (x, 0), code, false); ++ return true; ++ } ++ ++ /* Needs a libcall. */ ++ *total = THUMB2_LIBCALL_COST; ++ return false; ++ ++ case MINUS: ++ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT ++ && (mode == SFmode || !TARGET_VFP_SINGLE)) ++ { ++ *total = COSTS_WIDE_INSNS (1); ++ return false; ++ } ++ ++ if (mode == SImode) ++ { ++ enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); ++ enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); ++ ++ if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT ++ || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT ++ || subcode1 == ROTATE || subcode1 == ROTATERT ++ || subcode1 == ASHIFT || subcode1 == LSHIFTRT ++ || subcode1 == ASHIFTRT) ++ { ++ /* It's just the cost of the two operands. */ ++ *total = 0; ++ return false; ++ } ++ ++ if (subcode1 == CONST_INT) ++ { ++ HOST_WIDE_INT cst = INTVAL (XEXP (x, 1)); ++ ++ if (cst >= 0 && cst < 256) ++ *total = COSTS_NARROW_INSNS (1); ++ else ++ *total = COSTS_WIDE_INSNS (1); ++ ++ *total += rtx_cost (XEXP (x, 0), code, false); ++ ++ return true; ++ } ++ ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ } ++ ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case PLUS: ++ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT ++ && (mode == SFmode || !TARGET_VFP_SINGLE)) ++ { ++ *total = COSTS_WIDE_INSNS (1); ++ return false; ++ } ++ ++ /* Fall through */ ++ case AND: case XOR: case IOR: ++ if (mode == SImode) ++ { ++ enum rtx_code subcode = GET_CODE (XEXP (x, 0)); ++ ++ if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT ++ || subcode == LSHIFTRT || subcode == ASHIFTRT ++ || (code == AND && subcode == NOT)) ++ { ++ /* It's just the cost of the two operands. */ ++ *total = 0; ++ return false; ++ } ++ ++ if (code == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) ++ { ++ HOST_WIDE_INT cst = INTVAL (XEXP (x, 1)); ++ ++ if ((reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0)) ++ || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0))) ++ && cst > -512 && cst < 1024) ++ /* Only approximately correct, depending on destination ++ register. */ ++ *total = COSTS_NARROW_INSNS (1); ++ else if (cst > -256 && cst < 256) ++ *total = COSTS_NARROW_INSNS (1); ++ else ++ *total = COSTS_WIDE_INSNS (1); ++ ++ *total += rtx_cost (XEXP (x, 0), code, false); ++ ++ return true; ++ } ++ ++ if (subcode == MULT ++ && power_of_two_operand (XEXP (XEXP (x, 0), 1), mode)) ++ { ++ *total = COSTS_WIDE_INSNS (1) ++ + rtx_cost (XEXP (x, 1), code, false); ++ return true; ++ } ++ } ++ ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case MULT: ++ if (mode == SImode && GET_CODE (XEXP (x, 1)) != CONST_INT) ++ { ++ /* Might be using muls. */ ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ } ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case NEG: ++ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT ++ && (mode == SFmode || !TARGET_VFP_SINGLE)) ++ { ++ *total = COSTS_WIDE_INSNS (1); ++ return false; ++ } ++ ++ /* Fall through */ ++ case NOT: ++ if (mode == SImode) ++ { ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ } ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case IF_THEN_ELSE: ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ ++ case COMPARE: ++ if (cc_register (XEXP (x, 0), VOIDmode)) ++ *total = 0; ++ else ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ ++ case ABS: ++ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT ++ && (mode == SFmode || !TARGET_VFP_SINGLE)) ++ *total = COSTS_WIDE_INSNS (1); ++ else ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)) * 2; ++ return false; ++ ++ case SIGN_EXTEND: ++ if (GET_MODE_SIZE (mode) <= 4) ++ *total = GET_CODE (XEXP (x, 0)) == MEM ? 0 : COSTS_NARROW_INSNS (1); ++ else ++ *total = COSTS_NARROW_INSNS (1) ++ + COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case ZERO_EXTEND: ++ if (GET_MODE_SIZE (mode) > 4) ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode) - 1); ++ else if (GET_CODE (XEXP (x, 0)) == MEM) ++ *total = 0; ++ else ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ ++ case CONST_INT: ++ { ++ HOST_WIDE_INT cst = INTVAL (x); ++ ++ switch (outer_code) ++ { ++ case PLUS: ++ if (cst > -256 && cst < 256) ++ *total = 0; ++ else ++ /* See note about optabs below. */ ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case MINUS: ++ case COMPARE: ++ if (cst >= 0 && cst < 256) ++ *total = 0; ++ else ++ /* See note about optabs below. */ ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case ASHIFT: ++ case ASHIFTRT: ++ case LSHIFTRT: ++ *total = 0; ++ return true; ++ ++ default: ++ /* Constants are compared explicitly against COSTS_N_INSNS (1) in ++ optabs.c, creating an alternative, larger code sequence for more ++ expensive constants). So, it doesn't pay to make some constants ++ cost more than this. */ ++ *total = COSTS_N_INSNS (1); ++ } ++ return true; ++ } ++ ++ case CONST: ++ case LABEL_REF: ++ case SYMBOL_REF: ++ *total = COSTS_WIDE_INSNS (2); ++ return true; ++ ++ case CONST_DOUBLE: ++ *total = COSTS_WIDE_INSNS (4); ++ return true; ++ ++ case HIGH: ++ case LO_SUM: ++ /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the ++ cost of these slightly. */ ++ *total = COSTS_WIDE_INSNS (1) + 1; ++ return true; ++ ++ default: ++ if (mode != VOIDmode) ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ else ++ /* A guess (inherited from arm_size_rtx_costs). */ ++ *total = COSTS_WIDE_INSNS (4); ++ return false; ++ } ++ ++ return true; ++#undef THUMB2_LIBCALL_COST ++#undef COSTS_WIDE_INSNS ++#undef COSTS_NARROW_INSNS ++} ++ + /* RTX costs when optimizing for size. */ + static bool + arm_rtx_costs (rtx x, int code, int outer_code, int *total, + bool speed) + { + if (!speed) +- return arm_size_rtx_costs (x, (enum rtx_code) code, +- (enum rtx_code) outer_code, total); ++ { ++ if (TARGET_THUMB2) ++ return thumb2_size_rtx_costs (x, (enum rtx_code) code, ++ (enum rtx_code) outer_code, total); ++ else ++ return arm_size_rtx_costs (x, (enum rtx_code) code, ++ (enum rtx_code) outer_code, total); ++ } + else + return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code, + (enum rtx_code) outer_code, + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch new file mode 100644 index 0000000000..3f66f9d157 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch @@ -0,0 +1,184 @@ + Jie Zhang + + Issue #7122 + + gcc/ + * config/arm/vfp.md (movdf_vfp): Add load double 0.0 case. + (thumb2_movdf_vfp): Likewise. Require that one of the operands be a + register. + * config/arm/constraints.md (D0): New constraint. + + gcc/testsuite/ + * gcc.target/arm/neon-load-df0.c: New test. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-02-23 Julian Brown + + gcc/ + +=== modified file 'gcc/config/arm/constraints.md' +--- old/gcc/config/arm/constraints.md 2010-08-12 16:47:21 +0000 ++++ new/gcc/config/arm/constraints.md 2010-08-13 10:59:06 +0000 +@@ -29,7 +29,7 @@ + ;; in Thumb-1 state: I, J, K, L, M, N, O + + ;; The following multi-letter normal constraints have been used: +-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di ++;; in ARM/Thumb-2 state: D0, Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy + ;; in Thumb-1 state: Pa, Pb + ;; in Thumb-2 state: Ps, Pt, Pv + +@@ -173,6 +173,13 @@ + (and (match_code "const_double") + (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)"))) + ++(define_constraint "D0" ++ "@internal ++ In ARM/Thumb-2 state a 0.0 floating point constant which can ++ be loaded with a Neon vmov immediate instruction." ++ (and (match_code "const_double") ++ (match_test "TARGET_NEON && op == CONST0_RTX (mode)"))) ++ + (define_constraint "Da" + "@internal + In ARM/Thumb-2 state a const_int, const_double or const_vector that can + +=== modified file 'gcc/config/arm/vfp.md' +--- old/gcc/config/arm/vfp.md 2010-08-12 11:29:02 +0000 ++++ new/gcc/config/arm/vfp.md 2010-08-13 10:59:06 +0000 +@@ -402,8 +402,8 @@ + ;; DFmode moves + + (define_insn "*movdf_vfp" +- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r") +- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))] ++ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w, r, m,w ,Uv,w,r") ++ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,D0,mF,r,UvF,w, w,r"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP + && ( register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" +@@ -418,16 +418,18 @@ + case 2: + gcc_assert (TARGET_VFP_DOUBLE); + return \"fconstd%?\\t%P0, #%G1\"; +- case 3: case 4: ++ case 3: ++ return \"vmov.i32\\t%P0, #0\"; ++ case 4: case 5: + return output_move_double (operands); +- case 5: case 6: ++ case 6: case 7: + return output_move_vfp (operands); +- case 7: ++ case 8: + if (TARGET_VFP_SINGLE) + return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\"; + else + return \"fcpyd%?\\t%P0, %P1\"; +- case 8: ++ case 9: + return \"#\"; + default: + gcc_unreachable (); +@@ -435,10 +437,10 @@ + } + " + [(set_attr "type" +- "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") +- (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") +- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) +- (eq_attr "alternative" "7") ++ "r_2_f,f_2_r,fconstd,*,f_loadd,f_stored,load2,store2,ffarithd,*") ++ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,neon_vmov,*,*,*,*,neon_vmov,*") ++ (set (attr "length") (cond [(eq_attr "alternative" "4,5,9") (const_int 8) ++ (eq_attr "alternative" "8") + (if_then_else + (eq (symbol_ref "TARGET_VFP_SINGLE") + (const_int 1)) +@@ -446,14 +448,16 @@ + (const_int 4))] + (const_int 4))) + (set_attr "predicable" "yes") +- (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*") +- (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")] ++ (set_attr "pool_range" "*,*,*,*,1020,*,1020,*,*,*") ++ (set_attr "neg_pool_range" "*,*,*,*,1008,*,1008,*,*,*")] + ) + + (define_insn "*thumb2_movdf_vfp" +- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r") +- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))] +- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" ++ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,r, m,w ,Uv,w,r") ++ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,D0,mF,r,UvF,w, w,r"))] ++ "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP ++ && ( register_operand (operands[0], DFmode) ++ || register_operand (operands[1], DFmode))" + "* + { + switch (which_alternative) +@@ -465,11 +469,13 @@ + case 2: + gcc_assert (TARGET_VFP_DOUBLE); + return \"fconstd%?\\t%P0, #%G1\"; +- case 3: case 4: case 8: ++ case 3: ++ return \"vmov.i32\\t%P0, #0\"; ++ case 4: case 5: case 9: + return output_move_double (operands); +- case 5: case 6: ++ case 6: case 7: + return output_move_vfp (operands); +- case 7: ++ case 8: + if (TARGET_VFP_SINGLE) + return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\"; + else +@@ -480,18 +486,18 @@ + } + " + [(set_attr "type" +- "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*") +- (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") +- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) +- (eq_attr "alternative" "7") ++ "r_2_f,f_2_r,fconstd,*,load2,store2,f_load,f_store,ffarithd,*") ++ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,neon_vmov,*,*,*,*,neon_vmov,*") ++ (set (attr "length") (cond [(eq_attr "alternative" "4,5,9") (const_int 8) ++ (eq_attr "alternative" "8") + (if_then_else + (eq (symbol_ref "TARGET_VFP_SINGLE") + (const_int 1)) + (const_int 8) + (const_int 4))] + (const_int 4))) +- (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*") +- (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")] ++ (set_attr "pool_range" "*,*,*,*,4096,*,1020,*,*,*") ++ (set_attr "neg_pool_range" "*,*,*,*,0,*,1008,*,*,*")] + ) + + + +=== added file 'gcc/testsuite/gcc.target/arm/neon-load-df0.c' +--- old/gcc/testsuite/gcc.target/arm/neon-load-df0.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-load-df0.c 2010-08-13 10:59:06 +0000 +@@ -0,0 +1,14 @@ ++/* Test the optimization of loading 0.0 for ARM Neon. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++double x; ++void bar () ++{ ++ x = 0.0; ++} ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[dD\]\[0-9\]+, #0\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch new file mode 100644 index 0000000000..a1a2c2ad81 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch @@ -0,0 +1,552 @@ + * config/arm/arm.c (arm_rtx_costs_1): Adjust cost for + CONST_VECTOR. + (arm_size_rtx_costs): Likewise. + (thumb2_size_rtx_costs): Likewise. + (neon_valid_immediate): Add a case for double 0.0. + + gcc/testsuite/ + * gcc.target/arm/neon-vdup-1.c: New test case. + * gcc.target/arm/neon-vdup-2.c: New test case. + * gcc.target/arm/neon-vdup-3.c: New test case. + * gcc.target/arm/neon-vdup-4.c: New test case. + * gcc.target/arm/neon-vdup-5.c: New test case. + * gcc.target/arm/neon-vdup-6.c: New test case. + * gcc.target/arm/neon-vdup-7.c: New test case. + * gcc.target/arm/neon-vdup-8.c: New test case. + * gcc.target/arm/neon-vdup-9.c: New test case. + * gcc.target/arm/neon-vdup-10.c: New test case. + * gcc.target/arm/neon-vdup-11.c: New test case. + * gcc.target/arm/neon-vdup-12.c: New test case. + * gcc.target/arm/neon-vdup-13.c: New test case. + * gcc.target/arm/neon-vdup-14.c: New test case. + * gcc.target/arm/neon-vdup-15.c: New test case. + * gcc.target/arm/neon-vdup-16.c: New test case. + * gcc.target/arm/neon-vdup-17.c: New test case. + * gcc.target/arm/neon-vdup-18.c: New test case. + * gcc.target/arm/neon-vdup-19.c: New test case. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + Jie Zhang + + Issue #7122 + + gcc/ + * config/arm/vfp.md (movdf_vfp): Add load double 0.0 case. + (thumb2_movdf_vfp): Likewise. Require that one of the operands be a + register. + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-13 10:55:28 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-13 11:02:47 +0000 +@@ -7061,6 +7061,17 @@ + *total = COSTS_N_INSNS (4); + return true; + ++ case CONST_VECTOR: ++ if (TARGET_NEON ++ && TARGET_HARD_FLOAT ++ && outer == SET ++ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) ++ && neon_immediate_valid_for_move (x, mode, NULL, NULL)) ++ *total = COSTS_N_INSNS (1); ++ else ++ *total = COSTS_N_INSNS (4); ++ return true; ++ + default: + *total = COSTS_N_INSNS (4); + return false; +@@ -7301,6 +7312,17 @@ + *total = COSTS_N_INSNS (4); + return true; + ++ case CONST_VECTOR: ++ if (TARGET_NEON ++ && TARGET_HARD_FLOAT ++ && outer_code == SET ++ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) ++ && neon_immediate_valid_for_move (x, mode, NULL, NULL)) ++ *total = COSTS_N_INSNS (1); ++ else ++ *total = COSTS_N_INSNS (4); ++ return true; ++ + case HIGH: + case LO_SUM: + /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the +@@ -7647,6 +7669,17 @@ + *total = COSTS_WIDE_INSNS (4); + return true; + ++ case CONST_VECTOR: ++ if (TARGET_NEON ++ && TARGET_HARD_FLOAT ++ && outer_code == SET ++ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) ++ && neon_immediate_valid_for_move (x, mode, NULL, NULL)) ++ *total = COSTS_WIDE_INSNS (1); ++ else ++ *total = COSTS_WIDE_INSNS (4); ++ return true; ++ + case HIGH: + case LO_SUM: + /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the +@@ -8315,11 +8348,14 @@ + vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd + eeeeeeee ffffffff gggggggg hhhhhhhh + vmov f32 18 aBbbbbbc defgh000 00000000 00000000 ++ vmov f32 19 00000000 00000000 00000000 00000000 + + For case 18, B = !b. Representable values are exactly those accepted by + vfp3_const_double_index, but are output as floating-point numbers rather + than indices. + ++ For case 19, we will change it to vmov.i32 when assembling. ++ + Variants 0-5 (inclusive) may also be used as immediates for the second + operand of VORR/VBIC instructions. + +@@ -8362,7 +8398,7 @@ + rtx el0 = CONST_VECTOR_ELT (op, 0); + REAL_VALUE_TYPE r0; + +- if (!vfp3_const_double_rtx (el0)) ++ if (!vfp3_const_double_rtx (el0) && el0 != CONST0_RTX (GET_MODE (el0))) + return -1; + + REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); +@@ -8384,7 +8420,10 @@ + if (elementwidth) + *elementwidth = 0; + +- return 18; ++ if (el0 == CONST0_RTX (GET_MODE (el0))) ++ return 19; ++ else ++ return 18; + } + + /* Splat vector constant out into a byte vector. */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-1.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-1.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++float32x4_t out_float32x4_t; ++void test_vdupq_nf32 (void) ++{ ++ out_float32x4_t = vdupq_n_f32 (0.0); ++} ++ ++/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #0\.0\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-10.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-10.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-10.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x12000000); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #3992977407\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-11.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-11.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-11.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint16x8_t out_uint16x8_t; ++void test_vdupq_nu16 (void) ++{ ++ out_uint16x8_t = vdupq_n_u16 (0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-12.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-12.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-12.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint16x8_t out_uint16x8_t; ++void test_vdupq_nu16 (void) ++{ ++ out_uint16x8_t = vdupq_n_u16 (0x1200); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-13.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-13.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-13.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint16x8_t out_uint16x8_t; ++void test_vdupq_nu16 (void) ++{ ++ out_uint16x8_t = vdupq_n_u16 (~0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #65517\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-14.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-14.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-14.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint16x8_t out_uint16x8_t; ++void test_vdupq_nu16 (void) ++{ ++ out_uint16x8_t = vdupq_n_u16 (~0x1200); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #60927\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-15.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-15.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-15.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u8' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint8x16_t out_uint8x16_t; ++void test_vdupq_nu8 (void) ++{ ++ out_uint8x16_t = vdupq_n_u8 (0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i8\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-16.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-16.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-16.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x12ff); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4863\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-17.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-17.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-17.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x12ffff); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1245183\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-18.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-18.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-18.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x12ff); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962432\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-19.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-19.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-19.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x12ffff); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293722112\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-2.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-2.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++float32x4_t out_float32x4_t; ++void test_vdupq_nf32 (void) ++{ ++ out_float32x4_t = vdupq_n_f32 (0.125); ++} ++ ++/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #1\.25e-1\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-3.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-3.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-3.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-4.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-4.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-4.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x1200); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-5.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-5.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-5.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x120000); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1179648\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-6.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-6.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-6.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x12000000); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #301989888\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-7.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-7.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-7.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294967277\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-8.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-8.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-8.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x1200); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962687\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-9.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vdup-9.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-9.c 2010-08-13 11:02:47 +0000 +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x120000); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293787647\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch new file mode 100644 index 0000000000..675c2f3ceb --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch @@ -0,0 +1,121 @@ + 2010-04-07 Thomas Schwinge + Daniel Jacobowitz + + Issue #6715 + + PR debug/40521 + + gcc/ + * dwarf2out.c (NEED_UNWIND_TABLES): Define. + (dwarf2out_do_frame, dwarf2out_do_cfi_asm, dwarf2out_begin_prologue) + (dwarf2out_frame_finish, dwarf2out_assembly_start): Use it. + (dwarf2out_assembly_start): Correct logic for TARGET_UNWIND_INFO. + * config/arm/arm.h (DWARF2_UNWIND_INFO): Remove definition. + * config/arm/bpabi.h (DWARF2_UNWIND_INFO): Define to zero. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + Jie Zhang + + Issue #7122 + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-13 10:30:35 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-13 11:11:15 +0000 +@@ -932,9 +932,6 @@ + #define MUST_USE_SJLJ_EXCEPTIONS 1 + #endif + +-/* We can generate DWARF2 Unwind info, even though we don't use it. */ +-#define DWARF2_UNWIND_INFO 1 +- + /* Use r0 and r1 to pass exception handling information. */ + #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) + + +=== modified file 'gcc/config/arm/bpabi.h' +--- old/gcc/config/arm/bpabi.h 2009-11-20 17:37:30 +0000 ++++ new/gcc/config/arm/bpabi.h 2010-08-13 11:11:15 +0000 +@@ -26,6 +26,7 @@ + #define TARGET_BPABI (TARGET_AAPCS_BASED) + + /* BPABI targets use EABI frame unwinding tables. */ ++#define DWARF2_UNWIND_INFO 0 + #define TARGET_UNWIND_INFO 1 + + /* Section 4.1 of the AAPCS requires the use of VFP format. */ + +=== modified file 'gcc/dwarf2out.c' +--- old/gcc/dwarf2out.c 2010-07-01 11:31:19 +0000 ++++ new/gcc/dwarf2out.c 2010-08-13 11:11:15 +0000 +@@ -124,6 +124,9 @@ + # endif + #endif + ++#define NEED_UNWIND_TABLES \ ++ (flag_unwind_tables || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS)) ++ + /* Map register numbers held in the call frame info that gcc has + collected using DWARF_FRAME_REGNUM to those that should be output in + .debug_frame and .eh_frame. */ +@@ -147,9 +150,7 @@ + || write_symbols == VMS_AND_DWARF2_DEBUG + || DWARF2_FRAME_INFO || saved_do_cfi_asm + #ifdef DWARF2_UNWIND_INFO +- || (DWARF2_UNWIND_INFO +- && (flag_unwind_tables +- || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS))) ++ || (DWARF2_UNWIND_INFO && NEED_UNWIND_TABLES) + #endif + ); + } +@@ -185,7 +186,7 @@ + #ifdef TARGET_UNWIND_INFO + return false; + #else +- if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions)) ++ if (!NEED_UNWIND_TABLES) + return false; + #endif + } +@@ -3906,8 +3907,7 @@ + /* ??? current_function_func_begin_label is also used by except.c + for call-site information. We must emit this label if it might + be used. */ +- if ((! flag_exceptions || USING_SJLJ_EXCEPTIONS) +- && ! dwarf2out_do_frame ()) ++ if (! NEED_UNWIND_TABLES && ! dwarf2out_do_frame ()) + return; + #else + if (! dwarf2out_do_frame ()) +@@ -4067,7 +4067,7 @@ + + #ifndef TARGET_UNWIND_INFO + /* Output another copy for the unwinder. */ +- if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions)) ++ if (NEED_UNWIND_TABLES) + output_call_frame_info (1); + #endif + } +@@ -20732,10 +20732,15 @@ + { + if (HAVE_GAS_CFI_SECTIONS_DIRECTIVE && dwarf2out_do_cfi_asm ()) + { +-#ifndef TARGET_UNWIND_INFO +- if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions)) +-#endif ++#ifdef TARGET_UNWIND_INFO ++ /* We're only ever interested in .debug_frame. */ ++ fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n"); ++#else ++ /* GAS defaults to emitting .eh_frame only, and .debug_frame is not ++ wanted in case that the former one is present. */ ++ if (! NEED_UNWIND_TABLES) + fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n"); ++#endif + } + } + + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch new file mode 100644 index 0000000000..239251d2b5 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch @@ -0,0 +1,298 @@ + 2010-04-08 Bernd Schmidt + + Issue #6952 + + gcc/ + * ira-costs.c (record_reg_classes): Ignore alternatives that are + not enabled. + * config/arm/vfp.md (arm_movdi_vfp): Enable only when not tuning + for Cortex-A8. + (arm_movdi_vfp_cortexa8): New pattern. + * config/arm/neon.md (adddi3_neon, subdi3_neon, anddi3_neon, + iordi3_neon, xordi3_neon): Add alternatives to discourage Neon + instructions when tuning for Cortex-A8. Set attribute "alt_tune". + * config/arm/arm.md (define_attr "alt_tune", define_attr "enabled"): + New. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-04-07 Thomas Schwinge + Daniel Jacobowitz + + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-13 10:30:35 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-13 11:40:17 +0000 +@@ -432,6 +432,20 @@ + (const_string "yes") + (const_string "no")))) + ++; Specifies which machine an alternative is tuned for. Used to compute ++; attribute ENABLED. ++(define_attr "alt_tune" "all,onlya8,nota8" (const_string "all")) ++ ++(define_attr "enabled" "" ++ (cond [(and (eq_attr "alt_tune" "onlya8") ++ (not (eq_attr "tune" "cortexa8"))) ++ (const_int 0) ++ ++ (and (eq_attr "alt_tune" "nota8") ++ (eq_attr "tune" "cortexa8")) ++ (const_int 0)] ++ (const_int 1))) ++ + (include "arm-generic.md") + (include "arm926ejs.md") + (include "arm1020e.md") + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2010-08-10 13:31:21 +0000 ++++ new/gcc/config/arm/neon.md 2010-08-13 11:40:17 +0000 +@@ -827,23 +827,25 @@ + ) + + (define_insn "adddi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r") +- (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0") +- (match_operand:DI 2 "s_register_operand" "w,r,0"))) ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r") ++ (plus:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0") ++ (match_operand:DI 2 "s_register_operand" "w,w,r,0"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON" + { + switch (which_alternative) + { +- case 0: return "vadd.i64\t%P0, %P1, %P2"; +- case 1: return "#"; ++ case 0: /* fall through */ ++ case 1: return "vadd.i64\t%P0, %P1, %P2"; + case 2: return "#"; ++ case 3: return "#"; + default: gcc_unreachable (); + } + } +- [(set_attr "neon_type" "neon_int_1,*,*") +- (set_attr "conds" "*,clob,clob") +- (set_attr "length" "*,8,8")] ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") ++ (set_attr "conds" "*,*,clob,clob") ++ (set_attr "length" "*,*,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,*,*")] + ) + + (define_insn "*sub3_neon" +@@ -861,24 +863,26 @@ + ) + + (define_insn "subdi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r") +- (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0") +- (match_operand:DI 2 "s_register_operand" "w,r,0,0"))) ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r,?&r") ++ (minus:DI (match_operand:DI 1 "s_register_operand" "w,w,0,r,0") ++ (match_operand:DI 2 "s_register_operand" "w,w,r,0,0"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON" + { + switch (which_alternative) + { +- case 0: return "vsub.i64\t%P0, %P1, %P2"; +- case 1: /* fall through */ +- case 2: /* fall through */ +- case 3: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"; ++ case 0: /* fall through */ ++ case 1: return "vsub.i64\t%P0, %P1, %P2"; ++ case 2: /* fall through */ ++ case 3: /* fall through */ ++ case 4: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"; + default: gcc_unreachable (); + } + } +- [(set_attr "neon_type" "neon_int_2,*,*,*") +- (set_attr "conds" "*,clob,clob,clob") +- (set_attr "length" "*,8,8,8")] ++ [(set_attr "neon_type" "neon_int_2,neon_int_2,*,*,*") ++ (set_attr "conds" "*,*,clob,clob,clob") ++ (set_attr "length" "*,*,8,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,*,*,*")] + ) + + (define_insn "*mul3_neon" +@@ -964,23 +968,26 @@ + ) + + (define_insn "iordi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r") +- (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r") +- (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r")))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r") ++ (ior:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r") ++ (match_operand:DI 2 "neon_logic_op2" "w,w,Dl,Dl,r,r")))] + "TARGET_NEON" + { + switch (which_alternative) + { +- case 0: return "vorr\t%P0, %P1, %P2"; +- case 1: return neon_output_logic_immediate ("vorr", &operands[2], ++ case 0: /* fall through */ ++ case 1: return "vorr\t%P0, %P1, %P2"; ++ case 2: /* fall through */ ++ case 3: return neon_output_logic_immediate ("vorr", &operands[2], + DImode, 0, VALID_NEON_QREG_MODE (DImode)); +- case 2: return "#"; +- case 3: return "#"; ++ case 4: return "#"; ++ case 5: return "#"; + default: gcc_unreachable (); + } + } +- [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") +- (set_attr "length" "*,*,8,8")] ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*") ++ (set_attr "length" "*,*,*,*,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")] + ) + + ;; The concrete forms of the Neon immediate-logic instructions are vbic and +@@ -1006,23 +1013,26 @@ + ) + + (define_insn "anddi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r") +- (and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r") +- (match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r")))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r") ++ (and:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r") ++ (match_operand:DI 2 "neon_inv_logic_op2" "w,w,DL,DL,r,r")))] + "TARGET_NEON" + { + switch (which_alternative) + { +- case 0: return "vand\t%P0, %P1, %P2"; +- case 1: return neon_output_logic_immediate ("vand", &operands[2], ++ case 0: /* fall through */ ++ case 1: return "vand\t%P0, %P1, %P2"; ++ case 2: /* fall through */ ++ case 3: return neon_output_logic_immediate ("vand", &operands[2], + DImode, 1, VALID_NEON_QREG_MODE (DImode)); +- case 2: return "#"; +- case 3: return "#"; ++ case 4: return "#"; ++ case 5: return "#"; + default: gcc_unreachable (); + } + } +- [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") +- (set_attr "length" "*,*,8,8")] ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*") ++ (set_attr "length" "*,*,*,*,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")] + ) + + (define_insn "orn3_neon" +@@ -1080,16 +1090,18 @@ + ) + + (define_insn "xordi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r") +- (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r") +- (match_operand:DI 2 "s_register_operand" "w,r,r")))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r") ++ (xor:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,r") ++ (match_operand:DI 2 "s_register_operand" "w,w,r,r")))] + "TARGET_NEON" + "@ + veor\t%P0, %P1, %P2 ++ veor\t%P0, %P1, %P2 + # + #" +- [(set_attr "neon_type" "neon_int_1,*,*") +- (set_attr "length" "*,8,8")] ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") ++ (set_attr "length" "*,*,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,*,*")] + ) + + (define_insn "one_cmpl2" + +=== modified file 'gcc/config/arm/vfp.md' +--- old/gcc/config/arm/vfp.md 2010-08-13 10:59:06 +0000 ++++ new/gcc/config/arm/vfp.md 2010-08-13 11:40:17 +0000 +@@ -133,9 +133,51 @@ + ;; DImode moves + + (define_insn "*arm_movdi_vfp" +- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv") +- (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP ++ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,w,r,w,w, Uv") ++ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 ++ && ( register_operand (operands[0], DImode) ++ || register_operand (operands[1], DImode))" ++ "* ++ switch (which_alternative) ++ { ++ case 0: ++ return \"#\"; ++ case 1: ++ case 2: ++ return output_move_double (operands); ++ case 3: ++ return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; ++ case 4: ++ return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; ++ case 5: ++ if (TARGET_VFP_SINGLE) ++ return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; ++ else ++ return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; ++ case 6: case 7: ++ return output_move_vfp (operands); ++ default: ++ gcc_unreachable (); ++ } ++ " ++ [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") ++ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") ++ (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) ++ (eq_attr "alternative" "5") ++ (if_then_else ++ (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1)) ++ (const_int 8) ++ (const_int 4))] ++ (const_int 4))) ++ (set_attr "pool_range" "*,1020,*,*,*,*,1020,*") ++ (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")] ++) ++ ++(define_insn "*arm_movdi_vfp_cortexa8" ++ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,!r,w,w, Uv") ++ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "* + +=== modified file 'gcc/ira-costs.c' +--- old/gcc/ira-costs.c 2009-11-25 10:55:54 +0000 ++++ new/gcc/ira-costs.c 2010-08-13 11:40:17 +0000 +@@ -224,6 +224,14 @@ + int alt_fail = 0; + int alt_cost = 0, op_cost_add; + ++ if (!recog_data.alternative_enabled_p[alt]) ++ { ++ for (i = 0; i < recog_data.n_operands; i++) ++ constraints[i] = skip_alternative (constraints[i]); ++ ++ continue; ++ } ++ + for (i = 0; i < n_ops; i++) + { + unsigned char c; + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch new file mode 100644 index 0000000000..743e2751c7 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch @@ -0,0 +1,384 @@ + Richard Earnshaw + + gcc/ + * doc/tm.texi (OVERLAPPING_REGISTER_NAMES): Document new macro. + * output.h (decode_reg_name_and_count): Declare. + * varasm.c (decode_reg_name_and_count): New function. + (decode_reg_name): Reimplement using decode_reg_name_and_count. + * reginfo.c (fix_register): Use decode_reg_name_and_count and + iterate over all regs used. + * stmt.c (expand_asm_operands): Likewise. + * config/arm/aout.h (OVERLAPPING_REGISTER_NAMES): Define. + (ADDITIONAL_REGISTER_NAMES): Remove aliases that overlap + multiple machine registers. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-04-08 Bernd Schmidt + + Issue #6952 + +=== modified file 'gcc/config/arm/aout.h' +--- old/gcc/config/arm/aout.h 2009-06-21 19:48:15 +0000 ++++ new/gcc/config/arm/aout.h 2010-08-13 11:53:46 +0000 +@@ -163,31 +163,45 @@ + {"mvdx12", 39}, \ + {"mvdx13", 40}, \ + {"mvdx14", 41}, \ +- {"mvdx15", 42}, \ +- {"d0", 63}, {"q0", 63}, \ +- {"d1", 65}, \ +- {"d2", 67}, {"q1", 67}, \ +- {"d3", 69}, \ +- {"d4", 71}, {"q2", 71}, \ +- {"d5", 73}, \ +- {"d6", 75}, {"q3", 75}, \ +- {"d7", 77}, \ +- {"d8", 79}, {"q4", 79}, \ +- {"d9", 81}, \ +- {"d10", 83}, {"q5", 83}, \ +- {"d11", 85}, \ +- {"d12", 87}, {"q6", 87}, \ +- {"d13", 89}, \ +- {"d14", 91}, {"q7", 91}, \ +- {"d15", 93}, \ +- {"q8", 95}, \ +- {"q9", 99}, \ +- {"q10", 103}, \ +- {"q11", 107}, \ +- {"q12", 111}, \ +- {"q13", 115}, \ +- {"q14", 119}, \ +- {"q15", 123} \ ++ {"mvdx15", 42} \ ++} ++#endif ++ ++#ifndef OVERLAPPING_REGISTER_NAMES ++#define OVERLAPPING_REGISTER_NAMES \ ++{ \ ++ {"d0", 63, 2}, \ ++ {"d1", 65, 2}, \ ++ {"d2", 67, 2}, \ ++ {"d3", 69, 2}, \ ++ {"d4", 71, 2}, \ ++ {"d5", 73, 2}, \ ++ {"d6", 75, 2}, \ ++ {"d7", 77, 2}, \ ++ {"d8", 79, 2}, \ ++ {"d9", 81, 2}, \ ++ {"d10", 83, 2}, \ ++ {"d11", 85, 2}, \ ++ {"d12", 87, 2}, \ ++ {"d13", 89, 2}, \ ++ {"d14", 91, 2}, \ ++ {"d15", 93, 2}, \ ++ {"q0", 63, 4}, \ ++ {"q1", 67, 4}, \ ++ {"q2", 71, 4}, \ ++ {"q3", 75, 4}, \ ++ {"q4", 79, 4}, \ ++ {"q5", 83, 4}, \ ++ {"q6", 87, 4}, \ ++ {"q7", 91, 4}, \ ++ {"q8", 95, 4}, \ ++ {"q9", 99, 4}, \ ++ {"q10", 103, 4}, \ ++ {"q11", 107, 4}, \ ++ {"q12", 111, 4}, \ ++ {"q13", 115, 4}, \ ++ {"q14", 119, 4}, \ ++ {"q15", 123, 4} \ + } + #endif + + +=== modified file 'gcc/doc/tm.texi' +--- old/gcc/doc/tm.texi 2010-06-24 20:06:37 +0000 ++++ new/gcc/doc/tm.texi 2010-08-13 11:53:46 +0000 +@@ -8339,6 +8339,22 @@ + to registers using alternate names. + @end defmac + ++@defmac OVERLAPPING_REGISTER_NAMES ++If defined, a C initializer for an array of structures containing a ++name, a register number and a count of the number of consecutive ++machine registers the name overlaps. This macro defines additional ++names for hard registers, thus allowing the @code{asm} option in ++declarations to refer to registers using alternate names. Unlike ++@code{ADDITIONAL_REGISTER_NAMES}, this macro should be used when the ++register name implies multiple underlying registers. ++ ++This macro should be used when it is important that a clobber in an ++@code{asm} statement clobbers all the underlying values implied by the ++register name. For example, on ARM, clobbering the double-precision ++VFP register ``d0'' implies clobbering both single-precision registers ++``s0'' and ``s1''. ++@end defmac ++ + @defmac ASM_OUTPUT_OPCODE (@var{stream}, @var{ptr}) + Define this macro if you are using an unusual assembler that + requires different names for the machine instructions. + +=== modified file 'gcc/output.h' +--- old/gcc/output.h 2009-10-26 21:57:10 +0000 ++++ new/gcc/output.h 2010-08-13 11:53:46 +0000 +@@ -173,6 +173,11 @@ + Prefixes such as % are optional. */ + extern int decode_reg_name (const char *); + ++/* Similar to decode_reg_name, but takes an extra parameter that is a ++ pointer to the number of (internal) registers described by the ++ external name. */ ++extern int decode_reg_name_and_count (const char *, int *); ++ + extern void assemble_alias (tree, tree); + + extern void default_assemble_visibility (tree, int); + +=== modified file 'gcc/reginfo.c' +--- old/gcc/reginfo.c 2010-04-19 09:04:43 +0000 ++++ new/gcc/reginfo.c 2010-08-13 11:53:46 +0000 +@@ -799,36 +799,41 @@ + fix_register (const char *name, int fixed, int call_used) + { + int i; ++ int reg, nregs; + + /* Decode the name and update the primary form of + the register info. */ + +- if ((i = decode_reg_name (name)) >= 0) ++ if ((reg = decode_reg_name_and_count (name, &nregs)) >= 0) + { +- if ((i == STACK_POINTER_REGNUM ++ gcc_assert (nregs >= 1); ++ for (i = reg; i < reg + nregs; i++) ++ { ++ if ((i == STACK_POINTER_REGNUM + #ifdef HARD_FRAME_POINTER_REGNUM +- || i == HARD_FRAME_POINTER_REGNUM ++ || i == HARD_FRAME_POINTER_REGNUM + #else +- || i == FRAME_POINTER_REGNUM ++ || i == FRAME_POINTER_REGNUM + #endif +- ) +- && (fixed == 0 || call_used == 0)) +- { +- static const char * const what_option[2][2] = { +- { "call-saved", "call-used" }, +- { "no-such-option", "fixed" }}; ++ ) ++ && (fixed == 0 || call_used == 0)) ++ { ++ static const char * const what_option[2][2] = { ++ { "call-saved", "call-used" }, ++ { "no-such-option", "fixed" }}; + +- error ("can't use '%s' as a %s register", name, +- what_option[fixed][call_used]); +- } +- else +- { +- fixed_regs[i] = fixed; +- call_used_regs[i] = call_used; ++ error ("can't use '%s' as a %s register", name, ++ what_option[fixed][call_used]); ++ } ++ else ++ { ++ fixed_regs[i] = fixed; ++ call_used_regs[i] = call_used; + #ifdef CALL_REALLY_USED_REGISTERS +- if (fixed == 0) +- call_really_used_regs[i] = call_used; ++ if (fixed == 0) ++ call_really_used_regs[i] = call_used; + #endif ++ } + } + } + else + +=== modified file 'gcc/stmt.c' +--- old/gcc/stmt.c 2010-02-19 09:53:51 +0000 ++++ new/gcc/stmt.c 2010-08-13 11:53:46 +0000 +@@ -684,13 +684,14 @@ + for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) + { + const char *regname; ++ int nregs; + + if (TREE_VALUE (tail) == error_mark_node) + return; + regname = TREE_STRING_POINTER (TREE_VALUE (tail)); + +- i = decode_reg_name (regname); +- if (i >= 0 || i == -4) ++ i = decode_reg_name_and_count (regname, &nregs); ++ if (i == -4) + ++nclobbers; + else if (i == -2) + error ("unknown register name %qs in %", regname); +@@ -698,14 +699,21 @@ + /* Mark clobbered registers. */ + if (i >= 0) + { +- /* Clobbering the PIC register is an error. */ +- if (i == (int) PIC_OFFSET_TABLE_REGNUM) ++ int reg; ++ ++ for (reg = i; reg < i + nregs; reg++) + { +- error ("PIC register %qs clobbered in %", regname); +- return; ++ ++nclobbers; ++ ++ /* Clobbering the PIC register is an error. */ ++ if (reg == (int) PIC_OFFSET_TABLE_REGNUM) ++ { ++ error ("PIC register clobbered by %qs in %", regname); ++ return; ++ } ++ ++ SET_HARD_REG_BIT (clobbered_regs, reg); + } +- +- SET_HARD_REG_BIT (clobbered_regs, i); + } + } + +@@ -1026,7 +1034,8 @@ + for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) + { + const char *regname = TREE_STRING_POINTER (TREE_VALUE (tail)); +- int j = decode_reg_name (regname); ++ int reg, nregs; ++ int j = decode_reg_name_and_count (regname, &nregs); + rtx clobbered_reg; + + if (j < 0) +@@ -1048,30 +1057,39 @@ + continue; + } + +- /* Use QImode since that's guaranteed to clobber just one reg. */ +- clobbered_reg = gen_rtx_REG (QImode, j); +- +- /* Do sanity check for overlap between clobbers and respectively +- input and outputs that hasn't been handled. Such overlap +- should have been detected and reported above. */ +- if (!clobber_conflict_found) ++ for (reg = j; reg < j + nregs; reg++) + { +- int opno; +- +- /* We test the old body (obody) contents to avoid tripping +- over the under-construction body. */ +- for (opno = 0; opno < noutputs; opno++) +- if (reg_overlap_mentioned_p (clobbered_reg, output_rtx[opno])) +- internal_error ("asm clobber conflict with output operand"); +- +- for (opno = 0; opno < ninputs - ninout; opno++) +- if (reg_overlap_mentioned_p (clobbered_reg, +- ASM_OPERANDS_INPUT (obody, opno))) +- internal_error ("asm clobber conflict with input operand"); ++ /* Use QImode since that's guaranteed to clobber just ++ * one reg. */ ++ clobbered_reg = gen_rtx_REG (QImode, reg); ++ ++ /* Do sanity check for overlap between clobbers and ++ respectively input and outputs that hasn't been ++ handled. Such overlap should have been detected and ++ reported above. */ ++ if (!clobber_conflict_found) ++ { ++ int opno; ++ ++ /* We test the old body (obody) contents to avoid ++ tripping over the under-construction body. */ ++ for (opno = 0; opno < noutputs; opno++) ++ if (reg_overlap_mentioned_p (clobbered_reg, ++ output_rtx[opno])) ++ internal_error ++ ("asm clobber conflict with output operand"); ++ ++ for (opno = 0; opno < ninputs - ninout; opno++) ++ if (reg_overlap_mentioned_p (clobbered_reg, ++ ASM_OPERANDS_INPUT (obody, ++ opno))) ++ internal_error ++ ("asm clobber conflict with input operand"); ++ } ++ ++ XVECEXP (body, 0, i++) ++ = gen_rtx_CLOBBER (VOIDmode, clobbered_reg); + } +- +- XVECEXP (body, 0, i++) +- = gen_rtx_CLOBBER (VOIDmode, clobbered_reg); + } + + if (nlabels > 0) + +=== modified file 'gcc/varasm.c' +--- old/gcc/varasm.c 2010-03-27 11:56:30 +0000 ++++ new/gcc/varasm.c 2010-08-13 11:53:46 +0000 +@@ -1043,8 +1043,11 @@ + Prefixes such as % are optional. */ + + int +-decode_reg_name (const char *asmspec) ++decode_reg_name_and_count (const char *asmspec, int *pnregs) + { ++ /* Presume just one register is clobbered. */ ++ *pnregs = 1; ++ + if (asmspec != 0) + { + int i; +@@ -1070,6 +1073,25 @@ + && ! strcmp (asmspec, strip_reg_name (reg_names[i]))) + return i; + ++#ifdef OVERLAPPING_REGISTER_NAMES ++ { ++ static const struct ++ { ++ const char *const name; ++ const int number; ++ const int nregs; ++ } table[] = OVERLAPPING_REGISTER_NAMES; ++ ++ for (i = 0; i < (int) ARRAY_SIZE (table); i++) ++ if (table[i].name[0] ++ && ! strcmp (asmspec, table[i].name)) ++ { ++ *pnregs = table[i].nregs; ++ return table[i].number; ++ } ++ } ++#endif /* OVERLAPPING_REGISTER_NAMES */ ++ + #ifdef ADDITIONAL_REGISTER_NAMES + { + static const struct { const char *const name; const int number; } table[] +@@ -1093,6 +1115,14 @@ + + return -1; + } ++ ++int ++decode_reg_name (const char *name) ++{ ++ int count; ++ return decode_reg_name_and_count (name, &count); ++} ++ + + /* Return true if DECL's initializer is suitable for a BSS section. */ + + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch new file mode 100644 index 0000000000..b47c2ceb4c --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch @@ -0,0 +1,181 @@ + 2010-04-12 Andrew Stubbs + + Issue #7178 + + gcc/ + * config/arm/arm.c (arm_init_libfuncs): Change __gnu_f2h_ieee to + __aeabi_f2h, __gnu_f2h_alternative to __aeabi_f2h_alt, __gnu_h2f_ieee + to __aeabi_h2f, and __gnu_h2f_alternative to __aeabi_h2f_alt. + * config/arm/fp16.c (__gnu_f2h_internal): Change return type to + unsigned int. Change 'sign' variable likewise. + (__gnu_h2f_internal): Set to static inline. + Change return type to unsigned int. Change 'sign' variable likewise. + (ALIAS): New define. + (__gnu_f2h_ieee): Change unsigned short to unsigned int. + (__gnu_h2f_ieee): Likewise. + (__gnu_f2h_alternative): Likewise. + (__gnu_h2f_alternative): Likewise. + (__aeabi_f2h, __aeabi_h2f): New aliases. + (__aeabi_f2h_alt, __aeabi_h2f_alt): Likewise. + * config/arm/sfp-machine.h (__extendhfsf2): Set to __aeabi_h2f. + (__truncsfhf2): Set to __aeabi_f2h. + + gcc/testsuite/ + * g++.dg/ext/arm-fp16/arm-fp16-ops-5.C: Check for __aeabi_h2f + and __aeabi_f2h. + * g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Likewise. + * gcc.dg/torture/arm-fp16-ops-5.c: Likewise. + * gcc.dg/torture/arm-fp16-ops-6.c: Likewise. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + Richard Earnshaw + + gcc/ + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-13 11:02:47 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-13 14:08:20 +0000 +@@ -1054,12 +1054,12 @@ + /* Conversions. */ + set_conv_libfunc (trunc_optab, HFmode, SFmode, + (arm_fp16_format == ARM_FP16_FORMAT_IEEE +- ? "__gnu_f2h_ieee" +- : "__gnu_f2h_alternative")); ++ ? "__aeabi_f2h" ++ : "__aeabi_f2h_alt")); + set_conv_libfunc (sext_optab, SFmode, HFmode, + (arm_fp16_format == ARM_FP16_FORMAT_IEEE +- ? "__gnu_h2f_ieee" +- : "__gnu_h2f_alternative")); ++ ? "__aeabi_h2f" ++ : "__aeabi_h2f_alt")); + + /* Arithmetic. */ + set_optab_libfunc (add_optab, HFmode, NULL); + +=== modified file 'gcc/config/arm/fp16.c' +--- old/gcc/config/arm/fp16.c 2009-06-18 11:26:37 +0000 ++++ new/gcc/config/arm/fp16.c 2010-08-13 14:08:20 +0000 +@@ -22,10 +22,10 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +-static inline unsigned short ++static inline unsigned int + __gnu_f2h_internal(unsigned int a, int ieee) + { +- unsigned short sign = (a >> 16) & 0x8000; ++ unsigned int sign = (a >> 16) & 0x8000; + int aexp = (a >> 23) & 0xff; + unsigned int mantissa = a & 0x007fffff; + unsigned int mask; +@@ -95,10 +95,10 @@ + return sign | (((aexp + 14) << 10) + (mantissa >> 13)); + } + +-unsigned int +-__gnu_h2f_internal(unsigned short a, int ieee) ++static inline unsigned int ++__gnu_h2f_internal(unsigned int a, int ieee) + { +- unsigned int sign = (unsigned int)(a & 0x8000) << 16; ++ unsigned int sign = (a & 0x00008000) << 16; + int aexp = (a >> 10) & 0x1f; + unsigned int mantissa = a & 0x3ff; + +@@ -120,26 +120,33 @@ + return sign | (((aexp + 0x70) << 23) + (mantissa << 13)); + } + +-unsigned short ++#define ALIAS(src, dst) \ ++ typeof (src) dst __attribute__ ((alias (#src))); ++ ++unsigned int + __gnu_f2h_ieee(unsigned int a) + { + return __gnu_f2h_internal(a, 1); + } ++ALIAS (__gnu_f2h_ieee, __aeabi_f2h) + + unsigned int +-__gnu_h2f_ieee(unsigned short a) ++__gnu_h2f_ieee(unsigned int a) + { + return __gnu_h2f_internal(a, 1); + } ++ALIAS (__gnu_h2f_ieee, __aeabi_h2f) + +-unsigned short ++unsigned int + __gnu_f2h_alternative(unsigned int x) + { + return __gnu_f2h_internal(x, 0); + } ++ALIAS (__gnu_f2h_alternative, __aeabi_f2h_alt) + + unsigned int +-__gnu_h2f_alternative(unsigned short a) ++__gnu_h2f_alternative(unsigned int a) + { + return __gnu_h2f_internal(a, 0); + } ++ALIAS (__gnu_h2f_alternative, __aeabi_h2f_alt) + +=== modified file 'gcc/config/arm/sfp-machine.h' +--- old/gcc/config/arm/sfp-machine.h 2009-06-18 11:26:37 +0000 ++++ new/gcc/config/arm/sfp-machine.h 2010-08-13 14:08:20 +0000 +@@ -99,7 +99,7 @@ + #define __fixdfdi __aeabi_d2lz + #define __fixunsdfdi __aeabi_d2ulz + #define __floatdidf __aeabi_l2d +-#define __extendhfsf2 __gnu_h2f_ieee +-#define __truncsfhf2 __gnu_f2h_ieee ++#define __extendhfsf2 __aeabi_h2f ++#define __truncsfhf2 __aeabi_f2h + + #endif /* __ARM_EABI__ */ + +=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C' +--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C 2010-08-13 14:08:20 +0000 +@@ -13,3 +13,5 @@ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ + +=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C' +--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C 2010-08-13 14:08:20 +0000 +@@ -13,3 +13,5 @@ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c' +--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c 2010-08-13 14:08:20 +0000 +@@ -13,3 +13,5 @@ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c' +--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c 2010-08-13 14:08:20 +0000 +@@ -13,3 +13,5 @@ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch new file mode 100644 index 0000000000..64efbc759e --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch @@ -0,0 +1,376 @@ + + 2010-04-11 Julian Brown + + Issue #7326 + + gcc/ + * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. + * config/arm/arm.md (generic_sched): No for Cortex-A5. + (generic_vfp): Likewise. + (cortex-a5.md): Include. + * config/arm/cortex-a5.md: New. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-04-12 Andrew Stubbs + + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-13 14:08:20 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-13 15:15:12 +0000 +@@ -22262,6 +22262,7 @@ + { + case cortexr4: + case cortexr4f: ++ case cortexa5: + case cortexa8: + case cortexa9: + return 2; + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-13 11:40:17 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-13 15:15:12 +0000 +@@ -419,7 +419,7 @@ + + (define_attr "generic_sched" "yes,no" + (const (if_then_else +- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9") ++ (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9") + (eq_attr "tune_cortexr4" "yes")) + (const_string "no") + (const_string "yes")))) +@@ -427,7 +427,7 @@ + (define_attr "generic_vfp" "yes,no" + (const (if_then_else + (and (eq_attr "fpu" "vfp") +- (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9") ++ (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9") + (eq_attr "tune_cortexr4" "no")) + (const_string "yes") + (const_string "no")))) +@@ -451,6 +451,7 @@ + (include "arm1020e.md") + (include "arm1026ejs.md") + (include "arm1136jfs.md") ++(include "cortex-a5.md") + (include "cortex-a8.md") + (include "cortex-a9.md") + (include "cortex-r4.md") + +=== added file 'gcc/config/arm/cortex-a5.md' +--- old/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000 ++++ new/gcc/config/arm/cortex-a5.md 2010-08-13 15:15:12 +0000 +@@ -0,0 +1,310 @@ ++;; ARM Cortex-A5 pipeline description ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; Contributed by CodeSourcery. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "cortex_a5") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Functional units. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; The integer (ALU) pipeline. There are five DPU pipeline stages. However the ++;; decode/issue stages operate the same for all instructions, so do not model ++;; them. We only need to model the first execute stage because instructions ++;; always advance one stage per cycle in order. Only branch instructions may ++;; dual-issue, so a single unit covers all of the LS, ALU, MAC and FPU ++;; pipelines. ++ ++(define_cpu_unit "cortex_a5_ex1" "cortex_a5") ++ ++;; The branch pipeline. Branches can dual-issue with other instructions ++;; (except when those instructions take multiple cycles to issue). ++ ++(define_cpu_unit "cortex_a5_branch" "cortex_a5") ++ ++;; Pseudo-unit for blocking the multiply pipeline when a double-precision ++;; multiply is in progress. ++ ++(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5") ++ ++;; The floating-point add pipeline (ex1/f1 stage), used to model the usage ++;; of the add pipeline by fmac instructions, etc. ++ ++(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5") ++ ++;; Floating-point div/sqrt (long latency, out-of-order completion). ++ ++(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ALU instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_alu" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "alu")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_alu_shift" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "alu_shift,alu_shift_reg")) ++ "cortex_a5_ex1") ++ ++;; Forwarding path for unshifted operands. ++ ++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" ++ "cortex_a5_alu") ++ ++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" ++ "cortex_a5_alu_shift" ++ "arm_no_early_alu_shift_dep") ++ ++;; The multiplier pipeline can forward results from wr stage only (so I don't ++;; think there's any need to specify bypasses). ++ ++(define_insn_reservation "cortex_a5_mul" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "mult")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Load/store instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Address-generation happens in the issue stage, which is one stage behind ++;; the ex1 stage (the first stage we care about for scheduling purposes). The ++;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr. ++ ++;; FIXME: These might not be entirely accurate for load2, load3, load4. I think ++;; they make sense since there's a 32-bit interface between the DPU and the DCU, ++;; so we can't load more than that per cycle. The store2, store3, store4 ++;; reservations are similarly guessed. ++ ++(define_insn_reservation "cortex_a5_load1" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load_byte,load1")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store1" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store1")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load2" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load2")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store2" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store2")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load3" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store3" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load4" 5 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store4" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Branches. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Direct branches are the only instructions we can dual-issue (also IT and ++;; nop, but those aren't very interesting for scheduling). (The latency here ++;; is meant to represent when the branch actually takes place, but may not be ++;; entirely correct.) ++ ++(define_insn_reservation "cortex_a5_branch" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "branch,call")) ++ "cortex_a5_branch") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point arithmetic. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_fpalu" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ ++ fcmps, fcmpd")) ++ "cortex_a5_ex1+cortex_a5_fpadd_pipe") ++ ++;; For fconsts and fconstd, 8-bit immediate data is passed directly from ++;; f1 to f3 (which I think reduces the latency by one cycle). ++ ++(define_insn_reservation "cortex_a5_fconst" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fconsts,fconstd")) ++ "cortex_a5_ex1+cortex_a5_fpadd_pipe") ++ ++;; We should try not to attempt to issue a single-precision multiplication in ++;; the middle of a double-precision multiplication operation (the usage of ++;; cortex_a5_fpmul_pipe). ++ ++(define_insn_reservation "cortex_a5_fpmuls" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmuls")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe") ++ ++;; For single-precision multiply-accumulate, the add (accumulate) is issued ++;; whilst the multiply is in F4. The multiply result can then be forwarded ++;; from F5 to F1. The issue unit is only used once (when we first start ++;; processing the instruction), but the usage of the FP add pipeline could ++;; block other instructions attempting to use it simultaneously. We try to ++;; avoid that using cortex_a5_fpadd_pipe. ++ ++(define_insn_reservation "cortex_a5_fpmacs" 8 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmacs")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") ++ ++;; Non-multiply instructions can issue in the middle two instructions of a ++;; double-precision multiply. Note that it isn't entirely clear when a branch ++;; can dual-issue when a multi-cycle multiplication is in progress; we ignore ++;; that for now though. ++ ++(define_insn_reservation "cortex_a5_fpmuld" 7 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmuld")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ ++ cortex_a5_ex1+cortex_a5_fpmul_pipe") ++ ++(define_insn_reservation "cortex_a5_fpmacd" 11 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmacd")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ ++ cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point divide/square root instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; ??? Not sure if the 14 cycles taken for single-precision divide to complete ++;; includes the time taken for the special instruction used to collect the ++;; result to travel down the multiply pipeline, or not. Assuming so. (If ++;; that's wrong, the latency should be increased by a few cycles.) ++ ++;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the ++;; multiply pipeline to collect the divide/square-root result. ++ ++(define_insn_reservation "cortex_a5_fdivs" 14 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fdivs")) ++ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") ++ ++;; ??? Similarly for fdivd. ++ ++(define_insn_reservation "cortex_a5_fdivd" 29 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fdivd")) ++ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP to/from core transfers. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; FP loads take data from wr/rot/f3. Might need to define bypasses to model ++;; this? ++ ++;; Core-to-VFP transfers use the multiply pipeline. ++;; Not sure about this at all... I think we need some bypasses too. ++ ++(define_insn_reservation "cortex_a5_r2f" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "r_2_f")) ++ "cortex_a5_ex1") ++ ++;; Not sure about this either. 6.8.7 says "Additionally, the store pipe used ++;; for store and FP->core register transfers can forward into the F2 and F3 ++;; stages." ++;; This doesn't correspond to what we have though. ++ ++(define_insn_reservation "cortex_a5_f2r" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_2_r")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP flag transfer. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; ??? The flag forwarding described in section 6.8.11 of the Cortex-A5 DPU ++;; specification (from fmstat to the ex2 stage of the second instruction) is ++;; not modeled at present. ++ ++(define_insn_reservation "cortex_a5_f_flags" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_flag")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP load/store. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_f_loads" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_loads")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_loadd" 5 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_load,f_loadd")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_stores" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_stores")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_stored" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_store,f_stored")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++;; Load-to-use for floating-point values has a penalty of one cycle, i.e. a ++;; latency of two (6.8.3). ++ ++(define_bypass 2 "cortex_a5_f_loads" ++ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ ++ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ ++ cortex_a5_f2r") ++ ++(define_bypass 3 "cortex_a5_f_loadd" ++ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ ++ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ ++ cortex_a5_f2r") + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch new file mode 100644 index 0000000000..bbdd38b559 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch @@ -0,0 +1,27 @@ + 2010-06-12 Jie Zhang + + gcc/ + * config/arm/vfp.md (arm_movsi_vfp): Set neon_type correctly + for neon_ldr and neon_str instructions. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-04-11 Julian Brown + + Issue #7326 + +=== modified file 'gcc/config/arm/vfp.md' +--- old/gcc/config/arm/vfp.md 2010-08-13 11:40:17 +0000 ++++ new/gcc/config/arm/vfp.md 2010-08-13 15:28:31 +0000 +@@ -82,7 +82,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") +- (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") ++ (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,neon_ldr,neon_str") + (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] + ) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch new file mode 100644 index 0000000000..eedcf62d1e --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch @@ -0,0 +1,38 @@ + 2010-06-14 Paul Brook + + Issue #8879 + gcc/ + * config/arm/arm.c (use_vfp_abi): Add sorry() for Thumb-1 + hard-float ABI. + +2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-06-12 Jie Zhang + + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-13 15:15:12 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-13 15:37:39 +0000 +@@ -3969,7 +3969,18 @@ + use_vfp_abi (enum arm_pcs pcs_variant, bool is_double) + { + if (pcs_variant == ARM_PCS_AAPCS_VFP) +- return true; ++ { ++ static bool seen_thumb1_vfp = false; ++ ++ if (TARGET_THUMB1 && !seen_thumb1_vfp) ++ { ++ sorry ("Thumb-1 hard-float VFP ABI"); ++ /* sorry() is not immediately fatal, so only display this once. */ ++ seen_thumb1_vfp = true; ++ } ++ ++ return true; ++ } + + if (pcs_variant != ARM_PCS_AAPCS_LOCAL) + return false; + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch new file mode 100644 index 0000000000..92dfe00383 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch @@ -0,0 +1,27 @@ +2010-07-28 Julian Brown + + Backport from FSF mainline: + + gcc/ + * config/arm/thumb2.md (*thumb2_movdf_soft_insn): Fix alternatives + for pool ranges. + + 2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2010-08-13 10:30:35 +0000 ++++ new/gcc/config/arm/thumb2.md 2010-08-13 16:00:58 +0000 +@@ -319,8 +319,8 @@ + " + [(set_attr "length" "8,12,16,8,8") + (set_attr "type" "*,*,*,load2,store2") +- (set_attr "pool_range" "1020") +- (set_attr "neg_pool_range" "0")] ++ (set_attr "pool_range" "*,*,*,1020,*") ++ (set_attr "neg_pool_range" "*,*,*,0,*")] + ) + + (define_insn "*thumb2_cmpsi_shiftsi" + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch new file mode 100644 index 0000000000..a58dd24416 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch @@ -0,0 +1,1759 @@ +2010-07-28 Maxim Kuvyrkov + + Backport code hoisting improvements from mainline: + + 2010-07-28 Jakub Jelinek + PR debug/45105 + * gcc.dg/pr45105.c: New test. + + 2010-07-28 Jakub Jelinek + PR debug/45105 + * gcse.c (hoist_code): Use FOR_BB_INSNS macro. + + 2010-07-28 Maxim Kuvyrkov + PR rtl-optimization/45107 + * gcc.dg/pr45107.c: New test. + + 2010-07-28 Maxim Kuvyrkov + PR rtl-optimization/45107 + * gcse.c (hash_scan_set): Use max_distance for gcse-las. + + 2010-07-28 Maxim Kuvyrkov + PR rtl-optimization/45101 + * gcc.dg/pr45101.c: New test. + + 2010-07-28 Maxim Kuvyrkov + PR rtl-optimization/45101 + * gcse.c (hash_scan_set): Fix argument ordering of insert_expr_in_table + for gcse-las. + + 2010-07-27 Maxim Kuvyrkov + PR rtl-optimization/40956 + PR target/42495 + PR middle-end/42574 + * gcc.target/arm/pr40956.c, gcc.target/arm/pr42495.c, + * gcc.target/arm/pr42574.c: Add tests. + + 2010-07-27 Maxim Kuvyrkov + * config/arm/arm.c (params.h): Include. + (arm_override_options): Tune gcse-unrestricted-cost. + * config/arm/t-arm (arm.o): Define dependencies. + + 2010-07-27 Maxim Kuvyrkov + PR target/42495 + PR middle-end/42574 + * basic-block.h (get_dominated_to_depth): Declare. + * dominance.c (get_dominated_to_depth): New function, use + get_all_dominated_blocks as a base. + (get_all_dominated_blocks): Use get_dominated_to_depth. + * gcse.c (occr_t, VEC (occr_t, heap)): Define. + (hoist_exprs): Remove. + (alloc_code_hoist_mem, free_code_hoist_mem): Update. + (compute_code_hoist_vbeinout): Add debug print outs. + (hoist_code): Partially rewrite, simplify. Use get_dominated_to_depth. + * params.def (PARAM_MAX_HOIST_DEPTH): New parameter to avoid + quadratic behavior. + * params.h (MAX_HOIST_DEPTH): New macro. + * doc/invoke.texi (max-hoist-depth): Document. + + 2010-07-27 Maxim Kuvyrkov + PR rtl-optimization/40956 + * config/arm/arm.c (thumb1_size_rtx_costs): Fix cost of simple + constants. + + 2010-07-27 Maxim Kuvyrkov + PR target/42495 + PR middle-end/42574 + * config/arm/arm.c (legitimize_pic_address): Use + gen_calculate_pic_address pattern to emit calculation of PIC address. + (will_be_in_index_register): New function. + (arm_legitimate_address_outer_p, thumb2_legitimate_address_p,) + (thumb1_legitimate_address_p): Use it provided !strict_p. + * config/arm/arm.md (calculate_pic_address): New expand and split. + + 2010-07-27 Maxim Kuvyrkov + PR target/42495 + PR middle-end/42574 + * config/arm/arm.c (thumb1_size_rtx_costs): Add cost for "J" constants. + * config/arm/arm.md (define_split "J", define_split "K"): Make + IRA/reload friendly. + + 2010-07-27 Maxim Kuvyrkov + * gcse.c (insert_insn_end_basic_block): Update signature, remove + unused checks. + (pre_edge_insert, hoist_code): Update. + + 2010-07-27 Maxim Kuvyrkov + PR target/42495 + PR middle-end/42574 + * gcse.c (hoist_expr_reaches_here_p): Remove excessive check. + + 2010-07-27 Maxim Kuvyrkov + * gcse.c (hoist_code): Generate new pseudo for every new set insn. + + 2010-07-27 Maxim Kuvyrkov + PR rtl-optimization/40956 + PR target/42495 + PR middle-end/42574 + * gcse.c (compute_code_hoist_vbeinout): Consider more expressions + for hoisting. + (hoist_code): Count occurences in current block too. + + 2010-07-27 Maxim Kuvyrkov + * gcse.c (struct expr:max_distance): New field. + (doing_code_hoisting_p): New static variable. + (want_to_gcse_p): Change signature. Allow constrained hoisting of + simple expressions, don't change behavior for PRE. Set max_distance. + (insert_expr_in_table): Set new max_distance field. + (hash_scan_set): Update. + (hoist_expr_reaches_here_p): Stop search after max_distance + instructions. + (find_occr_in_bb): New static function. Use it in ... + (hoist_code): Calculate sizes of basic block before any changes are + done. Pass max_distance to hoist_expr_reaches_here_p. + (one_code_hoisting_pass): Set doing_code_hoisting_p. + * params.def (PARAM_GCSE_COST_DISTANCE_RATIO,) + (PARAM_GCSE_UNRESTRICTED_COST): New parameters. + * params.h (GCSE_COST_DISTANCE_RATIO, GCSE_UNRESTRICTED_COST): New + macros. + * doc/invoke.texi (gcse-cost-distance-ratio, gcse-unrestricted-cost): + Document. + + 2010-07-27 Jeff Law + Maxim Kuvyrkov + * gcse.c (compute_transpout, transpout): Remove, move logic + to prune_expressions. + (compute_pre_data): Move pruning of trapping expressions ... + (prune_expressions): ... here. New static function. + (compute_code_hoist_data): Use it. + (alloc_code_hoist_mem, free_code_hoist_mem, hoist_code): Update. + + 2010-07-27 Maxim Kuvyrkov + * dbgcnt.def (hoist_insn): New debug counter. + * gcse.c (hoist_code): Use it. + + 2010-07-28 Julian Brown + + Backport from FSF mainline: + +=== modified file 'gcc/basic-block.h' +--- old/gcc/basic-block.h 2010-04-02 18:54:46 +0000 ++++ new/gcc/basic-block.h 2010-08-16 09:41:58 +0000 +@@ -932,6 +932,8 @@ + extern VEC (basic_block, heap) *get_dominated_by_region (enum cdi_direction, + basic_block *, + unsigned); ++extern VEC (basic_block, heap) *get_dominated_to_depth (enum cdi_direction, ++ basic_block, int); + extern VEC (basic_block, heap) *get_all_dominated_blocks (enum cdi_direction, + basic_block); + extern void add_to_dominance_info (enum cdi_direction, basic_block); + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-13 15:37:39 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-16 09:41:58 +0000 +@@ -56,6 +56,7 @@ + #include "df.h" + #include "intl.h" + #include "libfuncs.h" ++#include "params.h" + + /* Forward definitions of types. */ + typedef struct minipool_node Mnode; +@@ -1902,6 +1903,14 @@ + flag_reorder_blocks = 1; + } + ++ if (!PARAM_SET_P (PARAM_GCSE_UNRESTRICTED_COST) ++ && flag_pic) ++ /* Hoisting PIC address calculations more aggressively provides a small, ++ but measurable, size reduction for PIC code. Therefore, we decrease ++ the bar for unrestricted expression hoisting to the cost of PIC address ++ calculation, which is 2 instructions. */ ++ set_param_value ("gcse-unrestricted-cost", 2); ++ + /* Register global variables with the garbage collector. */ + arm_add_gc_roots (); + +@@ -5070,17 +5079,13 @@ + if (GET_CODE (orig) == SYMBOL_REF + || GET_CODE (orig) == LABEL_REF) + { +- rtx pic_ref, address; + rtx insn; + + if (reg == 0) + { + gcc_assert (can_create_pseudo_p ()); + reg = gen_reg_rtx (Pmode); +- address = gen_reg_rtx (Pmode); + } +- else +- address = reg; + + /* VxWorks does not impose a fixed gap between segments; the run-time + gap can be different from the object-file gap. We therefore can't +@@ -5096,18 +5101,21 @@ + insn = arm_pic_static_addr (orig, reg); + else + { ++ rtx pat; ++ rtx mem; ++ + /* If this function doesn't have a pic register, create one now. */ + require_pic_register (); + +- if (TARGET_32BIT) +- emit_insn (gen_pic_load_addr_32bit (address, orig)); +- else /* TARGET_THUMB1 */ +- emit_insn (gen_pic_load_addr_thumb1 (address, orig)); +- +- pic_ref = gen_const_mem (Pmode, +- gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, +- address)); +- insn = emit_move_insn (reg, pic_ref); ++ pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig); ++ ++ /* Make the MEM as close to a constant as possible. */ ++ mem = SET_SRC (pat); ++ gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem)); ++ MEM_READONLY_P (mem) = 1; ++ MEM_NOTRAP_P (mem) = 1; ++ ++ insn = emit_insn (pat); + } + + /* Put a REG_EQUAL note on this insn, so that it can be optimized +@@ -5387,6 +5395,15 @@ + return FALSE; + } + ++/* Return true if X will surely end up in an index register after next ++ splitting pass. */ ++static bool ++will_be_in_index_register (const_rtx x) ++{ ++ /* arm.md: calculate_pic_address will split this into a register. */ ++ return GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_SYM; ++} ++ + /* Return nonzero if X is a valid ARM state address operand. */ + int + arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, +@@ -5444,8 +5461,9 @@ + rtx xop1 = XEXP (x, 1); + + return ((arm_address_register_rtx_p (xop0, strict_p) +- && GET_CODE(xop1) == CONST_INT +- && arm_legitimate_index_p (mode, xop1, outer, strict_p)) ++ && ((GET_CODE(xop1) == CONST_INT ++ && arm_legitimate_index_p (mode, xop1, outer, strict_p)) ++ || (!strict_p && will_be_in_index_register (xop1)))) + || (arm_address_register_rtx_p (xop1, strict_p) + && arm_legitimate_index_p (mode, xop0, outer, strict_p))); + } +@@ -5531,7 +5549,8 @@ + rtx xop1 = XEXP (x, 1); + + return ((arm_address_register_rtx_p (xop0, strict_p) +- && thumb2_legitimate_index_p (mode, xop1, strict_p)) ++ && (thumb2_legitimate_index_p (mode, xop1, strict_p) ++ || (!strict_p && will_be_in_index_register (xop1)))) + || (arm_address_register_rtx_p (xop1, strict_p) + && thumb2_legitimate_index_p (mode, xop0, strict_p))); + } +@@ -5834,7 +5853,8 @@ + && XEXP (x, 0) != frame_pointer_rtx + && XEXP (x, 1) != frame_pointer_rtx + && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) +- && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)) ++ && (thumb1_index_register_rtx_p (XEXP (x, 1), strict_p) ++ || (!strict_p && will_be_in_index_register (XEXP (x, 1))))) + return 1; + + /* REG+const has 5-7 bit offset for non-SP registers. */ +@@ -6413,12 +6433,16 @@ + + case CONST_INT: + if (outer == SET) +- { +- if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) +- return 0; +- if (thumb_shiftable_const (INTVAL (x))) +- return COSTS_N_INSNS (2); +- return COSTS_N_INSNS (3); ++ { ++ if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) ++ return COSTS_N_INSNS (1); ++ /* See split "TARGET_THUMB1 && satisfies_constraint_J". */ ++ if (INTVAL (x) >= -255 && INTVAL (x) <= -1) ++ return COSTS_N_INSNS (2); ++ /* See split "TARGET_THUMB1 && satisfies_constraint_K". */ ++ if (thumb_shiftable_const (INTVAL (x))) ++ return COSTS_N_INSNS (2); ++ return COSTS_N_INSNS (3); + } + else if ((outer == PLUS || outer == COMPARE) + && INTVAL (x) < 256 && INTVAL (x) > -256) +@@ -7110,6 +7134,12 @@ + a single register, otherwise it costs one insn per word. */ + if (REG_P (XEXP (x, 0))) + *total = COSTS_N_INSNS (1); ++ else if (flag_pic ++ && GET_CODE (XEXP (x, 0)) == PLUS ++ && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) ++ /* This will be split into two instructions. ++ See arm.md:calculate_pic_address. */ ++ *total = COSTS_N_INSNS (2); + else + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + return true; + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-13 15:15:12 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-16 09:41:58 +0000 +@@ -5290,17 +5290,21 @@ + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "const_int_operand" ""))] + "TARGET_THUMB1 && satisfies_constraint_J (operands[1])" +- [(set (match_dup 0) (match_dup 1)) +- (set (match_dup 0) (neg:SI (match_dup 0)))] +- "operands[1] = GEN_INT (- INTVAL (operands[1]));" ++ [(set (match_dup 2) (match_dup 1)) ++ (set (match_dup 0) (neg:SI (match_dup 2)))] ++ " ++ { ++ operands[1] = GEN_INT (- INTVAL (operands[1])); ++ operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; ++ }" + ) + + (define_split + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "const_int_operand" ""))] + "TARGET_THUMB1 && satisfies_constraint_K (operands[1])" +- [(set (match_dup 0) (match_dup 1)) +- (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))] ++ [(set (match_dup 2) (match_dup 1)) ++ (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))] + " + { + unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu; +@@ -5311,12 +5315,13 @@ + if ((val & (mask << i)) == val) + break; + +- /* Shouldn't happen, but we don't want to split if the shift is zero. */ ++ /* Don't split if the shift is zero. */ + if (i == 0) + FAIL; + + operands[1] = GEN_INT (val >> i); +- operands[2] = GEN_INT (i); ++ operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; ++ operands[3] = GEN_INT (i); + }" + ) + +@@ -5325,6 +5330,34 @@ + ;; we use an unspec. The offset will be loaded from a constant pool entry, + ;; since that is the only type of relocation we can use. + ++;; Wrap calculation of the whole PIC address in a single pattern for the ++;; benefit of optimizers, particularly, PRE and HOIST. Calculation of ++;; a PIC address involves two loads from memory, so we want to CSE it ++;; as often as possible. ++;; This pattern will be split into one of the pic_load_addr_* patterns ++;; and a move after GCSE optimizations. ++;; ++;; Note: Update arm.c: legitimize_pic_address() when changing this pattern. ++(define_expand "calculate_pic_address" ++ [(set (match_operand:SI 0 "register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "") ++ (unspec:SI [(match_operand:SI 2 "" "")] ++ UNSPEC_PIC_SYM))))] ++ "flag_pic" ++) ++ ++;; Split calculate_pic_address into pic_load_addr_* and a move. ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "") ++ (unspec:SI [(match_operand:SI 2 "" "")] ++ UNSPEC_PIC_SYM))))] ++ "flag_pic" ++ [(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_PIC_SYM)) ++ (set (match_dup 0) (mem:SI (plus:SI (match_dup 1) (match_dup 3))))] ++ "operands[3] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];" ++) ++ + ;; The rather odd constraints on the following are to force reload to leave + ;; the insn alone, and to force the minipool generation pass to then move + ;; the GOT symbol to memory. + +=== modified file 'gcc/config/arm/t-arm' +--- old/gcc/config/arm/t-arm 2009-06-21 19:48:15 +0000 ++++ new/gcc/config/arm/t-arm 2010-08-16 09:41:58 +0000 +@@ -45,6 +45,15 @@ + $(srcdir)/config/arm/arm-cores.def > \ + $(srcdir)/config/arm/arm-tune.md + ++arm.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ ++ $(RTL_H) $(TREE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \ ++ insn-config.h conditions.h output.h \ ++ $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \ ++ $(EXPR_H) $(OPTABS_H) toplev.h $(RECOG_H) $(CGRAPH_H) \ ++ $(GGC_H) except.h $(C_PRAGMA_H) $(INTEGRATE_H) $(TM_P_H) \ ++ $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \ ++ intl.h libfuncs.h $(PARAMS_H) ++ + arm-c.o: $(srcdir)/config/arm/arm-c.c $(CONFIG_H) $(SYSTEM_H) \ + coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + +=== modified file 'gcc/dbgcnt.def' +--- old/gcc/dbgcnt.def 2009-11-25 10:55:54 +0000 ++++ new/gcc/dbgcnt.def 2010-08-16 09:41:58 +0000 +@@ -158,6 +158,7 @@ + DEBUG_COUNTER (global_alloc_at_func) + DEBUG_COUNTER (global_alloc_at_reg) + DEBUG_COUNTER (hoist) ++DEBUG_COUNTER (hoist_insn) + DEBUG_COUNTER (ia64_sched2) + DEBUG_COUNTER (if_conversion) + DEBUG_COUNTER (if_after_combine) + +=== modified file 'gcc/doc/invoke.texi' +--- old/gcc/doc/invoke.texi 2010-08-05 15:20:54 +0000 ++++ new/gcc/doc/invoke.texi 2010-08-16 09:41:58 +0000 +@@ -8086,6 +8086,29 @@ + vectorization needs to be greater than the value specified by this option + to allow vectorization. The default value is 0. + ++@item gcse-cost-distance-ratio ++Scaling factor in calculation of maximum distance an expression ++can be moved by GCSE optimizations. This is currently supported only in ++code hoisting pass. The bigger the ratio, the more agressive code hoisting ++will be with simple expressions, i.e., the expressions which have cost ++less than @option{gcse-unrestricted-cost}. Specifying 0 will disable ++hoisting of simple expressions. The default value is 10. ++ ++@item gcse-unrestricted-cost ++Cost, roughly measured as the cost of a single typical machine ++instruction, at which GCSE optimizations will not constrain ++the distance an expression can travel. This is currently ++supported only in code hoisting pass. The lesser the cost, ++the more aggressive code hoisting will be. Specifying 0 will ++allow all expressions to travel unrestricted distances. ++The default value is 3. ++ ++@item max-hoist-depth ++The depth of search in the dominator tree for expressions to hoist. ++This is used to avoid quadratic behavior in hoisting algorithm. ++The value of 0 will avoid limiting the search, but may slow down compilation ++of huge functions. The default value is 30. ++ + @item max-unrolled-insns + The maximum number of instructions that a loop should have if that loop + is unrolled, and if the loop is unrolled, it determines how many times + +=== modified file 'gcc/dominance.c' +--- old/gcc/dominance.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/dominance.c 2010-08-16 09:41:58 +0000 +@@ -782,16 +782,20 @@ + } + + /* Returns the list of basic blocks including BB dominated by BB, in the +- direction DIR. The vector will be sorted in preorder. */ ++ direction DIR up to DEPTH in the dominator tree. The DEPTH of zero will ++ produce a vector containing all dominated blocks. The vector will be sorted ++ in preorder. */ + + VEC (basic_block, heap) * +-get_all_dominated_blocks (enum cdi_direction dir, basic_block bb) ++get_dominated_to_depth (enum cdi_direction dir, basic_block bb, int depth) + { + VEC(basic_block, heap) *bbs = NULL; + unsigned i; ++ unsigned next_level_start; + + i = 0; + VEC_safe_push (basic_block, heap, bbs, bb); ++ next_level_start = 1; /* = VEC_length (basic_block, bbs); */ + + do + { +@@ -802,12 +806,24 @@ + son; + son = next_dom_son (dir, son)) + VEC_safe_push (basic_block, heap, bbs, son); ++ ++ if (i == next_level_start && --depth) ++ next_level_start = VEC_length (basic_block, bbs); + } +- while (i < VEC_length (basic_block, bbs)); ++ while (i < next_level_start); + + return bbs; + } + ++/* Returns the list of basic blocks including BB dominated by BB, in the ++ direction DIR. The vector will be sorted in preorder. */ ++ ++VEC (basic_block, heap) * ++get_all_dominated_blocks (enum cdi_direction dir, basic_block bb) ++{ ++ return get_dominated_to_depth (dir, bb, 0); ++} ++ + /* Redirect all edges pointing to BB to TO. */ + void + redirect_immediate_dominators (enum cdi_direction dir, basic_block bb, + +=== modified file 'gcc/gcse.c' +--- old/gcc/gcse.c 2010-03-16 10:50:42 +0000 ++++ new/gcc/gcse.c 2010-08-16 09:41:58 +0000 +@@ -296,6 +296,12 @@ + The value is the newly created pseudo-reg to record a copy of the + expression in all the places that reach the redundant copy. */ + rtx reaching_reg; ++ /* Maximum distance in instructions this expression can travel. ++ We avoid moving simple expressions for more than a few instructions ++ to keep register pressure under control. ++ A value of "0" removes restrictions on how far the expression can ++ travel. */ ++ int max_distance; + }; + + /* Occurrence of an expression. +@@ -317,6 +323,10 @@ + char copied_p; + }; + ++typedef struct occr *occr_t; ++DEF_VEC_P (occr_t); ++DEF_VEC_ALLOC_P (occr_t, heap); ++ + /* Expression and copy propagation hash tables. + Each hash table is an array of buckets. + ??? It is known that if it were an array of entries, structure elements +@@ -419,6 +429,9 @@ + /* Number of global copies propagated. */ + static int global_copy_prop_count; + ++/* Doing code hoisting. */ ++static bool doing_code_hoisting_p = false; ++ + /* For available exprs */ + static sbitmap *ae_kill; + +@@ -432,12 +445,12 @@ + static void hash_scan_set (rtx, rtx, struct hash_table_d *); + static void hash_scan_clobber (rtx, rtx, struct hash_table_d *); + static void hash_scan_call (rtx, rtx, struct hash_table_d *); +-static int want_to_gcse_p (rtx); ++static int want_to_gcse_p (rtx, int *); + static bool gcse_constant_p (const_rtx); + static int oprs_unchanged_p (const_rtx, const_rtx, int); + static int oprs_anticipatable_p (const_rtx, const_rtx); + static int oprs_available_p (const_rtx, const_rtx); +-static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, ++static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, int, + struct hash_table_d *); + static void insert_set_in_table (rtx, rtx, struct hash_table_d *); + static unsigned int hash_expr (const_rtx, enum machine_mode, int *, int); +@@ -462,7 +475,6 @@ + static void alloc_cprop_mem (int, int); + static void free_cprop_mem (void); + static void compute_transp (const_rtx, int, sbitmap *, int); +-static void compute_transpout (void); + static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *, + struct hash_table_d *); + static void compute_cprop_data (void); +@@ -486,7 +498,7 @@ + static void compute_pre_data (void); + static int pre_expr_reaches_here_p (basic_block, struct expr *, + basic_block); +-static void insert_insn_end_basic_block (struct expr *, basic_block, int); ++static void insert_insn_end_basic_block (struct expr *, basic_block); + static void pre_insert_copy_insn (struct expr *, rtx); + static void pre_insert_copies (void); + static int pre_delete (void); +@@ -497,7 +509,8 @@ + static void free_code_hoist_mem (void); + static void compute_code_hoist_vbeinout (void); + static void compute_code_hoist_data (void); +-static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *); ++static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *, ++ int, int *); + static int hoist_code (void); + static int one_code_hoisting_pass (void); + static rtx process_insert_insn (struct expr *); +@@ -755,7 +768,7 @@ + GCSE. */ + + static int +-want_to_gcse_p (rtx x) ++want_to_gcse_p (rtx x, int *max_distance_ptr) + { + #ifdef STACK_REGS + /* On register stack architectures, don't GCSE constants from the +@@ -765,18 +778,67 @@ + x = avoid_constant_pool_reference (x); + #endif + ++ /* GCSE'ing constants: ++ ++ We do not specifically distinguish between constant and non-constant ++ expressions in PRE and Hoist. We use rtx_cost below to limit ++ the maximum distance simple expressions can travel. ++ ++ Nevertheless, constants are much easier to GCSE, and, hence, ++ it is easy to overdo the optimizations. Usually, excessive PRE and ++ Hoisting of constant leads to increased register pressure. ++ ++ RA can deal with this by rematerialing some of the constants. ++ Therefore, it is important that the back-end generates sets of constants ++ in a way that allows reload rematerialize them under high register ++ pressure, i.e., a pseudo register with REG_EQUAL to constant ++ is set only once. Failing to do so will result in IRA/reload ++ spilling such constants under high register pressure instead of ++ rematerializing them. */ ++ + switch (GET_CODE (x)) + { + case REG: + case SUBREG: +- case CONST_INT: +- case CONST_DOUBLE: +- case CONST_FIXED: +- case CONST_VECTOR: + case CALL: + return 0; + ++ case CONST_INT: ++ case CONST_DOUBLE: ++ case CONST_FIXED: ++ case CONST_VECTOR: ++ if (!doing_code_hoisting_p) ++ /* Do not PRE constants. */ ++ return 0; ++ ++ /* FALLTHRU */ ++ + default: ++ if (doing_code_hoisting_p) ++ /* PRE doesn't implement max_distance restriction. */ ++ { ++ int cost; ++ int max_distance; ++ ++ gcc_assert (!optimize_function_for_speed_p (cfun) ++ && optimize_function_for_size_p (cfun)); ++ cost = rtx_cost (x, SET, 0); ++ ++ if (cost < COSTS_N_INSNS (GCSE_UNRESTRICTED_COST)) ++ { ++ max_distance = (GCSE_COST_DISTANCE_RATIO * cost) / 10; ++ if (max_distance == 0) ++ return 0; ++ ++ gcc_assert (max_distance > 0); ++ } ++ else ++ max_distance = 0; ++ ++ if (max_distance_ptr) ++ *max_distance_ptr = max_distance; ++ } ++ + return can_assign_to_reg_without_clobbers_p (x); + } + } +@@ -1090,11 +1152,14 @@ + It is only used if X is a CONST_INT. + + ANTIC_P is nonzero if X is an anticipatable expression. +- AVAIL_P is nonzero if X is an available expression. */ ++ AVAIL_P is nonzero if X is an available expression. ++ ++ MAX_DISTANCE is the maximum distance in instructions this expression can ++ be moved. */ + + static void + insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p, +- int avail_p, struct hash_table_d *table) ++ int avail_p, int max_distance, struct hash_table_d *table) + { + int found, do_not_record_p; + unsigned int hash; +@@ -1137,7 +1202,11 @@ + cur_expr->next_same_hash = NULL; + cur_expr->antic_occr = NULL; + cur_expr->avail_occr = NULL; ++ gcc_assert (max_distance >= 0); ++ cur_expr->max_distance = max_distance; + } ++ else ++ gcc_assert (cur_expr->max_distance == max_distance); + + /* Now record the occurrence(s). */ + if (antic_p) +@@ -1238,6 +1307,8 @@ + cur_expr->next_same_hash = NULL; + cur_expr->antic_occr = NULL; + cur_expr->avail_occr = NULL; ++ /* Not used for set_p tables. */ ++ cur_expr->max_distance = 0; + } + + /* Now record the occurrence. */ +@@ -1307,6 +1378,7 @@ + { + unsigned int regno = REGNO (dest); + rtx tmp; ++ int max_distance = 0; + + /* See if a REG_EQUAL note shows this equivalent to a simpler expression. + +@@ -1329,7 +1401,7 @@ + && !REG_P (src) + && (table->set_p + ? gcse_constant_p (XEXP (note, 0)) +- : want_to_gcse_p (XEXP (note, 0)))) ++ : want_to_gcse_p (XEXP (note, 0), NULL))) + src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src); + + /* Only record sets of pseudo-regs in the hash table. */ +@@ -1344,7 +1416,7 @@ + can't do the same thing at the rtl level. */ + && !can_throw_internal (insn) + /* Is SET_SRC something we want to gcse? */ +- && want_to_gcse_p (src) ++ && want_to_gcse_p (src, &max_distance) + /* Don't CSE a nop. */ + && ! set_noop_p (pat) + /* Don't GCSE if it has attached REG_EQUIV note. +@@ -1368,7 +1440,8 @@ + int avail_p = (oprs_available_p (src, insn) + && ! JUMP_P (insn)); + +- insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, table); ++ insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, ++ max_distance, table); + } + + /* Record sets for constant/copy propagation. */ +@@ -1394,6 +1467,7 @@ + else if (flag_gcse_las && REG_P (src) && MEM_P (dest)) + { + unsigned int regno = REGNO (src); ++ int max_distance = 0; + + /* Do not do this for constant/copy propagation. */ + if (! table->set_p +@@ -1405,7 +1479,7 @@ + do that easily for EH edges so disable GCSE on these for now. */ + && !can_throw_internal (insn) + /* Is SET_DEST something we want to gcse? */ +- && want_to_gcse_p (dest) ++ && want_to_gcse_p (dest, &max_distance) + /* Don't CSE a nop. */ + && ! set_noop_p (pat) + /* Don't GCSE if it has attached REG_EQUIV note. +@@ -1427,7 +1501,7 @@ + + /* Record the memory expression (DEST) in the hash table. */ + insert_expr_in_table (dest, GET_MODE (dest), insn, +- antic_p, avail_p, table); ++ antic_p, avail_p, max_distance, table); + } + } + } +@@ -1513,8 +1587,8 @@ + if (flat_table[i] != 0) + { + expr = flat_table[i]; +- fprintf (file, "Index %d (hash value %d)\n ", +- expr->bitmap_index, hash_val[i]); ++ fprintf (file, "Index %d (hash value %d; max distance %d)\n ", ++ expr->bitmap_index, hash_val[i], expr->max_distance); + print_rtl (file, expr->expr); + fprintf (file, "\n"); + } +@@ -3168,11 +3242,6 @@ + /* Nonzero for expressions that are transparent in the block. */ + static sbitmap *transp; + +-/* Nonzero for expressions that are transparent at the end of the block. +- This is only zero for expressions killed by abnormal critical edge +- created by a calls. */ +-static sbitmap *transpout; +- + /* Nonzero for expressions that are computed (available) in the block. */ + static sbitmap *comp; + +@@ -3236,28 +3305,105 @@ + pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL; + } + +-/* Top level routine to do the dataflow analysis needed by PRE. */ ++/* Remove certain expressions from anticipatable and transparent ++ sets of basic blocks that have incoming abnormal edge. ++ For PRE remove potentially trapping expressions to avoid placing ++ them on abnormal edges. For hoisting remove memory references that ++ can be clobbered by calls. */ + + static void +-compute_pre_data (void) ++prune_expressions (bool pre_p) + { +- sbitmap trapping_expr; +- basic_block bb; ++ sbitmap prune_exprs; + unsigned int ui; +- +- compute_local_properties (transp, comp, antloc, &expr_hash_table); +- sbitmap_vector_zero (ae_kill, last_basic_block); +- +- /* Collect expressions which might trap. */ +- trapping_expr = sbitmap_alloc (expr_hash_table.n_elems); +- sbitmap_zero (trapping_expr); ++ basic_block bb; ++ ++ prune_exprs = sbitmap_alloc (expr_hash_table.n_elems); ++ sbitmap_zero (prune_exprs); + for (ui = 0; ui < expr_hash_table.size; ui++) + { + struct expr *e; + for (e = expr_hash_table.table[ui]; e != NULL; e = e->next_same_hash) +- if (may_trap_p (e->expr)) +- SET_BIT (trapping_expr, e->bitmap_index); +- } ++ { ++ /* Note potentially trapping expressions. */ ++ if (may_trap_p (e->expr)) ++ { ++ SET_BIT (prune_exprs, e->bitmap_index); ++ continue; ++ } ++ ++ if (!pre_p && MEM_P (e->expr)) ++ /* Note memory references that can be clobbered by a call. ++ We do not split abnormal edges in hoisting, so would ++ a memory reference get hoisted along an abnormal edge, ++ it would be placed /before/ the call. Therefore, only ++ constant memory references can be hoisted along abnormal ++ edges. */ ++ { ++ if (GET_CODE (XEXP (e->expr, 0)) == SYMBOL_REF ++ && CONSTANT_POOL_ADDRESS_P (XEXP (e->expr, 0))) ++ continue; ++ ++ if (MEM_READONLY_P (e->expr) ++ && !MEM_VOLATILE_P (e->expr) ++ && MEM_NOTRAP_P (e->expr)) ++ /* Constant memory reference, e.g., a PIC address. */ ++ continue; ++ ++ /* ??? Optimally, we would use interprocedural alias ++ analysis to determine if this mem is actually killed ++ by this call. */ ++ ++ SET_BIT (prune_exprs, e->bitmap_index); ++ } ++ } ++ } ++ ++ FOR_EACH_BB (bb) ++ { ++ edge e; ++ edge_iterator ei; ++ ++ /* If the current block is the destination of an abnormal edge, we ++ kill all trapping (for PRE) and memory (for hoist) expressions ++ because we won't be able to properly place the instruction on ++ the edge. So make them neither anticipatable nor transparent. ++ This is fairly conservative. ++ ++ ??? For hoisting it may be necessary to check for set-and-jump ++ instructions here, not just for abnormal edges. The general problem ++ is that when an expression cannot not be placed right at the end of ++ a basic block we should account for any side-effects of a subsequent ++ jump instructions that could clobber the expression. It would ++ be best to implement this check along the lines of ++ hoist_expr_reaches_here_p where the target block is already known ++ and, hence, there's no need to conservatively prune expressions on ++ "intermediate" set-and-jump instructions. */ ++ FOR_EACH_EDGE (e, ei, bb->preds) ++ if ((e->flags & EDGE_ABNORMAL) ++ && (pre_p || CALL_P (BB_END (e->src)))) ++ { ++ sbitmap_difference (antloc[bb->index], ++ antloc[bb->index], prune_exprs); ++ sbitmap_difference (transp[bb->index], ++ transp[bb->index], prune_exprs); ++ break; ++ } ++ } ++ ++ sbitmap_free (prune_exprs); ++} ++ ++/* Top level routine to do the dataflow analysis needed by PRE. */ ++ ++static void ++compute_pre_data (void) ++{ ++ basic_block bb; ++ ++ compute_local_properties (transp, comp, antloc, &expr_hash_table); ++ prune_expressions (true); ++ sbitmap_vector_zero (ae_kill, last_basic_block); + + /* Compute ae_kill for each basic block using: + +@@ -3266,21 +3412,6 @@ + + FOR_EACH_BB (bb) + { +- edge e; +- edge_iterator ei; +- +- /* If the current block is the destination of an abnormal edge, we +- kill all trapping expressions because we won't be able to properly +- place the instruction on the edge. So make them neither +- anticipatable nor transparent. This is fairly conservative. */ +- FOR_EACH_EDGE (e, ei, bb->preds) +- if (e->flags & EDGE_ABNORMAL) +- { +- sbitmap_difference (antloc[bb->index], antloc[bb->index], trapping_expr); +- sbitmap_difference (transp[bb->index], transp[bb->index], trapping_expr); +- break; +- } +- + sbitmap_a_or_b (ae_kill[bb->index], transp[bb->index], comp[bb->index]); + sbitmap_not (ae_kill[bb->index], ae_kill[bb->index]); + } +@@ -3291,7 +3422,6 @@ + antloc = NULL; + sbitmap_vector_free (ae_kill); + ae_kill = NULL; +- sbitmap_free (trapping_expr); + } + + /* PRE utilities */ +@@ -3406,14 +3536,10 @@ + + /* Add EXPR to the end of basic block BB. + +- This is used by both the PRE and code hoisting. +- +- For PRE, we want to verify that the expr is either transparent +- or locally anticipatable in the target block. This check makes +- no sense for code hoisting. */ ++ This is used by both the PRE and code hoisting. */ + + static void +-insert_insn_end_basic_block (struct expr *expr, basic_block bb, int pre) ++insert_insn_end_basic_block (struct expr *expr, basic_block bb) + { + rtx insn = BB_END (bb); + rtx new_insn; +@@ -3440,12 +3566,6 @@ + #ifdef HAVE_cc0 + rtx note; + #endif +- /* It should always be the case that we can put these instructions +- anywhere in the basic block with performing PRE optimizations. +- Check this. */ +- gcc_assert (!NONJUMP_INSN_P (insn) || !pre +- || TEST_BIT (antloc[bb->index], expr->bitmap_index) +- || TEST_BIT (transp[bb->index], expr->bitmap_index)); + + /* If this is a jump table, then we can't insert stuff here. Since + we know the previous real insn must be the tablejump, we insert +@@ -3482,15 +3602,7 @@ + /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers, + we search backward and place the instructions before the first + parameter is loaded. Do this for everyone for consistency and a +- presumption that we'll get better code elsewhere as well. +- +- It should always be the case that we can put these instructions +- anywhere in the basic block with performing PRE optimizations. +- Check this. */ +- +- gcc_assert (!pre +- || TEST_BIT (antloc[bb->index], expr->bitmap_index) +- || TEST_BIT (transp[bb->index], expr->bitmap_index)); ++ presumption that we'll get better code elsewhere as well. */ + + /* Since different machines initialize their parameter registers + in different orders, assume nothing. Collect the set of all +@@ -3587,7 +3699,7 @@ + now. */ + + if (eg->flags & EDGE_ABNORMAL) +- insert_insn_end_basic_block (index_map[j], bb, 0); ++ insert_insn_end_basic_block (index_map[j], bb); + else + { + insn = process_insert_insn (index_map[j]); +@@ -4046,61 +4158,12 @@ + } + } + +-/* Compute transparent outgoing information for each block. +- +- An expression is transparent to an edge unless it is killed by +- the edge itself. This can only happen with abnormal control flow, +- when the edge is traversed through a call. This happens with +- non-local labels and exceptions. +- +- This would not be necessary if we split the edge. While this is +- normally impossible for abnormal critical edges, with some effort +- it should be possible with exception handling, since we still have +- control over which handler should be invoked. But due to increased +- EH table sizes, this may not be worthwhile. */ +- +-static void +-compute_transpout (void) +-{ +- basic_block bb; +- unsigned int i; +- struct expr *expr; +- +- sbitmap_vector_ones (transpout, last_basic_block); +- +- FOR_EACH_BB (bb) +- { +- /* Note that flow inserted a nop at the end of basic blocks that +- end in call instructions for reasons other than abnormal +- control flow. */ +- if (! CALL_P (BB_END (bb))) +- continue; +- +- for (i = 0; i < expr_hash_table.size; i++) +- for (expr = expr_hash_table.table[i]; expr ; expr = expr->next_same_hash) +- if (MEM_P (expr->expr)) +- { +- if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF +- && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0))) +- continue; +- +- /* ??? Optimally, we would use interprocedural alias +- analysis to determine if this mem is actually killed +- by this call. */ +- RESET_BIT (transpout[bb->index], expr->bitmap_index); +- } +- } +-} +- + /* Code Hoisting variables and subroutines. */ + + /* Very busy expressions. */ + static sbitmap *hoist_vbein; + static sbitmap *hoist_vbeout; + +-/* Hoistable expressions. */ +-static sbitmap *hoist_exprs; +- + /* ??? We could compute post dominators and run this algorithm in + reverse to perform tail merging, doing so would probably be + more effective than the tail merging code in jump.c. +@@ -4119,8 +4182,6 @@ + + hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs); + hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs); +- hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs); +- transpout = sbitmap_vector_alloc (n_blocks, n_exprs); + } + + /* Free vars used for code hoisting analysis. */ +@@ -4134,8 +4195,6 @@ + + sbitmap_vector_free (hoist_vbein); + sbitmap_vector_free (hoist_vbeout); +- sbitmap_vector_free (hoist_exprs); +- sbitmap_vector_free (transpout); + + free_dominance_info (CDI_DOMINATORS); + } +@@ -4166,8 +4225,15 @@ + FOR_EACH_BB_REVERSE (bb) + { + if (bb->next_bb != EXIT_BLOCK_PTR) +- sbitmap_intersection_of_succs (hoist_vbeout[bb->index], +- hoist_vbein, bb->index); ++ { ++ sbitmap_intersection_of_succs (hoist_vbeout[bb->index], ++ hoist_vbein, bb->index); ++ ++ /* Include expressions in VBEout that are calculated ++ in BB and available at its end. */ ++ sbitmap_a_or_b (hoist_vbeout[bb->index], ++ hoist_vbeout[bb->index], comp[bb->index]); ++ } + + changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb->index], + antloc[bb->index], +@@ -4179,7 +4245,17 @@ + } + + if (dump_file) +- fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes); ++ { ++ fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes); ++ ++ FOR_EACH_BB (bb) ++ { ++ fprintf (dump_file, "vbein (%d): ", bb->index); ++ dump_sbitmap_file (dump_file, hoist_vbein[bb->index]); ++ fprintf (dump_file, "vbeout(%d): ", bb->index); ++ dump_sbitmap_file (dump_file, hoist_vbeout[bb->index]); ++ } ++ } + } + + /* Top level routine to do the dataflow analysis needed by code hoisting. */ +@@ -4188,7 +4264,7 @@ + compute_code_hoist_data (void) + { + compute_local_properties (transp, comp, antloc, &expr_hash_table); +- compute_transpout (); ++ prune_expressions (false); + compute_code_hoist_vbeinout (); + calculate_dominance_info (CDI_DOMINATORS); + if (dump_file) +@@ -4197,6 +4273,8 @@ + + /* Determine if the expression identified by EXPR_INDEX would + reach BB unimpared if it was placed at the end of EXPR_BB. ++ Stop the search if the expression would need to be moved more ++ than DISTANCE instructions. + + It's unclear exactly what Muchnick meant by "unimpared". It seems + to me that the expression must either be computed or transparent in +@@ -4209,12 +4287,24 @@ + paths. */ + + static int +-hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, char *visited) ++hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, ++ char *visited, int distance, int *bb_size) + { + edge pred; + edge_iterator ei; + int visited_allocated_locally = 0; + ++ /* Terminate the search if distance, for which EXPR is allowed to move, ++ is exhausted. */ ++ if (distance > 0) ++ { ++ distance -= bb_size[bb->index]; ++ ++ if (distance <= 0) ++ return 0; ++ } ++ else ++ gcc_assert (distance == 0); + + if (visited == NULL) + { +@@ -4233,9 +4323,6 @@ + else if (visited[pred_bb->index]) + continue; + +- /* Does this predecessor generate this expression? */ +- else if (TEST_BIT (comp[pred_bb->index], expr_index)) +- break; + else if (! TEST_BIT (transp[pred_bb->index], expr_index)) + break; + +@@ -4243,8 +4330,8 @@ + else + { + visited[pred_bb->index] = 1; +- if (! hoist_expr_reaches_here_p (expr_bb, expr_index, +- pred_bb, visited)) ++ if (! hoist_expr_reaches_here_p (expr_bb, expr_index, pred_bb, ++ visited, distance, bb_size)) + break; + } + } +@@ -4254,20 +4341,33 @@ + return (pred == NULL); + } + ++/* Find occurence in BB. */ ++static struct occr * ++find_occr_in_bb (struct occr *occr, basic_block bb) ++{ ++ /* Find the right occurrence of this expression. */ ++ while (occr && BLOCK_FOR_INSN (occr->insn) != bb) ++ occr = occr->next; ++ ++ return occr; ++} ++ + /* Actually perform code hoisting. */ + + static int + hoist_code (void) + { + basic_block bb, dominated; ++ VEC (basic_block, heap) *dom_tree_walk; ++ unsigned int dom_tree_walk_index; + VEC (basic_block, heap) *domby; + unsigned int i,j; + struct expr **index_map; + struct expr *expr; ++ int *to_bb_head; ++ int *bb_size; + int changed = 0; + +- sbitmap_vector_zero (hoist_exprs, last_basic_block); +- + /* Compute a mapping from expression number (`bitmap_index') to + hash table entry. */ + +@@ -4276,28 +4376,98 @@ + for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash) + index_map[expr->bitmap_index] = expr; + ++ /* Calculate sizes of basic blocks and note how far ++ each instruction is from the start of its block. We then use this ++ data to restrict distance an expression can travel. */ ++ ++ to_bb_head = XCNEWVEC (int, get_max_uid ()); ++ bb_size = XCNEWVEC (int, last_basic_block); ++ ++ FOR_EACH_BB (bb) ++ { ++ rtx insn; ++ int to_head; ++ ++ to_head = 0; ++ FOR_BB_INSNS (bb, insn) ++ { ++ /* Don't count debug instructions to avoid them affecting ++ decision choices. */ ++ if (NONDEBUG_INSN_P (insn)) ++ to_bb_head[INSN_UID (insn)] = to_head++; ++ } ++ ++ bb_size[bb->index] = to_head; ++ } ++ ++ gcc_assert (EDGE_COUNT (ENTRY_BLOCK_PTR->succs) == 1 ++ && (EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest ++ == ENTRY_BLOCK_PTR->next_bb)); ++ ++ dom_tree_walk = get_all_dominated_blocks (CDI_DOMINATORS, ++ ENTRY_BLOCK_PTR->next_bb); ++ + /* Walk over each basic block looking for potentially hoistable + expressions, nothing gets hoisted from the entry block. */ +- FOR_EACH_BB (bb) ++ for (dom_tree_walk_index = 0; ++ VEC_iterate (basic_block, dom_tree_walk, dom_tree_walk_index, bb); ++ dom_tree_walk_index++) + { +- int found = 0; +- int insn_inserted_p; +- +- domby = get_dominated_by (CDI_DOMINATORS, bb); ++ domby = get_dominated_to_depth (CDI_DOMINATORS, bb, MAX_HOIST_DEPTH); ++ ++ if (VEC_length (basic_block, domby) == 0) ++ continue; ++ + /* Examine each expression that is very busy at the exit of this + block. These are the potentially hoistable expressions. */ + for (i = 0; i < hoist_vbeout[bb->index]->n_bits; i++) + { +- int hoistable = 0; +- +- if (TEST_BIT (hoist_vbeout[bb->index], i) +- && TEST_BIT (transpout[bb->index], i)) ++ if (TEST_BIT (hoist_vbeout[bb->index], i)) + { ++ /* Current expression. */ ++ struct expr *expr = index_map[i]; ++ /* Number of occurences of EXPR that can be hoisted to BB. */ ++ int hoistable = 0; ++ /* Basic blocks that have occurences reachable from BB. */ ++ bitmap_head _from_bbs, *from_bbs = &_from_bbs; ++ /* Occurences reachable from BB. */ ++ VEC (occr_t, heap) *occrs_to_hoist = NULL; ++ /* We want to insert the expression into BB only once, so ++ note when we've inserted it. */ ++ int insn_inserted_p; ++ occr_t occr; ++ ++ bitmap_initialize (from_bbs, 0); ++ ++ /* If an expression is computed in BB and is available at end of ++ BB, hoist all occurences dominated by BB to BB. */ ++ if (TEST_BIT (comp[bb->index], i)) ++ { ++ occr = find_occr_in_bb (expr->antic_occr, bb); ++ ++ if (occr) ++ { ++ /* An occurence might've been already deleted ++ while processing a dominator of BB. */ ++ if (occr->deleted_p) ++ gcc_assert (MAX_HOIST_DEPTH > 1); ++ else ++ { ++ gcc_assert (NONDEBUG_INSN_P (occr->insn)); ++ hoistable++; ++ } ++ } ++ else ++ hoistable++; ++ } ++ + /* We've found a potentially hoistable expression, now + we look at every block BB dominates to see if it + computes the expression. */ + for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++) + { ++ int max_distance; ++ + /* Ignore self dominance. */ + if (bb == dominated) + continue; +@@ -4307,17 +4477,43 @@ + if (!TEST_BIT (antloc[dominated->index], i)) + continue; + ++ occr = find_occr_in_bb (expr->antic_occr, dominated); ++ gcc_assert (occr); ++ ++ /* An occurence might've been already deleted ++ while processing a dominator of BB. */ ++ if (occr->deleted_p) ++ { ++ gcc_assert (MAX_HOIST_DEPTH > 1); ++ continue; ++ } ++ gcc_assert (NONDEBUG_INSN_P (occr->insn)); ++ ++ max_distance = expr->max_distance; ++ if (max_distance > 0) ++ /* Adjust MAX_DISTANCE to account for the fact that ++ OCCR won't have to travel all of DOMINATED, but ++ only part of it. */ ++ max_distance += (bb_size[dominated->index] ++ - to_bb_head[INSN_UID (occr->insn)]); ++ + /* Note if the expression would reach the dominated block + unimpared if it was placed at the end of BB. + + Keep track of how many times this expression is hoistable + from a dominated block into BB. */ +- if (hoist_expr_reaches_here_p (bb, i, dominated, NULL)) +- hoistable++; ++ if (hoist_expr_reaches_here_p (bb, i, dominated, NULL, ++ max_distance, bb_size)) ++ { ++ hoistable++; ++ VEC_safe_push (occr_t, heap, ++ occrs_to_hoist, occr); ++ bitmap_set_bit (from_bbs, dominated->index); ++ } + } + + /* If we found more than one hoistable occurrence of this +- expression, then note it in the bitmap of expressions to ++ expression, then note it in the vector of expressions to + hoist. It makes no sense to hoist things which are computed + in only one BB, and doing so tends to pessimize register + allocation. One could increase this value to try harder +@@ -4326,91 +4522,80 @@ + the vast majority of hoistable expressions are only movable + from two successors, so raising this threshold is likely + to nullify any benefit we get from code hoisting. */ +- if (hoistable > 1) +- { +- SET_BIT (hoist_exprs[bb->index], i); +- found = 1; +- } +- } +- } +- /* If we found nothing to hoist, then quit now. */ +- if (! found) +- { +- VEC_free (basic_block, heap, domby); +- continue; +- } +- +- /* Loop over all the hoistable expressions. */ +- for (i = 0; i < hoist_exprs[bb->index]->n_bits; i++) +- { +- /* We want to insert the expression into BB only once, so +- note when we've inserted it. */ +- insn_inserted_p = 0; +- +- /* These tests should be the same as the tests above. */ +- if (TEST_BIT (hoist_exprs[bb->index], i)) +- { +- /* We've found a potentially hoistable expression, now +- we look at every block BB dominates to see if it +- computes the expression. */ +- for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++) +- { +- /* Ignore self dominance. */ +- if (bb == dominated) +- continue; +- +- /* We've found a dominated block, now see if it computes +- the busy expression and whether or not moving that +- expression to the "beginning" of that block is safe. */ +- if (!TEST_BIT (antloc[dominated->index], i)) +- continue; +- +- /* The expression is computed in the dominated block and +- it would be safe to compute it at the start of the +- dominated block. Now we have to determine if the +- expression would reach the dominated block if it was +- placed at the end of BB. */ +- if (hoist_expr_reaches_here_p (bb, i, dominated, NULL)) +- { +- struct expr *expr = index_map[i]; +- struct occr *occr = expr->antic_occr; +- rtx insn; +- rtx set; +- +- /* Find the right occurrence of this expression. */ +- while (BLOCK_FOR_INSN (occr->insn) != dominated && occr) +- occr = occr->next; +- +- gcc_assert (occr); +- insn = occr->insn; +- set = single_set (insn); +- gcc_assert (set); +- +- /* Create a pseudo-reg to store the result of reaching +- expressions into. Get the mode for the new pseudo +- from the mode of the original destination pseudo. */ +- if (expr->reaching_reg == NULL) +- expr->reaching_reg +- = gen_reg_rtx_and_attrs (SET_DEST (set)); +- +- gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn); +- delete_insn (insn); +- occr->deleted_p = 1; +- changed = 1; +- gcse_subst_count++; +- +- if (!insn_inserted_p) +- { +- insert_insn_end_basic_block (index_map[i], bb, 0); +- insn_inserted_p = 1; +- } +- } +- } ++ if (hoistable > 1 && dbg_cnt (hoist_insn)) ++ { ++ /* If (hoistable != VEC_length), then there is ++ an occurence of EXPR in BB itself. Don't waste ++ time looking for LCA in this case. */ ++ if ((unsigned) hoistable ++ == VEC_length (occr_t, occrs_to_hoist)) ++ { ++ basic_block lca; ++ ++ lca = nearest_common_dominator_for_set (CDI_DOMINATORS, ++ from_bbs); ++ if (lca != bb) ++ /* Punt, it's better to hoist these occurences to ++ LCA. */ ++ VEC_free (occr_t, heap, occrs_to_hoist); ++ } ++ } ++ else ++ /* Punt, no point hoisting a single occurence. */ ++ VEC_free (occr_t, heap, occrs_to_hoist); ++ ++ insn_inserted_p = 0; ++ ++ /* Walk through occurences of I'th expressions we want ++ to hoist to BB and make the transformations. */ ++ for (j = 0; ++ VEC_iterate (occr_t, occrs_to_hoist, j, occr); ++ j++) ++ { ++ rtx insn; ++ rtx set; ++ ++ gcc_assert (!occr->deleted_p); ++ ++ insn = occr->insn; ++ set = single_set (insn); ++ gcc_assert (set); ++ ++ /* Create a pseudo-reg to store the result of reaching ++ expressions into. Get the mode for the new pseudo ++ from the mode of the original destination pseudo. ++ ++ It is important to use new pseudos whenever we ++ emit a set. This will allow reload to use ++ rematerialization for such registers. */ ++ if (!insn_inserted_p) ++ expr->reaching_reg ++ = gen_reg_rtx_and_attrs (SET_DEST (set)); ++ ++ gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), ++ insn); ++ delete_insn (insn); ++ occr->deleted_p = 1; ++ changed = 1; ++ gcse_subst_count++; ++ ++ if (!insn_inserted_p) ++ { ++ insert_insn_end_basic_block (expr, bb); ++ insn_inserted_p = 1; ++ } ++ } ++ ++ VEC_free (occr_t, heap, occrs_to_hoist); ++ bitmap_clear (from_bbs); + } + } + VEC_free (basic_block, heap, domby); + } + ++ VEC_free (basic_block, heap, dom_tree_walk); ++ free (bb_size); ++ free (to_bb_head); + free (index_map); + + return changed; +@@ -4433,6 +4618,8 @@ + || is_too_expensive (_("GCSE disabled"))) + return 0; + ++ doing_code_hoisting_p = true; ++ + /* We need alias. */ + init_alias_analysis (); + +@@ -4468,6 +4655,8 @@ + gcse_subst_count, gcse_create_count); + } + ++ doing_code_hoisting_p = false; ++ + return changed; + } + + +=== modified file 'gcc/params.def' +--- old/gcc/params.def 2010-04-02 18:54:46 +0000 ++++ new/gcc/params.def 2010-08-16 09:41:58 +0000 +@@ -219,6 +219,29 @@ + "gcse-after-reload-critical-fraction", + "The threshold ratio of critical edges execution count that permit performing redundancy elimination after reload", + 10, 0, 0) ++ ++/* GCSE will use GCSE_COST_DISTANCE_RATION as a scaling factor ++ to calculate maximum distance for which an expression is allowed to move ++ from its rtx_cost. */ ++DEFPARAM(PARAM_GCSE_COST_DISTANCE_RATIO, ++ "gcse-cost-distance-ratio", ++ "Scaling factor in calculation of maximum distance an expression can be moved by GCSE optimizations", ++ 10, 0, 0) ++/* GCSE won't restrict distance for which an expression with rtx_cost greater ++ than COSTS_N_INSN(GCSE_UNRESTRICTED_COST) is allowed to move. */ ++DEFPARAM(PARAM_GCSE_UNRESTRICTED_COST, ++ "gcse-unrestricted-cost", ++ "Cost at which GCSE optimizations will not constraint the distance an expression can travel", ++ 3, 0, 0) ++ ++/* How deep from a given basic block the dominator tree should be searched ++ for expressions to hoist to the block. The value of 0 will avoid limiting ++ the search. */ ++DEFPARAM(PARAM_MAX_HOIST_DEPTH, ++ "max-hoist-depth", ++ "Maximum depth of search in the dominator tree for expressions to hoist", ++ 30, 0, 0) ++ + /* This parameter limits the number of insns in a loop that will be unrolled, + and by how much the loop is unrolled. + + +=== modified file 'gcc/params.h' +--- old/gcc/params.h 2009-12-01 19:12:29 +0000 ++++ new/gcc/params.h 2010-08-16 09:41:58 +0000 +@@ -125,6 +125,12 @@ + PARAM_VALUE (PARAM_GCSE_AFTER_RELOAD_PARTIAL_FRACTION) + #define GCSE_AFTER_RELOAD_CRITICAL_FRACTION \ + PARAM_VALUE (PARAM_GCSE_AFTER_RELOAD_CRITICAL_FRACTION) ++#define GCSE_COST_DISTANCE_RATIO \ ++ PARAM_VALUE (PARAM_GCSE_COST_DISTANCE_RATIO) ++#define GCSE_UNRESTRICTED_COST \ ++ PARAM_VALUE (PARAM_GCSE_UNRESTRICTED_COST) ++#define MAX_HOIST_DEPTH \ ++ PARAM_VALUE (PARAM_MAX_HOIST_DEPTH) + #define MAX_UNROLLED_INSNS \ + PARAM_VALUE (PARAM_MAX_UNROLLED_INSNS) + #define MAX_SMS_LOOP_NUMBER \ + +=== added file 'gcc/testsuite/gcc.dg/pr45101.c' +--- old/gcc/testsuite/gcc.dg/pr45101.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/pr45101.c 2010-08-16 09:41:58 +0000 +@@ -0,0 +1,15 @@ ++/* PR rtl-optimization/45101 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fgcse -fgcse-las" } */ ++ ++struct ++{ ++ int i; ++} *s; ++ ++extern void bar (void); ++ ++void foo () ++{ ++ !s ? s->i++ : bar (); ++} + +=== added file 'gcc/testsuite/gcc.dg/pr45105.c' +--- old/gcc/testsuite/gcc.dg/pr45105.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/pr45105.c 2010-08-16 09:41:58 +0000 +@@ -0,0 +1,27 @@ ++/* PR debug/45105 */ ++/* { dg-do compile } */ ++/* { dg-options "-Os -fcompare-debug" } */ ++ ++extern int *baz (int *, int *); ++ ++void ++bar (int *p1, int *p2) ++{ ++ int n = *baz (0, 0); ++ p1[n] = p2[n]; ++} ++ ++void ++foo (int *p, int l) ++{ ++ int a1[32]; ++ int a2[32]; ++ baz (a1, a2); ++ while (l) ++ { ++ if (l & 1) ++ p = baz (a2, p); ++ l--; ++ bar (a1, a2); ++ } ++} + +=== added file 'gcc/testsuite/gcc.dg/pr45107.c' +--- old/gcc/testsuite/gcc.dg/pr45107.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/pr45107.c 2010-08-16 09:41:58 +0000 +@@ -0,0 +1,13 @@ ++/* PR rtl-optimization/45107 */ ++/* { dg-do compile } */ ++/* { dg-options "-Os -fgcse-las" } */ ++ ++extern void bar(int *); ++ ++int foo (int *p) ++{ ++ int i = *p; ++ if (i != 1) ++ bar(&i); ++ *p = i; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/pr40956.c' +--- old/gcc/testsuite/gcc.target/arm/pr40956.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr40956.c 2010-08-16 09:41:58 +0000 +@@ -0,0 +1,14 @@ ++/* { dg-options "-mthumb -Os -fpic -march=armv5te" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-require-effective-target fpic } */ ++/* Make sure the constant "0" is loaded into register only once. */ ++/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */ ++ ++int foo(int p, int* q) ++{ ++ if (p!=9) ++ *q = 0; ++ else ++ *(q+1) = 0; ++ return 3; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/pr42495.c' +--- old/gcc/testsuite/gcc.target/arm/pr42495.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr42495.c 2010-08-16 09:41:58 +0000 +@@ -0,0 +1,31 @@ ++/* { dg-options "-mthumb -Os -fpic -march=armv5te -fdump-rtl-hoist" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-require-effective-target fpic } */ ++/* Make sure all calculations of gObj's address get hoisted to one location. */ ++/* { dg-final { scan-rtl-dump "PRE/HOIST: end of bb .* copying expression" "hoist" } } */ ++ ++struct st_a { ++ int data; ++}; ++ ++struct st_b { ++ struct st_a *p_a; ++ struct st_b *next; ++}; ++ ++extern struct st_b gObj; ++extern void foo(int, struct st_b*); ++ ++int goo(struct st_b * obj) { ++ struct st_a *pa; ++ if (gObj.p_a->data != 0) { ++ foo(gObj.p_a->data, obj); ++ } ++ pa = obj->p_a; ++ if (pa == 0) { ++ return 0; ++ } else if (pa == gObj.p_a) { ++ return 0; ++ } ++ return pa->data; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/pr42574.c' +--- old/gcc/testsuite/gcc.target/arm/pr42574.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr42574.c 2010-08-16 09:41:58 +0000 +@@ -0,0 +1,24 @@ ++/* { dg-options "-mthumb -Os -fpic -march=armv5te" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-require-effective-target fpic } */ ++/* Make sure the address of glob.c is calculated only once and using ++ a logical shift for the offset (200<<1). */ ++/* { dg-final { scan-assembler-times "lsl" 1 } } */ ++ ++struct A { ++ char a[400]; ++ float* c; ++}; ++struct A glob; ++void func(); ++void func1(float*); ++int func2(float*, int*); ++void func3(float*); ++ ++void test(int *p) { ++ func1(glob.c); ++ if (func2(glob.c, p)) { ++ func(); ++ } ++ func3(glob.c); ++} + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch new file mode 100644 index 0000000000..db9e63917d --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch @@ -0,0 +1,17586 @@ +2010-08-04 Julian Brown + + gcc/ + * config/arm/neon-testgen.ml (regexps): Allow any characters + in comments after assembly instructions. + + gcc/testsuite/ + * gcc.target/arm/neon/vfp-shift-a2t2.c: Allow any characters in + comments after assembly instructions. + * gcc.target/arm/neon/v*.c: Regenerate. + + 2010-07-28 Maxim Kuvyrkov + + Backport code hoisting improvements from mainline: + +=== modified file 'gcc/config/arm/neon-testgen.ml' +--- old/gcc/config/arm/neon-testgen.ml 2010-07-29 15:38:15 +0000 ++++ new/gcc/config/arm/neon-testgen.ml 2010-08-20 13:27:11 +0000 +@@ -257,7 +257,7 @@ + intrinsic expands to. Watch out for any writeback character and + comments after the instruction. *) + let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^ +- "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n") ++ "!?\\(\\[ \t\\]+@.*\\)?\\n") + (analyze_all_shapes features shape analyze_shape) + in + (* Emit file and function prologues. *) + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshls64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); + } + +-/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); + } + +-/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); + } + +-/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabals16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabals16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabals32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabals32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabals8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabals8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabalu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabalu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabalu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabas16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabas16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabas32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabas32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabas8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabas8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabau16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabau16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabau32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabau32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabau8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabau8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabds16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabds16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabds32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabds32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabds8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabds8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabdu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vabsq_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vabsq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vabsq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vabsq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabsf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabsf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vabs_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabss16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabss16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vabs_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabss32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabss32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vabs_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vabss8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vabss8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vabs_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vadds16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vadds16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vadds32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vadds32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vadds8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vadds8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddws16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddws32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddws8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vands16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vands16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vands32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vands32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vands8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vands8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vandu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vandu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbics16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbics16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbics32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbics32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbics8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbics8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbicu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslp16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslp8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbsls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbsls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbsls64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls64.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbsls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu64.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vbslu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcageQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcagef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcagef32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagtf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcalef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcalef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcalef32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaltf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vceqs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcequ16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcequ32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcequ8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgef32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcges16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcges16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcges32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcges32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcges8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcges8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgts16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgts32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgts8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclef32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcles16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcles16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcles32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcles32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcles8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcles8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcleu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vclsq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vclsq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vclsq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclss16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclss16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vcls_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclss32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclss32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vcls_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclss8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclss8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vcls_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclts16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclts16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclts32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclts32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclts8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclts8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcltu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vclzq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vclzq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vclzq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vclz_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vclz_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vclz_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vclz_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vclz_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vclzu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vclz_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vcntq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcnts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcnts8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcnts8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vcnt_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcntu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcntu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vdupq_n_f32 (arg0_float32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vdupq_n_s16 (arg0_int16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vdupq_n_s32 (arg0_int32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vdupq_n_s8 (arg0_int8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vdup_n_f32 (arg0_float32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4_t = vdup_n_p16 (arg0_poly16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vdup_n_p8 (arg0_poly8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vdup_n_s16 (arg0_int16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vdup_n_s32 (arg0_int32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vdup_n_s8 (arg0_int8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vdup_n_u16 (arg0_uint16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vdup_n_u32 (arg0_uint32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vdup_n_u8 (arg0_uint8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veorQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veors16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veors16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veors32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veors32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veors8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veors8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veoru16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veoru16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veoru32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veoru32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/veoru8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/veoru8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQp16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextp16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vexts16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vexts16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vexts32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vexts32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vexts64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vexts64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vexts8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vexts8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vextu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vextu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c 2010-08-20 13:27:11 +0000 +@@ -22,7 +22,7 @@ + return vshll_n_u32(a, 32); + } + +-/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vget_low_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vget_low_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vget_low_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vget_low_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhadds16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhadds32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhadds8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x4_t = vld1q_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x8_t = vld1q_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x16_t = vld1q_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x8_t = vld1q_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x4_t = vld1q_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x2_t = vld1q_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x16_t = vld1q_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x8_t = vld1q_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x4_t = vld1q_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x2_t = vld1q_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x16_t = vld1q_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x4_t = vld1q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x8_t = vld1q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x16_t = vld1q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x8_t = vld1q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x4_t = vld1q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x2_t = vld1q_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x16_t = vld1q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x8_t = vld1q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x4_t = vld1q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x2_t = vld1q_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x16_t = vld1q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x2_t = vld1_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4_t = vld1_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8_t = vld1_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x4_t = vld1_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x2_t = vld1_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x1_t = vld1_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x8_t = vld1_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4_t = vld1_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2_t = vld1_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1_t = vld1_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8_t = vld1_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x2_t = vld1_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4_t = vld1_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8_t = vld1_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x4_t = vld1_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x2_t = vld1_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x1_t = vld1_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x8_t = vld1_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4_t = vld1_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2_t = vld1_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1_t = vld1_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8_t = vld1_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_float32x4x2_t = vld2q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_poly16x8x2_t = vld2q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_poly8x16x2_t = vld2q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int16x8x2_t = vld2q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int32x4x2_t = vld2q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int8x16x2_t = vld2q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint16x8x2_t = vld2q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint32x4x2_t = vld2q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint8x16x2_t = vld2q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x2_t = vld2_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x2_t = vld2_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x2_t = vld2_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x2_t = vld2_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x2_t = vld2_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x2_t = vld2_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x2_t = vld2_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x2_t = vld2_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x2_t = vld2_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x2_t = vld2_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x2_t = vld2_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x2_t = vld2_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x2_t = vld2_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x2_t = vld2_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x2_t = vld2_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x2_t = vld2_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x2_t = vld2_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x2_t = vld2_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x2_t = vld2_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x2_t = vld2_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x2_t = vld2_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x2_t = vld2_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_float32x4x3_t = vld3q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_poly16x8x3_t = vld3q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_poly8x16x3_t = vld3q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int16x8x3_t = vld3q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int32x4x3_t = vld3q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int8x16x3_t = vld3q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint16x8x3_t = vld3q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint32x4x3_t = vld3q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint8x16x3_t = vld3q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x3_t = vld3_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x3_t = vld3_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x3_t = vld3_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x3_t = vld3_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x3_t = vld3_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x3_t = vld3_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x3_t = vld3_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x3_t = vld3_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x3_t = vld3_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x3_t = vld3_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x3_t = vld3_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x3_t = vld3_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x3_t = vld3_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x3_t = vld3_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x3_t = vld3_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x3_t = vld3_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x3_t = vld3_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x3_t = vld3_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x3_t = vld3_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x3_t = vld3_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x3_t = vld3_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x3_t = vld3_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_float32x4x4_t = vld4q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_poly16x8x4_t = vld4q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_poly8x16x4_t = vld4q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int16x8x4_t = vld4q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int32x4x4_t = vld4q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_int8x16x4_t = vld4q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint16x8x4_t = vld4q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint32x4x4_t = vld4q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-08-20 13:27:11 +0000 +@@ -15,6 +15,6 @@ + out_uint8x16x4_t = vld4q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x4_t = vld4_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x4_t = vld4_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x4_t = vld4_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x4_t = vld4_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x4_t = vld4_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x4_t = vld4_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x4_t = vld4_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x4_t = vld4_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x4_t = vld4_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x4_t = vld4_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x4_t = vld4_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x4_t = vld4_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x4_t = vld4_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x4_t = vld4_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x4_t = vld4_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x4_t = vld4_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x4_t = vld4_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x4_t = vld4_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x4_t = vld4_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x4_t = vld4_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x4_t = vld4_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-08-20 13:27:11 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x4_t = vld4_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmins16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmins16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmins32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmins32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmins8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmins8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vminu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vminu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlals16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlals32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlals8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlas16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlas32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlas8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlau16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlau32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlau8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlss16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlss32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlss8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vmovq_n_f32 (arg0_float32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vmovq_n_s16 (arg0_int16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vmovq_n_s32 (arg0_int32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vmovq_n_s8 (arg0_int8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vmov_n_f32 (arg0_float32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4_t = vmov_n_p16 (arg0_poly16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vmov_n_p8 (arg0_poly8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vmov_n_s16 (arg0_int16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vmov_n_s32 (arg0_int32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vmov_n_s8 (arg0_int8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vmov_n_u16 (arg0_uint16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vmov_n_u32 (arg0_uint32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vmov_n_u8 (arg0_uint8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vmovl_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vmovl_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vmovl_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vmovn_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vmovn_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vmovn_s64 (arg0_int64x2_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t); + } + +-/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t); + } + +-/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmullp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmullp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmullu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmullu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmullu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmuls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmuls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmuls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmulu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vmvnq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vmvnq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vmvnq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vmvn_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vmvn_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vmvn_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vnegq_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vnegq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vnegq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vnegq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vneg_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vneg_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vneg_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vnegs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vneg_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vornu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vornu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorrs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorru16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorru16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorru32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorru32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vorru8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vorru8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadals16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadals32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadals8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vpaddl_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x1_t = vpaddl_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vpaddl_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadds16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadds32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpadds8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpminf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpminf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmins16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmins32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpmins8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpminu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpminu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vpminu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vqabsq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vqabsq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vqabsq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabss16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vqabs_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabss32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vqabs_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqabss8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vqabs_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqadds16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqadds32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqadds64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqadds8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vqmovn_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vqmovn_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vqmovn_s64 (arg0_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vqnegq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vqnegq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vqnegq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vqneg_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vqneg_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vqneg_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshls64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vrecpe_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vrev16q_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vrev16_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vrev32q_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vrev32q_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vrev32_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vrev32_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vrev64q_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vrev64q_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vrev64q_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vrev64q_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vrev64_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vrev64_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vrev64_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vrev64_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshls64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshls64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshlu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_np16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_np8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_f32 (arg0_float32_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_s16 (arg0_int16_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_s32 (arg0_int32_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_s64 (arg0_int64_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_s8 (arg0_int8_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_f32 (arg0_float32_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_s16 (arg0_int16_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_s32 (arg0_int32_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_s64 (arg0_int64_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_s8 (arg0_int8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-08-20 13:27:11 +0000 +@@ -16,6 +16,6 @@ + vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-08-20 13:27:11 +0000 +@@ -16,5 +16,5 @@ + vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubls16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubls32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubls8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsublu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsublu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsublu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubws16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubws32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubws8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c 2010-08-20 13:27:11 +0000 +@@ -18,5 +18,5 @@ + out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrns16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrns32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrns8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtsts16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtsts32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtsts8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vtstu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzps16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzps32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzps8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipf32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipf32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipp16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipp16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipp8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipp8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzips16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzips16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzips32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzips32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzips8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzips8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipu16.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu16.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipu32.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu32.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vzipu8.c 2010-07-29 15:38:15 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu8.c 2010-08-20 13:27:11 +0000 +@@ -17,5 +17,5 @@ + out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99362.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99362.patch new file mode 100644 index 0000000000..fd825a1cea --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99362.patch @@ -0,0 +1,25 @@ +2010-08-04 Mark Mitchell + + Backport from mainline: + + gcc/testsuite/ + 2010-08-04 Daniel Gutson + * g++.dg/warn/miss-format-1.C: Update line number. + + 2010-08-04 Julian Brown + + gcc/ + +=== modified file 'gcc/testsuite/g++.dg/warn/miss-format-1.C' +--- old/gcc/testsuite/g++.dg/warn/miss-format-1.C 2010-05-03 17:32:50 +0000 ++++ new/gcc/testsuite/g++.dg/warn/miss-format-1.C 2010-08-20 15:08:29 +0000 +@@ -4,7 +4,7 @@ + /* { dg-options "-Wmissing-format-attribute" } */ + /* { dg-options "-Wmissing-format-attribute -Wno-abi" { target arm_eabi } } */ + /* VxWorks does not provide vscanf, either in kernel or RTP mode. */ +-/* { dg-error "not declared" "" { target *-*-solaris2.[7-8] *-*-vxworks* } 25 } */ ++/* { dg-error "not declared" "" { target *-*-solaris2.[7-8] *-*-vxworks* } 26 } */ + + #include + #include + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch new file mode 100644 index 0000000000..7003cf8376 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch @@ -0,0 +1,95 @@ +2010-08-05 Jie Zhang + + Issue #7257 + + Backport from mainline: + + gcc/ + 2010-08-05 Jie Zhang + PR tree-optimization/45144 + * tree-sra.c (type_consists_of_records_p): Return false + if the record contains bit-field. + + gcc/testsuite/ + 2010-08-05 Jie Zhang + PR tree-optimization/45144 + * gcc.dg/tree-ssa/pr45144.c: New test. + + 2010-08-04 Mark Mitchell + + Backport from mainline: + +=== added file 'gcc/testsuite/gcc.dg/tree-ssa/pr45144.c' +--- old/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c 2010-08-20 16:04:44 +0000 +@@ -0,0 +1,46 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++void baz (unsigned); ++ ++extern unsigned buf[]; ++ ++struct A ++{ ++ unsigned a1:10; ++ unsigned a2:3; ++ unsigned:19; ++}; ++ ++union TMP ++{ ++ struct A a; ++ unsigned int b; ++}; ++ ++static unsigned ++foo (struct A *p) ++{ ++ union TMP t; ++ struct A x; ++ ++ x = *p; ++ t.a = x; ++ return t.b; ++} ++ ++void ++bar (unsigned orig, unsigned *new) ++{ ++ struct A a; ++ union TMP s; ++ ++ s.b = orig; ++ a = s.a; ++ if (a.a1) ++ baz (a.a2); ++ *new = foo (&a); ++} ++ ++/* { dg-final { scan-tree-dump "x = a;" "optimized"} } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ + +=== modified file 'gcc/tree-sra.c' +--- old/gcc/tree-sra.c 2010-08-10 13:31:21 +0000 ++++ new/gcc/tree-sra.c 2010-08-20 16:04:44 +0000 +@@ -805,7 +805,7 @@ + /* Return true iff TYPE is a RECORD_TYPE with fields that are either of gimple + register types or (recursively) records with only these two kinds of fields. + It also returns false if any of these records has a zero-size field as its +- last field. */ ++ last field or has a bit-field. */ + + static bool + type_consists_of_records_p (tree type) +@@ -821,6 +821,9 @@ + { + tree ft = TREE_TYPE (fld); + ++ if (DECL_BIT_FIELD (fld)) ++ return false; ++ + if (!is_gimple_reg_type (ft) + && !type_consists_of_records_p (ft)) + return false; + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch new file mode 100644 index 0000000000..8ae781ecab --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch @@ -0,0 +1,511 @@ +2010-08-05 Julian Brown + + Backport from mainline (candidate patch): + + gcc/ + * expr.c (expand_assignment): Add assertion to prevent emitting null + rtx for movmisalign pattern. + (expand_expr_real_1): Likewise. + * config/arm/arm.c (arm_builtin_support_vector_misalignment): New. + (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): New. Use above. + (arm_vector_alignment_reachable): New. + (TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE): New. Use above. + (neon_vector_mem_operand): Disallow PRE_DEC for misaligned loads. + (arm_print_operand): Include alignment qualifier in %A. + * config/arm/neon.md (UNSPEC_MISALIGNED_ACCESS): New constant. + (movmisalign): New expander. + (movmisalign_neon_store, movmisalign_neon_load): New + insn patterns. + + gcc/testsuite/ + * gcc.dg/vect/vect-42.c: Use vect_element_align instead of + vect_hw_misalign. + * gcc.dg/vect/vect-60.c: Likewise. + * gcc.dg/vect/vect-56.c: Likewise. + * gcc.dg/vect/vect-93.c: Likewise. + * gcc.dg/vect/no-scevccp-outer-8.c: Likewise. + * gcc.dg/vect/vect-95.c: Likewise. + * gcc.dg/vect/vect-96.c: Likewise. + * gcc.dg/vect/vect-outer-5.c: Use quad-word vectors when available. + * gcc.dg/vect/slp-25.c: Likewise. + * gcc.dg/vect/slp-3.c: Likewise. + * gcc.dg/vect/vect-multitypes-1.c: Likewise. + * gcc.dg/vect/no-vfa-pr29145.c: Likewise. + * gcc.dg/vect/vect-multitypes-4.c: Likewise. Use vect_element_align. + * gcc.dg/vect/vect-109.c: Likewise. + * gcc.dg/vect/vect-peel-1.c: Likewise. + * gcc.dg/vect/vect-peel-2.c: Likewise. + * lib/target-supports.exp + (check_effective_target_arm_vect_no_misalign): New. + (check_effective_target_vect_no_align): Use above. + (check_effective_target_vect_element_align): New. + (add_options_for_quad_vectors): New. + + 2010-08-05 Jie Zhang + + Issue #7257 + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-16 09:41:58 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-20 16:21:01 +0000 +@@ -228,6 +228,11 @@ + static void arm_trampoline_init (rtx, tree, rtx); + static rtx arm_trampoline_adjust_address (rtx); + static rtx arm_pic_static_addr (rtx orig, rtx reg); ++static bool arm_vector_alignment_reachable (const_tree type, bool is_packed); ++static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, ++ const_tree type, ++ int misalignment, ++ bool is_packed); + + + /* Table of machine attributes. */ +@@ -514,6 +519,14 @@ + #undef TARGET_CAN_ELIMINATE + #define TARGET_CAN_ELIMINATE arm_can_eliminate + ++#undef TARGET_VECTOR_ALIGNMENT_REACHABLE ++#define TARGET_VECTOR_ALIGNMENT_REACHABLE \ ++ arm_vector_alignment_reachable ++ ++#undef TARGET_SUPPORT_VECTOR_MISALIGNMENT ++#define TARGET_SUPPORT_VECTOR_MISALIGNMENT \ ++ arm_builtin_support_vector_misalignment ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + /* Obstack for minipool constant handling. */ +@@ -9084,7 +9097,8 @@ + return arm_address_register_rtx_p (ind, 0); + + /* Allow post-increment with Neon registers. */ +- if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC)) ++ if ((type != 1 && GET_CODE (ind) == POST_INC) ++ || (type == 0 && GET_CODE (ind) == PRE_DEC)) + return arm_address_register_rtx_p (XEXP (ind, 0), 0); + + /* FIXME: vld1 allows register post-modify. */ +@@ -16365,6 +16379,8 @@ + { + rtx addr; + bool postinc = FALSE; ++ unsigned align, modesize, align_bits; ++ + gcc_assert (GET_CODE (x) == MEM); + addr = XEXP (x, 0); + if (GET_CODE (addr) == POST_INC) +@@ -16372,7 +16388,29 @@ + postinc = 1; + addr = XEXP (addr, 0); + } +- asm_fprintf (stream, "[%r]", REGNO (addr)); ++ asm_fprintf (stream, "[%r", REGNO (addr)); ++ ++ /* We know the alignment of this access, so we can emit a hint in the ++ instruction (for some alignments) as an aid to the memory subsystem ++ of the target. */ ++ align = MEM_ALIGN (x) >> 3; ++ modesize = GET_MODE_SIZE (GET_MODE (x)); ++ ++ /* Only certain alignment specifiers are supported by the hardware. */ ++ if (modesize == 16 && (align % 32) == 0) ++ align_bits = 256; ++ else if ((modesize == 8 || modesize == 16) && (align % 16) == 0) ++ align_bits = 128; ++ else if ((align % 8) == 0) ++ align_bits = 64; ++ else ++ align_bits = 0; ++ ++ if (align_bits != 0) ++ asm_fprintf (stream, ", :%d", align_bits); ++ ++ asm_fprintf (stream, "]"); ++ + if (postinc) + fputs("!", stream); + } +@@ -22450,4 +22488,43 @@ + return !TARGET_THUMB1; + } + ++static bool ++arm_vector_alignment_reachable (const_tree type, bool is_packed) ++{ ++ /* Vectors which aren't in packed structures will not be less aligned than ++ the natural alignment of their element type, so this is safe. */ ++ if (TARGET_NEON && !BYTES_BIG_ENDIAN) ++ return !is_packed; ++ ++ return default_builtin_vector_alignment_reachable (type, is_packed); ++} ++ ++static bool ++arm_builtin_support_vector_misalignment (enum machine_mode mode, ++ const_tree type, int misalignment, ++ bool is_packed) ++{ ++ if (TARGET_NEON && !BYTES_BIG_ENDIAN) ++ { ++ HOST_WIDE_INT align = TYPE_ALIGN_UNIT (type); ++ ++ if (is_packed) ++ return align == 1; ++ ++ /* If the misalignment is unknown, we should be able to handle the access ++ so long as it is not to a member of a packed data structure. */ ++ if (misalignment == -1) ++ return true; ++ ++ /* Return true if the misalignment is a multiple of the natural alignment ++ of the vector's element type. This is probably always going to be ++ true in practice, since we've already established that this isn't a ++ packed access. */ ++ return ((misalignment % align) == 0); ++ } ++ ++ return default_builtin_support_vector_misalignment (mode, type, misalignment, ++ is_packed); ++} ++ + #include "gt-arm.h" + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2010-08-13 11:40:17 +0000 ++++ new/gcc/config/arm/neon.md 2010-08-20 16:21:01 +0000 +@@ -140,7 +140,8 @@ + (UNSPEC_VUZP1 201) + (UNSPEC_VUZP2 202) + (UNSPEC_VZIP1 203) +- (UNSPEC_VZIP2 204)]) ++ (UNSPEC_VZIP2 204) ++ (UNSPEC_MISALIGNED_ACCESS 205)]) + + ;; Double-width vector modes. + (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) +@@ -660,6 +661,52 @@ + neon_disambiguate_copy (operands, dest, src, 4); + }) + ++(define_expand "movmisalign" ++ [(set (match_operand:VDQX 0 "nonimmediate_operand" "") ++ (unspec:VDQX [(match_operand:VDQX 1 "general_operand" "")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++{ ++ /* This pattern is not permitted to fail during expansion: if both arguments ++ are non-registers (e.g. memory := constant, which can be created by the ++ auto-vectorizer), force operand 1 into a register. */ ++ if (!s_register_operand (operands[0], mode) ++ && !s_register_operand (operands[1], mode)) ++ operands[1] = force_reg (mode, operands[1]); ++}) ++ ++(define_insn "*movmisalign_neon_store" ++ [(set (match_operand:VDX 0 "memory_operand" "=Um") ++ (unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++ "vst1.\t{%P1}, %A0" ++ [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) ++ ++(define_insn "*movmisalign_neon_load" ++ [(set (match_operand:VDX 0 "s_register_operand" "=w") ++ (unspec:VDX [(match_operand:VDX 1 "memory_operand" " Um")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++ "vld1.\t{%P0}, %A1" ++ [(set_attr "neon_type" "neon_vld1_1_2_regs")]) ++ ++(define_insn "*movmisalign_neon_store" ++ [(set (match_operand:VQX 0 "memory_operand" "=Um") ++ (unspec:VQX [(match_operand:VQX 1 "s_register_operand" " w")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++ "vst1.\t{%q1}, %A0" ++ [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) ++ ++(define_insn "*movmisalign_neon_load" ++ [(set (match_operand:VQX 0 "s_register_operand" "=w") ++ (unspec:VQX [(match_operand:VQX 1 "memory_operand" " Um")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++ "vld1.\t{%q0}, %A1" ++ [(set_attr "neon_type" "neon_vld1_1_2_regs")]) ++ + (define_insn "vec_set_internal" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (vec_merge:VD + +=== modified file 'gcc/expr.c' +--- old/gcc/expr.c 2010-08-12 13:51:16 +0000 ++++ new/gcc/expr.c 2010-08-20 16:21:01 +0000 +@@ -4362,7 +4362,10 @@ + && op_mode1 != VOIDmode) + reg = copy_to_mode_reg (op_mode1, reg); + +- insn = GEN_FCN (icode) (mem, reg); ++ insn = GEN_FCN (icode) (mem, reg); ++ /* The movmisalign pattern cannot fail, else the assignment would ++ silently be omitted. */ ++ gcc_assert (insn != NULL_RTX); + emit_insn (insn); + return; + } +@@ -8742,6 +8745,7 @@ + + /* Nor can the insn generator. */ + insn = GEN_FCN (icode) (reg, temp); ++ gcc_assert (insn != NULL_RTX); + emit_insn (insn); + + return reg; + +=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c' +--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c 2009-06-05 14:28:50 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c 2010-08-20 16:21:01 +0000 +@@ -46,5 +46,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { vect_hw_misalign } } } } } */ ++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { vect_element_align } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c' +--- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2008-08-18 19:36:03 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2010-08-20 16:21:01 +0000 +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-25.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-25.c 2009-10-27 11:46:07 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-25.c 2010-08-20 16:21:01 +0000 +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-3.c 2009-05-12 13:05:28 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-3.c 2010-08-20 16:21:01 +0000 +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-109.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-109.c 2010-07-10 20:38:32 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-109.c 2010-08-20 16:21:01 +0000 +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" +@@ -72,8 +73,8 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_hw_misalign } } } */ +-/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { xfail vect_hw_misalign } } } */ +-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 10 "vect" { target vect_hw_misalign } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_element_align } } } */ ++/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { xfail vect_element_align } } } */ ++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 10 "vect" { target vect_element_align } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-42.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-42.c 2009-11-04 10:22:22 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-42.c 2010-08-20 16:21:01 +0000 +@@ -64,7 +64,7 @@ + + /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ + /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 3 "vect" { target vect_no_align } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_hw_misalign } } } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_element_align } } } } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */ + /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-95.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-95.c 2009-10-27 11:46:07 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-95.c 2010-08-20 16:21:01 +0000 +@@ -56,14 +56,14 @@ + } + + /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { xfail {vect_hw_misalign} } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { xfail {vect_element_align} } } } */ + + /* For targets that support unaligned loads we version for the two unaligned + stores and generate misaligned accesses for the loads. For targets that + don't support unaligned loads we version for all four accesses. */ + +-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target vect_no_align } } } */ + /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 4 "vect" { target vect_no_align } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-96.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-96.c 2009-10-27 11:46:07 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-96.c 2010-08-20 16:21:01 +0000 +@@ -45,5 +45,5 @@ + /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { target { {! vect_no_align} && vector_alignment_reachable } } } } */ + /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { { vect_no_align } || {! vector_alignment_reachable} } } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { vect_no_align || { {! vector_alignment_reachable} && {! vect_hw_misalign} } } } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { vect_no_align || { {! vector_alignment_reachable} && {! vect_element_align} } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c 2009-10-27 11:46:07 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c 2010-08-20 16:21:01 +0000 +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" +@@ -78,11 +79,11 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail *-*-* } } } */ +-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c 2009-10-27 11:46:07 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c 2010-08-20 16:21:01 +0000 +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" +@@ -85,11 +86,11 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 8 "vect" { xfail *-*-* } } } */ +-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2009-05-08 12:39:01 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2010-08-20 16:21:01 +0000 +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_float } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include + +=== modified file 'gcc/testsuite/lib/target-supports.exp' +--- old/gcc/testsuite/lib/target-supports.exp 2010-08-10 13:31:21 +0000 ++++ new/gcc/testsuite/lib/target-supports.exp 2010-08-20 16:21:01 +0000 +@@ -1642,6 +1642,18 @@ + }] + } + ++# Return 1 if this is an ARM target that only supports aligned vector accesses ++proc check_effective_target_arm_vect_no_misalign { } { ++ return [check_no_compiler_messages arm_vect_no_misalign assembly { ++ #if !defined(__arm__) \ ++ || (defined(__ARMEL__) \ ++ && (!defined(__thumb__) || defined(__thumb2__))) ++ #error FOO ++ #endif ++ }] ++} ++ ++ + # Return 1 if this is an ARM target supporting -mfpu=vfp + # -mfloat-abi=softfp. Some multilibs may be incompatible with these + # options. +@@ -2547,7 +2559,7 @@ + if { [istarget mipsisa64*-*-*] + || [istarget sparc*-*-*] + || [istarget ia64-*-*] +- || [check_effective_target_arm32] } { ++ || [check_effective_target_arm_vect_no_misalign] } { + set et_vect_no_align_saved 1 + } + } +@@ -2682,6 +2694,25 @@ + return $et_vector_alignment_reachable_for_64bit_saved + } + ++# Return 1 if the target only requires element alignment for vector accesses ++ ++proc check_effective_target_vect_element_align { } { ++ global et_vect_element_align ++ ++ if [info exists et_vect_element_align] { ++ verbose "check_effective_target_vect_element_align: using cached result" 2 ++ } else { ++ set et_vect_element_align 0 ++ if { [istarget arm*-*-*] ++ || [check_effective_target_vect_hw_misalign] } { ++ set et_vect_element_align 1 ++ } ++ } ++ ++ verbose "check_effective_target_vect_element_align: returning $et_vect_element_align" 2 ++ return $et_vect_element_align ++} ++ + # Return 1 if the target supports vector conditional operations, 0 otherwise. + + proc check_effective_target_vect_condition { } { +@@ -3239,6 +3270,16 @@ + return $flags + } + ++# Add to FLAGS the flags needed to enable 128-bit vectors. ++ ++proc add_options_for_quad_vectors { flags } { ++ if [is-effective-target arm_neon_ok] { ++ return "$flags -mvectorize-with-neon-quad" ++ } ++ ++ return $flags ++} ++ + # Return 1 if the target provides a full C99 runtime. + + proc check_effective_target_c99_runtime { } { + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch new file mode 100644 index 0000000000..36a942118a --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch @@ -0,0 +1,38 @@ +2010-08-12 Jie Zhang + + Backport from mainline: + + gcc/testsuite/ + 2010-08-12 Jie Zhang + * gcc.dg/graphite/interchange-9.c (M): Define to be 111. + (N): Likewise. + (main): Adjust accordingly. + + 2010-08-05 Julian Brown + + Backport from mainline (candidate patch): + +=== modified file 'gcc/testsuite/gcc.dg/graphite/interchange-9.c' +--- old/gcc/testsuite/gcc.dg/graphite/interchange-9.c 2010-02-07 19:49:26 +0000 ++++ new/gcc/testsuite/gcc.dg/graphite/interchange-9.c 2010-08-20 16:32:45 +0000 +@@ -5,8 +5,8 @@ + #include + #endif + +-#define N 1111 +-#define M 1111 ++#define N 111 ++#define M 111 + + static int __attribute__((noinline)) + foo (int *x) +@@ -38,7 +38,7 @@ + fprintf (stderr, "res = %d \n", res); + #endif + +- if (res != 2468642) ++ if (res != 24642) + abort (); + + return 0; + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch new file mode 100644 index 0000000000..0998c812e8 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch @@ -0,0 +1,26 @@ +2010-08-13 Jie Zhang + + Backport from mainline: + + gcc/ + 2010-08-13 Jie Zhang + * config/arm/arm.md (cstoredf4): Only valid when + !TARGET_VFP_SINGLE. + + 2010-08-12 Jie Zhang + + Backport from mainline: + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-16 09:41:58 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-20 16:41:37 +0000 +@@ -8344,7 +8344,7 @@ + (match_operator:SI 1 "arm_comparison_operator" + [(match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_compare_operand" "")]))] +- "TARGET_32BIT && TARGET_HARD_FLOAT" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" + "emit_insn (gen_cstore_cc (operands[0], operands[1], + operands[2], operands[3])); DONE;" + ) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch new file mode 100644 index 0000000000..2d572b1bb0 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch @@ -0,0 +1,49 @@ +2010-08-18 Jie Zhang + + Backport from mainline: + + gcc/testsuite/ + 2010-08-18 Jie Zhang + * gcc.dg/builtin-apply2.c (STACK_ARGUMENTS_SIZE): Define to + 20 if __ARM_PCS is defined otherwise 64. + (bar): Use STACK_ARGUMENTS_SIZE for the third argument + instead of hard coded 64. + + 2010-08-13 Jie Zhang + + Backport from mainline: + +=== modified file 'gcc/testsuite/gcc.dg/builtin-apply2.c' +--- old/gcc/testsuite/gcc.dg/builtin-apply2.c 2009-08-06 13:27:45 +0000 ++++ new/gcc/testsuite/gcc.dg/builtin-apply2.c 2010-08-23 13:59:02 +0000 +@@ -8,10 +8,19 @@ + /* Verify that __builtin_apply behaves correctly on targets + with pre-pushed arguments (e.g. SPARC). */ + +- ++ + + #define INTEGER_ARG 5 + ++#ifdef __ARM_PCS ++/* For Base AAPCS, NAME is passed in r0. D is passed in r2 and r3. ++ E, F and G are passed on stack. So the size of the stack argument ++ data is 20. */ ++#define STACK_ARGUMENTS_SIZE 20 ++#else ++#define STACK_ARGUMENTS_SIZE 64 ++#endif ++ + extern void abort(void); + + void foo(char *name, double d, double e, double f, int g) +@@ -22,7 +31,7 @@ + + void bar(char *name, ...) + { +- __builtin_apply(foo, __builtin_apply_args(), 64); ++ __builtin_apply(foo, __builtin_apply_args(), STACK_ARGUMENTS_SIZE); + } + + int main(void) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch new file mode 100644 index 0000000000..fa13e0e9ea --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch @@ -0,0 +1,341 @@ +2010-08-18 Julian Brown + + Issue #9222 + + gcc/ + * config/arm/neon.md (UNSPEC_VCLE, UNSPEC_VCLT): New constants for + unspecs. + (vcond, vcondu): New expanders. + (neon_vceq, neon_vcge, neon_vcgt): Support + comparisons with zero. + (neon_vcle, neon_vclt): New patterns. + * config/arm/constraints.md (Dz): New constraint. + + 2010-08-18 Jie Zhang + + Backport from mainline: + +=== modified file 'gcc/config/arm/constraints.md' +--- old/gcc/config/arm/constraints.md 2010-08-13 10:59:06 +0000 ++++ new/gcc/config/arm/constraints.md 2010-08-23 14:29:45 +0000 +@@ -29,7 +29,7 @@ + ;; in Thumb-1 state: I, J, K, L, M, N, O + + ;; The following multi-letter normal constraints have been used: +-;; in ARM/Thumb-2 state: D0, Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy ++;; in ARM/Thumb-2 state: D0, Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy, Dz + ;; in Thumb-1 state: Pa, Pb + ;; in Thumb-2 state: Ps, Pt, Pv + +@@ -180,6 +180,12 @@ + (and (match_code "const_double") + (match_test "TARGET_NEON && op == CONST0_RTX (mode)"))) + ++(define_constraint "Dz" ++ "@internal ++ In ARM/Thumb-2 state a vector of constant zeros." ++ (and (match_code "const_vector") ++ (match_test "TARGET_NEON && op == CONST0_RTX (mode)"))) ++ + (define_constraint "Da" + "@internal + In ARM/Thumb-2 state a const_int, const_double or const_vector that can + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2010-08-20 16:21:01 +0000 ++++ new/gcc/config/arm/neon.md 2010-08-23 14:29:45 +0000 +@@ -141,7 +141,9 @@ + (UNSPEC_VUZP2 202) + (UNSPEC_VZIP1 203) + (UNSPEC_VZIP2 204) +- (UNSPEC_MISALIGNED_ACCESS 205)]) ++ (UNSPEC_MISALIGNED_ACCESS 205) ++ (UNSPEC_VCLE 206) ++ (UNSPEC_VCLT 207)]) + + ;; Double-width vector modes. + (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) +@@ -1804,6 +1806,169 @@ + [(set_attr "neon_type" "neon_int_5")] + ) + ++;; Conditional instructions. These are comparisons with conditional moves for ++;; vectors. They perform the assignment: ++;; ++;; Vop0 = (Vop4 Vop5) ? Vop1 : Vop2; ++;; ++;; where op3 is <, <=, ==, !=, >= or >. Operations are performed ++;; element-wise. ++ ++(define_expand "vcond" ++ [(set (match_operand:VDQW 0 "s_register_operand" "") ++ (if_then_else:VDQW ++ (match_operator 3 "arm_comparison_operator" ++ [(match_operand:VDQW 4 "s_register_operand" "") ++ (match_operand:VDQW 5 "nonmemory_operand" "")]) ++ (match_operand:VDQW 1 "s_register_operand" "") ++ (match_operand:VDQW 2 "s_register_operand" "")))] ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" ++{ ++ rtx mask; ++ int inverse = 0, immediate_zero = 0; ++ /* See the description of "magic" bits in the 'T' case of ++ arm_print_operand. */ ++ HOST_WIDE_INT magic_word = (mode == V2SFmode || mode == V4SFmode) ++ ? 3 : 1; ++ rtx magic_rtx = GEN_INT (magic_word); ++ ++ mask = gen_reg_rtx (mode); ++ ++ if (operands[5] == CONST0_RTX (mode)) ++ immediate_zero = 1; ++ else if (!REG_P (operands[5])) ++ operands[5] = force_reg (mode, operands[5]); ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case GE: ++ emit_insn (gen_neon_vcge (mask, operands[4], operands[5], ++ magic_rtx)); ++ break; ++ ++ case GT: ++ emit_insn (gen_neon_vcgt (mask, operands[4], operands[5], ++ magic_rtx)); ++ break; ++ ++ case EQ: ++ emit_insn (gen_neon_vceq (mask, operands[4], operands[5], ++ magic_rtx)); ++ break; ++ ++ case LE: ++ if (immediate_zero) ++ emit_insn (gen_neon_vcle (mask, operands[4], operands[5], ++ magic_rtx)); ++ else ++ emit_insn (gen_neon_vcge (mask, operands[5], operands[4], ++ magic_rtx)); ++ break; ++ ++ case LT: ++ if (immediate_zero) ++ emit_insn (gen_neon_vclt (mask, operands[4], operands[5], ++ magic_rtx)); ++ else ++ emit_insn (gen_neon_vcgt (mask, operands[5], operands[4], ++ magic_rtx)); ++ break; ++ ++ case NE: ++ emit_insn (gen_neon_vceq (mask, operands[4], operands[5], ++ magic_rtx)); ++ inverse = 1; ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (inverse) ++ emit_insn (gen_neon_vbsl (operands[0], mask, operands[2], ++ operands[1])); ++ else ++ emit_insn (gen_neon_vbsl (operands[0], mask, operands[1], ++ operands[2])); ++ ++ DONE; ++}) ++ ++(define_expand "vcondu" ++ [(set (match_operand:VDQIW 0 "s_register_operand" "") ++ (if_then_else:VDQIW ++ (match_operator 3 "arm_comparison_operator" ++ [(match_operand:VDQIW 4 "s_register_operand" "") ++ (match_operand:VDQIW 5 "s_register_operand" "")]) ++ (match_operand:VDQIW 1 "s_register_operand" "") ++ (match_operand:VDQIW 2 "s_register_operand" "")))] ++ "TARGET_NEON" ++{ ++ rtx mask; ++ int inverse = 0, immediate_zero = 0; ++ ++ mask = gen_reg_rtx (mode); ++ ++ if (operands[5] == CONST0_RTX (mode)) ++ immediate_zero = 1; ++ else if (!REG_P (operands[5])) ++ operands[5] = force_reg (mode, operands[5]); ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case GEU: ++ emit_insn (gen_neon_vcge (mask, operands[4], operands[5], ++ const0_rtx)); ++ break; ++ ++ case GTU: ++ emit_insn (gen_neon_vcgt (mask, operands[4], operands[5], ++ const0_rtx)); ++ break; ++ ++ case EQ: ++ emit_insn (gen_neon_vceq (mask, operands[4], operands[5], ++ const0_rtx)); ++ break; ++ ++ case LEU: ++ if (immediate_zero) ++ emit_insn (gen_neon_vcle (mask, operands[4], operands[5], ++ const0_rtx)); ++ else ++ emit_insn (gen_neon_vcge (mask, operands[5], operands[4], ++ const0_rtx)); ++ break; ++ ++ case LTU: ++ if (immediate_zero) ++ emit_insn (gen_neon_vclt (mask, operands[4], operands[5], ++ const0_rtx)); ++ else ++ emit_insn (gen_neon_vcgt (mask, operands[5], operands[4], ++ const0_rtx)); ++ break; ++ ++ case NE: ++ emit_insn (gen_neon_vceq (mask, operands[4], operands[5], ++ const0_rtx)); ++ inverse = 1; ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (inverse) ++ emit_insn (gen_neon_vbsl (operands[0], mask, operands[2], ++ operands[1])); ++ else ++ emit_insn (gen_neon_vbsl (operands[0], mask, operands[1], ++ operands[2])); ++ ++ DONE; ++}) ++ + ;; Patterns for builtins. + + ; good for plain vadd, vaddq. +@@ -2215,13 +2380,16 @@ + ) + + (define_insn "neon_vceq" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VCEQ))] ++ [(set (match_operand: 0 "s_register_operand" "=w,w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w,w") ++ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") ++ (match_operand:SI 3 "immediate_operand" "i,i")] ++ UNSPEC_VCEQ))] + "TARGET_NEON" +- "vceq.\t%0, %1, %2" ++ "@ ++ vceq.\t%0, %1, %2 ++ vceq.\t%0, %1, #0" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -2231,13 +2399,16 @@ + ) + + (define_insn "neon_vcge" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VCGE))] ++ [(set (match_operand: 0 "s_register_operand" "=w,w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w,w") ++ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") ++ (match_operand:SI 3 "immediate_operand" "i,i")] ++ UNSPEC_VCGE))] + "TARGET_NEON" +- "vcge.%T3%#\t%0, %1, %2" ++ "@ ++ vcge.%T3%#\t%0, %1, %2 ++ vcge.%T3%#\t%0, %1, #0" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -2247,13 +2418,16 @@ + ) + + (define_insn "neon_vcgt" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VCGT))] ++ [(set (match_operand: 0 "s_register_operand" "=w,w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w,w") ++ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") ++ (match_operand:SI 3 "immediate_operand" "i,i")] ++ UNSPEC_VCGT))] + "TARGET_NEON" +- "vcgt.%T3%#\t%0, %1, %2" ++ "@ ++ vcgt.%T3%#\t%0, %1, %2 ++ vcgt.%T3%#\t%0, %1, #0" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -2262,6 +2436,43 @@ + (const_string "neon_int_5")))] + ) + ++;; VCLE and VCLT only support comparisons with immediate zero (register ++;; variants are VCGE and VCGT with operands reversed). ++ ++(define_insn "neon_vcle" ++ [(set (match_operand: 0 "s_register_operand" "=w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w") ++ (match_operand:VDQW 2 "nonmemory_operand" "Dz") ++ (match_operand:SI 3 "immediate_operand" "i")] ++ UNSPEC_VCLE))] ++ "TARGET_NEON" ++ "vcle.%T3%#\t%0, %1, #0" ++ [(set (attr "neon_type") ++ (if_then_else (ne (symbol_ref "") (const_int 0)) ++ (if_then_else (ne (symbol_ref "") (const_int 0)) ++ (const_string "neon_fp_vadd_ddd_vabs_dd") ++ (const_string "neon_fp_vadd_qqq_vabs_qq")) ++ (const_string "neon_int_5")))] ++) ++ ++(define_insn "neon_vclt" ++ [(set (match_operand: 0 "s_register_operand" "=w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w") ++ (match_operand:VDQW 2 "nonmemory_operand" "Dz") ++ (match_operand:SI 3 "immediate_operand" "i")] ++ UNSPEC_VCLT))] ++ "TARGET_NEON" ++ "vclt.%T3%#\t%0, %1, #0" ++ [(set (attr "neon_type") ++ (if_then_else (ne (symbol_ref "") (const_int 0)) ++ (if_then_else (ne (symbol_ref "") (const_int 0)) ++ (const_string "neon_fp_vadd_ddd_vabs_dd") ++ (const_string "neon_fp_vadd_qqq_vabs_qq")) ++ (const_string "neon_int_5")))] ++) ++ + (define_insn "neon_vcage" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch new file mode 100644 index 0000000000..9bbc020629 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch @@ -0,0 +1,53 @@ +2010-08-20 Jie Zhang + + Merged from Sourcery G++ 4.4: + + gcc/ + 2009-05-29 Julian Brown + Merged from Sourcery G++ 4.3: + * config/arm/arm.md (movsi): Don't split symbol refs here. + (define_split): New. + + 2010-08-18 Julian Brown + + Issue #9222 + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-20 16:41:37 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-23 14:39:12 +0000 +@@ -5150,14 +5150,6 @@ + optimize && can_create_pseudo_p ()); + DONE; + } +- +- if (TARGET_USE_MOVT && !target_word_relocations +- && GET_CODE (operands[1]) == SYMBOL_REF +- && !flag_pic && !arm_tls_referenced_p (operands[1])) +- { +- arm_emit_movpair (operands[0], operands[1]); +- DONE; +- } + } + else /* TARGET_THUMB1... */ + { +@@ -5265,6 +5257,19 @@ + " + ) + ++(define_split ++ [(set (match_operand:SI 0 "arm_general_register_operand" "") ++ (match_operand:SI 1 "general_operand" ""))] ++ "TARGET_32BIT ++ && TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF ++ && !flag_pic && !target_word_relocations ++ && !arm_tls_referenced_p (operands[1])" ++ [(clobber (const_int 0))] ++{ ++ arm_emit_movpair (operands[0], operands[1]); ++ DONE; ++}) ++ + (define_insn "*thumb1_movsi_insn" + [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lhk") + (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*lhk"))] + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch new file mode 100644 index 0000000000..be102160c5 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch @@ -0,0 +1,663 @@ +2010-08-24 Andrew Stubbs + + Backport from FSF: + + 2010-08-07 Ramana Radhakrishnan + + * config/arm/cortex-a9.md: Rewrite VFP Pipeline description. + * config/arm/arm.c (arm_xscale_tune): Initialize sched_adjust_cost. + (arm_fastmul_tune,arm_slowmul_tune, arm_9e_tune): Likewise. + (arm_adjust_cost): Split into xscale_sched_adjust_cost and a + generic part. + (cortex_a9_sched_adjust_cost): New function. + (xscale_sched_adjust_cost): New function. + * config/arm/arm-protos.h (struct tune_params): New field + sched_adjust_cost. + * config/arm/arm-cores.def: Adjust costs for cortex-a9. + + 2010-04-17 Richard Earnshaw + + * arm-protos.h (tune_params): New structure. + * arm.c (current_tune): New variable. + (arm_constant_limit): Delete. + (struct processors): Add pointer to the tune parameters. + (arm_slowmul_tune): New tuning option. + (arm_fastmul_tune, arm_xscale_tune, arm_9e_tune): Likewise. + (all_cores): Adjust to pick up the tuning model. + (arm_constant_limit): New function. + (arm_override_options): Select the appropriate tuning model. Delete + initialization of arm_const_limit. + (arm_split_constant): Use the new constant-limit model. + (arm_rtx_costs): Pick up the current tuning model. + * arm.md (is_strongarm, is_xscale): Delete. + * arm-generic.md (load_ldsched_x, load_ldsched): Test explicitly + for Xscale variant architectures. + (mult_ldsched_strongarm, mult_ldsched): Similarly for StrongARM. + + 2010-08-23 Andrew Stubbs + + Backport from FSF: + +=== modified file 'gcc/config/arm/arm-cores.def' +--- old/gcc/config/arm/arm-cores.def 2010-07-29 15:53:39 +0000 ++++ new/gcc/config/arm/arm-cores.def 2010-08-24 13:15:54 +0000 +@@ -120,7 +120,7 @@ + ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, 9e) + ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e) + ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e) +-ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e) ++ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) + ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) + ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) + ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e) + +=== modified file 'gcc/config/arm/arm-generic.md' +--- old/gcc/config/arm/arm-generic.md 2007-08-02 09:49:31 +0000 ++++ new/gcc/config/arm/arm-generic.md 2010-08-24 13:15:54 +0000 +@@ -104,14 +104,14 @@ + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "ldsched" "yes") + (and (eq_attr "type" "load_byte,load1") +- (eq_attr "is_xscale" "yes")))) ++ (eq_attr "tune" "xscale,iwmmxt,iwmmxt2")))) + "core") + + (define_insn_reservation "load_ldsched" 2 + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "ldsched" "yes") + (and (eq_attr "type" "load_byte,load1") +- (eq_attr "is_xscale" "no")))) ++ (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2")))) + "core") + + (define_insn_reservation "load_or_store" 2 +@@ -128,14 +128,16 @@ + (define_insn_reservation "mult_ldsched_strongarm" 3 + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "ldsched" "yes") +- (and (eq_attr "is_strongarm" "yes") ++ (and (eq_attr "tune" ++ "strongarm,strongarm110,strongarm1100,strongarm1110") + (eq_attr "type" "mult")))) + "core*2") + + (define_insn_reservation "mult_ldsched" 4 + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "ldsched" "yes") +- (and (eq_attr "is_strongarm" "no") ++ (and (eq_attr "tune" ++ "!strongarm,strongarm110,strongarm1100,strongarm1110") + (eq_attr "type" "mult")))) + "core*4") + + +=== modified file 'gcc/config/arm/arm-protos.h' +--- old/gcc/config/arm/arm-protos.h 2010-08-10 13:31:21 +0000 ++++ new/gcc/config/arm/arm-protos.h 2010-08-24 13:15:54 +0000 +@@ -214,4 +214,17 @@ + + extern void arm_order_regs_for_local_alloc (void); + ++#ifdef RTX_CODE ++/* This needs to be here because we need RTX_CODE and similar. */ ++ ++struct tune_params ++{ ++ bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool); ++ bool (*sched_adjust_cost) (rtx, rtx, rtx, int *); ++ int constant_limit; ++}; ++ ++extern const struct tune_params *current_tune; ++#endif /* RTX_CODE */ ++ + #endif /* ! GCC_ARM_PROTOS_H */ + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-20 16:21:01 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-24 13:15:54 +0000 +@@ -228,6 +228,8 @@ + static void arm_trampoline_init (rtx, tree, rtx); + static rtx arm_trampoline_adjust_address (rtx); + static rtx arm_pic_static_addr (rtx orig, rtx reg); ++static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *); ++static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *); + static bool arm_vector_alignment_reachable (const_tree type, bool is_packed); + static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, + const_tree type, +@@ -545,6 +547,9 @@ + /* The processor for which instructions should be scheduled. */ + enum processor_type arm_tune = arm_none; + ++/* The current tuning set. */ ++const struct tune_params *current_tune; ++ + /* The default processor used if not overridden by commandline. */ + static enum processor_type arm_default_cpu = arm_none; + +@@ -720,9 +725,6 @@ + the next function. */ + static int after_arm_reorg = 0; + +-/* The maximum number of insns to be used when loading a constant. */ +-static int arm_constant_limit = 3; +- + enum arm_pcs arm_pcs_default; + + /* For an explanation of these variables, see final_prescan_insn below. */ +@@ -761,8 +763,44 @@ + enum processor_type core; + const char *arch; + const unsigned long flags; +- bool (* rtx_costs) (rtx, enum rtx_code, enum rtx_code, int *, bool); +-}; ++ const struct tune_params *const tune; ++}; ++ ++const struct tune_params arm_slowmul_tune = ++{ ++ arm_slowmul_rtx_costs, ++ NULL, ++ 3 ++}; ++ ++const struct tune_params arm_fastmul_tune = ++{ ++ arm_fastmul_rtx_costs, ++ NULL, ++ 1 ++}; ++ ++const struct tune_params arm_xscale_tune = ++{ ++ arm_xscale_rtx_costs, ++ xscale_sched_adjust_cost, ++ 2 ++}; ++ ++const struct tune_params arm_9e_tune = ++{ ++ arm_9e_rtx_costs, ++ NULL, ++ 1 ++}; ++ ++const struct tune_params arm_cortex_a9_tune = ++{ ++ arm_9e_rtx_costs, ++ cortex_a9_sched_adjust_cost, ++ 1 ++}; ++ + + /* Not all of these give usefully different compilation alternatives, + but there is no simple way of generalizing them. */ +@@ -770,7 +808,7 @@ + { + /* ARM Cores */ + #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ +- {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, ++ {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune}, + #include "arm-cores.def" + #undef ARM_CORE + {NULL, arm_none, NULL, 0, NULL} +@@ -779,7 +817,7 @@ + static const struct processors all_architectures[] = + { + /* ARM Architectures */ +- /* We don't specify rtx_costs here as it will be figured out ++ /* We don't specify tuning costs here as it will be figured out + from the core. */ + + {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, +@@ -928,6 +966,13 @@ + TLS_LE32 + }; + ++/* The maximum number of insns to be used when loading a constant. */ ++inline static int ++arm_constant_limit (bool size_p) ++{ ++ return size_p ? 1 : current_tune->constant_limit; ++} ++ + /* Emit an insn that's a simple single-set. Both the operands must be known + to be valid. */ + inline static rtx +@@ -1478,6 +1523,7 @@ + } + + tune_flags = all_cores[(int)arm_tune].flags; ++ current_tune = all_cores[(int)arm_tune].tune; + + if (target_fp16_format_name) + { +@@ -1875,26 +1921,12 @@ + + if (optimize_size) + { +- arm_constant_limit = 1; +- + /* If optimizing for size, bump the number of instructions that we + are prepared to conditionally execute (even on a StrongARM). */ + max_insns_skipped = 6; + } + else + { +- /* For processors with load scheduling, it never costs more than +- 2 cycles to load a constant, and the load scheduler may well +- reduce that to 1. */ +- if (arm_ld_sched) +- arm_constant_limit = 1; +- +- /* On XScale the longer latency of a load makes it more difficult +- to achieve a good schedule, so it's faster to synthesize +- constants that can be done in two insns. */ +- if (arm_tune_xscale) +- arm_constant_limit = 2; +- + /* StrongARM has early execution of branches, so a sequence + that is worth skipping is shorter. */ + if (arm_tune_strongarm) +@@ -2423,7 +2455,8 @@ + && !cond + && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, + 1, 0) +- > arm_constant_limit + (code != SET))) ++ > (arm_constant_limit (optimize_function_for_size_p (cfun)) ++ + (code != SET)))) + { + if (code == SET) + { +@@ -7771,9 +7804,9 @@ + (enum rtx_code) outer_code, total); + } + else +- return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code, +- (enum rtx_code) outer_code, +- total, speed); ++ return current_tune->rtx_costs (x, (enum rtx_code) code, ++ (enum rtx_code) outer_code, ++ total, speed); + } + + /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not +@@ -7918,7 +7951,8 @@ + so it can be ignored. */ + + static bool +-arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, int *total, bool speed) ++arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ++ int *total, bool speed) + { + enum machine_mode mode = GET_MODE (x); + +@@ -8119,15 +8153,15 @@ + return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); + } + +-static int +-arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) ++/* Adjust cost hook for XScale. */ ++static bool ++xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) + { + rtx i_pat, d_pat; + + /* Some true dependencies can have a higher cost depending + on precisely how certain input operands are used. */ +- if (arm_tune_xscale +- && REG_NOTE_KIND (link) == 0 ++ if (REG_NOTE_KIND (link) == 0 + && recog_memoized (insn) >= 0 + && recog_memoized (dep) >= 0) + { +@@ -8161,10 +8195,106 @@ + + if (reg_overlap_mentioned_p (recog_data.operand[opno], + shifted_operand)) +- return 2; ++ { ++ *cost = 2; ++ return false; ++ } + } + } + } ++ return true; ++} ++ ++/* Adjust cost hook for Cortex A9. */ ++static bool ++cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) ++{ ++ switch (REG_NOTE_KIND (link)) ++ { ++ case REG_DEP_ANTI: ++ *cost = 0; ++ return false; ++ ++ case REG_DEP_TRUE: ++ case REG_DEP_OUTPUT: ++ if (recog_memoized (insn) >= 0 ++ && recog_memoized (dep) >= 0) ++ { ++ if (GET_CODE (PATTERN (insn)) == SET) ++ { ++ if (GET_MODE_CLASS ++ (GET_MODE (SET_DEST (PATTERN (insn)))) == MODE_FLOAT ++ || GET_MODE_CLASS ++ (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) ++ { ++ enum attr_type attr_type_insn = get_attr_type (insn); ++ enum attr_type attr_type_dep = get_attr_type (dep); ++ ++ /* By default all dependencies of the form ++ s0 = s0 s1 ++ s0 = s0 s2 ++ have an extra latency of 1 cycle because ++ of the input and output dependency in this ++ case. However this gets modeled as an true ++ dependency and hence all these checks. */ ++ if (REG_P (SET_DEST (PATTERN (insn))) ++ && REG_P (SET_DEST (PATTERN (dep))) ++ && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)), ++ SET_DEST (PATTERN (dep)))) ++ { ++ /* FMACS is a special case where the dependant ++ instruction can be issued 3 cycles before ++ the normal latency in case of an output ++ dependency. */ ++ if ((attr_type_insn == TYPE_FMACS ++ || attr_type_insn == TYPE_FMACD) ++ && (attr_type_dep == TYPE_FMACS ++ || attr_type_dep == TYPE_FMACD)) ++ { ++ if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) ++ *cost = insn_default_latency (dep) - 3; ++ else ++ *cost = insn_default_latency (dep); ++ return false; ++ } ++ else ++ { ++ if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) ++ *cost = insn_default_latency (dep) + 1; ++ else ++ *cost = insn_default_latency (dep); ++ } ++ return false; ++ } ++ } ++ } ++ } ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ return true; ++} ++ ++/* This function implements the target macro TARGET_SCHED_ADJUST_COST. ++ It corrects the value of COST based on the relationship between ++ INSN and DEP through the dependence LINK. It returns the new ++ value. There is a per-core adjust_cost hook to adjust scheduler costs ++ and the per-core hook can choose to completely override the generic ++ adjust_cost function. Only put bits of code into arm_adjust_cost that ++ are common across all cores. */ ++static int ++arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) ++{ ++ rtx i_pat, d_pat; ++ ++ if (current_tune->sched_adjust_cost != NULL) ++ { ++ if (!current_tune->sched_adjust_cost (insn, link, dep, &cost)) ++ return cost; ++ } + + /* XXX This is not strictly true for the FPA. */ + if (REG_NOTE_KIND (link) == REG_DEP_ANTI +@@ -8187,7 +8317,8 @@ + constant pool are cached, and that others will miss. This is a + hack. */ + +- if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) ++ if ((GET_CODE (src_mem) == SYMBOL_REF ++ && CONSTANT_POOL_ADDRESS_P (src_mem)) + || reg_mentioned_p (stack_pointer_rtx, src_mem) + || reg_mentioned_p (frame_pointer_rtx, src_mem) + || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-23 14:39:12 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-24 13:15:54 +0000 +@@ -150,13 +150,6 @@ + ; patterns that share the same RTL in both ARM and Thumb code. + (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code"))) + +-; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects +-; scheduling decisions for the load unit and the multiplier. +-(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm"))) +- +-; IS_XSCALE is set to 'yes' when compiling for XScale. +-(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale"))) +- + ;; Operand number of an input operand that is shifted. Zero if the + ;; given instruction does not shift one of its input operands. + (define_attr "shift" "" (const_int 0)) + +=== modified file 'gcc/config/arm/cortex-a9.md' +--- old/gcc/config/arm/cortex-a9.md 2009-10-31 16:40:03 +0000 ++++ new/gcc/config/arm/cortex-a9.md 2010-08-24 13:15:54 +0000 +@@ -2,8 +2,10 @@ + ;; Copyright (C) 2008, 2009 Free Software Foundation, Inc. + ;; Originally written by CodeSourcery for VFP. + ;; +-;; Integer core pipeline description contributed by ARM Ltd. +-;; ++;; Rewritten by Ramana Radhakrishnan ++;; Integer Pipeline description contributed by ARM Ltd. ++;; VFP Pipeline description rewritten and contributed by ARM Ltd. ++ + ;; This file is part of GCC. + ;; + ;; GCC is free software; you can redistribute it and/or modify it +@@ -22,28 +24,27 @@ + + (define_automaton "cortex_a9") + +-;; The Cortex-A9 integer core is modelled as a dual issue pipeline that has ++;; The Cortex-A9 core is modelled as a dual issue pipeline that has + ;; the following components. + ;; 1. 1 Load Store Pipeline. + ;; 2. P0 / main pipeline for data processing instructions. + ;; 3. P1 / Dual pipeline for Data processing instructions. + ;; 4. MAC pipeline for multiply as well as multiply + ;; and accumulate instructions. +-;; 5. 1 VFP / Neon pipeline. +-;; The Load/Store and VFP/Neon pipeline are multiplexed. ++;; 5. 1 VFP and an optional Neon unit. ++;; The Load/Store, VFP and Neon issue pipeline are multiplexed. + ;; The P0 / main pipeline and M1 stage of the MAC pipeline are + ;; multiplexed. + ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are + ;; multiplexed. +-;; There are only 4 register read ports and hence at any point of ++;; There are only 4 integer register read ports and hence at any point of + ;; time we can't have issue down the E1 and the E2 ports unless + ;; of course there are bypass paths that get exercised. + ;; Both P0 and P1 have 2 stages E1 and E2. + ;; Data processing instructions issue to E1 or E2 depending on + ;; whether they have an early shift or not. + +- +-(define_cpu_unit "cortex_a9_vfp, cortex_a9_ls" "cortex_a9") ++(define_cpu_unit "ca9_issue_vfp_neon, cortex_a9_ls" "cortex_a9") + (define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9") + (define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9") + (define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9") +@@ -71,11 +72,7 @@ + + ;; Issue at the same time along the load store pipeline and + ;; the VFP / Neon pipeline is not possible. +-;; FIXME:: At some point we need to model the issue +-;; of the load store and the vfp being shared rather than anything else. +- +-(exclusion_set "cortex_a9_ls" "cortex_a9_vfp") +- ++(exclusion_set "cortex_a9_ls" "ca9_issue_vfp_neon") + + ;; Default data processing instruction without any shift + ;; The only exception to this is the mov instruction +@@ -101,18 +98,13 @@ + + (define_insn_reservation "cortex_a9_load1_2" 4 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "load1, load2, load_byte")) ++ (eq_attr "type" "load1, load2, load_byte, f_loads, f_loadd")) + "cortex_a9_ls") + + ;; Loads multiples and store multiples can't be issued for 2 cycles in a + ;; row. The description below assumes that addresses are 64 bit aligned. + ;; If not, there is an extra cycle latency which is not modelled. + +-;; FIXME:: This bit might need to be reworked when we get to +-;; tuning for the VFP because strictly speaking the ldm +-;; is sent to the LSU unit as is and there is only an +-;; issue restriction between the LSU and the VFP/ Neon unit. +- + (define_insn_reservation "cortex_a9_load3_4" 5 + (and (eq_attr "tune" "cortexa9") + (eq_attr "type" "load3, load4")) +@@ -120,12 +112,13 @@ + + (define_insn_reservation "cortex_a9_store1_2" 0 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "store1, store2")) ++ (eq_attr "type" "store1, store2, f_stores, f_stored")) + "cortex_a9_ls") + + ;; Almost all our store multiples use an auto-increment + ;; form. Don't issue back to back load and store multiples + ;; because the load store unit will stall. ++ + (define_insn_reservation "cortex_a9_store3_4" 0 + (and (eq_attr "tune" "cortexa9") + (eq_attr "type" "store3, store4")) +@@ -193,47 +186,79 @@ + (define_insn_reservation "cortex_a9_call" 0 + (and (eq_attr "tune" "cortexa9") + (eq_attr "type" "call")) +- "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + cortex_a9_vfp") ++ "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + ca9_issue_vfp_neon") + + + ;; Pipelining for VFP instructions. +- +-(define_insn_reservation "cortex_a9_ffarith" 1 ++;; Issue happens either along load store unit or the VFP / Neon unit. ++;; Pipeline Instruction Classification. ++;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r ++;; FP_ADD - fadds, faddd, fcmps (1) ++;; FPMUL - fmul{s,d}, fmac{s,d} ++;; FPDIV - fdiv{s,d} ++(define_cpu_unit "ca9fps" "cortex_a9") ++(define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9") ++(define_cpu_unit "ca9fp_mul1, ca9fp_mul2 , ca9fp_mul3, ca9fp_mul4" "cortex_a9") ++(define_cpu_unit "ca9fp_ds1" "cortex_a9") ++ ++ ++;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle. ++(define_insn_reservation "cortex_a9_fps" 2 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd,fconsts,fconstd")) +- "cortex_a9_vfp") ++ (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag")) ++ "ca9_issue_vfp_neon + ca9fps") ++ ++(define_bypass 1 ++ "cortex_a9_fps" ++ "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply") ++ ++;; Scheduling on the FP_ADD pipeline. ++(define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4") + + (define_insn_reservation "cortex_a9_fadd" 4 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fadds,faddd,f_cvt")) +- "cortex_a9_vfp") +- +-(define_insn_reservation "cortex_a9_fmuls" 5 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmuls")) +- "cortex_a9_vfp") +- +-(define_insn_reservation "cortex_a9_fmuld" 6 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmuld")) +- "cortex_a9_vfp*2") ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fadds, faddd, f_cvt")) ++ "ca9fp_add") ++ ++(define_insn_reservation "cortex_a9_fcmp" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fcmps, fcmpd")) ++ "ca9_issue_vfp_neon + ca9fp_add1") ++ ++;; Scheduling for the Multiply and MAC instructions. ++(define_reservation "ca9fmuls" ++ "ca9fp_mul1 + ca9_issue_vfp_neon, ca9fp_mul2, ca9fp_mul3, ca9fp_mul4") ++ ++(define_reservation "ca9fmuld" ++ "ca9fp_mul1 + ca9_issue_vfp_neon, (ca9fp_mul1 + ca9fp_mul2), ca9fp_mul2, ca9fp_mul3, ca9fp_mul4") ++ ++(define_insn_reservation "cortex_a9_fmuls" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fmuls")) ++ "ca9fmuls") ++ ++(define_insn_reservation "cortex_a9_fmuld" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fmuld")) ++ "ca9fmuld") + + (define_insn_reservation "cortex_a9_fmacs" 8 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmacs")) +- "cortex_a9_vfp") +- +-(define_insn_reservation "cortex_a9_fmacd" 8 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmacd")) +- "cortex_a9_vfp*2") +- ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fmacs")) ++ "ca9fmuls, ca9fp_add") ++ ++(define_insn_reservation "cortex_a9_fmacd" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fmacd")) ++ "ca9fmuld, ca9fp_add") ++ ++;; Division pipeline description. + (define_insn_reservation "cortex_a9_fdivs" 15 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fdivs")) +- "cortex_a9_vfp*10") ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fdivs")) ++ "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14") + + (define_insn_reservation "cortex_a9_fdivd" 25 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fdivd")) +- "cortex_a9_vfp*20") ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fdivd")) ++ "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24") + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch new file mode 100644 index 0000000000..03b478b798 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch @@ -0,0 +1,380 @@ +2010-08-25 Andrew Stubbs + + Revert: + + 2010-07-26 Julian Brown + + Merge from Sourcery G++ 4.4: + + 2010-04-11 Julian Brown + + Issue #7326 + + gcc/ + * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. + * config/arm/arm.md (generic_sched): No for Cortex-A5. + (generic_vfp): Likewise. + (cortex-a5.md): Include. + * config/arm/cortex-a5.md: New. + + 2010-08-24 Andrew Stubbs + + Backport from FSF: + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-24 13:15:54 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-25 16:20:13 +0000 +@@ -22472,7 +22472,6 @@ + { + case cortexr4: + case cortexr4f: +- case cortexa5: + case cortexa8: + case cortexa9: + return 2; + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-24 13:15:54 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-25 16:20:13 +0000 +@@ -412,7 +412,7 @@ + + (define_attr "generic_sched" "yes,no" + (const (if_then_else +- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9") ++ (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9") + (eq_attr "tune_cortexr4" "yes")) + (const_string "no") + (const_string "yes")))) +@@ -420,7 +420,7 @@ + (define_attr "generic_vfp" "yes,no" + (const (if_then_else + (and (eq_attr "fpu" "vfp") +- (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9") ++ (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9") + (eq_attr "tune_cortexr4" "no")) + (const_string "yes") + (const_string "no")))) +@@ -444,7 +444,6 @@ + (include "arm1020e.md") + (include "arm1026ejs.md") + (include "arm1136jfs.md") +-(include "cortex-a5.md") + (include "cortex-a8.md") + (include "cortex-a9.md") + (include "cortex-r4.md") + +=== removed file 'gcc/config/arm/cortex-a5.md' +--- old/gcc/config/arm/cortex-a5.md 2010-08-13 15:15:12 +0000 ++++ new/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000 +@@ -1,310 +0,0 @@ +-;; ARM Cortex-A5 pipeline description +-;; Copyright (C) 2010 Free Software Foundation, Inc. +-;; Contributed by CodeSourcery. +-;; +-;; This file is part of GCC. +-;; +-;; GCC is free software; you can redistribute it and/or modify it +-;; under the terms of the GNU General Public License as published by +-;; the Free Software Foundation; either version 3, or (at your option) +-;; any later version. +-;; +-;; GCC is distributed in the hope that it will be useful, but +-;; WITHOUT ANY WARRANTY; without even the implied warranty of +-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-;; General Public License for more details. +-;; +-;; You should have received a copy of the GNU General Public License +-;; along with GCC; see the file COPYING3. If not see +-;; . +- +-(define_automaton "cortex_a5") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; Functional units. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-;; The integer (ALU) pipeline. There are five DPU pipeline stages. However the +-;; decode/issue stages operate the same for all instructions, so do not model +-;; them. We only need to model the first execute stage because instructions +-;; always advance one stage per cycle in order. Only branch instructions may +-;; dual-issue, so a single unit covers all of the LS, ALU, MAC and FPU +-;; pipelines. +- +-(define_cpu_unit "cortex_a5_ex1" "cortex_a5") +- +-;; The branch pipeline. Branches can dual-issue with other instructions +-;; (except when those instructions take multiple cycles to issue). +- +-(define_cpu_unit "cortex_a5_branch" "cortex_a5") +- +-;; Pseudo-unit for blocking the multiply pipeline when a double-precision +-;; multiply is in progress. +- +-(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5") +- +-;; The floating-point add pipeline (ex1/f1 stage), used to model the usage +-;; of the add pipeline by fmac instructions, etc. +- +-(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5") +- +-;; Floating-point div/sqrt (long latency, out-of-order completion). +- +-(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; ALU instructions. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-(define_insn_reservation "cortex_a5_alu" 2 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "alu")) +- "cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_alu_shift" 2 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "alu_shift,alu_shift_reg")) +- "cortex_a5_ex1") +- +-;; Forwarding path for unshifted operands. +- +-(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" +- "cortex_a5_alu") +- +-(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" +- "cortex_a5_alu_shift" +- "arm_no_early_alu_shift_dep") +- +-;; The multiplier pipeline can forward results from wr stage only (so I don't +-;; think there's any need to specify bypasses). +- +-(define_insn_reservation "cortex_a5_mul" 2 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "mult")) +- "cortex_a5_ex1") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; Load/store instructions. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-;; Address-generation happens in the issue stage, which is one stage behind +-;; the ex1 stage (the first stage we care about for scheduling purposes). The +-;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr. +- +-;; FIXME: These might not be entirely accurate for load2, load3, load4. I think +-;; they make sense since there's a 32-bit interface between the DPU and the DCU, +-;; so we can't load more than that per cycle. The store2, store3, store4 +-;; reservations are similarly guessed. +- +-(define_insn_reservation "cortex_a5_load1" 2 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "load_byte,load1")) +- "cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_store1" 0 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "store1")) +- "cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_load2" 3 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "load2")) +- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_store2" 0 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "store2")) +- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_load3" 4 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "load3")) +- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ +- cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_store3" 0 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "store3")) +- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ +- cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_load4" 5 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "load3")) +- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ +- cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_store4" 0 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "store3")) +- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ +- cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; Branches. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-;; Direct branches are the only instructions we can dual-issue (also IT and +-;; nop, but those aren't very interesting for scheduling). (The latency here +-;; is meant to represent when the branch actually takes place, but may not be +-;; entirely correct.) +- +-(define_insn_reservation "cortex_a5_branch" 3 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "branch,call")) +- "cortex_a5_branch") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; Floating-point arithmetic. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-(define_insn_reservation "cortex_a5_fpalu" 4 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ +- fcmps, fcmpd")) +- "cortex_a5_ex1+cortex_a5_fpadd_pipe") +- +-;; For fconsts and fconstd, 8-bit immediate data is passed directly from +-;; f1 to f3 (which I think reduces the latency by one cycle). +- +-(define_insn_reservation "cortex_a5_fconst" 3 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fconsts,fconstd")) +- "cortex_a5_ex1+cortex_a5_fpadd_pipe") +- +-;; We should try not to attempt to issue a single-precision multiplication in +-;; the middle of a double-precision multiplication operation (the usage of +-;; cortex_a5_fpmul_pipe). +- +-(define_insn_reservation "cortex_a5_fpmuls" 4 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fmuls")) +- "cortex_a5_ex1+cortex_a5_fpmul_pipe") +- +-;; For single-precision multiply-accumulate, the add (accumulate) is issued +-;; whilst the multiply is in F4. The multiply result can then be forwarded +-;; from F5 to F1. The issue unit is only used once (when we first start +-;; processing the instruction), but the usage of the FP add pipeline could +-;; block other instructions attempting to use it simultaneously. We try to +-;; avoid that using cortex_a5_fpadd_pipe. +- +-(define_insn_reservation "cortex_a5_fpmacs" 8 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fmacs")) +- "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") +- +-;; Non-multiply instructions can issue in the middle two instructions of a +-;; double-precision multiply. Note that it isn't entirely clear when a branch +-;; can dual-issue when a multi-cycle multiplication is in progress; we ignore +-;; that for now though. +- +-(define_insn_reservation "cortex_a5_fpmuld" 7 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fmuld")) +- "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ +- cortex_a5_ex1+cortex_a5_fpmul_pipe") +- +-(define_insn_reservation "cortex_a5_fpmacd" 11 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fmacd")) +- "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ +- cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; Floating-point divide/square root instructions. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-;; ??? Not sure if the 14 cycles taken for single-precision divide to complete +-;; includes the time taken for the special instruction used to collect the +-;; result to travel down the multiply pipeline, or not. Assuming so. (If +-;; that's wrong, the latency should be increased by a few cycles.) +- +-;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the +-;; multiply pipeline to collect the divide/square-root result. +- +-(define_insn_reservation "cortex_a5_fdivs" 14 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fdivs")) +- "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") +- +-;; ??? Similarly for fdivd. +- +-(define_insn_reservation "cortex_a5_fdivd" 29 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "fdivd")) +- "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; VFP to/from core transfers. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-;; FP loads take data from wr/rot/f3. Might need to define bypasses to model +-;; this? +- +-;; Core-to-VFP transfers use the multiply pipeline. +-;; Not sure about this at all... I think we need some bypasses too. +- +-(define_insn_reservation "cortex_a5_r2f" 4 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "r_2_f")) +- "cortex_a5_ex1") +- +-;; Not sure about this either. 6.8.7 says "Additionally, the store pipe used +-;; for store and FP->core register transfers can forward into the F2 and F3 +-;; stages." +-;; This doesn't correspond to what we have though. +- +-(define_insn_reservation "cortex_a5_f2r" 2 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "f_2_r")) +- "cortex_a5_ex1") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; VFP flag transfer. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-;; ??? The flag forwarding described in section 6.8.11 of the Cortex-A5 DPU +-;; specification (from fmstat to the ex2 stage of the second instruction) is +-;; not modeled at present. +- +-(define_insn_reservation "cortex_a5_f_flags" 4 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "f_flag")) +- "cortex_a5_ex1") +- +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +-;; VFP load/store. +-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +- +-(define_insn_reservation "cortex_a5_f_loads" 4 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "f_loads")) +- "cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_f_loadd" 5 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "f_load,f_loadd")) +- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_f_stores" 0 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "f_stores")) +- "cortex_a5_ex1") +- +-(define_insn_reservation "cortex_a5_f_stored" 0 +- (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "f_store,f_stored")) +- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") +- +-;; Load-to-use for floating-point values has a penalty of one cycle, i.e. a +-;; latency of two (6.8.3). +- +-(define_bypass 2 "cortex_a5_f_loads" +- "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ +- cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ +- cortex_a5_f2r") +- +-(define_bypass 3 "cortex_a5_f_loadd" +- "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ +- cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ +- cortex_a5_f2r") + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch new file mode 100644 index 0000000000..60608e4813 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch @@ -0,0 +1,360 @@ + Backport from FSF: + + 2010-08-25 Julian Brown + + * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. + * config/arm/arm.md (generic_sched): No for Cortex-A5. + (generic_vfp): Likewise. + (cortex-a5.md): Include. + * config/arm/cortex-a5.md: New. + +2010-08-25 Andrew Stubbs + + Revert: + + 2010-07-26 Julian Brown + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-25 16:20:13 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-25 16:22:17 +0000 +@@ -22472,6 +22472,7 @@ + { + case cortexr4: + case cortexr4f: ++ case cortexa5: + case cortexa8: + case cortexa9: + return 2; + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-25 16:20:13 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-25 16:22:17 +0000 +@@ -412,7 +412,7 @@ + + (define_attr "generic_sched" "yes,no" + (const (if_then_else +- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9") ++ (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9") + (eq_attr "tune_cortexr4" "yes")) + (const_string "no") + (const_string "yes")))) +@@ -420,7 +420,7 @@ + (define_attr "generic_vfp" "yes,no" + (const (if_then_else + (and (eq_attr "fpu" "vfp") +- (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9") ++ (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9") + (eq_attr "tune_cortexr4" "no")) + (const_string "yes") + (const_string "no")))) +@@ -444,6 +444,7 @@ + (include "arm1020e.md") + (include "arm1026ejs.md") + (include "arm1136jfs.md") ++(include "cortex-a5.md") + (include "cortex-a8.md") + (include "cortex-a9.md") + (include "cortex-r4.md") + +=== added file 'gcc/config/arm/cortex-a5.md' +--- old/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000 ++++ new/gcc/config/arm/cortex-a5.md 2010-08-25 16:22:17 +0000 +@@ -0,0 +1,297 @@ ++;; ARM Cortex-A5 pipeline description ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; Contributed by CodeSourcery. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "cortex_a5") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Functional units. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; The integer (ALU) pipeline. There are five DPU pipeline ++;; stages. However the decode/issue stages operate the same for all ++;; instructions, so do not model them. We only need to model the ++;; first execute stage because instructions always advance one stage ++;; per cycle in order. Only branch instructions may dual-issue, so a ++;; single unit covers all of the LS, ALU, MAC and FPU pipelines. ++ ++(define_cpu_unit "cortex_a5_ex1" "cortex_a5") ++ ++;; The branch pipeline. Branches can dual-issue with other instructions ++;; (except when those instructions take multiple cycles to issue). ++ ++(define_cpu_unit "cortex_a5_branch" "cortex_a5") ++ ++;; Pseudo-unit for blocking the multiply pipeline when a double-precision ++;; multiply is in progress. ++ ++(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5") ++ ++;; The floating-point add pipeline (ex1/f1 stage), used to model the usage ++;; of the add pipeline by fmac instructions, etc. ++ ++(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5") ++ ++;; Floating-point div/sqrt (long latency, out-of-order completion). ++ ++(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ALU instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_alu" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "alu")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_alu_shift" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "alu_shift,alu_shift_reg")) ++ "cortex_a5_ex1") ++ ++;; Forwarding path for unshifted operands. ++ ++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" ++ "cortex_a5_alu") ++ ++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" ++ "cortex_a5_alu_shift" ++ "arm_no_early_alu_shift_dep") ++ ++;; The multiplier pipeline can forward results from wr stage only so ++;; there's no need to specify bypasses). ++ ++(define_insn_reservation "cortex_a5_mul" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "mult")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Load/store instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Address-generation happens in the issue stage, which is one stage behind ++;; the ex1 stage (the first stage we care about for scheduling purposes). The ++;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr. ++ ++(define_insn_reservation "cortex_a5_load1" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load_byte,load1")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store1" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store1")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load2" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load2")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store2" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store2")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load3" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store3" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load4" 5 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store4" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Branches. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Direct branches are the only instructions we can dual-issue (also IT and ++;; nop, but those aren't very interesting for scheduling). (The latency here ++;; is meant to represent when the branch actually takes place, but may not be ++;; entirely correct.) ++ ++(define_insn_reservation "cortex_a5_branch" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "branch,call")) ++ "cortex_a5_branch") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point arithmetic. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_fpalu" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ ++ fcmps, fcmpd")) ++ "cortex_a5_ex1+cortex_a5_fpadd_pipe") ++ ++;; For fconsts and fconstd, 8-bit immediate data is passed directly from ++;; f1 to f3 (which I think reduces the latency by one cycle). ++ ++(define_insn_reservation "cortex_a5_fconst" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fconsts,fconstd")) ++ "cortex_a5_ex1+cortex_a5_fpadd_pipe") ++ ++;; We should try not to attempt to issue a single-precision multiplication in ++;; the middle of a double-precision multiplication operation (the usage of ++;; cortex_a5_fpmul_pipe). ++ ++(define_insn_reservation "cortex_a5_fpmuls" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmuls")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe") ++ ++;; For single-precision multiply-accumulate, the add (accumulate) is issued ++;; whilst the multiply is in F4. The multiply result can then be forwarded ++;; from F5 to F1. The issue unit is only used once (when we first start ++;; processing the instruction), but the usage of the FP add pipeline could ++;; block other instructions attempting to use it simultaneously. We try to ++;; avoid that using cortex_a5_fpadd_pipe. ++ ++(define_insn_reservation "cortex_a5_fpmacs" 8 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmacs")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") ++ ++;; Non-multiply instructions can issue in the middle two instructions of a ++;; double-precision multiply. Note that it isn't entirely clear when a branch ++;; can dual-issue when a multi-cycle multiplication is in progress; we ignore ++;; that for now though. ++ ++(define_insn_reservation "cortex_a5_fpmuld" 7 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmuld")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ ++ cortex_a5_ex1+cortex_a5_fpmul_pipe") ++ ++(define_insn_reservation "cortex_a5_fpmacd" 11 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmacd")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ ++ cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point divide/square root instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; ??? Not sure if the 14 cycles taken for single-precision divide to complete ++;; includes the time taken for the special instruction used to collect the ++;; result to travel down the multiply pipeline, or not. Assuming so. (If ++;; that's wrong, the latency should be increased by a few cycles.) ++ ++;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the ++;; multiply pipeline to collect the divide/square-root result. ++ ++(define_insn_reservation "cortex_a5_fdivs" 14 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fdivs")) ++ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") ++ ++;; ??? Similarly for fdivd. ++ ++(define_insn_reservation "cortex_a5_fdivd" 29 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fdivd")) ++ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP to/from core transfers. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; FP loads take data from wr/rot/f3. ++ ++;; Core-to-VFP transfers use the multiply pipeline. ++ ++(define_insn_reservation "cortex_a5_r2f" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "r_2_f")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f2r" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_2_r")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP flag transfer. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; ??? The flag forwarding from fmstat to the ex2 stage of the second ++;; instruction is not modeled at present. ++ ++(define_insn_reservation "cortex_a5_f_flags" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_flag")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP load/store. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_f_loads" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_loads")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_loadd" 5 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_load,f_loadd")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_stores" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_stores")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_stored" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_store,f_stored")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++;; Load-to-use for floating-point values has a penalty of one cycle, ++;; i.e. a latency of two. ++ ++(define_bypass 2 "cortex_a5_f_loads" ++ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ ++ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ ++ cortex_a5_f2r") ++ ++(define_bypass 3 "cortex_a5_f_loadd" ++ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ ++ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ ++ cortex_a5_f2r") + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch new file mode 100644 index 0000000000..dfe193ff28 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch @@ -0,0 +1,72 @@ +2010-08-26 Andrew Stubbs + + Merge from Ubuntu GCC: + + GCC bugzilla PR objc/41848. + + gcc/ + * objc/lang-specs.h: Work around ObjC and -fsection-anchors. + + gcc/testsuite/ + * objc/execute/forward-1.x: Update for ARM. + + 2010-08-25 Andrew Stubbs + + Backport from FSF: + +=== modified file 'gcc/objc/lang-specs.h' +--- old/gcc/objc/lang-specs.h 2007-08-02 09:37:36 +0000 ++++ new/gcc/objc/lang-specs.h 2010-08-26 14:02:04 +0000 +@@ -26,29 +26,33 @@ + {"@objective-c", + "%{E|M|MM:cc1obj -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}\ + %(cpp_options) %(cpp_debug_options)}\ ++ %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ + %{!E:%{!M:%{!MM:\ + %{traditional|ftraditional|traditional-cpp:\ + %eGNU Objective C no longer supports traditional compilation}\ + %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ +- cc1obj -fpreprocessed %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\ ++ cc1obj -fpreprocessed -fno-section-anchors %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\ + %{!save-temps:%{!no-integrated-cpp:\ +- cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\ ++ cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, + {".mi", "@objc-cpp-output", 0, 0, 0}, + {"@objc-cpp-output", +- "%{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ +- %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, ++ "%{!M:%{!MM:%{!E:cc1obj -fno-section-anchors -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ %{!fsyntax-only:%(invoke_as)}}}} \ ++ %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} ", 0, 0, 0}, + {"@objective-c-header", + "%{E|M|MM:cc1obj -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}\ + %(cpp_options) %(cpp_debug_options)}\ ++ %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ + %{!E:%{!M:%{!MM:\ + %{traditional|ftraditional|traditional-cpp:\ + %eGNU Objective C no longer supports traditional compilation}\ + %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ +- cc1obj -fpreprocessed %b.mi %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ cc1obj -fpreprocessed %b.mi %(cc1_options) -fno-section-anchors %{print-objc-runtime-info} %{gen-decls}\ + -o %g.s %{!o*:--output-pch=%i.gch}\ + %W{o*:--output-pch=%*}%V}\ ++ %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ + %{!save-temps:%{!no-integrated-cpp:\ +- cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ + -o %g.s %{!o*:--output-pch=%i.gch}\ + %W{o*:--output-pch=%*}%V}}}}}", 0, 0, 0}, + +=== modified file 'gcc/testsuite/objc/execute/forward-1.x' +--- old/gcc/testsuite/objc/execute/forward-1.x 2010-03-25 22:25:05 +0000 ++++ new/gcc/testsuite/objc/execute/forward-1.x 2010-08-26 14:02:04 +0000 +@@ -4,6 +4,7 @@ + + if { ([istarget x86_64-*-linux*] && [check_effective_target_lp64] ) + || [istarget powerpc*-*-linux*] ++ || [istarget arm*] + || [istarget powerpc*-*-aix*] + || [istarget s390*-*-*-linux*] + || [istarget sh4-*-linux*] + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch new file mode 100644 index 0000000000..fac64b9642 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch @@ -0,0 +1,146 @@ +2010-08-26 Maciej Rozycki + + Merge from Sourcery G++ 4.4: + + 2009-02-17 Andrew Jenner + Maciej Rozycki + + gcc/ + * unwind.inc (_Unwind_RaiseException): Use return value of + uw_init_context. + * unwind-dw2.c (uw_init_context): Make macro an expression instead of + a statement. + (uw_init_context_1): Add return value. + * unwind-sjlj.c (uw_init_context): Add return value. + + 2010-08-26 Andrew Stubbs + + Merge from Ubuntu GCC: + +=== modified file 'gcc/unwind-dw2.c' +--- old/gcc/unwind-dw2.c 2010-04-27 08:41:30 +0000 ++++ new/gcc/unwind-dw2.c 2010-08-26 15:38:19 +0000 +@@ -1414,16 +1414,12 @@ + /* Fill in CONTEXT for top-of-stack. The only valid registers at this + level will be the return address and the CFA. */ + +-#define uw_init_context(CONTEXT) \ +- do \ +- { \ +- /* Do any necessary initialization to access arbitrary stack frames. \ +- On the SPARC, this means flushing the register windows. */ \ +- __builtin_unwind_init (); \ +- uw_init_context_1 (CONTEXT, __builtin_dwarf_cfa (), \ +- __builtin_return_address (0)); \ +- } \ +- while (0) ++#define uw_init_context(CONTEXT) \ ++ /* Do any necessary initialization to access arbitrary stack frames. \ ++ On the SPARC, this means flushing the register windows. */ \ ++ (__builtin_unwind_init (), \ ++ uw_init_context_1 ((CONTEXT), __builtin_dwarf_cfa (), \ ++ __builtin_return_address (0))) + + static inline void + init_dwarf_reg_size_table (void) +@@ -1431,7 +1427,7 @@ + __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table); + } + +-static void __attribute__((noinline)) ++static _Unwind_Reason_Code __attribute__((noinline)) + uw_init_context_1 (struct _Unwind_Context *context, + void *outer_cfa, void *outer_ra) + { +@@ -1445,7 +1441,8 @@ + context->flags = EXTENDED_CONTEXT_BIT; + + code = uw_frame_state_for (context, &fs); +- gcc_assert (code == _URC_NO_REASON); ++ if (code != _URC_NO_REASON) ++ return code; + + #if __GTHREADS + { +@@ -1471,6 +1468,8 @@ + initialization context, then we can't see it in the given + call frame data. So have the initialization context tell us. */ + context->ra = __builtin_extract_return_addr (outer_ra); ++ ++ return _URC_NO_REASON; + } + + static void _Unwind_DebugHook (void *, void *) + +=== modified file 'gcc/unwind-sjlj.c' +--- old/gcc/unwind-sjlj.c 2009-04-09 14:00:19 +0000 ++++ new/gcc/unwind-sjlj.c 2010-08-26 15:38:19 +0000 +@@ -292,10 +292,11 @@ + uw_update_context (context, fs); + } + +-static inline void ++static inline _Unwind_Reason_Code + uw_init_context (struct _Unwind_Context *context) + { + context->fc = _Unwind_SjLj_GetContext (); ++ return _URC_NO_REASON; + } + + static void __attribute__((noreturn)) + +=== modified file 'gcc/unwind.inc' +--- old/gcc/unwind.inc 2009-04-09 14:00:19 +0000 ++++ new/gcc/unwind.inc 2010-08-26 15:38:19 +0000 +@@ -85,7 +85,8 @@ + _Unwind_Reason_Code code; + + /* Set up this_context to describe the current stack frame. */ +- uw_init_context (&this_context); ++ code = uw_init_context (&this_context); ++ gcc_assert (code == _URC_NO_REASON); + cur_context = this_context; + + /* Phase 1: Search. Unwind the stack, calling the personality routine +@@ -198,7 +199,8 @@ + struct _Unwind_Context this_context, cur_context; + _Unwind_Reason_Code code; + +- uw_init_context (&this_context); ++ code = uw_init_context (&this_context); ++ gcc_assert (code == _URC_NO_REASON); + cur_context = this_context; + + exc->private_1 = (_Unwind_Ptr) stop; +@@ -221,7 +223,8 @@ + struct _Unwind_Context this_context, cur_context; + _Unwind_Reason_Code code; + +- uw_init_context (&this_context); ++ code = uw_init_context (&this_context); ++ gcc_assert (code == _URC_NO_REASON); + cur_context = this_context; + + /* Choose between continuing to process _Unwind_RaiseException +@@ -251,7 +254,8 @@ + if (exc->private_1 == 0) + return _Unwind_RaiseException (exc); + +- uw_init_context (&this_context); ++ code = uw_init_context (&this_context); ++ gcc_assert (code == _URC_NO_REASON); + cur_context = this_context; + + code = _Unwind_ForcedUnwind_Phase2 (exc, &cur_context); +@@ -280,7 +284,9 @@ + struct _Unwind_Context context; + _Unwind_Reason_Code code; + +- uw_init_context (&context); ++ code = uw_init_context (&context); ++ if (code != _URC_NO_REASON) ++ return _URC_FATAL_PHASE1_ERROR; + + while (1) + { + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch new file mode 100644 index 0000000000..5e402a753e --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch @@ -0,0 +1,35 @@ +2010-08-26 Paul Brook + + Merge from Sourcery G++ 4.3/4.4: + 2007-03-30 Paul Brook + gcc/ + * calls.c (store_one_arg): Check alignment of mode used for save. + + 2010-08-26 Maciej Rozycki + + Merge from Sourcery G++ 4.4: + +=== modified file 'gcc/calls.c' +--- old/gcc/calls.c 2010-08-13 10:50:45 +0000 ++++ new/gcc/calls.c 2010-08-26 15:44:20 +0000 +@@ -4048,8 +4048,17 @@ + /* We need to make a save area. */ + unsigned int size = arg->locate.size.constant * BITS_PER_UNIT; + enum machine_mode save_mode = mode_for_size (size, MODE_INT, 1); +- rtx adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); +- rtx stack_area = gen_rtx_MEM (save_mode, adr); ++ rtx adr; ++ rtx stack_area; ++ ++ /* We can only use save_mode if the arg is sufficiently ++ aligned. */ ++ if (STRICT_ALIGNMENT ++ && GET_MODE_ALIGNMENT (save_mode) > arg->locate.boundary) ++ save_mode = BLKmode; ++ ++ adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); ++ stack_area = gen_rtx_MEM (save_mode, adr); + + if (save_mode == BLKmode) + { + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch new file mode 100644 index 0000000000..d51f0874e3 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch @@ -0,0 +1,28 @@ + Issue #1510 + 2007-04-27 Paul Brook + gcc/ + * cse.c (cse_process_notes): Make sure PLUS are canonical. + +2010-08-26 Paul Brook + + Merge from Sourcery G++ 4.3/4.4: + 2007-03-30 Paul Brook + gcc/ + * calls.c (store_one_arg): Check alignment of mode used for save. + +=== modified file 'gcc/cse.c' +--- old/gcc/cse.c 2010-01-12 20:25:10 +0000 ++++ new/gcc/cse.c 2010-08-26 15:53:20 +0000 +@@ -6061,6 +6061,11 @@ + validate_change (object, &XEXP (x, i), + cse_process_notes (XEXP (x, i), object, changed), 0); + ++ /* Rebuild a PLUS expression in canonical form if the first operand ++ ends up as a constant. */ ++ if (code == PLUS && GET_CODE (XEXP (x, 0)) == CONST_INT) ++ return plus_constant (XEXP(x, 1), INTVAL (XEXP (x, 0))); ++ + return x; + } + + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch new file mode 100644 index 0000000000..aacf19b7c9 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch @@ -0,0 +1,159 @@ +2010-08-27 Paul Brook + + gcc/ + * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si, + thumb2_notsi_shiftsi, thumb2_notsi_shiftsi_compare0, + thumb2_not_shiftsi_compare0_scratch, thumb2_cmpsi_shiftsi, + thumb2_cmpsi_shiftsi_swp, thumb2_cmpsi_neg_shiftsi, + thumb2_arith_shiftsi, thumb2_arith_shiftsi_compare0, + thumb2_arith_shiftsi_compare0_scratch, thumb2_sub_shiftsi, + thumb2_sub_shiftsi_compare0, thumb2_sub_shiftsi_compare0_scratch): + Use const_shift_count predicate for "M" constraints. + * config/arm/predicates.md (const_shift_operand): Remove. + (const_shift_count): New. + + gcc/testsuite/ + * gcc.dg/long-long-shift-1.c: New test. + + 2010-08-26 Paul Brook + + Merge from Sourcery G++ 4.3/4.4: + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2010-08-12 13:35:39 +0000 ++++ new/gcc/config/arm/predicates.md 2010-08-31 09:40:16 +0000 +@@ -318,10 +318,9 @@ + (and (match_code "reg,subreg,mem") + (match_operand 0 "nonimmediate_soft_df_operand")))) + +-(define_predicate "const_shift_operand" ++(define_predicate "const_shift_count" + (and (match_code "const_int") +- (ior (match_operand 0 "power_of_two_operand") +- (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32")))) ++ (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))) + + + (define_special_predicate "load_multiple_operation" + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2010-08-13 16:00:58 +0000 ++++ new/gcc/config/arm/thumb2.md 2010-08-31 09:40:16 +0000 +@@ -55,7 +55,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=r") + (and:SI (not:SI (match_operator:SI 4 "shift_operator" + [(match_operand:SI 2 "s_register_operand" "r") +- (match_operand:SI 3 "const_int_operand" "M")])) ++ (match_operand:SI 3 "const_shift_count" "M")])) + (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_THUMB2" + "bic%?\\t%0, %1, %2%S4" +@@ -124,7 +124,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=r") + (not:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")])))] ++ (match_operand:SI 2 "const_shift_count" "M")])))] + "TARGET_THUMB2" + "mvn%?\\t%0, %1%S3" + [(set_attr "predicable" "yes") +@@ -136,7 +136,7 @@ + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")])) ++ (match_operand:SI 2 "const_shift_count" "M")])) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r") + (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))] +@@ -151,7 +151,7 @@ + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")])) ++ (match_operand:SI 2 "const_shift_count" "M")])) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r"))] + "TARGET_THUMB2" +@@ -328,7 +328,7 @@ + (compare:CC (match_operand:SI 0 "s_register_operand" "r") + (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")])))] ++ (match_operand:SI 2 "const_shift_count" "M")])))] + "TARGET_THUMB2" + "cmp%?\\t%0, %1%S3" + [(set_attr "conds" "set") +@@ -340,7 +340,7 @@ + [(set (reg:CC_SWP CC_REGNUM) + (compare:CC_SWP (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")]) ++ (match_operand:SI 2 "const_shift_count" "M")]) + (match_operand:SI 0 "s_register_operand" "r")))] + "TARGET_THUMB2" + "cmp%?\\t%0, %1%S3" +@@ -354,7 +354,7 @@ + (compare:CC (match_operand:SI 0 "s_register_operand" "r") + (neg:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")]))))] ++ (match_operand:SI 2 "const_shift_count" "M")]))))] + "TARGET_THUMB2" + "cmn%?\\t%0, %1%S3" + [(set_attr "conds" "set") +@@ -466,7 +466,7 @@ + (match_operator:SI 1 "shiftable_operator" + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "const_int_operand" "M")]) ++ (match_operand:SI 5 "const_shift_count" "M")]) + (match_operand:SI 2 "s_register_operand" "r")]))] + "TARGET_THUMB2" + "%i1%?\\t%0, %2, %4%S3" +@@ -499,7 +499,7 @@ + (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "const_int_operand" "M")]) ++ (match_operand:SI 5 "const_shift_count" "M")]) + (match_operand:SI 2 "s_register_operand" "r")]) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r") +@@ -517,7 +517,7 @@ + (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "const_int_operand" "M")]) ++ (match_operand:SI 5 "const_shift_count" "M")]) + (match_operand:SI 2 "s_register_operand" "r")]) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r"))] +@@ -533,7 +533,7 @@ + (minus:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "const_int_operand" "M")])))] ++ (match_operand:SI 4 "const_shift_count" "M")])))] + "TARGET_THUMB2" + "sub%?\\t%0, %1, %3%S2" + [(set_attr "predicable" "yes") +@@ -547,7 +547,7 @@ + (minus:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "const_int_operand" "M")])) ++ (match_operand:SI 4 "const_shift_count" "M")])) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) +@@ -565,7 +565,7 @@ + (minus:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "const_int_operand" "M")])) ++ (match_operand:SI 4 "const_shift_count" "M")])) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r"))] + "TARGET_THUMB2" + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch new file mode 100644 index 0000000000..e1e89bf8af --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch @@ -0,0 +1,2011 @@ +2010-08-29 Chung-Lin Tang + + Backport from mainline: + + 2010-04-16 Bernd Schmidt + + PR target/41514 + gcc/ + * config/arm/arm.md (cbranchsi4_insn): Renamed from "*cbranchsi4_insn". + If the previous insn is a cbranchsi4_insn with the same arguments, + omit the compare instruction. + + gcc/testsuite/ + * gcc.target/arm/thumb-comparisons.c: New test. + + gcc/ + * config/arm/arm.md (addsi3_cbranch): If destination is a high + register, inputs must be low registers and we need a low register + scratch. Handle alternative 2 like alternative 3. + + PR target/40603 + gcc/ + * config/arm/arm.md (cbranchqi4): New pattern. + * config/arm/predicates.md (const0_operand, + cbranchqi4_comparison_operator): New predicates. + + gcc/testsuite/ + * gcc.target/arm/thumb-cbranchqi.c: New test. + + 2010-04-27 Bernd Schmidt + + PR target/40657 + gcc/ + * config/arm/arm.c (thumb1_extra_regs_pushed): New function. + (thumb1_expand_prologue, thumb1_output_function_prologue): Call it + here to determine which regs to push and how much stack to reserve. + + gcc/testsuite/ + * gcc.target/arm/thumb-stackframe.c: New test. + + 2010-07-02 Bernd Schmidt + + PR target/42835 + gcc/ + * config/arm/arm-modes.def (CC_NOTB): New mode. + * config/arm/arm.c (get_arm_condition_code): Handle it. + * config/arm/thumb2.md (thumb2_compare_scc): Delete pattern. + * config/arm/arm.md (subsi3_compare0_c): New pattern. + (compare_scc): Now a define_and_split. Add a number of extra + splitters before it. + + gcc/testsuite/ + * gcc.target/arm/pr42835.c: New test. + + PR target/42172 + gcc/ + * config/arm/arm.c (thumb1_rtx_costs): Improve support for SIGN_EXTEND + and ZERO_EXTEND. + (arm_rtx_costs_1): Likewise. + (arm_size_rtx_costs): Use arm_rtx_costs_1 for these codes. + * config/arm/arm.md (is_arch6): New attribute. + (zero_extendhisi2, zero_extendqisi2, extendhisi2, + extendqisi2): Tighten the code somewhat, avoiding invalid + RTL to occur in the expander patterns. + (thumb1_zero_extendhisi2): Merge with thumb1_zero_extendhisi2_v6. + (thumb1_zero_extendhisi2_v6): Delete. + (thumb1_extendhisi2): Merge with thumb1_extendhisi2_v6. + (thumb1_extendhisi2_v6): Delete. + (thumb1_extendqisi2): Merge with thumb1_extendhisi2_v6. + (thumb1_extendqisi2_v6): Delete. + (zero_extendhisi2 for register input splitter): New. + (zero_extendqisi2 for register input splitter): New. + (thumb1_extendhisi2 for register input splitter): New. + (extendhisi2 for register input splitter): New. + (extendqisi2 for register input splitter): New. + (TARGET_THUMB1 extendqisi2 for memory input splitter): New. + (arm_zero_extendhisi2): Allow nonimmediate_operand for operand 1, + and add support for a register alternative requiring a split. + (thumb1_zero_extendqisi2): Likewise. + (arm_zero_extendqisi2): Likewise. + (arm_extendhisi2): Likewise. + (arm_extendqisi2): Likewise. + + gcc/testsuite/ + * gcc.target/arm/pr42172-1.c: New test. + + 2010-07-05 Bernd Schmidt + + * config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case. + * arm-modes.def (CC_NOTB): Don't define. + * config/arm/arm.md (arm_adddi3): Generate canonical RTL. + (adddi_sesidi_di, adddi_zesidi_di): Likewise. + (LTUGEU): New code_iterator. + (cnb, optab): New corresponding code_attrs. + (addsi3_carryin_): Renamed from addsi3_carryin. Change pattern + to canonical form. Operands 1 and 2 are commutative. Parametrize + using LTUGEU. + (addsi3_carryin_shift_): Likewise. + (addsi3_carryin_alt2_): Renamed from addsi3_carryin_alt2. + Operands 1 and 2 are commutative. Parametrize using LTUGEU. + (addsi3_carryin_alt1, addsi3_carryin_alt3): Remove. + (subsi3_compare): Renamed from subsi3_compare0_c. Change CC_NOTB to + CC. + (arm_subsi3_insn): Allow constants for operand 0. + (compare_scc peephole for eq case): New. + (compare_scc splitters): Change CC_NOTB to CC. + + 2010-07-09 Bernd Schmidt + + PR target/40657 + gcc/ + * config/arm/arm.c (thumb1_extra_regs_pushed): New arg FOR_PROLOGUE. + All callers changed. + Handle the case when we're called for the epilogue. + (thumb_unexpanded_epilogue): Use it. + (thumb1_expand_epilogue): Likewise. + + gcc/testsuite/ + * gcc.target/arm/pr40657-1.c: New test. + * gcc.target/arm/pr40657-2.c: New test. + * gcc.c-torture/execute/pr40657.c: New test. + + gcc/ + * config/arm/arm.md (addsi3_cbranch): Switch alternatives 0 and 1. + + * config/arm/arm.md (Thumb-1 ldrsb peephole): New. + + * config/arm/arm.md (cbranchqi4): Fix array size. + (addsi3_cbranch): Also andle alternative 2 like alternative 3 when + calculating length. + + 2010-08-27 Paul Brook + + gcc/ + +=== modified file 'gcc/config/arm/arm-modes.def' +--- old/gcc/config/arm/arm-modes.def 2010-07-29 16:58:56 +0000 ++++ new/gcc/config/arm/arm-modes.def 2010-08-31 10:00:27 +0000 +@@ -34,6 +34,8 @@ + CCFPmode should be used with floating equalities. + CC_NOOVmode should be used with SImode integer equalities. + CC_Zmode should be used if only the Z flag is set correctly ++ CC_Cmode should be used if only the C flag is set correctly, after an ++ addition. + CC_Nmode should be used if only the N (sign) flag is set correctly + CC_CZmode should be used if only the C and Z flags are correct + (used for DImode unsigned comparisons). + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-25 16:22:17 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-31 10:00:27 +0000 +@@ -6443,6 +6443,7 @@ + thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) + { + enum machine_mode mode = GET_MODE (x); ++ int total; + + switch (code) + { +@@ -6545,24 +6546,20 @@ + return 14; + return 2; + ++ case SIGN_EXTEND: + case ZERO_EXTEND: +- /* XXX still guessing. */ +- switch (GET_MODE (XEXP (x, 0))) +- { +- case QImode: +- return (1 + (mode == DImode ? 4 : 0) +- + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); +- +- case HImode: +- return (4 + (mode == DImode ? 4 : 0) +- + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); +- +- case SImode: +- return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); +- +- default: +- return 99; +- } ++ total = mode == DImode ? COSTS_N_INSNS (1) : 0; ++ total += thumb1_rtx_costs (XEXP (x, 0), GET_CODE (XEXP (x, 0)), code); ++ ++ if (mode == SImode) ++ return total; ++ ++ if (arm_arch6) ++ return total + COSTS_N_INSNS (1); ++ ++ /* Assume a two-shift sequence. Increase the cost slightly so ++ we prefer actual shifts over an extend operation. */ ++ return total + 1 + COSTS_N_INSNS (2); + + default: + return 99; +@@ -7046,44 +7043,39 @@ + return false; + + case SIGN_EXTEND: +- if (GET_MODE_CLASS (mode) == MODE_INT) +- { +- *total = 0; +- if (mode == DImode) +- *total += COSTS_N_INSNS (1); +- +- if (GET_MODE (XEXP (x, 0)) != SImode) +- { +- if (arm_arch6) +- { +- if (GET_CODE (XEXP (x, 0)) != MEM) +- *total += COSTS_N_INSNS (1); +- } +- else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) +- *total += COSTS_N_INSNS (2); +- } +- +- return false; +- } +- +- /* Fall through */ + case ZERO_EXTEND: + *total = 0; + if (GET_MODE_CLASS (mode) == MODE_INT) + { ++ rtx op = XEXP (x, 0); ++ enum machine_mode opmode = GET_MODE (op); ++ + if (mode == DImode) + *total += COSTS_N_INSNS (1); + +- if (GET_MODE (XEXP (x, 0)) != SImode) ++ if (opmode != SImode) + { +- if (arm_arch6) ++ if (MEM_P (op)) + { +- if (GET_CODE (XEXP (x, 0)) != MEM) +- *total += COSTS_N_INSNS (1); ++ /* If !arm_arch4, we use one of the extendhisi2_mem ++ or movhi_bytes patterns for HImode. For a QImode ++ sign extension, we first zero-extend from memory ++ and then perform a shift sequence. */ ++ if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND)) ++ *total += COSTS_N_INSNS (2); + } +- else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) +- *total += COSTS_N_INSNS (GET_MODE (XEXP (x, 0)) == QImode ? +- 1 : 2); ++ else if (arm_arch6) ++ *total += COSTS_N_INSNS (1); ++ ++ /* We don't have the necessary insn, so we need to perform some ++ other operation. */ ++ else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode) ++ /* An and with constant 255. */ ++ *total += COSTS_N_INSNS (1); ++ else ++ /* A shift sequence. Increase costs slightly to avoid ++ combining two shifts into an extend operation. */ ++ *total += COSTS_N_INSNS (2) + 1; + } + + return false; +@@ -7333,41 +7325,8 @@ + return false; + + case SIGN_EXTEND: +- *total = 0; +- if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) +- { +- if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) +- *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); +- } +- if (mode == DImode) +- *total += COSTS_N_INSNS (1); +- return false; +- + case ZERO_EXTEND: +- *total = 0; +- if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) +- { +- switch (GET_MODE (XEXP (x, 0))) +- { +- case QImode: +- *total += COSTS_N_INSNS (1); +- break; +- +- case HImode: +- *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); +- +- case SImode: +- break; +- +- default: +- *total += COSTS_N_INSNS (2); +- } +- } +- +- if (mode == DImode) +- *total += COSTS_N_INSNS (1); +- +- return false; ++ return arm_rtx_costs_1 (x, outer_code, total, 0); + + case CONST_INT: + if (const_ok_for_arm (INTVAL (x))) +@@ -16898,11 +16857,11 @@ + + case CC_Cmode: + switch (comp_code) +- { +- case LTU: return ARM_CS; +- case GEU: return ARM_CC; +- default: gcc_unreachable (); +- } ++ { ++ case LTU: return ARM_CS; ++ case GEU: return ARM_CC; ++ default: gcc_unreachable (); ++ } + + case CC_CZmode: + switch (comp_code) +@@ -20127,6 +20086,81 @@ + #endif + } + ++/* Given the stack offsets and register mask in OFFSETS, decide how ++ many additional registers to push instead of subtracting a constant ++ from SP. For epilogues the principle is the same except we use pop. ++ FOR_PROLOGUE indicates which we're generating. */ ++static int ++thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue) ++{ ++ HOST_WIDE_INT amount; ++ unsigned long live_regs_mask = offsets->saved_regs_mask; ++ /* Extract a mask of the ones we can give to the Thumb's push/pop ++ instruction. */ ++ unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff); ++ /* Then count how many other high registers will need to be pushed. */ ++ unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00); ++ int n_free, reg_base; ++ ++ if (!for_prologue && frame_pointer_needed) ++ amount = offsets->locals_base - offsets->saved_regs; ++ else ++ amount = offsets->outgoing_args - offsets->saved_regs; ++ ++ /* If the stack frame size is 512 exactly, we can save one load ++ instruction, which should make this a win even when optimizing ++ for speed. */ ++ if (!optimize_size && amount != 512) ++ return 0; ++ ++ /* Can't do this if there are high registers to push. */ ++ if (high_regs_pushed != 0) ++ return 0; ++ ++ /* Shouldn't do it in the prologue if no registers would normally ++ be pushed at all. In the epilogue, also allow it if we'll have ++ a pop insn for the PC. */ ++ if (l_mask == 0 ++ && (for_prologue ++ || TARGET_BACKTRACE ++ || (live_regs_mask & 1 << LR_REGNUM) == 0 ++ || TARGET_INTERWORK ++ || crtl->args.pretend_args_size != 0)) ++ return 0; ++ ++ /* Don't do this if thumb_expand_prologue wants to emit instructions ++ between the push and the stack frame allocation. */ ++ if (for_prologue ++ && ((flag_pic && arm_pic_register != INVALID_REGNUM) ++ || (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0))) ++ return 0; ++ ++ reg_base = 0; ++ n_free = 0; ++ if (!for_prologue) ++ { ++ reg_base = arm_size_return_regs () / UNITS_PER_WORD; ++ live_regs_mask >>= reg_base; ++ } ++ ++ while (reg_base + n_free < 8 && !(live_regs_mask & 1) ++ && (for_prologue || call_used_regs[reg_base + n_free])) ++ { ++ live_regs_mask >>= 1; ++ n_free++; ++ } ++ ++ if (n_free == 0) ++ return 0; ++ gcc_assert (amount / 4 * 4 == amount); ++ ++ if (amount >= 512 && (amount - n_free * 4) < 512) ++ return (amount - 508) / 4; ++ if (amount <= n_free * 4) ++ return amount / 4; ++ return 0; ++} ++ + /* The bits which aren't usefully expanded as rtl. */ + const char * + thumb_unexpanded_epilogue (void) +@@ -20135,6 +20169,7 @@ + int regno; + unsigned long live_regs_mask = 0; + int high_regs_pushed = 0; ++ int extra_pop; + int had_to_push_lr; + int size; + +@@ -20154,6 +20189,13 @@ + the register is used to hold a return value. */ + size = arm_size_return_regs (); + ++ extra_pop = thumb1_extra_regs_pushed (offsets, false); ++ if (extra_pop > 0) ++ { ++ unsigned long extra_mask = (1 << extra_pop) - 1; ++ live_regs_mask |= extra_mask << (size / UNITS_PER_WORD); ++ } ++ + /* The prolog may have pushed some high registers to use as + work registers. e.g. the testsuite file: + gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c +@@ -20237,7 +20279,9 @@ + live_regs_mask); + + /* We have either just popped the return address into the +- PC or it is was kept in LR for the entire function. */ ++ PC or it is was kept in LR for the entire function. ++ Note that thumb_pushpop has already called thumb_exit if the ++ PC was in the list. */ + if (!had_to_push_lr) + thumb_exit (asm_out_file, LR_REGNUM); + } +@@ -20419,6 +20463,7 @@ + stack_pointer_rtx); + + amount = offsets->outgoing_args - offsets->saved_regs; ++ amount -= 4 * thumb1_extra_regs_pushed (offsets, true); + if (amount) + { + if (amount < 512) +@@ -20503,6 +20548,7 @@ + emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); + amount = offsets->locals_base - offsets->saved_regs; + } ++ amount -= 4 * thumb1_extra_regs_pushed (offsets, false); + + gcc_assert (amount >= 0); + if (amount) +@@ -20723,7 +20769,11 @@ + register. */ + else if ((l_mask & 0xff) != 0 + || (high_regs_pushed == 0 && l_mask)) +- thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); ++ { ++ unsigned long mask = l_mask; ++ mask |= (1 << thumb1_extra_regs_pushed (offsets, true)) - 1; ++ thumb_pushpop (f, mask, 1, &cfa_offset, mask); ++ } + + if (high_regs_pushed) + { + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-25 16:22:17 +0000 ++++ new/gcc/config/arm/arm.md 2010-08-31 10:00:27 +0000 +@@ -150,6 +150,9 @@ + ; patterns that share the same RTL in both ARM and Thumb code. + (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code"))) + ++; IS_ARCH6 is set to 'yes' when we are generating code form ARMv6. ++(define_attr "is_arch6" "no,yes" (const (symbol_ref "arm_arch6"))) ++ + ;; Operand number of an input operand that is shifted. Zero if the + ;; given instruction does not shift one of its input operands. + (define_attr "shift" "" (const_int 0)) +@@ -515,8 +518,8 @@ + (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) + (match_dup 1))) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) +- (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI (match_dup 4) (match_dup 5))))] ++ (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + " + { + operands[3] = gen_highpart (SImode, operands[0]); +@@ -543,10 +546,10 @@ + (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) + (match_dup 1))) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) +- (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI (ashiftrt:SI (match_dup 2) ++ (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2) + (const_int 31)) +- (match_dup 4))))] ++ (match_dup 4)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + " + { + operands[3] = gen_highpart (SImode, operands[0]); +@@ -572,8 +575,8 @@ + (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) + (match_dup 1))) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) +- (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI (match_dup 4) (const_int 0))))] ++ (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + " + { + operands[3] = gen_highpart (SImode, operands[0]); +@@ -861,24 +864,38 @@ + [(set_attr "conds" "set")] + ) + +-(define_insn "*addsi3_carryin" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI (match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rI"))))] +- "TARGET_32BIT" +- "adc%?\\t%0, %1, %2" +- [(set_attr "conds" "use")] +-) +- +-(define_insn "*addsi3_carryin_shift" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI +- (match_operator:SI 2 "shift_operator" +- [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "reg_or_int_operand" "rM")]) +- (match_operand:SI 1 "s_register_operand" "r"))))] ++(define_code_iterator LTUGEU [ltu geu]) ++(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) ++(define_code_attr optab [(ltu "ltu") (geu "geu")]) ++ ++(define_insn "*addsi3_carryin_" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") ++ (match_operand:SI 2 "arm_rhs_operand" "rI")) ++ (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] ++ "TARGET_32BIT" ++ "adc%?\\t%0, %1, %2" ++ [(set_attr "conds" "use")] ++) ++ ++(define_insn "*addsi3_carryin_alt2_" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (plus:SI (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) ++ (match_operand:SI 1 "s_register_operand" "%r")) ++ (match_operand:SI 2 "arm_rhs_operand" "rI")))] ++ "TARGET_32BIT" ++ "adc%?\\t%0, %1, %2" ++ [(set_attr "conds" "use")] ++) ++ ++(define_insn "*addsi3_carryin_shift_" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (plus:SI (plus:SI ++ (match_operator:SI 2 "shift_operator" ++ [(match_operand:SI 3 "s_register_operand" "r") ++ (match_operand:SI 4 "reg_or_int_operand" "rM")]) ++ (match_operand:SI 1 "s_register_operand" "r")) ++ (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "adc%?\\t%0, %1, %3%S2" + [(set_attr "conds" "use") +@@ -887,36 +904,6 @@ + (const_string "alu_shift_reg")))] + ) + +-(define_insn "*addsi3_carryin_alt1" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rI")) +- (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] +- "TARGET_32BIT" +- "adc%?\\t%0, %1, %2" +- [(set_attr "conds" "use")] +-) +- +-(define_insn "*addsi3_carryin_alt2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (match_operand:SI 1 "s_register_operand" "r")) +- (match_operand:SI 2 "arm_rhs_operand" "rI")))] +- "TARGET_32BIT" +- "adc%?\\t%0, %1, %2" +- [(set_attr "conds" "use")] +-) +- +-(define_insn "*addsi3_carryin_alt3" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (match_operand:SI 2 "arm_rhs_operand" "rI")) +- (match_operand:SI 1 "s_register_operand" "r")))] +- "TARGET_32BIT" +- "adc%?\\t%0, %1, %2" +- [(set_attr "conds" "use")] +-) +- + (define_expand "incscc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (plus:SI (match_operator:SI 2 "arm_comparison_operator" +@@ -1116,24 +1103,27 @@ + + ; ??? Check Thumb-2 split length + (define_insn_and_split "*arm_subsi3_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,rk,r") +- (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,!k,?n") +- (match_operand:SI 2 "s_register_operand" "r, r, r")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r,r") ++ (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,!k,?n,r") ++ (match_operand:SI 2 "reg_or_int_operand" "r,rI, r, r,?n")))] + "TARGET_32BIT" + "@ + rsb%?\\t%0, %2, %1 + sub%?\\t%0, %1, %2 ++ sub%?\\t%0, %1, %2 ++ # + #" +- "TARGET_32BIT +- && GET_CODE (operands[1]) == CONST_INT +- && !const_ok_for_arm (INTVAL (operands[1]))" ++ "&& ((GET_CODE (operands[1]) == CONST_INT ++ && !const_ok_for_arm (INTVAL (operands[1]))) ++ || (GET_CODE (operands[2]) == CONST_INT ++ && !const_ok_for_arm (INTVAL (operands[2]))))" + [(clobber (const_int 0))] + " + arm_split_constant (MINUS, SImode, curr_insn, + INTVAL (operands[1]), operands[0], operands[2], 0); + DONE; + " +- [(set_attr "length" "4,4,16") ++ [(set_attr "length" "4,4,4,16,16") + (set_attr "predicable" "yes")] + ) + +@@ -1165,6 +1155,19 @@ + [(set_attr "conds" "set")] + ) + ++(define_insn "*subsi3_compare" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I") ++ (match_operand:SI 2 "arm_rhs_operand" "rI,r"))) ++ (set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (minus:SI (match_dup 1) (match_dup 2)))] ++ "TARGET_32BIT" ++ "@ ++ sub%.\\t%0, %1, %2 ++ rsb%.\\t%0, %2, %1" ++ [(set_attr "conds" "set")] ++) ++ + (define_expand "decscc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") +@@ -4050,93 +4053,46 @@ + ) + + (define_expand "zero_extendhisi2" +- [(set (match_dup 2) +- (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") +- (const_int 16))) +- (set (match_operand:SI 0 "s_register_operand" "") +- (lshiftrt:SI (match_dup 2) (const_int 16)))] ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] + "TARGET_EITHER" +- " +- { +- if ((TARGET_THUMB1 || arm_arch4) && GET_CODE (operands[1]) == MEM) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_ZERO_EXTEND (SImode, operands[1]))); +- DONE; +- } +- +- if (TARGET_ARM && GET_CODE (operands[1]) == MEM) +- { +- emit_insn (gen_movhi_bytes (operands[0], operands[1])); +- DONE; +- } +- +- if (!s_register_operand (operands[1], HImode)) +- operands[1] = copy_to_mode_reg (HImode, operands[1]); +- +- if (arm_arch6) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_ZERO_EXTEND (SImode, operands[1]))); +- DONE; +- } +- +- operands[1] = gen_lowpart (SImode, operands[1]); +- operands[2] = gen_reg_rtx (SImode); +- }" +-) ++{ ++ if (TARGET_ARM && !arm_arch4 && MEM_P (operands[1])) ++ { ++ emit_insn (gen_movhi_bytes (operands[0], operands[1])); ++ DONE; ++ } ++ if (!arm_arch6 && !MEM_P (operands[1])) ++ { ++ rtx t = gen_lowpart (SImode, operands[1]); ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16))); ++ emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (16))); ++ DONE; ++ } ++}) ++ ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (zero_extend:SI (match_operand:HI 1 "register_operand" "l,m")))] ++ "!TARGET_THUMB2 && !arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] ++{ ++ operands[2] = gen_lowpart (SImode, operands[1]); ++}) + + (define_insn "*thumb1_zero_extendhisi2" +- [(set (match_operand:SI 0 "register_operand" "=l") +- (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] +- "TARGET_THUMB1 && !arm_arch6" +- "* +- rtx mem = XEXP (operands[1], 0); +- +- if (GET_CODE (mem) == CONST) +- mem = XEXP (mem, 0); +- +- if (GET_CODE (mem) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (GET_CODE (mem) == PLUS) +- { +- rtx a = XEXP (mem, 0); +- rtx b = XEXP (mem, 1); +- +- /* This can happen due to bugs in reload. */ +- if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM) +- { +- rtx ops[2]; +- ops[0] = operands[0]; +- ops[1] = a; +- +- output_asm_insn (\"mov %0, %1\", ops); +- +- XEXP (mem, 0) = operands[0]; +- } +- +- else if ( GET_CODE (a) == LABEL_REF +- && GET_CODE (b) == CONST_INT) +- return \"ldr\\t%0, %1\"; +- } +- +- return \"ldrh\\t%0, %1\"; +- " +- [(set_attr "length" "4") +- (set_attr "type" "load_byte") +- (set_attr "pool_range" "60")] +-) +- +-(define_insn "*thumb1_zero_extendhisi2_v6" + [(set (match_operand:SI 0 "register_operand" "=l,l") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))] +- "TARGET_THUMB1 && arm_arch6" ++ "TARGET_THUMB1" + "* + rtx mem; + +- if (which_alternative == 0) ++ if (which_alternative == 0 && arm_arch6) + return \"uxth\\t%0, %1\"; ++ if (which_alternative == 0) ++ return \"#\"; + + mem = XEXP (operands[1], 0); + +@@ -4170,20 +4126,25 @@ + + return \"ldrh\\t%0, %1\"; + " +- [(set_attr "length" "2,4") ++ [(set_attr_alternative "length" ++ [(if_then_else (eq_attr "is_arch6" "yes") ++ (const_int 2) (const_int 4)) ++ (const_int 4)]) + (set_attr "type" "alu_shift,load_byte") + (set_attr "pool_range" "*,60")] + ) + + (define_insn "*arm_zero_extendhisi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + "TARGET_ARM && arm_arch4 && !arm_arch6" +- "ldr%(h%)\\t%0, %1" +- [(set_attr "type" "load_byte") ++ "@ ++ # ++ ldr%(h%)\\t%0, %1" ++ [(set_attr "type" "alu_shift,load_byte") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "256") +- (set_attr "neg_pool_range" "244")] ++ (set_attr "pool_range" "*,256") ++ (set_attr "neg_pool_range" "*,244")] + ) + + (define_insn "*arm_zero_extendhisi2_v6" +@@ -4213,50 +4174,49 @@ + [(set (match_operand:SI 0 "s_register_operand" "") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] + "TARGET_EITHER" +- " +- if (!arm_arch6 && GET_CODE (operands[1]) != MEM) +- { +- if (TARGET_ARM) +- { +- emit_insn (gen_andsi3 (operands[0], +- gen_lowpart (SImode, operands[1]), +- GEN_INT (255))); +- } +- else /* TARGET_THUMB */ +- { +- rtx temp = gen_reg_rtx (SImode); +- rtx ops[3]; +- +- operands[1] = copy_to_mode_reg (QImode, operands[1]); +- operands[1] = gen_lowpart (SImode, operands[1]); +- +- ops[0] = temp; +- ops[1] = operands[1]; +- ops[2] = GEN_INT (24); +- +- emit_insn (gen_rtx_SET (VOIDmode, ops[0], +- gen_rtx_ASHIFT (SImode, ops[1], ops[2]))); +- +- ops[0] = operands[0]; +- ops[1] = temp; +- ops[2] = GEN_INT (24); +- +- emit_insn (gen_rtx_SET (VOIDmode, ops[0], +- gen_rtx_LSHIFTRT (SImode, ops[1], ops[2]))); +- } +- DONE; +- } +- " +-) ++{ ++ if (TARGET_ARM && !arm_arch6 && GET_CODE (operands[1]) != MEM) ++ { ++ emit_insn (gen_andsi3 (operands[0], ++ gen_lowpart (SImode, operands[1]), ++ GEN_INT (255))); ++ DONE; ++ } ++ if (!arm_arch6 && !MEM_P (operands[1])) ++ { ++ rtx t = gen_lowpart (SImode, operands[1]); ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24))); ++ emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (24))); ++ DONE; ++ } ++}) ++ ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] ++ "!arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] ++{ ++ operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0); ++ if (TARGET_ARM) ++ { ++ emit_insn (gen_andsi3 (operands[0], operands[2], GEN_INT (255))); ++ DONE; ++ } ++}) + + (define_insn "*thumb1_zero_extendqisi2" +- [(set (match_operand:SI 0 "register_operand" "=l") +- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] ++ [(set (match_operand:SI 0 "register_operand" "=l,l") ++ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,m")))] + "TARGET_THUMB1 && !arm_arch6" +- "ldrb\\t%0, %1" +- [(set_attr "length" "2") +- (set_attr "type" "load_byte") +- (set_attr "pool_range" "32")] ++ "@ ++ # ++ ldrb\\t%0, %1" ++ [(set_attr "length" "4,2") ++ (set_attr "type" "alu_shift,load_byte") ++ (set_attr "pool_range" "*,32")] + ) + + (define_insn "*thumb1_zero_extendqisi2_v6" +@@ -4272,14 +4232,17 @@ + ) + + (define_insn "*arm_zero_extendqisi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] + "TARGET_ARM && !arm_arch6" +- "ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" +- [(set_attr "type" "load_byte") ++ "@ ++ # ++ ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" ++ [(set_attr "length" "8,4") ++ (set_attr "type" "alu_shift,load_byte") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "4096") +- (set_attr "neg_pool_range" "4084")] ++ (set_attr "pool_range" "*,4096") ++ (set_attr "neg_pool_range" "*,4084")] + ) + + (define_insn "*arm_zero_extendqisi2_v6" +@@ -4358,108 +4321,42 @@ + ) + + (define_expand "extendhisi2" +- [(set (match_dup 2) +- (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") +- (const_int 16))) +- (set (match_operand:SI 0 "s_register_operand" "") +- (ashiftrt:SI (match_dup 2) +- (const_int 16)))] ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] + "TARGET_EITHER" +- " +- { +- if (GET_CODE (operands[1]) == MEM) +- { +- if (TARGET_THUMB1) +- { +- emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); +- DONE; +- } +- else if (arm_arch4) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_SIGN_EXTEND (SImode, operands[1]))); +- DONE; +- } +- } +- +- if (TARGET_ARM && GET_CODE (operands[1]) == MEM) +- { +- emit_insn (gen_extendhisi2_mem (operands[0], operands[1])); +- DONE; +- } +- +- if (!s_register_operand (operands[1], HImode)) +- operands[1] = copy_to_mode_reg (HImode, operands[1]); +- +- if (arm_arch6) +- { +- if (TARGET_THUMB1) +- emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); +- else +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_SIGN_EXTEND (SImode, operands[1]))); +- +- DONE; +- } +- +- operands[1] = gen_lowpart (SImode, operands[1]); +- operands[2] = gen_reg_rtx (SImode); +- }" +-) +- +-(define_insn "thumb1_extendhisi2" +- [(set (match_operand:SI 0 "register_operand" "=l") +- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))) +- (clobber (match_scratch:SI 2 "=&l"))] +- "TARGET_THUMB1 && !arm_arch6" +- "* +- { +- rtx ops[4]; +- rtx mem = XEXP (operands[1], 0); +- +- /* This code used to try to use 'V', and fix the address only if it was +- offsettable, but this fails for e.g. REG+48 because 48 is outside the +- range of QImode offsets, and offsettable_address_p does a QImode +- address check. */ +- +- if (GET_CODE (mem) == CONST) +- mem = XEXP (mem, 0); +- +- if (GET_CODE (mem) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (GET_CODE (mem) == PLUS) +- { +- rtx a = XEXP (mem, 0); +- rtx b = XEXP (mem, 1); +- +- if (GET_CODE (a) == LABEL_REF +- && GET_CODE (b) == CONST_INT) +- return \"ldr\\t%0, %1\"; +- +- if (GET_CODE (b) == REG) +- return \"ldrsh\\t%0, %1\"; +- +- ops[1] = a; +- ops[2] = b; +- } +- else +- { +- ops[1] = mem; +- ops[2] = const0_rtx; +- } +- +- gcc_assert (GET_CODE (ops[1]) == REG); +- +- ops[0] = operands[0]; +- ops[3] = operands[2]; +- output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops); +- return \"\"; +- }" +- [(set_attr "length" "4") +- (set_attr "type" "load_byte") +- (set_attr "pool_range" "1020")] +-) ++{ ++ if (TARGET_THUMB1) ++ { ++ emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); ++ DONE; ++ } ++ if (MEM_P (operands[1]) && TARGET_ARM && !arm_arch4) ++ { ++ emit_insn (gen_extendhisi2_mem (operands[0], operands[1])); ++ DONE; ++ } ++ ++ if (!arm_arch6 && !MEM_P (operands[1])) ++ { ++ rtx t = gen_lowpart (SImode, operands[1]); ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16))); ++ emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (16))); ++ DONE; ++ } ++}) ++ ++(define_split ++ [(parallel ++ [(set (match_operand:SI 0 "register_operand" "") ++ (sign_extend:SI (match_operand:HI 1 "register_operand" ""))) ++ (clobber (match_scratch:SI 2 ""))])] ++ "!arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) ++ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))] ++{ ++ operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0); ++}) + + ;; We used to have an early-clobber on the scratch register here. + ;; However, there's a bug somewhere in reload which means that this +@@ -4468,16 +4365,18 @@ + ;; we try to verify the operands. Fortunately, we don't really need + ;; the early-clobber: we can always use operand 0 if operand 2 + ;; overlaps the address. +-(define_insn "*thumb1_extendhisi2_insn_v6" ++(define_insn "thumb1_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=l,l") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m"))) + (clobber (match_scratch:SI 2 "=X,l"))] +- "TARGET_THUMB1 && arm_arch6" ++ "TARGET_THUMB1" + "* + { + rtx ops[4]; + rtx mem; + ++ if (which_alternative == 0 && !arm_arch6) ++ return \"#\"; + if (which_alternative == 0) + return \"sxth\\t%0, %1\"; + +@@ -4525,7 +4424,10 @@ + output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops); + return \"\"; + }" +- [(set_attr "length" "2,4") ++ [(set_attr_alternative "length" ++ [(if_then_else (eq_attr "is_arch6" "yes") ++ (const_int 2) (const_int 4)) ++ (const_int 4)]) + (set_attr "type" "alu_shift,load_byte") + (set_attr "pool_range" "*,1020")] + ) +@@ -4566,15 +4468,28 @@ + }" + ) + ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] ++ "!arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) ++ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))] ++{ ++ operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0); ++}) ++ + (define_insn "*arm_extendhisi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + "TARGET_ARM && arm_arch4 && !arm_arch6" +- "ldr%(sh%)\\t%0, %1" +- [(set_attr "type" "load_byte") ++ "@ ++ # ++ ldr%(sh%)\\t%0, %1" ++ [(set_attr "length" "8,4") ++ (set_attr "type" "alu_shift,load_byte") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "256") +- (set_attr "neg_pool_range" "244")] ++ (set_attr "pool_range" "*,256") ++ (set_attr "neg_pool_range" "*,244")] + ) + + ;; ??? Check Thumb-2 pool range +@@ -4636,46 +4551,45 @@ + ) + + (define_expand "extendqisi2" +- [(set (match_dup 2) +- (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "") +- (const_int 24))) +- (set (match_operand:SI 0 "s_register_operand" "") +- (ashiftrt:SI (match_dup 2) +- (const_int 24)))] ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")))] + "TARGET_EITHER" +- " +- { +- if ((TARGET_THUMB || arm_arch4) && GET_CODE (operands[1]) == MEM) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_SIGN_EXTEND (SImode, operands[1]))); +- DONE; +- } +- +- if (!s_register_operand (operands[1], QImode)) +- operands[1] = copy_to_mode_reg (QImode, operands[1]); +- +- if (arm_arch6) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_SIGN_EXTEND (SImode, operands[1]))); +- DONE; +- } +- +- operands[1] = gen_lowpart (SImode, operands[1]); +- operands[2] = gen_reg_rtx (SImode); +- }" +-) ++{ ++ if (!arm_arch4 && MEM_P (operands[1])) ++ operands[1] = copy_to_mode_reg (QImode, operands[1]); ++ ++ if (!arm_arch6 && !MEM_P (operands[1])) ++ { ++ rtx t = gen_lowpart (SImode, operands[1]); ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24))); ++ emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (24))); ++ DONE; ++ } ++}) ++ ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] ++ "!arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) ++ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))] ++{ ++ operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0); ++}) + + (define_insn "*arm_extendqisi" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))] + "TARGET_ARM && arm_arch4 && !arm_arch6" +- "ldr%(sb%)\\t%0, %1" +- [(set_attr "type" "load_byte") ++ "@ ++ # ++ ldr%(sb%)\\t%0, %1" ++ [(set_attr "length" "8,4") ++ (set_attr "type" "alu_shift,load_byte") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "256") +- (set_attr "neg_pool_range" "244")] ++ (set_attr "pool_range" "*,256") ++ (set_attr "neg_pool_range" "*,244")] + ) + + (define_insn "*arm_extendqisi_v6" +@@ -4703,162 +4617,103 @@ + (set_attr "predicable" "yes")] + ) + +-(define_insn "*thumb1_extendqisi2" +- [(set (match_operand:SI 0 "register_operand" "=l,l") +- (sign_extend:SI (match_operand:QI 1 "memory_operand" "V,m")))] +- "TARGET_THUMB1 && !arm_arch6" +- "* +- { +- rtx ops[3]; +- rtx mem = XEXP (operands[1], 0); +- +- if (GET_CODE (mem) == CONST) +- mem = XEXP (mem, 0); +- +- if (GET_CODE (mem) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (GET_CODE (mem) == PLUS +- && GET_CODE (XEXP (mem, 0)) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (which_alternative == 0) +- return \"ldrsb\\t%0, %1\"; +- +- ops[0] = operands[0]; +- +- if (GET_CODE (mem) == PLUS) +- { +- rtx a = XEXP (mem, 0); +- rtx b = XEXP (mem, 1); +- +- ops[1] = a; +- ops[2] = b; +- +- if (GET_CODE (a) == REG) +- { +- if (GET_CODE (b) == REG) +- output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops); +- else if (REGNO (a) == REGNO (ops[0])) +- { +- output_asm_insn (\"ldrb\\t%0, [%1, %2]\", ops); +- output_asm_insn (\"lsl\\t%0, %0, #24\", ops); +- output_asm_insn (\"asr\\t%0, %0, #24\", ops); +- } +- else +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- else +- { +- gcc_assert (GET_CODE (b) == REG); +- if (REGNO (b) == REGNO (ops[0])) +- { +- output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops); +- output_asm_insn (\"lsl\\t%0, %0, #24\", ops); +- output_asm_insn (\"asr\\t%0, %0, #24\", ops); +- } +- else +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- } +- else if (GET_CODE (mem) == REG && REGNO (ops[0]) == REGNO (mem)) +- { +- output_asm_insn (\"ldrb\\t%0, [%0, #0]\", ops); +- output_asm_insn (\"lsl\\t%0, %0, #24\", ops); +- output_asm_insn (\"asr\\t%0, %0, #24\", ops); +- } +- else +- { +- ops[1] = mem; +- ops[2] = const0_rtx; +- +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- return \"\"; +- }" +- [(set_attr "length" "2,6") +- (set_attr "type" "load_byte,load_byte") +- (set_attr "pool_range" "32,32")] +-) +- +-(define_insn "*thumb1_extendqisi2_v6" ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (sign_extend:SI (match_operand:QI 1 "memory_operand" "")))] ++ "TARGET_THUMB1 && reload_completed" ++ [(set (match_dup 0) (match_dup 2)) ++ (set (match_dup 0) (sign_extend:SI (match_dup 3)))] ++{ ++ rtx addr = XEXP (operands[1], 0); ++ ++ if (GET_CODE (addr) == CONST) ++ addr = XEXP (addr, 0); ++ ++ if (GET_CODE (addr) == PLUS ++ && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1))) ++ /* No split necessary. */ ++ FAIL; ++ ++ if (GET_CODE (addr) == PLUS ++ && !REG_P (XEXP (addr, 0)) && !REG_P (XEXP (addr, 1))) ++ FAIL; ++ ++ if (reg_overlap_mentioned_p (operands[0], addr)) ++ { ++ rtx t = gen_lowpart (QImode, operands[0]); ++ emit_move_insn (t, operands[1]); ++ emit_insn (gen_thumb1_extendqisi2 (operands[0], t)); ++ DONE; ++ } ++ ++ if (REG_P (addr)) ++ { ++ addr = gen_rtx_PLUS (Pmode, addr, operands[0]); ++ operands[2] = const0_rtx; ++ } ++ else if (GET_CODE (addr) != PLUS) ++ FAIL; ++ else if (REG_P (XEXP (addr, 0))) ++ { ++ operands[2] = XEXP (addr, 1); ++ addr = gen_rtx_PLUS (Pmode, XEXP (addr, 0), operands[0]); ++ } ++ else ++ { ++ operands[2] = XEXP (addr, 0); ++ addr = gen_rtx_PLUS (Pmode, XEXP (addr, 1), operands[0]); ++ } ++ ++ operands[3] = change_address (operands[1], QImode, addr); ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "register_operand" "") ++ (plus:SI (match_dup 0) (match_operand 1 "const_int_operand"))) ++ (set (match_operand:SI 2 "register_operand" "") (const_int 0)) ++ (set (match_operand:SI 3 "register_operand" "") ++ (sign_extend:SI (match_operand:QI 4 "memory_operand" "")))] ++ "TARGET_THUMB1 ++ && GET_CODE (XEXP (operands[4], 0)) == PLUS ++ && rtx_equal_p (operands[0], XEXP (XEXP (operands[4], 0), 0)) ++ && rtx_equal_p (operands[2], XEXP (XEXP (operands[4], 0), 1)) ++ && (peep2_reg_dead_p (3, operands[0]) ++ || rtx_equal_p (operands[0], operands[3])) ++ && (peep2_reg_dead_p (3, operands[2]) ++ || rtx_equal_p (operands[2], operands[3]))" ++ [(set (match_dup 2) (match_dup 1)) ++ (set (match_dup 3) (sign_extend:SI (match_dup 4)))] ++{ ++ rtx addr = gen_rtx_PLUS (Pmode, operands[0], operands[2]); ++ operands[4] = change_address (operands[4], QImode, addr); ++}) ++ ++(define_insn "thumb1_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=l,l,l") + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))] +- "TARGET_THUMB1 && arm_arch6" +- "* +- { +- rtx ops[3]; +- rtx mem; +- +- if (which_alternative == 0) +- return \"sxtb\\t%0, %1\"; +- +- mem = XEXP (operands[1], 0); +- +- if (GET_CODE (mem) == CONST) +- mem = XEXP (mem, 0); +- +- if (GET_CODE (mem) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (GET_CODE (mem) == PLUS +- && GET_CODE (XEXP (mem, 0)) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (which_alternative == 0) +- return \"ldrsb\\t%0, %1\"; +- +- ops[0] = operands[0]; +- +- if (GET_CODE (mem) == PLUS) +- { +- rtx a = XEXP (mem, 0); +- rtx b = XEXP (mem, 1); +- +- ops[1] = a; +- ops[2] = b; +- +- if (GET_CODE (a) == REG) +- { +- if (GET_CODE (b) == REG) +- output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops); +- else if (REGNO (a) == REGNO (ops[0])) +- { +- output_asm_insn (\"ldrb\\t%0, [%1, %2]\", ops); +- output_asm_insn (\"sxtb\\t%0, %0\", ops); +- } +- else +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- else +- { +- gcc_assert (GET_CODE (b) == REG); +- if (REGNO (b) == REGNO (ops[0])) +- { +- output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops); +- output_asm_insn (\"sxtb\\t%0, %0\", ops); +- } +- else +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- } +- else if (GET_CODE (mem) == REG && REGNO (ops[0]) == REGNO (mem)) +- { +- output_asm_insn (\"ldrb\\t%0, [%0, #0]\", ops); +- output_asm_insn (\"sxtb\\t%0, %0\", ops); +- } +- else +- { +- ops[1] = mem; +- ops[2] = const0_rtx; +- +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- return \"\"; +- }" +- [(set_attr "length" "2,2,4") +- (set_attr "type" "alu_shift,load_byte,load_byte") +- (set_attr "pool_range" "*,32,32")] ++ "TARGET_THUMB1" ++{ ++ rtx addr; ++ ++ if (which_alternative == 0 && arm_arch6) ++ return "sxtb\\t%0, %1"; ++ if (which_alternative == 0) ++ return "#"; ++ ++ addr = XEXP (operands[1], 0); ++ if (GET_CODE (addr) == PLUS ++ && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1))) ++ return "ldrsb\\t%0, %1"; ++ ++ return "#"; ++} ++ [(set_attr_alternative "length" ++ [(if_then_else (eq_attr "is_arch6" "yes") ++ (const_int 2) (const_int 4)) ++ (const_int 2) ++ (if_then_else (eq_attr "is_arch6" "yes") ++ (const_int 4) (const_int 6))]) ++ (set_attr "type" "alu_shift,load_byte,load_byte")] + ) + + (define_expand "extendsfdf2" +@@ -6784,6 +6639,30 @@ + operands[2] = force_reg (SImode, operands[2]); + ") + ++;; A pattern to recognize a special situation and optimize for it. ++;; On the thumb, zero-extension from memory is preferrable to sign-extension ++;; due to the available addressing modes. Hence, convert a signed comparison ++;; with zero into an unsigned comparison with 127 if possible. ++(define_expand "cbranchqi4" ++ [(set (pc) (if_then_else ++ (match_operator 0 "lt_ge_comparison_operator" ++ [(match_operand:QI 1 "memory_operand" "") ++ (match_operand:QI 2 "const0_operand" "")]) ++ (label_ref (match_operand 3 "" "")) ++ (pc)))] ++ "TARGET_THUMB1" ++{ ++ rtx xops[4]; ++ xops[1] = gen_reg_rtx (SImode); ++ emit_insn (gen_zero_extendqisi2 (xops[1], operands[1])); ++ xops[2] = GEN_INT (127); ++ xops[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]) == GE ? LEU : GTU, ++ VOIDmode, xops[1], xops[2]); ++ xops[3] = operands[3]; ++ emit_insn (gen_cbranchsi4 (xops[0], xops[1], xops[2], xops[3])); ++ DONE; ++}) ++ + (define_expand "cbranchsf4" + [(set (pc) (if_then_else + (match_operator 0 "arm_comparison_operator" +@@ -6849,7 +6728,7 @@ + }" + ) + +-(define_insn "*cbranchsi4_insn" ++(define_insn "cbranchsi4_insn" + [(set (pc) (if_then_else + (match_operator 0 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "l,*h") +@@ -6858,7 +6737,20 @@ + (pc)))] + "TARGET_THUMB1" + "* +- output_asm_insn (\"cmp\\t%1, %2\", operands); ++ rtx t = prev_nonnote_insn (insn); ++ if (t != NULL_RTX ++ && INSN_P (t) ++ && INSN_CODE (t) == CODE_FOR_cbranchsi4_insn) ++ { ++ t = XEXP (SET_SRC (PATTERN (t)), 0); ++ if (!rtx_equal_p (XEXP (t, 0), operands[1]) ++ || !rtx_equal_p (XEXP (t, 1), operands[2])) ++ t = NULL_RTX; ++ } ++ else ++ t = NULL_RTX; ++ if (t == NULL_RTX) ++ output_asm_insn (\"cmp\\t%1, %2\", operands); + + switch (get_attr_length (insn)) + { +@@ -7674,15 +7566,15 @@ + (if_then_else + (match_operator 4 "arm_comparison_operator" + [(plus:SI +- (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1") +- (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ")) ++ (match_operand:SI 2 "s_register_operand" "%0,l,*l,1,1,1") ++ (match_operand:SI 3 "reg_or_int_operand" "IJ,lL,*l,lIJ,lIJ,lIJ")) + (const_int 0)]) + (label_ref (match_operand 5 "" "")) + (pc))) + (set + (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m") + (plus:SI (match_dup 2) (match_dup 3))) +- (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))] ++ (clobber (match_scratch:SI 1 "=X,X,l,l,&l,&l"))] + "TARGET_THUMB1 + && (GET_CODE (operands[4]) == EQ + || GET_CODE (operands[4]) == NE +@@ -7692,8 +7584,7 @@ + { + rtx cond[3]; + +- +- cond[0] = (which_alternative < 3) ? operands[0] : operands[1]; ++ cond[0] = (which_alternative < 2) ? operands[0] : operands[1]; + cond[1] = operands[2]; + cond[2] = operands[3]; + +@@ -7702,13 +7593,13 @@ + else + output_asm_insn (\"add\\t%0, %1, %2\", cond); + +- if (which_alternative >= 3 ++ if (which_alternative >= 2 + && which_alternative < 4) + output_asm_insn (\"mov\\t%0, %1\", operands); + else if (which_alternative >= 4) + output_asm_insn (\"str\\t%1, %0\", operands); + +- switch (get_attr_length (insn) - ((which_alternative >= 3) ? 2 : 0)) ++ switch (get_attr_length (insn) - ((which_alternative >= 2) ? 2 : 0)) + { + case 4: + return \"b%d4\\t%l5\"; +@@ -7722,7 +7613,7 @@ + [(set (attr "far_jump") + (if_then_else + (ior (and (lt (symbol_ref ("which_alternative")) +- (const_int 3)) ++ (const_int 2)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") +@@ -7730,7 +7621,7 @@ + (set (attr "length") + (if_then_else + (lt (symbol_ref ("which_alternative")) +- (const_int 3)) ++ (const_int 2)) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -250)) + (le (minus (match_dup 5) (pc)) (const_int 256))) +@@ -9483,41 +9374,117 @@ + (set_attr "length" "4,8")] + ) + +-(define_insn "*compare_scc" ++; A series of splitters for the compare_scc pattern below. Note that ++; order is important. ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (lt:SI (match_operand:SI 1 "s_register_operand" "") ++ (const_int 0))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 31)))]) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (ge:SI (match_operand:SI 1 "s_register_operand" "") ++ (const_int 0))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(set (match_dup 0) (not:SI (match_dup 1))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))]) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (eq:SI (match_operand:SI 1 "s_register_operand" "") ++ (const_int 0))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(parallel ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (const_int 1) (match_dup 1))) ++ (set (match_dup 0) ++ (minus:SI (const_int 1) (match_dup 1)))]) ++ (cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 0)))]) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (ne:SI (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 2 "const_int_operand" ""))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(parallel ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))]) ++ (cond_exec (ne:CC (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1)))] ++{ ++ operands[3] = GEN_INT (-INTVAL (operands[2])); ++}) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (ne:SI (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 2 "arm_add_operand" ""))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(parallel ++ [(set (reg:CC_NOOV CC_REGNUM) ++ (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2)) ++ (const_int 0))) ++ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) ++ (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1)))]) ++ ++(define_insn_and_split "*compare_scc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (match_operator:SI 1 "arm_comparison_operator" + [(match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "arm_add_operand" "rI,L")])) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- if (operands[3] == const0_rtx) +- { +- if (GET_CODE (operands[1]) == LT) +- return \"mov\\t%0, %2, lsr #31\"; +- +- if (GET_CODE (operands[1]) == GE) +- return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\"; +- +- if (GET_CODE (operands[1]) == EQ) +- return \"rsbs\\t%0, %2, #1\;movcc\\t%0, #0\"; +- } +- +- if (GET_CODE (operands[1]) == NE) +- { +- if (which_alternative == 1) +- return \"adds\\t%0, %2, #%n3\;movne\\t%0, #1\"; +- return \"subs\\t%0, %2, %3\;movne\\t%0, #1\"; +- } +- if (which_alternative == 1) +- output_asm_insn (\"cmn\\t%2, #%n3\", operands); +- else +- output_asm_insn (\"cmp\\t%2, %3\", operands); +- return \"mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) ++ "TARGET_32BIT" ++ "#" ++ "&& reload_completed" ++ [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 3))) ++ (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0))) ++ (cond_exec (match_dup 5) (set (match_dup 0) (const_int 1)))] ++{ ++ rtx tmp1; ++ enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), ++ operands[2], operands[3]); ++ enum rtx_code rc = GET_CODE (operands[1]); ++ ++ tmp1 = gen_rtx_REG (mode, CC_REGNUM); ++ ++ operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rc = reverse_condition_maybe_unordered (rc); ++ else ++ rc = reverse_condition (rc); ++ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); ++}) ++ ++;; Attempt to improve the sequence generated by the compare_scc splitters ++;; not to use conditional execution. ++(define_peephole2 ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "register_operand" "") ++ (match_operand:SI 2 "arm_rhs_operand" ""))) ++ (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "") (const_int 0))) ++ (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1))) ++ (match_scratch:SI 3 "r")] ++ "TARGET_32BIT" ++ [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) ++ (parallel ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (const_int 0) (match_dup 3))) ++ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))]) ++ (set (match_dup 0) ++ (plus:SI (plus:SI (match_dup 0) (match_dup 3)) ++ (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]) + + (define_insn "*cond_move" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2010-08-31 09:40:16 +0000 ++++ new/gcc/config/arm/predicates.md 2010-08-31 10:00:27 +0000 +@@ -115,6 +115,10 @@ + (and (match_code "const_int") + (match_test "const_ok_for_arm (~INTVAL (op))"))) + ++(define_predicate "const0_operand" ++ (and (match_code "const_int") ++ (match_test "INTVAL (op) == 0"))) ++ + ;; Something valid on the RHS of an ARM data-processing instruction + (define_predicate "arm_rhs_operand" + (ior (match_operand 0 "s_register_operand") +@@ -233,6 +237,9 @@ + && (TARGET_FPA || TARGET_VFP)") + (match_code "unordered,ordered,unlt,unle,unge,ungt")))) + ++(define_special_predicate "lt_ge_comparison_operator" ++ (match_code "lt,ge")) ++ + (define_special_predicate "minmax_operator" + (and (match_code "smin,smax,umin,umax") + (match_test "mode == GET_MODE (op)"))) + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2010-08-31 09:40:16 +0000 ++++ new/gcc/config/arm/thumb2.md 2010-08-31 10:00:27 +0000 +@@ -599,42 +599,6 @@ + (set_attr "length" "6,10")] + ) + +-(define_insn "*thumb2_compare_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,L")])) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_THUMB2" +- "* +- if (operands[3] == const0_rtx) +- { +- if (GET_CODE (operands[1]) == LT) +- return \"lsr\\t%0, %2, #31\"; +- +- if (GET_CODE (operands[1]) == GE) +- return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\"; +- +- if (GET_CODE (operands[1]) == EQ) +- return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\"; +- } +- +- if (GET_CODE (operands[1]) == NE) +- { +- if (which_alternative == 1) +- return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\"; +- return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\"; +- } +- if (which_alternative == 1) +- output_asm_insn (\"cmn\\t%2, #%n3\", operands); +- else +- output_asm_insn (\"cmp\\t%2, %3\", operands); +- return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "14")] +-) +- + (define_insn "*thumb2_cond_move" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (if_then_else:SI (match_operator 3 "equality_operator" + +=== added file 'gcc/testsuite/gcc.c-torture/execute/pr40657.c' +--- old/gcc/testsuite/gcc.c-torture/execute/pr40657.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.c-torture/execute/pr40657.c 2010-08-31 10:00:27 +0000 +@@ -0,0 +1,23 @@ ++/* Verify that that Thumb-1 epilogue size optimization does not clobber the ++ return value. */ ++ ++long long v = 0x123456789abc; ++ ++__attribute__((noinline)) void bar (int *x) ++{ ++ asm volatile ("" : "=m" (x) ::); ++} ++ ++__attribute__((noinline)) long long foo() ++{ ++ int x; ++ bar(&x); ++ return v; ++} ++ ++int main () ++{ ++ if (foo () != v) ++ abort (); ++ exit (0); ++} + +=== added file 'gcc/testsuite/gcc.target/arm/pr40657-1.c' +--- old/gcc/testsuite/gcc.target/arm/pr40657-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr40657-1.c 2010-08-31 10:00:27 +0000 +@@ -0,0 +1,13 @@ ++/* { dg-options "-Os -march=armv5te -mthumb" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler "pop.*r1.*pc" } } */ ++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ ++/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ ++ ++extern void bar(int*); ++int foo() ++{ ++ int x; ++ bar(&x); ++ return x; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/pr40657-2.c' +--- old/gcc/testsuite/gcc.target/arm/pr40657-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr40657-2.c 2010-08-31 10:00:27 +0000 +@@ -0,0 +1,20 @@ ++/* { dg-options "-Os -march=armv4t -mthumb" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ ++/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ ++ ++/* Here, we test that if there's a pop of r[4567] in the epilogue, ++ add sp,sp,#12 is removed and replaced by three additional pops ++ of lower-numbered regs. */ ++ ++extern void bar(int*); ++ ++int t1, t2, t3, t4, t5; ++int foo() ++{ ++ int i,j,k,x = 0; ++ for (i = 0; i < t1; i++) ++ for (j = 0; j < t2; j++) ++ bar(&x); ++ return x; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/pr42172-1.c' +--- old/gcc/testsuite/gcc.target/arm/pr42172-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr42172-1.c 2010-08-31 10:00:27 +0000 +@@ -0,0 +1,19 @@ ++/* { dg-options "-O2" } */ ++ ++struct A { ++ unsigned int f1 : 3; ++ unsigned int f2 : 3; ++ unsigned int f3 : 1; ++ unsigned int f4 : 1; ++ ++}; ++ ++void init_A (struct A *this) ++{ ++ this->f1 = 0; ++ this->f2 = 1; ++ this->f3 = 0; ++ this->f4 = 0; ++} ++ ++/* { dg-final { scan-assembler-times "ldr" 1 } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/pr42835.c' +--- old/gcc/testsuite/gcc.target/arm/pr42835.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr42835.c 2010-08-31 10:00:27 +0000 +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mthumb -Os" } */ ++/* { dg-require-effective-target arm_thumb2_ok } */ ++ ++int foo(int *p, int i) ++{ ++ return( (i < 0 && *p == 1) ++ || (i > 0 && *p == 2) ); ++} ++ ++/* { dg-final { scan-assembler-times "movne\[\\t \]*r.,\[\\t \]*#" 1 } } */ ++/* { dg-final { scan-assembler-times "moveq\[\\t \]*r.,\[\\t \]*#" 1 } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c' +--- old/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c 2010-08-31 10:00:27 +0000 +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mthumb -Os" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++ ++int ldrb(unsigned char* p) ++{ ++ if (p[8] <= 0x7F) ++ return 2; ++ else ++ return 5; ++} ++ ++ ++/* { dg-final { scan-assembler "127" } } */ ++/* { dg-final { scan-assembler "bhi" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/thumb-comparisons.c' +--- old/gcc/testsuite/gcc.target/arm/thumb-comparisons.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/thumb-comparisons.c 2010-08-31 10:00:27 +0000 +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mthumb -Os" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++ ++int foo(char ch) ++{ ++ switch (ch) { ++ case '-': ++ case '?': ++ case '/': ++ case 99: ++ return 1; ++ default: ++ return 0; ++ } ++} ++ ++/* { dg-final { scan-assembler-times "cmp\[\\t \]*r.,\[\\t \]*#63" 1 } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/thumb-stackframe.c' +--- old/gcc/testsuite/gcc.target/arm/thumb-stackframe.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/thumb-stackframe.c 2010-08-31 10:00:27 +0000 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mthumb -Os" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++ ++extern void bar(int*); ++int foo() ++{ ++ int x; ++ bar(&x); ++ return x; ++} ++ ++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp," } } */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch new file mode 100644 index 0000000000..c66c11f82c --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch @@ -0,0 +1,2997 @@ +2010-08-31 Chung-Lin Tang + + Backport from mainline: + + 2010-04-14 Bernd Schmidt + + PR target/21803 + gcc/ + * ifcvt.c (cond_exec_process_if_block): Look for identical sequences + at the start and end of the then/else blocks, and omit them from the + conversion. + * cfgcleanup.c (flow_find_cross_jump): No longer static. Remove MODE + argument; all callers changed. Pass zero to old_insns_match_p instead. + (flow_find_head_matching_sequence): New function. + (old_insns_match_p): Check REG_EH_REGION notes for calls. + * basic-block.h (flow_find_cross_jump, + flow_find_head_matching_sequence): Declare functions. + + gcc/testsuite/ + * gcc.target/arm/pr42496.c: New test. + + 2010-04-22 Bernd Schmidt + + PR middle-end/29274 + gcc/ + * tree-pass.h (pass_optimize_widening_mul): Declare. + * tree-ssa-math-opts.c (execute_optimize_widening_mul, + gate_optimize_widening_mul): New static functions. + (pass_optimize_widening_mul): New. + * expr.c (expand_expr_real_2) : New case. + : Remove support for widening multiplies. + * tree.def (WIDEN_MULT_EXPR): Tweak comment. + * cfgexpand.c (expand_debug_expr) : Use + simplify_gen_unary rather than directly building extensions. + * tree-cfg.c (verify_gimple_assign_binary): Add tests for + WIDEN_MULT_EXPR. + * expmed.c (expand_widening_mult): New function. + * passes.c (init_optimization_passes): Add pass_optimize_widening_mul. + * optabs.h (expand_widening_mult): Declare. + + gcc/testsuite/ + * gcc.target/i386/wmul-1.c: New test. + * gcc.target/i386/wmul-2.c: New test. + * gcc.target/bfin/wmul-1.c: New test. + * gcc.target/bfin/wmul-2.c: New test. + * gcc.target/arm/wmul-1.c: New test. + * gcc.target/arm/wmul-2.c: New test. + + 2010-04-24 Bernd Schmidt + + PR tree-optimization/41442 + gcc/ + * fold-const.c (merge_truthop_with_opposite_arm): New function. + (fold_binary_loc): Call it. + + gcc/testsuite/ + * gcc.target/i386/pr41442.c: New test. + + 2010-04-29 Bernd Schmidt + + PR target/42895 + gcc/ + * doc/tm.texi (ADJUST_REG_ALLOC_ORDER): Renamed from + ORDER_REGS_FOR_LOCAL_ALLOC. All instances of this macro changed. + (HONOR_REG_ALLOC_ORDER): Describe new macro. + * ira.c (setup_alloc_regs): Use ADJUST_REG_ALLOC_ORDER if defined. + * ira-color.c (assign_hard_reg): Take prologue/epilogue costs into + account only if HONOR_REG_ALLOC_ORDER is not defined. + * config/arm/arm.h (HONOR_REG_ALLOC_ORDER): Define. + * system.h (ORDER_REGS_FOR_LOCAL_ALLOC): Poison. + + 2010-05-04 Mikael Pettersson + + PR bootstrap/43964 + gcc/ + * ira-color.c (assign_hard_reg): Declare rclass and add_cost + only if HONOR_REG_ALLOC_ORDER is not defined. + + 2010-06-04 Bernd Schmidt + + PR rtl-optimization/39871 + PR rtl-optimization/40615 + PR rtl-optimization/42500 + PR rtl-optimization/42502 + gcc/ + * ira.c (init_reg_equiv_memory_loc: New function. + (ira): Call it twice. + * reload.h (calculate_elim_costs_all_insns): Declare. + * ira-costs.c: Include "reload.h". + (regno_equiv_gains): New static variable. + (init_costs): Allocate it. + (finish_costs): Free it. + (ira_costs): Call calculate_elim_costs_all_insns. + (find_costs_and_classes): Take estimated elimination costs + into account. + (ira_adjust_equiv_reg_cost): New function. + * ira.h (ira_adjust_equiv_reg_cost): Declare it. + * reload1.c (init_eliminable_invariants, free_reg_equiv, + elimination_costs_in_insn, note_reg_elim_costly): New static functions. + (elim_bb): New static variable. + (reload): Move code out of here into init_eliminable_invariants and + free_reg_equiv. Call them. + (calculate_elim_costs_all_insns): New function. + (eliminate_regs_1): Declare. Add extra arg FOR_COSTS; + all callers changed. If FOR_COSTS is true, don't call alter_reg, + but call note_reg_elim_costly if we turned a valid memory address + into an invalid one. + * Makefile.in (ira-costs.o): Depend on reload.h. + + gcc/testsuite/ + * gcc.target/arm/eliminate.c: New test. + + 2010-06-09 Bernd Schmidt + + gcc/ + * config/arm/arm.c (thumb2_reorg): New function. + (arm_reorg): Call it. + * config/arm/thumb2.md (define_peephole2 for flag clobbering + arithmetic operations): Delete. + + 2010-06-12 Bernd Schmidt + + gcc/ + * config/arm/arm.c (thumb2_reorg): Fix errors in previous change. + + 2010-06-17 Bernd Schmidt + + PR rtl-optimization/39871 + gcc/ + * reload1.c (init_eliminable_invariants): For flag_pic, disable + equivalences only for constants that aren't LEGITIMATE_PIC_OPERAND_P. + (function_invariant_p): Rule out a plus of frame or arg pointer with + a SYMBOL_REF. + * ira.c (find_reg_equiv_invariant_const): Likewise. + + 2010-06-18 Eric Botcazou + + PR rtl-optimization/40900 + gcc/ + * expr.c (expand_expr_real_1) : Fix long line. Save the + original expression for later reuse. + : Use promote_function_mode to compute the signedness + of the promoted RTL for a SSA_NAME on the LHS of a call statement. + + 2010-06-18 Bernd Schmidt + gcc/testsuite/ + * gcc.target/arm/pr40900.c: New test. + + 2010-06-30 Bernd Schmidt + + PR tree-optimization/39799 + gcc/ + * tree-inline.c (remap_ssa_name): Initialize variable only if + SSA_NAME_OCCURS_IN_ABNORMAL_PHI. + * tree-ssa.c (warn_uninit): Avoid emitting an unnecessary message. + + gcc/testsuite/ + * c-c++-common/uninit-17.c: New test. + + 2010-07-25 Eric Botcazou + + PR target/44484 + gcc/ + * config/sparc/predicates.md (memory_reg_operand): Delete. + * config/sparc/sync.md (sync_compare_and_swap): Minor tweaks. + (*sync_compare_and_swap): Encode the address form in the pattern. + (*sync_compare_and_swapdi_v8plus): Likewise. + + 2010-08-29 Chung-Lin Tang + + Backport from mainline: + +=== modified file 'gcc/Makefile.in' +--- old/gcc/Makefile.in 2010-08-10 13:31:21 +0000 ++++ new/gcc/Makefile.in 2010-09-01 13:29:58 +0000 +@@ -3193,7 +3193,7 @@ + ira-costs.o: ira-costs.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ + hard-reg-set.h $(RTL_H) $(EXPR_H) $(TM_P_H) $(FLAGS_H) $(BASIC_BLOCK_H) \ + $(REGS_H) addresses.h insn-config.h $(RECOG_H) $(TOPLEV_H) $(TARGET_H) \ +- $(PARAMS_H) $(IRA_INT_H) ++ $(PARAMS_H) $(IRA_INT_H) reload.h + ira-conflicts.o: ira-conflicts.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ + $(TARGET_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) \ + insn-config.h $(RECOG_H) $(BASIC_BLOCK_H) $(TOPLEV_H) $(TM_P_H) $(PARAMS_H) \ + +=== modified file 'gcc/basic-block.h' +--- old/gcc/basic-block.h 2010-08-16 09:41:58 +0000 ++++ new/gcc/basic-block.h 2010-09-01 13:29:58 +0000 +@@ -894,6 +894,10 @@ + + /* In cfgcleanup.c. */ + extern bool cleanup_cfg (int); ++extern int flow_find_cross_jump (basic_block, basic_block, rtx *, rtx *); ++extern int flow_find_head_matching_sequence (basic_block, basic_block, ++ rtx *, rtx *, int); ++ + extern bool delete_unreachable_blocks (void); + + extern bool mark_dfs_back_edges (void); + +=== modified file 'gcc/cfgcleanup.c' +--- old/gcc/cfgcleanup.c 2010-05-17 16:26:22 +0000 ++++ new/gcc/cfgcleanup.c 2010-09-01 13:29:58 +0000 +@@ -68,7 +68,6 @@ + static bool try_crossjump_to_edge (int, edge, edge); + static bool try_crossjump_bb (int, basic_block); + static bool outgoing_edges_match (int, basic_block, basic_block); +-static int flow_find_cross_jump (int, basic_block, basic_block, rtx *, rtx *); + static bool old_insns_match_p (int, rtx, rtx); + + static void merge_blocks_move_predecessor_nojumps (basic_block, basic_block); +@@ -972,13 +971,27 @@ + be filled that clobbers a parameter expected by the subroutine. + + ??? We take the simple route for now and assume that if they're +- equal, they were constructed identically. */ +- +- if (CALL_P (i1) +- && (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1), ++ equal, they were constructed identically. ++ ++ Also check for identical exception regions. */ ++ ++ if (CALL_P (i1)) ++ { ++ /* Ensure the same EH region. */ ++ rtx n1 = find_reg_note (i1, REG_EH_REGION, 0); ++ rtx n2 = find_reg_note (i2, REG_EH_REGION, 0); ++ ++ if (!n1 && n2) ++ return false; ++ ++ if (n1 && (!n2 || XEXP (n1, 0) != XEXP (n2, 0))) ++ return false; ++ ++ if (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1), + CALL_INSN_FUNCTION_USAGE (i2)) +- || SIBLING_CALL_P (i1) != SIBLING_CALL_P (i2))) +- return false; ++ || SIBLING_CALL_P (i1) != SIBLING_CALL_P (i2)) ++ return false; ++ } + + #ifdef STACK_REGS + /* If cross_jump_death_matters is not 0, the insn's mode +@@ -1017,6 +1030,29 @@ + return false; + } + ++/* When comparing insns I1 and I2 in flow_find_cross_jump or ++ flow_find_head_matching_sequence, ensure the notes match. */ ++ ++static void ++merge_notes (rtx i1, rtx i2) ++{ ++ /* If the merged insns have different REG_EQUAL notes, then ++ remove them. */ ++ rtx equiv1 = find_reg_equal_equiv_note (i1); ++ rtx equiv2 = find_reg_equal_equiv_note (i2); ++ ++ if (equiv1 && !equiv2) ++ remove_note (i1, equiv1); ++ else if (!equiv1 && equiv2) ++ remove_note (i2, equiv2); ++ else if (equiv1 && equiv2 ++ && !rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0))) ++ { ++ remove_note (i1, equiv1); ++ remove_note (i2, equiv2); ++ } ++} ++ + /* Look through the insns at the end of BB1 and BB2 and find the longest + sequence that are equivalent. Store the first insns for that sequence + in *F1 and *F2 and return the sequence length. +@@ -1024,9 +1060,8 @@ + To simplify callers of this function, if the blocks match exactly, + store the head of the blocks in *F1 and *F2. */ + +-static int +-flow_find_cross_jump (int mode ATTRIBUTE_UNUSED, basic_block bb1, +- basic_block bb2, rtx *f1, rtx *f2) ++int ++flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2) + { + rtx i1, i2, last1, last2, afterlast1, afterlast2; + int ninsns = 0; +@@ -1066,7 +1101,7 @@ + if (i1 == BB_HEAD (bb1) || i2 == BB_HEAD (bb2)) + break; + +- if (!old_insns_match_p (mode, i1, i2)) ++ if (!old_insns_match_p (0, i1, i2)) + break; + + merge_memattrs (i1, i2); +@@ -1074,21 +1109,7 @@ + /* Don't begin a cross-jump with a NOTE insn. */ + if (INSN_P (i1)) + { +- /* If the merged insns have different REG_EQUAL notes, then +- remove them. */ +- rtx equiv1 = find_reg_equal_equiv_note (i1); +- rtx equiv2 = find_reg_equal_equiv_note (i2); +- +- if (equiv1 && !equiv2) +- remove_note (i1, equiv1); +- else if (!equiv1 && equiv2) +- remove_note (i2, equiv2); +- else if (equiv1 && equiv2 +- && !rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0))) +- { +- remove_note (i1, equiv1); +- remove_note (i2, equiv2); +- } ++ merge_notes (i1, i2); + + afterlast1 = last1, afterlast2 = last2; + last1 = i1, last2 = i2; +@@ -1130,6 +1151,97 @@ + return ninsns; + } + ++/* Like flow_find_cross_jump, except start looking for a matching sequence from ++ the head of the two blocks. Do not include jumps at the end. ++ If STOP_AFTER is nonzero, stop after finding that many matching ++ instructions. */ ++ ++int ++flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, ++ rtx *f2, int stop_after) ++{ ++ rtx i1, i2, last1, last2, beforelast1, beforelast2; ++ int ninsns = 0; ++ edge e; ++ edge_iterator ei; ++ int nehedges1 = 0, nehedges2 = 0; ++ ++ FOR_EACH_EDGE (e, ei, bb1->succs) ++ if (e->flags & EDGE_EH) ++ nehedges1++; ++ FOR_EACH_EDGE (e, ei, bb2->succs) ++ if (e->flags & EDGE_EH) ++ nehedges2++; ++ ++ i1 = BB_HEAD (bb1); ++ i2 = BB_HEAD (bb2); ++ last1 = beforelast1 = last2 = beforelast2 = NULL_RTX; ++ ++ while (true) ++ { ++ ++ /* Ignore notes. */ ++ while (!NONDEBUG_INSN_P (i1) && i1 != BB_END (bb1)) ++ i1 = NEXT_INSN (i1); ++ ++ while (!NONDEBUG_INSN_P (i2) && i2 != BB_END (bb2)) ++ i2 = NEXT_INSN (i2); ++ ++ if (NOTE_P (i1) || NOTE_P (i2) ++ || JUMP_P (i1) || JUMP_P (i2)) ++ break; ++ ++ /* A sanity check to make sure we're not merging insns with different ++ effects on EH. If only one of them ends a basic block, it shouldn't ++ have an EH edge; if both end a basic block, there should be the same ++ number of EH edges. */ ++ if ((i1 == BB_END (bb1) && i2 != BB_END (bb2) ++ && nehedges1 > 0) ++ || (i2 == BB_END (bb2) && i1 != BB_END (bb1) ++ && nehedges2 > 0) ++ || (i1 == BB_END (bb1) && i2 == BB_END (bb2) ++ && nehedges1 != nehedges2)) ++ break; ++ ++ if (!old_insns_match_p (0, i1, i2)) ++ break; ++ ++ merge_memattrs (i1, i2); ++ ++ /* Don't begin a cross-jump with a NOTE insn. */ ++ if (INSN_P (i1)) ++ { ++ merge_notes (i1, i2); ++ ++ beforelast1 = last1, beforelast2 = last2; ++ last1 = i1, last2 = i2; ++ ninsns++; ++ } ++ ++ if (i1 == BB_END (bb1) || i2 == BB_END (bb2) ++ || (stop_after > 0 && ninsns == stop_after)) ++ break; ++ ++ i1 = NEXT_INSN (i1); ++ i2 = NEXT_INSN (i2); ++ } ++ ++#ifdef HAVE_cc0 ++ /* Don't allow a compare to be shared by cross-jumping unless the insn ++ after the compare is also shared. */ ++ if (ninsns && reg_mentioned_p (cc0_rtx, last1) && sets_cc0_p (last1)) ++ last1 = beforelast1, last2 = beforelast2, ninsns--; ++#endif ++ ++ if (ninsns) ++ { ++ *f1 = last1; ++ *f2 = last2; ++ } ++ ++ return ninsns; ++} ++ + /* Return true iff outgoing edges of BB1 and BB2 match, together with + the branch instruction. This means that if we commonize the control + flow before end of the basic block, the semantic remains unchanged. +@@ -1498,7 +1610,7 @@ + return false; + + /* ... and part the second. */ +- nmatch = flow_find_cross_jump (mode, src1, src2, &newpos1, &newpos2); ++ nmatch = flow_find_cross_jump (src1, src2, &newpos1, &newpos2); + + /* Don't proceed with the crossjump unless we found a sufficient number + of matching instructions or the 'from' block was totally matched + +=== modified file 'gcc/cfgexpand.c' +--- old/gcc/cfgexpand.c 2010-05-14 17:11:03 +0000 ++++ new/gcc/cfgexpand.c 2010-09-01 13:29:58 +0000 +@@ -3026,14 +3026,15 @@ + if (SCALAR_INT_MODE_P (GET_MODE (op0)) + && SCALAR_INT_MODE_P (mode)) + { ++ enum machine_mode inner_mode = GET_MODE (op0); + if (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0)))) +- op0 = gen_rtx_ZERO_EXTEND (mode, op0); ++ op0 = simplify_gen_unary (ZERO_EXTEND, mode, op0, inner_mode); + else +- op0 = gen_rtx_SIGN_EXTEND (mode, op0); ++ op0 = simplify_gen_unary (SIGN_EXTEND, mode, op0, inner_mode); + if (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 1)))) +- op1 = gen_rtx_ZERO_EXTEND (mode, op1); ++ op1 = simplify_gen_unary (ZERO_EXTEND, mode, op1, inner_mode); + else +- op1 = gen_rtx_SIGN_EXTEND (mode, op1); ++ op1 = simplify_gen_unary (SIGN_EXTEND, mode, op1, inner_mode); + return gen_rtx_MULT (mode, op0, op1); + } + return NULL; + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-31 10:00:27 +0000 ++++ new/gcc/config/arm/arm.c 2010-09-01 13:29:58 +0000 +@@ -8116,8 +8116,6 @@ + static bool + xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) + { +- rtx i_pat, d_pat; +- + /* Some true dependencies can have a higher cost depending + on precisely how certain input operands are used. */ + if (REG_NOTE_KIND (link) == 0 +@@ -12166,6 +12164,60 @@ + return result; + } + ++/* Convert instructions to their cc-clobbering variant if possible, since ++ that allows us to use smaller encodings. */ ++ ++static void ++thumb2_reorg (void) ++{ ++ basic_block bb; ++ regset_head live; ++ ++ INIT_REG_SET (&live); ++ ++ /* We are freeing block_for_insn in the toplev to keep compatibility ++ with old MDEP_REORGS that are not CFG based. Recompute it now. */ ++ compute_bb_for_insn (); ++ df_analyze (); ++ ++ FOR_EACH_BB (bb) ++ { ++ rtx insn; ++ COPY_REG_SET (&live, DF_LR_OUT (bb)); ++ df_simulate_initialize_backwards (bb, &live); ++ FOR_BB_INSNS_REVERSE (bb, insn) ++ { ++ if (NONJUMP_INSN_P (insn) ++ && !REGNO_REG_SET_P (&live, CC_REGNUM)) ++ { ++ rtx pat = PATTERN (insn); ++ if (GET_CODE (pat) == SET ++ && low_register_operand (XEXP (pat, 0), SImode) ++ && thumb_16bit_operator (XEXP (pat, 1), SImode) ++ && low_register_operand (XEXP (XEXP (pat, 1), 0), SImode) ++ && low_register_operand (XEXP (XEXP (pat, 1), 1), SImode)) ++ { ++ rtx dst = XEXP (pat, 0); ++ rtx src = XEXP (pat, 1); ++ rtx op0 = XEXP (src, 0); ++ if (rtx_equal_p (dst, op0) ++ || GET_CODE (src) == PLUS || GET_CODE (src) == MINUS) ++ { ++ rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM); ++ rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg); ++ rtvec vec = gen_rtvec (2, pat, clobber); ++ PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); ++ INSN_CODE (insn) = -1; ++ } ++ } ++ } ++ if (NONDEBUG_INSN_P (insn)) ++ df_simulate_one_insn_backwards (bb, insn, &live); ++ } ++ } ++ CLEAR_REG_SET (&live); ++} ++ + /* Gcc puts the pool in the wrong place for ARM, since we can only + load addresses a limited distance around the pc. We do some + special munging to move the constant pool values to the correct +@@ -12177,6 +12229,9 @@ + HOST_WIDE_INT address = 0; + Mfix * fix; + ++ if (TARGET_THUMB2) ++ thumb2_reorg (); ++ + minipool_fix_head = minipool_fix_tail = NULL; + + /* The first insn must always be a note, or the code below won't + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-13 11:11:15 +0000 ++++ new/gcc/config/arm/arm.h 2010-09-01 13:29:58 +0000 +@@ -1133,7 +1133,11 @@ + } + + /* Use different register alloc ordering for Thumb. */ +-#define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () ++ ++/* Tell IRA to use the order we define rather than messing it up with its ++ own cost calculations. */ ++#define HONOR_REG_ALLOC_ORDER + + /* Interrupt functions can only use registers that have already been + saved by the prologue, even if they would normally be + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-08-31 10:00:27 +0000 ++++ new/gcc/config/arm/arm.md 2010-09-01 13:29:58 +0000 +@@ -4074,7 +4074,7 @@ + + (define_split + [(set (match_operand:SI 0 "register_operand" "") +- (zero_extend:SI (match_operand:HI 1 "register_operand" "l,m")))] ++ (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] + "!TARGET_THUMB2 && !arm_arch6" + [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2010-08-31 10:00:27 +0000 ++++ new/gcc/config/arm/thumb2.md 2010-09-01 13:29:58 +0000 +@@ -1046,29 +1046,6 @@ + }" + ) + +-;; Peepholes and insns for 16-bit flag clobbering instructions. +-;; The conditional forms of these instructions do not clobber CC. +-;; However by the time peepholes are run it is probably too late to do +-;; anything useful with this information. +-(define_peephole2 +- [(set (match_operand:SI 0 "low_register_operand" "") +- (match_operator:SI 3 "thumb_16bit_operator" +- [(match_operand:SI 1 "low_register_operand" "") +- (match_operand:SI 2 "low_register_operand" "")]))] +- "TARGET_THUMB2 +- && (rtx_equal_p(operands[0], operands[1]) +- || GET_CODE(operands[3]) == PLUS +- || GET_CODE(operands[3]) == MINUS) +- && peep2_regno_dead_p(0, CC_REGNUM)" +- [(parallel +- [(set (match_dup 0) +- (match_op_dup 3 +- [(match_dup 1) +- (match_dup 2)])) +- (clobber (reg:CC CC_REGNUM))])] +- "" +-) +- + (define_insn "*thumb2_alusi3_short" + [(set (match_operand:SI 0 "s_register_operand" "=l") + (match_operator:SI 3 "thumb_16bit_operator" + +=== modified file 'gcc/config/avr/avr.h' +--- old/gcc/config/avr/avr.h 2010-01-11 23:12:14 +0000 ++++ new/gcc/config/avr/avr.h 2010-09-01 13:29:58 +0000 +@@ -232,7 +232,7 @@ + 32,33,34,35 \ + } + +-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () + + + #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +=== modified file 'gcc/config/i386/i386.h' +--- old/gcc/config/i386/i386.h 2010-04-27 19:14:19 +0000 ++++ new/gcc/config/i386/i386.h 2010-09-01 13:29:58 +0000 +@@ -955,7 +955,7 @@ + registers listed in CALL_USED_REGISTERS, keeping the others + available for storage of persistent values. + +- The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, ++ The ADJUST_REG_ALLOC_ORDER actually overwrite the order, + so this is just empty initializer for array. */ + + #define REG_ALLOC_ORDER \ +@@ -964,11 +964,11 @@ + 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52 } + +-/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order ++/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order + to be rearranged based on a particular function. When using sse math, + we want to allocate SSE before x87 registers and vice versa. */ + +-#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () + + + #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) + +=== modified file 'gcc/config/mips/mips.h' +--- old/gcc/config/mips/mips.h 2009-10-29 17:39:52 +0000 ++++ new/gcc/config/mips/mips.h 2010-09-01 13:29:58 +0000 +@@ -2059,12 +2059,12 @@ + 182,183,184,185,186,187 \ + } + +-/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order ++/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order + to be rearranged based on a particular function. On the mips16, we + want to allocate $24 (T_REG) before other registers for + instructions for which it is possible. */ + +-#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc () + + /* True if VALUE is an unsigned 6-bit number. */ + + +=== modified file 'gcc/config/picochip/picochip.h' +--- old/gcc/config/picochip/picochip.h 2009-11-04 11:06:36 +0000 ++++ new/gcc/config/picochip/picochip.h 2010-09-01 13:29:58 +0000 +@@ -261,7 +261,7 @@ + /* We can dynamically change the REG_ALLOC_ORDER using the following hook. + It would be desirable to change it for leaf functions so we can put + r12 at the end of this list.*/ +-#define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc () + + /* How Values Fit in Registers */ + + +=== modified file 'gcc/config/sparc/predicates.md' +--- old/gcc/config/sparc/predicates.md 2009-02-20 15:20:38 +0000 ++++ new/gcc/config/sparc/predicates.md 2010-09-01 13:29:58 +0000 +@@ -1,5 +1,5 @@ + ;; Predicate definitions for SPARC. +-;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc. ++;; Copyright (C) 2005, 2007, 2008, 2010 Free Software Foundation, Inc. + ;; + ;; This file is part of GCC. + ;; +@@ -473,9 +473,3 @@ + ;; and (xor ... (not ...)) to (not (xor ...)). */ + (define_predicate "cc_arith_not_operator" + (match_code "and,ior")) +- +-;; Return true if OP is memory operand with just [%reg] addressing mode. +-(define_predicate "memory_reg_operand" +- (and (match_code "mem") +- (and (match_operand 0 "memory_operand") +- (match_test "REG_P (XEXP (op, 0))")))) + +=== modified file 'gcc/config/sparc/sparc.h' +--- old/gcc/config/sparc/sparc.h 2010-04-02 18:54:46 +0000 ++++ new/gcc/config/sparc/sparc.h 2010-09-01 13:29:58 +0000 +@@ -1181,7 +1181,7 @@ + 96, 97, 98, 99, /* %fcc0-3 */ \ + 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ + +-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () + + extern char sparc_leaf_regs[]; + #define LEAF_REGISTERS sparc_leaf_regs + +=== modified file 'gcc/config/sparc/sync.md' +--- old/gcc/config/sparc/sync.md 2009-02-20 15:20:38 +0000 ++++ new/gcc/config/sparc/sync.md 2010-09-01 13:29:58 +0000 +@@ -1,5 +1,5 @@ + ;; GCC machine description for SPARC synchronization instructions. +-;; Copyright (C) 2005, 2007, 2009 ++;; Copyright (C) 2005, 2007, 2009, 2010 + ;; Free Software Foundation, Inc. + ;; + ;; This file is part of GCC. +@@ -62,7 +62,7 @@ + + (define_expand "sync_compare_and_swap" + [(parallel +- [(set (match_operand:I48MODE 0 "register_operand" "=r") ++ [(set (match_operand:I48MODE 0 "register_operand" "") + (match_operand:I48MODE 1 "memory_operand" "")) + (set (match_dup 1) + (unspec_volatile:I48MODE +@@ -71,7 +71,7 @@ + UNSPECV_CAS))])] + "TARGET_V9" + { +- if (! REG_P (XEXP (operands[1], 0))) ++ if (!REG_P (XEXP (operands[1], 0))) + { + rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); + operands[1] = replace_equiv_address (operands[1], addr); +@@ -81,20 +81,20 @@ + + (define_insn "*sync_compare_and_swap" + [(set (match_operand:I48MODE 0 "register_operand" "=r") +- (match_operand:I48MODE 1 "memory_reg_operand" "+m")) +- (set (match_dup 1) ++ (mem:I48MODE (match_operand 1 "register_operand" "r"))) ++ (set (mem:I48MODE (match_dup 1)) + (unspec_volatile:I48MODE + [(match_operand:I48MODE 2 "register_operand" "r") + (match_operand:I48MODE 3 "register_operand" "0")] + UNSPECV_CAS))] + "TARGET_V9 && (mode == SImode || TARGET_ARCH64)" +- "cas\t%1, %2, %0" ++ "cas\t[%1], %2, %0" + [(set_attr "type" "multi")]) + + (define_insn "*sync_compare_and_swapdi_v8plus" + [(set (match_operand:DI 0 "register_operand" "=h") +- (match_operand:DI 1 "memory_reg_operand" "+m")) +- (set (match_dup 1) ++ (mem:DI (match_operand 1 "register_operand" "r"))) ++ (set (mem:DI (match_dup 1)) + (unspec_volatile:DI + [(match_operand:DI 2 "register_operand" "h") + (match_operand:DI 3 "register_operand" "0")] +@@ -109,7 +109,7 @@ + output_asm_insn ("srl\t%L2, 0, %L2", operands); + output_asm_insn ("sllx\t%H2, 32, %H3", operands); + output_asm_insn ("or\t%L2, %H3, %H3", operands); +- output_asm_insn ("casx\t%1, %H3, %L3", operands); ++ output_asm_insn ("casx\t[%1], %H3, %L3", operands); + return "srlx\t%L3, 32, %H3"; + } + [(set_attr "type" "multi") + +=== modified file 'gcc/config/xtensa/xtensa.h' +--- old/gcc/config/xtensa/xtensa.h 2009-09-23 21:24:42 +0000 ++++ new/gcc/config/xtensa/xtensa.h 2010-09-01 13:29:58 +0000 +@@ -286,7 +286,7 @@ + incoming argument in a2 is live throughout the function and + local-alloc decides to use a2, then the incoming argument must + either be spilled or copied to another register. To get around +- this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine ++ this, we define ADJUST_REG_ALLOC_ORDER to redefine + reg_alloc_order for leaf functions such that lowest numbered + registers are used first with the exception that the incoming + argument registers are not used until after other register choices +@@ -300,7 +300,7 @@ + 35, \ + } + +-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () + + /* For Xtensa, the only point of this is to prevent GCC from otherwise + giving preference to call-used registers. To minimize window + +=== modified file 'gcc/doc/tm.texi' +--- old/gcc/doc/tm.texi 2010-08-13 11:53:46 +0000 ++++ new/gcc/doc/tm.texi 2010-09-01 13:29:58 +0000 +@@ -2093,7 +2093,7 @@ + the highest numbered allocable register first. + @end defmac + +-@defmac ORDER_REGS_FOR_LOCAL_ALLOC ++@defmac ADJUST_REG_ALLOC_ORDER + A C statement (sans semicolon) to choose the order in which to allocate + hard registers for pseudo-registers local to a basic block. + +@@ -2107,6 +2107,15 @@ + On most machines, it is not necessary to define this macro. + @end defmac + ++@defmac HONOR_REG_ALLOC_ORDER ++Normally, IRA tries to estimate the costs for saving a register in the ++prologue and restoring it in the epilogue. This discourages it from ++using call-saved registers. If a machine wants to ensure that IRA ++allocates registers in the order given by REG_ALLOC_ORDER even if some ++call-saved registers appear earlier than call-used ones, this macro ++should be defined. ++@end defmac ++ + @defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno}) + In some case register allocation order is not enough for the + Integrated Register Allocator (@acronym{IRA}) to generate a good code. + +=== modified file 'gcc/expmed.c' +--- old/gcc/expmed.c 2010-03-03 22:10:17 +0000 ++++ new/gcc/expmed.c 2010-09-01 13:29:58 +0000 +@@ -3253,6 +3253,55 @@ + gcc_assert (op0); + return op0; + } ++ ++/* Perform a widening multiplication and return an rtx for the result. ++ MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); ++ TARGET is a suggestion for where to store the result (an rtx). ++ THIS_OPTAB is the optab we should use, it must be either umul_widen_optab ++ or smul_widen_optab. ++ ++ We check specially for a constant integer as OP1, comparing the ++ cost of a widening multiply against the cost of a sequence of shifts ++ and adds. */ ++ ++rtx ++expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, ++ int unsignedp, optab this_optab) ++{ ++ bool speed = optimize_insn_for_speed_p (); ++ ++ if (CONST_INT_P (op1) ++ && (INTVAL (op1) >= 0 ++ || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)) ++ { ++ HOST_WIDE_INT coeff = INTVAL (op1); ++ int max_cost; ++ enum mult_variant variant; ++ struct algorithm algorithm; ++ ++ /* Special case powers of two. */ ++ if (EXACT_POWER_OF_2_OR_ZERO_P (coeff)) ++ { ++ op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab); ++ return expand_shift (LSHIFT_EXPR, mode, op0, ++ build_int_cst (NULL_TREE, floor_log2 (coeff)), ++ target, unsignedp); ++ } ++ ++ /* Exclude cost of op0 from max_cost to match the cost ++ calculation of the synth_mult. */ ++ max_cost = mul_widen_cost[speed][mode]; ++ if (choose_mult_variant (mode, coeff, &algorithm, &variant, ++ max_cost)) ++ { ++ op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab); ++ return expand_mult_const (mode, op0, coeff, target, ++ &algorithm, variant); ++ } ++ } ++ return expand_binop (mode, this_optab, op0, op1, target, ++ unsignedp, OPTAB_LIB_WIDEN); ++} + + /* Return the smallest n such that 2**n >= X. */ + + +=== modified file 'gcc/expr.c' +--- old/gcc/expr.c 2010-08-20 16:21:01 +0000 ++++ new/gcc/expr.c 2010-09-01 13:29:58 +0000 +@@ -7224,7 +7224,6 @@ + optab this_optab; + rtx subtarget, original_target; + int ignore; +- tree subexp0, subexp1; + bool reduce_bit_field; + gimple subexp0_def, subexp1_def; + tree top0, top1; +@@ -7679,13 +7678,7 @@ + + goto binop2; + +- case MULT_EXPR: +- /* If this is a fixed-point operation, then we cannot use the code +- below because "expand_mult" doesn't support sat/no-sat fixed-point +- multiplications. */ +- if (ALL_FIXED_POINT_MODE_P (mode)) +- goto binop; +- ++ case WIDEN_MULT_EXPR: + /* If first operand is constant, swap them. + Thus the following special case checks need only + check the second operand. */ +@@ -7696,96 +7689,35 @@ + treeop1 = t1; + } + +- /* Attempt to return something suitable for generating an +- indexed address, for machines that support that. */ +- +- if (modifier == EXPAND_SUM && mode == ptr_mode +- && host_integerp (treeop1, 0)) +- { +- tree exp1 = treeop1; +- +- op0 = expand_expr (treeop0, subtarget, VOIDmode, +- EXPAND_SUM); +- +- if (!REG_P (op0)) +- op0 = force_operand (op0, NULL_RTX); +- if (!REG_P (op0)) +- op0 = copy_to_mode_reg (mode, op0); +- +- return REDUCE_BIT_FIELD (gen_rtx_MULT (mode, op0, +- gen_int_mode (tree_low_cst (exp1, 0), +- TYPE_MODE (TREE_TYPE (exp1))))); +- } +- +- if (modifier == EXPAND_STACK_PARM) +- target = 0; +- +- /* Check for multiplying things that have been extended +- from a narrower type. If this machine supports multiplying +- in that narrower type with a result in the desired type, +- do it that way, and avoid the explicit type-conversion. */ +- +- subexp0 = treeop0; +- subexp1 = treeop1; +- subexp0_def = get_def_for_expr (subexp0, NOP_EXPR); +- subexp1_def = get_def_for_expr (subexp1, NOP_EXPR); +- top0 = top1 = NULL_TREE; +- + /* First, check if we have a multiplication of one signed and one + unsigned operand. */ +- if (subexp0_def +- && (top0 = gimple_assign_rhs1 (subexp0_def)) +- && subexp1_def +- && (top1 = gimple_assign_rhs1 (subexp1_def)) +- && TREE_CODE (type) == INTEGER_TYPE +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- < TYPE_PRECISION (TREE_TYPE (subexp0))) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- == TYPE_PRECISION (TREE_TYPE (top1))) +- && (TYPE_UNSIGNED (TREE_TYPE (top0)) +- != TYPE_UNSIGNED (TREE_TYPE (top1)))) ++ if (TREE_CODE (treeop1) != INTEGER_CST ++ && (TYPE_UNSIGNED (TREE_TYPE (treeop0)) ++ != TYPE_UNSIGNED (TREE_TYPE (treeop1)))) + { +- enum machine_mode innermode +- = TYPE_MODE (TREE_TYPE (top0)); ++ enum machine_mode innermode = TYPE_MODE (TREE_TYPE (treeop0)); + this_optab = usmul_widen_optab; +- if (mode == GET_MODE_WIDER_MODE (innermode)) ++ if (mode == GET_MODE_2XWIDER_MODE (innermode)) + { + if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) + { +- if (TYPE_UNSIGNED (TREE_TYPE (top0))) +- expand_operands (top0, top1, NULL_RTX, &op0, &op1, ++ if (TYPE_UNSIGNED (TREE_TYPE (treeop0))) ++ expand_operands (treeop0, treeop1, subtarget, &op0, &op1, + EXPAND_NORMAL); + else +- expand_operands (top0, top1, NULL_RTX, &op1, &op0, ++ expand_operands (treeop0, treeop1, subtarget, &op1, &op0, + EXPAND_NORMAL); +- + goto binop3; + } + } + } +- /* Check for a multiplication with matching signedness. If +- valid, TOP0 and TOP1 were set in the previous if +- condition. */ +- else if (top0 +- && TREE_CODE (type) == INTEGER_TYPE +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- < TYPE_PRECISION (TREE_TYPE (subexp0))) +- && ((TREE_CODE (subexp1) == INTEGER_CST +- && int_fits_type_p (subexp1, TREE_TYPE (top0)) +- /* Don't use a widening multiply if a shift will do. */ +- && ((GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (subexp1))) +- > HOST_BITS_PER_WIDE_INT) +- || exact_log2 (TREE_INT_CST_LOW (subexp1)) < 0)) +- || +- (top1 +- && (TYPE_PRECISION (TREE_TYPE (top1)) +- == TYPE_PRECISION (TREE_TYPE (top0)) +- /* If both operands are extended, they must either both +- be zero-extended or both be sign-extended. */ +- && (TYPE_UNSIGNED (TREE_TYPE (top1)) +- == TYPE_UNSIGNED (TREE_TYPE (top0))))))) ++ /* Check for a multiplication with matching signedness. */ ++ else if ((TREE_CODE (treeop1) == INTEGER_CST ++ && int_fits_type_p (treeop1, TREE_TYPE (treeop0))) ++ || (TYPE_UNSIGNED (TREE_TYPE (treeop1)) ++ == TYPE_UNSIGNED (TREE_TYPE (treeop0)))) + { +- tree op0type = TREE_TYPE (top0); ++ tree op0type = TREE_TYPE (treeop0); + enum machine_mode innermode = TYPE_MODE (op0type); + bool zextend_p = TYPE_UNSIGNED (op0type); + optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab; +@@ -7795,24 +7727,22 @@ + { + if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) + { +- if (TREE_CODE (subexp1) == INTEGER_CST) +- expand_operands (top0, subexp1, NULL_RTX, &op0, &op1, +- EXPAND_NORMAL); +- else +- expand_operands (top0, top1, NULL_RTX, &op0, &op1, +- EXPAND_NORMAL); +- goto binop3; ++ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, ++ EXPAND_NORMAL); ++ temp = expand_widening_mult (mode, op0, op1, target, ++ unsignedp, this_optab); ++ return REDUCE_BIT_FIELD (temp); + } +- else if (optab_handler (other_optab, mode)->insn_code != CODE_FOR_nothing +- && innermode == word_mode) ++ if (optab_handler (other_optab, mode)->insn_code != CODE_FOR_nothing ++ && innermode == word_mode) + { + rtx htem, hipart; +- op0 = expand_normal (top0); +- if (TREE_CODE (subexp1) == INTEGER_CST) ++ op0 = expand_normal (treeop0); ++ if (TREE_CODE (treeop1) == INTEGER_CST) + op1 = convert_modes (innermode, mode, +- expand_normal (subexp1), unsignedp); ++ expand_normal (treeop1), unsignedp); + else +- op1 = expand_normal (top1); ++ op1 = expand_normal (treeop1); + temp = expand_binop (mode, other_optab, op0, op1, target, + unsignedp, OPTAB_LIB_WIDEN); + hipart = gen_highpart (innermode, temp); +@@ -7825,7 +7755,53 @@ + } + } + } +- expand_operands (subexp0, subexp1, subtarget, &op0, &op1, EXPAND_NORMAL); ++ treeop0 = fold_build1 (CONVERT_EXPR, type, treeop0); ++ treeop1 = fold_build1 (CONVERT_EXPR, type, treeop1); ++ expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL); ++ return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp)); ++ ++ case MULT_EXPR: ++ /* If this is a fixed-point operation, then we cannot use the code ++ below because "expand_mult" doesn't support sat/no-sat fixed-point ++ multiplications. */ ++ if (ALL_FIXED_POINT_MODE_P (mode)) ++ goto binop; ++ ++ /* If first operand is constant, swap them. ++ Thus the following special case checks need only ++ check the second operand. */ ++ if (TREE_CODE (treeop0) == INTEGER_CST) ++ { ++ tree t1 = treeop0; ++ treeop0 = treeop1; ++ treeop1 = t1; ++ } ++ ++ /* Attempt to return something suitable for generating an ++ indexed address, for machines that support that. */ ++ ++ if (modifier == EXPAND_SUM && mode == ptr_mode ++ && host_integerp (treeop1, 0)) ++ { ++ tree exp1 = treeop1; ++ ++ op0 = expand_expr (treeop0, subtarget, VOIDmode, ++ EXPAND_SUM); ++ ++ if (!REG_P (op0)) ++ op0 = force_operand (op0, NULL_RTX); ++ if (!REG_P (op0)) ++ op0 = copy_to_mode_reg (mode, op0); ++ ++ return REDUCE_BIT_FIELD (gen_rtx_MULT (mode, op0, ++ gen_int_mode (tree_low_cst (exp1, 0), ++ TYPE_MODE (TREE_TYPE (exp1))))); ++ } ++ ++ if (modifier == EXPAND_STACK_PARM) ++ target = 0; ++ ++ expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL); + return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp)); + + case TRUNC_DIV_EXPR: +@@ -8311,6 +8287,8 @@ + location_t loc = EXPR_LOCATION (exp); + struct separate_ops ops; + tree treeop0, treeop1, treeop2; ++ tree ssa_name = NULL_TREE; ++ gimple g; + + type = TREE_TYPE (exp); + mode = TYPE_MODE (type); +@@ -8423,15 +8401,17 @@ + base variable. This unnecessarily allocates a pseudo, see how we can + reuse it, if partition base vars have it set already. */ + if (!currently_expanding_to_rtl) +- return expand_expr_real_1 (SSA_NAME_VAR (exp), target, tmode, modifier, NULL); +- { +- gimple g = get_gimple_for_ssa_name (exp); +- if (g) +- return expand_expr_real (gimple_assign_rhs_to_tree (g), target, +- tmode, modifier, NULL); +- } +- decl_rtl = get_rtx_for_ssa_name (exp); +- exp = SSA_NAME_VAR (exp); ++ return expand_expr_real_1 (SSA_NAME_VAR (exp), target, tmode, modifier, ++ NULL); ++ ++ g = get_gimple_for_ssa_name (exp); ++ if (g) ++ return expand_expr_real (gimple_assign_rhs_to_tree (g), target, tmode, ++ modifier, NULL); ++ ++ ssa_name = exp; ++ decl_rtl = get_rtx_for_ssa_name (ssa_name); ++ exp = SSA_NAME_VAR (ssa_name); + goto expand_decl_rtl; + + case PARM_DECL: +@@ -8533,15 +8513,21 @@ + /* If the mode of DECL_RTL does not match that of the decl, it + must be a promoted value. We return a SUBREG of the wanted mode, + but mark it so that we know that it was already extended. */ +- +- if (REG_P (decl_rtl) +- && GET_MODE (decl_rtl) != DECL_MODE (exp)) ++ if (REG_P (decl_rtl) && GET_MODE (decl_rtl) != DECL_MODE (exp)) + { + enum machine_mode pmode; + +- /* Get the signedness used for this variable. Ensure we get the +- same mode we got when the variable was declared. */ +- pmode = promote_decl_mode (exp, &unsignedp); ++ /* Get the signedness to be used for this variable. Ensure we get ++ the same mode we got when the variable was declared. */ ++ if (code == SSA_NAME ++ && (g = SSA_NAME_DEF_STMT (ssa_name)) ++ && gimple_code (g) == GIMPLE_CALL) ++ pmode = promote_function_mode (type, mode, &unsignedp, ++ TREE_TYPE ++ (TREE_TYPE (gimple_call_fn (g))), ++ 2); ++ else ++ pmode = promote_decl_mode (exp, &unsignedp); + gcc_assert (GET_MODE (decl_rtl) == pmode); + + temp = gen_lowpart_SUBREG (mode, decl_rtl); + +=== modified file 'gcc/fold-const.c' +--- old/gcc/fold-const.c 2010-04-06 09:36:57 +0000 ++++ new/gcc/fold-const.c 2010-09-01 13:29:58 +0000 +@@ -5741,6 +5741,76 @@ + const_binop (BIT_XOR_EXPR, c, temp, 0)); + } + ++/* For an expression that has the form ++ (A && B) || ~B ++ or ++ (A || B) && ~B, ++ we can drop one of the inner expressions and simplify to ++ A || ~B ++ or ++ A && ~B ++ LOC is the location of the resulting expression. OP is the inner ++ logical operation; the left-hand side in the examples above, while CMPOP ++ is the right-hand side. RHS_ONLY is used to prevent us from accidentally ++ removing a condition that guards another, as in ++ (A != NULL && A->...) || A == NULL ++ which we must not transform. If RHS_ONLY is true, only eliminate the ++ right-most operand of the inner logical operation. */ ++ ++static tree ++merge_truthop_with_opposite_arm (location_t loc, tree op, tree cmpop, ++ bool rhs_only) ++{ ++ tree type = TREE_TYPE (cmpop); ++ enum tree_code code = TREE_CODE (cmpop); ++ enum tree_code truthop_code = TREE_CODE (op); ++ tree lhs = TREE_OPERAND (op, 0); ++ tree rhs = TREE_OPERAND (op, 1); ++ tree orig_lhs = lhs, orig_rhs = rhs; ++ enum tree_code rhs_code = TREE_CODE (rhs); ++ enum tree_code lhs_code = TREE_CODE (lhs); ++ enum tree_code inv_code; ++ ++ if (TREE_SIDE_EFFECTS (op) || TREE_SIDE_EFFECTS (cmpop)) ++ return NULL_TREE; ++ ++ if (TREE_CODE_CLASS (code) != tcc_comparison) ++ return NULL_TREE; ++ ++ if (rhs_code == truthop_code) ++ { ++ tree newrhs = merge_truthop_with_opposite_arm (loc, rhs, cmpop, rhs_only); ++ if (newrhs != NULL_TREE) ++ { ++ rhs = newrhs; ++ rhs_code = TREE_CODE (rhs); ++ } ++ } ++ if (lhs_code == truthop_code && !rhs_only) ++ { ++ tree newlhs = merge_truthop_with_opposite_arm (loc, lhs, cmpop, false); ++ if (newlhs != NULL_TREE) ++ { ++ lhs = newlhs; ++ lhs_code = TREE_CODE (lhs); ++ } ++ } ++ ++ inv_code = invert_tree_comparison (code, HONOR_NANS (TYPE_MODE (type))); ++ if (inv_code == rhs_code ++ && operand_equal_p (TREE_OPERAND (rhs, 0), TREE_OPERAND (cmpop, 0), 0) ++ && operand_equal_p (TREE_OPERAND (rhs, 1), TREE_OPERAND (cmpop, 1), 0)) ++ return lhs; ++ if (!rhs_only && inv_code == lhs_code ++ && operand_equal_p (TREE_OPERAND (lhs, 0), TREE_OPERAND (cmpop, 0), 0) ++ && operand_equal_p (TREE_OPERAND (lhs, 1), TREE_OPERAND (cmpop, 1), 0)) ++ return rhs; ++ if (rhs != orig_rhs || lhs != orig_lhs) ++ return fold_build2_loc (loc, truthop_code, TREE_TYPE (cmpop), ++ lhs, rhs); ++ return NULL_TREE; ++} ++ + /* Find ways of folding logical expressions of LHS and RHS: + Try to merge two comparisons to the same innermost item. + Look for range tests like "ch >= '0' && ch <= '9'". +@@ -12539,6 +12609,22 @@ + if (0 != (tem = fold_range_test (loc, code, type, op0, op1))) + return tem; + ++ if ((code == TRUTH_ANDIF_EXPR && TREE_CODE (arg0) == TRUTH_ORIF_EXPR) ++ || (code == TRUTH_ORIF_EXPR && TREE_CODE (arg0) == TRUTH_ANDIF_EXPR)) ++ { ++ tem = merge_truthop_with_opposite_arm (loc, arg0, arg1, true); ++ if (tem) ++ return fold_build2_loc (loc, code, type, tem, arg1); ++ } ++ ++ if ((code == TRUTH_ANDIF_EXPR && TREE_CODE (arg1) == TRUTH_ORIF_EXPR) ++ || (code == TRUTH_ORIF_EXPR && TREE_CODE (arg1) == TRUTH_ANDIF_EXPR)) ++ { ++ tem = merge_truthop_with_opposite_arm (loc, arg1, arg0, false); ++ if (tem) ++ return fold_build2_loc (loc, code, type, arg0, tem); ++ } ++ + /* Check for the possibility of merging component references. If our + lhs is another similar operation, try to merge its rhs with our + rhs. Then try to merge our lhs and rhs. */ + +=== modified file 'gcc/ifcvt.c' +--- old/gcc/ifcvt.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/ifcvt.c 2010-09-01 13:29:58 +0000 +@@ -385,7 +385,11 @@ + rtx false_expr; /* test for then block insns */ + rtx true_prob_val; /* probability of else block */ + rtx false_prob_val; /* probability of then block */ +- int n_insns; ++ rtx then_last_head = NULL_RTX; /* Last match at the head of THEN */ ++ rtx else_last_head = NULL_RTX; /* Last match at the head of ELSE */ ++ rtx then_first_tail = NULL_RTX; /* First match at the tail of THEN */ ++ rtx else_first_tail = NULL_RTX; /* First match at the tail of ELSE */ ++ int then_n_insns, else_n_insns, n_insns; + enum rtx_code false_code; + + /* If test is comprised of && or || elements, and we've failed at handling +@@ -418,15 +422,78 @@ + number of insns and see if it is small enough to convert. */ + then_start = first_active_insn (then_bb); + then_end = last_active_insn (then_bb, TRUE); +- n_insns = ce_info->num_then_insns = count_bb_insns (then_bb); ++ then_n_insns = ce_info->num_then_insns = count_bb_insns (then_bb); ++ n_insns = then_n_insns; + max = MAX_CONDITIONAL_EXECUTE; + + if (else_bb) + { ++ int n_matching; ++ + max *= 2; + else_start = first_active_insn (else_bb); + else_end = last_active_insn (else_bb, TRUE); +- n_insns += ce_info->num_else_insns = count_bb_insns (else_bb); ++ else_n_insns = ce_info->num_else_insns = count_bb_insns (else_bb); ++ n_insns += else_n_insns; ++ ++ /* Look for matching sequences at the head and tail of the two blocks, ++ and limit the range of insns to be converted if possible. */ ++ n_matching = flow_find_cross_jump (then_bb, else_bb, ++ &then_first_tail, &else_first_tail); ++ if (then_first_tail == BB_HEAD (then_bb)) ++ then_start = then_end = NULL_RTX; ++ if (else_first_tail == BB_HEAD (else_bb)) ++ else_start = else_end = NULL_RTX; ++ ++ if (n_matching > 0) ++ { ++ if (then_end) ++ then_end = prev_active_insn (then_first_tail); ++ if (else_end) ++ else_end = prev_active_insn (else_first_tail); ++ n_insns -= 2 * n_matching; ++ } ++ ++ if (then_start && else_start) ++ { ++ int longest_match = MIN (then_n_insns - n_matching, ++ else_n_insns - n_matching); ++ n_matching ++ = flow_find_head_matching_sequence (then_bb, else_bb, ++ &then_last_head, ++ &else_last_head, ++ longest_match); ++ ++ if (n_matching > 0) ++ { ++ rtx insn; ++ ++ /* We won't pass the insns in the head sequence to ++ cond_exec_process_insns, so we need to test them here ++ to make sure that they don't clobber the condition. */ ++ for (insn = BB_HEAD (then_bb); ++ insn != NEXT_INSN (then_last_head); ++ insn = NEXT_INSN (insn)) ++ if (!LABEL_P (insn) && !NOTE_P (insn) ++ && !DEBUG_INSN_P (insn) ++ && modified_in_p (test_expr, insn)) ++ return FALSE; ++ } ++ ++ if (then_last_head == then_end) ++ then_start = then_end = NULL_RTX; ++ if (else_last_head == else_end) ++ else_start = else_end = NULL_RTX; ++ ++ if (n_matching > 0) ++ { ++ if (then_start) ++ then_start = next_active_insn (then_last_head); ++ if (else_start) ++ else_start = next_active_insn (else_last_head); ++ n_insns -= 2 * n_matching; ++ } ++ } + } + + if (n_insns > max) +@@ -570,7 +637,21 @@ + fprintf (dump_file, "%d insn%s converted to conditional execution.\n", + n_insns, (n_insns == 1) ? " was" : "s were"); + +- /* Merge the blocks! */ ++ /* Merge the blocks! If we had matching sequences, make sure to delete one ++ copy at the appropriate location first: delete the copy in the THEN branch ++ for a tail sequence so that the remaining one is executed last for both ++ branches, and delete the copy in the ELSE branch for a head sequence so ++ that the remaining one is executed first for both branches. */ ++ if (then_first_tail) ++ { ++ rtx from = then_first_tail; ++ if (!INSN_P (from)) ++ from = next_active_insn (from); ++ delete_insn_chain (from, BB_END (then_bb), false); ++ } ++ if (else_last_head) ++ delete_insn_chain (first_active_insn (else_bb), else_last_head, false); ++ + merge_if_block (ce_info); + cond_exec_changed_p = TRUE; + return TRUE; + +=== modified file 'gcc/ira-color.c' +--- old/gcc/ira-color.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/ira-color.c 2010-09-01 13:29:58 +0000 +@@ -441,14 +441,18 @@ + { + HARD_REG_SET conflicting_regs; + int i, j, k, hard_regno, best_hard_regno, class_size; +- int cost, mem_cost, min_cost, full_cost, min_full_cost, add_cost; ++ int cost, mem_cost, min_cost, full_cost, min_full_cost; + int *a_costs; + int *conflict_costs; +- enum reg_class cover_class, rclass, conflict_cover_class; ++ enum reg_class cover_class, conflict_cover_class; + enum machine_mode mode; + ira_allocno_t a, conflict_allocno; + ira_allocno_conflict_iterator aci; + static int costs[FIRST_PSEUDO_REGISTER], full_costs[FIRST_PSEUDO_REGISTER]; ++#ifndef HONOR_REG_ALLOC_ORDER ++ enum reg_class rclass; ++ int add_cost; ++#endif + #ifdef STACK_REGS + bool no_stack_reg_p; + #endif +@@ -586,6 +590,7 @@ + continue; + cost = costs[i]; + full_cost = full_costs[i]; ++#ifndef HONOR_REG_ALLOC_ORDER + if (! allocated_hardreg_p[hard_regno] + && ira_hard_reg_not_in_set_p (hard_regno, mode, call_used_reg_set)) + /* We need to save/restore the hard register in +@@ -598,6 +603,7 @@ + cost += add_cost; + full_cost += add_cost; + } ++#endif + if (min_cost > cost) + min_cost = cost; + if (min_full_cost > full_cost) + +=== modified file 'gcc/ira-costs.c' +--- old/gcc/ira-costs.c 2010-08-13 11:40:17 +0000 ++++ new/gcc/ira-costs.c 2010-09-01 13:29:58 +0000 +@@ -33,6 +33,7 @@ + #include "addresses.h" + #include "insn-config.h" + #include "recog.h" ++#include "reload.h" + #include "toplev.h" + #include "target.h" + #include "params.h" +@@ -123,6 +124,10 @@ + /* Record cover register class of each allocno with the same regno. */ + static enum reg_class *regno_cover_class; + ++/* Record cost gains for not allocating a register with an invariant ++ equivalence. */ ++static int *regno_equiv_gains; ++ + /* Execution frequency of the current insn. */ + static int frequency; + +@@ -1263,6 +1268,7 @@ + #ifdef FORBIDDEN_INC_DEC_CLASSES + int inc_dec_p = false; + #endif ++ int equiv_savings = regno_equiv_gains[i]; + + if (! allocno_p) + { +@@ -1311,6 +1317,15 @@ + #endif + } + } ++ if (equiv_savings < 0) ++ temp_costs->mem_cost = -equiv_savings; ++ else if (equiv_savings > 0) ++ { ++ temp_costs->mem_cost = 0; ++ for (k = 0; k < cost_classes_num; k++) ++ temp_costs->cost[k] += equiv_savings; ++ } ++ + best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; + best = ALL_REGS; + alt_class = NO_REGS; +@@ -1680,6 +1695,8 @@ + regno_cover_class + = (enum reg_class *) ira_allocate (sizeof (enum reg_class) + * max_reg_num ()); ++ regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ()); ++ memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ()); + } + + /* Common finalization function for ira_costs and +@@ -1687,6 +1704,7 @@ + static void + finish_costs (void) + { ++ ira_free (regno_equiv_gains); + ira_free (regno_cover_class); + ira_free (pref_buffer); + ira_free (costs); +@@ -1702,6 +1720,7 @@ + init_costs (); + total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size + * ira_allocnos_num); ++ calculate_elim_costs_all_insns (); + find_costs_and_classes (ira_dump_file); + setup_allocno_cover_class_and_costs (); + finish_costs (); +@@ -1775,3 +1794,16 @@ + ALLOCNO_COVER_CLASS_COST (a) = min_cost; + } + } ++ ++/* Add COST to the estimated gain for eliminating REGNO with its ++ equivalence. If COST is zero, record that no such elimination is ++ possible. */ ++ ++void ++ira_adjust_equiv_reg_cost (unsigned regno, int cost) ++{ ++ if (cost == 0) ++ regno_equiv_gains[regno] = 0; ++ else ++ regno_equiv_gains[regno] += cost; ++} + +=== modified file 'gcc/ira.c' +--- old/gcc/ira.c 2010-08-12 13:51:16 +0000 ++++ new/gcc/ira.c 2010-09-01 13:29:58 +0000 +@@ -431,9 +431,6 @@ + HARD_REG_SET processed_hard_reg_set; + + ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); +- /* We could call ORDER_REGS_FOR_LOCAL_ALLOC here (it is usually +- putting hard callee-used hard registers first). But our +- heuristics work better. */ + for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) + { + COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); +@@ -490,6 +487,9 @@ + static void + setup_alloc_regs (bool use_hard_frame_p) + { ++#ifdef ADJUST_REG_ALLOC_ORDER ++ ADJUST_REG_ALLOC_ORDER; ++#endif + COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); + if (! use_hard_frame_p) + SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); +@@ -1533,12 +1533,8 @@ + + x = XEXP (note, 0); + +- if (! function_invariant_p (x) +- || ! flag_pic +- /* A function invariant is often CONSTANT_P but may +- include a register. We promise to only pass CONSTANT_P +- objects to LEGITIMATE_PIC_OPERAND_P. */ +- || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) ++ if (! CONSTANT_P (x) ++ || ! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) + { + /* It can happen that a REG_EQUIV note contains a MEM + that is not a legitimate memory operand. As later +@@ -3097,8 +3093,19 @@ + if (dump_file) + print_insn_chains (dump_file); + } +- + ++/* Allocate memory for reg_equiv_memory_loc. */ ++static void ++init_reg_equiv_memory_loc (void) ++{ ++ max_regno = max_reg_num (); ++ ++ /* And the reg_equiv_memory_loc array. */ ++ VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno); ++ memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0, ++ sizeof (rtx) * max_regno); ++ reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec); ++} + + /* All natural loops. */ + struct loops ira_loops; +@@ -3203,6 +3210,8 @@ + record_loop_exits (); + current_loops = &ira_loops; + ++ init_reg_equiv_memory_loc (); ++ + if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) + fprintf (ira_dump_file, "Building IRA IR\n"); + loops_p = ira_build (optimize +@@ -3263,13 +3272,8 @@ + #endif + + delete_trivially_dead_insns (get_insns (), max_reg_num ()); +- max_regno = max_reg_num (); + +- /* And the reg_equiv_memory_loc array. */ +- VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno); +- memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0, +- sizeof (rtx) * max_regno); +- reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec); ++ init_reg_equiv_memory_loc (); + + if (max_regno != max_regno_before_ira) + { + +=== modified file 'gcc/ira.h' +--- old/gcc/ira.h 2009-09-02 17:54:25 +0000 ++++ new/gcc/ira.h 2010-09-01 13:29:58 +0000 +@@ -87,3 +87,4 @@ + extern void ira_mark_new_stack_slot (rtx, int, unsigned int); + extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); + ++extern void ira_adjust_equiv_reg_cost (unsigned, int); + +=== modified file 'gcc/optabs.h' +--- old/gcc/optabs.h 2009-11-25 10:55:54 +0000 ++++ new/gcc/optabs.h 2010-09-01 13:29:58 +0000 +@@ -771,6 +771,9 @@ + /* Generate code for float to integral conversion. */ + extern bool expand_sfix_optab (rtx, rtx, convert_optab); + ++/* Generate code for a widening multiply. */ ++extern rtx expand_widening_mult (enum machine_mode, rtx, rtx, rtx, int, optab); ++ + /* Return tree if target supports vector operations for COND_EXPR. */ + bool expand_vec_cond_expr_p (tree, enum machine_mode); + + +=== modified file 'gcc/passes.c' +--- old/gcc/passes.c 2010-05-19 12:14:37 +0000 ++++ new/gcc/passes.c 2010-09-01 13:29:58 +0000 +@@ -944,6 +944,7 @@ + NEXT_PASS (pass_forwprop); + NEXT_PASS (pass_phiopt); + NEXT_PASS (pass_fold_builtins); ++ NEXT_PASS (pass_optimize_widening_mul); + NEXT_PASS (pass_tail_calls); + NEXT_PASS (pass_rename_ssa_copies); + NEXT_PASS (pass_uncprop); + +=== modified file 'gcc/reload.h' +--- old/gcc/reload.h 2010-04-02 18:54:46 +0000 ++++ new/gcc/reload.h 2010-09-01 13:29:58 +0000 +@@ -347,6 +347,10 @@ + extern rtx eliminate_regs (rtx, enum machine_mode, rtx); + extern bool elimination_target_reg_p (rtx); + ++/* Called from the register allocator to estimate costs of eliminating ++ invariant registers. */ ++extern void calculate_elim_costs_all_insns (void); ++ + /* Deallocate the reload register used by reload number R. */ + extern void deallocate_reload_reg (int r); + + +=== modified file 'gcc/reload1.c' +--- old/gcc/reload1.c 2010-03-02 18:56:50 +0000 ++++ new/gcc/reload1.c 2010-09-01 13:29:58 +0000 +@@ -413,6 +413,7 @@ + static void set_label_offsets (rtx, rtx, int); + static void check_eliminable_occurrences (rtx); + static void elimination_effects (rtx, enum machine_mode); ++static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool); + static int eliminate_regs_in_insn (rtx, int); + static void update_eliminable_offsets (void); + static void mark_not_eliminable (rtx, const_rtx, void *); +@@ -420,8 +421,11 @@ + static bool verify_initial_elim_offsets (void); + static void set_initial_label_offsets (void); + static void set_offsets_for_label (rtx); ++static void init_eliminable_invariants (rtx, bool); + static void init_elim_table (void); ++static void free_reg_equiv (void); + static void update_eliminables (HARD_REG_SET *); ++static void elimination_costs_in_insn (rtx); + static void spill_hard_reg (unsigned int, int); + static int finish_spills (int); + static void scan_paradoxical_subregs (rtx); +@@ -698,6 +702,9 @@ + + /* Global variables used by reload and its subroutines. */ + ++/* The current basic block while in calculate_elim_costs_all_insns. */ ++static basic_block elim_bb; ++ + /* Set during calculate_needs if an insn needs register elimination. */ + static int something_needs_elimination; + /* Set during calculate_needs if an insn needs an operand changed. */ +@@ -776,22 +783,6 @@ + if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) + df_set_regs_ever_live (i, true); + +- /* Find all the pseudo registers that didn't get hard regs +- but do have known equivalent constants or memory slots. +- These include parameters (known equivalent to parameter slots) +- and cse'd or loop-moved constant memory addresses. +- +- Record constant equivalents in reg_equiv_constant +- so they will be substituted by find_reloads. +- Record memory equivalents in reg_mem_equiv so they can +- be substituted eventually by altering the REG-rtx's. */ +- +- reg_equiv_constant = XCNEWVEC (rtx, max_regno); +- reg_equiv_invariant = XCNEWVEC (rtx, max_regno); +- reg_equiv_mem = XCNEWVEC (rtx, max_regno); +- reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); +- reg_equiv_address = XCNEWVEC (rtx, max_regno); +- reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); + reg_old_renumber = XCNEWVEC (short, max_regno); + memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); + pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); +@@ -799,115 +790,9 @@ + + CLEAR_HARD_REG_SET (bad_spill_regs_global); + +- /* Look for REG_EQUIV notes; record what each pseudo is equivalent +- to. Also find all paradoxical subregs and find largest such for +- each pseudo. */ +- +- num_eliminable_invariants = 0; +- for (insn = first; insn; insn = NEXT_INSN (insn)) +- { +- rtx set = single_set (insn); +- +- /* We may introduce USEs that we want to remove at the end, so +- we'll mark them with QImode. Make sure there are no +- previously-marked insns left by say regmove. */ +- if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE +- && GET_MODE (insn) != VOIDmode) +- PUT_MODE (insn, VOIDmode); +- +- if (NONDEBUG_INSN_P (insn)) +- scan_paradoxical_subregs (PATTERN (insn)); +- +- if (set != 0 && REG_P (SET_DEST (set))) +- { +- rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); +- rtx x; +- +- if (! note) +- continue; +- +- i = REGNO (SET_DEST (set)); +- x = XEXP (note, 0); +- +- if (i <= LAST_VIRTUAL_REGISTER) +- continue; +- +- if (! function_invariant_p (x) +- || ! flag_pic +- /* A function invariant is often CONSTANT_P but may +- include a register. We promise to only pass +- CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ +- || (CONSTANT_P (x) +- && LEGITIMATE_PIC_OPERAND_P (x))) +- { +- /* It can happen that a REG_EQUIV note contains a MEM +- that is not a legitimate memory operand. As later +- stages of reload assume that all addresses found +- in the reg_equiv_* arrays were originally legitimate, +- we ignore such REG_EQUIV notes. */ +- if (memory_operand (x, VOIDmode)) +- { +- /* Always unshare the equivalence, so we can +- substitute into this insn without touching the +- equivalence. */ +- reg_equiv_memory_loc[i] = copy_rtx (x); +- } +- else if (function_invariant_p (x)) +- { +- if (GET_CODE (x) == PLUS) +- { +- /* This is PLUS of frame pointer and a constant, +- and might be shared. Unshare it. */ +- reg_equiv_invariant[i] = copy_rtx (x); +- num_eliminable_invariants++; +- } +- else if (x == frame_pointer_rtx || x == arg_pointer_rtx) +- { +- reg_equiv_invariant[i] = x; +- num_eliminable_invariants++; +- } +- else if (LEGITIMATE_CONSTANT_P (x)) +- reg_equiv_constant[i] = x; +- else +- { +- reg_equiv_memory_loc[i] +- = force_const_mem (GET_MODE (SET_DEST (set)), x); +- if (! reg_equiv_memory_loc[i]) +- reg_equiv_init[i] = NULL_RTX; +- } +- } +- else +- { +- reg_equiv_init[i] = NULL_RTX; +- continue; +- } +- } +- else +- reg_equiv_init[i] = NULL_RTX; +- } +- } +- +- if (dump_file) +- for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) +- if (reg_equiv_init[i]) +- { +- fprintf (dump_file, "init_insns for %u: ", i); +- print_inline_rtx (dump_file, reg_equiv_init[i], 20); +- fprintf (dump_file, "\n"); +- } +- ++ init_eliminable_invariants (first, true); + init_elim_table (); + +- first_label_num = get_first_label_num (); +- num_labels = max_label_num () - first_label_num; +- +- /* Allocate the tables used to store offset information at labels. */ +- /* We used to use alloca here, but the size of what it would try to +- allocate would occasionally cause it to exceed the stack limit and +- cause a core dump. */ +- offsets_known_at = XNEWVEC (char, num_labels); +- offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); +- + /* Alter each pseudo-reg rtx to contain its hard reg number. Assign + stack slots to the pseudos that lack hard regs or equivalents. + Do not touch virtual registers. */ +@@ -1411,31 +1296,11 @@ + } + } + ++ free (temp_pseudo_reg_arr); ++ + /* Indicate that we no longer have known memory locations or constants. */ +- if (reg_equiv_constant) +- free (reg_equiv_constant); +- if (reg_equiv_invariant) +- free (reg_equiv_invariant); +- reg_equiv_constant = 0; +- reg_equiv_invariant = 0; +- VEC_free (rtx, gc, reg_equiv_memory_loc_vec); +- reg_equiv_memory_loc = 0; +- +- free (temp_pseudo_reg_arr); +- +- if (offsets_known_at) +- free (offsets_known_at); +- if (offsets_at) +- free (offsets_at); +- +- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) +- if (reg_equiv_alt_mem_list[i]) +- free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); +- free (reg_equiv_alt_mem_list); +- +- free (reg_equiv_mem); ++ free_reg_equiv (); + reg_equiv_init = 0; +- free (reg_equiv_address); + free (reg_max_ref_width); + free (reg_old_renumber); + free (pseudo_previous_regs); +@@ -1728,6 +1593,100 @@ + *pprev_reload = 0; + } + ++/* This function is called from the register allocator to set up estimates ++ for the cost of eliminating pseudos which have REG_EQUIV equivalences to ++ an invariant. The structure is similar to calculate_needs_all_insns. */ ++ ++void ++calculate_elim_costs_all_insns (void) ++{ ++ int *reg_equiv_init_cost; ++ basic_block bb; ++ int i; ++ ++ reg_equiv_init_cost = XCNEWVEC (int, max_regno); ++ init_elim_table (); ++ init_eliminable_invariants (get_insns (), false); ++ ++ set_initial_elim_offsets (); ++ set_initial_label_offsets (); ++ ++ FOR_EACH_BB (bb) ++ { ++ rtx insn; ++ elim_bb = bb; ++ ++ FOR_BB_INSNS (bb, insn) ++ { ++ /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might ++ include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see ++ what effects this has on the known offsets at labels. */ ++ ++ if (LABEL_P (insn) || JUMP_P (insn) ++ || (INSN_P (insn) && REG_NOTES (insn) != 0)) ++ set_label_offsets (insn, insn, 0); ++ ++ if (INSN_P (insn)) ++ { ++ rtx set = single_set (insn); ++ ++ /* Skip insns that only set an equivalence. */ ++ if (set && REG_P (SET_DEST (set)) ++ && reg_renumber[REGNO (SET_DEST (set))] < 0 ++ && (reg_equiv_constant[REGNO (SET_DEST (set))] ++ || (reg_equiv_invariant[REGNO (SET_DEST (set))]))) ++ { ++ unsigned regno = REGNO (SET_DEST (set)); ++ rtx init = reg_equiv_init[regno]; ++ if (init) ++ { ++ rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn, ++ false, true); ++ int cost = rtx_cost (t, SET, ++ optimize_bb_for_speed_p (bb)); ++ int freq = REG_FREQ_FROM_BB (bb); ++ ++ reg_equiv_init_cost[regno] = cost * freq; ++ continue; ++ } ++ } ++ /* If needed, eliminate any eliminable registers. */ ++ if (num_eliminable || num_eliminable_invariants) ++ elimination_costs_in_insn (insn); ++ ++ if (num_eliminable) ++ update_eliminable_offsets (); ++ } ++ } ++ } ++ for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) ++ { ++ if (reg_equiv_invariant[i]) ++ { ++ if (reg_equiv_init[i]) ++ { ++ int cost = reg_equiv_init_cost[i]; ++ if (dump_file) ++ fprintf (dump_file, ++ "Reg %d has equivalence, initial gains %d\n", i, cost); ++ if (cost != 0) ++ ira_adjust_equiv_reg_cost (i, cost); ++ } ++ else ++ { ++ if (dump_file) ++ fprintf (dump_file, ++ "Reg %d had equivalence, but can't be eliminated\n", ++ i); ++ ira_adjust_equiv_reg_cost (i, 0); ++ } ++ } ++ } ++ ++ free_reg_equiv (); ++ free (reg_equiv_init_cost); ++} ++ + /* Comparison function for qsort to decide which of two reloads + should be handled first. *P1 and *P2 are the reload numbers. */ + +@@ -2514,6 +2473,36 @@ + } + } + ++/* Called through for_each_rtx, this function examines every reg that occurs ++ in PX and adjusts the costs for its elimination which are gathered by IRA. ++ DATA is the insn in which PX occurs. We do not recurse into MEM ++ expressions. */ ++ ++static int ++note_reg_elim_costly (rtx *px, void *data) ++{ ++ rtx insn = (rtx)data; ++ rtx x = *px; ++ ++ if (MEM_P (x)) ++ return -1; ++ ++ if (REG_P (x) ++ && REGNO (x) >= FIRST_PSEUDO_REGISTER ++ && reg_equiv_init[REGNO (x)] ++ && reg_equiv_invariant[REGNO (x)]) ++ { ++ rtx t = reg_equiv_invariant[REGNO (x)]; ++ rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true); ++ int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb)); ++ int freq = REG_FREQ_FROM_BB (elim_bb); ++ ++ if (cost != 0) ++ ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq); ++ } ++ return 0; ++} ++ + /* Scan X and replace any eliminable registers (such as fp) with a + replacement (such as sp), plus an offset. + +@@ -2533,6 +2522,9 @@ + This means, do not set ref_outside_mem even if the reference + is outside of MEMs. + ++ If FOR_COSTS is true, we are being called before reload in order to ++ estimate the costs of keeping registers with an equivalence unallocated. ++ + REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had + replacements done assuming all offsets are at their initial values. If + they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we +@@ -2541,7 +2533,7 @@ + + static rtx + eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn, +- bool may_use_invariant) ++ bool may_use_invariant, bool for_costs) + { + enum rtx_code code = GET_CODE (x); + struct elim_table *ep; +@@ -2589,11 +2581,12 @@ + { + if (may_use_invariant || (insn && DEBUG_INSN_P (insn))) + return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]), +- mem_mode, insn, true); ++ mem_mode, insn, true, for_costs); + /* There exists at least one use of REGNO that cannot be + eliminated. Prevent the defining insn from being deleted. */ + reg_equiv_init[regno] = NULL_RTX; +- alter_reg (regno, -1, true); ++ if (!for_costs) ++ alter_reg (regno, -1, true); + } + return x; + +@@ -2654,8 +2647,10 @@ + operand of a load-address insn. */ + + { +- rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); +- rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); ++ rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true, ++ for_costs); ++ rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, ++ for_costs); + + if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) + { +@@ -2729,9 +2724,11 @@ + case GE: case GT: case GEU: case GTU: + case LE: case LT: case LEU: case LTU: + { +- rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); ++ rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false, ++ for_costs); + rtx new1 = XEXP (x, 1) +- ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0; ++ ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false, ++ for_costs) : 0; + + if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) + return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); +@@ -2742,7 +2739,8 @@ + /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ + if (XEXP (x, 0)) + { +- new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); ++ new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true, ++ for_costs); + if (new_rtx != XEXP (x, 0)) + { + /* If this is a REG_DEAD note, it is not valid anymore. +@@ -2750,7 +2748,8 @@ + REG_DEAD note for the stack or frame pointer. */ + if (REG_NOTE_KIND (x) == REG_DEAD) + return (XEXP (x, 1) +- ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true) ++ ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, ++ for_costs) + : NULL_RTX); + + x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); +@@ -2765,7 +2764,8 @@ + strictly needed, but it simplifies the code. */ + if (XEXP (x, 1)) + { +- new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); ++ new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, ++ for_costs); + if (new_rtx != XEXP (x, 1)) + return + gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx); +@@ -2791,7 +2791,7 @@ + && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) + { + rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, +- insn, true); ++ insn, true, for_costs); + + if (new_rtx != XEXP (XEXP (x, 1), 1)) + return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), +@@ -2814,7 +2814,8 @@ + case POPCOUNT: + case PARITY: + case BSWAP: +- new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); ++ new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false, ++ for_costs); + if (new_rtx != XEXP (x, 0)) + return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); + return x; +@@ -2835,7 +2836,8 @@ + new_rtx = SUBREG_REG (x); + } + else +- new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false); ++ new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, ++ for_costs); + + if (new_rtx != SUBREG_REG (x)) + { +@@ -2869,14 +2871,20 @@ + /* Our only special processing is to pass the mode of the MEM to our + recursive call and copy the flags. While we are here, handle this + case more efficiently. */ +- return +- replace_equiv_address_nv (x, +- eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), +- insn, true)); ++ ++ new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true, ++ for_costs); ++ if (for_costs ++ && memory_address_p (GET_MODE (x), XEXP (x, 0)) ++ && !memory_address_p (GET_MODE (x), new_rtx)) ++ for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn); ++ ++ return replace_equiv_address_nv (x, new_rtx); + + case USE: + /* Handle insn_list USE that a call to a pure function may generate. */ +- new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false); ++ new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false, ++ for_costs); + if (new_rtx != XEXP (x, 0)) + return gen_rtx_USE (GET_MODE (x), new_rtx); + return x; +@@ -2900,7 +2908,8 @@ + { + if (*fmt == 'e') + { +- new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false); ++ new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false, ++ for_costs); + if (new_rtx != XEXP (x, i) && ! copied) + { + x = shallow_copy_rtx (x); +@@ -2913,7 +2922,8 @@ + int copied_vec = 0; + for (j = 0; j < XVECLEN (x, i); j++) + { +- new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false); ++ new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false, ++ for_costs); + if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) + { + rtvec new_v = gen_rtvec_v (XVECLEN (x, i), +@@ -2937,7 +2947,7 @@ + rtx + eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) + { +- return eliminate_regs_1 (x, mem_mode, insn, false); ++ return eliminate_regs_1 (x, mem_mode, insn, false, false); + } + + /* Scan rtx X for modifications of elimination target registers. Update +@@ -3455,7 +3465,8 @@ + /* Companion to the above plus substitution, we can allow + invariants as the source of a plain move. */ + is_set_src = false; +- if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) ++ if (old_set ++ && recog_data.operand_loc[i] == &SET_SRC (old_set)) + is_set_src = true; + in_plus = false; + if (plus_src +@@ -3466,7 +3477,7 @@ + substed_operand[i] + = eliminate_regs_1 (recog_data.operand[i], VOIDmode, + replace ? insn : NULL_RTX, +- is_set_src || in_plus); ++ is_set_src || in_plus, false); + if (substed_operand[i] != orig_operand[i]) + val = 1; + /* Terminate the search in check_eliminable_occurrences at +@@ -3594,11 +3605,167 @@ + the pre-passes. */ + if (val && REG_NOTES (insn) != 0) + REG_NOTES (insn) +- = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true); ++ = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true, ++ false); + + return val; + } + ++/* Like eliminate_regs_in_insn, but only estimate costs for the use of the ++ register allocator. INSN is the instruction we need to examine, we perform ++ eliminations in its operands and record cases where eliminating a reg with ++ an invariant equivalence would add extra cost. */ ++ ++static void ++elimination_costs_in_insn (rtx insn) ++{ ++ int icode = recog_memoized (insn); ++ rtx old_body = PATTERN (insn); ++ int insn_is_asm = asm_noperands (old_body) >= 0; ++ rtx old_set = single_set (insn); ++ int i; ++ rtx orig_operand[MAX_RECOG_OPERANDS]; ++ rtx orig_dup[MAX_RECOG_OPERANDS]; ++ struct elim_table *ep; ++ rtx plus_src, plus_cst_src; ++ bool sets_reg_p; ++ ++ if (! insn_is_asm && icode < 0) ++ { ++ gcc_assert (GET_CODE (PATTERN (insn)) == USE ++ || GET_CODE (PATTERN (insn)) == CLOBBER ++ || GET_CODE (PATTERN (insn)) == ADDR_VEC ++ || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC ++ || GET_CODE (PATTERN (insn)) == ASM_INPUT ++ || DEBUG_INSN_P (insn)); ++ return; ++ } ++ ++ if (old_set != 0 && REG_P (SET_DEST (old_set)) ++ && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) ++ { ++ /* Check for setting an eliminable register. */ ++ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) ++ if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) ++ return; ++ } ++ ++ /* We allow one special case which happens to work on all machines we ++ currently support: a single set with the source or a REG_EQUAL ++ note being a PLUS of an eliminable register and a constant. */ ++ plus_src = plus_cst_src = 0; ++ sets_reg_p = false; ++ if (old_set && REG_P (SET_DEST (old_set))) ++ { ++ sets_reg_p = true; ++ if (GET_CODE (SET_SRC (old_set)) == PLUS) ++ plus_src = SET_SRC (old_set); ++ /* First see if the source is of the form (plus (...) CST). */ ++ if (plus_src ++ && CONST_INT_P (XEXP (plus_src, 1))) ++ plus_cst_src = plus_src; ++ else if (REG_P (SET_SRC (old_set)) ++ || plus_src) ++ { ++ /* Otherwise, see if we have a REG_EQUAL note of the form ++ (plus (...) CST). */ ++ rtx links; ++ for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) ++ { ++ if ((REG_NOTE_KIND (links) == REG_EQUAL ++ || REG_NOTE_KIND (links) == REG_EQUIV) ++ && GET_CODE (XEXP (links, 0)) == PLUS ++ && CONST_INT_P (XEXP (XEXP (links, 0), 1))) ++ { ++ plus_cst_src = XEXP (links, 0); ++ break; ++ } ++ } ++ } ++ } ++ ++ /* Determine the effects of this insn on elimination offsets. */ ++ elimination_effects (old_body, VOIDmode); ++ ++ /* Eliminate all eliminable registers occurring in operands that ++ can be handled by reload. */ ++ extract_insn (insn); ++ for (i = 0; i < recog_data.n_dups; i++) ++ orig_dup[i] = *recog_data.dup_loc[i]; ++ ++ for (i = 0; i < recog_data.n_operands; i++) ++ { ++ orig_operand[i] = recog_data.operand[i]; ++ ++ /* For an asm statement, every operand is eliminable. */ ++ if (insn_is_asm || insn_data[icode].operand[i].eliminable) ++ { ++ bool is_set_src, in_plus; ++ ++ /* Check for setting a register that we know about. */ ++ if (recog_data.operand_type[i] != OP_IN ++ && REG_P (orig_operand[i])) ++ { ++ /* If we are assigning to a register that can be eliminated, it ++ must be as part of a PARALLEL, since the code above handles ++ single SETs. We must indicate that we can no longer ++ eliminate this reg. */ ++ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ++ ep++) ++ if (ep->from_rtx == orig_operand[i]) ++ ep->can_eliminate = 0; ++ } ++ ++ /* Companion to the above plus substitution, we can allow ++ invariants as the source of a plain move. */ ++ is_set_src = false; ++ if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) ++ is_set_src = true; ++ if (is_set_src && !sets_reg_p) ++ note_reg_elim_costly (&SET_SRC (old_set), insn); ++ in_plus = false; ++ if (plus_src && sets_reg_p ++ && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) ++ || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) ++ in_plus = true; ++ ++ eliminate_regs_1 (recog_data.operand[i], VOIDmode, ++ NULL_RTX, ++ is_set_src || in_plus, true); ++ /* Terminate the search in check_eliminable_occurrences at ++ this point. */ ++ *recog_data.operand_loc[i] = 0; ++ } ++ } ++ ++ for (i = 0; i < recog_data.n_dups; i++) ++ *recog_data.dup_loc[i] ++ = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; ++ ++ /* If any eliminable remain, they aren't eliminable anymore. */ ++ check_eliminable_occurrences (old_body); ++ ++ /* Restore the old body. */ ++ for (i = 0; i < recog_data.n_operands; i++) ++ *recog_data.operand_loc[i] = orig_operand[i]; ++ for (i = 0; i < recog_data.n_dups; i++) ++ *recog_data.dup_loc[i] = orig_dup[i]; ++ ++ /* Update all elimination pairs to reflect the status after the current ++ insn. The changes we make were determined by the earlier call to ++ elimination_effects. */ ++ ++ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) ++ { ++ if (ep->previous_offset != ep->offset && ep->ref_outside_mem) ++ ep->can_eliminate = 0; ++ ++ ep->ref_outside_mem = 0; ++ } ++ ++ return; ++} ++ + /* Loop through all elimination pairs. + Recalculate the number not at initial offset. + +@@ -3908,6 +4075,168 @@ + ep->to_rtx = gen_rtx_REG (Pmode, ep->to); + } + } ++ ++/* Find all the pseudo registers that didn't get hard regs ++ but do have known equivalent constants or memory slots. ++ These include parameters (known equivalent to parameter slots) ++ and cse'd or loop-moved constant memory addresses. ++ ++ Record constant equivalents in reg_equiv_constant ++ so they will be substituted by find_reloads. ++ Record memory equivalents in reg_mem_equiv so they can ++ be substituted eventually by altering the REG-rtx's. */ ++ ++static void ++init_eliminable_invariants (rtx first, bool do_subregs) ++{ ++ int i; ++ rtx insn; ++ ++ reg_equiv_constant = XCNEWVEC (rtx, max_regno); ++ reg_equiv_invariant = XCNEWVEC (rtx, max_regno); ++ reg_equiv_mem = XCNEWVEC (rtx, max_regno); ++ reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); ++ reg_equiv_address = XCNEWVEC (rtx, max_regno); ++ if (do_subregs) ++ reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); ++ else ++ reg_max_ref_width = NULL; ++ ++ num_eliminable_invariants = 0; ++ ++ first_label_num = get_first_label_num (); ++ num_labels = max_label_num () - first_label_num; ++ ++ /* Allocate the tables used to store offset information at labels. */ ++ offsets_known_at = XNEWVEC (char, num_labels); ++ offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); ++ ++/* Look for REG_EQUIV notes; record what each pseudo is equivalent ++ to. If DO_SUBREGS is true, also find all paradoxical subregs and ++ find largest such for each pseudo. FIRST is the head of the insn ++ list. */ ++ ++ for (insn = first; insn; insn = NEXT_INSN (insn)) ++ { ++ rtx set = single_set (insn); ++ ++ /* We may introduce USEs that we want to remove at the end, so ++ we'll mark them with QImode. Make sure there are no ++ previously-marked insns left by say regmove. */ ++ if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE ++ && GET_MODE (insn) != VOIDmode) ++ PUT_MODE (insn, VOIDmode); ++ ++ if (do_subregs && NONDEBUG_INSN_P (insn)) ++ scan_paradoxical_subregs (PATTERN (insn)); ++ ++ if (set != 0 && REG_P (SET_DEST (set))) ++ { ++ rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); ++ rtx x; ++ ++ if (! note) ++ continue; ++ ++ i = REGNO (SET_DEST (set)); ++ x = XEXP (note, 0); ++ ++ if (i <= LAST_VIRTUAL_REGISTER) ++ continue; ++ ++ /* If flag_pic and we have constant, verify it's legitimate. */ ++ if (!CONSTANT_P (x) ++ || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) ++ { ++ /* It can happen that a REG_EQUIV note contains a MEM ++ that is not a legitimate memory operand. As later ++ stages of reload assume that all addresses found ++ in the reg_equiv_* arrays were originally legitimate, ++ we ignore such REG_EQUIV notes. */ ++ if (memory_operand (x, VOIDmode)) ++ { ++ /* Always unshare the equivalence, so we can ++ substitute into this insn without touching the ++ equivalence. */ ++ reg_equiv_memory_loc[i] = copy_rtx (x); ++ } ++ else if (function_invariant_p (x)) ++ { ++ if (GET_CODE (x) == PLUS) ++ { ++ /* This is PLUS of frame pointer and a constant, ++ and might be shared. Unshare it. */ ++ reg_equiv_invariant[i] = copy_rtx (x); ++ num_eliminable_invariants++; ++ } ++ else if (x == frame_pointer_rtx || x == arg_pointer_rtx) ++ { ++ reg_equiv_invariant[i] = x; ++ num_eliminable_invariants++; ++ } ++ else if (LEGITIMATE_CONSTANT_P (x)) ++ reg_equiv_constant[i] = x; ++ else ++ { ++ reg_equiv_memory_loc[i] ++ = force_const_mem (GET_MODE (SET_DEST (set)), x); ++ if (! reg_equiv_memory_loc[i]) ++ reg_equiv_init[i] = NULL_RTX; ++ } ++ } ++ else ++ { ++ reg_equiv_init[i] = NULL_RTX; ++ continue; ++ } ++ } ++ else ++ reg_equiv_init[i] = NULL_RTX; ++ } ++ } ++ ++ if (dump_file) ++ for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) ++ if (reg_equiv_init[i]) ++ { ++ fprintf (dump_file, "init_insns for %u: ", i); ++ print_inline_rtx (dump_file, reg_equiv_init[i], 20); ++ fprintf (dump_file, "\n"); ++ } ++} ++ ++/* Indicate that we no longer have known memory locations or constants. ++ Free all data involved in tracking these. */ ++ ++static void ++free_reg_equiv (void) ++{ ++ int i; ++ ++ if (reg_equiv_constant) ++ free (reg_equiv_constant); ++ if (reg_equiv_invariant) ++ free (reg_equiv_invariant); ++ reg_equiv_constant = 0; ++ reg_equiv_invariant = 0; ++ VEC_free (rtx, gc, reg_equiv_memory_loc_vec); ++ reg_equiv_memory_loc = 0; ++ ++ if (offsets_known_at) ++ free (offsets_known_at); ++ if (offsets_at) ++ free (offsets_at); ++ offsets_at = 0; ++ offsets_known_at = 0; ++ ++ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ++ if (reg_equiv_alt_mem_list[i]) ++ free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); ++ free (reg_equiv_alt_mem_list); ++ ++ free (reg_equiv_mem); ++ free (reg_equiv_address); ++} + + /* Kick all pseudos out of hard register REGNO. + +@@ -5664,7 +5993,7 @@ + return 1; + if (GET_CODE (x) == PLUS + && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) +- && CONSTANT_P (XEXP (x, 1))) ++ && GET_CODE (XEXP (x, 1)) == CONST_INT) + return 1; + return 0; + } + +=== modified file 'gcc/system.h' +--- old/gcc/system.h 2009-12-13 23:00:53 +0000 ++++ new/gcc/system.h 2010-09-01 13:29:58 +0000 +@@ -761,7 +761,8 @@ + TARGET_ASM_EXCEPTION_SECTION TARGET_ASM_EH_FRAME_SECTION \ + SMALL_ARG_MAX ASM_OUTPUT_SHARED_BSS ASM_OUTPUT_SHARED_COMMON \ + ASM_OUTPUT_SHARED_LOCAL ASM_MAKE_LABEL_LINKONCE \ +- STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD ++ STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD \ ++ ORDER_REGS_FOR_LOCAL_ALLOC + + /* Hooks that are no longer used. */ + #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE \ + +=== added file 'gcc/testsuite/c-c++-common/uninit-17.c' +--- old/gcc/testsuite/c-c++-common/uninit-17.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/c-c++-common/uninit-17.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,25 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -Wuninitialized" } */ ++ ++inline int foo(int x) ++{ ++ return x; ++} ++static void bar(int a, int *ptr) ++{ ++ do ++ { ++ int b; /* { dg-warning "is used uninitialized" } */ ++ if (b < 40) { ++ ptr[0] = b; ++ } ++ b += 1; ++ ptr++; ++ } ++ while (--a != 0); ++} ++void foobar(int a, int *ptr) ++{ ++ bar(foo(a), ptr); ++} ++ + +=== added file 'gcc/testsuite/gcc.target/arm/eliminate.c' +--- old/gcc/testsuite/gcc.target/arm/eliminate.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/eliminate.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++struct X ++{ ++ int c; ++}; ++ ++extern void bar(struct X *); ++ ++void foo () ++{ ++ struct X x; ++ bar (&x); ++ bar (&x); ++ bar (&x); ++} ++ ++/* { dg-final { scan-assembler-times "r0,\[\\t \]*sp" 3 } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/pr40900.c' +--- old/gcc/testsuite/gcc.target/arm/pr40900.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr40900.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fno-optimize-sibling-calls" } */ ++ ++extern short shortv2(); ++short shortv1() ++{ ++ return shortv2(); ++} ++ ++/* { dg-final { scan-assembler-not "lsl" } } */ ++/* { dg-final { scan-assembler-not "asr" } } */ ++/* { dg-final { scan-assembler-not "sxth" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/pr42496.c' +--- old/gcc/testsuite/gcc.target/arm/pr42496.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr42496.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,16 @@ ++/* { dg-options "-O2" } */ ++ ++void foo(int i) ++{ ++ extern int j; ++ ++ if (i) { ++ j = 10; ++ } ++ else { ++ j = 20; ++ } ++} ++ ++/* { dg-final { scan-assembler-not "strne" } } */ ++/* { dg-final { scan-assembler-not "streq" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/wmul-1.c' +--- old/gcc/testsuite/gcc.target/arm/wmul-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/wmul-1.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */ ++ ++int mac(const short *a, const short *b, int sqr, int *sum) ++{ ++ int i; ++ int dotp = *sum; ++ ++ for (i = 0; i < 150; i++) { ++ dotp += b[i] * a[i]; ++ sqr += b[i] * b[i]; ++ } ++ ++ *sum = dotp; ++ return sqr; ++} ++ ++/* { dg-final { scan-assembler-times "smulbb" 2 } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/wmul-2.c' +--- old/gcc/testsuite/gcc.target/arm/wmul-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/wmul-2.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */ ++ ++void vec_mpy(int y[], const short x[], short scaler) ++{ ++ int i; ++ ++ for (i = 0; i < 150; i++) ++ y[i] += ((scaler * x[i]) >> 31); ++} ++ ++/* { dg-final { scan-assembler-times "smulbb" 1 } } */ + +=== added file 'gcc/testsuite/gcc.target/bfin/wmul-1.c' +--- old/gcc/testsuite/gcc.target/bfin/wmul-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/bfin/wmul-1.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++int mac(const short *a, const short *b, int sqr, int *sum) ++{ ++ int i; ++ int dotp = *sum; ++ ++ for (i = 0; i < 150; i++) { ++ dotp += b[i] * a[i]; ++ sqr += b[i] * b[i]; ++ } ++ ++ *sum = dotp; ++ return sqr; ++} ++ ++/* { dg-final { scan-assembler-times "\\(IS\\)" 2 } } */ + +=== added file 'gcc/testsuite/gcc.target/bfin/wmul-2.c' +--- old/gcc/testsuite/gcc.target/bfin/wmul-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/bfin/wmul-2.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++void vec_mpy(int y[], const short x[], short scaler) ++{ ++ int i; ++ ++ for (i = 0; i < 150; i++) ++ y[i] += ((scaler * x[i]) >> 31); ++} ++ ++/* { dg-final { scan-assembler-times "\\(IS\\)" 1 } } */ + +=== added file 'gcc/testsuite/gcc.target/i386/pr41442.c' +--- old/gcc/testsuite/gcc.target/i386/pr41442.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/i386/pr41442.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++typedef struct LINK link; ++struct LINK ++{ ++ link* next; ++}; ++ ++int haha(link* p1, link* p2) ++{ ++ if ((p1->next && !p2->next) || p2->next) ++ return 0; ++ ++ return 1; ++} ++ ++/* { dg-final { scan-assembler-times "test|cmp" 2 } } */ + +=== added file 'gcc/testsuite/gcc.target/i386/wmul-1.c' +--- old/gcc/testsuite/gcc.target/i386/wmul-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/i386/wmul-1.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++long long mac(const int *a, const int *b, long long sqr, long long *sum) ++{ ++ int i; ++ long long dotp = *sum; ++ ++ for (i = 0; i < 150; i++) { ++ dotp += (long long)b[i] * a[i]; ++ sqr += (long long)b[i] * b[i]; ++ } ++ ++ *sum = dotp; ++ return sqr; ++} ++ ++/* { dg-final { scan-assembler-times "imull" 2 } } */ + +=== added file 'gcc/testsuite/gcc.target/i386/wmul-2.c' +--- old/gcc/testsuite/gcc.target/i386/wmul-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/i386/wmul-2.c 2010-09-01 13:29:58 +0000 +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++void vec_mpy(int y[], const int x[], int scaler) ++{ ++ int i; ++ ++ for (i = 0; i < 150; i++) ++ y[i] += (((long long)scaler * x[i]) >> 31); ++} ++ ++/* { dg-final { scan-assembler-times "imull" 1 } } */ + +=== modified file 'gcc/tree-cfg.c' +--- old/gcc/tree-cfg.c 2010-08-10 13:31:21 +0000 ++++ new/gcc/tree-cfg.c 2010-09-01 13:29:58 +0000 +@@ -3428,8 +3428,13 @@ + connected to the operand types. */ + return verify_gimple_comparison (lhs_type, rhs1, rhs2); + ++ case WIDEN_MULT_EXPR: ++ if (TREE_CODE (lhs_type) != INTEGER_TYPE) ++ return true; ++ return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type)) ++ || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type))); ++ + case WIDEN_SUM_EXPR: +- case WIDEN_MULT_EXPR: + case VEC_WIDEN_MULT_HI_EXPR: + case VEC_WIDEN_MULT_LO_EXPR: + case VEC_PACK_TRUNC_EXPR: + +=== modified file 'gcc/tree-inline.c' +--- old/gcc/tree-inline.c 2010-08-10 13:31:21 +0000 ++++ new/gcc/tree-inline.c 2010-09-01 13:29:58 +0000 +@@ -229,6 +229,7 @@ + regions of the CFG, but this is expensive to test. */ + if (id->entry_bb + && is_gimple_reg (SSA_NAME_VAR (name)) ++ && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (name) + && TREE_CODE (SSA_NAME_VAR (name)) != PARM_DECL + && (id->entry_bb != EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest + || EDGE_COUNT (id->entry_bb->preds) != 1)) + +=== modified file 'gcc/tree-pass.h' +--- old/gcc/tree-pass.h 2010-04-02 18:54:46 +0000 ++++ new/gcc/tree-pass.h 2010-09-01 13:29:58 +0000 +@@ -407,6 +407,7 @@ + extern struct gimple_opt_pass pass_cse_reciprocals; + extern struct gimple_opt_pass pass_cse_sincos; + extern struct gimple_opt_pass pass_optimize_bswap; ++extern struct gimple_opt_pass pass_optimize_widening_mul; + extern struct gimple_opt_pass pass_warn_function_return; + extern struct gimple_opt_pass pass_warn_function_noreturn; + extern struct gimple_opt_pass pass_cselim; + +=== modified file 'gcc/tree-ssa-math-opts.c' +--- old/gcc/tree-ssa-math-opts.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/tree-ssa-math-opts.c 2010-09-01 13:29:58 +0000 +@@ -1260,3 +1260,137 @@ + 0 /* todo_flags_finish */ + } + }; ++ ++/* Find integer multiplications where the operands are extended from ++ smaller types, and replace the MULT_EXPR with a WIDEN_MULT_EXPR ++ where appropriate. */ ++ ++static unsigned int ++execute_optimize_widening_mul (void) ++{ ++ bool changed = false; ++ basic_block bb; ++ ++ FOR_EACH_BB (bb) ++ { ++ gimple_stmt_iterator gsi; ++ ++ for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi); gsi_next (&gsi)) ++ { ++ gimple stmt = gsi_stmt (gsi); ++ gimple rhs1_stmt = NULL, rhs2_stmt = NULL; ++ tree type, type1 = NULL, type2 = NULL; ++ tree rhs1, rhs2, rhs1_convop = NULL, rhs2_convop = NULL; ++ enum tree_code rhs1_code, rhs2_code; ++ ++ if (!is_gimple_assign (stmt) ++ || gimple_assign_rhs_code (stmt) != MULT_EXPR) ++ continue; ++ ++ type = TREE_TYPE (gimple_assign_lhs (stmt)); ++ ++ if (TREE_CODE (type) != INTEGER_TYPE) ++ continue; ++ ++ rhs1 = gimple_assign_rhs1 (stmt); ++ rhs2 = gimple_assign_rhs2 (stmt); ++ ++ if (TREE_CODE (rhs1) == SSA_NAME) ++ { ++ rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); ++ if (!is_gimple_assign (rhs1_stmt)) ++ continue; ++ rhs1_code = gimple_assign_rhs_code (rhs1_stmt); ++ if (!CONVERT_EXPR_CODE_P (rhs1_code)) ++ continue; ++ rhs1_convop = gimple_assign_rhs1 (rhs1_stmt); ++ type1 = TREE_TYPE (rhs1_convop); ++ if (TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type)) ++ continue; ++ } ++ else if (TREE_CODE (rhs1) != INTEGER_CST) ++ continue; ++ ++ if (TREE_CODE (rhs2) == SSA_NAME) ++ { ++ rhs2_stmt = SSA_NAME_DEF_STMT (rhs2); ++ if (!is_gimple_assign (rhs2_stmt)) ++ continue; ++ rhs2_code = gimple_assign_rhs_code (rhs2_stmt); ++ if (!CONVERT_EXPR_CODE_P (rhs2_code)) ++ continue; ++ rhs2_convop = gimple_assign_rhs1 (rhs2_stmt); ++ type2 = TREE_TYPE (rhs2_convop); ++ if (TYPE_PRECISION (type2) * 2 != TYPE_PRECISION (type)) ++ continue; ++ } ++ else if (TREE_CODE (rhs2) != INTEGER_CST) ++ continue; ++ ++ if (rhs1_stmt == NULL && rhs2_stmt == NULL) ++ continue; ++ ++ /* Verify that the machine can perform a widening multiply in this ++ mode/signedness combination, otherwise this transformation is ++ likely to pessimize code. */ ++ if ((rhs1_stmt == NULL || TYPE_UNSIGNED (type1)) ++ && (rhs2_stmt == NULL || TYPE_UNSIGNED (type2)) ++ && (optab_handler (umul_widen_optab, TYPE_MODE (type)) ++ ->insn_code == CODE_FOR_nothing)) ++ continue; ++ else if ((rhs1_stmt == NULL || !TYPE_UNSIGNED (type1)) ++ && (rhs2_stmt == NULL || !TYPE_UNSIGNED (type2)) ++ && (optab_handler (smul_widen_optab, TYPE_MODE (type)) ++ ->insn_code == CODE_FOR_nothing)) ++ continue; ++ else if (rhs1_stmt != NULL && rhs2_stmt != 0 ++ && (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) ++ && (optab_handler (usmul_widen_optab, TYPE_MODE (type)) ++ ->insn_code == CODE_FOR_nothing)) ++ continue; ++ ++ if ((rhs1_stmt == NULL && !int_fits_type_p (rhs1, type2)) ++ || (rhs2_stmt == NULL && !int_fits_type_p (rhs2, type1))) ++ continue; ++ ++ if (rhs1_stmt == NULL) ++ gimple_assign_set_rhs1 (stmt, fold_convert (type2, rhs1)); ++ else ++ gimple_assign_set_rhs1 (stmt, rhs1_convop); ++ if (rhs2_stmt == NULL) ++ gimple_assign_set_rhs2 (stmt, fold_convert (type1, rhs2)); ++ else ++ gimple_assign_set_rhs2 (stmt, rhs2_convop); ++ gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR); ++ update_stmt (stmt); ++ changed = true; ++ } ++ } ++ return (changed ? TODO_dump_func | TODO_update_ssa | TODO_verify_ssa ++ | TODO_verify_stmts : 0); ++} ++ ++static bool ++gate_optimize_widening_mul (void) ++{ ++ return flag_expensive_optimizations && optimize; ++} ++ ++struct gimple_opt_pass pass_optimize_widening_mul = ++{ ++ { ++ GIMPLE_PASS, ++ "widening_mul", /* name */ ++ gate_optimize_widening_mul, /* gate */ ++ execute_optimize_widening_mul, /* execute */ ++ NULL, /* sub */ ++ NULL, /* next */ ++ 0, /* static_pass_number */ ++ TV_NONE, /* tv_id */ ++ PROP_ssa, /* properties_required */ ++ 0, /* properties_provided */ ++ 0, /* properties_destroyed */ ++ 0, /* todo_flags_start */ ++ 0 /* todo_flags_finish */ ++ } ++}; + +=== modified file 'gcc/tree-ssa.c' +--- old/gcc/tree-ssa.c 2009-12-07 22:42:10 +0000 ++++ new/gcc/tree-ssa.c 2010-09-01 13:29:58 +0000 +@@ -1671,6 +1671,8 @@ + { + TREE_NO_WARNING (var) = 1; + ++ if (location == DECL_SOURCE_LOCATION (var)) ++ return; + if (xloc.file != floc.file + || xloc.line < floc.line + || xloc.line > LOCATION_LINE (cfun->function_end_locus)) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch new file mode 100644 index 0000000000..c504f44fbe --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch @@ -0,0 +1,512 @@ +2010-09-06 Mark Mitchell + + Issue #9022 + + Backport from mainline: + 2010-09-05 Mark Mitchell + * doc/invoke.texi: Document -Wdouble-promotion. + * c-typeck.c (convert_arguments): Check for implicit conversions + from float to double. + (do_warn_double_promotion): New function. + (build_conditional_expr): Use it. + (build_binary_op): Likewise. + * c.opt (Wdouble-promotion): New. + 2010-09-05 Mark Mitchell + * gcc.dg/Wdouble-promotion.c: New. + 2010-09-06 Mark Mitchell + gcc/ + * c-common.h (do_warn_double_promotion): Declare. + * c-common.c (do_warn_double_promotion): Define. + * c-typeck.c (do_warn_double_promotion): Remove. + * doc/invoke.texi (-Wdouble-promotion): Note available for C++ and + Objective-C++ too. + gcc/cp/ + * typeck.c (cp_build_binary_op): Call do_warn_double_promotion. + * call.c (build_conditional_expr): Likewise. + (convert_arg_to_ellipsis): Likewise. + gcc/testsuite/ + * g++.dg/warn/Wdouble-promotion.C: New. + + 2010-08-31 Chung-Lin Tang + + Backport from mainline: + +=== modified file 'gcc/c-common.c' +--- old/gcc/c-common.c 2010-06-25 09:35:40 +0000 ++++ new/gcc/c-common.c 2010-09-07 15:47:57 +0000 +@@ -9172,6 +9172,40 @@ + } + } + ++/* RESULT_TYPE is the result of converting TYPE1 and TYPE2 to a common ++ type via c_common_type. If -Wdouble-promotion is in use, and the ++ conditions for warning have been met, issue a warning. GMSGID is ++ the warning message. It must have two %T specifiers for the type ++ that was converted (generally "float") and the type to which it was ++ converted (generally "double), respectively. LOC is the location ++ to which the awrning should refer. */ ++ ++void ++do_warn_double_promotion (tree result_type, tree type1, tree type2, ++ const char *gmsgid, location_t loc) ++{ ++ tree source_type; ++ ++ if (!warn_double_promotion) ++ return; ++ /* If the conversion will not occur at run-time, there is no need to ++ warn about it. */ ++ if (c_inhibit_evaluation_warnings) ++ return; ++ if (TYPE_MAIN_VARIANT (result_type) != double_type_node ++ && TYPE_MAIN_VARIANT (result_type) != complex_double_type_node) ++ return; ++ if (TYPE_MAIN_VARIANT (type1) == float_type_node ++ || TYPE_MAIN_VARIANT (type1) == complex_float_type_node) ++ source_type = type1; ++ else if (TYPE_MAIN_VARIANT (type2) == float_type_node ++ || TYPE_MAIN_VARIANT (type2) == complex_float_type_node) ++ source_type = type2; ++ else ++ return; ++ warning_at (loc, OPT_Wdouble_promotion, gmsgid, source_type, result_type); ++} ++ + /* Setup a TYPE_DECL node as a typedef representation. + + X is a TYPE_DECL for a typedef statement. Create a brand new + +=== modified file 'gcc/c-common.h' +--- old/gcc/c-common.h 2009-12-17 03:22:22 +0000 ++++ new/gcc/c-common.h 2010-09-07 15:47:57 +0000 +@@ -1056,6 +1056,8 @@ + tree op0, tree op1, + tree result_type, + enum tree_code resultcode); ++extern void do_warn_double_promotion (tree, tree, tree, const char *, ++ location_t); + extern void set_underlying_type (tree x); + extern bool is_typedef_decl (tree x); + extern VEC(tree,gc) *make_tree_vector (void); + +=== modified file 'gcc/c-typeck.c' +--- old/gcc/c-typeck.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/c-typeck.c 2010-09-07 15:47:57 +0000 +@@ -3012,8 +3012,15 @@ + if (type_generic) + parmval = val; + else +- /* Convert `float' to `double'. */ +- parmval = convert (double_type_node, val); ++ { ++ /* Convert `float' to `double'. */ ++ if (warn_double_promotion && !c_inhibit_evaluation_warnings) ++ warning (OPT_Wdouble_promotion, ++ "implicit conversion from %qT to %qT when passing " ++ "argument to function", ++ valtype, double_type_node); ++ parmval = convert (double_type_node, val); ++ } + } + else if (excess_precision && !type_generic) + /* A "double" argument with excess precision being passed +@@ -4036,6 +4043,10 @@ + || code2 == COMPLEX_TYPE)) + { + result_type = c_common_type (type1, type2); ++ do_warn_double_promotion (result_type, type1, type2, ++ "implicit conversion from %qT to %qT to " ++ "match other result of conditional", ++ colon_loc); + + /* If -Wsign-compare, warn here if type1 and type2 have + different signedness. We'll promote the signed to unsigned +@@ -9607,6 +9618,11 @@ + if (shorten || common || short_compare) + { + result_type = c_common_type (type0, type1); ++ do_warn_double_promotion (result_type, type0, type1, ++ "implicit conversion from %qT to %qT " ++ "to match other operand of binary " ++ "expression", ++ location); + if (result_type == error_mark_node) + return error_mark_node; + } + +=== modified file 'gcc/c.opt' +--- old/gcc/c.opt 2010-04-02 18:54:46 +0000 ++++ new/gcc/c.opt 2010-09-07 15:47:57 +0000 +@@ -265,6 +265,10 @@ + Wimplicit + C ObjC C++ ObjC++ Warning + ++Wdouble-promotion ++C ObjC C++ ObjC++ Var(warn_double_promotion) Warning ++Warn about implicit conversions from \"float\" to \"double\" ++ + Wimplicit-function-declaration + C ObjC Var(warn_implicit_function_declaration) Init(-1) Warning + Warn about implicit function declarations + +=== modified file 'gcc/cp/call.c' +--- old/gcc/cp/call.c 2010-07-08 13:08:36 +0000 ++++ new/gcc/cp/call.c 2010-09-07 15:47:57 +0000 +@@ -3946,6 +3946,10 @@ + /* In this case, there is always a common type. */ + result_type = type_after_usual_arithmetic_conversions (arg2_type, + arg3_type); ++ do_warn_double_promotion (result_type, arg2_type, arg3_type, ++ "implicit conversion from %qT to %qT to " ++ "match other result of conditional", ++ input_location); + + if (TREE_CODE (arg2_type) == ENUMERAL_TYPE + && TREE_CODE (arg3_type) == ENUMERAL_TYPE) +@@ -5179,11 +5183,14 @@ + tree + convert_arg_to_ellipsis (tree arg) + { ++ tree arg_type; ++ + /* [expr.call] + + The lvalue-to-rvalue, array-to-pointer, and function-to-pointer + standard conversions are performed. */ + arg = decay_conversion (arg); ++ arg_type = TREE_TYPE (arg); + /* [expr.call] + + If the argument has integral or enumeration type that is subject +@@ -5191,19 +5198,27 @@ + type that is subject to the floating point promotion + (_conv.fpprom_), the value of the argument is converted to the + promoted type before the call. */ +- if (TREE_CODE (TREE_TYPE (arg)) == REAL_TYPE +- && (TYPE_PRECISION (TREE_TYPE (arg)) ++ if (TREE_CODE (arg_type) == REAL_TYPE ++ && (TYPE_PRECISION (arg_type) + < TYPE_PRECISION (double_type_node)) +- && !DECIMAL_FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (arg)))) +- arg = convert_to_real (double_type_node, arg); +- else if (INTEGRAL_OR_ENUMERATION_TYPE_P (TREE_TYPE (arg))) ++ && !DECIMAL_FLOAT_MODE_P (TYPE_MODE (arg_type))) ++ { ++ if (warn_double_promotion && !c_inhibit_evaluation_warnings) ++ warning (OPT_Wdouble_promotion, ++ "implicit conversion from %qT to %qT when passing " ++ "argument to function", ++ arg_type, double_type_node); ++ arg = convert_to_real (double_type_node, arg); ++ } ++ else if (INTEGRAL_OR_ENUMERATION_TYPE_P (arg_type)) + arg = perform_integral_promotions (arg); + + arg = require_complete_type (arg); ++ arg_type = TREE_TYPE (arg); + + if (arg != error_mark_node +- && (type_has_nontrivial_copy_init (TREE_TYPE (arg)) +- || TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (arg)))) ++ && (type_has_nontrivial_copy_init (arg_type) ++ || TYPE_HAS_NONTRIVIAL_DESTRUCTOR (arg_type))) + { + /* [expr.call] 5.2.2/7: + Passing a potentially-evaluated argument of class type (Clause 9) +@@ -5218,7 +5233,7 @@ + it is not potentially-evaluated. */ + if (cp_unevaluated_operand == 0) + error ("cannot pass objects of non-trivially-copyable " +- "type %q#T through %<...%>", TREE_TYPE (arg)); ++ "type %q#T through %<...%>", arg_type); + } + + return arg; + +=== modified file 'gcc/cp/typeck.c' +--- old/gcc/cp/typeck.c 2010-06-30 21:06:28 +0000 ++++ new/gcc/cp/typeck.c 2010-09-07 15:47:57 +0000 +@@ -260,6 +260,7 @@ + enum tree_code code2 = TREE_CODE (t2); + tree attributes; + ++ + /* In what follows, we slightly generalize the rules given in [expr] so + as to deal with `long long' and `complex'. First, merge the + attributes. */ +@@ -4226,7 +4227,14 @@ + if (!result_type + && arithmetic_types_p + && (shorten || common || short_compare)) +- result_type = cp_common_type (type0, type1); ++ { ++ result_type = cp_common_type (type0, type1); ++ do_warn_double_promotion (result_type, type0, type1, ++ "implicit conversion from %qT to %qT " ++ "to match other operand of binary " ++ "expression", ++ location); ++ } + + if (!result_type) + { + +=== modified file 'gcc/doc/invoke.texi' +--- old/gcc/doc/invoke.texi 2010-08-16 09:41:58 +0000 ++++ new/gcc/doc/invoke.texi 2010-09-07 15:47:57 +0000 +@@ -234,8 +234,8 @@ + -Wchar-subscripts -Wclobbered -Wcomment @gol + -Wconversion -Wcoverage-mismatch -Wno-deprecated @gol + -Wno-deprecated-declarations -Wdisabled-optimization @gol +--Wno-div-by-zero -Wempty-body -Wenum-compare -Wno-endif-labels @gol +--Werror -Werror=* @gol ++-Wno-div-by-zero -Wdouble-promotion -Wempty-body -Wenum-compare @gol ++-Wno-endif-labels -Werror -Werror=* @gol + -Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol + -Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol + -Wformat-security -Wformat-y2k @gol +@@ -2976,6 +2976,30 @@ + comment, or whenever a Backslash-Newline appears in a @samp{//} comment. + This warning is enabled by @option{-Wall}. + ++@item -Wdouble-promotion @r{(C, C++, Objective-C and Objective-C++ only)} ++@opindex Wdouble-promotion ++@opindex Wno-double-promotion ++Give a warning when a value of type @code{float} is implicitly ++promoted to @code{double}. CPUs with a 32-bit ``single-precision'' ++floating-point unit implement @code{float} in hardware, but emulate ++@code{double} in software. On such a machine, doing computations ++using @code{double} values is much more expensive because of the ++overhead required for software emulation. ++ ++It is easy to accidentally do computations with @code{double} because ++floating-point literals are implicitly of type @code{double}. For ++example, in: ++@smallexample ++@group ++float area(float radius) ++@{ ++ return 3.14159 * radius * radius; ++@} ++@end group ++@end smallexample ++the compiler will perform the entire computation with @code{double} ++because the floating-point literal is a @code{double}. ++ + @item -Wformat + @opindex Wformat + @opindex Wno-format + +=== added file 'gcc/testsuite/g++.dg/warn/Wdouble-promotion.C' +--- old/gcc/testsuite/g++.dg/warn/Wdouble-promotion.C 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/g++.dg/warn/Wdouble-promotion.C 2010-09-07 15:47:57 +0000 +@@ -0,0 +1,99 @@ ++/* { dg-do compile } */ ++/* { dg-options "-Wdouble-promotion" } */ ++ ++#include ++ ++/* Some targets do not provide so we define I ourselves. */ ++#define I 1.0iF ++#define ID ((_Complex double)I) ++ ++float f; ++double d; ++int i; ++long double ld; ++_Complex float cf; ++_Complex double cd; ++_Complex long double cld; ++size_t s; ++ ++extern void varargs_fn (int, ...); ++extern void double_fn (double); ++extern float float_fn (void); ++ ++void ++usual_arithmetic_conversions(void) ++{ ++ float local_f; ++ _Complex float local_cf; ++ ++ /* Values of type "float" are implicitly converted to "double" or ++ "long double" due to use in arithmetic with "double" or "long ++ double" operands. */ ++ local_f = f + 1.0; /* { dg-warning "implicit" } */ ++ local_f = f - d; /* { dg-warning "implicit" } */ ++ local_f = 1.0f * 1.0; /* { dg-warning "implicit" } */ ++ local_f = 1.0f / d; /* { dg-warning "implicit" } */ ++ ++ local_cf = cf + 1.0; /* { dg-warning "implicit" } */ ++ local_cf = cf - d; /* { dg-warning "implicit" } */ ++ local_cf = cf + 1.0 * ID; /* { dg-warning "implicit" } */ ++ local_cf = cf - cd; /* { dg-warning "implicit" } */ ++ ++ local_f = i ? f : d; /* { dg-warning "implicit" } */ ++ i = f == d; /* { dg-warning "implicit" } */ ++ i = d != f; /* { dg-warning "implicit" } */ ++} ++ ++void ++default_argument_promotion (void) ++{ ++ /* Because "f" is part of the variable argument list, it is promoted ++ to "double". */ ++ varargs_fn (1, f); /* { dg-warning "implicit" } */ ++} ++ ++/* There is no warning when an explicit cast is used to perform the ++ conversion. */ ++ ++void ++casts (void) ++{ ++ float local_f; ++ _Complex float local_cf; ++ ++ local_f = (double)f + 1.0; /* { dg-bogus "implicit" } */ ++ local_f = (double)f - d; /* { dg-bogus "implicit" } */ ++ local_f = (double)1.0f + 1.0; /* { dg-bogus "implicit" } */ ++ local_f = (double)1.0f - d; /* { dg-bogus "implicit" } */ ++ ++ local_cf = (_Complex double)cf + 1.0; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf - d; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf + 1.0 * ID; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf - cd; /* { dg-bogus "implicit" } */ ++ ++ local_f = i ? (double)f : d; /* { dg-bogus "implicit" } */ ++ i = (double)f == d; /* { dg-bogus "implicit" } */ ++ i = d != (double)f; /* { dg-bogus "implicit" } */ ++} ++ ++/* There is no warning on conversions that occur in assignment (and ++ assignment-like) contexts. */ ++ ++void ++assignments (void) ++{ ++ d = f; /* { dg-bogus "implicit" } */ ++ double_fn (f); /* { dg-bogus "implicit" } */ ++ d = float_fn (); /* { dg-bogus "implicit" } */ ++} ++ ++/* There is no warning in non-evaluated contexts. */ ++ ++void ++non_evaluated (void) ++{ ++ s = sizeof (f + 1.0); /* { dg-bogus "implicit" } */ ++ s = __alignof__ (f + 1.0); /* { dg-bogus "implicit" } */ ++ d = (__typeof__(f + 1.0))f; /* { dg-bogus "implicit" } */ ++ s = sizeof (i ? f : d); /* { dg-bogus "implicit" } */ ++} + +=== added file 'gcc/testsuite/gcc.dg/Wdouble-promotion.c' +--- old/gcc/testsuite/gcc.dg/Wdouble-promotion.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/Wdouble-promotion.c 2010-09-07 15:47:57 +0000 +@@ -0,0 +1,104 @@ ++/* { dg-do compile } */ ++/* { dg-options "-Wdouble-promotion" } */ ++ ++#include ++ ++/* Some targets do not provide so we define I ourselves. */ ++#define I 1.0iF ++#define ID ((_Complex double)I) ++ ++float f; ++double d; ++int i; ++long double ld; ++_Complex float cf; ++_Complex double cd; ++_Complex long double cld; ++size_t s; ++ ++extern void unprototyped_fn (); ++extern void varargs_fn (int, ...); ++extern void double_fn (double); ++extern float float_fn (void); ++ ++void ++usual_arithmetic_conversions(void) ++{ ++ float local_f; ++ _Complex float local_cf; ++ ++ /* Values of type "float" are implicitly converted to "double" or ++ "long double" due to use in arithmetic with "double" or "long ++ double" operands. */ ++ local_f = f + 1.0; /* { dg-warning "implicit" } */ ++ local_f = f - d; /* { dg-warning "implicit" } */ ++ local_f = 1.0f * 1.0; /* { dg-warning "implicit" } */ ++ local_f = 1.0f / d; /* { dg-warning "implicit" } */ ++ ++ local_cf = cf + 1.0; /* { dg-warning "implicit" } */ ++ local_cf = cf - d; /* { dg-warning "implicit" } */ ++ local_cf = cf + 1.0 * ID; /* { dg-warning "implicit" } */ ++ local_cf = cf - cd; /* { dg-warning "implicit" } */ ++ ++ local_f = i ? f : d; /* { dg-warning "implicit" } */ ++ i = f == d; /* { dg-warning "implicit" } */ ++ i = d != f; /* { dg-warning "implicit" } */ ++} ++ ++void ++default_argument_promotion (void) ++{ ++ /* Because there is no prototype, "f" is promoted to "double". */ ++ unprototyped_fn (f); /* { dg-warning "implicit" } */ ++ undeclared_fn (f); /* { dg-warning "implicit" } */ ++ /* Because "f" is part of the variable argument list, it is promoted ++ to "double". */ ++ varargs_fn (1, f); /* { dg-warning "implicit" } */ ++} ++ ++/* There is no warning when an explicit cast is used to perform the ++ conversion. */ ++ ++void ++casts (void) ++{ ++ float local_f; ++ _Complex float local_cf; ++ ++ local_f = (double)f + 1.0; /* { dg-bogus "implicit" } */ ++ local_f = (double)f - d; /* { dg-bogus "implicit" } */ ++ local_f = (double)1.0f + 1.0; /* { dg-bogus "implicit" } */ ++ local_f = (double)1.0f - d; /* { dg-bogus "implicit" } */ ++ ++ local_cf = (_Complex double)cf + 1.0; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf - d; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf + 1.0 * ID; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf - cd; /* { dg-bogus "implicit" } */ ++ ++ local_f = i ? (double)f : d; /* { dg-bogus "implicit" } */ ++ i = (double)f == d; /* { dg-bogus "implicit" } */ ++ i = d != (double)f; /* { dg-bogus "implicit" } */ ++} ++ ++/* There is no warning on conversions that occur in assignment (and ++ assignment-like) contexts. */ ++ ++void ++assignments (void) ++{ ++ d = f; /* { dg-bogus "implicit" } */ ++ double_fn (f); /* { dg-bogus "implicit" } */ ++ d = float_fn (); /* { dg-bogus "implicit" } */ ++} ++ ++/* There is no warning in non-evaluated contexts. */ ++ ++void ++non_evaluated (void) ++{ ++ s = sizeof (f + 1.0); /* { dg-bogus "implicit" } */ ++ s = __alignof__ (f + 1.0); /* { dg-bogus "implicit" } */ ++ d = (__typeof__(f + 1.0))f; /* { dg-bogus "implicit" } */ ++ s = sizeof (i ? f : d); /* { dg-bogus "implicit" } */ ++ s = sizeof (unprototyped_fn (f)); /* { dg-bogus "implicit" } */ ++} + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch new file mode 100644 index 0000000000..82a9e93e43 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch @@ -0,0 +1,369 @@ +2010-09-09 Andrew Stubbs + + Backport from mainline: + + 2010-08-25 Tejas Belagod + * config/arm/iterators.md (VU, SE, V_widen_l): New. + (V_unpack, US): New. + * config/arm/neon.md (vec_unpack_hi_): Expansion for + vmovl. + (vec_unpack_lo_): Likewise. + (neon_vec_unpack_hi_): Instruction pattern for vmovl. + (neon_vec_unpack_lo_): Likewise. + (vec_widen_mult_lo_): Expansion for vmull. + (vec_widen_mult_hi_): Likewise. + (neon_vec_mult_lo_"): Instruction pattern for vmull. + (neon_vec_mult_hi_"): Likewise. + (neon_unpack_): Widening move intermediate step for + vectorizing without -mvectorize-with-neon-quad. + (neon_vec_mult_): Widening multiply intermediate step + for vectorizing without -mvectorize-with-neon-quad. + * config/arm/predicates.md (vect_par_constant_high): Check for + high-half lanes of a vector. + (vect_par_constant_low): Check for low-half lanes of a vector. + + 2010-08-25 Tejas Belagod + * lib/target-supports.exp (check_effective_target_vect_unpack): + Set vect_unpack supported flag to true for neon. + + 2010-09-07 Andrew Stubbs + + Backport from gcc-patches: + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-09-01 13:29:58 +0000 ++++ new/gcc/config/arm/arm.md 2010-09-09 14:11:34 +0000 +@@ -868,6 +868,9 @@ + (define_code_attr cnb [(ltu "CC_C") (geu "CC")]) + (define_code_attr optab [(ltu "ltu") (geu "geu")]) + ++;; Assembler mnemonics for signedness of widening operations. ++(define_code_attr US [(sign_extend "s") (zero_extend "u")]) ++ + (define_insn "*addsi3_carryin_" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2010-08-23 14:29:45 +0000 ++++ new/gcc/config/arm/neon.md 2010-09-09 14:11:34 +0000 +@@ -235,6 +235,9 @@ + ;; Modes with 32-bit elements only. + (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) + ++;; Modes with 8-bit, 16-bit and 32-bit elements. ++(define_mode_iterator VU [V16QI V8HI V4SI]) ++ + ;; (Opposite) mode to convert to/from for above conversions. + (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") + (V4SI "V4SF") (V4SF "V4SI")]) +@@ -388,6 +391,9 @@ + ;; Same, without unsigned variants (for use with *SFmode pattern). + (define_code_iterator vqhs_ops [plus smin smax]) + ++;; A list of widening operators ++(define_code_iterator SE [sign_extend zero_extend]) ++ + ;; Assembler mnemonics for above codes. + (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") + (umin "vmin") (umax "vmax")]) +@@ -443,6 +449,12 @@ + (V2SF "2") (V4SF "4") + (DI "1") (V2DI "2")]) + ++;; Same as V_widen, but lower-case. ++(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) ++ ++;; Widen. Result is half the number of elements, but widened to double-width. ++(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) ++ + (define_insn "*neon_mov" + [(set (match_operand:VD 0 "nonimmediate_operand" + "=w,Uv,w, w, ?r,?w,?r,?r, ?Us") +@@ -5540,3 +5552,205 @@ + emit_insn (gen_orn3_neon (operands[0], operands[1], operands[2])); + DONE; + }) ++ ++(define_insn "neon_vec_unpack_lo_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (SE: (vec_select: ++ (match_operand:VU 1 "register_operand" "w") ++ (match_operand:VU 2 "vect_par_constant_low" ""))))] ++ "TARGET_NEON" ++ "vmovl. %q0, %e1" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_insn "neon_vec_unpack_hi_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (SE: (vec_select: ++ (match_operand:VU 1 "register_operand" "w") ++ (match_operand:VU 2 "vect_par_constant_high" ""))))] ++ "TARGET_NEON" ++ "vmovl. %q0, %f1" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_unpack_hi_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VU 1 "register_operand"))] ++ "TARGET_NEON" ++ { ++ rtvec v = rtvec_alloc (/2) ; ++ rtx t1; ++ int i; ++ for (i = 0; i < (/2); i++) ++ RTVEC_ELT (v, i) = GEN_INT ((/2) + i); ++ ++ t1 = gen_rtx_PARALLEL (mode, v); ++ emit_insn (gen_neon_vec_unpack_hi_ (operands[0], ++ operands[1], ++ t1)); ++ DONE; ++ } ++) ++ ++(define_expand "vec_unpack_lo_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VU 1 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtvec v = rtvec_alloc (/2) ; ++ rtx t1; ++ int i; ++ for (i = 0; i < (/2) ; i++) ++ RTVEC_ELT (v, i) = GEN_INT (i); ++ t1 = gen_rtx_PARALLEL (mode, v); ++ emit_insn (gen_neon_vec_unpack_lo_ (operands[0], ++ operands[1], ++ t1)); ++ DONE; ++ } ++) ++ ++(define_insn "neon_vec_mult_lo_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (mult: (SE: (vec_select: ++ (match_operand:VU 1 "register_operand" "w") ++ (match_operand:VU 2 "vect_par_constant_low" ""))) ++ (SE: (vec_select: ++ (match_operand:VU 3 "register_operand" "w") ++ (match_dup 2)))))] ++ "TARGET_NEON" ++ "vmull. %q0, %e1, %e3" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_widen_mult_lo_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VU 1 "register_operand" "")) ++ (SE: (match_operand:VU 2 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtvec v = rtvec_alloc (/2) ; ++ rtx t1; ++ int i; ++ for (i = 0; i < (/2) ; i++) ++ RTVEC_ELT (v, i) = GEN_INT (i); ++ t1 = gen_rtx_PARALLEL (mode, v); ++ ++ emit_insn (gen_neon_vec_mult_lo_ (operands[0], ++ operands[1], ++ t1, ++ operands[2])); ++ DONE; ++ } ++) ++ ++(define_insn "neon_vec_mult_hi_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (mult: (SE: (vec_select: ++ (match_operand:VU 1 "register_operand" "w") ++ (match_operand:VU 2 "vect_par_constant_high" ""))) ++ (SE: (vec_select: ++ (match_operand:VU 3 "register_operand" "w") ++ (match_dup 2)))))] ++ "TARGET_NEON" ++ "vmull. %q0, %f1, %f3" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_widen_mult_hi_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VU 1 "register_operand" "")) ++ (SE: (match_operand:VU 2 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtvec v = rtvec_alloc (/2) ; ++ rtx t1; ++ int i; ++ for (i = 0; i < (/2) ; i++) ++ RTVEC_ELT (v, i) = GEN_INT (/2 + i); ++ t1 = gen_rtx_PARALLEL (mode, v); ++ ++ emit_insn (gen_neon_vec_mult_hi_ (operands[0], ++ operands[1], ++ t1, ++ operands[2])); ++ DONE; ++ ++ } ++) ++ ++;; Vectorize for non-neon-quad case ++(define_insn "neon_unpack_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (SE: (match_operand:VDI 1 "register_operand" "")))] ++ "TARGET_NEON" ++ "vmovl. %q0, %1" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_unpack_lo_" ++ [(match_operand: 0 "register_operand" "") ++ (SE:(match_operand:VDI 1 "register_operand"))] ++ "TARGET_NEON" ++{ ++ rtx tmpreg = gen_reg_rtx (mode); ++ emit_insn (gen_neon_unpack_ (tmpreg, operands[1])); ++ emit_insn (gen_neon_vget_low (operands[0], tmpreg)); ++ ++ DONE; ++} ++) ++ ++(define_expand "vec_unpack_hi_" ++ [(match_operand: 0 "register_operand" "") ++ (SE:(match_operand:VDI 1 "register_operand"))] ++ "TARGET_NEON" ++{ ++ rtx tmpreg = gen_reg_rtx (mode); ++ emit_insn (gen_neon_unpack_ (tmpreg, operands[1])); ++ emit_insn (gen_neon_vget_high (operands[0], tmpreg)); ++ ++ DONE; ++} ++) ++ ++(define_insn "neon_vec_mult_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (mult: (SE: ++ (match_operand:VDI 1 "register_operand" "w")) ++ (SE: ++ (match_operand:VDI 2 "register_operand" "w"))))] ++ "TARGET_NEON" ++ "vmull. %q0, %1, %2" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_widen_mult_hi_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VDI 1 "register_operand" "")) ++ (SE: (match_operand:VDI 2 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtx tmpreg = gen_reg_rtx (mode); ++ emit_insn (gen_neon_vec_mult_ (tmpreg, operands[1], operands[2])); ++ emit_insn (gen_neon_vget_high (operands[0], tmpreg)); ++ ++ DONE; ++ ++ } ++) ++ ++(define_expand "vec_widen_mult_lo_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VDI 1 "register_operand" "")) ++ (SE: (match_operand:VDI 2 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtx tmpreg = gen_reg_rtx (mode); ++ emit_insn (gen_neon_vec_mult_ (tmpreg, operands[1], operands[2])); ++ emit_insn (gen_neon_vget_low (operands[0], tmpreg)); ++ ++ DONE; ++ ++ } ++) + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2010-08-31 10:00:27 +0000 ++++ new/gcc/config/arm/predicates.md 2010-09-09 14:11:34 +0000 +@@ -573,3 +573,61 @@ + (and (match_test "TARGET_32BIT") + (match_operand 0 "arm_di_operand")))) + ++;; Predicates for parallel expanders based on mode. ++(define_special_predicate "vect_par_constant_high" ++ (match_code "parallel") ++{ ++ HOST_WIDE_INT count = XVECLEN (op, 0); ++ int i; ++ int base = GET_MODE_NUNITS (mode); ++ ++ if ((count < 1) ++ || (count != base/2)) ++ return false; ++ ++ if (!VECTOR_MODE_P (mode)) ++ return false; ++ ++ for (i = 0; i < count; i++) ++ { ++ rtx elt = XVECEXP (op, 0, i); ++ int val; ++ ++ if (GET_CODE (elt) != CONST_INT) ++ return false; ++ ++ val = INTVAL (elt); ++ if (val != (base/2) + i) ++ return false; ++ } ++ return true; ++}) ++ ++(define_special_predicate "vect_par_constant_low" ++ (match_code "parallel") ++{ ++ HOST_WIDE_INT count = XVECLEN (op, 0); ++ int i; ++ int base = GET_MODE_NUNITS (mode); ++ ++ if ((count < 1) ++ || (count != base/2)) ++ return false; ++ ++ if (!VECTOR_MODE_P (mode)) ++ return false; ++ ++ for (i = 0; i < count; i++) ++ { ++ rtx elt = XVECEXP (op, 0, i); ++ int val; ++ ++ if (GET_CODE (elt) != CONST_INT) ++ return false; ++ ++ val = INTVAL (elt); ++ if (val != i) ++ return false; ++ } ++ return true; ++}) + +=== modified file 'gcc/testsuite/lib/target-supports.exp' +--- old/gcc/testsuite/lib/target-supports.exp 2010-08-24 13:00:03 +0000 ++++ new/gcc/testsuite/lib/target-supports.exp 2010-09-09 14:11:34 +0000 +@@ -2519,7 +2519,8 @@ + if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*]) + || [istarget i?86-*-*] + || [istarget x86_64-*-*] +- || [istarget spu-*-*] } { ++ || [istarget spu-*-*] ++ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } { + set et_vect_unpack_saved 1 + } + } + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch new file mode 100644 index 0000000000..89c04a8949 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch @@ -0,0 +1,1202 @@ + 2010-08-18 Marcus Shawcroft + * config/arm/arm-protos.h (arm_expand_sync): New. + (arm_output_memory_barrier, arm_output_sync_insn): New. + (arm_sync_loop_insns): New. + * config/arm/arm.c (FL_ARCH7): New. + (FL_FOR_ARCH7): Include FL_ARCH7. + (arm_arch7): New. + (arm_print_operand): Support %C markup. + (arm_legitimize_sync_memory): New. + (arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New. + (arm_process_output_memory_barrier, arm_output_memory_barrier): New. + (arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New. + (arm_output_op2, arm_output_op3, arm_output_sync_loop): New. + (arm_get_sync_operand, FETCH_SYNC_OPERAND): New. + (arm_process_output_sync_insn, arm_output_sync_insn): New. + (arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New. + * config/arm/arm.h (struct arm_sync_generator): New. + (TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New. + (TARGET_HAVE_MEMORY_BARRIER): New. + (TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New. + * config/arm/arm.md: Include sync.md. + (UNSPEC_MEMORY_BARRIER): New. + (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New. + (VUNSPEC_SYNC_OP):New. + (VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New. + (sync_result, sync_memory, sync_required_value): New attributes. + (sync_new_value, sync_t1, sync_t2): Likewise. + (sync_release_barrier, sync_op): Likewise. + (length): Add logic to length attribute defintion to call + arm_sync_loop_insns when appropriate. + * config/arm/sync.md: New file. + +2010-09-09 Andrew Stubbs + + Backport from mainline: + + 2010-08-25 Tejas Belagod + * config/arm/iterators.md (VU, SE, V_widen_l): New. + (V_unpack, US): New. + +=== modified file 'gcc/config/arm/arm-protos.h' +--- old/gcc/config/arm/arm-protos.h 2010-08-24 13:15:54 +0000 ++++ new/gcc/config/arm/arm-protos.h 2010-09-09 15:03:00 +0000 +@@ -148,6 +148,11 @@ + extern void arm_set_return_address (rtx, rtx); + extern int arm_eliminable_register (rtx); + extern const char *arm_output_shift(rtx *, int); ++extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *, ++ rtx, rtx, rtx, rtx); ++extern const char *arm_output_memory_barrier (rtx *); ++extern const char *arm_output_sync_insn (rtx, rtx *); ++extern unsigned int arm_sync_loop_insns (rtx , rtx *); + + extern bool arm_output_addr_const_extra (FILE *, rtx); + + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-09-01 13:29:58 +0000 ++++ new/gcc/config/arm/arm.c 2010-09-09 15:03:00 +0000 +@@ -605,6 +605,7 @@ + #define FL_NEON (1 << 20) /* Neon instructions. */ + #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M + architecture. */ ++#define FL_ARCH7 (1 << 22) /* Architecture 7. */ + + #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ + +@@ -625,7 +626,7 @@ + #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K + #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) + #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) +-#define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) ++#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) + #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) + #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) + #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) +@@ -663,6 +664,9 @@ + /* Nonzero if this chip supports the ARM 6K extensions. */ + int arm_arch6k = 0; + ++/* Nonzero if this chip supports the ARM 7 extensions. */ ++int arm_arch7 = 0; ++ + /* Nonzero if instructions not present in the 'M' profile can be used. */ + int arm_arch_notm = 0; + +@@ -1634,6 +1638,7 @@ + arm_arch6 = (insn_flags & FL_ARCH6) != 0; + arm_arch6k = (insn_flags & FL_ARCH6K) != 0; + arm_arch_notm = (insn_flags & FL_NOTM) != 0; ++ arm_arch7 = (insn_flags & FL_ARCH7) != 0; + arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; + arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; + arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; +@@ -16561,6 +16566,17 @@ + } + return; + ++ case 'C': ++ { ++ rtx addr; ++ ++ gcc_assert (GET_CODE (x) == MEM); ++ addr = XEXP (x, 0); ++ gcc_assert (GET_CODE (addr) == REG); ++ asm_fprintf (stream, "[%r]", REGNO (addr)); ++ } ++ return; ++ + /* Translate an S register number into a D register number and element index. */ + case 'y': + { +@@ -22763,4 +22779,372 @@ + is_packed); + } + ++/* Legitimize a memory reference for sync primitive implemented using ++ ldrex / strex. We currently force the form of the reference to be ++ indirect without offset. We do not yet support the indirect offset ++ addressing supported by some ARM targets for these ++ instructions. */ ++static rtx ++arm_legitimize_sync_memory (rtx memory) ++{ ++ rtx addr = force_reg (Pmode, XEXP (memory, 0)); ++ rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr); ++ ++ set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER); ++ MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory); ++ return legitimate_memory; ++} ++ ++/* An instruction emitter. */ ++typedef void (* emit_f) (int label, const char *, rtx *); ++ ++/* An instruction emitter that emits via the conventional ++ output_asm_insn. */ ++static void ++arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands) ++{ ++ output_asm_insn (pattern, operands); ++} ++ ++/* Count the number of emitted synchronization instructions. */ ++static unsigned arm_insn_count; ++ ++/* An emitter that counts emitted instructions but does not actually ++ emit instruction into the the instruction stream. */ ++static void ++arm_count (int label, ++ const char *pattern ATTRIBUTE_UNUSED, ++ rtx *operands ATTRIBUTE_UNUSED) ++{ ++ if (! label) ++ ++ arm_insn_count; ++} ++ ++/* Construct a pattern using conventional output formatting and feed ++ it to output_asm_insn. Provides a mechanism to construct the ++ output pattern on the fly. Note the hard limit on the pattern ++ buffer size. */ ++static void ++arm_output_asm_insn (emit_f emit, int label, rtx *operands, ++ const char *pattern, ...) ++{ ++ va_list ap; ++ char buffer[256]; ++ ++ va_start (ap, pattern); ++ vsprintf (buffer, pattern, ap); ++ va_end (ap); ++ emit (label, buffer, operands); ++} ++ ++/* Emit the memory barrier instruction, if any, provided by this ++ target to a specified emitter. */ ++static void ++arm_process_output_memory_barrier (emit_f emit, rtx *operands) ++{ ++ if (TARGET_HAVE_DMB) ++ { ++ /* Note we issue a system level barrier. We should consider ++ issuing a inner shareabilty zone barrier here instead, ie. ++ "DMB ISH". */ ++ emit (0, "dmb\tsy", operands); ++ return; ++ } ++ ++ if (TARGET_HAVE_DMB_MCR) ++ { ++ emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands); ++ return; ++ } ++ ++ gcc_unreachable (); ++} ++ ++/* Emit the memory barrier instruction, if any, provided by this ++ target. */ ++const char * ++arm_output_memory_barrier (rtx *operands) ++{ ++ arm_process_output_memory_barrier (arm_emit, operands); ++ return ""; ++} ++ ++/* Helper to figure out the instruction suffix required on ldrex/strex ++ for operations on an object of the specified mode. */ ++static const char * ++arm_ldrex_suffix (enum machine_mode mode) ++{ ++ switch (mode) ++ { ++ case QImode: return "b"; ++ case HImode: return "h"; ++ case SImode: return ""; ++ case DImode: return "d"; ++ default: ++ gcc_unreachable (); ++ } ++ return ""; ++} ++ ++/* Emit an ldrex{b,h,d, } instruction appropriate for the specified ++ mode. */ ++static void ++arm_output_ldrex (emit_f emit, ++ enum machine_mode mode, ++ rtx target, ++ rtx memory) ++{ ++ const char *suffix = arm_ldrex_suffix (mode); ++ rtx operands[2]; ++ ++ operands[0] = target; ++ operands[1] = memory; ++ arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix); ++} ++ ++/* Emit a strex{b,h,d, } instruction appropriate for the specified ++ mode. */ ++static void ++arm_output_strex (emit_f emit, ++ enum machine_mode mode, ++ const char *cc, ++ rtx result, ++ rtx value, ++ rtx memory) ++{ ++ const char *suffix = arm_ldrex_suffix (mode); ++ rtx operands[3]; ++ ++ operands[0] = result; ++ operands[1] = value; ++ operands[2] = memory; ++ arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix, ++ cc); ++} ++ ++/* Helper to emit a two operand instruction. */ ++static void ++arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s) ++{ ++ rtx operands[2]; ++ ++ operands[0] = d; ++ operands[1] = s; ++ arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic); ++} ++ ++/* Helper to emit a three operand instruction. */ ++static void ++arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b) ++{ ++ rtx operands[3]; ++ ++ operands[0] = d; ++ operands[1] = a; ++ operands[2] = b; ++ arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic); ++} ++ ++/* Emit a load store exclusive synchronization loop. ++ ++ do ++ old_value = [mem] ++ if old_value != required_value ++ break; ++ t1 = sync_op (old_value, new_value) ++ [mem] = t1, t2 = [0|1] ++ while ! t2 ++ ++ Note: ++ t1 == t2 is not permitted ++ t1 == old_value is permitted ++ ++ required_value: ++ ++ RTX register or const_int representing the required old_value for ++ the modify to continue, if NULL no comparsion is performed. */ ++static void ++arm_output_sync_loop (emit_f emit, ++ enum machine_mode mode, ++ rtx old_value, ++ rtx memory, ++ rtx required_value, ++ rtx new_value, ++ rtx t1, ++ rtx t2, ++ enum attr_sync_op sync_op, ++ int early_barrier_required) ++{ ++ rtx operands[1]; ++ ++ gcc_assert (t1 != t2); ++ ++ if (early_barrier_required) ++ arm_process_output_memory_barrier (emit, NULL); ++ ++ arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX); ++ ++ arm_output_ldrex (emit, mode, old_value, memory); ++ ++ if (required_value) ++ { ++ rtx operands[2]; ++ ++ operands[0] = old_value; ++ operands[1] = required_value; ++ arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1"); ++ arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX); ++ } ++ ++ switch (sync_op) ++ { ++ case SYNC_OP_ADD: ++ arm_output_op3 (emit, "add", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_SUB: ++ arm_output_op3 (emit, "sub", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_IOR: ++ arm_output_op3 (emit, "orr", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_XOR: ++ arm_output_op3 (emit, "eor", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_AND: ++ arm_output_op3 (emit,"and", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_NAND: ++ arm_output_op3 (emit, "and", t1, old_value, new_value); ++ arm_output_op2 (emit, "mvn", t1, t1); ++ break; ++ ++ case SYNC_OP_NONE: ++ t1 = new_value; ++ break; ++ } ++ ++ arm_output_strex (emit, mode, "", t2, t1, memory); ++ operands[0] = t2; ++ arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); ++ arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX); ++ ++ arm_process_output_memory_barrier (emit, NULL); ++ arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); ++} ++ ++static rtx ++arm_get_sync_operand (rtx *operands, int index, rtx default_value) ++{ ++ if (index > 0) ++ default_value = operands[index - 1]; ++ ++ return default_value; ++} ++ ++#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \ ++ arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT); ++ ++/* Extract the operands for a synchroniztion instruction from the ++ instructions attributes and emit the instruction. */ ++static void ++arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands) ++{ ++ rtx result, memory, required_value, new_value, t1, t2; ++ int early_barrier; ++ enum machine_mode mode; ++ enum attr_sync_op sync_op; ++ ++ result = FETCH_SYNC_OPERAND(result, 0); ++ memory = FETCH_SYNC_OPERAND(memory, 0); ++ required_value = FETCH_SYNC_OPERAND(required_value, 0); ++ new_value = FETCH_SYNC_OPERAND(new_value, 0); ++ t1 = FETCH_SYNC_OPERAND(t1, 0); ++ t2 = FETCH_SYNC_OPERAND(t2, 0); ++ early_barrier = ++ get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES; ++ sync_op = get_attr_sync_op (insn); ++ mode = GET_MODE (memory); ++ ++ arm_output_sync_loop (emit, mode, result, memory, required_value, ++ new_value, t1, t2, sync_op, early_barrier); ++} ++ ++/* Emit a synchronization instruction loop. */ ++const char * ++arm_output_sync_insn (rtx insn, rtx *operands) ++{ ++ arm_process_output_sync_insn (arm_emit, insn, operands); ++ return ""; ++} ++ ++/* Count the number of machine instruction that will be emitted for a ++ synchronization instruction. Note that the emitter used does not ++ emit instructions, it just counts instructions being carefull not ++ to count labels. */ ++unsigned int ++arm_sync_loop_insns (rtx insn, rtx *operands) ++{ ++ arm_insn_count = 0; ++ arm_process_output_sync_insn (arm_count, insn, operands); ++ return arm_insn_count; ++} ++ ++/* Helper to call a target sync instruction generator, dealing with ++ the variation in operands required by the different generators. */ ++static rtx ++arm_call_generator (struct arm_sync_generator *generator, rtx old_value, ++ rtx memory, rtx required_value, rtx new_value) ++{ ++ switch (generator->op) ++ { ++ case arm_sync_generator_omn: ++ gcc_assert (! required_value); ++ return generator->u.omn (old_value, memory, new_value); ++ ++ case arm_sync_generator_omrn: ++ gcc_assert (required_value); ++ return generator->u.omrn (old_value, memory, required_value, new_value); ++ } ++ ++ return NULL; ++} ++ ++/* Expand a synchronization loop. The synchronization loop is expanded ++ as an opaque block of instructions in order to ensure that we do ++ not subsequently get extraneous memory accesses inserted within the ++ critical region. The exclusive access property of ldrex/strex is ++ only guaranteed in there are no intervening memory accesses. */ ++void ++arm_expand_sync (enum machine_mode mode, ++ struct arm_sync_generator *generator, ++ rtx target, rtx memory, rtx required_value, rtx new_value) ++{ ++ if (target == NULL) ++ target = gen_reg_rtx (mode); ++ ++ memory = arm_legitimize_sync_memory (memory); ++ if (mode != SImode) ++ { ++ rtx load_temp = gen_reg_rtx (SImode); ++ ++ if (required_value) ++ required_value = convert_modes (SImode, mode, required_value, true); ++ ++ new_value = convert_modes (SImode, mode, new_value, true); ++ emit_insn (arm_call_generator (generator, load_temp, memory, ++ required_value, new_value)); ++ emit_move_insn (target, gen_lowpart (mode, load_temp)); ++ } ++ else ++ { ++ emit_insn (arm_call_generator (generator, target, memory, required_value, ++ new_value)); ++ } ++} ++ + #include "gt-arm.h" + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-09-01 13:29:58 +0000 ++++ new/gcc/config/arm/arm.h 2010-09-09 15:03:00 +0000 +@@ -128,6 +128,24 @@ + /* The processor for which instructions should be scheduled. */ + extern enum processor_type arm_tune; + ++enum arm_sync_generator_tag ++ { ++ arm_sync_generator_omn, ++ arm_sync_generator_omrn ++ }; ++ ++/* Wrapper to pass around a polymorphic pointer to a sync instruction ++ generator and. */ ++struct arm_sync_generator ++{ ++ enum arm_sync_generator_tag op; ++ union ++ { ++ rtx (* omn) (rtx, rtx, rtx); ++ rtx (* omrn) (rtx, rtx, rtx, rtx); ++ } u; ++}; ++ + typedef enum arm_cond_code + { + ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, +@@ -272,6 +290,20 @@ + for Thumb-2. */ + #define TARGET_UNIFIED_ASM TARGET_THUMB2 + ++/* Nonzero if this chip provides the DMB instruction. */ ++#define TARGET_HAVE_DMB (arm_arch7) ++ ++/* Nonzero if this chip implements a memory barrier via CP15. */ ++#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) ++ ++/* Nonzero if this chip implements a memory barrier instruction. */ ++#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) ++ ++/* Nonzero if this chip supports ldrex and strex */ ++#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) ++ ++/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ ++#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) + + /* True iff the full BPABI is being used. If TARGET_BPABI is true, + then TARGET_AAPCS_BASED must be true -- but the converse does not +@@ -405,6 +437,12 @@ + /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ + extern int arm_arch6; + ++/* Nonzero if this chip supports the ARM Architecture 6k extensions. */ ++extern int arm_arch6k; ++ ++/* Nonzero if this chip supports the ARM Architecture 7 extensions. */ ++extern int arm_arch7; ++ + /* Nonzero if instructions not present in the 'M' profile can be used. */ + extern int arm_arch_notm; + + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-09-09 14:11:34 +0000 ++++ new/gcc/config/arm/arm.md 2010-09-09 15:03:00 +0000 +@@ -103,6 +103,7 @@ + (UNSPEC_RBIT 26) ; rbit operation. + (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from + ; another symbolic address. ++ (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier. + ] + ) + +@@ -139,6 +140,11 @@ + (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment. + (VUNSPEC_EH_RETURN 20); Use to override the return address for exception + ; handling. ++ (VUNSPEC_SYNC_COMPARE_AND_SWAP 21) ; Represent an atomic compare swap. ++ (VUNSPEC_SYNC_LOCK 22) ; Represent a sync_lock_test_and_set. ++ (VUNSPEC_SYNC_OP 23) ; Represent a sync_ ++ (VUNSPEC_SYNC_NEW_OP 24) ; Represent a sync_new_ ++ (VUNSPEC_SYNC_OLD_OP 25) ; Represent a sync_old_ + ] + ) + +@@ -163,8 +169,21 @@ + (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp" + (const (symbol_ref "arm_fpu_attr"))) + ++(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_release_barrier" "yes,no" (const_string "yes")) ++(define_attr "sync_op" "none,add,sub,ior,xor,and,nand" ++ (const_string "none")) ++ + ; LENGTH of an instruction (in bytes) +-(define_attr "length" "" (const_int 4)) ++(define_attr "length" "" ++ (cond [(not (eq_attr "sync_memory" "none")) ++ (symbol_ref "arm_sync_loop_insns (insn, operands) * 4") ++ ] (const_int 4))) + + ; POOL_RANGE is how far away from a constant pool entry that this insn + ; can be placed. If the distance is zero, then this insn will never +@@ -11530,4 +11549,5 @@ + (include "thumb2.md") + ;; Neon patterns + (include "neon.md") +- ++;; Synchronization Primitives ++(include "sync.md") + +=== added file 'gcc/config/arm/sync.md' +--- old/gcc/config/arm/sync.md 1970-01-01 00:00:00 +0000 ++++ new/gcc/config/arm/sync.md 2010-09-09 15:03:00 +0000 +@@ -0,0 +1,594 @@ ++;; Machine description for ARM processor synchronization primitives. ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; Written by Marcus Shawcroft (marcus.shawcroft@arm.com) ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . */ ++ ++;; ARMV6 introduced ldrex and strex instruction. These instruction ++;; access SI width data. In order to implement synchronization ++;; primitives for the narrower QI and HI modes we insert appropriate ++;; AND/OR sequences into the synchronization loop to mask out the ++;; relevant component of an SI access. ++ ++(define_expand "memory_barrier" ++ [(set (match_dup 0) ++ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))] ++ "TARGET_HAVE_MEMORY_BARRIER" ++{ ++ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); ++ MEM_VOLATILE_P (operands[0]) = 1; ++}) ++ ++(define_expand "sync_compare_and_swapsi" ++ [(set (match_operand:SI 0 "s_register_operand") ++ (unspec_volatile:SI [(match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (match_operand:SI 3 "s_register_operand")] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omrn; ++ generator.u.omrn = gen_arm_sync_compare_and_swapsi; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], operands[2], ++ operands[3]); ++ DONE; ++ }) ++ ++(define_mode_iterator NARROW [QI HI]) ++ ++(define_expand "sync_compare_and_swap" ++ [(set (match_operand:NARROW 0 "s_register_operand") ++ (unspec_volatile:NARROW [(match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (match_operand:NARROW 3 "s_register_operand")] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omrn; ++ generator.u.omrn = gen_arm_sync_compare_and_swap; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ operands[2], operands[3]); ++ DONE; ++ }) ++ ++(define_expand "sync_lock_test_and_setsi" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand")] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_lock_test_and_setsi; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_lock_test_and_set" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand")] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_lock_test_and_set; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_code_iterator syncop [plus minus ior xor and]) ++ ++(define_code_attr sync_optab [(ior "ior") ++ (xor "xor") ++ (and "and") ++ (plus "add") ++ (minus "sub")]) ++ ++(define_expand "sync_si" ++ [(match_operand:SI 0 "memory_operand") ++ (match_operand:SI 1 "s_register_operand") ++ (syncop:SI (match_dup 0) (match_dup 1))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_si; ++ arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]); ++ DONE; ++ }) ++ ++(define_expand "sync_nandsi" ++ [(match_operand:SI 0 "memory_operand") ++ (match_operand:SI 1 "s_register_operand") ++ (not:SI (and:SI (match_dup 0) (match_dup 1)))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_nandsi; ++ arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]); ++ DONE; ++ }) ++ ++(define_expand "sync_" ++ [(match_operand:NARROW 0 "memory_operand") ++ (match_operand:NARROW 1 "s_register_operand") ++ (syncop:NARROW (match_dup 0) (match_dup 1))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_; ++ arm_expand_sync (mode, &generator, NULL, operands[0], NULL, ++ operands[1]); ++ DONE; ++ }) ++ ++(define_expand "sync_nand" ++ [(match_operand:NARROW 0 "memory_operand") ++ (match_operand:NARROW 1 "s_register_operand") ++ (not:NARROW (and:NARROW (match_dup 0) (match_dup 1)))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_nand; ++ arm_expand_sync (mode, &generator, NULL, operands[0], NULL, ++ operands[1]); ++ DONE; ++ }) ++ ++(define_expand "sync_new_si" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (syncop:SI (match_dup 1) (match_dup 2))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_si; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_new_nandsi" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (not:SI (and:SI (match_dup 1) (match_dup 2)))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_nandsi; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_new_" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (syncop:NARROW (match_dup 1) (match_dup 2))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ NULL, operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_new_nand" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_nand; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ NULL, operands[2]); ++ DONE; ++ }); ++ ++(define_expand "sync_old_si" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (syncop:SI (match_dup 1) (match_dup 2))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_old_si; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_old_nandsi" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (not:SI (and:SI (match_dup 1) (match_dup 2)))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_old_nandsi; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_old_" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (syncop:NARROW (match_dup 1) (match_dup 2))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_old_; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ NULL, operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_old_nand" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_old_nand; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ NULL, operands[2]); ++ DONE; ++ }) ++ ++(define_insn "arm_sync_compare_and_swapsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 2 "s_register_operand" "r") ++ (match_operand:SI 3 "s_register_operand" "r")] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ (clobber:SI (match_scratch:SI 4 "=&r")) ++ (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ ] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_required_value" "2") ++ (set_attr "sync_new_value" "3") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "4") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_compare_and_swap" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (zero_extend:SI ++ (unspec_volatile:NARROW ++ [(match_operand:NARROW 1 "memory_operand" "+m") ++ (match_operand:SI 2 "s_register_operand" "r") ++ (match_operand:SI 3 "s_register_operand" "r")] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP))) ++ (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ (clobber:SI (match_scratch:SI 4 "=&r")) ++ (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ ] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_required_value" "2") ++ (set_attr "sync_new_value" "3") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "4") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_lock_test_and_setsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (match_operand:SI 1 "memory_operand" "+m")) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")] ++ VUNSPEC_SYNC_LOCK)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_release_barrier" "no") ++ (set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_lock_test_and_set" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m"))) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")] ++ VUNSPEC_SYNC_LOCK)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_release_barrier" "no") ++ (set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_new_si" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(syncop:SI ++ (match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 2 "s_register_operand" "r")) ++ ] ++ VUNSPEC_SYNC_NEW_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_NEW_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "sync_op" "") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_new_nandsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(not:SI (and:SI ++ (match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ ] ++ VUNSPEC_SYNC_NEW_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_NEW_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "sync_op" "nand") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_new_" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(syncop:SI ++ (zero_extend:SI ++ (match_operand:NARROW 1 "memory_operand" "+m")) ++ (match_operand:SI 2 "s_register_operand" "r")) ++ ] ++ VUNSPEC_SYNC_NEW_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_NEW_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "sync_op" "") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_new_nand" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI ++ [(not:SI ++ (and:SI ++ (zero_extend:SI ++ (match_operand:NARROW 1 "memory_operand" "+m")) ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ ] VUNSPEC_SYNC_NEW_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_NEW_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "sync_op" "nand") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_old_si" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(syncop:SI ++ (match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 2 "s_register_operand" "r")) ++ ] ++ VUNSPEC_SYNC_OLD_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_OLD_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r")) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "3") ++ (set_attr "sync_t2" "4") ++ (set_attr "sync_op" "") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_old_nandsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(not:SI (and:SI ++ (match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ ] ++ VUNSPEC_SYNC_OLD_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_OLD_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r")) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "3") ++ (set_attr "sync_t2" "4") ++ (set_attr "sync_op" "nand") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_old_" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(syncop:SI ++ (zero_extend:SI ++ (match_operand:NARROW 1 "memory_operand" "+m")) ++ (match_operand:SI 2 "s_register_operand" "r")) ++ ] ++ VUNSPEC_SYNC_OLD_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_OLD_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r")) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "3") ++ (set_attr "sync_t2" "4") ++ (set_attr "sync_op" "") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_old_nand" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(not:SI (and:SI ++ (zero_extend:SI ++ (match_operand:NARROW 1 "memory_operand" "+m")) ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ ] ++ VUNSPEC_SYNC_OLD_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_OLD_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r")) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "3") ++ (set_attr "sync_t2" "4") ++ (set_attr "sync_op" "nand") ++ (set_attr "conds" "nocond") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "*memory_barrier" ++ [(set (match_operand:BLK 0 "" "") ++ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))] ++ "TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_memory_barrier (operands); ++ } ++ [(set_attr "length" "4") ++ (set_attr "conds" "unconditional") ++ (set_attr "predicable" "no")]) ++ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch new file mode 100644 index 0000000000..d10cf34654 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch @@ -0,0 +1,151 @@ + 2010-09-02 Marcus Shawcroft + * config/arm/predicates.md (arm_sync_memory_operand): New. + * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate + to arm_sync_memory_operand and constraint to Q. + (arm_sync_compare_and_swap): Likewise. + (arm_sync_compare_and_swap): Likewise. + (arm_sync_lock_test_and_setsi): Likewise. + (arm_sync_lock_test_and_set): Likewise. + (arm_sync_new_si): Likewise. + (arm_sync_new_nandsi): Likewise. + (arm_sync_new_): Likewise. + (arm_sync_new_nand): Likewise. + (arm_sync_old_si): Likewise. + (arm_sync_old_nandsi): Likewise. + (arm_sync_old_): Likewise. + (arm_sync_old_nand): Likewise. + +2010-09-09 Andrew Stubbs + + Backport from mainline: + + 2010-08-18 Marcus Shawcroft + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2010-09-09 14:11:34 +0000 ++++ new/gcc/config/arm/predicates.md 2010-09-09 15:18:16 +0000 +@@ -573,6 +573,11 @@ + (and (match_test "TARGET_32BIT") + (match_operand 0 "arm_di_operand")))) + ++;; True if the operand is memory reference suitable for a ldrex/strex. ++(define_predicate "arm_sync_memory_operand" ++ (and (match_operand 0 "memory_operand") ++ (match_code "reg" "0"))) ++ + ;; Predicates for parallel expanders based on mode. + (define_special_predicate "vect_par_constant_high" + (match_code "parallel") + +=== modified file 'gcc/config/arm/sync.md' +--- old/gcc/config/arm/sync.md 2010-09-09 15:03:00 +0000 ++++ new/gcc/config/arm/sync.md 2010-09-09 15:18:16 +0000 +@@ -280,7 +280,7 @@ + (define_insn "arm_sync_compare_and_swapsi" + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI +- [(match_operand:SI 1 "memory_operand" "+m") ++ [(match_operand:SI 1 "arm_sync_memory_operand" "+Q") + (match_operand:SI 2 "s_register_operand" "r") + (match_operand:SI 3 "s_register_operand" "r")] + VUNSPEC_SYNC_COMPARE_AND_SWAP)) +@@ -307,7 +307,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (zero_extend:SI + (unspec_volatile:NARROW +- [(match_operand:NARROW 1 "memory_operand" "+m") ++ [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q") + (match_operand:SI 2 "s_register_operand" "r") + (match_operand:SI 3 "s_register_operand" "r")] + VUNSPEC_SYNC_COMPARE_AND_SWAP))) +@@ -332,7 +332,7 @@ + + (define_insn "arm_sync_lock_test_and_setsi" + [(set (match_operand:SI 0 "s_register_operand" "=&r") +- (match_operand:SI 1 "memory_operand" "+m")) ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q")) + (set (match_dup 1) + (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")] + VUNSPEC_SYNC_LOCK)) +@@ -353,7 +353,7 @@ + + (define_insn "arm_sync_lock_test_and_set" + [(set (match_operand:SI 0 "s_register_operand" "=&r") +- (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m"))) ++ (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))) + (set (match_dup 1) + (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")] + VUNSPEC_SYNC_LOCK)) +@@ -375,7 +375,7 @@ + (define_insn "arm_sync_new_si" + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI [(syncop:SI +- (match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q") + (match_operand:SI 2 "s_register_operand" "r")) + ] + VUNSPEC_SYNC_NEW_OP)) +@@ -400,7 +400,7 @@ + (define_insn "arm_sync_new_nandsi" + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI [(not:SI (and:SI +- (match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q") + (match_operand:SI 2 "s_register_operand" "r"))) + ] + VUNSPEC_SYNC_NEW_OP)) +@@ -426,7 +426,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI [(syncop:SI + (zero_extend:SI +- (match_operand:NARROW 1 "memory_operand" "+m")) ++ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) + (match_operand:SI 2 "s_register_operand" "r")) + ] + VUNSPEC_SYNC_NEW_OP)) +@@ -454,7 +454,7 @@ + [(not:SI + (and:SI + (zero_extend:SI +- (match_operand:NARROW 1 "memory_operand" "+m")) ++ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) + (match_operand:SI 2 "s_register_operand" "r"))) + ] VUNSPEC_SYNC_NEW_OP)) + (set (match_dup 1) +@@ -478,7 +478,7 @@ + (define_insn "arm_sync_old_si" + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI [(syncop:SI +- (match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q") + (match_operand:SI 2 "s_register_operand" "r")) + ] + VUNSPEC_SYNC_OLD_OP)) +@@ -504,7 +504,7 @@ + (define_insn "arm_sync_old_nandsi" + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI [(not:SI (and:SI +- (match_operand:SI 1 "memory_operand" "+m") ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q") + (match_operand:SI 2 "s_register_operand" "r"))) + ] + VUNSPEC_SYNC_OLD_OP)) +@@ -531,7 +531,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI [(syncop:SI + (zero_extend:SI +- (match_operand:NARROW 1 "memory_operand" "+m")) ++ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) + (match_operand:SI 2 "s_register_operand" "r")) + ] + VUNSPEC_SYNC_OLD_OP)) +@@ -558,7 +558,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI [(not:SI (and:SI + (zero_extend:SI +- (match_operand:NARROW 1 "memory_operand" "+m")) ++ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) + (match_operand:SI 2 "s_register_operand" "r"))) + ] + VUNSPEC_SYNC_OLD_OP)) + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch new file mode 100644 index 0000000000..f603fcadba --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch @@ -0,0 +1,191 @@ +2010-09-13 Andrew Stubbs + + Backport from FSF: + + 2010-09-13 Marcus Shawcroft + + * config/arm/arm.md: (define_attr "conds"): Update comment. + * config/arm/sync.md (arm_sync_compare_and_swapsi): Change + conds attribute to clob. + (arm_sync_compare_and_swapsi): Likewise. + (arm_sync_compare_and_swap): Likewise. + (arm_sync_lock_test_and_setsi): Likewise. + (arm_sync_lock_test_and_set): Likewise. + (arm_sync_new_si): Likewise. + (arm_sync_new_nandsi): Likewise. + (arm_sync_new_): Likewise. + (arm_sync_new_nand): Likewise. + (arm_sync_old_si): Likewise. + (arm_sync_old_nandsi): Likewise. + (arm_sync_old_): Likewise. + (arm_sync_old_nand): Likewise. + + 2010-09-13 Marcus Shawcroft + + * gcc.target/arm/sync-1.c: New. + + 2010-09-10 Andrew Stubbs + + gcc/ + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-09-09 15:03:00 +0000 ++++ new/gcc/config/arm/arm.md 2010-09-13 15:39:11 +0000 +@@ -352,10 +352,11 @@ + ; CLOB means that the condition codes are altered in an undefined manner, if + ; they are altered at all + ; +-; UNCONDITIONAL means the instions can not be conditionally executed. ++; UNCONDITIONAL means the instruction can not be conditionally executed and ++; that the instruction does not use or alter the condition codes. + ; +-; NOCOND means that the condition codes are neither altered nor affect the +-; output of this insn ++; NOCOND means that the instruction does not use or alter the condition ++; codes but can be converted into a conditionally exectuted instruction. + + (define_attr "conds" "use,set,clob,unconditional,nocond" + (if_then_else (eq_attr "type" "call") + +=== modified file 'gcc/config/arm/sync.md' +--- old/gcc/config/arm/sync.md 2010-09-09 15:18:16 +0000 ++++ new/gcc/config/arm/sync.md 2010-09-13 15:39:11 +0000 +@@ -300,7 +300,7 @@ + (set_attr "sync_new_value" "3") + (set_attr "sync_t1" "0") + (set_attr "sync_t2" "4") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_compare_and_swap" +@@ -327,7 +327,7 @@ + (set_attr "sync_new_value" "3") + (set_attr "sync_t1" "0") + (set_attr "sync_t2" "4") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_lock_test_and_setsi" +@@ -348,7 +348,7 @@ + (set_attr "sync_new_value" "2") + (set_attr "sync_t1" "0") + (set_attr "sync_t2" "3") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_lock_test_and_set" +@@ -369,7 +369,7 @@ + (set_attr "sync_new_value" "2") + (set_attr "sync_t1" "0") + (set_attr "sync_t2" "3") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_new_si" +@@ -394,7 +394,7 @@ + (set_attr "sync_t1" "0") + (set_attr "sync_t2" "3") + (set_attr "sync_op" "") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_new_nandsi" +@@ -419,7 +419,7 @@ + (set_attr "sync_t1" "0") + (set_attr "sync_t2" "3") + (set_attr "sync_op" "nand") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_new_" +@@ -445,7 +445,7 @@ + (set_attr "sync_t1" "0") + (set_attr "sync_t2" "3") + (set_attr "sync_op" "") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_new_nand" +@@ -472,7 +472,7 @@ + (set_attr "sync_t1" "0") + (set_attr "sync_t2" "3") + (set_attr "sync_op" "nand") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_old_si" +@@ -498,7 +498,7 @@ + (set_attr "sync_t1" "3") + (set_attr "sync_t2" "4") + (set_attr "sync_op" "") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_old_nandsi" +@@ -524,7 +524,7 @@ + (set_attr "sync_t1" "3") + (set_attr "sync_t2" "4") + (set_attr "sync_op" "nand") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_old_" +@@ -551,7 +551,7 @@ + (set_attr "sync_t1" "3") + (set_attr "sync_t2" "4") + (set_attr "sync_op" "") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "arm_sync_old_nand" +@@ -578,7 +578,7 @@ + (set_attr "sync_t1" "3") + (set_attr "sync_t2" "4") + (set_attr "sync_op" "nand") +- (set_attr "conds" "nocond") ++ (set_attr "conds" "clob") + (set_attr "predicable" "no")]) + + (define_insn "*memory_barrier" + +=== added file 'gcc/testsuite/gcc.target/arm/sync-1.c' +--- old/gcc/testsuite/gcc.target/arm/sync-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/sync-1.c 2010-09-13 15:39:11 +0000 +@@ -0,0 +1,25 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 -march=armv7-a" } */ ++ ++volatile int mem; ++ ++int ++bar (int x, int y) ++{ ++ if (x) ++ __sync_fetch_and_add(&mem, y); ++ return 0; ++} ++ ++extern void abort (void); ++ ++int ++main (int argc, char *argv[]) ++{ ++ mem = 0; ++ bar (0, 1); ++ bar (1, 1); ++ if (mem != 1) ++ abort (); ++ return 0; ++} + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch new file mode 100644 index 0000000000..31122e34be --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch @@ -0,0 +1,43 @@ +2010-09-08 Tom de Vries + + gcc/ + * gcc/emit-rtl.c (set_mem_attributes_minus_bitpos): Set MEM_READONLY_P + for static const strings. + * gcc/testsuite/gcc.dg/memcpy-3.c: New test. + + 2010-09-13 Andrew Stubbs + + gcc/ + +=== modified file 'gcc/emit-rtl.c' +--- old/gcc/emit-rtl.c 2009-11-27 12:00:28 +0000 ++++ new/gcc/emit-rtl.c 2010-09-15 16:40:06 +0000 +@@ -1648,6 +1648,11 @@ + MEM_READONLY_P (ref) = 1; + } + ++ /* Mark static const strings readonly as well. */ ++ if (base && TREE_CODE (base) == STRING_CST && TREE_READONLY (base) ++ && TREE_STATIC (base)) ++ MEM_READONLY_P (ref) = 1; ++ + /* If this expression uses it's parent's alias set, mark it such + that we won't change it. */ + if (component_uses_parent_alias_set (t)) + +=== added file 'gcc/testsuite/gcc.dg/memcpy-3.c' +--- old/gcc/testsuite/gcc.dg/memcpy-3.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/memcpy-3.c 2010-09-15 16:40:06 +0000 +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-expand" } */ ++ ++void ++f1 (char *p) ++{ ++ __builtin_memcpy (p, "123", 3); ++} ++ ++/* { dg-final { scan-rtl-dump-times "mem/s/u:" 3 "expand" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "expand" } } */ + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch new file mode 100644 index 0000000000..9a9d5940c8 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch @@ -0,0 +1,33 @@ +2010-09-10 Nathan Froyd + + Issue #9120 + + * release-notes-csl.xml (Compiler optimization improvements): New + bullet. + + gcc/ + * gimple.c (is_gimple_min_invariant): Check for constant INDIRECT_REFs. + + 2010-09-08 Tom de Vries + + gcc/ + +=== modified file 'gcc/gimple.c' +--- old/gcc/gimple.c 2010-06-22 17:23:11 +0000 ++++ new/gcc/gimple.c 2010-09-15 16:47:52 +0000 +@@ -2591,7 +2591,13 @@ + + op = strip_invariant_refs (TREE_OPERAND (t, 0)); + +- return op && (CONSTANT_CLASS_P (op) || decl_address_invariant_p (op)); ++ if (!op) ++ return false; ++ ++ if (TREE_CODE (op) == INDIRECT_REF) ++ return CONSTANT_CLASS_P (TREE_OPERAND (op, 0)); ++ else ++ return CONSTANT_CLASS_P (op) || decl_address_invariant_p (op); + } + + /* Return true if T is a gimple invariant address at IPA level + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch new file mode 100644 index 0000000000..d8df57a448 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch @@ -0,0 +1,45 @@ +2010-09-13 Chung-Lin Tang + + Backport from mainline: + + 2010-09-12 Bernd Schmidt + + gcc/ + * config/arm/arm.md (arm_ashldi3_1bit, arm_ashrdi3_1bit, + arm_lshrdi3_1bit): Put earlyclobber on the right alternative. + + 2010-09-10 Nathan Froyd + + Issue #9120 + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-09-13 15:39:11 +0000 ++++ new/gcc/config/arm/arm.md 2010-09-15 16:55:55 +0000 +@@ -3295,7 +3295,7 @@ + ) + + (define_insn "arm_ashldi3_1bit" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,r") ++ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") + (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] +@@ -3354,7 +3354,7 @@ + ) + + (define_insn "arm_ashrdi3_1bit" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,r") ++ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") + (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] +@@ -3410,7 +3410,7 @@ + ) + + (define_insn "arm_lshrdi3_1bit" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,r") ++ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") + (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch new file mode 100644 index 0000000000..809a20aae0 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch @@ -0,0 +1,26 @@ +2010-09-15 Jie Zhang + + Backport from mainline: + + gcc/ + 2010-09-15 Jie Zhang + * config/arm/vfp.md (cmpsf_trap_vfp): Change type from + fcmpd to fcmps. + + 2010-09-13 Chung-Lin Tang + + Backport from mainline: + +=== modified file 'gcc/config/arm/vfp.md' +--- old/gcc/config/arm/vfp.md 2010-08-13 15:28:31 +0000 ++++ new/gcc/config/arm/vfp.md 2010-09-16 08:57:30 +0000 +@@ -1159,7 +1159,7 @@ + fcmpes%?\\t%0, %1 + fcmpezs%?\\t%0" + [(set_attr "predicable" "yes") +- (set_attr "type" "fcmpd")] ++ (set_attr "type" "fcmps")] + ) + + (define_insn "*cmpdf_vfp" + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch new file mode 100644 index 0000000000..655399ab11 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch @@ -0,0 +1,1760 @@ +2010-09-15 Chung-Lin Tang + + Issue #9441 + + Backport from mainline: + + 2010-06-25 Bernd Schmidt + + With large parts from Jim Wilson: + PR target/43902 + + gcc/ + * tree-pretty-print.c (dump_generic_node, op_code_prio): Add + WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR. + * optabs.c (optab_for_tree_code): Likewise. + (expand_widen_pattern_expr): Likewise. + * tree-ssa-math-opts.c (convert_mult_to_widen): New function, broken + out of execute_optimize_widening_mul. + (convert_plusminus_to_widen): New function. + (execute_optimize_widening_mul): Use the two new functions. + * expr.c (expand_expr_real_2): Add support for GIMPLE_TERNARY_RHS. + Remove code to generate widening multiply-accumulate. Add support + for WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR. + * gimple-pretty-print.c (dump_ternary_rhs): New function. + (dump_gimple_assign): Call it when appropriate. + * tree.def (WIDEN_MULT_PLUS_EXPR, WIDEN_MULT_MINUS_EXPR): New codes. + * cfgexpand.c (gimple_assign_rhs_to_tree): Likewise. + (expand_gimple_stmt_1): Likewise. + (expand_debug_expr): Support WIDEN_MULT_PLUS_EXPR and + WIDEN_MULT_MINUS_EXPR. + * tree-ssa-operands.c (get_expr_operands): Likewise. + * tree-inline.c (estimate_operator_cost): Likewise. + * gimple.c (extract_ops_from_tree_1): Renamed from + extract_ops_from_tree. Add new arg for a third operand; fill it. + (gimple_build_assign_stat): Support operations with three operands. + (gimple_build_assign_with_ops_stat): Likewise. + (gimple_assign_set_rhs_from_tree): Likewise. + (gimple_assign_set_rhs_with_ops_1): Renamed from + gimple_assign_set_rhs_with_ops. Add new arg for a third operand. + (get_gimple_rhs_num_ops): Support GIMPLE_TERNARY_RHS. + (get_gimple_rhs_num_ops): Handle WIDEN_MULT_PLUS_EXPR and + WIDEN_MULT_MINUS_EXPR. + * gimple.h (enum gimple_rhs_class): Add GIMPLE_TERNARY_RHS. + (extract_ops_from_tree_1): Adjust declaration. + (gimple_assign_set_rhs_with_ops_1): Likewise. + (gimple_build_assign_with_ops): Pass NULL for last operand. + (gimple_build_assign_with_ops3): New macro. + (gimple_assign_rhs3, gimple_assign_rhs3_ptr, gimple_assign_set_rhs3, + gimple_assign_set_rhs_with_ops, extract_ops_from_tree): New inline + functions. + * tree-cfg.c (verify_gimple_assign_ternary): New static function. + (verify_gimple_assign): Call it. + * doc/gimple.texi (Manipulating operands): Document GIMPLE_TERNARY_RHS. + (Tuple specific accessors, subsection GIMPLE_ASSIGN): Document new + functions for dealing with three-operand statements. + * tree.c (commutative_ternary_tree_code): New function. + * tree.h (commutative_ternary_tree_code): Declare it. + * tree-vrp.c (gimple_assign_nonnegative_warnv_p): Return false for + ternary statements. + (gimple_assign_nonzero_warnv_p): Likewise. + * tree-ssa-sccvn.c (stmt_has_constants): Handle GIMPLE_TERNARY_RHS. + * tree-ssa-ccp.c (get_rhs_assign_op_for_ccp): New static function. + (ccp_fold): Use it. Handle GIMPLE_TERNARY_RHS. + * tree-ssa-dom.c (enum expr_kind): Add EXPR_TERNARY. + (struct hashtable_expr): New member ternary in the union. + (initialize_hash_element): Handle GIMPLE_TERNARY_RHS. + (hashable_expr_equal_p): Fix indentation. Handle EXPR_TERNARY. + (iterative_hash_hashable_expr): Likewise. + (print_expr_hash_elt): Handle EXPR_TERNARY. + * gimple-fold.c (fold_gimple_assign): Handle GIMPLE_TERNARY_RHS. + * tree-ssa-threadedge.c (fold_assignment_stmt): Remove useless break + statements. Handle GIMPLE_TERNARY_RHS. + + From Jim Wilson: + gcc/testsuite/ + * gcc.target/mips/madd-9.c: New test. + + 2010-06-29 Bernd Schmidt + + PR target/43902 + gcc/ + * config/arm/arm.md (maddsidi4, umaddsidi4): New expanders. + (maddhisi4): Renamed from mulhisi3addsi. Operands renumbered. + (maddhidi4): Likewise. + + gcc/testsuite/ + * gcc.target/arm/wmul-1.c: Test for smlabb instead of smulbb. + * gcc.target/arm/wmul-3.c: New test. + * gcc.target/arm/wmul-4.c: New test. + + 2010-07-22 Richard Sandiford + + gcc/ + * tree-ssa-math-opts.c (is_widening_mult_rhs_p): New function. + (is_widening_mult_p): Likewise. + (convert_to_widen): Use them. + (convert_plusminus_to_widen): Likewise. Handle fixed-point types as + well as integer ones. + + 2010-07-31 Richard Sandiford + + gcc/ + * tree-ssa-math-opts.c (convert_plusminus_to_widen): Fix type + used in the call to optab_for_tree_code. Fix the second + is_widening_mult_p call. Check that both unwidened operands + have the same sign. + + 2010-09-15 Jie Zhang + + Backport from mainline: + +=== modified file 'gcc/cfgexpand.c' +--- old/gcc/cfgexpand.c 2010-09-01 13:29:58 +0000 ++++ new/gcc/cfgexpand.c 2010-09-16 09:15:46 +0000 +@@ -64,7 +64,13 @@ + + grhs_class = get_gimple_rhs_class (gimple_expr_code (stmt)); + +- if (grhs_class == GIMPLE_BINARY_RHS) ++ if (grhs_class == GIMPLE_TERNARY_RHS) ++ t = build3 (gimple_assign_rhs_code (stmt), ++ TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ else if (grhs_class == GIMPLE_BINARY_RHS) + t = build2 (gimple_assign_rhs_code (stmt), + TREE_TYPE (gimple_assign_lhs (stmt)), + gimple_assign_rhs1 (stmt), +@@ -1887,6 +1893,9 @@ + ops.type = TREE_TYPE (lhs); + switch (get_gimple_rhs_class (gimple_expr_code (stmt))) + { ++ case GIMPLE_TERNARY_RHS: ++ ops.op2 = gimple_assign_rhs3 (stmt); ++ /* Fallthru */ + case GIMPLE_BINARY_RHS: + ops.op1 = gimple_assign_rhs2 (stmt); + /* Fallthru */ +@@ -2237,6 +2246,8 @@ + { + case COND_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + goto ternary; + + case TRUTH_ANDIF_EXPR: +@@ -3023,6 +3034,8 @@ + return NULL; + + case WIDEN_MULT_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + if (SCALAR_INT_MODE_P (GET_MODE (op0)) + && SCALAR_INT_MODE_P (mode)) + { +@@ -3035,7 +3048,13 @@ + op1 = simplify_gen_unary (ZERO_EXTEND, mode, op1, inner_mode); + else + op1 = simplify_gen_unary (SIGN_EXTEND, mode, op1, inner_mode); +- return gen_rtx_MULT (mode, op0, op1); ++ op0 = gen_rtx_MULT (mode, op0, op1); ++ if (TREE_CODE (exp) == WIDEN_MULT_EXPR) ++ return op0; ++ else if (TREE_CODE (exp) == WIDEN_MULT_PLUS_EXPR) ++ return gen_rtx_PLUS (mode, op0, op2); ++ else ++ return gen_rtx_MINUS (mode, op2, op0); + } + return NULL; + + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-09-15 16:55:55 +0000 ++++ new/gcc/config/arm/arm.md 2010-09-16 09:15:46 +0000 +@@ -1507,7 +1507,15 @@ + (set_attr "predicable" "yes")] + ) + +-;; Unnamed template to match long long multiply-accumulate (smlal) ++(define_expand "maddsidi4" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (plus:DI ++ (mult:DI ++ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) ++ (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))) ++ (match_operand:DI 3 "s_register_operand" "")))] ++ "TARGET_32BIT && arm_arch3m" ++ "") + + (define_insn "*mulsidi3adddi" + [(set (match_operand:DI 0 "s_register_operand" "=&r") +@@ -1603,7 +1611,15 @@ + (set_attr "predicable" "yes")] + ) + +-;; Unnamed template to match long long unsigned multiply-accumulate (umlal) ++(define_expand "umaddsidi4" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (plus:DI ++ (mult:DI ++ (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) ++ (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))) ++ (match_operand:DI 3 "s_register_operand" "")))] ++ "TARGET_32BIT && arm_arch3m" ++ "") + + (define_insn "*umulsidi3adddi" + [(set (match_operand:DI 0 "s_register_operand" "=&r") +@@ -1771,29 +1787,29 @@ + (set_attr "predicable" "yes")] + ) + +-(define_insn "*mulhisi3addsi" ++(define_insn "maddhisi4" + [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (match_operand:SI 1 "s_register_operand" "r") ++ (plus:SI (match_operand:SI 3 "s_register_operand" "r") + (mult:SI (sign_extend:SI +- (match_operand:HI 2 "s_register_operand" "%r")) ++ (match_operand:HI 1 "s_register_operand" "%r")) + (sign_extend:SI +- (match_operand:HI 3 "s_register_operand" "r")))))] ++ (match_operand:HI 2 "s_register_operand" "r")))))] + "TARGET_DSP_MULTIPLY" +- "smlabb%?\\t%0, %2, %3, %1" ++ "smlabb%?\\t%0, %1, %2, %3" + [(set_attr "insn" "smlaxy") + (set_attr "predicable" "yes")] + ) + +-(define_insn "*mulhidi3adddi" ++(define_insn "*maddhidi4" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (plus:DI +- (match_operand:DI 1 "s_register_operand" "0") ++ (match_operand:DI 3 "s_register_operand" "0") + (mult:DI (sign_extend:DI +- (match_operand:HI 2 "s_register_operand" "%r")) ++ (match_operand:HI 1 "s_register_operand" "%r")) + (sign_extend:DI +- (match_operand:HI 3 "s_register_operand" "r")))))] ++ (match_operand:HI 2 "s_register_operand" "r")))))] + "TARGET_DSP_MULTIPLY" +- "smlalbb%?\\t%Q0, %R0, %2, %3" ++ "smlalbb%?\\t%Q0, %R0, %1, %2" + [(set_attr "insn" "smlalxy") + (set_attr "predicable" "yes")]) + + +=== modified file 'gcc/doc/gimple.texi' +--- old/gcc/doc/gimple.texi 2010-07-06 19:23:53 +0000 ++++ new/gcc/doc/gimple.texi 2010-09-16 09:15:46 +0000 +@@ -554,6 +554,9 @@ + @item @code{GIMPLE_INVALID_RHS} + The tree cannot be used as a GIMPLE operand. + ++@item @code{GIMPLE_TERNARY_RHS} ++The tree is a valid GIMPLE ternary operation. ++ + @item @code{GIMPLE_BINARY_RHS} + The tree is a valid GIMPLE binary operation. + +@@ -575,10 +578,11 @@ + expressions should be flattened into the operand vector. + @end itemize + +-For tree nodes in the categories @code{GIMPLE_BINARY_RHS} and +-@code{GIMPLE_UNARY_RHS}, they cannot be stored inside tuples directly. +-They first need to be flattened and separated into individual +-components. For instance, given the GENERIC expression ++For tree nodes in the categories @code{GIMPLE_TERNARY_RHS}, ++@code{GIMPLE_BINARY_RHS} and @code{GIMPLE_UNARY_RHS}, they cannot be ++stored inside tuples directly. They first need to be flattened and ++separated into individual components. For instance, given the GENERIC ++expression + + @smallexample + a = b + c +@@ -1082,7 +1086,16 @@ + Return the address of the second operand on the @code{RHS} of assignment + statement @code{G}. + @end deftypefn ++ ++@deftypefn {GIMPLE function} tree gimple_assign_rhs3 (gimple g) ++Return the third operand on the @code{RHS} of assignment statement @code{G}. ++@end deftypefn + ++@deftypefn {GIMPLE function} tree *gimple_assign_rhs3_ptr (gimple g) ++Return the address of the third operand on the @code{RHS} of assignment ++statement @code{G}. ++@end deftypefn ++ + @deftypefn {GIMPLE function} void gimple_assign_set_lhs (gimple g, tree lhs) + Set @code{LHS} to be the @code{LHS} operand of assignment statement @code{G}. + @end deftypefn +@@ -1092,20 +1105,16 @@ + statement @code{G}. + @end deftypefn + +-@deftypefn {GIMPLE function} tree gimple_assign_rhs2 (gimple g) +-Return the second operand on the @code{RHS} of assignment statement @code{G}. +-@end deftypefn +- +-@deftypefn {GIMPLE function} tree *gimple_assign_rhs2_ptr (gimple g) +-Return a pointer to the second operand on the @code{RHS} of assignment +-statement @code{G}. +-@end deftypefn +- + @deftypefn {GIMPLE function} void gimple_assign_set_rhs2 (gimple g, tree rhs) + Set @code{RHS} to be the second operand on the @code{RHS} of assignment + statement @code{G}. + @end deftypefn + ++@deftypefn {GIMPLE function} void gimple_assign_set_rhs3 (gimple g, tree rhs) ++Set @code{RHS} to be the third operand on the @code{RHS} of assignment ++statement @code{G}. ++@end deftypefn ++ + @deftypefn {GIMPLE function} bool gimple_assign_cast_p (gimple s) + Return true if @code{S} is a type-cast assignment. + @end deftypefn + +=== modified file 'gcc/expr.c' +--- old/gcc/expr.c 2010-09-01 13:29:58 +0000 ++++ new/gcc/expr.c 2010-09-16 09:15:46 +0000 +@@ -7225,8 +7225,6 @@ + rtx subtarget, original_target; + int ignore; + bool reduce_bit_field; +- gimple subexp0_def, subexp1_def; +- tree top0, top1; + location_t loc = ops->location; + tree treeop0, treeop1; + #define REDUCE_BIT_FIELD(expr) (reduce_bit_field \ +@@ -7246,7 +7244,8 @@ + exactly those that are valid in gimple expressions that aren't + GIMPLE_SINGLE_RHS (or invalid). */ + gcc_assert (get_gimple_rhs_class (code) == GIMPLE_UNARY_RHS +- || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS); ++ || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS ++ || get_gimple_rhs_class (code) == GIMPLE_TERNARY_RHS); + + ignore = (target == const0_rtx + || ((CONVERT_EXPR_CODE_P (code) +@@ -7421,58 +7420,6 @@ + fold_convert_loc (loc, ssizetype, + treeop1)); + case PLUS_EXPR: +- +- /* Check if this is a case for multiplication and addition. */ +- if ((TREE_CODE (type) == INTEGER_TYPE +- || TREE_CODE (type) == FIXED_POINT_TYPE) +- && (subexp0_def = get_def_for_expr (treeop0, +- MULT_EXPR))) +- { +- tree subsubexp0, subsubexp1; +- gimple subsubexp0_def, subsubexp1_def; +- enum tree_code this_code; +- +- this_code = TREE_CODE (type) == INTEGER_TYPE ? NOP_EXPR +- : FIXED_CONVERT_EXPR; +- subsubexp0 = gimple_assign_rhs1 (subexp0_def); +- subsubexp0_def = get_def_for_expr (subsubexp0, this_code); +- subsubexp1 = gimple_assign_rhs2 (subexp0_def); +- subsubexp1_def = get_def_for_expr (subsubexp1, this_code); +- if (subsubexp0_def && subsubexp1_def +- && (top0 = gimple_assign_rhs1 (subsubexp0_def)) +- && (top1 = gimple_assign_rhs1 (subsubexp1_def)) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- < TYPE_PRECISION (TREE_TYPE (subsubexp0))) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- == TYPE_PRECISION (TREE_TYPE (top1))) +- && (TYPE_UNSIGNED (TREE_TYPE (top0)) +- == TYPE_UNSIGNED (TREE_TYPE (top1)))) +- { +- tree op0type = TREE_TYPE (top0); +- enum machine_mode innermode = TYPE_MODE (op0type); +- bool zextend_p = TYPE_UNSIGNED (op0type); +- bool sat_p = TYPE_SATURATING (TREE_TYPE (subsubexp0)); +- if (sat_p == 0) +- this_optab = zextend_p ? umadd_widen_optab : smadd_widen_optab; +- else +- this_optab = zextend_p ? usmadd_widen_optab +- : ssmadd_widen_optab; +- if (mode == GET_MODE_2XWIDER_MODE (innermode) +- && (optab_handler (this_optab, mode)->insn_code +- != CODE_FOR_nothing)) +- { +- expand_operands (top0, top1, NULL_RTX, &op0, &op1, +- EXPAND_NORMAL); +- op2 = expand_expr (treeop1, subtarget, +- VOIDmode, EXPAND_NORMAL); +- temp = expand_ternary_op (mode, this_optab, op0, op1, op2, +- target, unsignedp); +- gcc_assert (temp); +- return REDUCE_BIT_FIELD (temp); +- } +- } +- } +- + /* If we are adding a constant, a VAR_DECL that is sp, fp, or ap, and + something else, make sure we add the register to the constant and + then to the other thing. This case can occur during strength +@@ -7587,57 +7534,6 @@ + return REDUCE_BIT_FIELD (simplify_gen_binary (PLUS, mode, op0, op1)); + + case MINUS_EXPR: +- /* Check if this is a case for multiplication and subtraction. */ +- if ((TREE_CODE (type) == INTEGER_TYPE +- || TREE_CODE (type) == FIXED_POINT_TYPE) +- && (subexp1_def = get_def_for_expr (treeop1, +- MULT_EXPR))) +- { +- tree subsubexp0, subsubexp1; +- gimple subsubexp0_def, subsubexp1_def; +- enum tree_code this_code; +- +- this_code = TREE_CODE (type) == INTEGER_TYPE ? NOP_EXPR +- : FIXED_CONVERT_EXPR; +- subsubexp0 = gimple_assign_rhs1 (subexp1_def); +- subsubexp0_def = get_def_for_expr (subsubexp0, this_code); +- subsubexp1 = gimple_assign_rhs2 (subexp1_def); +- subsubexp1_def = get_def_for_expr (subsubexp1, this_code); +- if (subsubexp0_def && subsubexp1_def +- && (top0 = gimple_assign_rhs1 (subsubexp0_def)) +- && (top1 = gimple_assign_rhs1 (subsubexp1_def)) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- < TYPE_PRECISION (TREE_TYPE (subsubexp0))) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- == TYPE_PRECISION (TREE_TYPE (top1))) +- && (TYPE_UNSIGNED (TREE_TYPE (top0)) +- == TYPE_UNSIGNED (TREE_TYPE (top1)))) +- { +- tree op0type = TREE_TYPE (top0); +- enum machine_mode innermode = TYPE_MODE (op0type); +- bool zextend_p = TYPE_UNSIGNED (op0type); +- bool sat_p = TYPE_SATURATING (TREE_TYPE (subsubexp0)); +- if (sat_p == 0) +- this_optab = zextend_p ? umsub_widen_optab : smsub_widen_optab; +- else +- this_optab = zextend_p ? usmsub_widen_optab +- : ssmsub_widen_optab; +- if (mode == GET_MODE_2XWIDER_MODE (innermode) +- && (optab_handler (this_optab, mode)->insn_code +- != CODE_FOR_nothing)) +- { +- expand_operands (top0, top1, NULL_RTX, &op0, &op1, +- EXPAND_NORMAL); +- op2 = expand_expr (treeop0, subtarget, +- VOIDmode, EXPAND_NORMAL); +- temp = expand_ternary_op (mode, this_optab, op0, op1, op2, +- target, unsignedp); +- gcc_assert (temp); +- return REDUCE_BIT_FIELD (temp); +- } +- } +- } +- + /* For initializers, we are allowed to return a MINUS of two + symbolic constants. Here we handle all cases when both operands + are constant. */ +@@ -7678,6 +7574,14 @@ + + goto binop2; + ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL); ++ op2 = expand_normal (ops->op2); ++ target = expand_widen_pattern_expr (ops, op0, op1, op2, ++ target, unsignedp); ++ return target; ++ + case WIDEN_MULT_EXPR: + /* If first operand is constant, swap them. + Thus the following special case checks need only + +=== modified file 'gcc/gimple-pretty-print.c' +--- old/gcc/gimple-pretty-print.c 2009-11-25 10:55:54 +0000 ++++ new/gcc/gimple-pretty-print.c 2010-09-16 09:15:46 +0000 +@@ -376,6 +376,34 @@ + } + } + ++/* Helper for dump_gimple_assign. Print the ternary RHS of the ++ assignment GS. BUFFER, SPC and FLAGS are as in dump_gimple_stmt. */ ++ ++static void ++dump_ternary_rhs (pretty_printer *buffer, gimple gs, int spc, int flags) ++{ ++ const char *p; ++ enum tree_code code = gimple_assign_rhs_code (gs); ++ switch (code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ for (p = tree_code_name [(int) code]; *p; p++) ++ pp_character (buffer, TOUPPER (*p)); ++ pp_string (buffer, " <"); ++ dump_generic_node (buffer, gimple_assign_rhs1 (gs), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, gimple_assign_rhs2 (gs), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, gimple_assign_rhs3 (gs), spc, flags, false); ++ pp_character (buffer, '>'); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ + + /* Dump the gimple assignment GS. BUFFER, SPC and FLAGS are as in + dump_gimple_stmt. */ +@@ -418,6 +446,8 @@ + dump_unary_rhs (buffer, gs, spc, flags); + else if (gimple_num_ops (gs) == 3) + dump_binary_rhs (buffer, gs, spc, flags); ++ else if (gimple_num_ops (gs) == 4) ++ dump_ternary_rhs (buffer, gs, spc, flags); + else + gcc_unreachable (); + if (!(flags & TDF_RHS_ONLY)) + +=== modified file 'gcc/gimple.c' +--- old/gcc/gimple.c 2010-09-15 16:47:52 +0000 ++++ new/gcc/gimple.c 2010-09-16 09:15:46 +0000 +@@ -289,31 +289,40 @@ + + + /* Extract the operands and code for expression EXPR into *SUBCODE_P, +- *OP1_P and *OP2_P respectively. */ ++ *OP1_P, *OP2_P and *OP3_P respectively. */ + + void +-extract_ops_from_tree (tree expr, enum tree_code *subcode_p, tree *op1_p, +- tree *op2_p) ++extract_ops_from_tree_1 (tree expr, enum tree_code *subcode_p, tree *op1_p, ++ tree *op2_p, tree *op3_p) + { + enum gimple_rhs_class grhs_class; + + *subcode_p = TREE_CODE (expr); + grhs_class = get_gimple_rhs_class (*subcode_p); + +- if (grhs_class == GIMPLE_BINARY_RHS) +- { +- *op1_p = TREE_OPERAND (expr, 0); +- *op2_p = TREE_OPERAND (expr, 1); ++ if (grhs_class == GIMPLE_TERNARY_RHS) ++ { ++ *op1_p = TREE_OPERAND (expr, 0); ++ *op2_p = TREE_OPERAND (expr, 1); ++ *op3_p = TREE_OPERAND (expr, 2); ++ } ++ else if (grhs_class == GIMPLE_BINARY_RHS) ++ { ++ *op1_p = TREE_OPERAND (expr, 0); ++ *op2_p = TREE_OPERAND (expr, 1); ++ *op3_p = NULL_TREE; + } + else if (grhs_class == GIMPLE_UNARY_RHS) + { + *op1_p = TREE_OPERAND (expr, 0); + *op2_p = NULL_TREE; ++ *op3_p = NULL_TREE; + } + else if (grhs_class == GIMPLE_SINGLE_RHS) + { + *op1_p = expr; + *op2_p = NULL_TREE; ++ *op3_p = NULL_TREE; + } + else + gcc_unreachable (); +@@ -329,10 +338,10 @@ + gimple_build_assign_stat (tree lhs, tree rhs MEM_STAT_DECL) + { + enum tree_code subcode; +- tree op1, op2; ++ tree op1, op2, op3; + +- extract_ops_from_tree (rhs, &subcode, &op1, &op2); +- return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2 ++ extract_ops_from_tree_1 (rhs, &subcode, &op1, &op2, &op3); ++ return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2, op3 + PASS_MEM_STAT); + } + +@@ -343,7 +352,7 @@ + + gimple + gimple_build_assign_with_ops_stat (enum tree_code subcode, tree lhs, tree op1, +- tree op2 MEM_STAT_DECL) ++ tree op2, tree op3 MEM_STAT_DECL) + { + unsigned num_ops; + gimple p; +@@ -362,6 +371,12 @@ + gimple_assign_set_rhs2 (p, op2); + } + ++ if (op3) ++ { ++ gcc_assert (num_ops > 3); ++ gimple_assign_set_rhs3 (p, op3); ++ } ++ + return p; + } + +@@ -1860,22 +1875,22 @@ + gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *gsi, tree expr) + { + enum tree_code subcode; +- tree op1, op2; ++ tree op1, op2, op3; + +- extract_ops_from_tree (expr, &subcode, &op1, &op2); +- gimple_assign_set_rhs_with_ops (gsi, subcode, op1, op2); ++ extract_ops_from_tree_1 (expr, &subcode, &op1, &op2, &op3); ++ gimple_assign_set_rhs_with_ops_1 (gsi, subcode, op1, op2, op3); + } + + + /* Set the RHS of assignment statement pointed-to by GSI to CODE with +- operands OP1 and OP2. ++ operands OP1, OP2 and OP3. + + NOTE: The statement pointed-to by GSI may be reallocated if it + did not have enough operand slots. */ + + void +-gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code, +- tree op1, tree op2) ++gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *gsi, enum tree_code code, ++ tree op1, tree op2, tree op3) + { + unsigned new_rhs_ops = get_gimple_rhs_num_ops (code); + gimple stmt = gsi_stmt (*gsi); +@@ -1899,6 +1914,8 @@ + gimple_assign_set_rhs1 (stmt, op1); + if (new_rhs_ops > 1) + gimple_assign_set_rhs2 (stmt, op2); ++ if (new_rhs_ops > 2) ++ gimple_assign_set_rhs3 (stmt, op3); + } + + +@@ -2378,6 +2395,8 @@ + return 1; + else if (rhs_class == GIMPLE_BINARY_RHS) + return 2; ++ else if (rhs_class == GIMPLE_TERNARY_RHS) ++ return 3; + else + gcc_unreachable (); + } +@@ -2394,6 +2413,8 @@ + || (SYM) == TRUTH_OR_EXPR \ + || (SYM) == TRUTH_XOR_EXPR) ? GIMPLE_BINARY_RHS \ + : (SYM) == TRUTH_NOT_EXPR ? GIMPLE_UNARY_RHS \ ++ : ((SYM) == WIDEN_MULT_PLUS_EXPR \ ++ || (SYM) == WIDEN_MULT_MINUS_EXPR) ? GIMPLE_TERNARY_RHS \ + : ((SYM) == COND_EXPR \ + || (SYM) == CONSTRUCTOR \ + || (SYM) == OBJ_TYPE_REF \ + +=== modified file 'gcc/gimple.h' +--- old/gcc/gimple.h 2010-08-10 13:31:21 +0000 ++++ new/gcc/gimple.h 2010-09-16 09:15:46 +0000 +@@ -80,6 +80,7 @@ + enum gimple_rhs_class + { + GIMPLE_INVALID_RHS, /* The expression cannot be used on the RHS. */ ++ GIMPLE_TERNARY_RHS, /* The expression is a ternary operation. */ + GIMPLE_BINARY_RHS, /* The expression is a binary operation. */ + GIMPLE_UNARY_RHS, /* The expression is a unary operation. */ + GIMPLE_SINGLE_RHS /* The expression is a single object (an SSA +@@ -786,12 +787,14 @@ + gimple gimple_build_assign_stat (tree, tree MEM_STAT_DECL); + #define gimple_build_assign(l,r) gimple_build_assign_stat (l, r MEM_STAT_INFO) + +-void extract_ops_from_tree (tree, enum tree_code *, tree *, tree *); ++void extract_ops_from_tree_1 (tree, enum tree_code *, tree *, tree *, tree *); + + gimple gimple_build_assign_with_ops_stat (enum tree_code, tree, tree, +- tree MEM_STAT_DECL); +-#define gimple_build_assign_with_ops(c,o1,o2,o3) \ +- gimple_build_assign_with_ops_stat (c, o1, o2, o3 MEM_STAT_INFO) ++ tree, tree MEM_STAT_DECL); ++#define gimple_build_assign_with_ops(c,o1,o2,o3) \ ++ gimple_build_assign_with_ops_stat (c, o1, o2, o3, NULL_TREE MEM_STAT_INFO) ++#define gimple_build_assign_with_ops3(c,o1,o2,o3,o4) \ ++ gimple_build_assign_with_ops_stat (c, o1, o2, o3, o4 MEM_STAT_INFO) + + gimple gimple_build_debug_bind_stat (tree, tree, gimple MEM_STAT_DECL); + #define gimple_build_debug_bind(var,val,stmt) \ +@@ -850,8 +853,8 @@ + bool gimple_assign_unary_nop_p (gimple); + void gimple_set_bb (gimple, struct basic_block_def *); + void gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *, tree); +-void gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *, enum tree_code, +- tree, tree); ++void gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *, enum tree_code, ++ tree, tree, tree); + tree gimple_get_lhs (const_gimple); + void gimple_set_lhs (gimple, tree); + void gimple_replace_lhs (gimple, tree); +@@ -1793,6 +1796,63 @@ + gimple_set_op (gs, 2, rhs); + } + ++/* Return the third operand on the RHS of assignment statement GS. ++ If GS does not have two operands, NULL is returned instead. */ ++ ++static inline tree ++gimple_assign_rhs3 (const_gimple gs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_ASSIGN); ++ ++ if (gimple_num_ops (gs) >= 4) ++ return gimple_op (gs, 3); ++ else ++ return NULL_TREE; ++} ++ ++/* Return a pointer to the third operand on the RHS of assignment ++ statement GS. */ ++ ++static inline tree * ++gimple_assign_rhs3_ptr (const_gimple gs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_ASSIGN); ++ return gimple_op_ptr (gs, 3); ++} ++ ++ ++/* Set RHS to be the third operand on the RHS of assignment statement GS. */ ++ ++static inline void ++gimple_assign_set_rhs3 (gimple gs, tree rhs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_ASSIGN); ++ ++ gimple_set_op (gs, 3, rhs); ++} ++ ++/* A wrapper around gimple_assign_set_rhs_with_ops_1, for callers which expect ++ to see only a maximum of two operands. */ ++ ++static inline void ++gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code, ++ tree op1, tree op2) ++{ ++ gimple_assign_set_rhs_with_ops_1 (gsi, code, op1, op2, NULL); ++} ++ ++/* A wrapper around extract_ops_from_tree_1, for callers which expect ++ to see only a maximum of two operands. */ ++ ++static inline void ++extract_ops_from_tree (tree expr, enum tree_code *code, tree *op0, ++ tree *op1) ++{ ++ tree op2; ++ extract_ops_from_tree_1 (expr, code, op0, op1, &op2); ++ gcc_assert (op2 == NULL_TREE); ++} ++ + /* Returns true if GS is a nontemporal move. */ + + static inline bool + +=== modified file 'gcc/optabs.c' +--- old/gcc/optabs.c 2010-03-19 19:45:01 +0000 ++++ new/gcc/optabs.c 2010-09-16 09:15:46 +0000 +@@ -408,6 +408,20 @@ + case DOT_PROD_EXPR: + return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; + ++ case WIDEN_MULT_PLUS_EXPR: ++ return (TYPE_UNSIGNED (type) ++ ? (TYPE_SATURATING (type) ++ ? usmadd_widen_optab : umadd_widen_optab) ++ : (TYPE_SATURATING (type) ++ ? ssmadd_widen_optab : smadd_widen_optab)); ++ ++ case WIDEN_MULT_MINUS_EXPR: ++ return (TYPE_UNSIGNED (type) ++ ? (TYPE_SATURATING (type) ++ ? usmsub_widen_optab : umsub_widen_optab) ++ : (TYPE_SATURATING (type) ++ ? ssmsub_widen_optab : smsub_widen_optab)); ++ + case REDUC_MAX_EXPR: + return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; + +@@ -547,7 +561,12 @@ + tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); + widen_pattern_optab = + optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default); +- icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; ++ if (ops->code == WIDEN_MULT_PLUS_EXPR ++ || ops->code == WIDEN_MULT_MINUS_EXPR) ++ icode = (int) optab_handler (widen_pattern_optab, ++ TYPE_MODE (TREE_TYPE (ops->op2)))->insn_code; ++ else ++ icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; + gcc_assert (icode != CODE_FOR_nothing); + xmode0 = insn_data[icode].operand[1].mode; + + +=== modified file 'gcc/testsuite/gcc.target/arm/wmul-1.c' +--- old/gcc/testsuite/gcc.target/arm/wmul-1.c 2010-09-01 13:29:58 +0000 ++++ new/gcc/testsuite/gcc.target/arm/wmul-1.c 2010-09-16 09:15:46 +0000 +@@ -15,4 +15,4 @@ + return sqr; + } + +-/* { dg-final { scan-assembler-times "smulbb" 2 } } */ ++/* { dg-final { scan-assembler-times "smlabb" 2 } } */ + +=== modified file 'gcc/tree-cfg.c' +--- old/gcc/tree-cfg.c 2010-09-01 13:29:58 +0000 ++++ new/gcc/tree-cfg.c 2010-09-16 09:15:46 +0000 +@@ -3483,6 +3483,65 @@ + return false; + } + ++/* Verify a gimple assignment statement STMT with a ternary rhs. ++ Returns true if anything is wrong. */ ++ ++static bool ++verify_gimple_assign_ternary (gimple stmt) ++{ ++ enum tree_code rhs_code = gimple_assign_rhs_code (stmt); ++ tree lhs = gimple_assign_lhs (stmt); ++ tree lhs_type = TREE_TYPE (lhs); ++ tree rhs1 = gimple_assign_rhs1 (stmt); ++ tree rhs1_type = TREE_TYPE (rhs1); ++ tree rhs2 = gimple_assign_rhs2 (stmt); ++ tree rhs2_type = TREE_TYPE (rhs2); ++ tree rhs3 = gimple_assign_rhs3 (stmt); ++ tree rhs3_type = TREE_TYPE (rhs3); ++ ++ if (!is_gimple_reg (lhs) ++ && !(optimize == 0 ++ && TREE_CODE (lhs_type) == COMPLEX_TYPE)) ++ { ++ error ("non-register as LHS of ternary operation"); ++ return true; ++ } ++ ++ if (!is_gimple_val (rhs1) ++ || !is_gimple_val (rhs2) ++ || !is_gimple_val (rhs3)) ++ { ++ error ("invalid operands in ternary operation"); ++ return true; ++ } ++ ++ /* First handle operations that involve different types. */ ++ switch (rhs_code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ if ((!INTEGRAL_TYPE_P (rhs1_type) ++ && !FIXED_POINT_TYPE_P (rhs1_type)) ++ || !useless_type_conversion_p (rhs1_type, rhs2_type) ++ || !useless_type_conversion_p (lhs_type, rhs3_type) ++ || 2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type) ++ || TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)) ++ { ++ error ("type mismatch in widening multiply-accumulate expression"); ++ debug_generic_expr (lhs_type); ++ debug_generic_expr (rhs1_type); ++ debug_generic_expr (rhs2_type); ++ debug_generic_expr (rhs3_type); ++ return true; ++ } ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ return false; ++} ++ + /* Verify a gimple assignment statement STMT with a single rhs. + Returns true if anything is wrong. */ + +@@ -3615,6 +3674,9 @@ + case GIMPLE_BINARY_RHS: + return verify_gimple_assign_binary (stmt); + ++ case GIMPLE_TERNARY_RHS: ++ return verify_gimple_assign_ternary (stmt); ++ + default: + gcc_unreachable (); + } + +=== modified file 'gcc/tree-inline.c' +--- old/gcc/tree-inline.c 2010-09-01 13:29:58 +0000 ++++ new/gcc/tree-inline.c 2010-09-16 09:15:46 +0000 +@@ -3199,6 +3199,8 @@ + case WIDEN_SUM_EXPR: + case WIDEN_MULT_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + + case VEC_WIDEN_MULT_HI_EXPR: + case VEC_WIDEN_MULT_LO_EXPR: + +=== modified file 'gcc/tree-pretty-print.c' +--- old/gcc/tree-pretty-print.c 2009-11-30 10:36:54 +0000 ++++ new/gcc/tree-pretty-print.c 2010-09-16 09:15:46 +0000 +@@ -1939,6 +1939,26 @@ + pp_string (buffer, " > "); + break; + ++ case WIDEN_MULT_PLUS_EXPR: ++ pp_string (buffer, " WIDEN_MULT_PLUS_EXPR < "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); ++ pp_string (buffer, " > "); ++ break; ++ ++ case WIDEN_MULT_MINUS_EXPR: ++ pp_string (buffer, " WIDEN_MULT_MINUS_EXPR < "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); ++ pp_string (buffer, " > "); ++ break; ++ + case OMP_PARALLEL: + pp_string (buffer, "#pragma omp parallel"); + dump_omp_clauses (buffer, OMP_PARALLEL_CLAUSES (node), spc, flags); +@@ -2432,6 +2452,8 @@ + case VEC_WIDEN_MULT_LO_EXPR: + case WIDEN_MULT_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + case MULT_EXPR: + case TRUNC_DIV_EXPR: + case CEIL_DIV_EXPR: + +=== modified file 'gcc/tree-ssa-ccp.c' +--- old/gcc/tree-ssa-ccp.c 2010-08-10 13:31:21 +0000 ++++ new/gcc/tree-ssa-ccp.c 2010-09-16 09:15:46 +0000 +@@ -915,6 +915,23 @@ + TREE_TYPE (TREE_OPERAND (addr, 0)))); + } + ++/* Get operand number OPNR from the rhs of STMT. Before returning it, ++ simplify it to a constant if possible. */ ++ ++static tree ++get_rhs_assign_op_for_ccp (gimple stmt, int opnr) ++{ ++ tree op = gimple_op (stmt, opnr); ++ ++ if (TREE_CODE (op) == SSA_NAME) ++ { ++ prop_value_t *val = get_value (op); ++ if (val->lattice_val == CONSTANT) ++ op = get_value (op)->value; ++ } ++ return op; ++} ++ + /* CCP specific front-end to the non-destructive constant folding + routines. + +@@ -1037,15 +1054,7 @@ + Note that we know the single operand must be a constant, + so this should almost always return a simplified RHS. */ + tree lhs = gimple_assign_lhs (stmt); +- tree op0 = gimple_assign_rhs1 (stmt); +- +- /* Simplify the operand down to a constant. */ +- if (TREE_CODE (op0) == SSA_NAME) +- { +- prop_value_t *val = get_value (op0); +- if (val->lattice_val == CONSTANT) +- op0 = get_value (op0)->value; +- } ++ tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); + + /* Conversions are useless for CCP purposes if they are + value-preserving. Thus the restrictions that +@@ -1082,23 +1091,8 @@ + case GIMPLE_BINARY_RHS: + { + /* Handle binary operators that can appear in GIMPLE form. */ +- tree op0 = gimple_assign_rhs1 (stmt); +- tree op1 = gimple_assign_rhs2 (stmt); +- +- /* Simplify the operands down to constants when appropriate. */ +- if (TREE_CODE (op0) == SSA_NAME) +- { +- prop_value_t *val = get_value (op0); +- if (val->lattice_val == CONSTANT) +- op0 = val->value; +- } +- +- if (TREE_CODE (op1) == SSA_NAME) +- { +- prop_value_t *val = get_value (op1); +- if (val->lattice_val == CONSTANT) +- op1 = val->value; +- } ++ tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); ++ tree op1 = get_rhs_assign_op_for_ccp (stmt, 2); + + /* Fold &foo + CST into an invariant reference if possible. */ + if (gimple_assign_rhs_code (stmt) == POINTER_PLUS_EXPR +@@ -1115,6 +1109,17 @@ + gimple_expr_type (stmt), op0, op1); + } + ++ case GIMPLE_TERNARY_RHS: ++ { ++ /* Handle binary operators that can appear in GIMPLE form. */ ++ tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); ++ tree op1 = get_rhs_assign_op_for_ccp (stmt, 2); ++ tree op2 = get_rhs_assign_op_for_ccp (stmt, 3); ++ ++ return fold_ternary_loc (loc, subcode, ++ gimple_expr_type (stmt), op0, op1, op2); ++ } ++ + default: + gcc_unreachable (); + } +@@ -2959,6 +2964,33 @@ + } + break; + ++ case GIMPLE_TERNARY_RHS: ++ result = fold_ternary_loc (loc, subcode, ++ TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ ++ if (result) ++ { ++ STRIP_USELESS_TYPE_CONVERSION (result); ++ if (valid_gimple_rhs_p (result)) ++ return result; ++ ++ /* Fold might have produced non-GIMPLE, so if we trust it blindly ++ we lose canonicalization opportunities. Do not go again ++ through fold here though, or the same non-GIMPLE will be ++ produced. */ ++ if (commutative_ternary_tree_code (subcode) ++ && tree_swap_operands_p (gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), false)) ++ return build3 (subcode, TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ } ++ break; ++ + case GIMPLE_INVALID_RHS: + gcc_unreachable (); + } + +=== modified file 'gcc/tree-ssa-dom.c' +--- old/gcc/tree-ssa-dom.c 2010-07-20 11:44:16 +0000 ++++ new/gcc/tree-ssa-dom.c 2010-09-16 09:15:46 +0000 +@@ -54,6 +54,7 @@ + EXPR_SINGLE, + EXPR_UNARY, + EXPR_BINARY, ++ EXPR_TERNARY, + EXPR_CALL + }; + +@@ -64,7 +65,8 @@ + union { + struct { tree rhs; } single; + struct { enum tree_code op; tree opnd; } unary; +- struct { enum tree_code op; tree opnd0; tree opnd1; } binary; ++ struct { enum tree_code op; tree opnd0, opnd1; } binary; ++ struct { enum tree_code op; tree opnd0, opnd1, opnd2; } ternary; + struct { tree fn; bool pure; size_t nargs; tree *args; } call; + } ops; + }; +@@ -214,22 +216,30 @@ + switch (get_gimple_rhs_class (subcode)) + { + case GIMPLE_SINGLE_RHS: +- expr->kind = EXPR_SINGLE; +- expr->ops.single.rhs = gimple_assign_rhs1 (stmt); +- break; ++ expr->kind = EXPR_SINGLE; ++ expr->ops.single.rhs = gimple_assign_rhs1 (stmt); ++ break; + case GIMPLE_UNARY_RHS: +- expr->kind = EXPR_UNARY; ++ expr->kind = EXPR_UNARY; + expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); +- expr->ops.unary.op = subcode; +- expr->ops.unary.opnd = gimple_assign_rhs1 (stmt); +- break; ++ expr->ops.unary.op = subcode; ++ expr->ops.unary.opnd = gimple_assign_rhs1 (stmt); ++ break; + case GIMPLE_BINARY_RHS: +- expr->kind = EXPR_BINARY; +- expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); +- expr->ops.binary.op = subcode; +- expr->ops.binary.opnd0 = gimple_assign_rhs1 (stmt); +- expr->ops.binary.opnd1 = gimple_assign_rhs2 (stmt); +- break; ++ expr->kind = EXPR_BINARY; ++ expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); ++ expr->ops.binary.op = subcode; ++ expr->ops.binary.opnd0 = gimple_assign_rhs1 (stmt); ++ expr->ops.binary.opnd1 = gimple_assign_rhs2 (stmt); ++ break; ++ case GIMPLE_TERNARY_RHS: ++ expr->kind = EXPR_TERNARY; ++ expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); ++ expr->ops.ternary.op = subcode; ++ expr->ops.ternary.opnd0 = gimple_assign_rhs1 (stmt); ++ expr->ops.ternary.opnd1 = gimple_assign_rhs2 (stmt); ++ expr->ops.ternary.opnd2 = gimple_assign_rhs3 (stmt); ++ break; + default: + gcc_unreachable (); + } +@@ -374,23 +384,40 @@ + expr1->ops.unary.opnd, 0); + + case EXPR_BINARY: +- { +- if (expr0->ops.binary.op != expr1->ops.binary.op) +- return false; +- +- if (operand_equal_p (expr0->ops.binary.opnd0, +- expr1->ops.binary.opnd0, 0) +- && operand_equal_p (expr0->ops.binary.opnd1, +- expr1->ops.binary.opnd1, 0)) +- return true; +- +- /* For commutative ops, allow the other order. */ +- return (commutative_tree_code (expr0->ops.binary.op) +- && operand_equal_p (expr0->ops.binary.opnd0, +- expr1->ops.binary.opnd1, 0) +- && operand_equal_p (expr0->ops.binary.opnd1, +- expr1->ops.binary.opnd0, 0)); +- } ++ if (expr0->ops.binary.op != expr1->ops.binary.op) ++ return false; ++ ++ if (operand_equal_p (expr0->ops.binary.opnd0, ++ expr1->ops.binary.opnd0, 0) ++ && operand_equal_p (expr0->ops.binary.opnd1, ++ expr1->ops.binary.opnd1, 0)) ++ return true; ++ ++ /* For commutative ops, allow the other order. */ ++ return (commutative_tree_code (expr0->ops.binary.op) ++ && operand_equal_p (expr0->ops.binary.opnd0, ++ expr1->ops.binary.opnd1, 0) ++ && operand_equal_p (expr0->ops.binary.opnd1, ++ expr1->ops.binary.opnd0, 0)); ++ ++ case EXPR_TERNARY: ++ if (expr0->ops.ternary.op != expr1->ops.ternary.op ++ || !operand_equal_p (expr0->ops.ternary.opnd2, ++ expr1->ops.ternary.opnd2, 0)) ++ return false; ++ ++ if (operand_equal_p (expr0->ops.ternary.opnd0, ++ expr1->ops.ternary.opnd0, 0) ++ && operand_equal_p (expr0->ops.ternary.opnd1, ++ expr1->ops.ternary.opnd1, 0)) ++ return true; ++ ++ /* For commutative ops, allow the other order. */ ++ return (commutative_ternary_tree_code (expr0->ops.ternary.op) ++ && operand_equal_p (expr0->ops.ternary.opnd0, ++ expr1->ops.ternary.opnd1, 0) ++ && operand_equal_p (expr0->ops.ternary.opnd1, ++ expr1->ops.ternary.opnd0, 0)); + + case EXPR_CALL: + { +@@ -453,8 +480,8 @@ + case EXPR_BINARY: + val = iterative_hash_object (expr->ops.binary.op, val); + if (commutative_tree_code (expr->ops.binary.op)) +- val = iterative_hash_exprs_commutative (expr->ops.binary.opnd0, +- expr->ops.binary.opnd1, val); ++ val = iterative_hash_exprs_commutative (expr->ops.binary.opnd0, ++ expr->ops.binary.opnd1, val); + else + { + val = iterative_hash_expr (expr->ops.binary.opnd0, val); +@@ -462,6 +489,19 @@ + } + break; + ++ case EXPR_TERNARY: ++ val = iterative_hash_object (expr->ops.ternary.op, val); ++ if (commutative_ternary_tree_code (expr->ops.ternary.op)) ++ val = iterative_hash_exprs_commutative (expr->ops.ternary.opnd0, ++ expr->ops.ternary.opnd1, val); ++ else ++ { ++ val = iterative_hash_expr (expr->ops.ternary.opnd0, val); ++ val = iterative_hash_expr (expr->ops.ternary.opnd1, val); ++ } ++ val = iterative_hash_expr (expr->ops.ternary.opnd2, val); ++ break; ++ + case EXPR_CALL: + { + size_t i; +@@ -514,6 +554,16 @@ + print_generic_expr (stream, element->expr.ops.binary.opnd1, 0); + break; + ++ case EXPR_TERNARY: ++ fprintf (stream, " %s <", tree_code_name[element->expr.ops.ternary.op]); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd0, 0); ++ fputs (", ", stream); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd1, 0); ++ fputs (", ", stream); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd2, 0); ++ fputs (">", stream); ++ break; ++ + case EXPR_CALL: + { + size_t i; + +=== modified file 'gcc/tree-ssa-math-opts.c' +--- old/gcc/tree-ssa-math-opts.c 2010-09-01 13:29:58 +0000 ++++ new/gcc/tree-ssa-math-opts.c 2010-09-16 09:15:46 +0000 +@@ -1261,6 +1261,235 @@ + } + }; + ++/* Return true if RHS is a suitable operand for a widening multiplication. ++ There are two cases: ++ ++ - RHS makes some value twice as wide. Store that value in *NEW_RHS_OUT ++ if so, and store its type in *TYPE_OUT. ++ ++ - RHS is an integer constant. Store that value in *NEW_RHS_OUT if so, ++ but leave *TYPE_OUT untouched. */ ++ ++static bool ++is_widening_mult_rhs_p (tree rhs, tree *type_out, tree *new_rhs_out) ++{ ++ gimple stmt; ++ tree type, type1, rhs1; ++ enum tree_code rhs_code; ++ ++ if (TREE_CODE (rhs) == SSA_NAME) ++ { ++ type = TREE_TYPE (rhs); ++ stmt = SSA_NAME_DEF_STMT (rhs); ++ if (!is_gimple_assign (stmt)) ++ return false; ++ ++ rhs_code = gimple_assign_rhs_code (stmt); ++ if (TREE_CODE (type) == INTEGER_TYPE ++ ? !CONVERT_EXPR_CODE_P (rhs_code) ++ : rhs_code != FIXED_CONVERT_EXPR) ++ return false; ++ ++ rhs1 = gimple_assign_rhs1 (stmt); ++ type1 = TREE_TYPE (rhs1); ++ if (TREE_CODE (type1) != TREE_CODE (type) ++ || TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type)) ++ return false; ++ ++ *new_rhs_out = rhs1; ++ *type_out = type1; ++ return true; ++ } ++ ++ if (TREE_CODE (rhs) == INTEGER_CST) ++ { ++ *new_rhs_out = rhs; ++ *type_out = NULL; ++ return true; ++ } ++ ++ return false; ++} ++ ++/* Return true if STMT performs a widening multiplication. If so, ++ store the unwidened types of the operands in *TYPE1_OUT and *TYPE2_OUT ++ respectively. Also fill *RHS1_OUT and *RHS2_OUT such that converting ++ those operands to types *TYPE1_OUT and *TYPE2_OUT would give the ++ operands of the multiplication. */ ++ ++static bool ++is_widening_mult_p (gimple stmt, ++ tree *type1_out, tree *rhs1_out, ++ tree *type2_out, tree *rhs2_out) ++{ ++ tree type; ++ ++ type = TREE_TYPE (gimple_assign_lhs (stmt)); ++ if (TREE_CODE (type) != INTEGER_TYPE ++ && TREE_CODE (type) != FIXED_POINT_TYPE) ++ return false; ++ ++ if (!is_widening_mult_rhs_p (gimple_assign_rhs1 (stmt), type1_out, rhs1_out)) ++ return false; ++ ++ if (!is_widening_mult_rhs_p (gimple_assign_rhs2 (stmt), type2_out, rhs2_out)) ++ return false; ++ ++ if (*type1_out == NULL) ++ { ++ if (*type2_out == NULL || !int_fits_type_p (*rhs1_out, *type2_out)) ++ return false; ++ *type1_out = *type2_out; ++ } ++ ++ if (*type2_out == NULL) ++ { ++ if (!int_fits_type_p (*rhs2_out, *type1_out)) ++ return false; ++ *type2_out = *type1_out; ++ } ++ ++ return true; ++} ++ ++/* Process a single gimple statement STMT, which has a MULT_EXPR as ++ its rhs, and try to convert it into a WIDEN_MULT_EXPR. The return ++ value is true iff we converted the statement. */ ++ ++static bool ++convert_mult_to_widen (gimple stmt) ++{ ++ tree lhs, rhs1, rhs2, type, type1, type2; ++ enum insn_code handler; ++ ++ lhs = gimple_assign_lhs (stmt); ++ type = TREE_TYPE (lhs); ++ if (TREE_CODE (type) != INTEGER_TYPE) ++ return false; ++ ++ if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2)) ++ return false; ++ ++ if (TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2)) ++ handler = optab_handler (umul_widen_optab, TYPE_MODE (type))->insn_code; ++ else if (!TYPE_UNSIGNED (type1) && !TYPE_UNSIGNED (type2)) ++ handler = optab_handler (smul_widen_optab, TYPE_MODE (type))->insn_code; ++ else ++ handler = optab_handler (usmul_widen_optab, TYPE_MODE (type))->insn_code; ++ ++ if (handler == CODE_FOR_nothing) ++ return false; ++ ++ gimple_assign_set_rhs1 (stmt, fold_convert (type1, rhs1)); ++ gimple_assign_set_rhs2 (stmt, fold_convert (type2, rhs2)); ++ gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR); ++ update_stmt (stmt); ++ return true; ++} ++ ++/* Process a single gimple statement STMT, which is found at the ++ iterator GSI and has a either a PLUS_EXPR or a MINUS_EXPR as its ++ rhs (given by CODE), and try to convert it into a ++ WIDEN_MULT_PLUS_EXPR or a WIDEN_MULT_MINUS_EXPR. The return value ++ is true iff we converted the statement. */ ++ ++static bool ++convert_plusminus_to_widen (gimple_stmt_iterator *gsi, gimple stmt, ++ enum tree_code code) ++{ ++ gimple rhs1_stmt = NULL, rhs2_stmt = NULL; ++ tree type, type1, type2; ++ tree lhs, rhs1, rhs2, mult_rhs1, mult_rhs2, add_rhs; ++ enum tree_code rhs1_code = ERROR_MARK, rhs2_code = ERROR_MARK; ++ optab this_optab; ++ enum tree_code wmult_code; ++ ++ lhs = gimple_assign_lhs (stmt); ++ type = TREE_TYPE (lhs); ++ if (TREE_CODE (type) != INTEGER_TYPE ++ && TREE_CODE (type) != FIXED_POINT_TYPE) ++ return false; ++ ++ if (code == MINUS_EXPR) ++ wmult_code = WIDEN_MULT_MINUS_EXPR; ++ else ++ wmult_code = WIDEN_MULT_PLUS_EXPR; ++ ++ rhs1 = gimple_assign_rhs1 (stmt); ++ rhs2 = gimple_assign_rhs2 (stmt); ++ ++ if (TREE_CODE (rhs1) == SSA_NAME) ++ { ++ rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); ++ if (is_gimple_assign (rhs1_stmt)) ++ rhs1_code = gimple_assign_rhs_code (rhs1_stmt); ++ } ++ else ++ return false; ++ ++ if (TREE_CODE (rhs2) == SSA_NAME) ++ { ++ rhs2_stmt = SSA_NAME_DEF_STMT (rhs2); ++ if (is_gimple_assign (rhs2_stmt)) ++ rhs2_code = gimple_assign_rhs_code (rhs2_stmt); ++ } ++ else ++ return false; ++ ++ if (code == PLUS_EXPR && rhs1_code == MULT_EXPR) ++ { ++ if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1, ++ &type2, &mult_rhs2)) ++ return false; ++ add_rhs = rhs2; ++ } ++ else if (rhs2_code == MULT_EXPR) ++ { ++ if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1, ++ &type2, &mult_rhs2)) ++ return false; ++ add_rhs = rhs1; ++ } ++ else if (code == PLUS_EXPR && rhs1_code == WIDEN_MULT_EXPR) ++ { ++ mult_rhs1 = gimple_assign_rhs1 (rhs1_stmt); ++ mult_rhs2 = gimple_assign_rhs2 (rhs1_stmt); ++ type1 = TREE_TYPE (mult_rhs1); ++ type2 = TREE_TYPE (mult_rhs2); ++ add_rhs = rhs2; ++ } ++ else if (rhs2_code == WIDEN_MULT_EXPR) ++ { ++ mult_rhs1 = gimple_assign_rhs1 (rhs2_stmt); ++ mult_rhs2 = gimple_assign_rhs2 (rhs2_stmt); ++ type1 = TREE_TYPE (mult_rhs1); ++ type2 = TREE_TYPE (mult_rhs2); ++ add_rhs = rhs1; ++ } ++ else ++ return false; ++ ++ if (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) ++ return false; ++ ++ /* Verify that the machine can perform a widening multiply ++ accumulate in this mode/signedness combination, otherwise ++ this transformation is likely to pessimize code. */ ++ this_optab = optab_for_tree_code (wmult_code, type1, optab_default); ++ if (optab_handler (this_optab, TYPE_MODE (type))->insn_code ++ == CODE_FOR_nothing) ++ return false; ++ ++ /* ??? May need some type verification here? */ ++ ++ gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, ++ fold_convert (type1, mult_rhs1), ++ fold_convert (type2, mult_rhs2), ++ add_rhs); ++ update_stmt (gsi_stmt (*gsi)); ++ return true; ++} ++ + /* Find integer multiplications where the operands are extended from + smaller types, and replace the MULT_EXPR with a WIDEN_MULT_EXPR + where appropriate. */ +@@ -1278,94 +1507,19 @@ + for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi); gsi_next (&gsi)) + { + gimple stmt = gsi_stmt (gsi); +- gimple rhs1_stmt = NULL, rhs2_stmt = NULL; +- tree type, type1 = NULL, type2 = NULL; +- tree rhs1, rhs2, rhs1_convop = NULL, rhs2_convop = NULL; +- enum tree_code rhs1_code, rhs2_code; +- +- if (!is_gimple_assign (stmt) +- || gimple_assign_rhs_code (stmt) != MULT_EXPR) +- continue; +- +- type = TREE_TYPE (gimple_assign_lhs (stmt)); +- +- if (TREE_CODE (type) != INTEGER_TYPE) +- continue; +- +- rhs1 = gimple_assign_rhs1 (stmt); +- rhs2 = gimple_assign_rhs2 (stmt); +- +- if (TREE_CODE (rhs1) == SSA_NAME) +- { +- rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); +- if (!is_gimple_assign (rhs1_stmt)) +- continue; +- rhs1_code = gimple_assign_rhs_code (rhs1_stmt); +- if (!CONVERT_EXPR_CODE_P (rhs1_code)) +- continue; +- rhs1_convop = gimple_assign_rhs1 (rhs1_stmt); +- type1 = TREE_TYPE (rhs1_convop); +- if (TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type)) +- continue; +- } +- else if (TREE_CODE (rhs1) != INTEGER_CST) +- continue; +- +- if (TREE_CODE (rhs2) == SSA_NAME) +- { +- rhs2_stmt = SSA_NAME_DEF_STMT (rhs2); +- if (!is_gimple_assign (rhs2_stmt)) +- continue; +- rhs2_code = gimple_assign_rhs_code (rhs2_stmt); +- if (!CONVERT_EXPR_CODE_P (rhs2_code)) +- continue; +- rhs2_convop = gimple_assign_rhs1 (rhs2_stmt); +- type2 = TREE_TYPE (rhs2_convop); +- if (TYPE_PRECISION (type2) * 2 != TYPE_PRECISION (type)) +- continue; +- } +- else if (TREE_CODE (rhs2) != INTEGER_CST) +- continue; +- +- if (rhs1_stmt == NULL && rhs2_stmt == NULL) +- continue; +- +- /* Verify that the machine can perform a widening multiply in this +- mode/signedness combination, otherwise this transformation is +- likely to pessimize code. */ +- if ((rhs1_stmt == NULL || TYPE_UNSIGNED (type1)) +- && (rhs2_stmt == NULL || TYPE_UNSIGNED (type2)) +- && (optab_handler (umul_widen_optab, TYPE_MODE (type)) +- ->insn_code == CODE_FOR_nothing)) +- continue; +- else if ((rhs1_stmt == NULL || !TYPE_UNSIGNED (type1)) +- && (rhs2_stmt == NULL || !TYPE_UNSIGNED (type2)) +- && (optab_handler (smul_widen_optab, TYPE_MODE (type)) +- ->insn_code == CODE_FOR_nothing)) +- continue; +- else if (rhs1_stmt != NULL && rhs2_stmt != 0 +- && (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) +- && (optab_handler (usmul_widen_optab, TYPE_MODE (type)) +- ->insn_code == CODE_FOR_nothing)) +- continue; +- +- if ((rhs1_stmt == NULL && !int_fits_type_p (rhs1, type2)) +- || (rhs2_stmt == NULL && !int_fits_type_p (rhs2, type1))) +- continue; +- +- if (rhs1_stmt == NULL) +- gimple_assign_set_rhs1 (stmt, fold_convert (type2, rhs1)); +- else +- gimple_assign_set_rhs1 (stmt, rhs1_convop); +- if (rhs2_stmt == NULL) +- gimple_assign_set_rhs2 (stmt, fold_convert (type1, rhs2)); +- else +- gimple_assign_set_rhs2 (stmt, rhs2_convop); +- gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR); +- update_stmt (stmt); +- changed = true; ++ enum tree_code code; ++ ++ if (!is_gimple_assign (stmt)) ++ continue; ++ ++ code = gimple_assign_rhs_code (stmt); ++ if (code == MULT_EXPR) ++ changed |= convert_mult_to_widen (stmt); ++ else if (code == PLUS_EXPR || code == MINUS_EXPR) ++ changed |= convert_plusminus_to_widen (&gsi, stmt, code); + } + } ++ + return (changed ? TODO_dump_func | TODO_update_ssa | TODO_verify_ssa + | TODO_verify_stmts : 0); + } + +=== modified file 'gcc/tree-ssa-operands.c' +--- old/gcc/tree-ssa-operands.c 2010-04-02 18:54:46 +0000 ++++ new/gcc/tree-ssa-operands.c 2010-09-16 09:15:46 +0000 +@@ -994,11 +994,13 @@ + + case DOT_PROD_EXPR: + case REALIGN_LOAD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + { + get_expr_operands (stmt, &TREE_OPERAND (expr, 0), flags); +- get_expr_operands (stmt, &TREE_OPERAND (expr, 1), flags); +- get_expr_operands (stmt, &TREE_OPERAND (expr, 2), flags); +- return; ++ get_expr_operands (stmt, &TREE_OPERAND (expr, 1), flags); ++ get_expr_operands (stmt, &TREE_OPERAND (expr, 2), flags); ++ return; + } + + case FUNCTION_DECL: + +=== modified file 'gcc/tree-ssa-sccvn.c' +--- old/gcc/tree-ssa-sccvn.c 2010-05-14 11:40:18 +0000 ++++ new/gcc/tree-ssa-sccvn.c 2010-09-16 09:15:46 +0000 +@@ -2277,6 +2277,10 @@ + case GIMPLE_BINARY_RHS: + return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt)) + || is_gimple_min_invariant (gimple_assign_rhs2 (stmt))); ++ case GIMPLE_TERNARY_RHS: ++ return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt)) ++ || is_gimple_min_invariant (gimple_assign_rhs2 (stmt)) ++ || is_gimple_min_invariant (gimple_assign_rhs3 (stmt))); + case GIMPLE_SINGLE_RHS: + /* Constants inside reference ops are rarely interesting, but + it can take a lot of looking to find them. */ + +=== modified file 'gcc/tree-ssa-threadedge.c' +--- old/gcc/tree-ssa-threadedge.c 2009-11-25 10:55:54 +0000 ++++ new/gcc/tree-ssa-threadedge.c 2010-09-16 09:15:46 +0000 +@@ -247,14 +247,14 @@ + + return fold (rhs); + } +- break; ++ + case GIMPLE_UNARY_RHS: + { + tree lhs = gimple_assign_lhs (stmt); + tree op0 = gimple_assign_rhs1 (stmt); + return fold_unary (subcode, TREE_TYPE (lhs), op0); + } +- break; ++ + case GIMPLE_BINARY_RHS: + { + tree lhs = gimple_assign_lhs (stmt); +@@ -262,7 +262,16 @@ + tree op1 = gimple_assign_rhs2 (stmt); + return fold_binary (subcode, TREE_TYPE (lhs), op0, op1); + } +- break; ++ ++ case GIMPLE_TERNARY_RHS: ++ { ++ tree lhs = gimple_assign_lhs (stmt); ++ tree op0 = gimple_assign_rhs1 (stmt); ++ tree op1 = gimple_assign_rhs2 (stmt); ++ tree op2 = gimple_assign_rhs3 (stmt); ++ return fold_ternary (subcode, TREE_TYPE (lhs), op0, op1, op2); ++ } ++ + default: + gcc_unreachable (); + } + +=== modified file 'gcc/tree-vrp.c' +--- old/gcc/tree-vrp.c 2010-06-14 14:23:31 +0000 ++++ new/gcc/tree-vrp.c 2010-09-16 09:15:46 +0000 +@@ -864,6 +864,8 @@ + gimple_assign_rhs1 (stmt), + gimple_assign_rhs2 (stmt), + strict_overflow_p); ++ case GIMPLE_TERNARY_RHS: ++ return false; + case GIMPLE_SINGLE_RHS: + return tree_single_nonnegative_warnv_p (gimple_assign_rhs1 (stmt), + strict_overflow_p); +@@ -935,6 +937,8 @@ + gimple_assign_rhs1 (stmt), + gimple_assign_rhs2 (stmt), + strict_overflow_p); ++ case GIMPLE_TERNARY_RHS: ++ return false; + case GIMPLE_SINGLE_RHS: + return tree_single_nonzero_warnv_p (gimple_assign_rhs1 (stmt), + strict_overflow_p); + +=== modified file 'gcc/tree.c' +--- old/gcc/tree.c 2010-08-10 13:31:21 +0000 ++++ new/gcc/tree.c 2010-09-16 09:15:46 +0000 +@@ -6538,6 +6538,23 @@ + return false; + } + ++/* Return true if CODE represents a ternary tree code for which the ++ first two operands are commutative. Otherwise return false. */ ++bool ++commutative_ternary_tree_code (enum tree_code code) ++{ ++ switch (code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ return true; ++ ++ default: ++ break; ++ } ++ return false; ++} ++ + /* Generate a hash value for an expression. This can be used iteratively + by passing a previous result as the VAL argument. + + +=== modified file 'gcc/tree.def' +--- old/gcc/tree.def 2010-04-02 18:54:46 +0000 ++++ new/gcc/tree.def 2010-09-16 09:15:46 +0000 +@@ -1083,6 +1083,18 @@ + the arguments from type t1 to type t2, and then multiplying them. */ + DEFTREECODE (WIDEN_MULT_EXPR, "widen_mult_expr", tcc_binary, 2) + ++/* Widening multiply-accumulate. ++ The first two arguments are of type t1. ++ The third argument and the result are of type t2, such as t2 is at least ++ twice the size of t1. t1 and t2 must be integral or fixed-point types. ++ The expression is equivalent to a WIDEN_MULT_EXPR operation ++ of the first two operands followed by an add or subtract of the third ++ operand. */ ++DEFTREECODE (WIDEN_MULT_PLUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3) ++/* This is like the above, except in the final expression the multiply result ++ is subtracted from t3. */ ++DEFTREECODE (WIDEN_MULT_MINUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3) ++ + /* Whole vector left/right shift in bits. + Operand 0 is a vector to be shifted. + Operand 1 is an integer shift amount in bits. */ + +=== modified file 'gcc/tree.h' +--- old/gcc/tree.h 2010-08-10 13:31:21 +0000 ++++ new/gcc/tree.h 2010-09-16 09:15:46 +0000 +@@ -4705,6 +4705,7 @@ + extern int type_num_arguments (const_tree); + extern bool associative_tree_code (enum tree_code); + extern bool commutative_tree_code (enum tree_code); ++extern bool commutative_ternary_tree_code (enum tree_code); + extern tree upper_bound_in_type (tree, tree); + extern tree lower_bound_in_type (tree, tree); + extern int operand_equal_for_phi_arg_p (const_tree, const_tree); + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch new file mode 100644 index 0000000000..e795d54e0f --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch @@ -0,0 +1,3565 @@ +2010-09-16 Andrew Stubbs + + Backport from FSF: + + 2010-09-01 Ramana Radhakrishnan + + * config/arm/neon-schedgen.ml (core): New type. + (allCores): List of supported cores. + (availability_table): Add supported cores. + (collate_bypasses): Accept core as a parameter. + (worst_case_latencies_and_bypasses): Accept core as a + parameter. + (emit_insn_reservations): Accept core as a parameter. + Use tuneStr and coreStr to get tune attribute and prefix + for functional units. + (emit_bypasses): Accept core name and use it. + (calculate_per_core_availability_table): New. + (filter_core): New. + (calculate_core_availability_table): New. + (main): Use calculate_core_availablity_table. + * config/arm/cortex-a8-neon.md: Update copyright year. + Regenerated from ml file and merged in. + (neon_mrrc, neon_mrc): Rename to cortex_a8_neon_mrrc and + cortex_a8_neon_mrc. + + 2010-09-10 Ramana Radhakrishnan + + * config/arm/neon-schedgen.ml (allCores): Add support for + Cortex-A9. + * config/arm/cortex-a9-neon.md: New and partially generated. + * config/arm/cortex-a9.md (cortex_a9_dp): Adjust for Neon. + + 2010-09-15 Chung-Lin Tang + + Issue #9441 + +=== modified file 'gcc/config/arm/cortex-a8-neon.md' +--- old/gcc/config/arm/cortex-a8-neon.md 2009-02-20 15:20:38 +0000 ++++ new/gcc/config/arm/cortex-a8-neon.md 2010-09-16 09:47:44 +0000 +@@ -182,12 +182,12 @@ + + ;; NEON -> core transfers. + +-(define_insn_reservation "neon_mrc" 20 ++(define_insn_reservation "cortex_a8_neon_mrc" 20 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mrc")) + "cortex_a8_neon_ls") + +-(define_insn_reservation "neon_mrrc" 21 ++(define_insn_reservation "cortex_a8_neon_mrrc" 21 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mrrc")) + "cortex_a8_neon_ls_2") +@@ -196,48 +196,48 @@ + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N3. +-(define_insn_reservation "neon_int_1" 3 ++(define_insn_reservation "cortex_a8_neon_int_1" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_1")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their (D|Q)m operands at N1, + ;; their (D|Q)n operands at N2, and produce a result at N3. +-(define_insn_reservation "neon_int_2" 3 ++(define_insn_reservation "cortex_a8_neon_int_2" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_2")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N3. +-(define_insn_reservation "neon_int_3" 3 ++(define_insn_reservation "cortex_a8_neon_int_3" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_3")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N4. +-(define_insn_reservation "neon_int_4" 4 ++(define_insn_reservation "cortex_a8_neon_int_4" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_4")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their (D|Q)m operands at N1, + ;; their (D|Q)n operands at N2, and produce a result at N4. +-(define_insn_reservation "neon_int_5" 4 ++(define_insn_reservation "cortex_a8_neon_int_5" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_5")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N4. +-(define_insn_reservation "neon_vqneg_vqabs" 4 ++(define_insn_reservation "cortex_a8_neon_vqneg_vqabs" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vqneg_vqabs")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation produce a result at N3. +-(define_insn_reservation "neon_vmov" 3 ++(define_insn_reservation "cortex_a8_neon_vmov" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vmov")) + "cortex_a8_neon_dp") +@@ -245,7 +245,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6. +-(define_insn_reservation "neon_vaba" 6 ++(define_insn_reservation "cortex_a8_neon_vaba" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vaba")) + "cortex_a8_neon_dp") +@@ -253,35 +253,35 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_vaba_qqq" 7 ++(define_insn_reservation "cortex_a8_neon_vaba_qqq" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vaba_qqq")) + "cortex_a8_neon_dp_2") + + ;; Instructions using this reservation read their (D|Q)m operands at N1, + ;; their (D|Q)d operands at N3, and produce a result at N6. +-(define_insn_reservation "neon_vsma" 6 ++(define_insn_reservation "cortex_a8_neon_vsma" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vsma")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N6. +-(define_insn_reservation "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++(define_insn_reservation "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_mul_qqq_8_16_32_ddd_32" 7 ++(define_insn_reservation "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) + "cortex_a8_neon_dp_2") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 ++(define_insn_reservation "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) + "cortex_a8_neon_dp_2") +@@ -289,7 +289,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and + ;; produce a result at N6. +-(define_insn_reservation "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++(define_insn_reservation "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) + "cortex_a8_neon_dp") +@@ -297,7 +297,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and + ;; produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_mla_qqq_8_16" 7 ++(define_insn_reservation "cortex_a8_neon_mla_qqq_8_16" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_qqq_8_16")) + "cortex_a8_neon_dp_2") +@@ -305,7 +305,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 ++(define_insn_reservation "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) + "cortex_a8_neon_dp_2") +@@ -313,21 +313,21 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6 on cycle 4. +-(define_insn_reservation "neon_mla_qqq_32_qqd_32_scalar" 9 ++(define_insn_reservation "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) + "cortex_a8_neon_dp_4") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N6. +-(define_insn_reservation "neon_mul_ddd_16_scalar_32_16_long_scalar" 6 ++(define_insn_reservation "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. +-(define_insn_reservation "neon_mul_qqd_32_scalar" 9 ++(define_insn_reservation "cortex_a8_neon_mul_qqd_32_scalar" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) + "cortex_a8_neon_dp_4") +@@ -335,84 +335,84 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6. +-(define_insn_reservation "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 ++(define_insn_reservation "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N3. +-(define_insn_reservation "neon_shift_1" 3 ++(define_insn_reservation "cortex_a8_neon_shift_1" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_shift_1")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N4. +-(define_insn_reservation "neon_shift_2" 4 ++(define_insn_reservation "cortex_a8_neon_shift_2" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_shift_2")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N3 on cycle 2. +-(define_insn_reservation "neon_shift_3" 4 ++(define_insn_reservation "cortex_a8_neon_shift_3" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_shift_3")) + "cortex_a8_neon_dp_2") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N1. +-(define_insn_reservation "neon_vshl_ddd" 1 ++(define_insn_reservation "cortex_a8_neon_vshl_ddd" 1 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vshl_ddd")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N4 on cycle 2. +-(define_insn_reservation "neon_vqshl_vrshl_vqrshl_qqq" 5 ++(define_insn_reservation "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) + "cortex_a8_neon_dp_2") + + ;; Instructions using this reservation read their (D|Q)m operands at N1, + ;; their (D|Q)d operands at N3, and produce a result at N6. +-(define_insn_reservation "neon_vsra_vrsra" 6 ++(define_insn_reservation "cortex_a8_neon_vsra_vrsra" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vsra_vrsra")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N5. +-(define_insn_reservation "neon_fp_vadd_ddd_vabs_dd" 5 ++(define_insn_reservation "cortex_a8_neon_fp_vadd_ddd_vabs_dd" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) + "cortex_a8_neon_fadd") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N5 on cycle 2. +-(define_insn_reservation "neon_fp_vadd_qqq_vabs_qq" 6 ++(define_insn_reservation "cortex_a8_neon_fp_vadd_qqq_vabs_qq" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) + "cortex_a8_neon_fadd_2") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N5. +-(define_insn_reservation "neon_fp_vsum" 5 ++(define_insn_reservation "cortex_a8_neon_fp_vsum" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vsum")) + "cortex_a8_neon_fadd") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N5. +-(define_insn_reservation "neon_fp_vmul_ddd" 5 ++(define_insn_reservation "cortex_a8_neon_fp_vmul_ddd" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmul_ddd")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. +-(define_insn_reservation "neon_fp_vmul_qqd" 6 ++(define_insn_reservation "cortex_a8_neon_fp_vmul_qqd" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmul_qqd")) + "cortex_a8_neon_dp_2") +@@ -420,7 +420,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and + ;; produce a result at N9. +-(define_insn_reservation "neon_fp_vmla_ddd" 9 ++(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmla_ddd")) + "cortex_a8_neon_fmul_then_fadd") +@@ -428,7 +428,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and + ;; produce a result at N9 on cycle 2. +-(define_insn_reservation "neon_fp_vmla_qqq" 10 ++(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq" 10 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmla_qqq")) + "cortex_a8_neon_fmul_then_fadd_2") +@@ -436,7 +436,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N9. +-(define_insn_reservation "neon_fp_vmla_ddd_scalar" 9 ++(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd_scalar" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) + "cortex_a8_neon_fmul_then_fadd") +@@ -444,869 +444,869 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N9 on cycle 2. +-(define_insn_reservation "neon_fp_vmla_qqq_scalar" 10 ++(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq_scalar" 10 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) + "cortex_a8_neon_fmul_then_fadd_2") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N9. +-(define_insn_reservation "neon_fp_vrecps_vrsqrts_ddd" 9 ++(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) + "cortex_a8_neon_fmul_then_fadd") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N9 on cycle 2. +-(define_insn_reservation "neon_fp_vrecps_vrsqrts_qqq" 10 ++(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" 10 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) + "cortex_a8_neon_fmul_then_fadd_2") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2. +-(define_insn_reservation "neon_bp_simple" 2 ++(define_insn_reservation "cortex_a8_neon_bp_simple" 2 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_bp_simple")) + "cortex_a8_neon_perm") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2 on cycle 2. +-(define_insn_reservation "neon_bp_2cycle" 3 ++(define_insn_reservation "cortex_a8_neon_bp_2cycle" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_bp_2cycle")) + "cortex_a8_neon_perm_2") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2 on cycle 3. +-(define_insn_reservation "neon_bp_3cycle" 4 ++(define_insn_reservation "cortex_a8_neon_bp_3cycle" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_bp_3cycle")) + "cortex_a8_neon_perm_3") + + ;; Instructions using this reservation produce a result at N1. +-(define_insn_reservation "neon_ldr" 1 ++(define_insn_reservation "cortex_a8_neon_ldr" 1 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_ldr")) + "cortex_a8_neon_ls") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_str" 0 ++(define_insn_reservation "cortex_a8_neon_str" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_str")) + "cortex_a8_neon_ls") + + ;; Instructions using this reservation produce a result at N1 on cycle 2. +-(define_insn_reservation "neon_vld1_1_2_regs" 2 ++(define_insn_reservation "cortex_a8_neon_vld1_1_2_regs" 2 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld1_1_2_regs")) + "cortex_a8_neon_ls_2") + + ;; Instructions using this reservation produce a result at N1 on cycle 3. +-(define_insn_reservation "neon_vld1_3_4_regs" 3 ++(define_insn_reservation "cortex_a8_neon_vld1_3_4_regs" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld1_3_4_regs")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation produce a result at N2 on cycle 2. +-(define_insn_reservation "neon_vld2_2_regs_vld1_vld2_all_lanes" 3 ++(define_insn_reservation "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) + "cortex_a8_neon_ls_2") + + ;; Instructions using this reservation produce a result at N2 on cycle 3. +-(define_insn_reservation "neon_vld2_4_regs" 4 ++(define_insn_reservation "cortex_a8_neon_vld2_4_regs" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld2_4_regs")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation produce a result at N2 on cycle 4. +-(define_insn_reservation "neon_vld3_vld4" 5 ++(define_insn_reservation "cortex_a8_neon_vld3_vld4" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld3_vld4")) + "cortex_a8_neon_ls_4") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst1_1_2_regs_vst2_2_regs" 0 ++(define_insn_reservation "cortex_a8_neon_vst1_1_2_regs_vst2_2_regs" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) + "cortex_a8_neon_ls_2") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst1_3_4_regs" 0 ++(define_insn_reservation "cortex_a8_neon_vst1_3_4_regs" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst1_3_4_regs")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst2_4_regs_vst3_vst4" 0 ++(define_insn_reservation "cortex_a8_neon_vst2_4_regs_vst3_vst4" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) + "cortex_a8_neon_ls_4") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst3_vst4" 0 ++(define_insn_reservation "cortex_a8_neon_vst3_vst4" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst3_vst4")) + "cortex_a8_neon_ls_4") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2 on cycle 3. +-(define_insn_reservation "neon_vld1_vld2_lane" 4 ++(define_insn_reservation "cortex_a8_neon_vld1_vld2_lane" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld1_vld2_lane")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2 on cycle 5. +-(define_insn_reservation "neon_vld3_vld4_lane" 6 ++(define_insn_reservation "cortex_a8_neon_vld3_vld4_lane" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld3_vld4_lane")) + "cortex_a8_neon_ls_5") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst1_vst2_lane" 0 ++(define_insn_reservation "cortex_a8_neon_vst1_vst2_lane" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst1_vst2_lane")) + "cortex_a8_neon_ls_2") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst3_vst4_lane" 0 ++(define_insn_reservation "cortex_a8_neon_vst3_vst4_lane" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst3_vst4_lane")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation produce a result at N2 on cycle 2. +-(define_insn_reservation "neon_vld3_vld4_all_lanes" 3 ++(define_insn_reservation "cortex_a8_neon_vld3_vld4_all_lanes" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation produce a result at N2. +-(define_insn_reservation "neon_mcr" 2 ++(define_insn_reservation "cortex_a8_neon_mcr" 2 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mcr")) + "cortex_a8_neon_perm") + + ;; Instructions using this reservation produce a result at N2. +-(define_insn_reservation "neon_mcr_2_mcrr" 2 ++(define_insn_reservation "cortex_a8_neon_mcr_2_mcrr" 2 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mcr_2_mcrr")) + "cortex_a8_neon_perm_2") + + ;; Exceptions to the default latencies. + +-(define_bypass 1 "neon_mcr_2_mcrr" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 1 "neon_mcr" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_vld3_vld4_all_lanes" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_vld3_vld4_lane" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_vld1_vld2_lane" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_vld3_vld4" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_vld2_4_regs" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_vld2_2_regs_vld1_vld2_all_lanes" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_vld1_3_4_regs" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 1 "neon_vld1_1_2_regs" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 0 "neon_ldr" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_bp_3cycle" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_bp_2cycle" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 1 "neon_bp_simple" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 9 "neon_fp_vrecps_vrsqrts_qqq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_fp_vrecps_vrsqrts_ddd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 9 "neon_fp_vmla_qqq_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_fp_vmla_ddd_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 9 "neon_fp_vmla_qqq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_fp_vmla_ddd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_fp_vmul_qqd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_fp_vmul_ddd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_fp_vsum" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_fp_vadd_qqq_vabs_qq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_fp_vadd_ddd_vabs_dd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_vsra_vrsra" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_vqshl_vrshl_vqrshl_qqq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 0 "neon_vshl_ddd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_shift_3" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_shift_2" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_shift_1" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_mul_qqd_32_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_mul_ddd_16_scalar_32_16_long_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_mla_qqq_32_qqd_32_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_mla_qqq_8_16" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_mul_qqq_8_16_32_ddd_32" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_vsma" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_vaba_qqq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_vaba" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_vmov" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_vqneg_vqabs" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_int_5" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_int_4" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_int_3" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_int_2" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_int_1" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") ++(define_bypass 1 "cortex_a8_neon_mcr_2_mcrr" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a8_neon_mcr" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_vld3_vld4_all_lanes" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_vld3_vld4_lane" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_vld1_vld2_lane" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_vld3_vld4" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_vld2_4_regs" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_vld1_3_4_regs" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a8_neon_vld1_1_2_regs" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 0 "cortex_a8_neon_ldr" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_bp_3cycle" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_bp_2cycle" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a8_neon_bp_simple" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_fp_vmul_qqd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_fp_vmul_ddd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_fp_vsum" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_fp_vadd_qqq_vabs_qq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_fp_vadd_ddd_vabs_dd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_vsra_vrsra" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 0 "cortex_a8_neon_vshl_ddd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_shift_3" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_shift_2" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_shift_1" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_mul_qqd_32_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_mla_qqq_8_16" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_vsma" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_vaba_qqq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_vaba" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_vmov" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_vqneg_vqabs" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_int_5" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_int_4" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_int_3" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_int_2" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_int_1" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") + + +=== added file 'gcc/config/arm/cortex-a9-neon.md' +--- old/gcc/config/arm/cortex-a9-neon.md 1970-01-01 00:00:00 +0000 ++++ new/gcc/config/arm/cortex-a9-neon.md 2010-09-16 09:47:44 +0000 +@@ -0,0 +1,1237 @@ ++;; ARM Cortex-A9 pipeline description ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; ++;; Neon pipeline description contributed by ARM Ltd. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++ ++(define_automaton "cortex_a9_neon") ++ ++;; Only one instruction can be issued per cycle. ++(define_cpu_unit "cortex_a9_neon_issue_perm" "cortex_a9_neon") ++ ++;; Only one data-processing instruction can be issued per cycle. ++(define_cpu_unit "cortex_a9_neon_issue_dp" "cortex_a9_neon") ++ ++;; We need a special mutual exclusion (to be used in addition to ++;; cortex_a9_neon_issue_dp) for the case when an instruction such as ++;; vmla.f is forwarded from E5 of the floating-point multiply pipeline to ++;; E2 of the floating-point add pipeline. On the cycle previous to that ++;; forward we must prevent issue of any instruction to the floating-point ++;; add pipeline, but still allow issue of a data-processing instruction ++;; to any of the other pipelines. ++(define_cpu_unit "cortex_a9_neon_issue_fadd" "cortex_a9_neon") ++(define_cpu_unit "cortex_a9_neon_mcr" "cortex_a9_neon") ++ ++ ++;; Patterns of reservation. ++;; We model the NEON issue units as running in parallel with the core ones. ++;; We assume that multi-cycle NEON instructions get decomposed into ++;; micro-ops as they are issued into the NEON pipeline. ++ ++(define_reservation "cortex_a9_neon_dp" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp") ++(define_reservation "cortex_a9_neon_dp_2" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ cortex_a9_neon_issue_dp") ++(define_reservation "cortex_a9_neon_dp_4" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp") ++ ++(define_reservation "cortex_a9_neon_fadd" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp + \ ++ cortex_a9_neon_issue_fadd") ++(define_reservation "cortex_a9_neon_fadd_2" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ cortex_a9_neon_issue_fadd,\ ++ cortex_a9_neon_issue_dp") ++ ++(define_reservation "cortex_a9_neon_perm" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_perm_2" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm, \ ++ cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_perm_3" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++ ++(define_reservation "cortex_a9_neon_ls" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm+cortex_a9_ls") ++(define_reservation "cortex_a9_neon_ls_2" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_ls_3" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_ls_4" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_ls_5" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++ ++(define_reservation "cortex_a9_neon_fmul_then_fadd" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ nothing*3,\ ++ cortex_a9_neon_issue_fadd") ++(define_reservation "cortex_a9_neon_fmul_then_fadd_2" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ cortex_a9_neon_issue_dp,\ ++ nothing*2,\ ++ cortex_a9_neon_issue_fadd,\ ++ cortex_a9_neon_issue_fadd") ++ ++ ++;; NEON -> core transfers. ++(define_insn_reservation "ca9_neon_mrc" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mrc")) ++ "ca9_issue_vfp_neon + cortex_a9_neon_mcr") ++ ++(define_insn_reservation "ca9_neon_mrrc" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mrrc")) ++ "ca9_issue_vfp_neon + cortex_a9_neon_mcr") ++ ++;; The remainder of this file is auto-generated by neon-schedgen. ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_int_1" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_1")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)m operands at N1, ++;; their (D|Q)n operands at N2, and produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_int_2" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_2")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_int_3" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_3")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N4. ++(define_insn_reservation "cortex_a9_neon_int_4" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_4")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)m operands at N1, ++;; their (D|Q)n operands at N2, and produce a result at N4. ++(define_insn_reservation "cortex_a9_neon_int_5" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_5")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N4. ++(define_insn_reservation "cortex_a9_neon_vqneg_vqabs" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vqneg_vqabs")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_vmov" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vmov")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_vaba" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vaba")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vaba_qqq" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vaba_qqq")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)m operands at N1, ++;; their (D|Q)d operands at N3, and produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_vsma" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vsma")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and ++;; produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and ++;; produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_mla_qqq_8_16" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_qqq_8_16")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6 on cycle 4. ++(define_insn_reservation "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) ++ "cortex_a9_neon_dp_4") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. ++(define_insn_reservation "cortex_a9_neon_mul_qqd_32_scalar" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) ++ "cortex_a9_neon_dp_4") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_shift_1" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_shift_1")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N4. ++(define_insn_reservation "cortex_a9_neon_shift_2" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_shift_2")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N3 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_shift_3" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_shift_3")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N1. ++(define_insn_reservation "cortex_a9_neon_vshl_ddd" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vshl_ddd")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N4 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)m operands at N1, ++;; their (D|Q)d operands at N3, and produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_vsra_vrsra" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vsra_vrsra")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N5. ++(define_insn_reservation "cortex_a9_neon_fp_vadd_ddd_vabs_dd" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) ++ "cortex_a9_neon_fadd") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N5 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vadd_qqq_vabs_qq" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) ++ "cortex_a9_neon_fadd_2") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N5. ++(define_insn_reservation "cortex_a9_neon_fp_vsum" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vsum")) ++ "cortex_a9_neon_fadd") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N5. ++(define_insn_reservation "cortex_a9_neon_fp_vmul_ddd" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmul_ddd")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vmul_qqd" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmul_qqd")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and ++;; produce a result at N9. ++(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmla_ddd")) ++ "cortex_a9_neon_fmul_then_fadd") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and ++;; produce a result at N9 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq" 10 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmla_qqq")) ++ "cortex_a9_neon_fmul_then_fadd_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N9. ++(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd_scalar" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) ++ "cortex_a9_neon_fmul_then_fadd") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N9 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq_scalar" 10 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) ++ "cortex_a9_neon_fmul_then_fadd_2") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N9. ++(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) ++ "cortex_a9_neon_fmul_then_fadd") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N9 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" 10 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) ++ "cortex_a9_neon_fmul_then_fadd_2") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2. ++(define_insn_reservation "cortex_a9_neon_bp_simple" 2 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_bp_simple")) ++ "cortex_a9_neon_perm") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_bp_2cycle" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_bp_2cycle")) ++ "cortex_a9_neon_perm_2") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2 on cycle 3. ++(define_insn_reservation "cortex_a9_neon_bp_3cycle" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_bp_3cycle")) ++ "cortex_a9_neon_perm_3") ++ ++;; Instructions using this reservation produce a result at N1. ++(define_insn_reservation "cortex_a9_neon_ldr" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_ldr")) ++ "cortex_a9_neon_ls") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_str" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_str")) ++ "cortex_a9_neon_ls") ++ ++;; Instructions using this reservation produce a result at N1 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vld1_1_2_regs" 2 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld1_1_2_regs")) ++ "cortex_a9_neon_ls_2") ++ ++;; Instructions using this reservation produce a result at N1 on cycle 3. ++(define_insn_reservation "cortex_a9_neon_vld1_3_4_regs" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld1_3_4_regs")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation produce a result at N2 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) ++ "cortex_a9_neon_ls_2") ++ ++;; Instructions using this reservation produce a result at N2 on cycle 3. ++(define_insn_reservation "cortex_a9_neon_vld2_4_regs" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld2_4_regs")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation produce a result at N2 on cycle 4. ++(define_insn_reservation "cortex_a9_neon_vld3_vld4" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld3_vld4")) ++ "cortex_a9_neon_ls_4") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst1_1_2_regs_vst2_2_regs" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) ++ "cortex_a9_neon_ls_2") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst1_3_4_regs" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst1_3_4_regs")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst2_4_regs_vst3_vst4" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) ++ "cortex_a9_neon_ls_4") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst3_vst4" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst3_vst4")) ++ "cortex_a9_neon_ls_4") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2 on cycle 3. ++(define_insn_reservation "cortex_a9_neon_vld1_vld2_lane" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld1_vld2_lane")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2 on cycle 5. ++(define_insn_reservation "cortex_a9_neon_vld3_vld4_lane" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld3_vld4_lane")) ++ "cortex_a9_neon_ls_5") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst1_vst2_lane" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst1_vst2_lane")) ++ "cortex_a9_neon_ls_2") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst3_vst4_lane" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst3_vst4_lane")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation produce a result at N2 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vld3_vld4_all_lanes" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation produce a result at N2. ++(define_insn_reservation "cortex_a9_neon_mcr" 2 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mcr")) ++ "cortex_a9_neon_perm") ++ ++;; Instructions using this reservation produce a result at N2. ++(define_insn_reservation "cortex_a9_neon_mcr_2_mcrr" 2 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mcr_2_mcrr")) ++ "cortex_a9_neon_perm_2") ++ ++;; Exceptions to the default latencies. ++ ++(define_bypass 1 "cortex_a9_neon_mcr_2_mcrr" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a9_neon_mcr" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_vld3_vld4_all_lanes" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_vld3_vld4_lane" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_vld1_vld2_lane" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_vld3_vld4" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_vld2_4_regs" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_vld1_3_4_regs" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a9_neon_vld1_1_2_regs" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 0 "cortex_a9_neon_ldr" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_bp_3cycle" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_bp_2cycle" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a9_neon_bp_simple" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_fp_vmul_qqd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_fp_vmul_ddd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_fp_vsum" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_fp_vadd_qqq_vabs_qq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_fp_vadd_ddd_vabs_dd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_vsra_vrsra" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 0 "cortex_a9_neon_vshl_ddd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_shift_3" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_shift_2" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_shift_1" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_mul_qqd_32_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_mla_qqq_8_16" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_vsma" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_vaba_qqq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_vaba" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_vmov" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_vqneg_vqabs" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_int_5" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_int_4" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_int_3" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_int_2" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_int_1" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ + +=== modified file 'gcc/config/arm/cortex-a9.md' +--- old/gcc/config/arm/cortex-a9.md 2010-08-24 13:15:54 +0000 ++++ new/gcc/config/arm/cortex-a9.md 2010-09-16 09:47:44 +0000 +@@ -80,8 +80,9 @@ + (define_insn_reservation "cortex_a9_dp" 2 + (and (eq_attr "tune" "cortexa9") + (ior (eq_attr "type" "alu") +- (and (eq_attr "type" "alu_shift_reg, alu_shift") +- (eq_attr "insn" "mov")))) ++ (ior (and (eq_attr "type" "alu_shift_reg, alu_shift") ++ (eq_attr "insn" "mov")) ++ (eq_attr "neon_type" "none")))) + "cortex_a9_p0_default|cortex_a9_p1_default") + + ;; An instruction using the shifter will go down E1. + +=== modified file 'gcc/config/arm/neon-schedgen.ml' +--- old/gcc/config/arm/neon-schedgen.ml 2010-04-02 18:54:46 +0000 ++++ new/gcc/config/arm/neon-schedgen.ml 2010-09-16 09:47:44 +0000 +@@ -1,7 +1,6 @@ + (* Emission of the core of the Cortex-A8 NEON scheduling description. + Copyright (C) 2007, 2010 Free Software Foundation, Inc. + Contributed by CodeSourcery. +- + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under +@@ -21,7 +20,14 @@ + + (* This scheduling description generator works as follows. + - Each group of instructions has source and destination requirements +- specified. The source requirements may be specified using ++ specified and a list of cores supported. This is then filtered ++ and per core scheduler descriptions are generated out. ++ The reservations generated are prefixed by the name of the ++ core and the check is performed on the basis of what the tuning ++ string is. Running this will generate Neon scheduler descriptions ++ for all cores supported. ++ ++ The source requirements may be specified using + Source (the stage at which all source operands not otherwise + described are read), Source_m (the stage at which Rm operands are + read), Source_n (likewise for Rn) and Source_d (likewise for Rd). +@@ -83,6 +89,17 @@ + | Ls of int + | Fmul_then_fadd | Fmul_then_fadd_2 + ++type core = CortexA8 | CortexA9 ++let allCores = [CortexA8; CortexA9] ++let coreStr = function ++ CortexA8 -> "cortex_a8" ++ | CortexA9 -> "cortex_a9" ++ ++let tuneStr = function ++ CortexA8 -> "cortexa8" ++ | CortexA9 -> "cortexa9" ++ ++ + (* This table must be kept as short as possible by conflating + entries with the same availability behavior. + +@@ -90,129 +107,136 @@ + Second components: availability requirements, in the order in which + they should appear in the comments in the .md file. + Third components: reservation info ++ Fourth components: List of supported cores. + *) + let availability_table = [ + (* NEON integer ALU instructions. *) + (* vbit vbif vbsl vorr vbic vnot vcls vclz vcnt vadd vand vorr + veor vbic vorn ddd qqq *) +- "neon_int_1", [Source n2; Dest n3], ALU; ++ "neon_int_1", [Source n2; Dest n3], ALU, allCores; + (* vadd vsub qqd vsub ddd qqq *) +- "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU; ++ "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU, allCores; + (* vsum vneg dd qq vadd vsub qdd *) +- "neon_int_3", [Source n1; Dest n3], ALU; ++ "neon_int_3", [Source n1; Dest n3], ALU, allCores; + (* vabs vceqz vcgez vcbtz vclez vcltz vadh vradh vsbh vrsbh dqq *) + (* vhadd vrhadd vqadd vtst ddd qqq *) +- "neon_int_4", [Source n2; Dest n4], ALU; ++ "neon_int_4", [Source n2; Dest n4], ALU, allCores; + (* vabd qdd vhsub vqsub vabd vceq vcge vcgt vmax vmin vfmx vfmn ddd ddd *) +- "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU; ++ "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU, allCores; + (* vqneg vqabs dd qq *) +- "neon_vqneg_vqabs", [Source n1; Dest n4], ALU; ++ "neon_vqneg_vqabs", [Source n1; Dest n4], ALU, allCores; + (* vmov vmvn *) +- "neon_vmov", [Dest n3], ALU; ++ "neon_vmov", [Dest n3], ALU, allCores; + (* vaba *) +- "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU; ++ "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU, allCores; + "neon_vaba_qqq", +- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ALU_2cycle; ++ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ++ ALU_2cycle, allCores; + (* vsma *) +- "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU; ++ "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU, allCores; + + (* NEON integer multiply instructions. *) + (* vmul, vqdmlh, vqrdmlh *) + (* vmul, vqdmul, qdd 16/8 long 32/16 long *) +- "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], Mul; +- "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], Mul_2cycle; ++ "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], ++ Mul, allCores; ++ "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], ++ Mul_2cycle, allCores; + (* vmul, vqdmul again *) + "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar", +- [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle; ++ [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle, allCores; + (* vmla, vmls *) + "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long", +- [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul; ++ [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul, allCores; + "neon_mla_qqq_8_16", +- [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle; ++ [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], ++ Mul_2cycle, allCores; + "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long", +- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle; ++ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ++ Mul_2cycle, allCores; + "neon_mla_qqq_32_qqd_32_scalar", +- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], Mul_4cycle; ++ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], ++ Mul_4cycle, allCores; + (* vmul, vqdmulh, vqrdmulh *) + (* vmul, vqdmul *) + "neon_mul_ddd_16_scalar_32_16_long_scalar", +- [Source_n n2; Source_m n1; Dest n6], Mul; ++ [Source_n n2; Source_m n1; Dest n6], Mul, allCores; + "neon_mul_qqd_32_scalar", +- [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle; ++ [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle, allCores; + (* vmla, vmls *) + (* vmla, vmla, vqdmla, vqdmls *) + "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar", +- [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul; ++ [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul, allCores; + + (* NEON integer shift instructions. *) + (* vshr/vshl immediate, vshr_narrow, vshl_vmvh, vsli_vsri_ddd *) +- "neon_shift_1", [Source n1; Dest n3], Shift; +- (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow; ++ "neon_shift_1", [Source n1; Dest n3], Shift, allCores; ++ (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow, allCores; + vqshl_vrshl_vqrshl_ddd *) +- "neon_shift_2", [Source n1; Dest n4], Shift; ++ "neon_shift_2", [Source n1; Dest n4], Shift, allCores; + (* vsli, vsri and vshl for qqq *) +- "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle; +- "neon_vshl_ddd", [Source n1; Dest n1], Shift; ++ "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle, allCores; ++ "neon_vshl_ddd", [Source n1; Dest n1], Shift, allCores; + "neon_vqshl_vrshl_vqrshl_qqq", [Source n1; Dest_n_after (1, n4)], +- Shift_2cycle; +- "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift; ++ Shift_2cycle, allCores; ++ "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift, allCores; + + (* NEON floating-point instructions. *) + (* vadd, vsub, vabd, vmul, vceq, vcge, vcgt, vcage, vcagt, vmax, vmin *) + (* vabs, vneg, vceqz, vcgez, vcgtz, vclez, vcltz, vrecpe, vrsqrte, vcvt *) +- "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd; ++ "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd, allCores; + "neon_fp_vadd_qqq_vabs_qq", [Source n2; Dest_n_after (1, n5)], +- Fadd_2cycle; ++ Fadd_2cycle, allCores; + (* vsum, fvmx, vfmn *) +- "neon_fp_vsum", [Source n1; Dest n5], Fadd; +- "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul; ++ "neon_fp_vsum", [Source n1; Dest n5], Fadd, allCores; ++ "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul, allCores; + "neon_fp_vmul_qqd", [Source_n n2; Source_m n1; Dest_n_after (1, n5)], +- Fmul_2cycle; ++ Fmul_2cycle, allCores; + (* vmla, vmls *) + "neon_fp_vmla_ddd", +- [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd; ++ [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd, allCores; + "neon_fp_vmla_qqq", + [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n9)], +- Fmul_then_fadd_2; ++ Fmul_then_fadd_2, allCores; + "neon_fp_vmla_ddd_scalar", +- [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd; ++ [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd, allCores; + "neon_fp_vmla_qqq_scalar", + [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n9)], +- Fmul_then_fadd_2; +- "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd; ++ Fmul_then_fadd_2, allCores; ++ "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd, allCores; + "neon_fp_vrecps_vrsqrts_qqq", [Source n2; Dest_n_after (1, n9)], +- Fmul_then_fadd_2; ++ Fmul_then_fadd_2, allCores; + + (* NEON byte permute instructions. *) + (* vmov; vtrn and vswp for dd; vzip for dd; vuzp for dd; vrev; vext for dd *) +- "neon_bp_simple", [Source n1; Dest n2], Permute 1; +- (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}; ++ "neon_bp_simple", [Source n1; Dest n2], Permute 1, allCores; ++ (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}, allCores; + similarly for vtbx *) +- "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2; ++ "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2, allCores; + (* all the rest *) +- "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3; ++ "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3, allCores; + + (* NEON load/store instructions. *) +- "neon_ldr", [Dest n1], Ls 1; +- "neon_str", [Source n1], Ls 1; +- "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2; +- "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3; +- "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2; +- "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3; +- "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4; +- "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2; +- "neon_vst1_3_4_regs", [Source n1], Ls 3; +- "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4; +- "neon_vst3_vst4", [Source n1], Ls 4; +- "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3; +- "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5; +- "neon_vst1_vst2_lane", [Source n1], Ls 2; +- "neon_vst3_vst4_lane", [Source n1], Ls 3; +- "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3; ++ "neon_ldr", [Dest n1], Ls 1, allCores; ++ "neon_str", [Source n1], Ls 1, allCores; ++ "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2, allCores; ++ "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3, allCores; ++ "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2, allCores; ++ "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3, allCores; ++ "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4, allCores; ++ "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2, allCores; ++ "neon_vst1_3_4_regs", [Source n1], Ls 3, allCores; ++ "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4, allCores; ++ "neon_vst3_vst4", [Source n1], Ls 4, allCores; ++ "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3, allCores; ++ "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5, allCores; ++ "neon_vst1_vst2_lane", [Source n1], Ls 2, allCores; ++ "neon_vst3_vst4_lane", [Source n1], Ls 3, allCores; ++ "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3, allCores; + + (* NEON register transfer instructions. *) +- "neon_mcr", [Dest n2], Permute 1; +- "neon_mcr_2_mcrr", [Dest n2], Permute 2; ++ "neon_mcr", [Dest n2], Permute 1, allCores; ++ "neon_mcr_2_mcrr", [Dest n2], Permute 2, allCores; + (* MRC instructions are in the .tpl file. *) + ] + +@@ -221,7 +245,7 @@ + required. (It is also possible that an entry in the table has no + source requirements.) *) + let calculate_sources = +- List.map (fun (name, avail, res) -> ++ List.map (fun (name, avail, res, cores) -> + let earliest_stage = + List.fold_left + (fun cur -> fun info -> +@@ -331,7 +355,7 @@ + of one bypass from this producer to any particular consumer listed + in LATENCIES.) Use a hash table to collate bypasses with the + same latency and guard. *) +-let collate_bypasses (producer_name, _, _, _) largest latencies = ++let collate_bypasses (producer_name, _, _, _) largest latencies core = + let ht = Hashtbl.create 42 in + let keys = ref [] in + List.iter ( +@@ -350,7 +374,7 @@ + (if (try ignore (Hashtbl.find ht (guard, latency)); false + with Not_found -> true) then + keys := (guard, latency) :: !keys); +- Hashtbl.add ht (guard, latency) consumer ++ Hashtbl.add ht (guard, latency) ((coreStr core) ^ "_" ^ consumer) + end + ) latencies; + (* The hash table now has bypasses collated so that ones with the +@@ -372,7 +396,7 @@ + the output in such a way that all bypasses with the same producer + and latency are together, and so that bypasses with the worst-case + latency are ignored. *) +-let worst_case_latencies_and_bypasses = ++let worst_case_latencies_and_bypasses core = + let rec f (worst_acc, bypasses_acc) prev xs = + match xs with + [] -> (worst_acc, bypasses_acc) +@@ -400,7 +424,7 @@ + (* Having got the largest latency, collect all bypasses for + this producer and filter out those with that larger + latency. Record the others for later emission. *) +- let bypasses = collate_bypasses producer largest latencies in ++ let bypasses = collate_bypasses producer largest latencies core in + (* Go on to process remaining producers, having noted + the result for this one. *) + f ((producer_name, producer_avail, largest, +@@ -444,14 +468,18 @@ + in + f avail 0 + ++ + (* Emit a define_insn_reservation for each producer. The latency + written in will be its worst-case latency. *) +-let emit_insn_reservations = +- List.iter ( ++let emit_insn_reservations core = ++ let corestring = coreStr core in ++ let tunestring = tuneStr core ++ in List.iter ( + fun (producer, avail, latency, reservation) -> + write_comment producer avail; +- Printf.printf "(define_insn_reservation \"%s\" %d\n" producer latency; +- Printf.printf " (and (eq_attr \"tune\" \"cortexa8\")\n"; ++ Printf.printf "(define_insn_reservation \"%s_%s\" %d\n" ++ corestring producer latency; ++ Printf.printf " (and (eq_attr \"tune\" \"%s\")\n" tunestring; + Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer; + let str = + match reservation with +@@ -467,7 +495,7 @@ + | Fmul_then_fadd -> "fmul_then_fadd" + | Fmul_then_fadd_2 -> "fmul_then_fadd_2" + in +- Printf.printf " \"cortex_a8_neon_%s\")\n\n" str ++ Printf.printf " \"%s_neon_%s\")\n\n" corestring str + ) + + (* Given a guard description, return the name of the C function to +@@ -480,10 +508,12 @@ + | Guard_none -> assert false + + (* Emit a define_bypass for each bypass. *) +-let emit_bypasses = ++let emit_bypasses core = + List.iter ( + fun (producer, consumers, latency, guard) -> +- Printf.printf "(define_bypass %d \"%s\"\n" latency producer; ++ Printf.printf "(define_bypass %d \"%s_%s\"\n" ++ latency (coreStr core) producer; ++ + if guard = Guard_none then + Printf.printf " \"%s\")\n\n" consumers + else +@@ -493,11 +523,21 @@ + end + ) + ++ ++let calculate_per_core_availability_table core availability_table = ++ let table = calculate_sources availability_table in ++ let worst_cases, bypasses = worst_case_latencies_and_bypasses core table in ++ emit_insn_reservations core (List.rev worst_cases); ++ Printf.printf ";; Exceptions to the default latencies.\n\n"; ++ emit_bypasses core bypasses ++ ++let calculate_core_availability_table core availability_table = ++let filter_core = List.filter (fun (_, _, _, cores) ++ -> List.exists ((=) core) cores) ++in calculate_per_core_availability_table core (filter_core availability_table) ++ ++ + (* Program entry point. *) + let main = +- let table = calculate_sources availability_table in +- let worst_cases, bypasses = worst_case_latencies_and_bypasses table in +- emit_insn_reservations (List.rev worst_cases); +- Printf.printf ";; Exceptions to the default latencies.\n\n"; +- emit_bypasses bypasses +- ++ List.map (fun core -> calculate_core_availability_table ++ core availability_table) allCores + diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch new file mode 100644 index 0000000000..c332d50fa1 --- /dev/null +++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch @@ -0,0 +1,76 @@ +2010-09-21 Yao Qi + + Backport from FSF to fix ICE found in LP:635409: + + 2010-07-07 Bernd Schmidt + + gcc/ + PR rtl-optimization/44787 + * config/arm/arm.md (arith_shiftsi): Allow stack pointer in operand 2. + * config/arm/thumb2.md (thumb2_arith_shiftsi): Likewise. + + gcc/testsuite/ + PR rtl-optimization/44787 + * gcc.c-torture/compile/pr44788.c: New test. + * gcc.target/arm/pr44788.c: New test. + + 2010-09-16 Andrew Stubbs + + Backport from FSF: + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2010-09-16 09:15:46 +0000 ++++ new/gcc/config/arm/arm.md 2010-09-22 05:54:42 +0000 +@@ -9268,7 +9268,7 @@ + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "reg_or_int_operand" "rI")]) +- (match_operand:SI 2 "s_register_operand" "r")]))] ++ (match_operand:SI 2 "s_register_operand" "rk")]))] + "TARGET_ARM" + "%i1%?\\t%0, %2, %4%S3" + [(set_attr "predicable" "yes") + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2010-09-01 13:29:58 +0000 ++++ new/gcc/config/arm/thumb2.md 2010-09-22 05:54:42 +0000 +@@ -467,7 +467,7 @@ + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "const_shift_count" "M")]) +- (match_operand:SI 2 "s_register_operand" "r")]))] ++ (match_operand:SI 2 "s_register_operand" "rk")]))] + "TARGET_THUMB2" + "%i1%?\\t%0, %2, %4%S3" + [(set_attr "predicable" "yes") + +=== added file 'gcc/testsuite/gcc.c-torture/compile/pr44788.c' +--- old/gcc/testsuite/gcc.c-torture/compile/pr44788.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.c-torture/compile/pr44788.c 2010-09-22 05:54:42 +0000 +@@ -0,0 +1,8 @@ ++void joint_decode(float* mlt_buffer1, int t) { ++ int i; ++ float decode_buffer[1060]; ++ foo(decode_buffer); ++ for (i=0; i<10 ; i++) { ++ mlt_buffer1[i] = i * decode_buffer[t]; ++ } ++} + +=== added file 'gcc/testsuite/gcc.target/arm/pr44788.c' +--- old/gcc/testsuite/gcc.target/arm/pr44788.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr44788.c 2010-09-22 05:54:42 +0000 +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_thumb2_ok } */ ++/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */ ++ ++void joint_decode(float* mlt_buffer1, int t) { ++ int i; ++ float decode_buffer[1060]; ++ foo(decode_buffer); ++ for (i=0; i<10 ; i++) { ++ mlt_buffer1[i] = i * decode_buffer[t]; ++ } ++} + -- cgit 1.2.3-korg