MaverickCrunch FPUs only exist in silicon with an arm920t core and Cirrus have stopped development of their ARM processors (1 April 2008, no joke!) This means Maverick-Thumb2 combinations will never exist in hardware, so remove all existing Maverick+Thumb2 descriptions. Martin Guy November 2008 --- gcc-4.3.2/gcc/config/arm/cirrus.md.old 2008-11-18 12:09:40.000000000 +0000 +++ gcc-4.3.2/gcc/config/arm/cirrus.md 2008-11-18 12:12:38.000000000 +0000 @@ -452,87 +452,3 @@ (set_attr "neg_pool_range" " *, *, *, *, 1008, *, 1008, *, *, *") (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] ) - -(define_insn "*cirrus_thumb2_movdi" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") - (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK" - "* - { - switch (which_alternative) - { - case 0: - case 1: - case 2: - return (output_move_double (operands)); - - case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\"; - case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\"; - - case 5: return \"cfldr64%?\\t%V0, %1\"; - case 6: return \"cfstr64%?\\t%V1, %0\"; - - /* Shifting by 0 will just copy %1 into %0. */ - case 7: return \"cfsh64%?\\t%V0, %V1, #0\"; - - default: abort (); - } - }" - [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4") - (set_attr "type" " *,load2,store2, *, *, load2,store2, *") - (set_attr "pool_range" " *,4096, *, *, *, 1020, *, *") - (set_attr "neg_pool_range" " *, 0, *, *, *, 1008, *, *") - (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")] -) - -(define_insn "*thumb2_cirrus_movsf_hard_insn" - [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") - (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] - "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK - && (GET_CODE (operands[0]) != MEM - || register_operand (operands[1], SFmode))" - "@ - cfcpys%?\\t%V0, %V1 - cfldrs%?\\t%V0, %1 - cfmvsr%?\\t%V0, %1 - cfmvrs%?\\t%0, %V1 - cfstrs%?\\t%V1, %0 - mov%?\\t%0, %1 - ldr%?\\t%0, %1\\t%@ float - str%?\\t%1, %0\\t%@ float" - [(set_attr "length" " *, *, *, *, *, 4, 4, 4") - (set_attr "type" " *, load1, *, *,store1, *,load1,store1") - (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") - (set_attr "neg_pool_range" " *, 1008, *, *, *, *, 0, *") - (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] -) - -(define_insn "*thumb2_cirrus_movdf_hard_insn" - [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") - (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] - "TARGET_THUMB2 - && TARGET_HARD_FLOAT && TARGET_MAVERICK - && (GET_CODE (operands[0]) != MEM - || register_operand (operands[1], DFmode))" - "* - { - switch (which_alternative) - { - case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\"; - case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; - case 2: case 3: case 4: return output_move_double (operands); - case 5: return \"cfcpyd%?\\t%V0, %V1\"; - case 6: return \"cfldrd%?\\t%V0, %1\"; - case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; - case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; - case 9: return \"cfstrd%?\\t%V1, %0\"; - default: abort (); - } - }" - [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2") - (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") - (set_attr "pool_range" " *, *, *, *,4092, *, 1020, *, *, *") - (set_attr "neg_pool_range" " *, *, *, *, 0, *, 1008, *, *, *") - (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] -) -