diff options
| -rw-r--r-- | meta-oe/recipes-bsp/flashrom/flashrom/0001-hwaccess-use-__asm__-as-is-done-elsewhere.patch | 52 | ||||
| -rw-r--r-- | meta-oe/recipes-bsp/flashrom/flashrom_1.2.bb | 1 |
2 files changed, 53 insertions, 0 deletions
diff --git a/meta-oe/recipes-bsp/flashrom/flashrom/0001-hwaccess-use-__asm__-as-is-done-elsewhere.patch b/meta-oe/recipes-bsp/flashrom/flashrom/0001-hwaccess-use-__asm__-as-is-done-elsewhere.patch new file mode 100644 index 0000000000..f3316aa264 --- /dev/null +++ b/meta-oe/recipes-bsp/flashrom/flashrom/0001-hwaccess-use-__asm__-as-is-done-elsewhere.patch @@ -0,0 +1,52 @@ +From 3334dd4e9fc34c79c3925c3c24869939d8955f21 Mon Sep 17 00:00:00 2001 +From: Rosen Penev <rosenp@gmail.com> +Date: Sat, 18 Jul 2020 12:16:00 -0700 +Subject: [PATCH] hwaccess: use __asm__ as is done elsewhere + +Fixes compilation under powerpc platform. Made the change for the SPARC +platform as well. + +../hwaccess.c: In function 'sync_primitive': +../hwaccess.c:74:2: warning: implicit declaration of function 'asm' + [-Wimplicit-function-declaration] + 74 | asm("eieio" : : : "memory"); + | ^~~ +../hwaccess.c:74:13: error: expected ')' before ':' token + 74 | asm("eieio" : : : "memory"); + +Upstream-Status: Submitted [https://github.com/flashrom/flashrom/pull/155] +Signed-off-by: Rosen Penev <rosenp@gmail.com> +Signed-off-by: Khem Raj <raj.khem@gmail.com> +--- + hwaccess.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/hwaccess.c b/hwaccess.c +index 48ccb34..2a39989 100644 +--- a/hwaccess.c ++++ b/hwaccess.c +@@ -71,18 +71,18 @@ static inline void sync_primitive(void) + * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/memory-barriers.txt + */ + #if IS_PPC // cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h +- asm("eieio" : : : "memory"); ++ __asm__ ("eieio" : : : "memory"); + #elif IS_SPARC + #if defined(__sparc_v9__) || defined(__sparcv9) + /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like + * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we + * use the strongest hardware memory barriers that exist on Sparc V9. */ +- asm volatile ("membar #Sync" ::: "memory"); ++ __asm__ volatile ("membar #Sync" ::: "memory"); + #elif defined(__sparc_v8__) || defined(__sparcv8) + /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run + * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable + * operation in the V8 instruction set anyway. If you know better then please tell us. */ +- asm volatile ("stbar"); ++ __asm__ volatile ("stbar"); + #else + #error Unknown and/or unsupported SPARC instruction set version detected. + #endif +-- +2.32.0 + diff --git a/meta-oe/recipes-bsp/flashrom/flashrom_1.2.bb b/meta-oe/recipes-bsp/flashrom/flashrom_1.2.bb index 145a3cad02..1d06132144 100644 --- a/meta-oe/recipes-bsp/flashrom/flashrom_1.2.bb +++ b/meta-oe/recipes-bsp/flashrom/flashrom_1.2.bb @@ -7,6 +7,7 @@ SRC_URI = "https://download.flashrom.org/releases/flashrom-v${PV}.tar.bz2 \ file://0001-typecast-enum-conversions-explicitly.patch \ file://meson-fixes.patch \ file://0001-flashrom-Mark-RISCV-as-non-memory-mapped-I-O-archite.patch \ + file://0001-hwaccess-use-__asm__-as-is-done-elsewhere.patch \ " SRC_URI[md5sum] = "7f8e4b87087eb12ecee0fcc5445b4956" SRC_URI[sha256sum] = "e1f8d95881f5a4365dfe58776ce821dfcee0f138f75d0f44f8a3cd032d9ea42b" |