gcc: add support for Neoverse N2 CPU

This patch backports the AArch32 support for Arm's Neoverse N2 CPU.

Upstream-Status: Backport
[https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=d7e8411f6a333d4054894ad3b23f23415a525230]

Signed-off-by: pgowda <pgowda.cve@gmail.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>

2 files changed, 89 insertions, 0 deletions

diff --git a/meta/recipes-devtools/gcc/gcc-10.2.inc b/meta/recipes-devtools/gcc/gcc-10.2.inc
index 656c43258c..e7e3395c55 100644
--- a/meta/recipes-devtools/gcc/gcc-10.2.inc
+++ b/meta/recipes-devtools/gcc/gcc-10.2.inc
@@ -74,6 +74,7 @@ SRC_URI = "\
            file://0002-CVE-2021-35465.patch \
            file://0003-CVE-2021-35465.patch \
            file://0004-CVE-2021-35465.patch \
+           file://0038-arm-neoverse-n2-support.patch \
            file://0039-arm64-neoverse-n2-support.patch \
            file://0001-CVE-2021-42574.patch \
            file://0002-CVE-2021-42574.patch \
diff --git a/meta/recipes-devtools/gcc/gcc/0038-arm-neoverse-n2-support.patch b/meta/recipes-devtools/gcc/gcc/0038-arm-neoverse-n2-support.patch
new file mode 100644
index 0000000000..3e42266b81
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc/0038-arm-neoverse-n2-support.patch
@@ -0,0 +1,88 @@
+From d7e8411f6a333d4054894ad3b23f23415a525230 Mon Sep 17 00:00:00 2001
+From: Alex Coplan <alex.coplan@arm.com>
+Date: Fri, 2 Oct 2020 16:06:15 +0100
+Subject: [PATCH] arm: Add support for Neoverse N2 CPU
+
+This patch backports the AArch32 support for Arm's Neoverse N2 CPU to
+GCC 10.
+
+gcc/ChangeLog:
+
+	* config/arm/arm-cpus.in (neoverse-n2): New.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Regenerate.
+	* doc/invoke.texi: Document support for Neoverse N2.
+
+Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=d7e8411f6a333d4054894ad3b23f23415a525230]
+
+Signed-off-by: pgowda <pgowda.cve@gmail.com>
+---
+ gcc/config/arm/arm-cpus.in    | 12 ++++++++++++
+ gcc/config/arm/arm-tables.opt |  3 +++
+ gcc/config/arm/arm-tune.md    |  5 +++--
+ gcc/doc/invoke.texi           |  6 +++---
+ 4 files changed, 21 insertions(+), 5 deletions(-)
+
+diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
+--- a/gcc/config/arm/arm-cpus.in	2021-12-20 20:24:59.912159845 -0800
++++ b/gcc/config/arm/arm-cpus.in	2021-12-20 21:00:04.417003845 -0800
+@@ -1481,6 +1481,18 @@ begin cpu cortex-a76.cortex-a55
+  costs cortex_a57
+ end cpu cortex-a76.cortex-a55
+ 
++# Armv8.5 A-profile Architecture Processors
++begin cpu neoverse-n2
++  cname neoversen2
++  tune for cortex-a57
++  tune flags LDSCHED
++  architecture armv8.5-a+fp16+bf16+i8mm
++  option crypto add FP_ARMv8 CRYPTO
++  costs cortex_a57
++  vendor 41
++  part 0xd49
++end cpu neoverse-n2
++
+ # V8 M-profile implementations.
+ begin cpu cortex-m23
+  cname cortexm23
+diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
+--- a/gcc/config/arm/arm-tables.opt	2020-07-22 23:35:54.688795958 -0700
++++ b/gcc/config/arm/arm-tables.opt	2021-12-20 21:00:04.421003776 -0800
+@@ -253,6 +253,9 @@ EnumValue
+ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
+ 
+ EnumValue
++Enum(processor_type) String(neoverse-n2) Value( TARGET_CPU_neoversen2)
++
++EnumValue
+ Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
+ 
+ EnumValue
+diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
+--- a/gcc/config/arm/arm-tune.md	2020-07-22 23:35:54.684795913 -0700
++++ b/gcc/config/arm/arm-tune.md	2021-12-20 21:02:44.630260284 -0800
+@@ -46,6 +46,6 @@
+ 	cortexa73cortexa53,cortexa55,cortexa75,
+ 	cortexa76,cortexa76ae,cortexa77,
+ 	neoversen1,cortexa75cortexa55,cortexa76cortexa55,
+-	cortexm23,cortexm33,cortexm35p,
+-	cortexm55,cortexr52"
++	neoversen2,cortexm23,cortexm33,
++	cortexm35p,cortexm55,cortexr52"
+ 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+--- a/gcc/doc/invoke.texi	2021-12-20 20:24:59.916159782 -0800
++++ b/gcc/doc/invoke.texi	2021-12-20 21:03:41.337290704 -0800
+@@ -18857,9 +18857,9 @@ Permissible names are: @samp{arm7tdmi},
+ @samp{cortex-m35p}, @samp{cortex-m55},
+ @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
+ @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
+-@samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2},
+-@samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te},
+-@samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
++@samp{neoverse-n1}, @samp{neoverse-n2}, @samp{xscale}, @samp{iwmmxt},
++@samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te},
++@samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
+ 
+ Additionally, this option can specify that GCC should tune the performance
+ of the code for a big.LITTLE system.  Permissible names are: