merge of '1458e9ca6c6d9b78bff4114c4a3b09c7aa6b7a8e'

and 'df907de16e9f058a9d98b4ee458c93e7c4965a9c'
author: Paul Sokolovsky <pmiscml@gmail.com> 2008-03-11 13:48:44 +0000
committer: Paul Sokolovsky <pmiscml@gmail.com> 2008-03-11 13:48:44 +0000
commit: 7e8dbb134a4c8488fe533b8611528637930e0a02 (patch)
tree: 6408bb8eb701cc38d96deef0090cdbbd831b6c21 /packages
parent: 84c5f5d53e3417913c75df26cf33678efe0a148e (diff)
parent: 6b6cf4dab96836c4c814ffc79a05fc12ff113a62 (diff)
download: openembedded-7e8dbb134a4c8488fe533b8611528637930e0a02.tar.gz
86 files changed, 9818 insertions, 1702 deletions
diff --git a/packages/aircrack/aircrack-ng_0.9.1.bb b/packages/aircrack/aircrack-ng_0.9.1.bb
deleted file mode 100644
index 116ee599e3..0000000000
--- a/packages/aircrack/aircrack-ng_0.9.1.bb
+++ /dev/null
@@ -1,22 +0,0 @@
-DESCRIPTION = "Aircrack-ng is a set of tools for wep key statistical cracking"
-HOMEPAGE = "http://www.aircrack-ng.org/"
-SECTION = "console/network"
-LICENSE = "GPLv2"
-PR = "r2"
-
-SRC_URI = "http://download.aircrack-ng.org/aircrack-ng-${PV}.tar.gz"
-
-do_install() {
-        install -d ${D}/${sbindir}
-	install -d ${D}/${bindir}
-        install -m 0755 airodump-ng       ${D}/${sbindir}
-        install -m 0755 aircrack-ng       ${D}/${bindir}
-        install -m 0755 aireplay-ng       ${D}/${sbindir}
-        install -m 0755 airdecap-ng       ${D}/${bindir}
-        install -m 0755 packetforge-ng    ${D}/${bindir}
-        install -m 0755 airmon-ng         ${D}/${sbindir}
-        install -m 0755 ivstools          ${D}/${bindir}
-	install -m 0755 kstats		  ${D}/${bindir}
-	install -m 0755 airtun-ng	  ${D}/${sbindir}
-	install -m 0755 makeivs 	  ${D}/${bindir}
-}
diff --git a/packages/aircrack/aircrack-ng_0.9.3.bb b/packages/aircrack/aircrack-ng_0.9.3.bb
new file mode 100644
index 0000000000..1452a64bc1
--- /dev/null
+++ b/packages/aircrack/aircrack-ng_0.9.3.bb
@@ -0,0 +1,22 @@
+DESCRIPTION = "Aircrack-ng is a set of tools for wep key statistical cracking"
+HOMEPAGE = "http://www.aircrack-ng.org/"
+SECTION = "console/network"
+LICENSE = "GPLv2"
+PR = "r0"
+
+SRC_URI = "http://download.aircrack-ng.org/aircrack-ng-${PV}.tar.gz"
+
+SBINFILES = "airodump-ng aireplay-ng airmon-ng airtun-ng"
+BINFILES = "aircrack-ng airdecap-ng packetforge-ng ivstools kstats makeivs"
+
+do_install() {
+	install -d ${D}/${sbindir}
+	for i in ${SBINFILES}; do
+		install -m 0755 $i ${D}/${sbindir}
+	done
+
+	install -d ${D}/${bindir}
+	for i in ${BINFILES}; do
+		install -m 0755 $i ${D}/${bindir}
+	done
+}
diff --git a/packages/nano/nano-1.2.1/.mtn2git_empty b/packages/apr/apr-util/.mtn2git_empty
index e69de29bb2..e69de29bb2 100644
--- a/packages/nano/nano-1.2.1/.mtn2git_empty
+++ b/packages/apr/apr-util/.mtn2git_empty
diff --git a/packages/apr/apr-util/configure_fixes.patch b/packages/apr/apr-util/configure_fixes.patch
new file mode 100644
index 0000000000..16f88b3bba
--- /dev/null
+++ b/packages/apr/apr-util/configure_fixes.patch
@@ -0,0 +1,25 @@
+Index: apr-util-1.2.12/configure.in
+===================================================================
+--- apr-util-1.2.12.orig/configure.in	2008-03-08 19:15:00.000000000 +0000
++++ apr-util-1.2.12/configure.in	2008-03-08 19:15:13.000000000 +0000
+@@ -8,13 +8,13 @@
+ AC_CONFIG_HEADER(include/private/apu_config.h)
+ AC_CONFIG_AUX_DIR(build)
+ 
+-sinclude(build/apu-conf.m4)
+-sinclude(build/apu-iconv.m4)
+-sinclude(build/apu-hints.m4)
+-sinclude(build/apr_common.m4)
+-sinclude(build/find_apr.m4)
+-sinclude(build/dbm.m4)
+-sinclude(build/dbd.m4)
++#sinclude(build/apu-conf.m4)
++#sinclude(build/apu-iconv.m4)
++#sinclude(build/apu-hints.m4)
++#sinclude(build/apr_common.m4)
++#sinclude(build/find_apr.m4)
++#sinclude(build/dbm.m4)
++#sinclude(build/dbd.m4)
+ 
+ dnl Generate ./config.nice for reproducing runs of configure
+ dnl 
diff --git a/packages/apr/apr-util_1.2.12.bb b/packages/apr/apr-util_1.2.12.bb
new file mode 100644
index 0000000000..64f6bcbcf8
--- /dev/null
+++ b/packages/apr/apr-util_1.2.12.bb
@@ -0,0 +1,29 @@
+DESCRIPTION = "Apache Portable Runtime (APR) companion library"
+SECTION = "libs"
+DEPENDS = "apr expat gdbm"
+LICENSE = "Apache License, Version 2.0"
+
+PR = "r2"
+
+# apache mirrors?
+SRC_URI = "${APACHE_MIRROR}/apr/${P}.tar.gz \
+           file://configure_fixes.patch;patch=1"
+
+EXTRA_OECONF = "--with-apr=${STAGING_BINDIR_CROSS} --with-dbm=gdbm \
+		--with-gdbm=${STAGING_DIR_HOST}${layout_prefix} \
+		--without-sqlite2 \
+		--without-sqlite3 \
+		--with-expat=${STAGING_DIR_HOST}${layout_prefix}"
+
+
+inherit autotools lib_package binconfig
+
+OE_BINCONFIG_EXTRA_MANGLE = " -e 's:location=source:location=installed:'"
+
+do_configure_prepend() {
+	cp ${STAGING_DATADIR}/apr/apr_rules.mk ${S}/build/rules.mk
+}
+
+do_stage() {
+	autotools_stage_all
+}
diff --git a/packages/apr/apr-util_1.2.7.bb b/packages/apr/apr-util_1.2.7.bb
index 904e41f8a3..5f019d624e 100644
--- a/packages/apr/apr-util_1.2.7.bb
+++ b/packages/apr/apr-util_1.2.7.bb
@@ -3,10 +3,11 @@ SECTION = "libs"
 DEPENDS = "apr expat gdbm"
 LICENSE = "Apache License, Version 2.0"
 
-PR = "r2"
+PR = "r3"
 
 # apache mirrors?
-SRC_URI = "${APACHE_MIRROR}/apr/${P}.tar.gz"
+SRC_URI = "${APACHE_MIRROR}/apr/${P}.tar.gz \
+           file://configure_fixes.patch;patch=1"
 
 EXTRA_OECONF = "--with-apr=${STAGING_BINDIR_CROSS} --with-dbm=gdbm \
 		--with-gdbm=${STAGING_DIR_HOST}${layout_prefix} \
@@ -19,14 +20,10 @@ inherit autotools lib_package binconfig
 
 OE_BINCONFIG_EXTRA_MANGLE = " -e 's:location=source:location=installed:'"
 
-do_configure() {
-  cp ${STAGING_DATADIR}/apr_rules.mk ${S}/build/rules.mk
-  oe_runconf
+do_configure_prepend () {
+	cp ${STAGING_DATADIR}/apr/apr_rules.mk ${S}/build/rules.mk
 }
 
 do_stage() {
-  autotools_stage_all
-  sed -i s,/usr/lib/libgdbm.la,-lgdbm,g   ${STAGING_LIBDIR}/libaprutil-1.la
-  sed -i s,/usr/lib/libexpat.la,-lexpat,g ${STAGING_LIBDIR}/libaprutil-1.la
-  sed -i s,/usr/lib/libapr-1.la,-lapr-1,g ${STAGING_LIBDIR}/libaprutil-1.la
+	autotools_stage_all
 }
diff --git a/packages/nano/nano-2.0.6/.mtn2git_empty b/packages/apr/apr/.mtn2git_empty
index e69de29bb2..e69de29bb2 100644
--- a/packages/nano/nano-2.0.6/.mtn2git_empty
+++ b/packages/apr/apr/.mtn2git_empty
diff --git a/packages/apr/apr/configure_fixes.patch b/packages/apr/apr/configure_fixes.patch
new file mode 100644
index 0000000000..2b2e0eccb2
--- /dev/null
+++ b/packages/apr/apr/configure_fixes.patch
@@ -0,0 +1,22 @@
+Index: apr-1.2.12/configure.in
+===================================================================
+--- apr-1.2.12.orig/configure.in	2008-03-08 21:41:43.000000000 +0000
++++ apr-1.2.12/configure.in	2008-03-08 21:43:08.000000000 +0000
+@@ -13,12 +13,11 @@
+ dnl 
+ dnl Include our own M4 macros along with those for libtool
+ dnl 
+-sinclude(build/apr_common.m4)
+-sinclude(build/apr_network.m4)
+-sinclude(build/apr_threads.m4)
+-sinclude(build/apr_hints.m4)
+-sinclude(build/libtool.m4)
+-sinclude(build/ltsugar.m4)
++#sinclude(build/apr_common.m4)
++#sinclude(build/apr_network.m4)
++#sinclude(build/apr_threads.m4)
++#sinclude(build/apr_hints.m4)
++#sinclude(build/libtool.m4)
+ 
+ dnl Hard-coded inclusion at the tail end of apr_private.h:
+ AH_BOTTOM([
diff --git a/packages/apr/apr_1.2.12.bb b/packages/apr/apr_1.2.12.bb
new file mode 100644
index 0000000000..923e9b380c
--- /dev/null
+++ b/packages/apr/apr_1.2.12.bb
@@ -0,0 +1,26 @@
+DESCRIPTION = "Apache Portable Runtime (APR) library"
+SECTION = "libs"
+LICENSE = "Apache License, Version 2.0"
+
+PR = "r0"
+
+# apache mirrors?
+SRC_URI = "${APACHE_MIRROR}/apr/${P}.tar.bz2 \
+           file://configure_fixes.patch;patch=1"
+
+inherit autotools lib_package binconfig
+
+OE_BINCONFIG_EXTRA_MANGLE = " -e 's:location=source:location=installed:'"
+
+do_stage() {
+  autotools_stage_all
+  install -d ${STAGING_DATADIR}/apr
+  cp ${S}/build/apr_rules.mk ${STAGING_DATADIR}/apr/
+  sed -i s,apr_builddir=.*,apr_builddir=,g ${STAGING_DATADIR}/apr/apr_rules.mk
+  sed -i s,apr_builders=.*,apr_builders=,g ${STAGING_DATADIR}/apr/apr_rules.mk
+  sed -i s,LIBTOOL=.*,LIBTOOL=\$\(SHELL\)\ ${TARGET_PREFIX}libtool,g ${STAGING_DATADIR}/apr/apr_rules.mk
+  sed -i s,\$\(apr_builders\),${STAGING_DATADIR}/apr/,g ${STAGING_DATADIR}/apr/apr_rules.mk
+  cp ${S}/build/mkdir.sh ${STAGING_DATADIR}/apr/
+  cp ${S}/build/make_exports.awk ${STAGING_DATADIR}/apr/
+  cp ${S}/build/make_var_export.awk ${STAGING_DATADIR}/apr/
+}
diff --git a/packages/apr/apr_1.2.7.bb b/packages/apr/apr_1.2.7.bb
index d0f2916bfa..16365d7998 100644
--- a/packages/apr/apr_1.2.7.bb
+++ b/packages/apr/apr_1.2.7.bb
@@ -2,10 +2,11 @@ DESCRIPTION = "Apache Portable Runtime (APR) library"
 SECTION = "libs"
 LICENSE = "Apache License, Version 2.0"
 
-PR = "r1"
+PR = "r2"
 
 # apache mirrors?
-SRC_URI = "${APACHE_MIRROR}/apr/${P}.tar.bz2"
+SRC_URI = "${APACHE_MIRROR}/apr/${P}.tar.bz2 \
+           file://configure_fixes.patch;patch=1"
 
 inherit autotools lib_package binconfig
 
@@ -17,5 +18,13 @@ do_configure() {
 
 do_stage() {
   autotools_stage_all
-  cp ${S}/build/apr_rules.mk ${STAGING_DATADIR}
+  install -d ${STAGING_DATADIR}/apr
+  cp ${S}/build/apr_rules.mk ${STAGING_DATADIR}/apr/
+  sed -i s,apr_builddir=.*,apr_builddir=,g ${STAGING_DATADIR}/apr/apr_rules.mk
+  sed -i s,apr_builders=.*,apr_builders=,g ${STAGING_DATADIR}/apr/apr_rules.mk
+  sed -i s,LIBTOOL=.*,LIBTOOL=\$\(SHELL\)\ ${TARGET_PREFIX}libtool,g ${STAGING_DATADIR}/apr/apr_rules.mk
+  sed -i s,\$\(apr_builders\),${STAGING_DATADIR}/apr/,g ${STAGING_DATADIR}/apr/apr_rules.mk
+  cp ${S}/build/mkdir.sh ${STAGING_DATADIR}/apr/
+  cp ${S}/build/make_exports.awk ${STAGING_DATADIR}/apr/
+  cp ${S}/build/make_var_export.awk ${STAGING_DATADIR}/apr/
 }
diff --git a/packages/c-nc/.mtn2git_empty b/packages/c-nc/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/c-nc/.mtn2git_empty
diff --git a/packages/c-nc/c-nc_0.5.bb b/packages/c-nc/c-nc_0.5.bb
new file mode 100644
index 0000000000..b7d91621db
--- /dev/null
+++ b/packages/c-nc/c-nc_0.5.bb
@@ -0,0 +1,19 @@
+DESCRIPTION = "A Mastermind style game in GTK+"
+SECTION = "x11/games"
+LICENSE = "GPLv2"
+HOMEPAGE = "http://freshmeat.net/projects/c-nc/"
+DEPENDS = "gtk+"
+AUTHOR = "Alexandru Scvortov <scvalex@gmail.com>"
+PV = "0.5"
+
+inherit autotools
+
+SRC_URI = "http://c-nc.googlecode.com/files/c-nc-${PV}.tar.gz"
+
+do_install() {
+	install -d ${D}${bindir} ${D}${docdir}/c-nc
+	install -m 0755 ${S}/c-nc ${D}${bindir}
+	install -d ${D}${datadir}/applications/
+	install -m 0755	${S}/c-nc.desktop ${D}${datadir}/applications/
+}
+
diff --git a/packages/dt/.mtn2git_empty b/packages/dt/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/dt/.mtn2git_empty
diff --git a/packages/dt/dt_15.14.bb b/packages/dt/dt_15.14.bb
new file mode 100644
index 0000000000..5185af4f15
--- /dev/null
+++ b/packages/dt/dt_15.14.bb
@@ -0,0 +1,18 @@
+DESCRIPTION = "The Data Test Program (dt) is a generic data test program used to verify proper \
+operation of peripherals, file systems, device drivers, or any data stream supported by the \
+operating system."
+SECTION = "console/tests"
+HOMEPAGE = "http://home.comcast.net/~SCSIguy/SCSI_FAQ/RMiller_Tools/dt.html"
+LICENSE = "Public domain"
+
+SRC_URI = "http://home.comcast.net/~SCSIguy/SCSI_FAQ/RMiller_Tools/ftp/dt/dt-source.tar.gz"
+S = "${WORKDIR}/${PN}.d-WIP"
+
+do_compile() {
+	${MAKE} -f Makefile.linux
+}
+
+do_install() {
+	install -d ${D}${bindir}
+	install -m 0755 dt ${D}${bindir}
+}
diff --git a/packages/e2fsprogs/e2fsprogs.inc b/packages/e2fsprogs/e2fsprogs.inc
index 7673d49e21..eb094470c4 100644
--- a/packages/e2fsprogs/e2fsprogs.inc
+++ b/packages/e2fsprogs/e2fsprogs.inc
@@ -9,7 +9,6 @@ S = "${WORKDIR}/e2fsprogs-${PV}"
 
 inherit autotools
 
-EXTRA_OECONF_linux-uclibc = "--disable-nls"
-EXTRA_OECONF += " --enable-dynamic-e2fsck"
+EXTRA_OECONF = "--enable-dynamic-e2fsck --disable-nls --sbindir=${base_sbindir}"
 
 PARALLEL_MAKE = ""
diff --git a/packages/e2fsprogs/e2fsprogs_1.38.bb b/packages/e2fsprogs/e2fsprogs_1.38.bb
index 91a391975f..a586c1ab10 100644
--- a/packages/e2fsprogs/e2fsprogs_1.38.bb
+++ b/packages/e2fsprogs/e2fsprogs_1.38.bb
@@ -1,13 +1,9 @@
 require e2fsprogs.inc
 
-PR = "r11"
+PR = "r12"
 
 SRC_URI += "file://no-hardlinks.patch;patch=1"
 
-EXTRA_OECONF += " --sbindir=${base_sbindir} \
-                  --disable-nls \
-                "
-
 do_compile_prepend () {
 	find ./ -print|xargs chmod u=rwX
 	( cd util; ${BUILD_CC} subst.c -o subst )
diff --git a/packages/espeak/espeak_1.30.bb b/packages/espeak/espeak_1.30.bb
index a460b5b4ba..523acc77cb 100644
--- a/packages/espeak/espeak_1.30.bb
+++ b/packages/espeak/espeak_1.30.bb
@@ -15,9 +15,9 @@ DEPENDS = "portaudio-v19"
 
 ######################################################################################
 
-PR = "r1"
+PR = "r2"
 
-SRC_URI = "http://kent.dl.sourceforge.net/sourceforge/espeak/espeak-${PV}-source.zip"
+SRC_URI = "${SOURCEFORGE_MIRROR}/espeak/espeak-${PV}-source.zip"
 
 S = "${WORKDIR}/${PN}-${PV}-source"
 
diff --git a/packages/gcc/gcc-cross-initial.inc b/packages/gcc/gcc-cross-initial.inc
index 2165bf22ce..d5722473cf 100644
--- a/packages/gcc/gcc-cross-initial.inc
+++ b/packages/gcc/gcc-cross-initial.inc
@@ -1,5 +1,6 @@
 DEPENDS = "virtual/${TARGET_PREFIX}binutils"
-DEPENDS += "${@['virtual/${TARGET_PREFIX}libc-initial',''][bb.data.getVar('TARGET_ARCH', d, 1) in ['arm', 'armeb', 'mips', 'mipsel']]}"
+# @todo Please add comment on why this is (still?) needed?
+DEPENDS += "${@['virtual/${TARGET_PREFIX}libc-initial',''][bb.data.getVar('TARGET_ARCH', d, 1) in ['arm', 'armeb', 'mips', 'mipsel', 'powerpc']]}"
 PROVIDES = "virtual/${TARGET_PREFIX}gcc-initial"
 PACKAGES = ""
 
diff --git a/packages/gnutls/gnutls.inc b/packages/gnutls/gnutls.inc
index 781267093c..6400e80b11 100644
--- a/packages/gnutls/gnutls.inc
+++ b/packages/gnutls/gnutls.inc
@@ -7,10 +7,10 @@ SRC_URI = "ftp://ftp.gnutls.org/pub/gnutls/gnutls-${PV}.tar.bz2"
 
 inherit autotools binconfig pkgconfig
 
-EXTRA_OECONF="--with-included-opencdk --with-included-libtasn1"
+EXTRA_OECONF = "--with-included-opencdk --with-included-libtasn1"
 
 # fix wrong dependency
-do_configure_append() {
+do_configure_prepend() {
     sed -i s,gcrypt,libgcrypt, lib/gnutls.pc.in
 }
 
diff --git a/packages/gnutls/gnutls_1.4.5.bb b/packages/gnutls/gnutls_1.4.5.bb
index 4c247717ae..749064af65 100644
--- a/packages/gnutls/gnutls_1.4.5.bb
+++ b/packages/gnutls/gnutls_1.4.5.bb
@@ -1,3 +1,3 @@
 require gnutls.inc
 
-PR = "r2"
+PR = "r3"
diff --git a/packages/gnutls/gnutls_1.6.3.bb b/packages/gnutls/gnutls_1.6.3.bb
index cc35d8b7a3..ce10a4b6cf 100644
--- a/packages/gnutls/gnutls_1.6.3.bb
+++ b/packages/gnutls/gnutls_1.6.3.bb
@@ -6,4 +6,4 @@ SRC_URI += "\
 	file://configure_madness.patch;patch=1 \
 	"
 
-PR = "r5"
+PR = "r6"
diff --git a/packages/gstreamer/gst-plugins-bad_0.10.3.bb b/packages/gstreamer/gst-plugins-bad_0.10.3.bb
deleted file mode 100644
index 3e487314be..0000000000
--- a/packages/gstreamer/gst-plugins-bad_0.10.3.bb
+++ /dev/null
@@ -1,5 +0,0 @@
-require gst-plugins.inc
-
-DEPENDS += "gst-plugins-base directfb"
-SRC_URI += "file://cross-compile.patch;patch=1"
-PR = "r6"
diff --git a/packages/gstreamer/gst-plugins-bad_0.10.5.bb b/packages/gstreamer/gst-plugins-bad_0.10.6.bb
index ce61d10010..2a998589ac 100644
--- a/packages/gstreamer/gst-plugins-bad_0.10.5.bb
+++ b/packages/gstreamer/gst-plugins-bad_0.10.6.bb
@@ -8,5 +8,3 @@ do_compile_prepend() {
 	# work around missing files in upstream tarball (upstream bug #454078)
 	install -m 0644 ${WORKDIR}/vorbis*.h ${S}/ext/ivorbis/
 }
-
-PR = "r1"
diff --git a/packages/gstreamer/gst-plugins-base_0.10.12.bb b/packages/gstreamer/gst-plugins-base_0.10.12.bb
deleted file mode 100644
index 33b189a0ff..0000000000
--- a/packages/gstreamer/gst-plugins-base_0.10.12.bb
+++ /dev/null
@@ -1,12 +0,0 @@
-require gst-plugins.inc
-
-PROVIDES += "gst-plugins"
-
-# gst-plugins-base only builds the alsa plugin
-# if alsa has been built and is present.  You will
-# not get an error if this is not present, just 
-# a missing alsa plugin
-DEPENDS += "alsa-lib"
-
-PR = "r2"
-
diff --git a/packages/gstreamer/gst-plugins-base_0.10.14.bb b/packages/gstreamer/gst-plugins-base_0.10.14.bb
deleted file mode 100644
index 33b189a0ff..0000000000
--- a/packages/gstreamer/gst-plugins-base_0.10.14.bb
+++ /dev/null
@@ -1,12 +0,0 @@
-require gst-plugins.inc
-
-PROVIDES += "gst-plugins"
-
-# gst-plugins-base only builds the alsa plugin
-# if alsa has been built and is present.  You will
-# not get an error if this is not present, just 
-# a missing alsa plugin
-DEPENDS += "alsa-lib"
-
-PR = "r2"
-
diff --git a/packages/gstreamer/gst-plugins-good_0.10.6.bb b/packages/gstreamer/gst-plugins-good_0.10.6.bb
deleted file mode 100644
index e009145ead..0000000000
--- a/packages/gstreamer/gst-plugins-good_0.10.6.bb
+++ /dev/null
@@ -1,5 +0,0 @@
-require gst-plugins.inc
-
-EXTRA_OECONF += "--with-check=no"
-DEPENDS += "gst-plugins-base"
-PR = "r3"
diff --git a/packages/gstreamer/gst-plugins-good_0.10.5.bb b/packages/gstreamer/gst-plugins-good_0.10.7.bb
index e009145ead..e84c4801f1 100644
--- a/packages/gstreamer/gst-plugins-good_0.10.5.bb
+++ b/packages/gstreamer/gst-plugins-good_0.10.7.bb
@@ -2,4 +2,3 @@ require gst-plugins.inc
 
 EXTRA_OECONF += "--with-check=no"
 DEPENDS += "gst-plugins-base"
-PR = "r3"
diff --git a/packages/gstreamer/gst-plugins-ugly_0.10.6.bb b/packages/gstreamer/gst-plugins-ugly_0.10.6.bb
deleted file mode 100644
index c88a4db990..0000000000
--- a/packages/gstreamer/gst-plugins-ugly_0.10.6.bb
+++ /dev/null
@@ -1,9 +0,0 @@
-require gst-plugins.inc
-
-DEPENDS += "gst-plugins-base mpeg2dec libsidplay"
-PR = "r3"
-
-SRC_URI += "file://cross-compile.patch;patch=1 \
-            file://gstmad_16bit.patch;patch=1 \
-            file://gstsid_autofoo_HACK.patch;patch=1"
-
diff --git a/packages/gstreamer/gst-plugins-ugly_0.10.7.bb b/packages/gstreamer/gst-plugins-ugly_0.10.7.bb
new file mode 100644
index 0000000000..fd008b065a
--- /dev/null
+++ b/packages/gstreamer/gst-plugins-ugly_0.10.7.bb
@@ -0,0 +1,10 @@
+require gst-plugins.inc
+PR = "r0"
+
+DEPENDS += "gst-plugins-base mpeg2dec libsidplay"
+
+SRC_URI += "\
+#  file://cross-compile.patch;patch=1 \
+  file://gstmad_16bit.patch;patch=1 \
+  file://gstsid_autofoo_HACK.patch;patch=1 \
+"
diff --git a/packages/gstreamer/gst-plugins.inc b/packages/gstreamer/gst-plugins.inc
index 8e8fd0f1ca..66546d5f2b 100644
--- a/packages/gstreamer/gst-plugins.inc
+++ b/packages/gstreamer/gst-plugins.inc
@@ -24,3 +24,6 @@ python populate_packages_prepend () {
 }
 
 ALLOW_EMPTY = "1"
+
+FILES_${PN}-dbg += "${libdir}/gstreamer-${LIBV}/.debug"
+
diff --git a/packages/gstreamer/gstreamer_0.10.12.bb b/packages/gstreamer/gstreamer_0.10.12.bb
deleted file mode 100644
index 49d7f37053..0000000000
--- a/packages/gstreamer/gstreamer_0.10.12.bb
+++ /dev/null
@@ -1,3 +0,0 @@
-require gstreamer.inc
-
-PR = "r1"
-\ No newline at end of file
diff --git a/packages/gstreamer/gstreamer_0.10.14.bb b/packages/gstreamer/gstreamer_0.10.14.bb
deleted file mode 100644
index 9e9ae62cb1..0000000000
--- a/packages/gstreamer/gstreamer_0.10.14.bb
+++ /dev/null
@@ -1,3 +0,0 @@
-require gstreamer.inc
-
-PR = "r0"
diff --git a/packages/gtk-webcore/midori_0.0.17.bb b/packages/gtk-webcore/midori_0.0.17.bb
new file mode 100644
index 0000000000..19cc686566
--- /dev/null
+++ b/packages/gtk-webcore/midori_0.0.17.bb
@@ -0,0 +1,11 @@
+DESCRIPTION = "Midori is a lightweight web browser."
+LICENSE = "GPLv2"
+
+DEPENDS = "webkit-gtk libsexy" 
+
+inherit autotools pkgconfig
+
+SRC_URI = "http://software.twotoasts.de/media/midori/midori-${PV}.tar.gz \
+           file://webkit-update.patch;patch=1"
+
+
diff --git a/packages/libgee/.mtn2git_empty b/packages/libgee/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/libgee/.mtn2git_empty
diff --git a/packages/libgee/files/.mtn2git_empty b/packages/libgee/files/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/libgee/files/.mtn2git_empty
diff --git a/packages/libgee/files/no-tests.patch b/packages/libgee/files/no-tests.patch
new file mode 100644
index 0000000000..d2d20b2c4e
--- /dev/null
+++ b/packages/libgee/files/no-tests.patch
@@ -0,0 +1,12 @@
+Index: libgee-0.1.2/Makefile.am
+===================================================================
+--- libgee-0.1.2.orig/Makefile.am
++++ libgee-0.1.2/Makefile.am
+@@ -4,7 +4,6 @@ NULL =
+ 
+ SUBDIRS = \
+ 	gee \
+-	tests \
+ 	$(NULL)
+ 
+ pkgconfigdir = $(libdir)/pkgconfig
diff --git a/packages/libgee/libgee_0.1.2.bb b/packages/libgee/libgee_0.1.2.bb
new file mode 100644
index 0000000000..4f6d113150
--- /dev/null
+++ b/packages/libgee/libgee_0.1.2.bb
@@ -0,0 +1,12 @@
+DESCRIPTION = "libgee is a collection library providing GObject-based interfaces \
+and classes for commonly used data structures."
+HOMEPAGE = "http://live.gnome.org/Libgee"
+SECTION = "libs"
+DEPENDS = "glib-2.0"
+LICENSE = "LGPL"
+
+SRC_URI = "ftp://ftp.gnome.org/pub/GNOME/sources/libgee/0.1/libgee-${PV}.tar.bz2 \
+           file://no-tests.patch;patch=1"
+
+inherit autotools pkgconfig
+
diff --git a/packages/libol/libol_0.3.16.bb b/packages/libol/libol_0.3.16.bb
deleted file mode 100644
index 1e4a1e9408..0000000000
--- a/packages/libol/libol_0.3.16.bb
+++ /dev/null
@@ -1,15 +0,0 @@
-PR = "r5"
-
-SRC_URI = "http://www.balabit.com/downloads/files/libol/0.3/${P}.tar.gz"
-
-S = "${WORKDIR}/${PN}-${PV}"
-inherit autotools
-
-do_stage() {
-	install -d ${STAGING_INCDIR}/libol
-	install -m 0755 ${S}/libol-config ${STAGING_BINDIR_CROSS}
-	install -m 0755 ${S}/src/.libs/libol.so.0.0.0 ${STAGING_LIBDIR}
-	ln -fs ${STAGING_LIBDIR}/libol.so.0.0.0 ${STAGING_LIBDIR}/libol.so.0
-	install ${S}/src/*.h ${STAGING_INCDIR}/libol/
-}
-
diff --git a/packages/libol/libol_0.3.18.bb b/packages/libol/libol_0.3.18.bb
index 0b6518c43e..7dc48f92df 100644
--- a/packages/libol/libol_0.3.18.bb
+++ b/packages/libol/libol_0.3.18.bb
@@ -1,14 +1,12 @@
-PR = "r7"
+DESCRIPTION = "A tiny C support library"
+SECTION = "libs"
+LICENSE = "GPL"
+PR = "r8"
 
 SRC_URI = "http://www.balabit.com/downloads/files/libol/0.3/${P}.tar.gz"
 
-S = "${WORKDIR}/${PN}-${PV}"
-
 inherit autotools binconfig
 
 do_stage() {
-        install -d ${STAGING_INCDIR}/libol
-        install -m 0755 ${S}/src/.libs/libol.so.0.0.0 ${STAGING_LIBDIR}/
-        ln -fs ${STAGING_LIBDIR}/libol.so.0.0.0 ${STAGING_LIBDIR}/libol.so.0
-        install ${S}/src/*.h ${STAGING_INCDIR}/libol/
+	autotools_stage_all
 }
diff --git a/packages/libtool/libtool-cross_1.5.10.bb b/packages/libtool/libtool-cross_1.5.10.bb
index 5f15c56a97..0d0b90ac81 100644
--- a/packages/libtool/libtool-cross_1.5.10.bb
+++ b/packages/libtool/libtool-cross_1.5.10.bb
@@ -1,7 +1,7 @@
-SECTION = "devel"
+require libtool.inc
 require libtool_${PV}.bb
 
-PR = "r9"
+PR = "r10"
 PACKAGES = ""
 FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/libtool-${PV}"
 SRC_URI_append = " file://libdir-la.patch;patch=1 \
@@ -18,7 +18,7 @@ prefix = "${STAGING_DIR_NATIVE}${layout_prefix}"
 exec_prefix = "${STAGING_DIR_NATIVE}${layout_exec_prefix}"
 bindir = "${STAGING_BINDIR_NATIVE}"
 
-do_compile () {
+do_configure_prepend () {
 	rm -f ltmain.shT
 	date=`/bin/sh ./mkstamp < ./ChangeLog` && \
         sed -e 's/@''PACKAGE@/libtool/' -e 's/@''VERSION@/1.5.10/' \
@@ -28,6 +28,10 @@ do_compile () {
 	cp ltmain.sh ./libltdl/
 }
 
+do_compile () {
+	:
+}
+
 do_stage () {
         install -m 0755 ${HOST_SYS}-libtool ${bindir}/${HOST_SYS}-libtool
         install -m 0644 libltdl/ltdl.h ${STAGING_INCDIR}/
diff --git a/packages/libtool/libtool-cross_1.5.22.bb b/packages/libtool/libtool-cross_1.5.22.bb
index c91647b559..c44b0512ee 100644
--- a/packages/libtool/libtool-cross_1.5.22.bb
+++ b/packages/libtool/libtool-cross_1.5.22.bb
@@ -1,6 +1,6 @@
 DEFAULT_PREFERENCE = "-1"
 
-SECTION = "devel"
+require libtool.inc
 require libtool_${PV}.bb
 
 PR = "r0"
diff --git a/packages/libtool/libtool-cross_1.5.24.bb b/packages/libtool/libtool-cross_1.5.24.bb
index e60db4b808..cf6cc18ef6 100644
--- a/packages/libtool/libtool-cross_1.5.24.bb
+++ b/packages/libtool/libtool-cross_1.5.24.bb
@@ -1,4 +1,4 @@
-SECTION = "devel"
+require libtool.inc
 require libtool_${PV}.bb
 
 PR = "r0"
diff --git a/packages/libtool/libtool-native_1.5.10.bb b/packages/libtool/libtool-native_1.5.10.bb
index e21a20b85d..ec3dd604cd 100644
--- a/packages/libtool/libtool-native_1.5.10.bb
+++ b/packages/libtool/libtool-native_1.5.10.bb
@@ -1,4 +1,4 @@
-SECTION = "devel"
+require libtool.inc
 require libtool_${PV}.bb
 
 PR = "r9"
diff --git a/packages/libtool/libtool-native_1.5.22.bb b/packages/libtool/libtool-native_1.5.22.bb
index dec4bf1e14..16db0bb65b 100644
--- a/packages/libtool/libtool-native_1.5.22.bb
+++ b/packages/libtool/libtool-native_1.5.22.bb
@@ -1,6 +1,6 @@
 DEFAULT_PREFERENCE = "-1"
 
-SECTION = "devel"
+require libtool.inc
 require libtool_${PV}.bb
 
 PR = "r0"
diff --git a/packages/libtool/libtool-native_1.5.24.bb b/packages/libtool/libtool-native_1.5.24.bb
index 3587dd8034..1b0cb90a1e 100644
--- a/packages/libtool/libtool-native_1.5.24.bb
+++ b/packages/libtool/libtool-native_1.5.24.bb
@@ -1,6 +1,7 @@
 SECTION = "devel"
+
+require libtool.inc
 require libtool_${PV}.bb
-DEFAULT_PREFERENCE = "-1"
 
 PR = "r0"
 FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/libtool-${PV}"
diff --git a/packages/libtool/libtool.inc b/packages/libtool/libtool.inc
new file mode 100644
index 0000000000..db86d15ba4
--- /dev/null
+++ b/packages/libtool/libtool.inc
@@ -0,0 +1,8 @@
+DESCRIPTION = "Generic library support script \
+This is GNU libtool, a generic library support script.  Libtool hides \
+the complexity of generating special library types (such as shared \
+libraries) behind a consistent interface."
+HOMEPAGE = "http://www.gnu.org/software/libtool/libtool.html"
+LICENSE = "GPL"
+SECTION = "devel"
+
diff --git a/packages/libtool/libtool_1.5.10.bb b/packages/libtool/libtool_1.5.10.bb
index 3a9ff7ef59..428a06a0e7 100644
--- a/packages/libtool/libtool_1.5.10.bb
+++ b/packages/libtool/libtool_1.5.10.bb
@@ -1,10 +1,4 @@
-DESCRIPTION = "Generic library support script \
-This is GNU libtool, a generic library support script.  Libtool hides \
-the complexity of generating special library types (such as shared \
-libraries) behind a consistent interface."
-HOMEPAGE = "http://www.gnu.org/software/libtool/libtool.html"
-LICENSE = "GPL"
-SECTION = "devel"
+require libtool.inc
 PR = "r5"
 
 SRC_URI = "${GNU_MIRROR}/libtool/libtool-${PV}.tar.gz \
diff --git a/packages/libtool/libtool_1.5.22.bb b/packages/libtool/libtool_1.5.22.bb
index 66182cb57e..4bed7842b4 100644
--- a/packages/libtool/libtool_1.5.22.bb
+++ b/packages/libtool/libtool_1.5.22.bb
@@ -1,12 +1,6 @@
 DEFAULT_PREFERENCE = "-1"
 
-DESCRIPTION = "Generic library support script \
-This is GNU libtool, a generic library support script.  Libtool hides \
-the complexity of generating special library types (such as shared \
-libraries) behind a consistent interface."
-HOMEPAGE = "http://www.gnu.org/software/libtool/libtool.html"
-LICENSE = "GPL"
-SECTION = "devel"
+require libtool.inc
 PR = "r1"
 
 SRC_URI = "${GNU_MIRROR}/libtool/libtool-${PV}.tar.gz \
diff --git a/packages/libtool/libtool_1.5.24.bb b/packages/libtool/libtool_1.5.24.bb
index f40613f3ee..7bdad1bed4 100644
--- a/packages/libtool/libtool_1.5.24.bb
+++ b/packages/libtool/libtool_1.5.24.bb
@@ -1,12 +1,6 @@
 DEFAULT_PREFERENCE = "-1"
 
-DESCRIPTION = "Generic library support script \
-This is GNU libtool, a generic library support script.  Libtool hides \
-the complexity of generating special library types (such as shared \
-libraries) behind a consistent interface."
-HOMEPAGE = "http://www.gnu.org/software/libtool/libtool.html"
-LICENSE = "GPL"
-SECTION = "devel"
+require libtool.inc
 PR = "r1"
 
 SRC_URI = "${GNU_MIRROR}/libtool/libtool-${PV}.tar.gz \
diff --git a/packages/libtool/libtool_1.5.6.bb b/packages/libtool/libtool_1.5.6.bb
index 7c02c4ba97..7fd9b81a3d 100644
--- a/packages/libtool/libtool_1.5.6.bb
+++ b/packages/libtool/libtool_1.5.6.bb
@@ -1,12 +1,6 @@
 # Exists for compatibility with certain distributions (e.g. Maemo).
 
-DESCRIPTION = "Generic library support script \
-This is GNU libtool, a generic library support script.  Libtool hides \
-the complexity of generating special library types (such as shared \
-libraries) behind a consistent interface."
-HOMEPAGE = "http://www.gnu.org/software/libtool/libtool.html"
-LICENSE = "GPL"
-SECTION = "devel"
+require libtool.inc
 PR = "r2"
 
 DEFAULT_PREFERENCE = "-1"
diff --git a/packages/linux/linux-mainstone/.mtn2git_empty b/packages/linux/linux-mainstone/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/linux/linux-mainstone/.mtn2git_empty
diff --git a/packages/linux/linux-mainstone/mainstone-keypad.patch b/packages/linux/linux-mainstone/mainstone-keypad.patch
new file mode 100644
index 0000000000..cad6289260
--- /dev/null
+++ b/packages/linux/linux-mainstone/mainstone-keypad.patch
@@ -0,0 +1,7631 @@
+diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/devices.c linux-2.6.25-rc4/arch/arm/mach-pxa/devices.c
+--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/devices.c	2008-03-08 18:25:54.000000000 +0100
++++ linux-2.6.25-rc4/arch/arm/mach-pxa/devices.c	2008-03-08 16:22:35.000000000 +0100
+@@ -396,6 +396,31 @@
+ 
+ #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+ 
++static struct resource pxa27x_resource_keypad[] = {
++	[0] = {
++		.start	= 0x41500000,
++		.end	= 0x4150004c,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= IRQ_KEYPAD,
++		.end	= IRQ_KEYPAD,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++struct platform_device pxa27x_device_keypad = {
++	.name		= "pxa27x-keypad",
++	.id		= -1,
++	.resource	= pxa27x_resource_keypad,
++	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
++};
++
++void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
++{
++	pxa_register_device(&pxa27x_device_keypad, info);
++}
++
+ static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
+ 
+ static struct resource pxa27x_resource_ohci[] = {
+diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/devices.h linux-2.6.25-rc4/arch/arm/mach-pxa/devices.h
+--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/devices.h	2008-03-08 18:25:54.000000000 +0100
++++ linux-2.6.25-rc4/arch/arm/mach-pxa/devices.h	2008-03-08 16:22:35.000000000 +0100
+@@ -14,6 +14,7 @@
+ 
+ extern struct platform_device pxa27x_device_i2c_power;
+ extern struct platform_device pxa27x_device_ohci;
++extern struct platform_device pxa27x_device_keypad;
+ 
+ extern struct platform_device pxa25x_device_ssp;
+ extern struct platform_device pxa25x_device_nssp;
+diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/mainstone.c linux-2.6.25-rc4/arch/arm/mach-pxa/mainstone.c
+--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/mainstone.c	2008-03-08 18:25:54.000000000 +0100
++++ linux-2.6.25-rc4/arch/arm/mach-pxa/mainstone.c	2008-03-08 16:11:42.000000000 +0100
+@@ -46,6 +46,7 @@
+ #include <asm/arch/mmc.h>
+ #include <asm/arch/irda.h>
+ #include <asm/arch/ohci.h>
++#include <asm/arch/pxa27x_keypad.h>
+ 
+ #include "generic.h"
+ #include "devices.h"
+@@ -460,6 +461,72 @@
+ 	.init		= mainstone_ohci_init,
+ };
+ 
++#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
++static unsigned int mainstone_matrix_keys[] = {
++	KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
++	KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
++	KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
++	KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L),
++	KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O),
++	KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R),
++	KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U),
++	KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X),
++	KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z),
++
++	KEY(0, 4, KEY_DOT),	/* . */
++	KEY(1, 4, KEY_CLOSE),	/* @ */
++	KEY(4, 4, KEY_SLASH),
++	KEY(5, 4, KEY_BACKSLASH),
++	KEY(0, 5, KEY_HOME),
++	KEY(1, 5, KEY_LEFTSHIFT),
++	KEY(2, 5, KEY_SPACE),
++	KEY(3, 5, KEY_SPACE),
++	KEY(4, 5, KEY_ENTER),
++	KEY(5, 5, KEY_BACKSPACE),
++
++	KEY(0, 6, KEY_UP),
++	KEY(1, 6, KEY_DOWN),
++	KEY(2, 6, KEY_LEFT),
++	KEY(3, 6, KEY_RIGHT),
++	KEY(4, 6, KEY_SELECT),
++};
++
++struct pxa27x_keypad_platform_data mainstone_keypad_info = {
++	.matrix_key_rows	= 6,
++	.matrix_key_cols	= 7,
++	.matrix_key_map		= mainstone_matrix_keys,
++	.matrix_key_map_size	= ARRAY_SIZE(mainstone_matrix_keys),
++
++	.enable_rotary0		= 1,
++	.rotary0_up_key		= KEY_UP,
++	.rotary0_down_key	= KEY_DOWN,
++
++	.debounce_interval	= 30,
++};
++
++static void __init mainstone_init_keypad(void)
++{
++	pxa_gpio_mode(100 | GPIO_ALT_FN_1_IN);  /* MKIN0 */
++	pxa_gpio_mode(101 | GPIO_ALT_FN_1_IN);  /* MKIN1 */
++	pxa_gpio_mode(102 | GPIO_ALT_FN_1_IN);  /* MKIN2 */
++	pxa_gpio_mode( 97 | GPIO_ALT_FN_3_IN);  /* MKIN3 */
++	pxa_gpio_mode( 98 | GPIO_ALT_FN_3_IN);  /* MKIN4 */
++	pxa_gpio_mode( 99 | GPIO_ALT_FN_3_IN);  /* MKIN5 */
++	pxa_gpio_mode(103 | GPIO_ALT_FN_2_OUT); /* MKOUT0 */
++	pxa_gpio_mode(104 | GPIO_ALT_FN_2_OUT); /* MKOUT1 */
++	pxa_gpio_mode(105 | GPIO_ALT_FN_2_OUT); /* MKOUT2 */
++	pxa_gpio_mode(106 | GPIO_ALT_FN_2_OUT); /* MKOUT3 */
++	pxa_gpio_mode(107 | GPIO_ALT_FN_2_OUT); /* MKOUT4 */
++	pxa_gpio_mode(108 | GPIO_ALT_FN_2_OUT); /* MKOUT5 */
++	pxa_gpio_mode( 93 | GPIO_ALT_FN_1_IN);	/* DKIN0 */
++	pxa_gpio_mode( 94 | GPIO_ALT_FN_1_IN);	/* DKIN1 */
++
++	pxa_set_keypad_info(&mainstone_keypad_info);
++}
++#else
++static inline void mainstone_init_keypad(void) { }
++#endif
++
+ static void __init mainstone_init(void)
+ {
+ 	int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
+@@ -520,6 +587,8 @@
+ 	pxa_set_mci_info(&mainstone_mci_platform_data);
+ 	pxa_set_ficp_info(&mainstone_ficp_platform_data);
+ 	pxa_set_ohci_info(&mainstone_ohci_platform_data);
++
++	mainstone_init_keypad();
+ }
+ 
+ 
+diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/pxa27x.c linux-2.6.25-rc4/arch/arm/mach-pxa/pxa27x.c
+--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/pxa27x.c	2008-03-08 18:25:54.000000000 +0100
++++ linux-2.6.25-rc4/arch/arm/mach-pxa/pxa27x.c	2008-03-08 16:22:35.000000000 +0100
+@@ -151,7 +151,7 @@
+ 
+ 	INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
+ 	INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
+-	INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
++	INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
+ 
+ 	INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
+ 	INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
+diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/pxa3xx.c linux-2.6.25-rc4/arch/arm/mach-pxa/pxa3xx.c
+--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/pxa3xx.c	2008-03-08 18:25:54.000000000 +0100
++++ linux-2.6.25-rc4/arch/arm/mach-pxa/pxa3xx.c	2008-03-08 16:22:35.000000000 +0100
+@@ -185,6 +185,7 @@
+ 	PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
+ 	PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa_device_udc.dev),
+ 	PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
++	PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
+ 
+ 	PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
+ 	PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/akita.h linux-2.6.25-rc4/include/asm-arm/arch/akita.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/akita.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/akita.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,32 @@
++/*
++ * Hardware specific definitions for SL-C1000 (Akita)
++ *
++ * Copyright (c) 2005 Richard Purdie
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++/* Akita IO Expander GPIOs */
++
++#define AKITA_IOEXP_RESERVED_7      (1 << 7)
++#define AKITA_IOEXP_IR_ON           (1 << 6)
++#define AKITA_IOEXP_AKIN_PULLUP     (1 << 5)
++#define AKITA_IOEXP_BACKLIGHT_CONT  (1 << 4)
++#define AKITA_IOEXP_BACKLIGHT_ON    (1 << 3)
++#define AKITA_IOEXP_MIC_BIAS        (1 << 2)
++#define AKITA_IOEXP_RESERVED_1      (1 << 1)
++#define AKITA_IOEXP_RESERVED_0      (1 << 0)
++
++/* Direction Bitfield  0=output  1=input */
++#define AKITA_IOEXP_IO_DIR	0
++/* Default Values */
++#define AKITA_IOEXP_IO_OUT	(AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP)
++
++extern struct platform_device akitaioexp_device;
++
++void akita_set_ioexp(struct device *dev, unsigned char bitmask);
++void akita_reset_ioexp(struct device *dev, unsigned char bitmask);
++
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/audio.h linux-2.6.25-rc4/include/asm-arm/arch/audio.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/audio.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/audio.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,15 @@
++#ifndef __ASM_ARCH_AUDIO_H__
++#define __ASM_ARCH_AUDIO_H__
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++
++typedef struct {
++	int (*startup)(struct snd_pcm_substream *, void *);
++	void (*shutdown)(struct snd_pcm_substream *, void *);
++	void (*suspend)(void *);
++	void (*resume)(void *);
++	void *priv;
++} pxa2xx_audio_ops_t;
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/bitfield.h linux-2.6.25-rc4/include/asm-arm/arch/bitfield.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/bitfield.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/bitfield.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,113 @@
++/*
++ *	FILE    	bitfield.h
++ *
++ *	Version 	1.1
++ *	Author  	Copyright (c) Marc A. Viredaz, 1998
++ *	        	DEC Western Research Laboratory, Palo Alto, CA
++ *	Date    	April 1998 (April 1997)
++ *	System  	Advanced RISC Machine (ARM)
++ *	Language	C or ARM Assembly
++ *	Purpose 	Definition of macros to operate on bit fields.
++ */
++
++
++
++#ifndef __BITFIELD_H
++#define __BITFIELD_H
++
++#ifndef __ASSEMBLY__
++#define UData(Data)	((unsigned long) (Data))
++#else
++#define UData(Data)	(Data)
++#endif
++
++
++/*
++ * MACRO: Fld
++ *
++ * Purpose
++ *    The macro "Fld" encodes a bit field, given its size and its shift value
++ *    with respect to bit 0.
++ *
++ * Note
++ *    A more intuitive way to encode bit fields would have been to use their
++ *    mask. However, extracting size and shift value information from a bit
++ *    field's mask is cumbersome and might break the assembler (255-character
++ *    line-size limit).
++ *
++ * Input
++ *    Size      	Size of the bit field, in number of bits.
++ *    Shft      	Shift value of the bit field with respect to bit 0.
++ *
++ * Output
++ *    Fld       	Encoded bit field.
++ */
++
++#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
++
++
++/*
++ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
++ *
++ * Purpose
++ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
++ *    the size, shift value, mask, aligned mask, and first bit of a
++ *    bit field.
++ *
++ * Input
++ *    Field     	Encoded bit field (using the macro "Fld").
++ *
++ * Output
++ *    FSize     	Size of the bit field, in number of bits.
++ *    FShft     	Shift value of the bit field with respect to bit 0.
++ *    FMsk      	Mask for the bit field.
++ *    FAlnMsk   	Mask for the bit field, aligned on bit 0.
++ *    F1stBit   	First bit of the bit field.
++ */
++
++#define FSize(Field)	((Field) >> 16)
++#define FShft(Field)	((Field) & 0x0000FFFF)
++#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
++#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
++#define F1stBit(Field)	(UData (1) << FShft (Field))
++
++
++/*
++ * MACRO: FInsrt
++ *
++ * Purpose
++ *    The macro "FInsrt" inserts a value into a bit field by shifting the
++ *    former appropriately.
++ *
++ * Input
++ *    Value     	Bit-field value.
++ *    Field     	Encoded bit field (using the macro "Fld").
++ *
++ * Output
++ *    FInsrt    	Bit-field value positioned appropriately.
++ */
++
++#define FInsrt(Value, Field) \
++                	(UData (Value) << FShft (Field))
++
++
++/*
++ * MACRO: FExtr
++ *
++ * Purpose
++ *    The macro "FExtr" extracts the value of a bit field by masking and
++ *    shifting it appropriately.
++ *
++ * Input
++ *    Data      	Data containing the bit-field to be extracted.
++ *    Field     	Encoded bit field (using the macro "Fld").
++ *
++ * Output
++ *    FExtr     	Bit-field value.
++ */
++
++#define FExtr(Data, Field) \
++                	((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
++
++
++#endif /* __BITFIELD_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/cm-x270.h linux-2.6.25-rc4/include/asm-arm/arch/cm-x270.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/cm-x270.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/cm-x270.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,50 @@
++/*
++ * linux/include/asm/arch-pxa/cm-x270.h
++ *
++ * Copyright Compulab Ltd., 2003, 2007
++ * Mike Rapoport <mike@compulab.co.il>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++/* CM-x270 device physical addresses */
++#define CMX270_CS1_PHYS		(PXA_CS1_PHYS)
++#define MARATHON_PHYS		(PXA_CS2_PHYS)
++#define CMX270_IDE104_PHYS	(PXA_CS3_PHYS)
++#define CMX270_IT8152_PHYS	(PXA_CS4_PHYS)
++
++/* Statically mapped regions */
++#define CMX270_VIRT_BASE		(0xe8000000)
++#define CMX270_IT8152_VIRT		(CMX270_VIRT_BASE)
++#define CMX270_IDE104_VIRT		(CMX270_IT8152_VIRT + SZ_64M)
++
++/* GPIO related definitions */
++#define GPIO_IT8152_IRQ			(22)
++
++#define IRQ_GPIO_IT8152_IRQ	IRQ_GPIO(GPIO_IT8152_IRQ)
++#define PME_IRQ			IRQ_GPIO(0)
++#define CMX270_IDE_IRQ		IRQ_GPIO(100)
++#define CMX270_GPIRQ1		IRQ_GPIO(101)
++#define CMX270_TOUCHIRQ		IRQ_GPIO(96)
++#define CMX270_ETHIRQ		IRQ_GPIO(10)
++#define CMX270_GFXIRQ		IRQ_GPIO(95)
++#define CMX270_NANDIRQ		IRQ_GPIO(89)
++#define CMX270_MMC_IRQ		IRQ_GPIO(83)
++
++/* PCMCIA related definitions */
++#define PCC_DETECT(x)	(GPLR(84 - (x)) & GPIO_bit(84 - (x)))
++#define PCC_READY(x)	(GPLR(82 - (x)) & GPIO_bit(82 - (x)))
++
++#define PCMCIA_S0_CD_VALID		IRQ_GPIO(84)
++#define PCMCIA_S0_CD_VALID_EDGE		GPIO_BOTH_EDGES
++
++#define PCMCIA_S1_CD_VALID		IRQ_GPIO(83)
++#define PCMCIA_S1_CD_VALID_EDGE		GPIO_BOTH_EDGES
++
++#define PCMCIA_S0_RDYINT		IRQ_GPIO(82)
++#define PCMCIA_S1_RDYINT		IRQ_GPIO(81)
++
++#define PCMCIA_RESET_GPIO		53
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/colibri.h linux-2.6.25-rc4/include/asm-arm/arch/colibri.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/colibri.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/colibri.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,19 @@
++#ifndef _COLIBRI_H_
++#define _COLIBRI_H_
++
++/* physical memory regions */
++#define COLIBRI_FLASH_PHYS	(PXA_CS0_PHYS)  /* Flash region */
++#define COLIBRI_ETH_PHYS	(PXA_CS2_PHYS)  /* Ethernet DM9000 region */
++#define COLIBRI_SDRAM_BASE	0xa0000000      /* SDRAM region */
++
++/* virtual memory regions */
++#define COLIBRI_DISK_VIRT	0xF0000000	/* Disk On Chip region */
++
++/* size of flash */
++#define COLIBRI_FLASH_SIZE	0x02000000	/* Flash size 32 MB */
++
++/* Ethernet Controller Davicom DM9000 */
++#define GPIO_DM9000		114
++#define COLIBRI_ETH_IRQ	IRQ_GPIO(GPIO_DM9000)
++
++#endif /* _COLIBRI_H_ */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/corgi.h linux-2.6.25-rc4/include/asm-arm/arch/corgi.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/corgi.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/corgi.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,109 @@
++/*
++ * Hardware specific definitions for SL-C7xx series of PDAs
++ *
++ * Copyright (c) 2004-2005 Richard Purdie
++ *
++ * Based on Sharp's 2.4 kernel patches
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#ifndef __ASM_ARCH_CORGI_H
++#define __ASM_ARCH_CORGI_H  1
++
++
++/*
++ * Corgi (Non Standard) GPIO Definitions
++ */
++#define CORGI_GPIO_KEY_INT			(0)	/* Keyboard Interrupt */
++#define CORGI_GPIO_AC_IN			(1) /* Charger Detection */
++#define CORGI_GPIO_WAKEUP			(3) /* System wakeup notification? */
++#define CORGI_GPIO_AK_INT			(4)	/* Headphone Jack Control Interrupt */
++#define CORGI_GPIO_TP_INT			(5)	/* Touch Panel Interrupt */
++#define CORGI_GPIO_nSD_WP			(7) /* SD Write Protect? */
++#define CORGI_GPIO_nSD_DETECT		(9) /* MMC/SD Card Detect */
++#define CORGI_GPIO_nSD_INT			(10) /* SD Interrupt for SDIO? */
++#define CORGI_GPIO_MAIN_BAT_LOW		(11) /* Main Battery Low Notification */
++#define CORGI_GPIO_BAT_COVER		(11) /* Battery Cover Detect */
++#define CORGI_GPIO_LED_ORANGE		(13) /* Orange LED Control */
++#define CORGI_GPIO_CF_CD			(14) /* Compact Flash Card Detect */
++#define CORGI_GPIO_CHRG_FULL		(16) /* Charging Complete Notification */
++#define CORGI_GPIO_CF_IRQ			(17) /* Compact Flash Interrupt */
++#define CORGI_GPIO_LCDCON_CS		(19) /* LCD Control Chip Select */
++#define CORGI_GPIO_MAX1111_CS		(20) /* MAX1111 Chip Select */
++#define CORGI_GPIO_ADC_TEMP_ON		(21) /* Select battery voltage or temperature */
++#define CORGI_GPIO_IR_ON			(22) /* Enable IR Transciever */
++#define CORGI_GPIO_ADS7846_CS		(24) /* ADS7846 Chip Select */
++#define CORGI_GPIO_SD_PWR			(33) /* MMC/SD Power */
++#define CORGI_GPIO_CHRG_ON			(38) /* Enable battery Charging */
++#define CORGI_GPIO_DISCHARGE_ON		(42) /* Enable battery Discharge */
++#define CORGI_GPIO_CHRG_UKN			(43) /* Unknown Charging (Bypass Control?) */
++#define CORGI_GPIO_HSYNC			(44) /* LCD HSync Pulse */
++#define CORGI_GPIO_USB_PULLUP		(45) /* USB show presence to host */
++
++
++/*
++ * Corgi Keyboard Definitions
++ */
++#define CORGI_KEY_STROBE_NUM		(12)
++#define CORGI_KEY_SENSE_NUM			(8)
++#define CORGI_GPIO_ALL_STROBE_BIT	(0x00003ffc)
++#define CORGI_GPIO_HIGH_SENSE_BIT	(0xfc000000)
++#define CORGI_GPIO_HIGH_SENSE_RSHIFT	(26)
++#define CORGI_GPIO_LOW_SENSE_BIT	(0x00000003)
++#define CORGI_GPIO_LOW_SENSE_LSHIFT	(6)
++#define CORGI_GPIO_STROBE_BIT(a)	GPIO_bit(66+(a))
++#define CORGI_GPIO_SENSE_BIT(a)		GPIO_bit(58+(a))
++#define CORGI_GAFR_ALL_STROBE_BIT	(0x0ffffff0)
++#define CORGI_GAFR_HIGH_SENSE_BIT	(0xfff00000)
++#define CORGI_GAFR_LOW_SENSE_BIT	(0x0000000f)
++#define CORGI_GPIO_KEY_SENSE(a)		(58+(a))
++#define CORGI_GPIO_KEY_STROBE(a)	(66+(a))
++
++
++/*
++ * Corgi Interrupts
++ */
++#define CORGI_IRQ_GPIO_KEY_INT		IRQ_GPIO(0)
++#define CORGI_IRQ_GPIO_AC_IN		IRQ_GPIO(1)
++#define CORGI_IRQ_GPIO_WAKEUP		IRQ_GPIO(3)
++#define CORGI_IRQ_GPIO_AK_INT		IRQ_GPIO(4)
++#define CORGI_IRQ_GPIO_TP_INT		IRQ_GPIO(5)
++#define CORGI_IRQ_GPIO_nSD_DETECT	IRQ_GPIO(9)
++#define CORGI_IRQ_GPIO_nSD_INT		IRQ_GPIO(10)
++#define CORGI_IRQ_GPIO_MAIN_BAT_LOW	IRQ_GPIO(11)
++#define CORGI_IRQ_GPIO_CF_CD		IRQ_GPIO(14)
++#define CORGI_IRQ_GPIO_CHRG_FULL	IRQ_GPIO(16)	/* Battery fully charged */
++#define CORGI_IRQ_GPIO_CF_IRQ		IRQ_GPIO(17)
++#define CORGI_IRQ_GPIO_KEY_SENSE(a)	IRQ_GPIO(58+(a))	/* Keyboard Sense lines */
++
++
++/*
++ * Corgi SCOOP GPIOs and Config
++ */
++#define CORGI_SCP_LED_GREEN		SCOOP_GPCR_PA11
++#define CORGI_SCP_SWA			SCOOP_GPCR_PA12  /* Hinge Switch A */
++#define CORGI_SCP_SWB			SCOOP_GPCR_PA13  /* Hinge Switch B */
++#define CORGI_SCP_MUTE_L		SCOOP_GPCR_PA14
++#define CORGI_SCP_MUTE_R		SCOOP_GPCR_PA15
++#define CORGI_SCP_AKIN_PULLUP	SCOOP_GPCR_PA16
++#define CORGI_SCP_APM_ON		SCOOP_GPCR_PA17
++#define CORGI_SCP_BACKLIGHT_CONT	SCOOP_GPCR_PA18
++#define CORGI_SCP_MIC_BIAS		SCOOP_GPCR_PA19
++
++#define CORGI_SCOOP_IO_DIR	( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \
++			CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \
++			CORGI_SCP_MIC_BIAS )
++#define CORGI_SCOOP_IO_OUT	( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
++
++
++/*
++ * Shared data structures
++ */
++extern struct platform_device corgiscoop_device;
++extern struct platform_device corgissp_device;
++
++#endif /* __ASM_ARCH_CORGI_H  */
++
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/debug-macro.S linux-2.6.25-rc4/include/asm-arm/arch/debug-macro.S
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/debug-macro.S	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/debug-macro.S	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,25 @@
++/* linux/include/asm-arm/arch-pxa/debug-macro.S
++ *
++ * Debugging macro include header
++ *
++ *  Copyright (C) 1994-1999 Russell King
++ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include "hardware.h"
++
++		.macro	addruart,rx
++		mrc	p15, 0, \rx, c1, c0
++		tst	\rx, #1			@ MMU enabled?
++		moveq	\rx, #0x40000000		@ physical
++		movne	\rx, #io_p2v(0x40000000)	@ virtual
++		orr	\rx, \rx, #0x00100000
++		.endm
++
++#define UART_SHIFT	2
++#include <asm/hardware/debug-8250.S>
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/dma.h linux-2.6.25-rc4/include/asm-arm/arch/dma.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/dma.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/dma.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,50 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/dma.h
++ *
++ *  Author:	Nicolas Pitre
++ *  Created:	Jun 15, 2001
++ *  Copyright:	MontaVista Software, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __ASM_ARCH_DMA_H
++#define __ASM_ARCH_DMA_H
++
++/*
++ * Descriptor structure for PXA's DMA engine
++ * Note: this structure must always be aligned to a 16-byte boundary.
++ */
++
++typedef struct pxa_dma_desc {
++	volatile u32 ddadr;	/* Points to the next descriptor + flags */
++	volatile u32 dsadr;	/* DSADR value for the current transfer */
++	volatile u32 dtadr;	/* DTADR value for the current transfer */
++	volatile u32 dcmd;	/* DCMD value for the current transfer */
++} pxa_dma_desc;
++
++typedef enum {
++	DMA_PRIO_HIGH = 0,
++	DMA_PRIO_MEDIUM = 1,
++	DMA_PRIO_LOW = 2
++} pxa_dma_prio;
++
++#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
++#define HAVE_ARCH_PCI_SET_DMA_MASK	1
++#endif
++
++/*
++ * DMA registration
++ */
++
++int __init pxa_init_dma(int num_ch);
++
++int pxa_request_dma (char *name,
++			 pxa_dma_prio prio,
++			 void (*irq_handler)(int, void *),
++			 void *data);
++
++void pxa_free_dma (int dma_ch);
++
++#endif /* _ASM_ARCH_DMA_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/entry-macro.S linux-2.6.25-rc4/include/asm-arm/arch/entry-macro.S
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/entry-macro.S	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/entry-macro.S	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,57 @@
++/*
++ * include/asm-arm/arch-pxa/entry-macro.S
++ *
++ * Low-level IRQ helper macros for PXA-based platforms
++ *
++ * This file is licensed under  the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#include <asm/hardware.h>
++#include <asm/arch/irqs.h>
++
++		.macro	disable_fiq
++		.endm
++
++		.macro  get_irqnr_preamble, base, tmp
++		.endm
++
++		.macro  arch_ret_to_user, tmp1, tmp2
++		.endm
++
++		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
++		mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
++		mov	\tmp, \tmp, lsr #13
++		and	\tmp, \tmp, #0x7		@ Core G
++		cmp	\tmp, #1
++		bhi	1004f
++
++		mov	\base, #io_p2v(0x40000000)	@ IIR Ctl = 0x40d00000
++		add	\base, \base, #0x00d00000
++		ldr	\irqstat, [\base, #0]		@ ICIP
++		ldr	\irqnr, [\base, #4]		@ ICMR
++		b	1002f
++
++1004:
++		mrc	p6, 0, \irqstat, c6, c0, 0	@ ICIP2
++		mrc	p6, 0, \irqnr, c7, c0, 0	@ ICMR2
++		ands	\irqnr, \irqstat, \irqnr
++		beq	1003f
++		rsb	\irqstat, \irqnr, #0
++		and	\irqstat, \irqstat, \irqnr
++		clz	\irqnr, \irqstat
++		rsb	\irqnr, \irqnr, #31
++		add	\irqnr, \irqnr, #32
++		b	1001f
++1003:
++		mrc	p6, 0, \irqstat, c0, c0, 0	@ ICIP
++		mrc	p6, 0, \irqnr, c1, c0, 0	@ ICMR
++1002:
++		ands	\irqnr, \irqstat, \irqnr
++		beq	1001f
++		rsb	\irqstat, \irqnr, #0
++		and	\irqstat, \irqstat, \irqnr
++		clz	\irqnr, \irqstat
++		rsb	\irqnr, \irqnr, #31
++1001:
++		.endm
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/gpio.h linux-2.6.25-rc4/include/asm-arm/arch/gpio.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/gpio.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/gpio.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,65 @@
++/*
++ * linux/include/asm-arm/arch-pxa/gpio.h
++ *
++ * PXA GPIO wrappers for arch-neutral GPIO calls
++ *
++ * Written by Philipp Zabel <philipp.zabel@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#ifndef __ASM_ARCH_PXA_GPIO_H
++#define __ASM_ARCH_PXA_GPIO_H
++
++#include <asm/arch/pxa-regs.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++
++#include <asm-generic/gpio.h>
++
++
++/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
++ * Those cases currently cause holes in the GPIO number space.
++ */
++#define NR_BUILTIN_GPIO 128
++
++static inline int gpio_get_value(unsigned gpio)
++{
++	if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
++		return GPLR(gpio) & GPIO_bit(gpio);
++	else
++		return __gpio_get_value(gpio);
++}
++
++static inline void gpio_set_value(unsigned gpio, int value)
++{
++	if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
++		if (value)
++			GPSR(gpio) = GPIO_bit(gpio);
++		else
++			GPCR(gpio) = GPIO_bit(gpio);
++	} else {
++		__gpio_set_value(gpio, value);
++	}
++}
++
++#define gpio_cansleep __gpio_cansleep
++
++#define gpio_to_irq(gpio)	IRQ_GPIO(gpio)
++#define irq_to_gpio(irq)	IRQ_TO_GPIO(irq)
++
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/hardware.h linux-2.6.25-rc4/include/asm-arm/arch/hardware.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/hardware.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/hardware.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,216 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/hardware.h
++ *
++ *  Author:	Nicolas Pitre
++ *  Created:	Jun 15, 2001
++ *  Copyright:	MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_HARDWARE_H
++#define __ASM_ARCH_HARDWARE_H
++
++/*
++ * We requires absolute addresses.
++ */
++#define PCIO_BASE		0
++
++/*
++ * Workarounds for at least 2 errata so far require this.
++ * The mapping is set in mach-pxa/generic.c.
++ */
++#define UNCACHED_PHYS_0		0xff000000
++#define UNCACHED_ADDR		UNCACHED_PHYS_0
++
++/*
++ * Intel PXA2xx internal register mapping:
++ *
++ * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
++ * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
++ * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
++ * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
++ * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
++ * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
++ * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
++ *
++ * Note that not all PXA2xx chips implement all those addresses, and the
++ * kernel only maps the minimum needed range of this mapping.
++ */
++#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
++#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
++
++#ifndef __ASSEMBLY__
++
++# define __REG(x)	(*((volatile u32 *)io_p2v(x)))
++
++/* With indexed regs we don't want to feed the index through io_p2v()
++   especially if it is a variable, otherwise horrible code will result. */
++# define __REG2(x,y)	\
++	(*(volatile u32 *)((u32)&__REG(x) + (y)))
++
++# define __PREG(x)	(io_v2p((u32)&(x)))
++
++#else
++
++# define __REG(x)	io_p2v(x)
++# define __PREG(x)	io_v2p(x)
++
++#endif
++
++#ifndef __ASSEMBLY__
++
++#ifdef CONFIG_PXA25x
++#define __cpu_is_pxa21x(id)				\
++	({						\
++		unsigned int _id = (id) >> 4 & 0xf3f;	\
++		_id == 0x212;				\
++	})
++
++#define __cpu_is_pxa25x(id)				\
++	({						\
++		unsigned int _id = (id) >> 4 & 0xfff;	\
++		_id == 0x2d0 || _id == 0x290;		\
++	})
++#else
++#define __cpu_is_pxa21x(id)	(0)
++#define __cpu_is_pxa25x(id)	(0)
++#endif
++
++#ifdef CONFIG_PXA27x
++#define __cpu_is_pxa27x(id)				\
++	({						\
++		unsigned int _id = (id) >> 4 & 0xfff;	\
++		_id == 0x411;				\
++	})
++#else
++#define __cpu_is_pxa27x(id)	(0)
++#endif
++
++#ifdef CONFIG_CPU_PXA300
++#define __cpu_is_pxa300(id)				\
++	({						\
++		unsigned int _id = (id) >> 4 & 0xfff;	\
++		_id == 0x688;				\
++	 })
++#else
++#define __cpu_is_pxa300(id)	(0)
++#endif
++
++#ifdef CONFIG_CPU_PXA310
++#define __cpu_is_pxa310(id)				\
++	({						\
++		unsigned int _id = (id) >> 4 & 0xfff;	\
++		_id == 0x689;				\
++	 })
++#else
++#define __cpu_is_pxa310(id)	(0)
++#endif
++
++#ifdef CONFIG_CPU_PXA320
++#define __cpu_is_pxa320(id)				\
++	({						\
++		unsigned int _id = (id) >> 4 & 0xfff;	\
++		_id == 0x603 || _id == 0x682;		\
++	 })
++#else
++#define __cpu_is_pxa320(id)	(0)
++#endif
++
++#define cpu_is_pxa21x()					\
++	({						\
++		__cpu_is_pxa21x(read_cpuid_id());	\
++	})
++
++#define cpu_is_pxa25x()					\
++	({						\
++		__cpu_is_pxa25x(read_cpuid_id());	\
++	})
++
++#define cpu_is_pxa27x()					\
++	({						\
++		__cpu_is_pxa27x(read_cpuid_id());	\
++	})
++
++#define cpu_is_pxa300()					\
++	({						\
++		__cpu_is_pxa300(read_cpuid_id());	\
++	 })
++
++#define cpu_is_pxa310()					\
++	({						\
++		__cpu_is_pxa310(read_cpuid_id());	\
++	 })
++
++#define cpu_is_pxa320()					\
++	({						\
++		__cpu_is_pxa320(read_cpuid_id());	\
++	 })
++
++/*
++ * CPUID Core Generation Bit
++ * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
++ * == 0x3 for pxa300/pxa310/pxa320
++ */
++#define __cpu_is_pxa2xx(id)				\
++	({						\
++		unsigned int _id = (id) >> 13 & 0x7;	\
++		_id <= 0x2;				\
++	 })
++
++#define __cpu_is_pxa3xx(id)				\
++	({						\
++		unsigned int _id = (id) >> 13 & 0x7;	\
++		_id == 0x3;				\
++	 })
++
++#define cpu_is_pxa2xx()					\
++	({						\
++		__cpu_is_pxa2xx(read_cpuid_id());	\
++	 })
++
++#define cpu_is_pxa3xx()					\
++	({						\
++		__cpu_is_pxa3xx(read_cpuid_id());	\
++	 })
++
++/*
++ * Handy routine to set GPIO alternate functions
++ */
++extern int pxa_gpio_mode( int gpio_mode );
++
++/*
++ * Return GPIO level, nonzero means high, zero is low
++ */
++extern int pxa_gpio_get_value(unsigned gpio);
++
++/*
++ * Set output GPIO level
++ */
++extern void pxa_gpio_set_value(unsigned gpio, int value);
++
++/*
++ * Routine to enable or disable CKEN
++ */
++static inline void __deprecated pxa_set_cken(int clock, int enable)
++{
++	extern void __pxa_set_cken(int clock, int enable);
++	__pxa_set_cken(clock, enable);
++}
++
++/*
++ * return current memory and LCD clock frequency in units of 10kHz
++ */
++extern unsigned int get_memclk_frequency_10khz(void);
++
++#endif
++
++#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
++#define PCIBIOS_MIN_IO		0
++#define PCIBIOS_MIN_MEM		0
++#define pcibios_assign_all_busses()	1
++#endif
++
++#endif  /* _ASM_ARCH_HARDWARE_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/i2c.h linux-2.6.25-rc4/include/asm-arm/arch/i2c.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/i2c.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/i2c.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,77 @@
++/*
++ *  i2c_pxa.h
++ *
++ *  Copyright (C) 2002 Intrinsyc Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation.
++ *
++ */
++#ifndef _I2C_PXA_H_
++#define _I2C_PXA_H_
++
++#if 0
++#define DEF_TIMEOUT             3
++#else
++/* need a longer timeout if we're dealing with the fact we may well be
++ * looking at a multi-master environment
++*/
++#define DEF_TIMEOUT             32
++#endif
++
++#define BUS_ERROR               (-EREMOTEIO)
++#define XFER_NAKED              (-ECONNREFUSED)
++#define I2C_RETRY               (-2000) /* an error has occurred retry transmit */
++
++/* ICR initialize bit values
++*
++*  15. FM       0 (100 Khz operation)
++*  14. UR       0 (No unit reset)
++*  13. SADIE    0 (Disables the unit from interrupting on slave addresses
++*                                       matching its slave address)
++*  12. ALDIE    0 (Disables the unit from interrupt when it loses arbitration
++*                                       in master mode)
++*  11. SSDIE    0 (Disables interrupts from a slave stop detected, in slave mode)
++*  10. BEIE     1 (Enable interrupts from detected bus errors, no ACK sent)
++*  9.  IRFIE    1 (Enable interrupts from full buffer received)
++*  8.  ITEIE    1 (Enables the I2C unit to interrupt when transmit buffer empty)
++*  7.  GCD      1 (Disables i2c unit response to general call messages as a slave)
++*  6.  IUE      0 (Disable unit until we change settings)
++*  5.  SCLE     1 (Enables the i2c clock output for master mode (drives SCL)
++*  4.  MA       0 (Only send stop with the ICR stop bit)
++*  3.  TB       0 (We are not transmitting a byte initially)
++*  2.  ACKNAK   0 (Send an ACK after the unit receives a byte)
++*  1.  STOP     0 (Do not send a STOP)
++*  0.  START    0 (Do not send a START)
++*
++*/
++#define I2C_ICR_INIT	(ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
++
++/* I2C status register init values
++ *
++ * 10. BED      1 (Clear bus error detected)
++ * 9.  SAD      1 (Clear slave address detected)
++ * 7.  IRF      1 (Clear IDBR Receive Full)
++ * 6.  ITE      1 (Clear IDBR Transmit Empty)
++ * 5.  ALD      1 (Clear Arbitration Loss Detected)
++ * 4.  SSD      1 (Clear Slave Stop Detected)
++ */
++#define I2C_ISR_INIT	0x7FF  /* status register init */
++
++struct i2c_slave_client;
++
++struct i2c_pxa_platform_data {
++	unsigned int		slave_addr;
++	struct i2c_slave_client	*slave;
++	unsigned int		class;
++	int			use_pio;
++};
++
++extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
++
++#ifdef CONFIG_PXA27x
++extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info);
++#endif
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/idp.h linux-2.6.25-rc4/include/asm-arm/arch/idp.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/idp.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/idp.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,199 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/idp.h
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
++ *
++ * 2001-09-13: Cliff Brake <cbrake@accelent.com>
++ *             Initial code
++ *
++ * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
++ *             <http://www.vibren.com> <http://bec-systems.com>
++ *             Changes for 2.6 kernel.
++ */
++
++
++/*
++ * Note: this file must be safe to include in assembly files
++ *
++ * Support for the Vibren PXA255 IDP requires rev04 or later
++ * IDP hardware.
++ */
++
++
++#define IDP_FLASH_PHYS		(PXA_CS0_PHYS)
++#define IDP_ALT_FLASH_PHYS	(PXA_CS1_PHYS)
++#define IDP_MEDIAQ_PHYS		(PXA_CS3_PHYS)
++#define IDP_IDE_PHYS		(PXA_CS5_PHYS + 0x03000000)
++#define IDP_ETH_PHYS		(PXA_CS5_PHYS + 0x03400000)
++#define IDP_COREVOLT_PHYS	(PXA_CS5_PHYS + 0x03800000)
++#define IDP_CPLD_PHYS		(PXA_CS5_PHYS + 0x03C00000)
++
++
++/*
++ * virtual memory map
++ */
++
++#define IDP_COREVOLT_VIRT	(0xf0000000)
++#define IDP_COREVOLT_SIZE	(1*1024*1024)
++
++#define IDP_CPLD_VIRT		(IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
++#define IDP_CPLD_SIZE		(1*1024*1024)
++
++#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
++#error Your custom IO space is getting a bit large !!
++#endif
++
++#define CPLD_P2V(x)		((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
++#define CPLD_V2P(x)		((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
++
++#ifndef __ASSEMBLY__
++#  define __CPLD_REG(x)		(*((volatile unsigned long *)CPLD_P2V(x)))
++#else
++#  define __CPLD_REG(x)		CPLD_P2V(x)
++#endif
++
++/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
++
++#define _IDP_CPLD_REV			(IDP_CPLD_PHYS + 0x00)
++#define _IDP_CPLD_PERIPH_PWR		(IDP_CPLD_PHYS + 0x04)
++#define _IDP_CPLD_LED_CONTROL		(IDP_CPLD_PHYS + 0x08)
++#define _IDP_CPLD_KB_COL_HIGH		(IDP_CPLD_PHYS + 0x0C)
++#define _IDP_CPLD_KB_COL_LOW		(IDP_CPLD_PHYS + 0x10)
++#define _IDP_CPLD_PCCARD_EN		(IDP_CPLD_PHYS + 0x14)
++#define _IDP_CPLD_GPIOH_DIR		(IDP_CPLD_PHYS + 0x18)
++#define _IDP_CPLD_GPIOH_VALUE		(IDP_CPLD_PHYS + 0x1C)
++#define _IDP_CPLD_GPIOL_DIR		(IDP_CPLD_PHYS + 0x20)
++#define _IDP_CPLD_GPIOL_VALUE		(IDP_CPLD_PHYS + 0x24)
++#define _IDP_CPLD_PCCARD_PWR		(IDP_CPLD_PHYS + 0x28)
++#define _IDP_CPLD_MISC_CTRL		(IDP_CPLD_PHYS + 0x2C)
++#define _IDP_CPLD_LCD			(IDP_CPLD_PHYS + 0x30)
++#define _IDP_CPLD_FLASH_WE		(IDP_CPLD_PHYS + 0x34)
++
++#define _IDP_CPLD_KB_ROW		(IDP_CPLD_PHYS + 0x50)
++#define _IDP_CPLD_PCCARD0_STATUS	(IDP_CPLD_PHYS + 0x54)
++#define _IDP_CPLD_PCCARD1_STATUS	(IDP_CPLD_PHYS + 0x58)
++#define _IDP_CPLD_MISC_STATUS		(IDP_CPLD_PHYS + 0x5C)
++
++/* FPGA register virtual addresses */
++
++#define IDP_CPLD_REV			__CPLD_REG(_IDP_CPLD_REV)
++#define IDP_CPLD_PERIPH_PWR		__CPLD_REG(_IDP_CPLD_PERIPH_PWR)
++#define IDP_CPLD_LED_CONTROL		__CPLD_REG(_IDP_CPLD_LED_CONTROL)
++#define IDP_CPLD_KB_COL_HIGH		__CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
++#define IDP_CPLD_KB_COL_LOW		__CPLD_REG(_IDP_CPLD_KB_COL_LOW)
++#define IDP_CPLD_PCCARD_EN		__CPLD_REG(_IDP_CPLD_PCCARD_EN)
++#define IDP_CPLD_GPIOH_DIR		__CPLD_REG(_IDP_CPLD_GPIOH_DIR)
++#define IDP_CPLD_GPIOH_VALUE		__CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
++#define IDP_CPLD_GPIOL_DIR		__CPLD_REG(_IDP_CPLD_GPIOL_DIR)
++#define IDP_CPLD_GPIOL_VALUE		__CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
++#define IDP_CPLD_PCCARD_PWR		__CPLD_REG(_IDP_CPLD_PCCARD_PWR)
++#define IDP_CPLD_MISC_CTRL		__CPLD_REG(_IDP_CPLD_MISC_CTRL)
++#define IDP_CPLD_LCD			__CPLD_REG(_IDP_CPLD_LCD)
++#define IDP_CPLD_FLASH_WE		__CPLD_REG(_IDP_CPLD_FLASH_WE)
++
++#define IDP_CPLD_KB_ROW		        __CPLD_REG(_IDP_CPLD_KB_ROW)
++#define IDP_CPLD_PCCARD0_STATUS	        __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
++#define IDP_CPLD_PCCARD1_STATUS	        __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
++#define IDP_CPLD_MISC_STATUS		__CPLD_REG(_IDP_CPLD_MISC_STATUS)
++
++
++/*
++ * Bit masks for various registers
++ */
++
++// IDP_CPLD_PCCARD_PWR
++#define PCC0_PWR0	(1 << 0)
++#define PCC0_PWR1	(1 << 1)
++#define PCC0_PWR2	(1 << 2)
++#define PCC0_PWR3	(1 << 3)
++#define PCC1_PWR0	(1 << 4)
++#define PCC1_PWR1	(1 << 5)
++#define PCC1_PWR2	(1 << 6)
++#define PCC1_PWR3	(1 << 7)
++
++// IDP_CPLD_PCCARD_EN
++#define PCC0_RESET	(1 << 6)
++#define PCC1_RESET	(1 << 7)
++#define PCC0_ENABLE	(1 << 0)
++#define PCC1_ENABLE	(1 << 1)
++
++// IDP_CPLD_PCCARDx_STATUS
++#define _PCC_WRPROT	(1 << 7) // 7-4 read as low true
++#define _PCC_RESET	(1 << 6)
++#define _PCC_IRQ	(1 << 5)
++#define _PCC_INPACK	(1 << 4)
++#define PCC_BVD2	(1 << 3)
++#define PCC_BVD1	(1 << 2)
++#define PCC_VS2		(1 << 1)
++#define PCC_VS1		(1 << 0)
++
++#define PCC_DETECT(x)	(GPLR(7 + (x)) & GPIO_bit(7 + (x)))
++
++/* A listing of interrupts used by external hardware devices */
++
++#define TOUCH_PANEL_IRQ			IRQ_GPIO(5)
++#define IDE_IRQ				IRQ_GPIO(21)
++
++#define TOUCH_PANEL_IRQ_EDGE		IRQT_FALLING
++
++#define ETHERNET_IRQ			IRQ_GPIO(4)
++#define ETHERNET_IRQ_EDGE		IRQT_RISING
++
++#define IDE_IRQ_EDGE			IRQT_RISING
++
++#define PCMCIA_S0_CD_VALID		IRQ_GPIO(7)
++#define PCMCIA_S0_CD_VALID_EDGE		IRQT_BOTHEDGE
++
++#define PCMCIA_S1_CD_VALID		IRQ_GPIO(8)
++#define PCMCIA_S1_CD_VALID_EDGE		IRQT_BOTHEDGE
++
++#define PCMCIA_S0_RDYINT		IRQ_GPIO(19)
++#define PCMCIA_S1_RDYINT		IRQ_GPIO(22)
++
++
++/*
++ * Macros for LED Driver
++ */
++
++/* leds 0 = ON */
++#define IDP_HB_LED	(1<<5)
++#define IDP_BUSY_LED	(1<<6)
++
++#define IDP_LEDS_MASK	(IDP_HB_LED | IDP_BUSY_LED)
++
++/*
++ * macros for MTD driver
++ */
++
++#define FLASH_WRITE_PROTECT_DISABLE()	((IDP_CPLD_FLASH_WE) &= ~(0x1))
++#define FLASH_WRITE_PROTECT_ENABLE()	((IDP_CPLD_FLASH_WE) |= (0x1))
++
++/*
++ * macros for matrix keyboard driver
++ */
++
++#define KEYBD_MATRIX_NUMBER_INPUTS	7
++#define KEYBD_MATRIX_NUMBER_OUTPUTS	14
++
++#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC	FALSE
++#define KEYBD_MATRIX_INVERT_INPUT_LOGIC		FALSE
++
++#define KEYBD_MATRIX_SETTLING_TIME_US			100
++#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT		2
++
++#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
++{\
++	IDP_CPLD_KB_COL_LOW = outputs;\
++	IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
++}
++
++#define KEYBD_MATRIX_GET_INPUTS(inputs) \
++{\
++	inputs = (IDP_CPLD_KB_ROW & 0x7f);\
++}
++
++
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/io.h linux-2.6.25-rc4/include/asm-arm/arch/io.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/io.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/io.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,20 @@
++/*
++ * linux/include/asm-arm/arch-pxa/io.h
++ *
++ * Copied from asm/arch/sa1100/io.h
++ */
++#ifndef __ASM_ARM_ARCH_IO_H
++#define __ASM_ARM_ARCH_IO_H
++
++#include <asm/hardware.h>
++
++#define IO_SPACE_LIMIT 0xffffffff
++
++/*
++ * We don't actually have real ISA nor PCI buses, but there is so many
++ * drivers out there that might just work if we fake them...
++ */
++#define __io(a)			((void __iomem *)(a))
++#define __mem_pci(a)		(a)
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/irda.h linux-2.6.25-rc4/include/asm-arm/arch/irda.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/irda.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/irda.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,17 @@
++#ifndef ASMARM_ARCH_IRDA_H
++#define ASMARM_ARCH_IRDA_H
++
++/* board specific transceiver capabilities */
++
++#define IR_OFF		1
++#define IR_SIRMODE	2
++#define IR_FIRMODE	4
++
++struct pxaficp_platform_data {
++	int transceiver_cap;
++	void (*transceiver_mode)(struct device *dev, int mode);
++};
++
++extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/irqs.h linux-2.6.25-rc4/include/asm-arm/arch/irqs.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/irqs.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/irqs.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,257 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/irqs.h
++ *
++ *  Author:	Nicolas Pitre
++ *  Created:	Jun 15, 2001
++ *  Copyright:	MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++#define PXA_IRQ(x)	(x)
++
++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
++#define IRQ_SSP3	PXA_IRQ(0)	/* SSP3 service request */
++#define IRQ_MSL		PXA_IRQ(1)	/* MSL Interface interrupt */
++#define IRQ_USBH2	PXA_IRQ(2)	/* USB Host interrupt 1 (OHCI) */
++#define IRQ_USBH1	PXA_IRQ(3)	/* USB Host interrupt 2 (non-OHCI) */
++#define IRQ_KEYPAD	PXA_IRQ(4)	/* Key pad controller */
++#define IRQ_MEMSTK	PXA_IRQ(5)	/* Memory Stick interrupt */
++#define IRQ_PWRI2C	PXA_IRQ(6)	/* Power I2C interrupt */
++#endif
++
++#define IRQ_HWUART	PXA_IRQ(7)	/* HWUART Transmit/Receive/Error (PXA26x) */
++#define IRQ_OST_4_11	PXA_IRQ(7)	/* OS timer 4-11 matches (PXA27x) */
++#define	IRQ_GPIO0	PXA_IRQ(8)	/* GPIO0 Edge Detect */
++#define	IRQ_GPIO1	PXA_IRQ(9)	/* GPIO1 Edge Detect */
++#define	IRQ_GPIO_2_x	PXA_IRQ(10)	/* GPIO[2-x] Edge Detect */
++#define	IRQ_USB		PXA_IRQ(11)	/* USB Service */
++#define	IRQ_PMU		PXA_IRQ(12)	/* Performance Monitoring Unit */
++#define	IRQ_I2S		PXA_IRQ(13)	/* I2S Interrupt */
++#define	IRQ_AC97	PXA_IRQ(14)	/* AC97 Interrupt */
++#define IRQ_ASSP	PXA_IRQ(15)	/* Audio SSP Service Request (PXA25x) */
++#define IRQ_USIM	PXA_IRQ(15)     /* Smart Card interface interrupt (PXA27x) */
++#define IRQ_NSSP	PXA_IRQ(16)	/* Network SSP Service Request (PXA25x) */
++#define IRQ_SSP2	PXA_IRQ(16)	/* SSP2 interrupt (PXA27x) */
++#define	IRQ_LCD		PXA_IRQ(17)	/* LCD Controller Service Request */
++#define	IRQ_I2C		PXA_IRQ(18)	/* I2C Service Request */
++#define	IRQ_ICP		PXA_IRQ(19)	/* ICP Transmit/Receive/Error */
++#define	IRQ_STUART	PXA_IRQ(20)	/* STUART Transmit/Receive/Error */
++#define	IRQ_BTUART	PXA_IRQ(21)	/* BTUART Transmit/Receive/Error */
++#define	IRQ_FFUART	PXA_IRQ(22)	/* FFUART Transmit/Receive/Error*/
++#define	IRQ_MMC		PXA_IRQ(23)	/* MMC Status/Error Detection */
++#define	IRQ_SSP		PXA_IRQ(24)	/* SSP Service Request */
++#define	IRQ_DMA 	PXA_IRQ(25)	/* DMA Channel Service Request */
++#define	IRQ_OST0 	PXA_IRQ(26)	/* OS Timer match 0 */
++#define	IRQ_OST1 	PXA_IRQ(27)	/* OS Timer match 1 */
++#define	IRQ_OST2 	PXA_IRQ(28)	/* OS Timer match 2 */
++#define	IRQ_OST3 	PXA_IRQ(29)	/* OS Timer match 3 */
++#define	IRQ_RTC1Hz	PXA_IRQ(30)	/* RTC HZ Clock Tick */
++#define	IRQ_RTCAlrm	PXA_IRQ(31)	/* RTC Alarm */
++
++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
++#define IRQ_TPM		PXA_IRQ(32)	/* TPM interrupt */
++#define IRQ_CAMERA	PXA_IRQ(33)	/* Camera Interface */
++#endif
++
++#ifdef CONFIG_PXA3xx
++#define IRQ_SSP4	PXA_IRQ(13)	/* SSP4 service request */
++#define IRQ_CIR		PXA_IRQ(34)	/* Consumer IR */
++#define IRQ_TSI		PXA_IRQ(36)	/* Touch Screen Interface (PXA320) */
++#define IRQ_USIM2	PXA_IRQ(38)	/* USIM2 Controller */
++#define IRQ_GRPHICS	PXA_IRQ(39)	/* Graphics Controller */
++#define IRQ_MMC2	PXA_IRQ(41)	/* MMC2 Controller */
++#define IRQ_1WIRE	PXA_IRQ(44)	/* 1-Wire Controller */
++#define IRQ_NAND	PXA_IRQ(45)	/* NAND Controller */
++#define IRQ_USB2	PXA_IRQ(46)	/* USB 2.0 Device Controller */
++#define IRQ_WAKEUP0	PXA_IRQ(49)	/* EXT_WAKEUP0 */
++#define IRQ_WAKEUP1	PXA_IRQ(50)	/* EXT_WAKEUP1 */
++#define IRQ_DMEMC	PXA_IRQ(51)	/* Dynamic Memory Controller */
++#define IRQ_MMC3	PXA_IRQ(55)	/* MMC3 Controller (PXA310) */
++#endif
++
++#define PXA_GPIO_IRQ_BASE	(64)
++#define PXA_GPIO_IRQ_NUM	(128)
++
++#define GPIO_2_x_TO_IRQ(x)	(PXA_GPIO_IRQ_BASE + (x))
++#define IRQ_GPIO(x)	(((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
++
++#define IRQ_TO_GPIO_2_x(i)	((i) - PXA_GPIO_IRQ_BASE)
++#define IRQ_TO_GPIO(i)	(((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
++
++/*
++ * The next 16 interrupts are for board specific purposes.  Since
++ * the kernel can only run on one machine at a time, we can re-use
++ * these.  If you need more, increase IRQ_BOARD_END, but keep it
++ * within sensible limits.
++ */
++#define IRQ_BOARD_START		(PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
++#define IRQ_BOARD_END		(IRQ_BOARD_START + 16)
++
++#define IRQ_SA1111_START	(IRQ_BOARD_END)
++#define IRQ_GPAIN0		(IRQ_BOARD_END + 0)
++#define IRQ_GPAIN1		(IRQ_BOARD_END + 1)
++#define IRQ_GPAIN2		(IRQ_BOARD_END + 2)
++#define IRQ_GPAIN3		(IRQ_BOARD_END + 3)
++#define IRQ_GPBIN0		(IRQ_BOARD_END + 4)
++#define IRQ_GPBIN1		(IRQ_BOARD_END + 5)
++#define IRQ_GPBIN2		(IRQ_BOARD_END + 6)
++#define IRQ_GPBIN3		(IRQ_BOARD_END + 7)
++#define IRQ_GPBIN4		(IRQ_BOARD_END + 8)
++#define IRQ_GPBIN5		(IRQ_BOARD_END + 9)
++#define IRQ_GPCIN0		(IRQ_BOARD_END + 10)
++#define IRQ_GPCIN1		(IRQ_BOARD_END + 11)
++#define IRQ_GPCIN2		(IRQ_BOARD_END + 12)
++#define IRQ_GPCIN3		(IRQ_BOARD_END + 13)
++#define IRQ_GPCIN4		(IRQ_BOARD_END + 14)
++#define IRQ_GPCIN5		(IRQ_BOARD_END + 15)
++#define IRQ_GPCIN6		(IRQ_BOARD_END + 16)
++#define IRQ_GPCIN7		(IRQ_BOARD_END + 17)
++#define IRQ_MSTXINT		(IRQ_BOARD_END + 18)
++#define IRQ_MSRXINT		(IRQ_BOARD_END + 19)
++#define IRQ_MSSTOPERRINT	(IRQ_BOARD_END + 20)
++#define IRQ_TPTXINT		(IRQ_BOARD_END + 21)
++#define IRQ_TPRXINT		(IRQ_BOARD_END + 22)
++#define IRQ_TPSTOPERRINT	(IRQ_BOARD_END + 23)
++#define SSPXMTINT		(IRQ_BOARD_END + 24)
++#define SSPRCVINT		(IRQ_BOARD_END + 25)
++#define SSPROR			(IRQ_BOARD_END + 26)
++#define AUDXMTDMADONEA		(IRQ_BOARD_END + 32)
++#define AUDRCVDMADONEA		(IRQ_BOARD_END + 33)
++#define AUDXMTDMADONEB		(IRQ_BOARD_END + 34)
++#define AUDRCVDMADONEB		(IRQ_BOARD_END + 35)
++#define AUDTFSR			(IRQ_BOARD_END + 36)
++#define AUDRFSR			(IRQ_BOARD_END + 37)
++#define AUDTUR			(IRQ_BOARD_END + 38)
++#define AUDROR			(IRQ_BOARD_END + 39)
++#define AUDDTS			(IRQ_BOARD_END + 40)
++#define AUDRDD			(IRQ_BOARD_END + 41)
++#define AUDSTO			(IRQ_BOARD_END + 42)
++#define IRQ_USBPWR		(IRQ_BOARD_END + 43)
++#define IRQ_HCIM		(IRQ_BOARD_END + 44)
++#define IRQ_HCIBUFFACC		(IRQ_BOARD_END + 45)
++#define IRQ_HCIRMTWKP		(IRQ_BOARD_END + 46)
++#define IRQ_NHCIMFCIR		(IRQ_BOARD_END + 47)
++#define IRQ_USB_PORT_RESUME	(IRQ_BOARD_END + 48)
++#define IRQ_S0_READY_NINT	(IRQ_BOARD_END + 49)
++#define IRQ_S1_READY_NINT	(IRQ_BOARD_END + 50)
++#define IRQ_S0_CD_VALID		(IRQ_BOARD_END + 51)
++#define IRQ_S1_CD_VALID		(IRQ_BOARD_END + 52)
++#define IRQ_S0_BVD1_STSCHG	(IRQ_BOARD_END + 53)
++#define IRQ_S1_BVD1_STSCHG	(IRQ_BOARD_END + 54)
++
++#define IRQ_LOCOMO_START	(IRQ_BOARD_END)
++#define IRQ_LOCOMO_KEY		(IRQ_BOARD_END + 0)
++#define IRQ_LOCOMO_GPIO0	(IRQ_BOARD_END + 1)
++#define IRQ_LOCOMO_GPIO1	(IRQ_BOARD_END + 2)
++#define IRQ_LOCOMO_GPIO2	(IRQ_BOARD_END + 3)
++#define IRQ_LOCOMO_GPIO3	(IRQ_BOARD_END + 4)
++#define IRQ_LOCOMO_GPIO4	(IRQ_BOARD_END + 5)
++#define IRQ_LOCOMO_GPIO5	(IRQ_BOARD_END + 6)
++#define IRQ_LOCOMO_GPIO6	(IRQ_BOARD_END + 7)
++#define IRQ_LOCOMO_GPIO7	(IRQ_BOARD_END + 8)
++#define IRQ_LOCOMO_GPIO8	(IRQ_BOARD_END + 9)
++#define IRQ_LOCOMO_GPIO9	(IRQ_BOARD_END + 10)
++#define IRQ_LOCOMO_GPIO10	(IRQ_BOARD_END + 11)
++#define IRQ_LOCOMO_GPIO11	(IRQ_BOARD_END + 12)
++#define IRQ_LOCOMO_GPIO12	(IRQ_BOARD_END + 13)
++#define IRQ_LOCOMO_GPIO13	(IRQ_BOARD_END + 14)
++#define IRQ_LOCOMO_GPIO14	(IRQ_BOARD_END + 15)
++#define IRQ_LOCOMO_GPIO15	(IRQ_BOARD_END + 16)
++#define IRQ_LOCOMO_LT		(IRQ_BOARD_END + 17)
++#define IRQ_LOCOMO_SPI_RFR	(IRQ_BOARD_END + 18)
++#define IRQ_LOCOMO_SPI_RFW	(IRQ_BOARD_END + 19)
++#define IRQ_LOCOMO_SPI_OVRN	(IRQ_BOARD_END + 20)
++#define IRQ_LOCOMO_SPI_TEND	(IRQ_BOARD_END + 21)
++
++/*
++ * Figure out the MAX IRQ number.
++ *
++ * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
++ * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
++ * Otherwise, we have the standard IRQs only.
++ */
++#ifdef CONFIG_SA1111
++#define NR_IRQS			(IRQ_S1_BVD1_STSCHG + 1)
++#elif defined(CONFIG_SHARP_LOCOMO)
++#define NR_IRQS			(IRQ_LOCOMO_SPI_TEND + 1)
++#elif defined(CONFIG_ARCH_LUBBOCK) || \
++      defined(CONFIG_MACH_LOGICPD_PXA270) || \
++      defined(CONFIG_MACH_MAINSTONE) || \
++      defined(CONFIG_MACH_PCM027)
++#define NR_IRQS			(IRQ_BOARD_END)
++#else
++#define NR_IRQS			(IRQ_BOARD_START)
++#endif
++
++/*
++ * Board specific IRQs.  Define them here.
++ * Do not surround them with ifdefs.
++ */
++#define LUBBOCK_IRQ(x)		(IRQ_BOARD_START + (x))
++#define LUBBOCK_SD_IRQ		LUBBOCK_IRQ(0)
++#define LUBBOCK_SA1111_IRQ	LUBBOCK_IRQ(1)
++#define LUBBOCK_USB_IRQ		LUBBOCK_IRQ(2)  /* usb connect */
++#define LUBBOCK_ETH_IRQ		LUBBOCK_IRQ(3)
++#define LUBBOCK_UCB1400_IRQ	LUBBOCK_IRQ(4)
++#define LUBBOCK_BB_IRQ		LUBBOCK_IRQ(5)
++#define LUBBOCK_USB_DISC_IRQ	LUBBOCK_IRQ(6)  /* usb disconnect */
++#define LUBBOCK_LAST_IRQ	LUBBOCK_IRQ(6)
++
++#define LPD270_IRQ(x)		(IRQ_BOARD_START + (x))
++#define LPD270_USBC_IRQ		LPD270_IRQ(2)
++#define LPD270_ETHERNET_IRQ	LPD270_IRQ(3)
++#define LPD270_AC97_IRQ		LPD270_IRQ(4)
++
++#define MAINSTONE_IRQ(x)	(IRQ_BOARD_START + (x))
++#define MAINSTONE_MMC_IRQ	MAINSTONE_IRQ(0)
++#define MAINSTONE_USIM_IRQ	MAINSTONE_IRQ(1)
++#define MAINSTONE_USBC_IRQ	MAINSTONE_IRQ(2)
++#define MAINSTONE_ETHERNET_IRQ	MAINSTONE_IRQ(3)
++#define MAINSTONE_AC97_IRQ	MAINSTONE_IRQ(4)
++#define MAINSTONE_PEN_IRQ	MAINSTONE_IRQ(5)
++#define MAINSTONE_MSINS_IRQ	MAINSTONE_IRQ(6)
++#define MAINSTONE_EXBRD_IRQ	MAINSTONE_IRQ(7)
++#define MAINSTONE_S0_CD_IRQ	MAINSTONE_IRQ(9)
++#define MAINSTONE_S0_STSCHG_IRQ	MAINSTONE_IRQ(10)
++#define MAINSTONE_S0_IRQ	MAINSTONE_IRQ(11)
++#define MAINSTONE_S1_CD_IRQ	MAINSTONE_IRQ(13)
++#define MAINSTONE_S1_STSCHG_IRQ	MAINSTONE_IRQ(14)
++#define MAINSTONE_S1_IRQ	MAINSTONE_IRQ(15)
++
++/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
++#define IRQ_LOCOMO_KEY_BASE	(IRQ_BOARD_START + 0)
++#define IRQ_LOCOMO_GPIO_BASE	(IRQ_BOARD_START + 1)
++#define IRQ_LOCOMO_LT_BASE	(IRQ_BOARD_START + 2)
++#define IRQ_LOCOMO_SPI_BASE	(IRQ_BOARD_START + 3)
++
++/* phyCORE-PXA270 (PCM027) Interrupts */
++#define PCM027_IRQ(x)          (IRQ_BOARD_START + (x))
++#define PCM027_BTDET_IRQ       PCM027_IRQ(0)
++#define PCM027_FF_RI_IRQ       PCM027_IRQ(1)
++#define PCM027_MMCDET_IRQ      PCM027_IRQ(2)
++#define PCM027_PM_5V_IRQ       PCM027_IRQ(3)
++
++/* ITE8152 irqs */
++/* add IT8152 IRQs beyond BOARD_END */
++#ifdef CONFIG_PCI_HOST_ITE8152
++#define IT8152_IRQ(x)   (IRQ_GPIO(IRQ_BOARD_END) + 1 + (x))
++
++/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
++#define IT8152_LD_IRQ_COUNT     9
++#define IT8152_LP_IRQ_COUNT     16
++#define IT8152_PD_IRQ_COUNT     15
++
++/* Priorities: */
++#define IT8152_PD_IRQ(i)        IT8152_IRQ(i)
++#define IT8152_LP_IRQ(i)        (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
++#define IT8152_LD_IRQ(i)        (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
++
++#define IT8152_LAST_IRQ         IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
++
++#undef NR_IRQS
++#define NR_IRQS (IT8152_LAST_IRQ+1)
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/littleton.h linux-2.6.25-rc4/include/asm-arm/arch/littleton.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/littleton.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/littleton.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,6 @@
++#ifndef __ASM_ARCH_ZYLONITE_H
++#define __ASM_ARCH_ZYLONITE_H
++
++#define LITTLETON_ETH_PHYS	0x30000000
++
++#endif /* __ASM_ARCH_ZYLONITE_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/lpd270.h linux-2.6.25-rc4/include/asm-arm/arch/lpd270.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/lpd270.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/lpd270.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,38 @@
++/*
++ * include/asm-arm/arch-pxa/lpd270.h
++ *
++ * Author:	Lennert Buytenhek
++ * Created:	Feb 10, 2006
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_LPD270_H
++#define __ASM_ARCH_LPD270_H
++
++#define LPD270_CPLD_PHYS	PXA_CS2_PHYS
++#define LPD270_CPLD_VIRT	0xf0000000
++#define LPD270_CPLD_SIZE	0x00100000
++
++#define LPD270_ETH_PHYS		(PXA_CS2_PHYS + 0x01000000)
++
++/* CPLD registers  */
++#define LPD270_CPLD_REG(x)	((unsigned long)(LPD270_CPLD_VIRT + (x)))
++#define LPD270_CONTROL		LPD270_CPLD_REG(0x00)
++#define LPD270_PERIPHERAL0	LPD270_CPLD_REG(0x04)
++#define LPD270_PERIPHERAL1	LPD270_CPLD_REG(0x08)
++#define LPD270_CPLD_REVISION	LPD270_CPLD_REG(0x14)
++#define LPD270_EEPROM_SPI_ITF	LPD270_CPLD_REG(0x20)
++#define LPD270_MODE_PINS	LPD270_CPLD_REG(0x24)
++#define LPD270_EGPIO		LPD270_CPLD_REG(0x30)
++#define LPD270_INT_MASK		LPD270_CPLD_REG(0x40)
++#define LPD270_INT_STATUS	LPD270_CPLD_REG(0x50)
++
++#define LPD270_INT_AC97		(1 << 4)  /* AC'97 CODEC IRQ */
++#define LPD270_INT_ETHERNET	(1 << 3)  /* Ethernet controller IRQ */
++#define LPD270_INT_USBC		(1 << 2)  /* USB client cable detection IRQ */
++
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/lubbock.h linux-2.6.25-rc4/include/asm-arm/arch/lubbock.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/lubbock.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/lubbock.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,40 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/lubbock.h
++ *
++ *  Author:	Nicolas Pitre
++ *  Created:	Jun 15, 2001
++ *  Copyright:	MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#define LUBBOCK_ETH_PHYS	PXA_CS3_PHYS
++
++#define LUBBOCK_FPGA_PHYS	PXA_CS2_PHYS
++#define LUBBOCK_FPGA_VIRT	(0xf0000000)
++#define LUB_P2V(x)		((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
++#define LUB_V2P(x)		((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
++
++#ifndef __ASSEMBLY__
++#  define __LUB_REG(x)		(*((volatile unsigned long *)LUB_P2V(x)))
++#else
++#  define __LUB_REG(x)		LUB_P2V(x)
++#endif
++
++/* FPGA register virtual addresses */
++#define LUB_WHOAMI		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
++#define LUB_HEXLED		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
++#define LUB_DISC_BLNK_LED	__LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
++#define LUB_CONF_SWITCHES	__LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
++#define LUB_USER_SWITCHES	__LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
++#define LUB_MISC_WR		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
++#define LUB_MISC_RD		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
++#define LUB_IRQ_MASK_EN		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
++#define LUB_IRQ_SET_CLR		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
++#define LUB_GP			__LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
++
++#ifndef __ASSEMBLY__
++extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/magician.h linux-2.6.25-rc4/include/asm-arm/arch/magician.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/magician.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/magician.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,111 @@
++/*
++ * GPIO and IRQ definitions for HTC Magician PDA phones
++ *
++ * Copyright (c) 2007 Philipp Zabel
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef _MAGICIAN_H_
++#define _MAGICIAN_H_
++
++#include <asm/arch/pxa-regs.h>
++
++/*
++ * PXA GPIOs
++ */
++
++#define GPIO0_MAGICIAN_KEY_POWER		0
++#define GPIO9_MAGICIAN_UNKNOWN			9
++#define GPIO10_MAGICIAN_GSM_IRQ			10
++#define GPIO11_MAGICIAN_GSM_OUT1		11
++#define GPIO13_MAGICIAN_CPLD_IRQ		13
++#define GPIO18_MAGICIAN_UNKNOWN			18
++#define GPIO22_MAGICIAN_VIBRA_EN		22
++#define GPIO26_MAGICIAN_GSM_POWER		26
++#define GPIO27_MAGICIAN_USBC_PUEN		27
++#define GPIO30_MAGICIAN_nCHARGE_EN		30
++#define GPIO37_MAGICIAN_KEY_HANGUP		37
++#define GPIO38_MAGICIAN_KEY_CONTACTS		38
++#define GPIO40_MAGICIAN_GSM_OUT2		40
++#define GPIO48_MAGICIAN_UNKNOWN			48
++#define GPIO56_MAGICIAN_UNKNOWN			56
++#define GPIO57_MAGICIAN_CAM_RESET		57
++#define GPIO83_MAGICIAN_nIR_EN			83
++#define GPIO86_MAGICIAN_GSM_RESET		86
++#define GPIO87_MAGICIAN_GSM_SELECT		87
++#define GPIO90_MAGICIAN_KEY_CALENDAR		90
++#define GPIO91_MAGICIAN_KEY_CAMERA		91
++#define GPIO93_MAGICIAN_KEY_UP			93
++#define GPIO94_MAGICIAN_KEY_DOWN		94
++#define GPIO95_MAGICIAN_KEY_LEFT		95
++#define GPIO96_MAGICIAN_KEY_RIGHT		96
++#define GPIO97_MAGICIAN_KEY_ENTER		97
++#define GPIO98_MAGICIAN_KEY_RECORD		98
++#define GPIO99_MAGICIAN_HEADPHONE_IN		99
++#define GPIO100_MAGICIAN_KEY_VOL_UP		100
++#define GPIO101_MAGICIAN_KEY_VOL_DOWN 		101
++#define GPIO102_MAGICIAN_KEY_PHONE		102
++#define GPIO103_MAGICIAN_LED_KP			103
++#define GPIO104_MAGICIAN_LCD_POWER_1 		104
++#define GPIO105_MAGICIAN_LCD_POWER_2		105
++#define GPIO106_MAGICIAN_LCD_POWER_3		106
++#define GPIO107_MAGICIAN_DS1WM_IRQ		107
++#define GPIO108_MAGICIAN_GSM_READY		108
++#define GPIO114_MAGICIAN_UNKNOWN		114
++#define GPIO115_MAGICIAN_nPEN_IRQ		115
++#define GPIO116_MAGICIAN_nCAM_EN		116
++#define GPIO119_MAGICIAN_UNKNOWN		119
++#define GPIO120_MAGICIAN_UNKNOWN		120
++
++/*
++ * PXA GPIO alternate function mode & direction
++ */
++
++#define GPIO0_MAGICIAN_KEY_POWER_MD		(0 | GPIO_IN)
++#define GPIO9_MAGICIAN_UNKNOWN_MD		(9 | GPIO_IN)
++#define GPIO10_MAGICIAN_GSM_IRQ_MD		(10 | GPIO_IN)
++#define GPIO11_MAGICIAN_GSM_OUT1_MD		(11 | GPIO_OUT)
++#define GPIO13_MAGICIAN_CPLD_IRQ_MD		(13 | GPIO_IN)
++#define GPIO18_MAGICIAN_UNKNOWN_MD		(18 | GPIO_OUT)
++#define GPIO22_MAGICIAN_VIBRA_EN_MD		(22 | GPIO_OUT)
++#define GPIO26_MAGICIAN_GSM_POWER_MD		(26 | GPIO_OUT)
++#define GPIO27_MAGICIAN_USBC_PUEN_MD		(27 | GPIO_OUT)
++#define GPIO30_MAGICIAN_nCHARGE_EN_MD		(30 | GPIO_OUT)
++#define GPIO37_MAGICIAN_KEY_HANGUP_MD		(37 | GPIO_OUT)
++#define GPIO38_MAGICIAN_KEY_CONTACTS_MD		(38 | GPIO_OUT)
++#define GPIO40_MAGICIAN_GSM_OUT2_MD		(40 | GPIO_OUT)
++#define GPIO48_MAGICIAN_UNKNOWN_MD		(48 | GPIO_OUT)
++#define GPIO56_MAGICIAN_UNKNOWN_MD		(56 | GPIO_OUT)
++#define GPIO57_MAGICIAN_CAM_RESET_MD		(57 | GPIO_OUT)
++#define GPIO83_MAGICIAN_nIR_EN_MD		(83 | GPIO_OUT)
++#define GPIO86_MAGICIAN_GSM_RESET_MD		(86 | GPIO_OUT)
++#define GPIO87_MAGICIAN_GSM_SELECT_MD		(87 | GPIO_OUT)
++#define GPIO90_MAGICIAN_KEY_CALENDAR_MD		(90 | GPIO_OUT)
++#define GPIO91_MAGICIAN_KEY_CAMERA_MD		(91 | GPIO_OUT)
++#define GPIO93_MAGICIAN_KEY_UP_MD		(93 | GPIO_IN)
++#define GPIO94_MAGICIAN_KEY_DOWN_MD		(94 | GPIO_IN)
++#define GPIO95_MAGICIAN_KEY_LEFT_MD		(95 | GPIO_IN)
++#define GPIO96_MAGICIAN_KEY_RIGHT_MD		(96 | GPIO_IN)
++#define GPIO97_MAGICIAN_KEY_ENTER_MD		(97 | GPIO_IN)
++#define GPIO98_MAGICIAN_KEY_RECORD_MD		(98 | GPIO_IN)
++#define GPIO99_MAGICIAN_HEADPHONE_IN_MD		(99 | GPIO_IN)
++#define GPIO100_MAGICIAN_KEY_VOL_UP_MD		(100 | GPIO_IN)
++#define GPIO101_MAGICIAN_KEY_VOL_DOWN_MD 	(101 | GPIO_IN)
++#define GPIO102_MAGICIAN_KEY_PHONE_MD		(102 | GPIO_IN)
++#define GPIO103_MAGICIAN_LED_KP_MD		(103 | GPIO_OUT)
++#define GPIO104_MAGICIAN_LCD_POWER_1_MD 	(104 | GPIO_OUT)
++#define GPIO105_MAGICIAN_LCD_POWER_2_MD		(105 | GPIO_OUT)
++#define GPIO106_MAGICIAN_LCD_POWER_3_MD		(106 | GPIO_OUT)
++#define GPIO107_MAGICIAN_DS1WM_IRQ_MD		(107 | GPIO_IN)
++#define GPIO108_MAGICIAN_GSM_READY_MD		(108 | GPIO_IN)
++#define GPIO114_MAGICIAN_UNKNOWN_MD		(114 | GPIO_OUT)
++#define GPIO115_MAGICIAN_nPEN_IRQ_MD		(115 | GPIO_IN)
++#define GPIO116_MAGICIAN_nCAM_EN_MD		(116 | GPIO_OUT)
++#define GPIO119_MAGICIAN_UNKNOWN_MD		(119 | GPIO_OUT)
++#define GPIO120_MAGICIAN_UNKNOWN_MD		(120 | GPIO_OUT)
++
++#endif /* _MAGICIAN_H_ */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mainstone.h linux-2.6.25-rc4/include/asm-arm/arch/mainstone.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mainstone.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/mainstone.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,120 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/mainstone.h
++ *
++ *  Author:	Nicolas Pitre
++ *  Created:	Nov 14, 2002
++ *  Copyright:	MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef ASM_ARCH_MAINSTONE_H
++#define ASM_ARCH_MAINSTONE_H
++
++#define MST_ETH_PHYS		PXA_CS4_PHYS
++
++#define MST_FPGA_PHYS		PXA_CS2_PHYS
++#define MST_FPGA_VIRT		(0xf0000000)
++#define MST_P2V(x)		((x) - MST_FPGA_PHYS + MST_FPGA_VIRT)
++#define MST_V2P(x)		((x) - MST_FPGA_VIRT + MST_FPGA_PHYS)
++
++#ifndef __ASSEMBLY__
++# define __MST_REG(x)		(*((volatile unsigned long *)MST_P2V(x)))
++#else
++# define __MST_REG(x)		MST_P2V(x)
++#endif
++
++/* board level registers in the FPGA */
++
++#define MST_LEDDAT1		__MST_REG(0x08000010)
++#define MST_LEDDAT2		__MST_REG(0x08000014)
++#define MST_LEDCTRL		__MST_REG(0x08000040)
++#define MST_GPSWR		__MST_REG(0x08000060)
++#define MST_MSCWR1		__MST_REG(0x08000080)
++#define MST_MSCWR2		__MST_REG(0x08000084)
++#define MST_MSCWR3		__MST_REG(0x08000088)
++#define MST_MSCRD		__MST_REG(0x08000090)
++#define MST_INTMSKENA		__MST_REG(0x080000c0)
++#define MST_INTSETCLR		__MST_REG(0x080000d0)
++#define MST_PCMCIA0		__MST_REG(0x080000e0)
++#define MST_PCMCIA1		__MST_REG(0x080000e4)
++
++#define MST_MSCWR1_CAMERA_ON	(1 << 15)  /* Camera interface power control */
++#define MST_MSCWR1_CAMERA_SEL	(1 << 14)  /* Camera interface mux control */
++#define MST_MSCWR1_LCD_CTL	(1 << 13)  /* General-purpose LCD control */
++#define MST_MSCWR1_MS_ON	(1 << 12)  /* Memory Stick power control */
++#define MST_MSCWR1_MMC_ON	(1 << 11)  /* MultiMediaCard* power control */
++#define MST_MSCWR1_MS_SEL	(1 << 10)  /* SD/MS multiplexer control */
++#define MST_MSCWR1_BB_SEL	(1 << 9)   /* PCMCIA/Baseband multiplexer */
++#define MST_MSCWR1_BT_ON	(1 << 8)   /* Bluetooth UART transceiver */
++#define MST_MSCWR1_BTDTR	(1 << 7)   /* Bluetooth UART DTR */
++
++#define MST_MSCWR1_IRDA_MASK	(3 << 5)   /* IrDA transceiver mode */
++#define MST_MSCWR1_IRDA_FULL	(0 << 5)   /* full distance power */
++#define MST_MSCWR1_IRDA_OFF	(1 << 5)   /* shutdown */
++#define MST_MSCWR1_IRDA_MED	(2 << 5)   /* 2/3 distance power */
++#define MST_MSCWR1_IRDA_LOW	(3 << 5)   /* 1/3 distance power */
++
++#define MST_MSCWR1_IRDA_FIR	(1 << 4)   /* IrDA transceiver SIR/FIR */
++#define MST_MSCWR1_GREENLED	(1 << 3)   /* LED D1 control */
++#define MST_MSCWR1_PDC_CTL	(1 << 2)   /* reserved */
++#define MST_MSCWR1_MTR_ON	(1 << 1)   /* Silent alert motor */
++#define MST_MSCWR1_SYSRESET	(1 << 0)   /* System reset */
++
++#define MST_MSCWR2_USB_OTG_RST	(1 << 6)   /* USB On The Go reset */
++#define MST_MSCWR2_USB_OTG_SEL	(1 << 5)   /* USB On The Go control */
++#define MST_MSCWR2_nUSBC_SC	(1 << 4)   /* USB client soft connect control */
++#define MST_MSCWR2_I2S_SPKROFF	(1 << 3)   /* I2S CODEC amplifier control */
++#define MST_MSCWR2_AC97_SPKROFF	(1 << 2)   /* AC97 CODEC amplifier control */
++#define MST_MSCWR2_RADIO_PWR	(1 << 1)   /* Radio module power control */
++#define MST_MSCWR2_RADIO_WAKE	(1 << 0)   /* Radio module wake-up signal */
++
++#define MST_MSCWR3_GPIO_RESET_EN	(1 << 2) /* Enable GPIO Reset */
++#define MST_MSCWR3_GPIO_RESET		(1 << 1) /* Initiate a GPIO Reset */
++#define MST_MSCWR3_COMMS_SW_RESET	(1 << 0) /* Communications Processor Reset Control */
++
++#define MST_MSCRD_nPENIRQ	(1 << 9)   /* ADI7873* nPENIRQ signal */
++#define MST_MSCRD_nMEMSTK_CD	(1 << 8)   /* Memory Stick detection signal */
++#define MST_MSCRD_nMMC_CD	(1 << 7)   /* SD/MMC card detection signal */
++#define MST_MSCRD_nUSIM_CD	(1 << 6)   /* USIM card detection signal */
++#define MST_MSCRD_USB_CBL	(1 << 5)   /* USB client cable status */
++#define MST_MSCRD_TS_BUSY	(1 << 4)   /* ADI7873 busy */
++#define MST_MSCRD_BTDSR		(1 << 3)   /* Bluetooth UART DSR */
++#define MST_MSCRD_BTRI		(1 << 2)   /* Bluetooth UART Ring Indicator */
++#define MST_MSCRD_BTDCD		(1 << 1)   /* Bluetooth UART DCD */
++#define MST_MSCRD_nMMC_WP	(1 << 0)   /* SD/MMC write-protect status */
++
++#define MST_INT_S1_IRQ		(1 << 15)  /* PCMCIA socket 1 IRQ */
++#define MST_INT_S1_STSCHG	(1 << 14)  /* PCMCIA socket 1 status changed */
++#define MST_INT_S1_CD		(1 << 13)  /* PCMCIA socket 1 card detection */
++#define MST_INT_S0_IRQ		(1 << 11)  /* PCMCIA socket 0 IRQ */
++#define MST_INT_S0_STSCHG	(1 << 10)  /* PCMCIA socket 0 status changed */
++#define MST_INT_S0_CD		(1 << 9)   /* PCMCIA socket 0 card detection */
++#define MST_INT_nEXBRD_INT	(1 << 7)   /* Expansion board IRQ */
++#define MST_INT_MSINS		(1 << 6)   /* Memory Stick* detection */
++#define MST_INT_PENIRQ		(1 << 5)   /* ADI7873* touch-screen IRQ */
++#define MST_INT_AC97		(1 << 4)   /* AC'97 CODEC IRQ */
++#define MST_INT_ETHERNET	(1 << 3)   /* Ethernet controller IRQ */
++#define MST_INT_USBC		(1 << 2)   /* USB client cable detection IRQ */
++#define MST_INT_USIM		(1 << 1)   /* USIM card detection IRQ */
++#define MST_INT_MMC		(1 << 0)   /* MMC/SD card detection IRQ */
++
++#define MST_PCMCIA_nIRQ		(1 << 10)  /* IRQ / ready signal */
++#define MST_PCMCIA_nSPKR_BVD2	(1 << 9)   /* VDD sense / digital speaker */
++#define MST_PCMCIA_nSTSCHG_BVD1	(1 << 8)   /* VDD sense / card status changed */
++#define MST_PCMCIA_nVS2		(1 << 7)   /* VSS voltage sense */
++#define MST_PCMCIA_nVS1		(1 << 6)   /* VSS voltage sense */
++#define MST_PCMCIA_nCD		(1 << 5)   /* Card detection signal */
++#define MST_PCMCIA_RESET	(1 << 4)   /* Card reset signal */
++#define MST_PCMCIA_PWR_MASK	(0x000f)   /* MAX1602 power-supply controls */
++
++#define MST_PCMCIA_PWR_VPP_0    0x0	   /* voltage VPP = 0V */
++#define MST_PCMCIA_PWR_VPP_120  0x2 	   /* voltage VPP = 12V*/
++#define MST_PCMCIA_PWR_VPP_VCC  0x1	   /* voltage VPP = VCC */
++#define MST_PCMCIA_PWR_VCC_0    0x0	   /* voltage VCC = 0V */
++#define MST_PCMCIA_PWR_VCC_33   0x8	   /* voltage VCC = 3.3V */
++#define MST_PCMCIA_PWR_VCC_50   0x4	   /* voltage VCC = 5.0V */
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/memory.h linux-2.6.25-rc4/include/asm-arm/arch/memory.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/memory.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/memory.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,52 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/memory.h
++ *
++ * Author:	Nicolas Pitre
++ * Copyright:	(C) 2001 MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_MEMORY_H
++#define __ASM_ARCH_MEMORY_H
++
++/*
++ * Physical DRAM offset.
++ */
++#define PHYS_OFFSET	UL(0xa0000000)
++
++/*
++ * Virtual view <-> DMA view memory address translations
++ * virt_to_bus: Used to translate the virtual address to an
++ *		address suitable to be passed to set_dma_addr
++ * bus_to_virt: Used to convert an address for DMA operations
++ *		to an address that the kernel can use.
++ */
++#define __virt_to_bus(x)	 __virt_to_phys(x)
++#define __bus_to_virt(x)	 __phys_to_virt(x)
++
++/*
++ * The nodes are matched with the physical SDRAM banks as follows:
++ *
++ * 	node 0:  0xa0000000-0xa3ffffff	-->  0xc0000000-0xc3ffffff
++ * 	node 1:  0xa4000000-0xa7ffffff	-->  0xc4000000-0xc7ffffff
++ * 	node 2:  0xa8000000-0xabffffff	-->  0xc8000000-0xcbffffff
++ * 	node 3:  0xac000000-0xafffffff	-->  0xcc000000-0xcfffffff
++ *
++ * This needs a node mem size of 26 bits.
++ */
++#define NODE_MEM_SIZE_BITS	26
++
++#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
++void cmx270_pci_adjust_zones(int node, unsigned long *size,
++			     unsigned long *holes);
++
++#define arch_adjust_zones(node, size, holes) \
++	cmx270_pci_adjust_zones(node, size, holes)
++
++#define ISA_DMA_THRESHOLD	(PHYS_OFFSET + SZ_64M - 1)
++#endif
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp.h linux-2.6.25-rc4/include/asm-arm/arch/mfp.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/mfp.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,311 @@
++/*
++ * linux/include/asm-arm/arch-pxa/mfp.h
++ *
++ * Multi-Function Pin Definitions
++ *
++ * Copyright (C) 2007 Marvell International Ltd.
++ *
++ * 2007-8-21: eric miao <eric.miao@marvell.com>
++ *            initial version
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_MFP_H
++#define __ASM_ARCH_MFP_H
++
++#define mfp_to_gpio(m)	((m) % 128)
++
++/* list of all the configurable MFP pins */
++enum {
++	MFP_PIN_INVALID = -1,
++
++	MFP_PIN_GPIO0 = 0,
++	MFP_PIN_GPIO1,
++	MFP_PIN_GPIO2,
++	MFP_PIN_GPIO3,
++	MFP_PIN_GPIO4,
++	MFP_PIN_GPIO5,
++	MFP_PIN_GPIO6,
++	MFP_PIN_GPIO7,
++	MFP_PIN_GPIO8,
++	MFP_PIN_GPIO9,
++	MFP_PIN_GPIO10,
++	MFP_PIN_GPIO11,
++	MFP_PIN_GPIO12,
++	MFP_PIN_GPIO13,
++	MFP_PIN_GPIO14,
++	MFP_PIN_GPIO15,
++	MFP_PIN_GPIO16,
++	MFP_PIN_GPIO17,
++	MFP_PIN_GPIO18,
++	MFP_PIN_GPIO19,
++	MFP_PIN_GPIO20,
++	MFP_PIN_GPIO21,
++	MFP_PIN_GPIO22,
++	MFP_PIN_GPIO23,
++	MFP_PIN_GPIO24,
++	MFP_PIN_GPIO25,
++	MFP_PIN_GPIO26,
++	MFP_PIN_GPIO27,
++	MFP_PIN_GPIO28,
++	MFP_PIN_GPIO29,
++	MFP_PIN_GPIO30,
++	MFP_PIN_GPIO31,
++	MFP_PIN_GPIO32,
++	MFP_PIN_GPIO33,
++	MFP_PIN_GPIO34,
++	MFP_PIN_GPIO35,
++	MFP_PIN_GPIO36,
++	MFP_PIN_GPIO37,
++	MFP_PIN_GPIO38,
++	MFP_PIN_GPIO39,
++	MFP_PIN_GPIO40,
++	MFP_PIN_GPIO41,
++	MFP_PIN_GPIO42,
++	MFP_PIN_GPIO43,
++	MFP_PIN_GPIO44,
++	MFP_PIN_GPIO45,
++	MFP_PIN_GPIO46,
++	MFP_PIN_GPIO47,
++	MFP_PIN_GPIO48,
++	MFP_PIN_GPIO49,
++	MFP_PIN_GPIO50,
++	MFP_PIN_GPIO51,
++	MFP_PIN_GPIO52,
++	MFP_PIN_GPIO53,
++	MFP_PIN_GPIO54,
++	MFP_PIN_GPIO55,
++	MFP_PIN_GPIO56,
++	MFP_PIN_GPIO57,
++	MFP_PIN_GPIO58,
++	MFP_PIN_GPIO59,
++	MFP_PIN_GPIO60,
++	MFP_PIN_GPIO61,
++	MFP_PIN_GPIO62,
++	MFP_PIN_GPIO63,
++	MFP_PIN_GPIO64,
++	MFP_PIN_GPIO65,
++	MFP_PIN_GPIO66,
++	MFP_PIN_GPIO67,
++	MFP_PIN_GPIO68,
++	MFP_PIN_GPIO69,
++	MFP_PIN_GPIO70,
++	MFP_PIN_GPIO71,
++	MFP_PIN_GPIO72,
++	MFP_PIN_GPIO73,
++	MFP_PIN_GPIO74,
++	MFP_PIN_GPIO75,
++	MFP_PIN_GPIO76,
++	MFP_PIN_GPIO77,
++	MFP_PIN_GPIO78,
++	MFP_PIN_GPIO79,
++	MFP_PIN_GPIO80,
++	MFP_PIN_GPIO81,
++	MFP_PIN_GPIO82,
++	MFP_PIN_GPIO83,
++	MFP_PIN_GPIO84,
++	MFP_PIN_GPIO85,
++	MFP_PIN_GPIO86,
++	MFP_PIN_GPIO87,
++	MFP_PIN_GPIO88,
++	MFP_PIN_GPIO89,
++	MFP_PIN_GPIO90,
++	MFP_PIN_GPIO91,
++	MFP_PIN_GPIO92,
++	MFP_PIN_GPIO93,
++	MFP_PIN_GPIO94,
++	MFP_PIN_GPIO95,
++	MFP_PIN_GPIO96,
++	MFP_PIN_GPIO97,
++	MFP_PIN_GPIO98,
++	MFP_PIN_GPIO99,
++	MFP_PIN_GPIO100,
++	MFP_PIN_GPIO101,
++	MFP_PIN_GPIO102,
++	MFP_PIN_GPIO103,
++	MFP_PIN_GPIO104,
++	MFP_PIN_GPIO105,
++	MFP_PIN_GPIO106,
++	MFP_PIN_GPIO107,
++	MFP_PIN_GPIO108,
++	MFP_PIN_GPIO109,
++	MFP_PIN_GPIO110,
++	MFP_PIN_GPIO111,
++	MFP_PIN_GPIO112,
++	MFP_PIN_GPIO113,
++	MFP_PIN_GPIO114,
++	MFP_PIN_GPIO115,
++	MFP_PIN_GPIO116,
++	MFP_PIN_GPIO117,
++	MFP_PIN_GPIO118,
++	MFP_PIN_GPIO119,
++	MFP_PIN_GPIO120,
++	MFP_PIN_GPIO121,
++	MFP_PIN_GPIO122,
++	MFP_PIN_GPIO123,
++	MFP_PIN_GPIO124,
++	MFP_PIN_GPIO125,
++	MFP_PIN_GPIO126,
++	MFP_PIN_GPIO127,
++	MFP_PIN_GPIO0_2,
++	MFP_PIN_GPIO1_2,
++	MFP_PIN_GPIO2_2,
++	MFP_PIN_GPIO3_2,
++	MFP_PIN_GPIO4_2,
++	MFP_PIN_GPIO5_2,
++	MFP_PIN_GPIO6_2,
++	MFP_PIN_GPIO7_2,
++	MFP_PIN_GPIO8_2,
++	MFP_PIN_GPIO9_2,
++	MFP_PIN_GPIO10_2,
++	MFP_PIN_GPIO11_2,
++	MFP_PIN_GPIO12_2,
++	MFP_PIN_GPIO13_2,
++	MFP_PIN_GPIO14_2,
++	MFP_PIN_GPIO15_2,
++	MFP_PIN_GPIO16_2,
++	MFP_PIN_GPIO17_2,
++
++	MFP_PIN_ULPI_STP,
++	MFP_PIN_ULPI_NXT,
++	MFP_PIN_ULPI_DIR,
++
++	MFP_PIN_nXCVREN,
++	MFP_PIN_DF_CLE_nOE,
++	MFP_PIN_DF_nADV1_ALE,
++	MFP_PIN_DF_SCLK_E,
++	MFP_PIN_DF_SCLK_S,
++	MFP_PIN_nBE0,
++	MFP_PIN_nBE1,
++	MFP_PIN_DF_nADV2_ALE,
++	MFP_PIN_DF_INT_RnB,
++	MFP_PIN_DF_nCS0,
++	MFP_PIN_DF_nCS1,
++	MFP_PIN_nLUA,
++	MFP_PIN_nLLA,
++	MFP_PIN_DF_nWE,
++	MFP_PIN_DF_ALE_nWE,
++	MFP_PIN_DF_nRE_nOE,
++	MFP_PIN_DF_ADDR0,
++	MFP_PIN_DF_ADDR1,
++	MFP_PIN_DF_ADDR2,
++	MFP_PIN_DF_ADDR3,
++	MFP_PIN_DF_IO0,
++	MFP_PIN_DF_IO1,
++	MFP_PIN_DF_IO2,
++	MFP_PIN_DF_IO3,
++	MFP_PIN_DF_IO4,
++	MFP_PIN_DF_IO5,
++	MFP_PIN_DF_IO6,
++	MFP_PIN_DF_IO7,
++	MFP_PIN_DF_IO8,
++	MFP_PIN_DF_IO9,
++	MFP_PIN_DF_IO10,
++	MFP_PIN_DF_IO11,
++	MFP_PIN_DF_IO12,
++	MFP_PIN_DF_IO13,
++	MFP_PIN_DF_IO14,
++	MFP_PIN_DF_IO15,
++
++	MFP_PIN_MAX,
++};
++
++/*
++ * a possible MFP configuration is represented by a 32-bit integer
++ *
++ * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
++ * bit 10..12 - Alternate Function Selection
++ * bit 13..15 - Drive Strength
++ * bit 16..18 - Low Power Mode State
++ * bit 19..20 - Low Power Mode Edge Detection
++ * bit 21..22 - Run Mode Pull State
++ *
++ * to facilitate the definition, the following macros are provided
++ *
++ * MFP_CFG_DEFAULT - default MFP configuration value, with
++ * 		  alternate function = 0,
++ * 		  drive strength = fast 3mA (MFP_DS03X)
++ * 		  low power mode = default
++ * 		  edge detection = none
++ *
++ * MFP_CFG	- default MFPR value with alternate function
++ * MFP_CFG_DRV	- default MFPR value with alternate function and
++ * 		  pin drive strength
++ * MFP_CFG_LPM	- default MFPR value with alternate function and
++ * 		  low power mode
++ * MFP_CFG_X	- default MFPR value with alternate function,
++ * 		  pin drive strength and low power mode
++ */
++
++typedef unsigned long mfp_cfg_t;
++
++#define MFP_PIN(x)		((x) & 0x3ff)
++
++#define MFP_AF0			(0x0 << 10)
++#define MFP_AF1			(0x1 << 10)
++#define MFP_AF2			(0x2 << 10)
++#define MFP_AF3			(0x3 << 10)
++#define MFP_AF4			(0x4 << 10)
++#define MFP_AF5			(0x5 << 10)
++#define MFP_AF6			(0x6 << 10)
++#define MFP_AF7			(0x7 << 10)
++#define MFP_AF_MASK		(0x7 << 10)
++#define MFP_AF(x)		(((x) >> 10) & 0x7)
++
++#define MFP_DS01X		(0x0 << 13)
++#define MFP_DS02X		(0x1 << 13)
++#define MFP_DS03X		(0x2 << 13)
++#define MFP_DS04X		(0x3 << 13)
++#define MFP_DS06X		(0x4 << 13)
++#define MFP_DS08X		(0x5 << 13)
++#define MFP_DS10X		(0x6 << 13)
++#define MFP_DS13X		(0x7 << 13)
++#define MFP_DS_MASK		(0x7 << 13)
++#define MFP_DS(x)		(((x) >> 13) & 0x7)
++
++#define MFP_LPM_INPUT		(0x0 << 16)
++#define MFP_LPM_DRIVE_LOW	(0x1 << 16)
++#define MFP_LPM_DRIVE_HIGH	(0x2 << 16)
++#define MFP_LPM_PULL_LOW	(0x3 << 16)
++#define MFP_LPM_PULL_HIGH	(0x4 << 16)
++#define MFP_LPM_FLOAT		(0x5 << 16)
++#define MFP_LPM_STATE_MASK	(0x7 << 16)
++#define MFP_LPM_STATE(x)	(((x) >> 16) & 0x7)
++
++#define MFP_LPM_EDGE_NONE	(0x0 << 19)
++#define MFP_LPM_EDGE_RISE	(0x1 << 19)
++#define MFP_LPM_EDGE_FALL	(0x2 << 19)
++#define MFP_LPM_EDGE_BOTH	(0x3 << 19)
++#define MFP_LPM_EDGE_MASK	(0x3 << 19)
++#define MFP_LPM_EDGE(x)		(((x) >> 19) & 0x3)
++
++#define MFP_PULL_NONE		(0x0 << 21)
++#define MFP_PULL_LOW		(0x1 << 21)
++#define MFP_PULL_HIGH		(0x2 << 21)
++#define MFP_PULL_BOTH		(0x3 << 21)
++#define MFP_PULL_MASK		(0x3 << 21)
++#define MFP_PULL(x)		(((x) >> 21) & 0x3)
++
++#define MFP_CFG_DEFAULT		(MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
++				 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
++
++#define MFP_CFG(pin, af)		\
++	((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
++	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
++
++#define MFP_CFG_DRV(pin, af, drv)	\
++	((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
++	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
++
++#define MFP_CFG_LPM(pin, af, lpm)	\
++	((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
++	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
++
++#define MFP_CFG_X(pin, af, drv, lpm)	\
++	((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
++	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
++
++#endif /* __ASM_ARCH_MFP_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa300.h linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa300.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa300.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa300.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,575 @@
++/*
++ * linux/include/asm-arm/arch-pxa/mfp-pxa300.h
++ *
++ * PXA300/PXA310 specific MFP configuration definitions
++ *
++ * Copyright (C) 2007 Marvell International Ltd.
++ * 2007-08-21: eric miao <eric.miao@marvell.com>
++ *             initial version
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_MFP_PXA300_H
++#define __ASM_ARCH_MFP_PXA300_H
++
++#include <asm/arch/mfp.h>
++#include <asm/arch/mfp-pxa3xx.h>
++
++/* GPIO */
++#define GPIO46_GPIO		MFP_CFG(GPIO46, AF1)
++#define GPIO49_GPIO		MFP_CFG(GPIO49, AF3)
++#define GPIO50_GPIO		MFP_CFG(GPIO50, AF2)
++#define GPIO51_GPIO		MFP_CFG(GPIO51, AF3)
++#define GPIO52_GPIO		MFP_CFG(GPIO52, AF3)
++#define GPIO56_GPIO		MFP_CFG(GPIO56, AF0)
++#define GPIO58_GPIO		MFP_CFG(GPIO58, AF0)
++#define GPIO59_GPIO		MFP_CFG(GPIO59, AF0)
++#define GPIO60_GPIO		MFP_CFG(GPIO60, AF0)
++#define GPIO61_GPIO		MFP_CFG(GPIO61, AF0)
++#define GPIO62_GPIO		MFP_CFG(GPIO62, AF0)
++
++#ifdef CONFIG_CPU_PXA310
++#define GPIO7_2_GPIO		MFP_CFG(GPIO7_2, AF0)
++#define GPIO8_2_GPIO		MFP_CFG(GPIO8_2, AF0)
++#define GPIO9_2_GPIO		MFP_CFG(GPIO9_2, AF0)
++#define GPIO10_2_GPIO		MFP_CFG(GPIO10_2, AF0)
++#define GPIO11_2_GPIO		MFP_CFG(GPIO11_2, AF0)
++#define GPIO12_2_GPIO		MFP_CFG(GPIO12_2, AF0)
++#endif
++
++/* Chip Select */
++#define GPIO2_nCS3		MFP_CFG(GPIO2,  AF1)
++
++/* AC97 */
++#define GPIO23_AC97_nACRESET	MFP_CFG(GPIO23, AF1)
++#define GPIO24_AC97_SYSCLK	MFP_CFG(GPIO24, AF1)
++#define GPIO29_AC97_BITCLK	MFP_CFG(GPIO29, AF1)
++#define GPIO25_AC97_SDATA_IN_0	MFP_CFG(GPIO25, AF1)
++#define GPIO26_AC97_SDATA_IN_1	MFP_CFG(GPIO26, AF1)
++#define GPIO17_AC97_SDATA_IN_2	MFP_CFG(GPIO17, AF3)
++#define GPIO21_AC97_SDATA_IN_2	MFP_CFG(GPIO21, AF2)
++#define GPIO18_AC97_SDATA_IN_3	MFP_CFG(GPIO18, AF3)
++#define GPIO22_AC97_SDATA_IN_3	MFP_CFG(GPIO22, AF2)
++#define GPIO27_AC97_SDATA_OUT	MFP_CFG(GPIO27, AF1)
++#define GPIO28_AC97_SYNC	MFP_CFG(GPIO28, AF1)
++
++/* I2C */
++#define GPIO21_I2C_SCL		MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
++#define GPIO22_I2C_SDA		MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
++
++/* QCI */
++#define GPIO39_CI_DD_0		MFP_CFG_DRV(GPIO39, AF1, DS04X)
++#define GPIO40_CI_DD_1		MFP_CFG_DRV(GPIO40, AF1, DS04X)
++#define GPIO41_CI_DD_2		MFP_CFG_DRV(GPIO41, AF1, DS04X)
++#define GPIO42_CI_DD_3		MFP_CFG_DRV(GPIO42, AF1, DS04X)
++#define GPIO43_CI_DD_4		MFP_CFG_DRV(GPIO43, AF1, DS04X)
++#define GPIO44_CI_DD_5		MFP_CFG_DRV(GPIO44, AF1, DS04X)
++#define GPIO45_CI_DD_6		MFP_CFG_DRV(GPIO45, AF1, DS04X)
++#define GPIO46_CI_DD_7		MFP_CFG_DRV(GPIO46, AF0, DS04X)
++#define GPIO47_CI_DD_8		MFP_CFG_DRV(GPIO47, AF1, DS04X)
++#define GPIO48_CI_DD_9		MFP_CFG_DRV(GPIO48, AF1, DS04X)
++#define GPIO52_CI_HSYNC		MFP_CFG_DRV(GPIO52, AF0, DS04X)
++#define GPIO51_CI_VSYNC		MFP_CFG_DRV(GPIO51, AF0, DS04X)
++#define GPIO49_CI_MCLK		MFP_CFG_DRV(GPIO49, AF0, DS04X)
++#define GPIO50_CI_PCLK		MFP_CFG_DRV(GPIO50, AF0, DS04X)
++
++/* KEYPAD */
++#define GPIO3_KP_DKIN_6		MFP_CFG_LPM(GPIO3,   AF2, FLOAT)
++#define GPIO4_KP_DKIN_7		MFP_CFG_LPM(GPIO4,   AF2, FLOAT)
++#define GPIO16_KP_DKIN_6	MFP_CFG_LPM(GPIO16,  AF6, FLOAT)
++#define GPIO83_KP_DKIN_2	MFP_CFG_LPM(GPIO83,  AF5, FLOAT)
++#define GPIO84_KP_DKIN_1	MFP_CFG_LPM(GPIO84,  AF5, FLOAT)
++#define GPIO85_KP_DKIN_0	MFP_CFG_LPM(GPIO85,  AF3, FLOAT)
++#define GPIO86_KP_DKIN_1	MFP_CFG_LPM(GPIO86,  AF3, FLOAT)
++#define GPIO87_KP_DKIN_2	MFP_CFG_LPM(GPIO87,  AF3, FLOAT)
++#define GPIO88_KP_DKIN_3	MFP_CFG_LPM(GPIO88,  AF3, FLOAT)
++#define GPIO89_KP_DKIN_3	MFP_CFG_LPM(GPIO89,  AF3, FLOAT)
++#define GPIO107_KP_DKIN_0	MFP_CFG_LPM(GPIO107, AF2, FLOAT)
++#define GPIO108_KP_DKIN_1	MFP_CFG_LPM(GPIO108, AF2, FLOAT)
++#define GPIO109_KP_DKIN_2	MFP_CFG_LPM(GPIO109, AF2, FLOAT)
++#define GPIO110_KP_DKIN_3	MFP_CFG_LPM(GPIO110, AF2, FLOAT)
++#define GPIO111_KP_DKIN_4	MFP_CFG_LPM(GPIO111, AF2, FLOAT)
++#define GPIO112_KP_DKIN_5	MFP_CFG_LPM(GPIO112, AF2, FLOAT)
++#define GPIO113_KP_DKIN_6	MFP_CFG_LPM(GPIO113, AF2, FLOAT)
++#define GPIO114_KP_DKIN_7	MFP_CFG_LPM(GPIO114, AF2, FLOAT)
++#define GPIO115_KP_DKIN_0	MFP_CFG_LPM(GPIO115, AF2, FLOAT)
++#define GPIO116_KP_DKIN_1	MFP_CFG_LPM(GPIO116, AF2, FLOAT)
++#define GPIO117_KP_DKIN_2	MFP_CFG_LPM(GPIO117, AF2, FLOAT)
++#define GPIO118_KP_DKIN_3	MFP_CFG_LPM(GPIO118, AF2, FLOAT)
++#define GPIO119_KP_DKIN_4	MFP_CFG_LPM(GPIO119, AF2, FLOAT)
++#define GPIO120_KP_DKIN_5	MFP_CFG_LPM(GPIO120, AF2, FLOAT)
++#define GPIO121_KP_DKIN_6	MFP_CFG_LPM(GPIO121, AF2, FLOAT)
++#define GPIO122_KP_DKIN_5	MFP_CFG_LPM(GPIO122, AF2, FLOAT)
++#define GPIO123_KP_DKIN_4	MFP_CFG_LPM(GPIO123, AF2, FLOAT)
++#define GPIO124_KP_DKIN_3	MFP_CFG_LPM(GPIO124, AF2, FLOAT)
++#define GPIO127_KP_DKIN_0	MFP_CFG_LPM(GPIO127, AF5, FLOAT)
++#define GPIO0_2_KP_DKIN_0	MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
++#define GPIO1_2_KP_DKIN_1	MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
++#define GPIO2_2_KP_DKIN_6	MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
++#define GPIO3_2_KP_DKIN_7	MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
++#define GPIO4_2_KP_DKIN_1	MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
++#define GPIO5_2_KP_DKIN_0	MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
++
++#define GPIO5_KP_MKIN_0		MFP_CFG_LPM(GPIO5,   AF2, FLOAT)
++#define GPIO6_KP_MKIN_1		MFP_CFG_LPM(GPIO6,   AF2, FLOAT)
++#define GPIO9_KP_MKIN_6		MFP_CFG_LPM(GPIO9,   AF3, FLOAT)
++#define GPIO10_KP_MKIN_7	MFP_CFG_LPM(GPIO10,  AF3, FLOAT)
++#define GPIO70_KP_MKIN_6	MFP_CFG_LPM(GPIO70,  AF3, FLOAT)
++#define GPIO71_KP_MKIN_7	MFP_CFG_LPM(GPIO71,  AF3, FLOAT)
++#define GPIO100_KP_MKIN_6	MFP_CFG_LPM(GPIO100, AF7, FLOAT)
++#define GPIO101_KP_MKIN_7	MFP_CFG_LPM(GPIO101, AF7, FLOAT)
++#define GPIO112_KP_MKIN_6	MFP_CFG_LPM(GPIO112, AF4, FLOAT)
++#define GPIO113_KP_MKIN_7	MFP_CFG_LPM(GPIO113, AF4, FLOAT)
++#define GPIO115_KP_MKIN_0	MFP_CFG_LPM(GPIO115, AF1, FLOAT)
++#define GPIO116_KP_MKIN_1	MFP_CFG_LPM(GPIO116, AF1, FLOAT)
++#define GPIO117_KP_MKIN_2	MFP_CFG_LPM(GPIO117, AF1, FLOAT)
++#define GPIO118_KP_MKIN_3	MFP_CFG_LPM(GPIO118, AF1, FLOAT)
++#define GPIO119_KP_MKIN_4	MFP_CFG_LPM(GPIO119, AF1, FLOAT)
++#define GPIO120_KP_MKIN_5	MFP_CFG_LPM(GPIO120, AF1, FLOAT)
++#define GPIO125_KP_MKIN_2	MFP_CFG_LPM(GPIO125, AF2, FLOAT)
++#define GPIO2_2_KP_MKIN_6	MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
++#define GPIO3_2_KP_MKIN_7	MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
++
++#define GPIO7_KP_MKOUT_5	MFP_CFG_LPM(GPIO7,   AF1, DRIVE_HIGH)
++#define GPIO11_KP_MKOUT_5	MFP_CFG_LPM(GPIO11,  AF3, DRIVE_HIGH)
++#define GPIO12_KP_MKOUT_6	MFP_CFG_LPM(GPIO12,  AF3, DRIVE_HIGH)
++#define GPIO13_KP_MKOUT_7	MFP_CFG_LPM(GPIO13,  AF3, DRIVE_HIGH)
++#define GPIO19_KP_MKOUT_4	MFP_CFG_LPM(GPIO19,  AF3, DRIVE_HIGH)
++#define GPIO20_KP_MKOUT_5	MFP_CFG_LPM(GPIO20,  AF3, DRIVE_HIGH)
++#define GPIO38_KP_MKOUT_5	MFP_CFG_LPM(GPIO38,  AF5, DRIVE_HIGH)
++#define GPIO53_KP_MKOUT_6	MFP_CFG_LPM(GPIO53,  AF5, DRIVE_HIGH)
++#define GPIO78_KP_MKOUT_7	MFP_CFG_LPM(GPIO78,  AF5, DRIVE_HIGH)
++#define GPIO85_KP_MKOUT_0	MFP_CFG_LPM(GPIO85,  AF2, DRIVE_HIGH)
++#define GPIO86_KP_MKOUT_1	MFP_CFG_LPM(GPIO86,  AF2, DRIVE_HIGH)
++#define GPIO87_KP_MKOUT_2	MFP_CFG_LPM(GPIO87,  AF2, DRIVE_HIGH)
++#define GPIO88_KP_MKOUT_3	MFP_CFG_LPM(GPIO88,  AF2, DRIVE_HIGH)
++#define GPIO104_KP_MKOUT_6	MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
++#define GPIO105_KP_MKOUT_7	MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
++#define GPIO121_KP_MKOUT_0	MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
++#define GPIO122_KP_MKOUT_1	MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
++#define GPIO123_KP_MKOUT_2	MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
++#define GPIO124_KP_MKOUT_3	MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
++#define GPIO125_KP_MKOUT_4	MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
++#define GPIO126_KP_MKOUT_7	MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
++#define GPIO5_2_KP_MKOUT_6	MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
++#define GPIO4_2_KP_MKOUT_5	MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
++#define GPIO6_2_KP_MKOUT_7	MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
++
++/* LCD */
++#define GPIO54_LCD_LDD_0	MFP_CFG_DRV(GPIO54, AF1, DS01X)
++#define GPIO55_LCD_LDD_1	MFP_CFG_DRV(GPIO55, AF1, DS01X)
++#define GPIO56_LCD_LDD_2	MFP_CFG_DRV(GPIO56, AF1, DS01X)
++#define GPIO57_LCD_LDD_3	MFP_CFG_DRV(GPIO57, AF1, DS01X)
++#define GPIO58_LCD_LDD_4	MFP_CFG_DRV(GPIO58, AF1, DS01X)
++#define GPIO59_LCD_LDD_5	MFP_CFG_DRV(GPIO59, AF1, DS01X)
++#define GPIO60_LCD_LDD_6	MFP_CFG_DRV(GPIO60, AF1, DS01X)
++#define GPIO61_LCD_LDD_7	MFP_CFG_DRV(GPIO61, AF1, DS01X)
++#define GPIO62_LCD_LDD_8	MFP_CFG_DRV(GPIO62, AF1, DS01X)
++#define GPIO63_LCD_LDD_9	MFP_CFG_DRV(GPIO63, AF1, DS01X)
++#define GPIO64_LCD_LDD_10	MFP_CFG_DRV(GPIO64, AF1, DS01X)
++#define GPIO65_LCD_LDD_11	MFP_CFG_DRV(GPIO65, AF1, DS01X)
++#define GPIO66_LCD_LDD_12	MFP_CFG_DRV(GPIO66, AF1, DS01X)
++#define GPIO67_LCD_LDD_13	MFP_CFG_DRV(GPIO67, AF1, DS01X)
++#define GPIO68_LCD_LDD_14	MFP_CFG_DRV(GPIO68, AF1, DS01X)
++#define GPIO69_LCD_LDD_15	MFP_CFG_DRV(GPIO69, AF1, DS01X)
++#define GPIO70_LCD_LDD_16	MFP_CFG_DRV(GPIO70, AF1, DS01X)
++#define GPIO71_LCD_LDD_17	MFP_CFG_DRV(GPIO71, AF1, DS01X)
++#define GPIO62_LCD_CS_N		MFP_CFG_DRV(GPIO62, AF2, DS01X)
++#define GPIO72_LCD_FCLK		MFP_CFG_DRV(GPIO72, AF1, DS01X)
++#define GPIO73_LCD_LCLK		MFP_CFG_DRV(GPIO73, AF1, DS01X)
++#define GPIO74_LCD_PCLK		MFP_CFG_DRV(GPIO74, AF1, DS02X)
++#define GPIO75_LCD_BIAS		MFP_CFG_DRV(GPIO75, AF1, DS01X)
++#define GPIO76_LCD_VSYNC	MFP_CFG_DRV(GPIO76, AF2, DS01X)
++
++#define GPIO15_LCD_CS_N		MFP_CFG_DRV(GPIO15,  AF2, DS01X)
++#define GPIO127_LCD_CS_N	MFP_CFG_DRV(GPIO127, AF1, DS01X)
++#define GPIO63_LCD_VSYNC	MFP_CFG_DRV(GPIO63,  AF2, DS01X)
++
++/* Mini-LCD */
++#define GPIO72_MLCD_FCLK	MFP_CFG_DRV(GPIO72, AF7, DS08X)
++#define GPIO73_MLCD_LCLK	MFP_CFG_DRV(GPIO73, AF7, DS08X)
++#define GPIO54_MLCD_LDD_0	MFP_CFG_DRV(GPIO54, AF7, DS08X)
++#define GPIO55_MLCD_LDD_1	MFP_CFG_DRV(GPIO55, AF7, DS08X)
++#define GPIO56_MLCD_LDD_2	MFP_CFG_DRV(GPIO56, AF7, DS08X)
++#define GPIO57_MLCD_LDD_3	MFP_CFG_DRV(GPIO57, AF7, DS08X)
++#define GPIO58_MLCD_LDD_4	MFP_CFG_DRV(GPIO58, AF7, DS08X)
++#define GPIO59_MLCD_LDD_5	MFP_CFG_DRV(GPIO59, AF7, DS08X)
++#define GPIO60_MLCD_LDD_6	MFP_CFG_DRV(GPIO60, AF7, DS08X)
++#define GPIO61_MLCD_LDD_7	MFP_CFG_DRV(GPIO61, AF7, DS08X)
++#define GPIO62_MLCD_LDD_8	MFP_CFG_DRV(GPIO62, AF7, DS08X)
++#define GPIO63_MLCD_LDD_9	MFP_CFG_DRV(GPIO63, AF7, DS08X)
++#define GPIO64_MLCD_LDD_10	MFP_CFG_DRV(GPIO64, AF7, DS08X)
++#define GPIO65_MLCD_LDD_11	MFP_CFG_DRV(GPIO65, AF7, DS08X)
++#define GPIO66_MLCD_LDD_12	MFP_CFG_DRV(GPIO66, AF7, DS08X)
++#define GPIO67_MLCD_LDD_13	MFP_CFG_DRV(GPIO67, AF7, DS08X)
++#define GPIO68_MLCD_LDD_14	MFP_CFG_DRV(GPIO68, AF7, DS08X)
++#define GPIO69_MLCD_LDD_15	MFP_CFG_DRV(GPIO69, AF7, DS08X)
++#define GPIO74_MLCD_PCLK	MFP_CFG_DRV(GPIO74, AF7, DS08X)
++#define GPIO75_MLCD_BIAS	MFP_CFG_DRV(GPIO75, AF2, DS08X)
++
++/* MMC1 */
++#define GPIO7_MMC1_CLK		MFP_CFG_LPM(GPIO7,  AF4, DRIVE_HIGH)
++#define GPIO8_MMC1_CMD		MFP_CFG_LPM(GPIO8,  AF4, DRIVE_HIGH)
++#define GPIO14_MMC1_CMD		MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
++#define GPIO15_MMC1_CMD		MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
++#define GPIO3_MMC1_DAT0		MFP_CFG_LPM(GPIO3,  AF4, DRIVE_HIGH)
++#define GPIO4_MMC1_DAT1		MFP_CFG_LPM(GPIO4,  AF4, DRIVE_HIGH)
++#define GPIO5_MMC1_DAT2		MFP_CFG_LPM(GPIO5,  AF4, DRIVE_HIGH)
++#define GPIO6_MMC1_DAT3		MFP_CFG_LPM(GPIO6,  AF4, DRIVE_HIGH)
++
++/* MMC2 */
++#define GPIO9_MMC2_DAT0		MFP_CFG_LPM(GPIO9,  AF4, PULL_HIGH)
++#define GPIO10_MMC2_DAT1	MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
++#define GPIO11_MMC2_DAT2	MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
++#define GPIO12_MMC2_DAT3	MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
++#define GPIO13_MMC2_CLK		MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
++#define GPIO14_MMC2_CMD		MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
++#define GPIO77_MMC2_DAT0	MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
++#define GPIO78_MMC2_DAT1	MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
++#define GPIO79_MMC2_DAT2	MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
++#define GPIO80_MMC2_DAT3	MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
++#define GPIO81_MMC2_CLK		MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
++#define GPIO82_MMC2_CMD		MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
++
++/* SSP1 */
++#define GPIO89_SSP1_EXTCLK	MFP_CFG(GPIO89, AF1)
++#define GPIO90_SSP1_SYSCLK	MFP_CFG(GPIO90, AF1)
++#define GPIO15_SSP1_SCLK	MFP_CFG(GPIO15, AF6)
++#define GPIO16_SSP1_FRM		MFP_CFG(GPIO16, AF2)
++#define GPIO33_SSP1_SCLK	MFP_CFG(GPIO33, AF5)
++#define GPIO34_SSP1_FRM		MFP_CFG(GPIO34, AF5)
++#define GPIO85_SSP1_SCLK	MFP_CFG(GPIO85, AF1)
++#define GPIO86_SSP1_FRM		MFP_CFG(GPIO86, AF1)
++#define GPIO18_SSP1_TXD		MFP_CFG(GPIO18, AF7)
++#define GPIO18_SSP1_RXD		MFP_CFG(GPIO18, AF2)
++#define GPIO20_SSP1_TXD		MFP_CFG(GPIO20, AF2)
++#define GPIO20_SSP1_RXD		MFP_CFG(GPIO20, AF7)
++#define GPIO35_SSP1_TXD		MFP_CFG(GPIO35, AF5)
++#define GPIO35_SSP1_RXD		MFP_CFG(GPIO35, AF4)
++#define GPIO36_SSP1_TXD		MFP_CFG(GPIO36, AF5)
++#define GPIO36_SSP1_RXD		MFP_CFG(GPIO36, AF6)
++#define GPIO87_SSP1_TXD		MFP_CFG(GPIO87, AF1)
++#define GPIO87_SSP1_RXD		MFP_CFG(GPIO87, AF6)
++#define GPIO88_SSP1_TXD		MFP_CFG(GPIO88, AF6)
++#define GPIO88_SSP1_RXD		MFP_CFG(GPIO88, AF1)
++
++/* SSP2 */
++#define GPIO29_SSP2_EXTCLK	MFP_CFG(GPIO29, AF2)
++#define GPIO23_SSP2_SCLK	MFP_CFG(GPIO23, AF2)
++#define GPIO17_SSP2_FRM		MFP_CFG(GPIO17, AF2)
++#define GPIO25_SSP2_SCLK	MFP_CFG(GPIO25, AF2)
++#define GPIO26_SSP2_FRM		MFP_CFG(GPIO26, AF2)
++#define GPIO33_SSP2_SCLK	MFP_CFG(GPIO33, AF6)
++#define GPIO34_SSP2_FRM		MFP_CFG(GPIO34, AF6)
++#define GPIO64_SSP2_SCLK	MFP_CFG(GPIO64, AF2)
++#define GPIO65_SSP2_FRM		MFP_CFG(GPIO65, AF2)
++#define GPIO19_SSP2_TXD		MFP_CFG(GPIO19, AF2)
++#define GPIO19_SSP2_RXD		MFP_CFG(GPIO19, AF7)
++#define GPIO24_SSP2_TXD		MFP_CFG(GPIO24, AF5)
++#define GPIO24_SSP2_RXD		MFP_CFG(GPIO24, AF4)
++#define GPIO27_SSP2_TXD		MFP_CFG(GPIO27, AF2)
++#define GPIO27_SSP2_RXD		MFP_CFG(GPIO27, AF5)
++#define GPIO28_SSP2_TXD		MFP_CFG(GPIO28, AF5)
++#define GPIO28_SSP2_RXD		MFP_CFG(GPIO28, AF2)
++#define GPIO35_SSP2_TXD		MFP_CFG(GPIO35, AF7)
++#define GPIO35_SSP2_RXD		MFP_CFG(GPIO35, AF6)
++#define GPIO66_SSP2_TXD		MFP_CFG(GPIO66, AF4)
++#define GPIO66_SSP2_RXD		MFP_CFG(GPIO66, AF2)
++#define GPIO67_SSP2_TXD		MFP_CFG(GPIO67, AF2)
++#define GPIO67_SSP2_RXD		MFP_CFG(GPIO67, AF4)
++#define GPIO36_SSP2_TXD		MFP_CFG(GPIO36, AF7)
++
++/* SSP3 */
++#define GPIO69_SSP3_FRM		MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
++#define GPIO68_SSP3_SCLK	MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
++#define GPIO92_SSP3_FRM		MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
++#define GPIO91_SSP3_SCLK	MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
++#define GPIO70_SSP3_TXD		MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
++#define GPIO70_SSP3_RXD		MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
++#define GPIO71_SSP3_TXD		MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
++#define GPIO71_SSP3_RXD		MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
++#define GPIO93_SSP3_TXD		MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
++#define GPIO93_SSP3_RXD		MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
++#define GPIO94_SSP3_TXD		MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
++#define GPIO94_SSP3_RXD		MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
++
++/* SSP4 */
++#define GPIO95_SSP4_SCLK	MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
++#define GPIO96_SSP4_FRM		MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
++#define GPIO97_SSP4_TXD		MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
++#define GPIO97_SSP4_RXD		MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
++#define GPIO98_SSP4_TXD		MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
++#define GPIO98_SSP4_RXD		MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
++
++/* UART1 */
++#define GPIO32_UART1_CTS	MFP_CFG_LPM(GPIO32,  AF2, FLOAT)
++#define GPIO37_UART1_CTS	MFP_CFG_LPM(GPIO37,  AF4, FLOAT)
++#define GPIO79_UART1_CTS	MFP_CFG_LPM(GPIO79,  AF1, FLOAT)
++#define GPIO84_UART1_CTS	MFP_CFG_LPM(GPIO84,  AF3, FLOAT)
++#define GPIO101_UART1_CTS	MFP_CFG_LPM(GPIO101, AF1, FLOAT)
++#define GPIO106_UART1_CTS	MFP_CFG_LPM(GPIO106, AF6, FLOAT)
++
++#define GPIO32_UART1_RTS	MFP_CFG_LPM(GPIO32,  AF4, FLOAT)
++#define GPIO37_UART1_RTS	MFP_CFG_LPM(GPIO37,  AF2, FLOAT)
++#define GPIO79_UART1_RTS	MFP_CFG_LPM(GPIO79,  AF3, FLOAT)
++#define GPIO84_UART1_RTS	MFP_CFG_LPM(GPIO84,  AF1, FLOAT)
++#define GPIO101_UART1_RTS	MFP_CFG_LPM(GPIO101, AF6, FLOAT)
++#define GPIO106_UART1_RTS	MFP_CFG_LPM(GPIO106, AF1, FLOAT)
++
++#define GPIO34_UART1_DSR	MFP_CFG_LPM(GPIO34,  AF2, FLOAT)
++#define GPIO36_UART1_DSR	MFP_CFG_LPM(GPIO36,  AF4, FLOAT)
++#define GPIO81_UART1_DSR	MFP_CFG_LPM(GPIO81,  AF1, FLOAT)
++#define GPIO83_UART1_DSR	MFP_CFG_LPM(GPIO83,  AF3, FLOAT)
++#define GPIO103_UART1_DSR	MFP_CFG_LPM(GPIO103, AF1, FLOAT)
++#define GPIO105_UART1_DSR	MFP_CFG_LPM(GPIO105, AF6, FLOAT)
++
++#define GPIO34_UART1_DTR	MFP_CFG_LPM(GPIO34,  AF4, FLOAT)
++#define GPIO36_UART1_DTR	MFP_CFG_LPM(GPIO36,  AF2, FLOAT)
++#define GPIO81_UART1_DTR	MFP_CFG_LPM(GPIO81,  AF3, FLOAT)
++#define GPIO83_UART1_DTR	MFP_CFG_LPM(GPIO83,  AF1, FLOAT)
++#define GPIO103_UART1_DTR	MFP_CFG_LPM(GPIO103, AF6, FLOAT)
++#define GPIO105_UART1_DTR	MFP_CFG_LPM(GPIO105, AF1, FLOAT)
++
++#define GPIO35_UART1_RI		MFP_CFG_LPM(GPIO35,  AF2, FLOAT)
++#define GPIO82_UART1_RI		MFP_CFG_LPM(GPIO82,  AF1, FLOAT)
++#define GPIO104_UART1_RI	MFP_CFG_LPM(GPIO104, AF1, FLOAT)
++
++#define GPIO33_UART1_DCD	MFP_CFG_LPM(GPIO33,  AF2, FLOAT)
++#define GPIO80_UART1_DCD	MFP_CFG_LPM(GPIO80,  AF1, FLOAT)
++#define GPIO102_UART1_DCD	MFP_CFG_LPM(GPIO102, AF1, FLOAT)
++
++#define GPIO30_UART1_RXD	MFP_CFG_LPM(GPIO30,  AF2, FLOAT)
++#define GPIO31_UART1_RXD	MFP_CFG_LPM(GPIO31,  AF4, FLOAT)
++#define GPIO77_UART1_RXD	MFP_CFG_LPM(GPIO77,  AF1, FLOAT)
++#define GPIO78_UART1_RXD	MFP_CFG_LPM(GPIO78,  AF3, FLOAT)
++#define GPIO99_UART1_RXD	MFP_CFG_LPM(GPIO99,  AF1, FLOAT)
++#define GPIO100_UART1_RXD	MFP_CFG_LPM(GPIO100, AF6, FLOAT)
++#define GPIO102_UART1_RXD	MFP_CFG_LPM(GPIO102, AF6, FLOAT)
++#define GPIO104_UART1_RXD	MFP_CFG_LPM(GPIO104, AF4, FLOAT)
++
++#define GPIO30_UART1_TXD	MFP_CFG_LPM(GPIO30,  AF4, FLOAT)
++#define GPIO31_UART1_TXD	MFP_CFG_LPM(GPIO31,  AF2, FLOAT)
++#define GPIO77_UART1_TXD	MFP_CFG_LPM(GPIO77,  AF3, FLOAT)
++#define GPIO78_UART1_TXD	MFP_CFG_LPM(GPIO78,  AF1, FLOAT)
++#define GPIO99_UART1_TXD	MFP_CFG_LPM(GPIO99,  AF6, FLOAT)
++#define GPIO100_UART1_TXD	MFP_CFG_LPM(GPIO100, AF1, FLOAT)
++#define GPIO102_UART1_TXD	MFP_CFG_LPM(GPIO102, AF4, FLOAT)
++
++/* UART2 */
++#define GPIO15_UART2_CTS	MFP_CFG_LPM(GPIO15,  AF3, FLOAT)
++#define GPIO16_UART2_CTS	MFP_CFG_LPM(GPIO16,  AF5, FLOAT)
++#define GPIO111_UART2_CTS	MFP_CFG_LPM(GPIO111, AF3, FLOAT)
++#define GPIO114_UART2_CTS	MFP_CFG_LPM(GPIO114, AF1, FLOAT)
++
++#define GPIO15_UART2_RTS	MFP_CFG_LPM(GPIO15,  AF4, FLOAT)
++#define GPIO16_UART2_RTS	MFP_CFG_LPM(GPIO16,  AF4, FLOAT)
++#define GPIO114_UART2_RTS	MFP_CFG_LPM(GPIO114, AF3, FLOAT)
++#define GPIO111_UART2_RTS	MFP_CFG_LPM(GPIO111, AF1, FLOAT)
++
++#define GPIO18_UART2_RXD	MFP_CFG_LPM(GPIO18,  AF5, FLOAT)
++#define GPIO19_UART2_RXD	MFP_CFG_LPM(GPIO19,  AF4, FLOAT)
++#define GPIO112_UART2_RXD	MFP_CFG_LPM(GPIO112, AF1, FLOAT)
++#define GPIO113_UART2_RXD	MFP_CFG_LPM(GPIO113, AF3, FLOAT)
++
++#define GPIO18_UART2_TXD	MFP_CFG_LPM(GPIO18,  AF4, FLOAT)
++#define GPIO19_UART2_TXD	MFP_CFG_LPM(GPIO19,  AF5, FLOAT)
++#define GPIO112_UART2_TXD	MFP_CFG_LPM(GPIO112, AF3, FLOAT)
++#define GPIO113_UART2_TXD	MFP_CFG_LPM(GPIO113, AF1, FLOAT)
++
++/* UART3 */
++#define GPIO91_UART3_CTS	MFP_CFG_LPM(GPIO91,  AF2, FLOAT)
++#define GPIO92_UART3_CTS	MFP_CFG_LPM(GPIO92,  AF4, FLOAT)
++#define GPIO107_UART3_CTS	MFP_CFG_LPM(GPIO107, AF1, FLOAT)
++#define GPIO108_UART3_CTS	MFP_CFG_LPM(GPIO108, AF3, FLOAT)
++
++#define GPIO91_UART3_RTS	MFP_CFG_LPM(GPIO91,  AF4, FLOAT)
++#define GPIO92_UART3_RTS	MFP_CFG_LPM(GPIO92,  AF2, FLOAT)
++#define GPIO107_UART3_RTS	MFP_CFG_LPM(GPIO107, AF3, FLOAT)
++#define GPIO108_UART3_RTS	MFP_CFG_LPM(GPIO108, AF1, FLOAT)
++
++#define GPIO7_UART3_RXD		MFP_CFG_LPM(GPIO7,   AF2, FLOAT)
++#define GPIO8_UART3_RXD		MFP_CFG_LPM(GPIO8,   AF6, FLOAT)
++#define GPIO93_UART3_RXD	MFP_CFG_LPM(GPIO93,  AF4, FLOAT)
++#define GPIO94_UART3_RXD	MFP_CFG_LPM(GPIO94,  AF2, FLOAT)
++#define GPIO109_UART3_RXD	MFP_CFG_LPM(GPIO109, AF3, FLOAT)
++#define GPIO110_UART3_RXD	MFP_CFG_LPM(GPIO110, AF1, FLOAT)
++
++#define GPIO7_UART3_TXD		MFP_CFG_LPM(GPIO7,   AF6, FLOAT)
++#define GPIO8_UART3_TXD		MFP_CFG_LPM(GPIO8,   AF2, FLOAT)
++#define GPIO93_UART3_TXD	MFP_CFG_LPM(GPIO93,  AF2, FLOAT)
++#define GPIO94_UART3_TXD	MFP_CFG_LPM(GPIO94,  AF4, FLOAT)
++#define GPIO109_UART3_TXD	MFP_CFG_LPM(GPIO109, AF1, FLOAT)
++#define GPIO110_UART3_TXD	MFP_CFG_LPM(GPIO110, AF3, FLOAT)
++
++/* USB Host */
++#define GPIO0_2_USBH_PEN	MFP_CFG(GPIO0_2, AF1)
++#define GPIO1_2_USBH_PWR	MFP_CFG(GPIO1_2, AF1)
++
++/* USB P3 */
++#define GPIO77_USB_P3_1		MFP_CFG(GPIO77,  AF2)
++#define GPIO78_USB_P3_2		MFP_CFG(GPIO78,  AF2)
++#define GPIO79_USB_P3_3		MFP_CFG(GPIO79,  AF2)
++#define GPIO80_USB_P3_4		MFP_CFG(GPIO80,  AF2)
++#define GPIO81_USB_P3_5		MFP_CFG(GPIO81,  AF2)
++#define GPIO82_USB_P3_6		MFP_CFG(GPIO82,  AF2)
++
++/* PWM */
++#define GPIO17_PWM0_OUT		MFP_CFG(GPIO17, AF1)
++#define GPIO18_PWM1_OUT		MFP_CFG(GPIO18, AF1)
++#define GPIO19_PWM2_OUT		MFP_CFG(GPIO19, AF1)
++#define GPIO20_PWM3_OUT		MFP_CFG(GPIO20, AF1)
++
++/* CIR */
++#define GPIO8_CIR_OUT		MFP_CFG(GPIO8, AF5)
++#define GPIO16_CIR_OUT		MFP_CFG(GPIO16, AF3)
++
++#define GPIO20_OW_DQ_IN		MFP_CFG(GPIO20, AF5)
++#define GPIO126_OW_DQ		MFP_CFG(GPIO126, AF2)
++
++#define GPIO0_DF_RDY		MFP_CFG(GPIO0, AF1)
++#define GPIO7_CLK_BYPASS_XSC	MFP_CFG(GPIO7, AF7)
++#define GPIO17_EXT_SYNC_MVT_0	MFP_CFG(GPIO17, AF6)
++#define GPIO18_EXT_SYNC_MVT_1	MFP_CFG(GPIO18, AF6)
++#define GPIO19_OST_CHOUT_MVT_0	MFP_CFG(GPIO19, AF6)
++#define GPIO20_OST_CHOUT_MVT_1	MFP_CFG(GPIO20, AF6)
++#define GPIO49_48M_CLK		MFP_CFG(GPIO49, AF2)
++#define GPIO126_EXT_CLK		MFP_CFG(GPIO126, AF3)
++#define GPIO127_CLK_BYPASS_GB	MFP_CFG(GPIO127, AF7)
++#define GPIO71_EXT_MATCH_MVT	MFP_CFG(GPIO71, AF6)
++
++#define GPIO3_uIO_IN		MFP_CFG(GPIO3, AF1)
++
++#define GPIO4_uSIM_CARD_STATE	MFP_CFG(GPIO4, AF1)
++#define GPIO5_uSIM_uCLK		MFP_CFG(GPIO5, AF1)
++#define GPIO6_uSIM_uRST		MFP_CFG(GPIO6, AF1)
++#define GPIO16_uSIM_UVS_0	MFP_CFG(GPIO16, AF1)
++
++#define GPIO9_SCIO		MFP_CFG(GPIO9, AF1)
++#define GPIO20_RTC_MVT		MFP_CFG(GPIO20, AF4)
++#define GPIO126_RTC_MVT		MFP_CFG(GPIO126, AF1)
++
++/*
++ * PXA300 specific MFP configurations
++ */
++#ifdef CONFIG_CPU_PXA300
++#define GPIO99_USB_P2_2		MFP_CFG(GPIO99, AF2)
++#define GPIO99_USB_P2_5		MFP_CFG(GPIO99, AF3)
++#define GPIO99_USB_P2_6		MFP_CFG(GPIO99, AF4)
++#define GPIO100_USB_P2_2	MFP_CFG(GPIO100, AF4)
++#define GPIO100_USB_P2_5	MFP_CFG(GPIO100, AF5)
++#define GPIO101_USB_P2_1	MFP_CFG(GPIO101, AF2)
++#define GPIO102_USB_P2_4	MFP_CFG(GPIO102, AF2)
++#define GPIO104_USB_P2_3	MFP_CFG(GPIO104, AF2)
++#define GPIO105_USB_P2_5	MFP_CFG(GPIO105, AF2)
++#define GPIO100_USB_P2_6	MFP_CFG(GPIO100, AF2)
++#define GPIO106_USB_P2_7	MFP_CFG(GPIO106, AF2)
++#define GPIO103_USB_P2_8	MFP_CFG(GPIO103, AF2)
++
++/* U2D UTMI */
++#define GPIO38_UTM_CLK		MFP_CFG(GPIO38,  AF1)
++#define GPIO26_U2D_RXERROR	MFP_CFG(GPIO26,  AF3)
++#define GPIO50_U2D_RXERROR	MFP_CFG(GPIO50,  AF1)
++#define GPIO89_U2D_RXERROR	MFP_CFG(GPIO89,  AF5)
++#define GPIO24_UTM_RXVALID	MFP_CFG(GPIO24,  AF3)
++#define GPIO48_UTM_RXVALID	MFP_CFG(GPIO48,  AF2)
++#define GPIO87_UTM_RXVALID	MFP_CFG(GPIO87,  AF5)
++#define GPIO25_UTM_RXACTIVE	MFP_CFG(GPIO25,  AF3)
++#define GPIO47_UTM_RXACTIVE	MFP_CFG(GPIO47,  AF2)
++#define GPIO49_UTM_RXACTIVE	MFP_CFG(GPIO49,  AF1)
++#define GPIO88_UTM_RXACTIVE	MFP_CFG(GPIO88,  AF5)
++#define GPIO53_UTM_TXREADY	MFP_CFG(GPIO53,  AF1)
++#define GPIO67_UTM_LINESTATE_0	MFP_CFG(GPIO67,  AF3)
++#define GPIO92_UTM_LINESTATE_0	MFP_CFG(GPIO92,  AF3)
++#define GPIO104_UTM_LINESTATE_0	MFP_CFG(GPIO104, AF3)
++#define GPIO109_UTM_LINESTATE_0	MFP_CFG(GPIO109, AF4)
++#define GPIO68_UTM_LINESTATE_1	MFP_CFG(GPIO68,  AF3)
++#define GPIO93_UTM_LINESTATE_1	MFP_CFG(GPIO93,  AF3)
++#define GPIO105_UTM_LINESTATE_1	MFP_CFG(GPIO105, AF3)
++#define GPIO27_U2D_OPMODE_0	MFP_CFG(GPIO27,  AF4)
++#define GPIO51_U2D_OPMODE_0	MFP_CFG(GPIO51,  AF2)
++#define GPIO90_U2D_OPMODE_0	MFP_CFG(GPIO90,  AF7)
++#define GPIO28_U2D_OPMODE_1	MFP_CFG(GPIO28,  AF4)
++#define GPIO52_U2D_OPMODE_1	MFP_CFG(GPIO52,  AF2)
++#define GPIO106_U2D_OPMODE_1	MFP_CFG(GPIO106, AF3)
++#define GPIO110_U2D_OPMODE_1	MFP_CFG(GPIO110, AF5)
++#define GPIO76_U2D_RESET	MFP_CFG(GPIO76,  AF1)
++#define GPIO95_U2D_RESET	MFP_CFG(GPIO95,  AF2)
++#define GPIO100_U2D_RESET	MFP_CFG(GPIO100, AF3)
++#define GPIO66_U2D_SUSPEND	MFP_CFG(GPIO66,  AF3)
++#define GPIO98_U2D_SUSPEND	MFP_CFG(GPIO98,  AF2)
++#define GPIO103_U2D_SUSPEND	MFP_CFG(GPIO103, AF3)
++#define GPIO65_U2D_TERM_SEL	MFP_CFG(GPIO65,  AF5)
++#define GPIO97_U2D_TERM_SEL	MFP_CFG(GPIO97,  AF3)
++#define GPIO102_U2D_TERM_SEL	MFP_CFG(GPIO102, AF5)
++#define GPIO29_U2D_TXVALID	MFP_CFG(GPIO29,  AF3)
++#define GPIO52_U2D_TXVALID	MFP_CFG(GPIO52,  AF4)
++#define GPIO69_U2D_TXVALID	MFP_CFG(GPIO69,  AF3)
++#define GPIO85_U2D_TXVALID	MFP_CFG(GPIO85,  AF7)
++#define GPIO64_U2D_XCVR_SEL	MFP_CFG(GPIO64,  AF5)
++#define GPIO96_U2D_XCVR_SEL	MFP_CFG(GPIO96,  AF3)
++#define GPIO101_U2D_XCVR_SEL	MFP_CFG(GPIO101, AF5)
++#define GPIO30_UTM_PHYDATA_0	MFP_CFG(GPIO30,  AF3)
++#define GPIO31_UTM_PHYDATA_1	MFP_CFG(GPIO31,  AF3)
++#define GPIO32_UTM_PHYDATA_2	MFP_CFG(GPIO32,  AF3)
++#define GPIO33_UTM_PHYDATA_3	MFP_CFG(GPIO33,  AF3)
++#define GPIO34_UTM_PHYDATA_4	MFP_CFG(GPIO34,  AF3)
++#define GPIO35_UTM_PHYDATA_5	MFP_CFG(GPIO35,  AF3)
++#define GPIO36_UTM_PHYDATA_6	MFP_CFG(GPIO36,  AF3)
++#define GPIO37_UTM_PHYDATA_7	MFP_CFG(GPIO37,  AF3)
++#define GPIO39_UTM_PHYDATA_0	MFP_CFG(GPIO39,  AF3)
++#define GPIO40_UTM_PHYDATA_1	MFP_CFG(GPIO40,  AF3)
++#define GPIO41_UTM_PHYDATA_2	MFP_CFG(GPIO41,  AF3)
++#define GPIO42_UTM_PHYDATA_3	MFP_CFG(GPIO42,  AF3)
++#define GPIO43_UTM_PHYDATA_4	MFP_CFG(GPIO43,  AF3)
++#define GPIO44_UTM_PHYDATA_5	MFP_CFG(GPIO44,  AF3)
++#define GPIO45_UTM_PHYDATA_6	MFP_CFG(GPIO45,  AF3)
++#define GPIO46_UTM_PHYDATA_7	MFP_CFG(GPIO46,  AF3)
++#endif /* CONFIG_CPU_PXA300 */
++
++/*
++ * PXA310 specific MFP configurations
++ */
++#ifdef CONFIG_CPU_PXA310
++/* USB P2 */
++#define GPIO36_USB_P2_1		MFP_CFG(GPIO36, AF1)
++#define GPIO30_USB_P2_2		MFP_CFG(GPIO30, AF1)
++#define GPIO35_USB_P2_3		MFP_CFG(GPIO35, AF1)
++#define GPIO32_USB_P2_4		MFP_CFG(GPIO32, AF1)
++#define GPIO34_USB_P2_5		MFP_CFG(GPIO34, AF1)
++#define GPIO31_USB_P2_6		MFP_CFG(GPIO31, AF1)
++
++/* MMC1 */
++#define GPIO24_MMC1_CMD		MFP_CFG(GPIO24, AF3)
++#define GPIO29_MMC1_DAT0	MFP_CFG(GPIO29, AF3)
++
++/* MMC3 */
++#define GPIO103_MMC3_CLK	MFP_CFG(GPIO103, AF2)
++#define GPIO105_MMC3_CMD	MFP_CFG(GPIO105, AF2)
++#define GPIO11_2_MMC3_CLK	MFP_CFG(GPIO11_2, AF1)
++#define GPIO12_2_MMC3_CMD	MFP_CFG(GPIO12_2, AF1)
++#define GPIO7_2_MMC3_DAT0	MFP_CFG(GPIO7_2, AF1)
++#define GPIO8_2_MMC3_DAT1	MFP_CFG(GPIO8_2, AF1)
++#define GPIO9_2_MMC3_DAT2	MFP_CFG(GPIO9_2, AF1)
++#define GPIO10_2_MMC3_DAT3	MFP_CFG(GPIO10_2, AF1)
++
++/* ULPI */
++#define GPIO38_ULPI_CLK		MFP_CFG(GPIO38, AF1)
++#define GPIO30_ULPI_DATA_OUT_0	MFP_CFG(GPIO30, AF3)
++#define GPIO31_ULPI_DATA_OUT_1	MFP_CFG(GPIO31, AF3)
++#define GPIO32_ULPI_DATA_OUT_2	MFP_CFG(GPIO32, AF3)
++#define GPIO33_ULPI_DATA_OUT_3	MFP_CFG(GPIO33, AF3)
++#define GPIO34_ULPI_DATA_OUT_4	MFP_CFG(GPIO34, AF3)
++#define GPIO35_ULPI_DATA_OUT_5	MFP_CFG(GPIO35, AF3)
++#define GPIO36_ULPI_DATA_OUT_6	MFP_CFG(GPIO36, AF3)
++#define GPIO37_ULPI_DATA_OUT_7	MFP_CFG(GPIO37, AF3)
++#define GPIO33_ULPI_OTG_INTR	MFP_CFG(GPIO33, AF1)
++
++#define ULPI_DIR	MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
++#define ULPI_NXT	MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
++#define ULPI_STP	MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
++#endif /* CONFIG_CPU_PXA310 */
++
++#endif /* __ASM_ARCH_MFP_PXA300_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa320.h linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa320.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa320.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa320.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,447 @@
++/*
++ * linux/include/asm-arm/arch-pxa/mfp-pxa320.h
++ *
++ * PXA320 specific MFP configuration definitions
++ *
++ * Copyright (C) 2007 Marvell International Ltd.
++ * 2007-08-21: eric miao <eric.miao@marvell.com>
++ *             initial version
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_MFP_PXA320_H
++#define __ASM_ARCH_MFP_PXA320_H
++
++#include <asm/arch/mfp.h>
++#include <asm/arch/mfp-pxa3xx.h>
++
++/* GPIO */
++#define GPIO46_GPIO		MFP_CFG(GPIO46, AF0)
++#define GPIO49_GPIO		MFP_CFG(GPIO49, AF0)
++#define GPIO50_GPIO		MFP_CFG(GPIO50, AF0)
++#define GPIO51_GPIO		MFP_CFG(GPIO51, AF0)
++#define GPIO52_GPIO		MFP_CFG(GPIO52, AF0)
++
++#define GPIO7_2_GPIO		MFP_CFG(GPIO7_2, AF0)
++#define GPIO8_2_GPIO		MFP_CFG(GPIO8_2, AF0)
++#define GPIO9_2_GPIO		MFP_CFG(GPIO9_2, AF0)
++#define GPIO10_2_GPIO		MFP_CFG(GPIO10_2, AF0)
++#define GPIO11_2_GPIO		MFP_CFG(GPIO11_2, AF0)
++#define GPIO12_2_GPIO		MFP_CFG(GPIO12_2, AF0)
++#define GPIO13_2_GPIO		MFP_CFG(GPIO13_2, AF0)
++#define GPIO14_2_GPIO		MFP_CFG(GPIO14_2, AF0)
++#define GPIO15_2_GPIO		MFP_CFG(GPIO15_2, AF0)
++#define GPIO16_2_GPIO		MFP_CFG(GPIO16_2, AF0)
++#define GPIO17_2_GPIO		MFP_CFG(GPIO17_2, AF0)
++
++/* Chip Select */
++#define GPIO4_nCS3		MFP_CFG(GPIO4, AF1)
++
++/* AC97 */
++#define GPIO34_AC97_SYSCLK	MFP_CFG(GPIO34, AF1)
++#define GPIO39_AC97_BITCLK	MFP_CFG(GPIO39, AF1)
++#define GPIO40_AC97_nACRESET	MFP_CFG(GPIO40, AF1)
++#define GPIO35_AC97_SDATA_IN_0	MFP_CFG(GPIO35, AF1)
++#define GPIO36_AC97_SDATA_IN_1	MFP_CFG(GPIO36, AF1)
++#define GPIO32_AC97_SDATA_IN_2	MFP_CFG(GPIO32, AF2)
++#define GPIO33_AC97_SDATA_IN_3	MFP_CFG(GPIO33, AF2)
++#define GPIO11_AC97_SDATA_IN_2	MFP_CFG(GPIO11, AF3)
++#define GPIO12_AC97_SDATA_IN_3	MFP_CFG(GPIO12, AF3)
++#define GPIO37_AC97_SDATA_OUT	MFP_CFG(GPIO37, AF1)
++#define GPIO38_AC97_SYNC	MFP_CFG(GPIO38, AF1)
++
++/* I2C */
++#define GPIO32_I2C_SCL		MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
++#define GPIO33_I2C_SDA		MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
++
++/* QCI */
++#define GPIO49_CI_DD_0		MFP_CFG_DRV(GPIO49, AF1, DS04X)
++#define GPIO50_CI_DD_1		MFP_CFG_DRV(GPIO50, AF1, DS04X)
++#define GPIO51_CI_DD_2		MFP_CFG_DRV(GPIO51, AF1, DS04X)
++#define GPIO52_CI_DD_3		MFP_CFG_DRV(GPIO52, AF1, DS04X)
++#define GPIO53_CI_DD_4		MFP_CFG_DRV(GPIO53, AF1, DS04X)
++#define GPIO54_CI_DD_5		MFP_CFG_DRV(GPIO54, AF1, DS04X)
++#define GPIO55_CI_DD_6		MFP_CFG_DRV(GPIO55, AF1, DS04X)
++#define GPIO56_CI_DD_7		MFP_CFG_DRV(GPIO56, AF0, DS04X)
++#define GPIO57_CI_DD_8		MFP_CFG_DRV(GPIO57, AF1, DS04X)
++#define GPIO58_CI_DD_9		MFP_CFG_DRV(GPIO58, AF1, DS04X)
++#define GPIO59_CI_MCLK		MFP_CFG_DRV(GPIO59, AF0, DS04X)
++#define GPIO60_CI_PCLK		MFP_CFG_DRV(GPIO60, AF0, DS04X)
++#define GPIO61_CI_HSYNC		MFP_CFG_DRV(GPIO61, AF0, DS04X)
++#define GPIO62_CI_VSYNC		MFP_CFG_DRV(GPIO62, AF0, DS04X)
++
++#define GPIO31_CIR_OUT		MFP_CFG(GPIO31, AF5)
++
++#define GPIO0_2_CLK_EXT		MFP_CFG(GPIO0_2, AF3)
++#define GPIO0_DRQ		MFP_CFG(GPIO0, AF2)
++#define GPIO11_EXT_SYNC0	MFP_CFG(GPIO11, AF5)
++#define GPIO12_EXT_SYNC1	MFP_CFG(GPIO12, AF6)
++#define GPIO0_2_HZ_CLK		MFP_CFG(GPIO0_2, AF1)
++#define GPIO14_HZ_CLK		MFP_CFG(GPIO14, AF4)
++#define GPIO30_ICP_RXD		MFP_CFG(GPIO30, AF1)
++#define GPIO31_ICP_TXD		MFP_CFG(GPIO31, AF1)
++
++#define GPIO83_KP_DKIN_0	MFP_CFG_LPM(GPIO83, AF3, FLOAT)
++#define GPIO84_KP_DKIN_1	MFP_CFG_LPM(GPIO84, AF3, FLOAT)
++#define GPIO85_KP_DKIN_2	MFP_CFG_LPM(GPIO85, AF3, FLOAT)
++#define GPIO86_KP_DKIN_3	MFP_CFG_LPM(GPIO86, AF3, FLOAT)
++
++#define GPIO105_KP_DKIN_0	MFP_CFG_LPM(GPIO105, AF2, FLOAT)
++#define GPIO106_KP_DKIN_1	MFP_CFG_LPM(GPIO106, AF2, FLOAT)
++#define GPIO107_KP_DKIN_2	MFP_CFG_LPM(GPIO107, AF2, FLOAT)
++#define GPIO108_KP_DKIN_3	MFP_CFG_LPM(GPIO108, AF2, FLOAT)
++#define GPIO109_KP_DKIN_4	MFP_CFG_LPM(GPIO109, AF2, FLOAT)
++#define GPIO110_KP_DKIN_5	MFP_CFG_LPM(GPIO110, AF2, FLOAT)
++#define GPIO111_KP_DKIN_6	MFP_CFG_LPM(GPIO111, AF2, FLOAT)
++#define GPIO112_KP_DKIN_7	MFP_CFG_LPM(GPIO112, AF2, FLOAT)
++
++#define GPIO113_KP_DKIN_0	MFP_CFG_LPM(GPIO113, AF2, FLOAT)
++#define GPIO114_KP_DKIN_1	MFP_CFG_LPM(GPIO114, AF2, FLOAT)
++#define GPIO115_KP_DKIN_2	MFP_CFG_LPM(GPIO115, AF2, FLOAT)
++#define GPIO116_KP_DKIN_3	MFP_CFG_LPM(GPIO116, AF2, FLOAT)
++#define GPIO117_KP_DKIN_4	MFP_CFG_LPM(GPIO117, AF2, FLOAT)
++#define GPIO118_KP_DKIN_5	MFP_CFG_LPM(GPIO118, AF2, FLOAT)
++#define GPIO119_KP_DKIN_6	MFP_CFG_LPM(GPIO119, AF2, FLOAT)
++#define GPIO120_KP_DKIN_7	MFP_CFG_LPM(GPIO120, AF2, FLOAT)
++
++#define GPIO127_KP_DKIN_0	MFP_CFG_LPM(GPIO127, AF2, FLOAT)
++#define GPIO126_KP_DKIN_1	MFP_CFG_LPM(GPIO126, AF2, FLOAT)
++
++#define GPIO2_2_KP_DKIN_0	MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
++#define GPIO3_2_KP_DKIN_1	MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
++#define GPIO125_KP_DKIN_2	MFP_CFG_LPM(GPIO125, AF2, FLOAT)
++#define GPIO124_KP_DKIN_3	MFP_CFG_LPM(GPIO124, AF2, FLOAT)
++#define GPIO123_KP_DKIN_4	MFP_CFG_LPM(GPIO123, AF2, FLOAT)
++#define GPIO122_KP_DKIN_5	MFP_CFG_LPM(GPIO122, AF2, FLOAT)
++#define GPIO121_KP_DKIN_6	MFP_CFG_LPM(GPIO121, AF2, FLOAT)
++#define GPIO4_2_KP_DKIN_7	MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
++
++#define GPIO113_KP_MKIN_0	MFP_CFG_LPM(GPIO113, AF1, FLOAT)
++#define GPIO114_KP_MKIN_1	MFP_CFG_LPM(GPIO114, AF1, FLOAT)
++#define GPIO115_KP_MKIN_2	MFP_CFG_LPM(GPIO115, AF1, FLOAT)
++#define GPIO116_KP_MKIN_3	MFP_CFG_LPM(GPIO116, AF1, FLOAT)
++#define GPIO117_KP_MKIN_4	MFP_CFG_LPM(GPIO117, AF1, FLOAT)
++#define GPIO118_KP_MKIN_5	MFP_CFG_LPM(GPIO118, AF1, FLOAT)
++#define GPIO119_KP_MKIN_6	MFP_CFG_LPM(GPIO119, AF1, FLOAT)
++#define GPIO120_KP_MKIN_7	MFP_CFG_LPM(GPIO120, AF1, FLOAT)
++
++#define GPIO83_KP_MKOUT_0	MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
++#define GPIO84_KP_MKOUT_1	MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
++#define GPIO85_KP_MKOUT_2	MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
++#define GPIO86_KP_MKOUT_3	MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
++#define GPIO13_KP_MKOUT_4	MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
++#define GPIO14_KP_MKOUT_5	MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
++
++#define GPIO121_KP_MKOUT_0	MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
++#define GPIO122_KP_MKOUT_1	MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
++#define GPIO123_KP_MKOUT_2	MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
++#define GPIO124_KP_MKOUT_3	MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
++#define GPIO125_KP_MKOUT_4	MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
++#define GPIO126_KP_MKOUT_5	MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
++#define GPIO127_KP_MKOUT_6	MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
++#define GPIO5_2_KP_MKOUT_7	MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
++
++/* LCD */
++#define GPIO6_2_LCD_LDD_0	MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
++#define GPIO7_2_LCD_LDD_1	MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
++#define GPIO8_2_LCD_LDD_2	MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
++#define GPIO9_2_LCD_LDD_3	MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
++#define GPIO10_2_LCD_LDD_4	MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
++#define GPIO11_2_LCD_LDD_5	MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
++#define GPIO12_2_LCD_LDD_6	MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
++#define GPIO13_2_LCD_LDD_7	MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
++#define GPIO63_LCD_LDD_8	MFP_CFG_DRV(GPIO63, AF1, DS01X)
++#define GPIO64_LCD_LDD_9	MFP_CFG_DRV(GPIO64, AF1, DS01X)
++#define GPIO65_LCD_LDD_10	MFP_CFG_DRV(GPIO65, AF1, DS01X)
++#define GPIO66_LCD_LDD_11	MFP_CFG_DRV(GPIO66, AF1, DS01X)
++#define GPIO67_LCD_LDD_12	MFP_CFG_DRV(GPIO67, AF1, DS01X)
++#define GPIO68_LCD_LDD_13	MFP_CFG_DRV(GPIO68, AF1, DS01X)
++#define GPIO69_LCD_LDD_14	MFP_CFG_DRV(GPIO69, AF1, DS01X)
++#define GPIO70_LCD_LDD_15	MFP_CFG_DRV(GPIO70, AF1, DS01X)
++#define GPIO71_LCD_LDD_16	MFP_CFG_DRV(GPIO71, AF1, DS01X)
++#define GPIO72_LCD_LDD_17	MFP_CFG_DRV(GPIO72, AF1, DS01X)
++#define GPIO73_LCD_CS_N		MFP_CFG_DRV(GPIO73, AF2, DS01X)
++#define GPIO74_LCD_VSYNC	MFP_CFG_DRV(GPIO74, AF2, DS01X)
++#define GPIO14_2_LCD_FCLK	MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
++#define GPIO15_2_LCD_LCLK	MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
++#define GPIO16_2_LCD_PCLK	MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
++#define GPIO17_2_LCD_BIAS	MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
++#define GPIO64_LCD_VSYNC	MFP_CFG_DRV(GPIO64, AF2, DS01X)
++#define GPIO63_LCD_CS_N		MFP_CFG_DRV(GPIO63, AF2, DS01X)
++
++#define GPIO6_2_MLCD_DD_0	MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
++#define GPIO7_2_MLCD_DD_1	MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
++#define GPIO8_2_MLCD_DD_2	MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
++#define GPIO9_2_MLCD_DD_3	MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
++#define GPIO10_2_MLCD_DD_4	MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
++#define GPIO11_2_MLCD_DD_5	MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
++#define GPIO12_2_MLCD_DD_6	MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
++#define GPIO13_2_MLCD_DD_7	MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
++#define GPIO63_MLCD_DD_8	MFP_CFG_DRV(GPIO63, AF7, DS08X)
++#define GPIO64_MLCD_DD_9	MFP_CFG_DRV(GPIO64, AF7, DS08X)
++#define GPIO65_MLCD_DD_10	MFP_CFG_DRV(GPIO65, AF7, DS08X)
++#define GPIO66_MLCD_DD_11	MFP_CFG_DRV(GPIO66, AF7, DS08X)
++#define GPIO67_MLCD_DD_12	MFP_CFG_DRV(GPIO67, AF7, DS08X)
++#define GPIO68_MLCD_DD_13	MFP_CFG_DRV(GPIO68, AF7, DS08X)
++#define GPIO69_MLCD_DD_14	MFP_CFG_DRV(GPIO69, AF7, DS08X)
++#define GPIO70_MLCD_DD_15	MFP_CFG_DRV(GPIO70, AF7, DS08X)
++#define GPIO71_MLCD_DD_16	MFP_CFG_DRV(GPIO71, AF7, DS08X)
++#define GPIO72_MLCD_DD_17	MFP_CFG_DRV(GPIO72, AF7, DS08X)
++#define GPIO73_MLCD_CS		MFP_CFG_DRV(GPIO73, AF7, DS08X)
++#define GPIO74_MLCD_VSYNC	MFP_CFG_DRV(GPIO74, AF7, DS08X)
++#define GPIO14_2_MLCD_FCLK	MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
++#define GPIO15_2_MLCD_LCLK	MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
++#define GPIO16_2_MLCD_PCLK	MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
++#define GPIO17_2_MLCD_BIAS	MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
++
++/* MMC1 */
++#define GPIO9_MMC1_CMD		MFP_CFG_LPM(GPIO9,  AF4, DRIVE_HIGH)
++#define GPIO22_MMC1_CLK		MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
++#define GPIO23_MMC1_CMD		MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
++#define GPIO30_MMC1_CLK		MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
++#define GPIO31_MMC1_CMD		MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
++#define GPIO5_MMC1_DAT0		MFP_CFG_LPM(GPIO5,  AF4, DRIVE_HIGH)
++#define GPIO6_MMC1_DAT1		MFP_CFG_LPM(GPIO6,  AF4, DRIVE_HIGH)
++#define GPIO7_MMC1_DAT2		MFP_CFG_LPM(GPIO7,  AF4, DRIVE_HIGH)
++#define GPIO8_MMC1_DAT3		MFP_CFG_LPM(GPIO8,  AF4, DRIVE_HIGH)
++#define GPIO18_MMC1_DAT0	MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
++#define GPIO19_MMC1_DAT1	MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
++#define GPIO20_MMC1_DAT2	MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
++#define GPIO21_MMC1_DAT3	MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
++
++#define GPIO28_MMC2_CLK		MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
++#define GPIO29_MMC2_CMD		MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
++#define GPIO30_MMC2_CLK		MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
++#define GPIO31_MMC2_CMD		MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
++#define GPIO79_MMC2_CLK		MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
++#define GPIO80_MMC2_CMD		MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
++
++#define GPIO5_MMC2_DAT0		MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
++#define GPIO6_MMC2_DAT1		MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
++#define GPIO7_MMC2_DAT2		MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
++#define GPIO8_MMC2_DAT3		MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
++#define GPIO24_MMC2_DAT0	MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
++#define GPIO75_MMC2_DAT0	MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
++#define GPIO25_MMC2_DAT1	MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
++#define GPIO76_MMC2_DAT1	MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
++#define GPIO26_MMC2_DAT2	MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
++#define GPIO77_MMC2_DAT2	MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
++#define GPIO27_MMC2_DAT3	MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
++#define GPIO78_MMC2_DAT3	MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
++
++/* 1-Wire */
++#define GPIO14_ONE_WIRE		MFP_CFG_LPM(GPIO14,  AF5, FLOAT)
++#define GPIO0_2_ONE_WIRE	MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
++
++/* SSP1 */
++#define GPIO87_SSP1_EXTCLK	MFP_CFG(GPIO87, AF1)
++#define GPIO88_SSP1_SYSCLK	MFP_CFG(GPIO88, AF1)
++#define GPIO83_SSP1_SCLK	MFP_CFG(GPIO83, AF1)
++#define GPIO84_SSP1_SFRM	MFP_CFG(GPIO84, AF1)
++#define GPIO85_SSP1_RXD		MFP_CFG(GPIO85, AF6)
++#define GPIO85_SSP1_TXD		MFP_CFG(GPIO85, AF1)
++#define GPIO86_SSP1_RXD		MFP_CFG(GPIO86, AF1)
++#define GPIO86_SSP1_TXD		MFP_CFG(GPIO86, AF6)
++
++/* SSP2 */
++#define GPIO39_SSP2_EXTCLK	MFP_CFG(GPIO39, AF2)
++#define GPIO40_SSP2_SYSCLK	MFP_CFG(GPIO40, AF2)
++#define GPIO12_SSP2_SCLK	MFP_CFG(GPIO12, AF2)
++#define GPIO35_SSP2_SCLK	MFP_CFG(GPIO35, AF2)
++#define GPIO36_SSP2_SFRM	MFP_CFG(GPIO36, AF2)
++#define GPIO37_SSP2_RXD		MFP_CFG(GPIO37, AF5)
++#define GPIO37_SSP2_TXD		MFP_CFG(GPIO37, AF2)
++#define GPIO38_SSP2_RXD		MFP_CFG(GPIO38, AF2)
++#define GPIO38_SSP2_TXD		MFP_CFG(GPIO38, AF5)
++
++#define GPIO69_SSP3_SCLK	MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
++#define GPIO70_SSP3_FRM		MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
++#define GPIO89_SSP3_SCLK	MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
++#define GPIO90_SSP3_FRM		MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
++#define GPIO71_SSP3_RXD		MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
++#define GPIO71_SSP3_TXD		MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
++#define GPIO72_SSP3_RXD		MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
++#define GPIO72_SSP3_TXD		MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
++#define GPIO91_SSP3_RXD		MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
++#define GPIO91_SSP3_TXD		MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
++#define GPIO92_SSP3_RXD		MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
++#define GPIO92_SSP3_TXD		MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
++
++#define GPIO93_SSP4_SCLK	MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
++#define GPIO94_SSP4_FRM		MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
++#define GPIO94_SSP4_RXD		MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
++#define GPIO95_SSP4_RXD		MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
++#define GPIO95_SSP4_TXD		MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
++#define GPIO96_SSP4_RXD		MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
++#define GPIO96_SSP4_TXD		MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
++
++/* UART1 */
++#define GPIO41_UART1_RXD	MFP_CFG_LPM(GPIO41, AF2, FLOAT)
++#define GPIO41_UART1_TXD	MFP_CFG_LPM(GPIO41, AF4, FLOAT)
++#define GPIO42_UART1_RXD	MFP_CFG_LPM(GPIO42, AF4, FLOAT)
++#define GPIO42_UART1_TXD	MFP_CFG_LPM(GPIO42, AF2, FLOAT)
++#define GPIO97_UART1_RXD	MFP_CFG_LPM(GPIO97, AF1, FLOAT)
++#define GPIO97_UART1_TXD	MFP_CFG_LPM(GPIO97, AF6, FLOAT)
++#define GPIO98_UART1_RXD	MFP_CFG_LPM(GPIO98, AF6, FLOAT)
++#define GPIO98_UART1_TXD	MFP_CFG_LPM(GPIO98, AF1, FLOAT)
++#define GPIO43_UART1_CTS	MFP_CFG_LPM(GPIO43, AF2, FLOAT)
++#define GPIO43_UART1_RTS	MFP_CFG_LPM(GPIO43, AF4, FLOAT)
++#define GPIO48_UART1_CTS	MFP_CFG_LPM(GPIO48, AF4, FLOAT)
++#define GPIO48_UART1_RTS	MFP_CFG_LPM(GPIO48, AF2, FLOAT)
++#define GPIO99_UART1_CTS	MFP_CFG_LPM(GPIO99, AF1, FLOAT)
++#define GPIO99_UART1_RTS	MFP_CFG_LPM(GPIO99, AF6, FLOAT)
++#define GPIO104_UART1_CTS	MFP_CFG_LPM(GPIO104, AF6, FLOAT)
++#define GPIO104_UART1_RTS	MFP_CFG_LPM(GPIO104, AF1, FLOAT)
++#define GPIO45_UART1_DTR	MFP_CFG_LPM(GPIO45, AF4, FLOAT)
++#define GPIO45_UART1_DSR	MFP_CFG_LPM(GPIO45, AF2, FLOAT)
++#define GPIO47_UART1_DTR	MFP_CFG_LPM(GPIO47, AF2, FLOAT)
++#define GPIO47_UART1_DSR	MFP_CFG_LPM(GPIO47, AF4, FLOAT)
++#define GPIO101_UART1_DTR	MFP_CFG_LPM(GPIO101, AF6, FLOAT)
++#define GPIO101_UART1_DSR	MFP_CFG_LPM(GPIO101, AF1, FLOAT)
++#define GPIO103_UART1_DTR	MFP_CFG_LPM(GPIO103, AF1, FLOAT)
++#define GPIO103_UART1_DSR	MFP_CFG_LPM(GPIO103, AF6, FLOAT)
++#define GPIO44_UART1_DCD	MFP_CFG_LPM(GPIO44, AF2, FLOAT)
++#define GPIO100_UART1_DCD	MFP_CFG_LPM(GPIO100, AF1, FLOAT)
++#define GPIO46_UART1_RI		MFP_CFG_LPM(GPIO46, AF2, FLOAT)
++#define GPIO102_UART1_RI	MFP_CFG_LPM(GPIO102, AF1, FLOAT)
++
++/* UART2 */
++#define GPIO109_UART2_CTS	MFP_CFG_LPM(GPIO109, AF3, FLOAT)
++#define GPIO109_UART2_RTS	MFP_CFG_LPM(GPIO109, AF1, FLOAT)
++#define GPIO112_UART2_CTS	MFP_CFG_LPM(GPIO112, AF1, FLOAT)
++#define GPIO112_UART2_RTS	MFP_CFG_LPM(GPIO112, AF3, FLOAT)
++#define GPIO110_UART2_RXD	MFP_CFG_LPM(GPIO110, AF1, FLOAT)
++#define GPIO110_UART2_TXD	MFP_CFG_LPM(GPIO110, AF3, FLOAT)
++#define GPIO111_UART2_RXD	MFP_CFG_LPM(GPIO111, AF3, FLOAT)
++#define GPIO111_UART2_TXD	MFP_CFG_LPM(GPIO111, AF1, FLOAT)
++
++/* UART3 */
++#define GPIO89_UART3_CTS	MFP_CFG_LPM(GPIO89, AF2, FLOAT)
++#define GPIO89_UART3_RTS	MFP_CFG_LPM(GPIO89, AF4, FLOAT)
++#define GPIO90_UART3_CTS	MFP_CFG_LPM(GPIO90, AF4, FLOAT)
++#define GPIO90_UART3_RTS	MFP_CFG_LPM(GPIO90, AF2, FLOAT)
++#define GPIO105_UART3_CTS	MFP_CFG_LPM(GPIO105, AF1, FLOAT)
++#define GPIO105_UART3_RTS	MFP_CFG_LPM(GPIO105, AF3, FLOAT)
++#define GPIO106_UART3_CTS	MFP_CFG_LPM(GPIO106, AF3, FLOAT)
++#define GPIO106_UART3_RTS	MFP_CFG_LPM(GPIO106, AF1, FLOAT)
++#define GPIO30_UART3_RXD	MFP_CFG_LPM(GPIO30, AF2, FLOAT)
++#define GPIO30_UART3_TXD	MFP_CFG_LPM(GPIO30, AF6, FLOAT)
++#define GPIO31_UART3_RXD	MFP_CFG_LPM(GPIO31, AF6, FLOAT)
++#define GPIO31_UART3_TXD	MFP_CFG_LPM(GPIO31, AF2, FLOAT)
++#define GPIO91_UART3_RXD	MFP_CFG_LPM(GPIO91, AF4, FLOAT)
++#define GPIO91_UART3_TXD	MFP_CFG_LPM(GPIO91, AF2, FLOAT)
++#define GPIO92_UART3_RXD	MFP_CFG_LPM(GPIO92, AF2, FLOAT)
++#define GPIO92_UART3_TXD	MFP_CFG_LPM(GPIO92, AF4, FLOAT)
++#define GPIO107_UART3_RXD	MFP_CFG_LPM(GPIO107, AF3, FLOAT)
++#define GPIO107_UART3_TXD	MFP_CFG_LPM(GPIO107, AF1, FLOAT)
++#define GPIO108_UART3_RXD	MFP_CFG_LPM(GPIO108, AF1, FLOAT)
++#define GPIO108_UART3_TXD	MFP_CFG_LPM(GPIO108, AF3, FLOAT)
++
++
++/* USB 2.0 UTMI */
++#define GPIO10_UTM_CLK		MFP_CFG(GPIO10, AF1)
++#define GPIO36_U2D_RXERROR	MFP_CFG(GPIO36, AF3)
++#define GPIO60_U2D_RXERROR	MFP_CFG(GPIO60, AF1)
++#define GPIO87_U2D_RXERROR	MFP_CFG(GPIO87, AF5)
++#define GPIO34_UTM_RXVALID	MFP_CFG(GPIO34, AF3)
++#define GPIO58_UTM_RXVALID	MFP_CFG(GPIO58, AF2)
++#define GPIO85_UTM_RXVALID	MFP_CFG(GPIO85, AF5)
++#define GPIO35_UTM_RXACTIVE	MFP_CFG(GPIO35, AF3)
++#define GPIO59_UTM_RXACTIVE	MFP_CFG(GPIO59, AF1)
++#define GPIO86_UTM_RXACTIVE	MFP_CFG(GPIO86, AF5)
++#define GPIO73_UTM_TXREADY	MFP_CFG(GPIO73, AF1)
++#define GPIO68_UTM_LINESTATE_0	MFP_CFG(GPIO68, AF3)
++#define GPIO90_UTM_LINESTATE_0	MFP_CFG(GPIO90, AF3)
++#define GPIO102_UTM_LINESTATE_0	MFP_CFG(GPIO102, AF3)
++#define GPIO107_UTM_LINESTATE_0	MFP_CFG(GPIO107, AF4)
++#define GPIO69_UTM_LINESTATE_1	MFP_CFG(GPIO69, AF3)
++#define GPIO91_UTM_LINESTATE_1	MFP_CFG(GPIO91, AF3)
++#define GPIO103_UTM_LINESTATE_1	MFP_CFG(GPIO103, AF3)
++
++#define GPIO41_U2D_PHYDATA_0	MFP_CFG(GPIO41, AF3)
++#define GPIO42_U2D_PHYDATA_1	MFP_CFG(GPIO42, AF3)
++#define GPIO43_U2D_PHYDATA_2	MFP_CFG(GPIO43, AF3)
++#define GPIO44_U2D_PHYDATA_3	MFP_CFG(GPIO44, AF3)
++#define GPIO45_U2D_PHYDATA_4	MFP_CFG(GPIO45, AF3)
++#define GPIO46_U2D_PHYDATA_5	MFP_CFG(GPIO46, AF3)
++#define GPIO47_U2D_PHYDATA_6	MFP_CFG(GPIO47, AF3)
++#define GPIO48_U2D_PHYDATA_7	MFP_CFG(GPIO48, AF3)
++
++#define GPIO49_U2D_PHYDATA_0	MFP_CFG(GPIO49, AF3)
++#define GPIO50_U2D_PHYDATA_1	MFP_CFG(GPIO50, AF3)
++#define GPIO51_U2D_PHYDATA_2	MFP_CFG(GPIO51, AF3)
++#define GPIO52_U2D_PHYDATA_3	MFP_CFG(GPIO52, AF3)
++#define GPIO53_U2D_PHYDATA_4	MFP_CFG(GPIO53, AF3)
++#define GPIO54_U2D_PHYDATA_5	MFP_CFG(GPIO54, AF3)
++#define GPIO55_U2D_PHYDATA_6	MFP_CFG(GPIO55, AF3)
++#define GPIO56_U2D_PHYDATA_7	MFP_CFG(GPIO56, AF3)
++
++#define GPIO37_U2D_OPMODE0	MFP_CFG(GPIO37, AF4)
++#define GPIO61_U2D_OPMODE0	MFP_CFG(GPIO61, AF2)
++#define GPIO88_U2D_OPMODE0	MFP_CFG(GPIO88, AF7)
++
++#define GPIO38_U2D_OPMODE1	MFP_CFG(GPIO38, AF4)
++#define GPIO62_U2D_OPMODE1	MFP_CFG(GPIO62, AF2)
++#define GPIO104_U2D_OPMODE1	MFP_CFG(GPIO104, AF4)
++#define GPIO108_U2D_OPMODE1	MFP_CFG(GPIO108, AF5)
++
++#define GPIO74_U2D_RESET	MFP_CFG(GPIO74, AF1)
++#define GPIO93_U2D_RESET	MFP_CFG(GPIO93, AF2)
++#define GPIO98_U2D_RESET	MFP_CFG(GPIO98, AF3)
++
++#define GPIO67_U2D_SUSPEND	MFP_CFG(GPIO67, AF3)
++#define GPIO96_U2D_SUSPEND	MFP_CFG(GPIO96, AF2)
++#define GPIO101_U2D_SUSPEND	MFP_CFG(GPIO101, AF3)
++
++#define GPIO66_U2D_TERM_SEL	MFP_CFG(GPIO66, AF5)
++#define GPIO95_U2D_TERM_SEL	MFP_CFG(GPIO95, AF3)
++#define GPIO97_U2D_TERM_SEL	MFP_CFG(GPIO97, AF7)
++#define GPIO100_U2D_TERM_SEL	MFP_CFG(GPIO100, AF5)
++
++#define GPIO39_U2D_TXVALID	MFP_CFG(GPIO39, AF4)
++#define GPIO70_U2D_TXVALID	MFP_CFG(GPIO70, AF5)
++#define GPIO83_U2D_TXVALID	MFP_CFG(GPIO83, AF7)
++
++#define GPIO65_U2D_XCVR_SEL	MFP_CFG(GPIO65, AF5)
++#define GPIO94_U2D_XCVR_SEL	MFP_CFG(GPIO94, AF3)
++#define GPIO99_U2D_XCVR_SEL	MFP_CFG(GPIO99, AF5)
++
++/* USB Host 1.1 */
++#define GPIO2_2_USBH_PEN	MFP_CFG(GPIO2_2, AF1)
++#define GPIO3_2_USBH_PWR	MFP_CFG(GPIO3_2, AF1)
++
++/* USB P2 */
++#define GPIO97_USB_P2_2		MFP_CFG(GPIO97, AF2)
++#define GPIO97_USB_P2_6		MFP_CFG(GPIO97, AF4)
++#define GPIO98_USB_P2_2		MFP_CFG(GPIO98, AF4)
++#define GPIO98_USB_P2_6		MFP_CFG(GPIO98, AF2)
++#define GPIO99_USB_P2_1		MFP_CFG(GPIO99, AF2)
++#define GPIO100_USB_P2_4	MFP_CFG(GPIO100, AF2)
++#define GPIO101_USB_P2_8	MFP_CFG(GPIO101, AF2)
++#define GPIO102_USB_P2_3	MFP_CFG(GPIO102, AF2)
++#define GPIO103_USB_P2_5	MFP_CFG(GPIO103, AF2)
++#define GPIO104_USB_P2_7	MFP_CFG(GPIO104, AF2)
++
++/* USB P3 */
++#define GPIO75_USB_P3_1		MFP_CFG(GPIO75, AF2)
++#define GPIO76_USB_P3_2		MFP_CFG(GPIO76, AF2)
++#define GPIO77_USB_P3_3		MFP_CFG(GPIO77, AF2)
++#define GPIO78_USB_P3_4		MFP_CFG(GPIO78, AF2)
++#define GPIO79_USB_P3_5		MFP_CFG(GPIO79, AF2)
++#define GPIO80_USB_P3_6		MFP_CFG(GPIO80, AF2)
++
++#define GPIO13_CHOUT0		MFP_CFG(GPIO13, AF6)
++#define GPIO14_CHOUT1		MFP_CFG(GPIO14, AF6)
++
++#define GPIO2_RDY		MFP_CFG(GPIO2, AF1)
++#define GPIO5_NPIOR		MFP_CFG(GPIO5, AF3)
++
++#define GPIO11_PWM0_OUT		MFP_CFG(GPIO11, AF1)
++#define GPIO12_PWM1_OUT		MFP_CFG(GPIO12, AF1)
++#define GPIO13_PWM2_OUT		MFP_CFG(GPIO13, AF1)
++#define GPIO14_PWM3_OUT		MFP_CFG(GPIO14, AF1)
++
++#endif /* __ASM_ARCH_MFP_PXA320_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa3xx.h linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa3xx.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa3xx.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa3xx.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,252 @@
++#ifndef __ASM_ARCH_MFP_PXA3XX_H
++#define __ASM_ARCH_MFP_PXA3XX_H
++
++#define MFPR_BASE	(0x40e10000)
++#define MFPR_SIZE	(PAGE_SIZE)
++
++/* MFPR register bit definitions */
++#define MFPR_PULL_SEL		(0x1 << 15)
++#define MFPR_PULLUP_EN		(0x1 << 14)
++#define MFPR_PULLDOWN_EN	(0x1 << 13)
++#define MFPR_SLEEP_SEL		(0x1 << 9)
++#define MFPR_SLEEP_OE_N		(0x1 << 7)
++#define MFPR_EDGE_CLEAR		(0x1 << 6)
++#define MFPR_EDGE_FALL_EN	(0x1 << 5)
++#define MFPR_EDGE_RISE_EN	(0x1 << 4)
++
++#define MFPR_SLEEP_DATA(x)	((x) << 8)
++#define MFPR_DRIVE(x)		(((x) & 0x7) << 10)
++#define MFPR_AF_SEL(x)		(((x) & 0x7) << 0)
++
++#define MFPR_EDGE_NONE		(0)
++#define MFPR_EDGE_RISE		(MFPR_EDGE_RISE_EN)
++#define MFPR_EDGE_FALL		(MFPR_EDGE_FALL_EN)
++#define MFPR_EDGE_BOTH		(MFPR_EDGE_RISE | MFPR_EDGE_FALL)
++
++/*
++ * Table that determines the low power modes outputs, with actual settings
++ * used in parentheses for don't-care values. Except for the float output,
++ * the configured driven and pulled levels match, so if there is a need for
++ * non-LPM pulled output, the same configuration could probably be used.
++ *
++ * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
++ *                 (bit 7)    (bit 8)    (bit 14)     (bit 13)   (bit 15)
++ *
++ * Input            0          X(0)        X(0)        X(0)       0
++ * Drive 0          0          0           0           X(1)       0
++ * Drive 1          0          1           X(1)        0	  0
++ * Pull hi (1)      1          X(1)        1           0	  0
++ * Pull lo (0)      1          X(0)        0           1	  0
++ * Z (float)        1          X(0)        0           0	  0
++ */
++#define MFPR_LPM_INPUT		(0)
++#define MFPR_LPM_DRIVE_LOW	(MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
++#define MFPR_LPM_DRIVE_HIGH    	(MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
++#define MFPR_LPM_PULL_LOW      	(MFPR_LPM_DRIVE_LOW  | MFPR_SLEEP_OE_N)
++#define MFPR_LPM_PULL_HIGH     	(MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
++#define MFPR_LPM_FLOAT         	(MFPR_SLEEP_OE_N)
++#define MFPR_LPM_MASK		(0xe080)
++
++/*
++ * The pullup and pulldown state of the MFP pin at run mode is by default
++ * determined by the selected alternate function. In case that some buggy
++ * devices need to override this default behavior,  the definitions below
++ * indicates the setting of corresponding MFPR bits
++ *
++ * Definition       pull_sel  pullup_en  pulldown_en
++ * MFPR_PULL_NONE       0         0        0
++ * MFPR_PULL_LOW        1         0        1
++ * MFPR_PULL_HIGH       1         1        0
++ * MFPR_PULL_BOTH       1         1        1
++ */
++#define MFPR_PULL_NONE		(0)
++#define MFPR_PULL_LOW		(MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
++#define MFPR_PULL_BOTH		(MFPR_PULL_LOW | MFPR_PULLUP_EN)
++#define MFPR_PULL_HIGH		(MFPR_PULL_SEL | MFPR_PULLUP_EN)
++
++/* PXA3xx common MFP configurations - processor specific ones defined
++ * in mfp-pxa300.h and mfp-pxa320.h
++ */
++#define GPIO0_GPIO		MFP_CFG(GPIO0, AF0)
++#define GPIO1_GPIO		MFP_CFG(GPIO1, AF0)
++#define GPIO2_GPIO		MFP_CFG(GPIO2, AF0)
++#define GPIO3_GPIO		MFP_CFG(GPIO3, AF0)
++#define GPIO4_GPIO		MFP_CFG(GPIO4, AF0)
++#define GPIO5_GPIO		MFP_CFG(GPIO5, AF0)
++#define GPIO6_GPIO		MFP_CFG(GPIO6, AF0)
++#define GPIO7_GPIO		MFP_CFG(GPIO7, AF0)
++#define GPIO8_GPIO		MFP_CFG(GPIO8, AF0)
++#define GPIO9_GPIO		MFP_CFG(GPIO9, AF0)
++#define GPIO10_GPIO		MFP_CFG(GPIO10, AF0)
++#define GPIO11_GPIO		MFP_CFG(GPIO11, AF0)
++#define GPIO12_GPIO		MFP_CFG(GPIO12, AF0)
++#define GPIO13_GPIO		MFP_CFG(GPIO13, AF0)
++#define GPIO14_GPIO		MFP_CFG(GPIO14, AF0)
++#define GPIO15_GPIO		MFP_CFG(GPIO15, AF0)
++#define GPIO16_GPIO		MFP_CFG(GPIO16, AF0)
++#define GPIO17_GPIO		MFP_CFG(GPIO17, AF0)
++#define GPIO18_GPIO		MFP_CFG(GPIO18, AF0)
++#define GPIO19_GPIO		MFP_CFG(GPIO19, AF0)
++#define GPIO20_GPIO		MFP_CFG(GPIO20, AF0)
++#define GPIO21_GPIO		MFP_CFG(GPIO21, AF0)
++#define GPIO22_GPIO		MFP_CFG(GPIO22, AF0)
++#define GPIO23_GPIO		MFP_CFG(GPIO23, AF0)
++#define GPIO24_GPIO		MFP_CFG(GPIO24, AF0)
++#define GPIO25_GPIO		MFP_CFG(GPIO25, AF0)
++#define GPIO26_GPIO		MFP_CFG(GPIO26, AF0)
++#define GPIO27_GPIO		MFP_CFG(GPIO27, AF0)
++#define GPIO28_GPIO		MFP_CFG(GPIO28, AF0)
++#define GPIO29_GPIO		MFP_CFG(GPIO29, AF0)
++#define GPIO30_GPIO		MFP_CFG(GPIO30, AF0)
++#define GPIO31_GPIO		MFP_CFG(GPIO31, AF0)
++#define GPIO32_GPIO		MFP_CFG(GPIO32, AF0)
++#define GPIO33_GPIO		MFP_CFG(GPIO33, AF0)
++#define GPIO34_GPIO		MFP_CFG(GPIO34, AF0)
++#define GPIO35_GPIO		MFP_CFG(GPIO35, AF0)
++#define GPIO36_GPIO		MFP_CFG(GPIO36, AF0)
++#define GPIO37_GPIO		MFP_CFG(GPIO37, AF0)
++#define GPIO38_GPIO		MFP_CFG(GPIO38, AF0)
++#define GPIO39_GPIO		MFP_CFG(GPIO39, AF0)
++#define GPIO40_GPIO		MFP_CFG(GPIO40, AF0)
++#define GPIO41_GPIO		MFP_CFG(GPIO41, AF0)
++#define GPIO42_GPIO		MFP_CFG(GPIO42, AF0)
++#define GPIO43_GPIO		MFP_CFG(GPIO43, AF0)
++#define GPIO44_GPIO		MFP_CFG(GPIO44, AF0)
++#define GPIO45_GPIO		MFP_CFG(GPIO45, AF0)
++
++#define GPIO47_GPIO		MFP_CFG(GPIO47, AF0)
++#define GPIO48_GPIO		MFP_CFG(GPIO48, AF0)
++
++#define GPIO53_GPIO		MFP_CFG(GPIO53, AF0)
++#define GPIO54_GPIO		MFP_CFG(GPIO54, AF0)
++#define GPIO55_GPIO		MFP_CFG(GPIO55, AF0)
++
++#define GPIO57_GPIO		MFP_CFG(GPIO57, AF0)
++
++#define GPIO63_GPIO		MFP_CFG(GPIO63, AF0)
++#define GPIO64_GPIO		MFP_CFG(GPIO64, AF0)
++#define GPIO65_GPIO		MFP_CFG(GPIO65, AF0)
++#define GPIO66_GPIO		MFP_CFG(GPIO66, AF0)
++#define GPIO67_GPIO		MFP_CFG(GPIO67, AF0)
++#define GPIO68_GPIO		MFP_CFG(GPIO68, AF0)
++#define GPIO69_GPIO		MFP_CFG(GPIO69, AF0)
++#define GPIO70_GPIO		MFP_CFG(GPIO70, AF0)
++#define GPIO71_GPIO		MFP_CFG(GPIO71, AF0)
++#define GPIO72_GPIO		MFP_CFG(GPIO72, AF0)
++#define GPIO73_GPIO		MFP_CFG(GPIO73, AF0)
++#define GPIO74_GPIO		MFP_CFG(GPIO74, AF0)
++#define GPIO75_GPIO		MFP_CFG(GPIO75, AF0)
++#define GPIO76_GPIO		MFP_CFG(GPIO76, AF0)
++#define GPIO77_GPIO		MFP_CFG(GPIO77, AF0)
++#define GPIO78_GPIO		MFP_CFG(GPIO78, AF0)
++#define GPIO79_GPIO		MFP_CFG(GPIO79, AF0)
++#define GPIO80_GPIO		MFP_CFG(GPIO80, AF0)
++#define GPIO81_GPIO		MFP_CFG(GPIO81, AF0)
++#define GPIO82_GPIO		MFP_CFG(GPIO82, AF0)
++#define GPIO83_GPIO		MFP_CFG(GPIO83, AF0)
++#define GPIO84_GPIO		MFP_CFG(GPIO84, AF0)
++#define GPIO85_GPIO		MFP_CFG(GPIO85, AF0)
++#define GPIO86_GPIO		MFP_CFG(GPIO86, AF0)
++#define GPIO87_GPIO		MFP_CFG(GPIO87, AF0)
++#define GPIO88_GPIO		MFP_CFG(GPIO88, AF0)
++#define GPIO89_GPIO		MFP_CFG(GPIO89, AF0)
++#define GPIO90_GPIO		MFP_CFG(GPIO90, AF0)
++#define GPIO91_GPIO		MFP_CFG(GPIO91, AF0)
++#define GPIO92_GPIO		MFP_CFG(GPIO92, AF0)
++#define GPIO93_GPIO		MFP_CFG(GPIO93, AF0)
++#define GPIO94_GPIO		MFP_CFG(GPIO94, AF0)
++#define GPIO95_GPIO		MFP_CFG(GPIO95, AF0)
++#define GPIO96_GPIO		MFP_CFG(GPIO96, AF0)
++#define GPIO97_GPIO		MFP_CFG(GPIO97, AF0)
++#define GPIO98_GPIO		MFP_CFG(GPIO98, AF0)
++#define GPIO99_GPIO		MFP_CFG(GPIO99, AF0)
++#define GPIO100_GPIO		MFP_CFG(GPIO100, AF0)
++#define GPIO101_GPIO		MFP_CFG(GPIO101, AF0)
++#define GPIO102_GPIO		MFP_CFG(GPIO102, AF0)
++#define GPIO103_GPIO		MFP_CFG(GPIO103, AF0)
++#define GPIO104_GPIO		MFP_CFG(GPIO104, AF0)
++#define GPIO105_GPIO		MFP_CFG(GPIO105, AF0)
++#define GPIO106_GPIO		MFP_CFG(GPIO106, AF0)
++#define GPIO107_GPIO		MFP_CFG(GPIO107, AF0)
++#define GPIO108_GPIO		MFP_CFG(GPIO108, AF0)
++#define GPIO109_GPIO		MFP_CFG(GPIO109, AF0)
++#define GPIO110_GPIO		MFP_CFG(GPIO110, AF0)
++#define GPIO111_GPIO		MFP_CFG(GPIO111, AF0)
++#define GPIO112_GPIO		MFP_CFG(GPIO112, AF0)
++#define GPIO113_GPIO		MFP_CFG(GPIO113, AF0)
++#define GPIO114_GPIO		MFP_CFG(GPIO114, AF0)
++#define GPIO115_GPIO		MFP_CFG(GPIO115, AF0)
++#define GPIO116_GPIO		MFP_CFG(GPIO116, AF0)
++#define GPIO117_GPIO		MFP_CFG(GPIO117, AF0)
++#define GPIO118_GPIO		MFP_CFG(GPIO118, AF0)
++#define GPIO119_GPIO		MFP_CFG(GPIO119, AF0)
++#define GPIO120_GPIO		MFP_CFG(GPIO120, AF0)
++#define GPIO121_GPIO		MFP_CFG(GPIO121, AF0)
++#define GPIO122_GPIO		MFP_CFG(GPIO122, AF0)
++#define GPIO123_GPIO		MFP_CFG(GPIO123, AF0)
++#define GPIO124_GPIO		MFP_CFG(GPIO124, AF0)
++#define GPIO125_GPIO		MFP_CFG(GPIO125, AF0)
++#define GPIO126_GPIO		MFP_CFG(GPIO126, AF0)
++#define GPIO127_GPIO		MFP_CFG(GPIO127, AF0)
++
++#define GPIO0_2_GPIO		MFP_CFG(GPIO0_2, AF0)
++#define GPIO1_2_GPIO		MFP_CFG(GPIO1_2, AF0)
++#define GPIO2_2_GPIO		MFP_CFG(GPIO2_2, AF0)
++#define GPIO3_2_GPIO		MFP_CFG(GPIO3_2, AF0)
++#define GPIO4_2_GPIO		MFP_CFG(GPIO4_2, AF0)
++#define GPIO5_2_GPIO		MFP_CFG(GPIO5_2, AF0)
++#define GPIO6_2_GPIO		MFP_CFG(GPIO6_2, AF0)
++
++/*
++ * each MFP pin will have a MFPR register, since the offset of the
++ * register varies between processors, the processor specific code
++ * should initialize the pin offsets by pxa3xx_mfp_init_addr()
++ *
++ * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
++ * structure, which represents a range of MFP pins from "start" to
++ * "end", with the offset begining at "offset", to define a single
++ * pin, let "end" = -1
++ *
++ * use
++ *
++ * MFP_ADDR_X() to define a range of pins
++ * MFP_ADDR()   to define a single pin
++ * MFP_ADDR_END to signal the end of pin offset definitions
++ */
++struct pxa3xx_mfp_addr_map {
++	unsigned int	start;
++	unsigned int	end;
++	unsigned long	offset;
++};
++
++#define MFP_ADDR_X(start, end, offset) \
++	{ MFP_PIN_##start, MFP_PIN_##end, offset }
++
++#define MFP_ADDR(pin, offset) \
++	{ MFP_PIN_##pin, -1, offset }
++
++#define MFP_ADDR_END	{ MFP_PIN_INVALID, 0 }
++
++/*
++ * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
++ * to the MFPR register
++ */
++unsigned long pxa3xx_mfp_read(int mfp);
++void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
++
++/*
++ * pxa3xx_mfp_config - configure the MFPR registers
++ *
++ * used by board specific initialization code
++ */
++void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
++
++/*
++ * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
++ * index and MFPR register offset
++ *
++ * used by processor specific code
++ */
++void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
++void __init pxa3xx_init_mfp(void);
++#endif /* __ASM_ARCH_MFP_PXA3XX_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mmc.h linux-2.6.25-rc4/include/asm-arm/arch/mmc.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mmc.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/mmc.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,23 @@
++#ifndef ASMARM_ARCH_MMC_H
++#define ASMARM_ARCH_MMC_H
++
++#include <linux/mmc/host.h>
++#include <linux/interrupt.h>
++
++struct device;
++struct mmc_host;
++
++struct pxamci_platform_data {
++	unsigned int ocr_mask;			/* available voltages */
++	unsigned long detect_delay;		/* delay in jiffies before detecting cards after interrupt */
++	int (*init)(struct device *, irq_handler_t , void *);
++	int (*get_ro)(struct device *);
++	void (*setpower)(struct device *, unsigned int);
++	void (*exit)(struct device *, void *);
++};
++
++extern void pxa_set_mci_info(struct pxamci_platform_data *info);
++extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
++extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mtd-xip.h linux-2.6.25-rc4/include/asm-arm/arch/mtd-xip.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mtd-xip.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/mtd-xip.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,37 @@
++/*
++ * MTD primitives for XIP support. Architecture specific functions
++ *
++ * Do not include this file directly. It's included from linux/mtd/xip.h
++ * 
++ * Author:	Nicolas Pitre
++ * Created:	Nov 2, 2004
++ * Copyright:	(C) 2004 MontaVista Software, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
++ */
++
++#ifndef __ARCH_PXA_MTD_XIP_H__
++#define __ARCH_PXA_MTD_XIP_H__
++
++#include <asm/arch/pxa-regs.h>
++
++#define xip_irqpending()	(ICIP & ICMR)
++
++/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
++#define xip_currtime()		(OSCR)
++#define xip_elapsed_since(x)	(signed)((OSCR - (x)) / 4)
++
++/*
++ * xip_cpu_idle() is used when waiting for a delay equal or larger than
++ * the system timer tick period.  This should put the CPU into idle mode
++ * to save power and to be woken up only when some interrupts are pending.
++ * As above, this should not rely upon standard kernel code.
++ */
++
++#define xip_cpu_idle()  asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
++
++#endif /* __ARCH_PXA_MTD_XIP_H__ */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/ohci.h linux-2.6.25-rc4/include/asm-arm/arch/ohci.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/ohci.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/ohci.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,20 @@
++#ifndef ASMARM_ARCH_OHCI_H
++#define ASMARM_ARCH_OHCI_H
++
++struct device;
++
++struct pxaohci_platform_data {
++	int (*init)(struct device *);
++	void (*exit)(struct device *);
++
++	int port_mode;
++#define PMM_NPS_MODE           1
++#define PMM_GLOBAL_MODE        2
++#define PMM_PERPORT_MODE       3
++
++	int power_budget;
++};
++
++extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pcm027.h linux-2.6.25-rc4/include/asm-arm/arch/pcm027.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pcm027.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pcm027.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,75 @@
++/*
++ * linux/include/asm-arm/arch-pxa/pcm027.h
++ *
++ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
++ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++/*
++ * Definitions of CPU card resources only
++ */
++
++/* I2C RTC */
++#define PCM027_RTC_IRQ_GPIO	0
++#define PCM027_RTC_IRQ		IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
++#define PCM027_RTC_IRQ_EDGE	IRQ_TYPE_EDGE_FALLING
++#define ADR_PCM027_RTC		0x51	/* I2C address */
++
++/* I2C EEPROM */
++#define ADR_PCM027_EEPROM	0x54	/* I2C address */
++
++/* Ethernet chip (SMSC91C111) */
++#define PCM027_ETH_IRQ_GPIO	52
++#define PCM027_ETH_IRQ		IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
++#define PCM027_ETH_IRQ_EDGE	IRQ_TYPE_EDGE_RISING
++#define PCM027_ETH_PHYS		PXA_CS5_PHYS
++#define PCM027_ETH_SIZE		(1*1024*1024)
++
++/* CAN controller SJA1000 (unsupported yet) */
++#define PCM027_CAN_IRQ_GPIO	114
++#define PCM027_CAN_IRQ		IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
++#define PCM027_CAN_IRQ_EDGE	IRQ_TYPE_EDGE_FALLING
++#define PCM027_CAN_PHYS		0x22000000
++#define PCM027_CAN_SIZE		0x100
++
++/* SPI GPIO expander (unsupported yet) */
++#define PCM027_EGPIO_IRQ_GPIO	27
++#define PCM027_EGPIO_IRQ	IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
++#define PCM027_EGPIO_IRQ_EDGE	IRQ_TYPE_EDGE_FALLING
++#define PCM027_EGPIO_CS		24
++/*
++ * TODO: Switch this pin from dedicated usage to GPIO if
++ * more than the MAX7301 device is connected to this SPI bus
++ */
++#define PCM027_EGPIO_CS_MODE	GPIO24_SFRM_MD
++
++/* Flash memory */
++#define PCM027_FLASH_PHYS	0x00000000
++#define PCM027_FLASH_SIZE	0x02000000
++
++/* onboard LEDs connected to GPIO */
++#define PCM027_LED_CPU		90
++#define PCM027_LED_HEARD_BEAT	91
++
++/*
++ * This CPU module needs a baseboard to work. After basic initializing
++ * its own devices, it calls baseboard's init function.
++ * TODO: Add your own basebaord init function and call it from
++ * inside pcm027_init(). This example here is for the developmen board.
++ * Refer pcm990-baseboard.c
++ */
++extern void pcm990_baseboard_init(void);
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pcm990_baseboard.h linux-2.6.25-rc4/include/asm-arm/arch/pcm990_baseboard.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pcm990_baseboard.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pcm990_baseboard.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,275 @@
++/*
++ * include/asm-arm/arch-pxa/pcm990_baseboard.h
++ *
++ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
++ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <asm/arch/pcm027.h>
++
++/*
++ * definitions relevant only when the PCM-990
++ * development base board is in use
++ */
++
++/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
++#define PCM990_CTRL_INT_IRQ_GPIO	9
++#define PCM990_CTRL_INT_IRQ		IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
++#define PCM990_CTRL_INT_IRQ_EDGE	IRQT_RISING
++#define PCM990_CTRL_PHYS		PXA_CS1_PHYS	/* 16-Bit */
++#define PCM990_CTRL_BASE		0xea000000
++#define PCM990_CTRL_SIZE		(1*1024*1024)
++
++#define PCM990_CTRL_PWR_IRQ_GPIO	14
++#define PCM990_CTRL_PWR_IRQ		IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
++#define PCM990_CTRL_PWR_IRQ_EDGE	IRQT_RISING
++
++/* visible CPLD (U7) registers */
++#define PCM990_CTRL_REG0	0x0000	/* RESET REGISTER */
++#define PCM990_CTRL_SYSRES	0x0001	/* System RESET REGISTER */
++#define PCM990_CTRL_RESOUT	0x0002	/* RESETOUT Enable REGISTER */
++#define PCM990_CTRL_RESGPIO	0x0004	/* RESETGPIO Enable REGISTER */
++
++#define PCM990_CTRL_REG1	0x0002	/* Power REGISTER */
++#define PCM990_CTRL_5VOFF	0x0001	/* Disable  5V Regulators */
++#define PCM990_CTRL_CANPWR	0x0004	/* Enable CANPWR ADUM */
++#define PCM990_CTRL_PM_5V	0x0008	/* Read 5V OK */
++
++#define PCM990_CTRL_REG2	0x0004	/* LED REGISTER */
++#define PCM990_CTRL_LEDPWR	0x0001	/* POWER LED enable */
++#define PCM990_CTRL_LEDBAS	0x0002	/* BASIS LED enable */
++#define PCM990_CTRL_LEDUSR	0x0004	/* USER LED enable */
++
++#define PCM990_CTRL_REG3	0x0006	/* LCD CTRL REGISTER 3 */
++#define PCM990_CTRL_LCDPWR	0x0001	/* RW LCD Power on */
++#define PCM990_CTRL_LCDON	0x0002	/* RW LCD Latch on */
++#define PCM990_CTRL_LCDPOS1	0x0004	/* RW POS 1 */
++#define PCM990_CTRL_LCDPOS2	0x0008	/* RW POS 2 */
++
++#define PCM990_CTRL_REG4	0x0008	/* MMC1 CTRL REGISTER 4 */
++#define PCM990_CTRL_MMC1PWR	0x0001 /* RW MMC1 Power on */
++
++#define PCM990_CTRL_REG5	0x000A	/* MMC2 CTRL REGISTER 5 */
++#define PCM990_CTRL_MMC2PWR	0x0001	/* RW MMC2 Power on */
++#define PCM990_CTRL_MMC2LED	0x0002	/* RW MMC2 LED */
++#define PCM990_CTRL_MMC2DE	0x0004	/* R MMC2 Card detect */
++#define PCM990_CTRL_MMC2WP	0x0008	/* R MMC2 Card write protect */
++
++#define PCM990_CTRL_REG6	0x000C	/* Interrupt Clear REGISTER */
++#define PCM990_CTRL_INTC0	0x0001	/* Clear Reg BT Detect */
++#define PCM990_CTRL_INTC1	0x0002	/* Clear Reg FR RI */
++#define PCM990_CTRL_INTC2	0x0004	/* Clear Reg MMC1 Detect */
++#define PCM990_CTRL_INTC3	0x0008	/* Clear Reg PM_5V off */
++
++#define PCM990_CTRL_REG7	0x000E	/* Interrupt Enable REGISTER */
++#define PCM990_CTRL_ENAINT0	0x0001	/* Enable Int BT Detect */
++#define PCM990_CTRL_ENAINT1	0x0002	/* Enable Int FR RI */
++#define PCM990_CTRL_ENAINT2	0x0004	/* Enable Int MMC1 Detect */
++#define PCM990_CTRL_ENAINT3	0x0008	/* Enable Int PM_5V off */
++
++#define PCM990_CTRL_REG8	0x0014	/* Uart REGISTER */
++#define PCM990_CTRL_FFSD	0x0001	/* BT Uart Enable */
++#define PCM990_CTRL_BTSD	0x0002	/* FF Uart Enable */
++#define PCM990_CTRL_FFRI	0x0004	/* FF Uart RI detect */
++#define PCM990_CTRL_BTRX	0x0008	/* BT Uart Rx detect */
++
++#define PCM990_CTRL_REG9	0x0010	/* AC97 Flash REGISTER */
++#define PCM990_CTRL_FLWP	0x0001	/* pC Flash Write Protect */
++#define PCM990_CTRL_FLDIS	0x0002	/* pC Flash Disable */
++#define PCM990_CTRL_AC97ENA	0x0004	/* Enable AC97 Expansion */
++
++#define PCM990_CTRL_REG10	0x0012	/* GPS-REGISTER */
++#define PCM990_CTRL_GPSPWR	0x0004	/* GPS-Modul Power on */
++#define PCM990_CTRL_GPSENA	0x0008	/* GPS-Modul Enable */
++
++#define PCM990_CTRL_REG11	0x0014	/* Accu REGISTER */
++#define PCM990_CTRL_ACENA	0x0001	/* Charge Enable */
++#define PCM990_CTRL_ACSEL	0x0002	/* Charge Akku -> DC Enable */
++#define PCM990_CTRL_ACPRES	0x0004	/* DC Present */
++#define PCM990_CTRL_ACALARM	0x0008	/* Error Akku */
++
++#define PCM990_CTRL_P2V(x)	((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
++#define PCM990_CTRL_V2P(x)	((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
++
++#ifndef __ASSEMBLY__
++#  define __PCM990_CTRL_REG(x) \
++		(*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
++#else
++#  define __PCM990_CTRL_REG(x)	PCM990_CTRL_P2V(x)
++#endif
++
++#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
++#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
++#define PCM990_CTRL0	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
++#define PCM990_CTRL1	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
++#define PCM990_CTRL2	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
++#define PCM990_CTRL3	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
++#define PCM990_CTRL4	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
++#define PCM990_CTRL5	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
++#define PCM990_CTRL6	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
++#define PCM990_CTRL7	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
++#define PCM990_CTRL8	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
++#define PCM990_CTRL9	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
++#define PCM990_CTRL10	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
++#define PCM990_CTRL11	__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
++
++
++/*
++ * IDE
++ */
++#define PCM990_IDE_IRQ_GPIO	13
++#define PCM990_IDE_IRQ		IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
++#define PCM990_IDE_IRQ_EDGE	IRQT_RISING
++#define PCM990_IDE_PLD_PHYS	0x20000000	/* 16 bit wide */
++#define PCM990_IDE_PLD_BASE	0xee000000
++#define PCM990_IDE_PLD_SIZE	(1*1024*1024)
++
++/* visible CPLD (U6) registers */
++#define PCM990_IDE_PLD_REG0	0x1000	/* OFFSET IDE REGISTER 0 */
++#define PCM990_IDE_PM5V		0x0004	/* R System VCC_5V */
++#define PCM990_IDE_STBY		0x0008	/* R System StandBy */
++
++#define PCM990_IDE_PLD_REG1	0x1002	/* OFFSET IDE REGISTER 1 */
++#define PCM990_IDE_IDEMODE	0x0001	/* R TrueIDE Mode */
++#define PCM990_IDE_DMAENA	0x0004	/* RW DMA Enable */
++#define PCM990_IDE_DMA1_0	0x0008	/* RW 1=DREQ1 0=DREQ0 */
++
++#define PCM990_IDE_PLD_REG2	0x1004	/* OFFSET IDE REGISTER 2 */
++#define PCM990_IDE_RESENA	0x0001	/* RW IDE Reset Bit enable */
++#define PCM990_IDE_RES		0x0002	/* RW IDE Reset Bit */
++#define PCM990_IDE_RDY		0x0008	/* RDY */
++
++#define PCM990_IDE_PLD_REG3	0x1006	/* OFFSET IDE REGISTER 3 */
++#define PCM990_IDE_IDEOE	0x0001	/* RW Latch on Databus */
++#define PCM990_IDE_IDEON	0x0002	/* RW Latch on Control Address */
++#define PCM990_IDE_IDEIN	0x0004	/* RW Latch on Interrupt usw. */
++
++#define PCM990_IDE_PLD_REG4	0x1008	/* OFFSET IDE REGISTER 4 */
++#define PCM990_IDE_PWRENA	0x0001	/* RW IDE Power enable */
++#define PCM990_IDE_5V		0x0002	/* R IDE Power 5V */
++#define PCM990_IDE_PWG		0x0008	/* R IDE Power is on */
++
++#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
++#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
++
++#ifndef __ASSEMBLY__
++# define  __PCM990_IDE_PLD_REG(x) \
++	(*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
++#else
++# define  __PCM990_IDE_PLD_REG(x)	PCM990_IDE_PLD_P2V(x)
++#endif
++
++#define PCM990_IDE0 \
++	__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
++#define PCM990_IDE1 \
++	__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
++#define PCM990_IDE2 \
++	__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
++#define PCM990_IDE3 \
++	__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
++#define PCM990_IDE4 \
++	__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
++
++/*
++ * Compact Flash
++ */
++#define PCM990_CF_IRQ_GPIO	11
++#define PCM990_CF_IRQ		IRQ_GPIO(PCM990_CF_IRQ_GPIO)
++#define PCM990_CF_IRQ_EDGE	IRQT_RISING
++
++#define PCM990_CF_CD_GPIO	12
++#define PCM990_CF_CD		IRQ_GPIO(PCM990_CF_CD_GPIO)
++#define PCM990_CF_CD_EDGE	IRQT_RISING
++
++#define PCM990_CF_PLD_PHYS	0x30000000	/* 16 bit wide */
++#define PCM990_CF_PLD_BASE	0xef000000
++#define PCM990_CF_PLD_SIZE	(1*1024*1024)
++#define PCM990_CF_PLD_P2V(x)	((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
++#define PCM990_CF_PLD_V2P(x)	((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
++
++/* visible CPLD (U6) registers */
++#define PCM990_CF_PLD_REG0	0x1000	/* OFFSET CF REGISTER 0 */
++#define PCM990_CF_REG0_LED	0x0001	/* RW LED on */
++#define PCM990_CF_REG0_BLK	0x0002	/* RW LED flash when access */
++#define PCM990_CF_REG0_PM5V	0x0004	/* R System VCC_5V enable */
++#define PCM990_CF_REG0_STBY	0x0008	/* R System StandBy */
++
++#define PCM990_CF_PLD_REG1	0x1002	/* OFFSET CF REGISTER 1 */
++#define PCM990_CF_REG1_IDEMODE	0x0001	/* RW CF card run as TrueIDE */
++#define PCM990_CF_REG1_CF0	0x0002	/* RW CF card at ADDR 0x28000000 */
++
++#define PCM990_CF_PLD_REG2	0x1004	/* OFFSET CF REGISTER 2 */
++#define PCM990_CF_REG2_RES	0x0002	/* RW CF RESET BIT */
++#define PCM990_CF_REG2_RDYENA	0x0004	/* RW Enable CF_RDY */
++#define PCM990_CF_REG2_RDY	0x0008	/* R CF_RDY auf PWAIT */
++
++#define PCM990_CF_PLD_REG3	0x1006	/* OFFSET CF REGISTER 3 */
++#define PCM990_CF_REG3_CFOE	0x0001	/* RW Latch on Databus */
++#define PCM990_CF_REG3_CFON	0x0002	/* RW Latch on Control Address */
++#define PCM990_CF_REG3_CFIN	0x0004	/* RW Latch on Interrupt usw. */
++#define PCM990_CF_REG3_CFCD	0x0008	/* RW Latch on CD1/2 VS1/2 usw */
++
++#define PCM990_CF_PLD_REG4	0x1008	/* OFFSET CF REGISTER 4 */
++#define PCM990_CF_REG4_PWRENA	0x0001	/* RW CF Power on (CD1/2 = "00") */
++#define PCM990_CF_REG4_5_3V	0x0002	/* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
++#define PCM990_CF_REG4_3B	0x0004	/* RW 3.0V Backup from VCC (5_3V=0) */
++#define PCM990_CF_REG4_PWG	0x0008	/* R CF-Power is on */
++
++#define PCM990_CF_PLD_REG5	0x100A	/* OFFSET CF REGISTER 5 */
++#define PCM990_CF_REG5_BVD1	0x0001	/* R CF /BVD1 */
++#define PCM990_CF_REG5_BVD2	0x0002	/* R CF /BVD2 */
++#define PCM990_CF_REG5_VS1	0x0004	/* R CF /VS1 */
++#define PCM990_CF_REG5_VS2	0x0008	/* R CF /VS2 */
++
++#define PCM990_CF_PLD_REG6	0x100C	/* OFFSET CF REGISTER 6 */
++#define PCM990_CF_REG6_CD1	0x0001	/* R CF Card_Detect1 */
++#define PCM990_CF_REG6_CD2	0x0002	/* R CF Card_Detect2 */
++
++#ifndef __ASSEMBLY__
++#  define  __PCM990_CF_PLD_REG(x) \
++	(*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
++#else
++#  define  __PCM990_CF_PLD_REG(x)	PCM990_CF_PLD_P2V(x)
++#endif
++
++#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
++#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
++#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
++#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
++#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
++#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
++#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
++
++/*
++ * Wolfson AC97 Touch
++ */
++#define PCM990_AC97_IRQ_GPIO	10
++#define PCM990_AC97_IRQ		IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
++#define PCM990_AC97_IRQ_EDGE	IRQT_RISING
++
++/*
++ * MMC phyCORE
++ */
++#define PCM990_MMC0_IRQ_GPIO	9
++#define PCM990_MMC0_IRQ		IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
++#define PCM990_MMC0_IRQ_EDGE	IRQT_FALLING
++
++/*
++ * USB phyCore
++ */
++#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
++#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pm.h linux-2.6.25-rc4/include/asm-arm/arch/pm.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pm.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pm.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (c) 2005 Richard Purdie
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/suspend.h>
++
++struct pxa_cpu_pm_fns {
++	int	save_size;
++	void	(*save)(unsigned long *);
++	void	(*restore)(unsigned long *);
++	int	(*valid)(suspend_state_t state);
++	void	(*enter)(suspend_state_t state);
++};
++
++extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
++
++/* sleep.S */
++extern void pxa25x_cpu_suspend(unsigned int);
++extern void pxa27x_cpu_suspend(unsigned int);
++extern void pxa_cpu_resume(void);
++
++extern int pxa_pm_enter(suspend_state_t state);
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/poodle.h linux-2.6.25-rc4/include/asm-arm/arch/poodle.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/poodle.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/poodle.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,75 @@
++/*
++ * linux/include/asm-arm/arch-pxa/poodle.h
++ *
++ * May be copied or modified under the terms of the GNU General Public
++ * License.  See linux/COPYING for more information.
++ *
++ * Based on:
++ *   linux/include/asm-arm/arch-sa1100/collie.h
++ *
++ * ChangeLog:
++ *   04-06-2001 Lineo Japan, Inc.
++ *   04-16-2001 SHARP Corporation
++ *   Update to 2.6 John Lenz
++ */
++#ifndef __ASM_ARCH_POODLE_H
++#define __ASM_ARCH_POODLE_H  1
++
++/*
++ * GPIOs
++ */
++/* PXA GPIOs */
++#define POODLE_GPIO_ON_KEY		(0)
++#define POODLE_GPIO_AC_IN		(1)
++#define POODLE_GPIO_CO			16
++#define POODLE_GPIO_TP_INT		(5)
++#define POODLE_GPIO_WAKEUP		(11)	/* change battery */
++#define POODLE_GPIO_GA_INT		(10)
++#define POODLE_GPIO_IR_ON		(22)
++#define POODLE_GPIO_HP_IN		(4)
++#define POODLE_GPIO_CF_IRQ		(17)
++#define POODLE_GPIO_CF_CD		(14)
++#define POODLE_GPIO_CF_STSCHG		(14)
++#define POODLE_GPIO_SD_PWR		(33)
++#define POODLE_GPIO_SD_PWR1		(3)
++#define POODLE_GPIO_nSD_CLK		(6)
++#define POODLE_GPIO_nSD_WP		(7)
++#define POODLE_GPIO_nSD_INT		(8)
++#define POODLE_GPIO_nSD_DETECT		(9)
++#define POODLE_GPIO_MAIN_BAT_LOW	(13)
++#define POODLE_GPIO_BAT_COVER		(13)
++#define POODLE_GPIO_USB_PULLUP		(20)
++#define POODLE_GPIO_ADC_TEMP_ON		(21)
++#define POODLE_GPIO_BYPASS_ON		(36)
++#define POODLE_GPIO_CHRG_ON		(38)
++#define POODLE_GPIO_CHRG_FULL		(16)
++#define POODLE_GPIO_DISCHARGE_ON        (42) /* Enable battery discharge */
++
++/* PXA GPIOs */
++#define POODLE_IRQ_GPIO_ON_KEY		IRQ_GPIO(0)
++#define POODLE_IRQ_GPIO_AC_IN		IRQ_GPIO(1)
++#define POODLE_IRQ_GPIO_HP_IN		IRQ_GPIO(4)
++#define POODLE_IRQ_GPIO_CO		IRQ_GPIO(16)
++#define POODLE_IRQ_GPIO_TP_INT		IRQ_GPIO(5)
++#define POODLE_IRQ_GPIO_WAKEUP		IRQ_GPIO(11)
++#define POODLE_IRQ_GPIO_GA_INT		IRQ_GPIO(10)
++#define POODLE_IRQ_GPIO_CF_IRQ		IRQ_GPIO(17)
++#define POODLE_IRQ_GPIO_CF_CD		IRQ_GPIO(14)
++#define POODLE_IRQ_GPIO_nSD_INT		IRQ_GPIO(8)
++#define POODLE_IRQ_GPIO_nSD_DETECT	IRQ_GPIO(9)
++#define POODLE_IRQ_GPIO_MAIN_BAT_LOW	IRQ_GPIO(13)
++
++/* SCOOP GPIOs */
++#define POODLE_SCOOP_CHARGE_ON	SCOOP_GPCR_PA11
++#define POODLE_SCOOP_CP401	SCOOP_GPCR_PA13
++#define POODLE_SCOOP_VPEN	SCOOP_GPCR_PA18
++#define POODLE_SCOOP_L_PCLK	SCOOP_GPCR_PA20
++#define POODLE_SCOOP_L_LCLK	SCOOP_GPCR_PA21
++#define POODLE_SCOOP_HS_OUT	SCOOP_GPCR_PA22
++
++#define POODLE_SCOOP_IO_DIR	( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
++#define POODLE_SCOOP_IO_OUT	( 0 )
++
++extern struct platform_device poodle_locomo_device;
++
++#endif /* __ASM_ARCH_POODLE_H  */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa27x_keypad.h linux-2.6.25-rc4/include/asm-arm/arch/pxa27x_keypad.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa27x_keypad.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa27x_keypad.h	2008-03-08 16:22:35.000000000 +0100
+@@ -0,0 +1,58 @@
++#ifndef __ASM_ARCH_PXA27x_KEYPAD_H
++#define __ASM_ARCH_PXA27x_KEYPAD_H
++
++#include <linux/input.h>
++
++#define MAX_MATRIX_KEY_ROWS	(8)
++#define MAX_MATRIX_KEY_COLS	(8)
++
++/* pxa3xx keypad platform specific parameters
++ *
++ * NOTE:
++ * 1. direct_key_num indicates the number of keys in the direct keypad
++ *    _plus_ the number of rotary-encoder sensor inputs,  this can be
++ *    left as 0 if only rotary encoders are enabled,  the driver will
++ *    automatically calculate this
++ *
++ * 2. direct_key_map is the key code map for the direct keys, if rotary
++ *    encoder(s) are enabled, direct key 0/1(2/3) will be ignored
++ *
++ * 3. rotary can be either interpreted as a relative input event (e.g.
++ *    REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT)
++ *
++ * 4. matrix key and direct key will use the same debounce_interval by
++ *    default, which should be sufficient in most cases
++ */
++struct pxa27x_keypad_platform_data {
++
++	/* code map for the matrix keys */
++	unsigned int	matrix_key_rows;
++	unsigned int	matrix_key_cols;
++	unsigned int	*matrix_key_map;
++	int		matrix_key_map_size;
++
++	/* direct keys */
++	int		direct_key_num;
++	unsigned int	direct_key_map[8];
++
++	/* rotary encoders 0 */
++	int		enable_rotary0;
++	int		rotary0_rel_code;
++	int		rotary0_up_key;
++	int		rotary0_down_key;
++
++	/* rotary encoders 1 */
++	int		enable_rotary1;
++	int		rotary1_rel_code;
++	int		rotary1_up_key;
++	int		rotary1_down_key;
++
++	/* key debounce interval */
++	unsigned int	debounce_interval;
++};
++
++#define KEY(row, col, val)	(((row) << 28) | ((col) << 24) | (val))
++
++extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
++
++#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa2xx-regs.h linux-2.6.25-rc4/include/asm-arm/arch/pxa2xx-regs.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa2xx-regs.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa2xx-regs.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,84 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
++ *
++ *  Taken from pxa-regs.h by Russell King
++ *
++ *  Author:	Nicolas Pitre
++ *  Copyright:	MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __PXA2XX_REGS_H
++#define __PXA2XX_REGS_H
++
++/*
++ * Memory controller
++ */
++
++#define MDCNFG		__REG(0x48000000)  /* SDRAM Configuration Register 0 */
++#define MDREFR		__REG(0x48000004)  /* SDRAM Refresh Control Register */
++#define MSC0		__REG(0x48000008)  /* Static Memory Control Register 0 */
++#define MSC1		__REG(0x4800000C)  /* Static Memory Control Register 1 */
++#define MSC2		__REG(0x48000010)  /* Static Memory Control Register 2 */
++#define MECR		__REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
++#define SXLCR		__REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
++#define SXCNFG		__REG(0x4800001C)  /* Synchronous Static Memory Control Register */
++#define SXMRS		__REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
++#define MCMEM0		__REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
++#define MCMEM1		__REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
++#define MCATT0		__REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
++#define MCATT1		__REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
++#define MCIO0		__REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
++#define MCIO1		__REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
++#define MDMRS		__REG(0x48000040)  /* MRS value to be written to SDRAM */
++#define BOOT_DEF	__REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
++
++/*
++ * More handy macros for PCMCIA
++ *
++ * Arg is socket number
++ */
++#define MCMEM(s)	__REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
++#define MCATT(s)	__REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
++#define MCIO(s)		__REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
++
++/* MECR register defines */
++#define MECR_NOS	(1 << 0)	/* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
++#define MECR_CIT	(1 << 1)	/* Card Is There: 0 -> no card, 1 -> card inserted */
++
++#define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
++#define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
++#define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
++#define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
++#define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
++#define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
++#define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
++#define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
++#define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
++#define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
++#define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
++#define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
++#define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
++#define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
++
++
++#ifdef CONFIG_PXA27x
++
++#define ARB_CNTRL	__REG(0x48000048)  /* Arbiter Control Register */
++
++#define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
++#define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
++#define ARB_EX_MEM_PARK 	(1<<29)	   /* Be parked with external MEMC when idle */
++#define ARB_INT_MEM_PARK	(1<<28)	   /* Be parked with internal MEMC when idle */
++#define ARB_USB_PARK		(1<<27)	   /* Be parked with USB when idle */
++#define ARB_LCD_PARK		(1<<26)	   /* Be parked with LCD when idle */
++#define ARB_DMA_PARK		(1<<25)	   /* Be parked with DMA when idle */
++#define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
++#define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
++
++#endif
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa2xx_spi.h linux-2.6.25-rc4/include/asm-arm/arch/pxa2xx_spi.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa2xx_spi.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa2xx_spi.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,44 @@
++/*
++ * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#ifndef PXA2XX_SPI_H_
++#define PXA2XX_SPI_H_
++
++#define PXA2XX_CS_ASSERT (0x01)
++#define PXA2XX_CS_DEASSERT (0x02)
++
++/* device.platform_data for SSP controller devices */
++struct pxa2xx_spi_master {
++	u32 clock_enable;
++	u16 num_chipselect;
++	u8 enable_dma;
++};
++
++/* spi_board_info.controller_data for SPI slave devices,
++ * copied to spi_device.platform_data ... mostly for dma tuning
++ */
++struct pxa2xx_spi_chip {
++	u8 tx_threshold;
++	u8 rx_threshold;
++	u8 dma_burst_size;
++	u32 timeout;
++	u8 enable_loopback;
++	void (*cs_control)(u32 command);
++};
++
++#endif /*PXA2XX_SPI_H_*/
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa3xx-regs.h linux-2.6.25-rc4/include/asm-arm/arch/pxa3xx-regs.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa3xx-regs.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa3xx-regs.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,174 @@
++/*
++ * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
++ *
++ * PXA3xx specific register definitions
++ *
++ * Copyright (C) 2007 Marvell International Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_PXA3XX_REGS_H
++#define __ASM_ARCH_PXA3XX_REGS_H
++/*
++ * Service Power Management Unit (MPMU)
++ */
++#define PMCR		__REG(0x40F50000)	/* Power Manager Control Register */
++#define PSR		__REG(0x40F50004)	/* Power Manager S2 Status Register */
++#define PSPR		__REG(0x40F50008)	/* Power Manager Scratch Pad Register */
++#define PCFR		__REG(0x40F5000C)	/* Power Manager General Configuration Register */
++#define PWER		__REG(0x40F50010)	/* Power Manager Wake-up Enable Register */
++#define PWSR		__REG(0x40F50014)	/* Power Manager Wake-up Status Register */
++#define PECR		__REG(0x40F50018)	/* Power Manager EXT_WAKEUP[1:0] Control Register */
++#define DCDCSR		__REG(0x40F50080)	/* DC-DC Controller Status Register */
++#define PVCR		__REG(0x40F50100)	/* Power Manager Voltage Change Control Register */
++#define PCMD(x)		__REG(0x40F50110 + ((x) << 2))
++
++/*
++ * Slave Power Managment Unit
++ */
++#define ASCR		__REG(0x40f40000)	/* Application Subsystem Power Status/Configuration */
++#define ARSR		__REG(0x40f40004)	/* Application Subsystem Reset Status */
++#define AD3ER		__REG(0x40f40008)	/* Application Subsystem Wake-Up from D3 Enable */
++#define AD3SR		__REG(0x40f4000c)	/* Application Subsystem Wake-Up from D3 Status */
++#define AD2D0ER		__REG(0x40f40010)	/* Application Subsystem Wake-Up from D2 to D0 Enable */
++#define AD2D0SR		__REG(0x40f40014)	/* Application Subsystem Wake-Up from D2 to D0 Status */
++#define AD2D1ER		__REG(0x40f40018)	/* Application Subsystem Wake-Up from D2 to D1 Enable */
++#define AD2D1SR		__REG(0x40f4001c)	/* Application Subsystem Wake-Up from D2 to D1 Status */
++#define AD1D0ER		__REG(0x40f40020)	/* Application Subsystem Wake-Up from D1 to D0 Enable */
++#define AD1D0SR		__REG(0x40f40024)	/* Application Subsystem Wake-Up from D1 to D0 Status */
++#define AGENP		__REG(0x40f4002c)	/* Application Subsystem General Purpose */
++#define AD3R		__REG(0x40f40030)	/* Application Subsystem D3 Configuration */
++#define AD2R		__REG(0x40f40034)	/* Application Subsystem D2 Configuration */
++#define AD1R		__REG(0x40f40038)	/* Application Subsystem D1 Configuration */
++
++/*
++ * Application Subsystem Configuration bits.
++ */
++#define ASCR_RDH		(1 << 31)
++#define ASCR_D1S		(1 << 2)
++#define ASCR_D2S		(1 << 1)
++#define ASCR_D3S		(1 << 0)
++
++/*
++ * Application Reset Status bits.
++ */
++#define ARSR_GPR		(1 << 3)
++#define ARSR_LPMR		(1 << 2)
++#define ARSR_WDT		(1 << 1)
++#define ARSR_HWR		(1 << 0)
++
++/*
++ * Application Subsystem Wake-Up bits.
++ */
++#define ADXER_WRTC		(1 << 31)	/* RTC */
++#define ADXER_WOST		(1 << 30)	/* OS Timer */
++#define ADXER_WTSI		(1 << 29)	/* Touchscreen */
++#define ADXER_WUSBH		(1 << 28)	/* USB host */
++#define ADXER_WUSB2		(1 << 26)	/* USB client 2.0 */
++#define ADXER_WMSL0		(1 << 24)	/* MSL port 0*/
++#define ADXER_WDMUX3		(1 << 23)	/* USB EDMUX3 */
++#define ADXER_WDMUX2		(1 << 22)	/* USB EDMUX2 */
++#define ADXER_WKP		(1 << 21)	/* Keypad */
++#define ADXER_WUSIM1		(1 << 20)	/* USIM Port 1 */
++#define ADXER_WUSIM0		(1 << 19)	/* USIM Port 0 */
++#define ADXER_WOTG		(1 << 16)	/* USBOTG input */
++#define ADXER_MFP_WFLASH	(1 << 15)	/* MFP: Data flash busy */
++#define ADXER_MFP_GEN12		(1 << 14)	/* MFP: MMC3/GPIO/OST inputs */
++#define ADXER_MFP_WMMC2		(1 << 13)	/* MFP: MMC2 */
++#define ADXER_MFP_WMMC1		(1 << 12)	/* MFP: MMC1 */
++#define ADXER_MFP_WI2C		(1 << 11)	/* MFP: I2C */
++#define ADXER_MFP_WSSP4		(1 << 10)	/* MFP: SSP4 */
++#define ADXER_MFP_WSSP3		(1 << 9)	/* MFP: SSP3 */
++#define ADXER_MFP_WMAXTRIX	(1 << 8)	/* MFP: matrix keypad */
++#define ADXER_MFP_WUART3	(1 << 7)	/* MFP: UART3 */
++#define ADXER_MFP_WUART2	(1 << 6)	/* MFP: UART2 */
++#define ADXER_MFP_WUART1	(1 << 5)	/* MFP: UART1 */
++#define ADXER_MFP_WSSP2		(1 << 4)	/* MFP: SSP2 */
++#define ADXER_MFP_WSSP1		(1 << 3)	/* MFP: SSP1 */
++#define ADXER_MFP_WAC97		(1 << 2)	/* MFP: AC97 */
++#define ADXER_WEXTWAKE1		(1 << 1)	/* External Wake 1 */
++#define ADXER_WEXTWAKE0		(1 << 0)	/* External Wake 0 */
++
++/*
++ * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
++ */
++#define ADXR_L2			(1 << 8)
++#define ADXR_R5			(1 << 5)
++#define ADXR_R4			(1 << 4)
++#define ADXR_R3			(1 << 3)
++#define ADXR_R2			(1 << 2)
++#define ADXR_R1			(1 << 1)
++#define ADXR_R0			(1 << 0)
++
++/*
++ * Values for PWRMODE CP15 register
++ */
++#define PXA3xx_PM_S3D4C4	0x07	/* aka deep sleep */
++#define PXA3xx_PM_S2D3C4	0x06	/* aka sleep */
++#define PXA3xx_PM_S0D2C2	0x03	/* aka standby */
++#define PXA3xx_PM_S0D1C2	0x02	/* aka LCD refresh */
++#define PXA3xx_PM_S0D0C1	0x01
++
++/*
++ * Application Subsystem Clock
++ */
++#define ACCR		__REG(0x41340000)	/* Application Subsystem Clock Configuration Register */
++#define ACSR		__REG(0x41340004)	/* Application Subsystem Clock Status Register */
++#define AICSR		__REG(0x41340008)	/* Application Subsystem Interrupt Control/Status Register */
++#define CKENA		__REG(0x4134000C)	/* A Clock Enable Register */
++#define CKENB		__REG(0x41340010)	/* B Clock Enable Register */
++#define AC97_DIV	__REG(0x41340014)	/* AC97 clock divisor value register */
++
++/*
++ * Clock Enable Bit
++ */
++#define CKEN_LCD	1	/* < LCD Clock Enable */
++#define CKEN_USBH	2	/* < USB host clock enable */
++#define CKEN_CAMERA	3	/* < Camera interface clock enable */
++#define CKEN_NAND	4	/* < NAND Flash Controller Clock Enable */
++#define CKEN_USB2	6	/* < USB 2.0 client clock enable. */
++#define CKEN_DMC	8	/* < Dynamic Memory Controller clock enable */
++#define CKEN_SMC	9	/* < Static Memory Controller clock enable */
++#define CKEN_ISC	10	/* < Internal SRAM Controller clock enable */
++#define CKEN_BOOT	11	/* < Boot rom clock enable */
++#define CKEN_MMC1	12	/* < MMC1 Clock enable */
++#define CKEN_MMC2	13	/* < MMC2 clock enable */
++#define CKEN_KEYPAD	14	/* < Keypand Controller Clock Enable */
++#define CKEN_CIR	15	/* < Consumer IR Clock Enable */
++#define CKEN_USIM0	17	/* < USIM[0] Clock Enable */
++#define CKEN_USIM1	18	/* < USIM[1] Clock Enable */
++#define CKEN_TPM	19	/* < TPM clock enable */
++#define CKEN_UDC	20	/* < UDC clock enable */
++#define CKEN_BTUART	21	/* < BTUART clock enable */
++#define CKEN_FFUART	22	/* < FFUART clock enable */
++#define CKEN_STUART	23	/* < STUART clock enable */
++#define CKEN_AC97	24	/* < AC97 clock enable */
++#define CKEN_TOUCH	25	/* < Touch screen Interface Clock Enable */
++#define CKEN_SSP1	26	/* < SSP1 clock enable */
++#define CKEN_SSP2	27	/* < SSP2 clock enable */
++#define CKEN_SSP3	28	/* < SSP3 clock enable */
++#define CKEN_SSP4	29	/* < SSP4 clock enable */
++#define CKEN_MSL0	30	/* < MSL0 clock enable */
++#define CKEN_PWM0	32	/* < PWM[0] clock enable */
++#define CKEN_PWM1	33	/* < PWM[1] clock enable */
++#define CKEN_I2C	36	/* < I2C clock enable */
++#define CKEN_INTC	38	/* < Interrupt controller clock enable */
++#define CKEN_GPIO	39	/* < GPIO clock enable */
++#define CKEN_1WIRE	40	/* < 1-wire clock enable */
++#define CKEN_HSIO2	41	/* < HSIO2 clock enable */
++#define CKEN_MINI_IM	48	/* < Mini-IM */
++#define CKEN_MINI_LCD	49	/* < Mini LCD */
++
++#if defined(CONFIG_CPU_PXA310)
++#define CKEN_MMC3	5	/* < MMC3 Clock Enable */
++#define CKEN_MVED	43	/* < MVED clock enable */
++#endif
++
++/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
++#define PXA300_CKEN_GRAPHICS	42	/* Graphics controller clock enable */
++#define PXA320_CKEN_GRAPHICS	7	/* Graphics controller clock enable */
++
++#endif /* __ASM_ARCH_PXA3XX_REGS_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxafb.h linux-2.6.25-rc4/include/asm-arm/arch/pxafb.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxafb.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pxafb.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,85 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/pxafb.h
++ *
++ *  Support for the xscale frame buffer.
++ *
++ *  Author:     Jean-Frederic Clere
++ *  Created:    Sep 22, 2003
++ *  Copyright:  jfclere@sinix.net
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation.
++ */
++
++#include <linux/fb.h>
++
++/*
++ * This structure describes the machine which we are running on.
++ * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
++ * of linux/drivers/video/pxafb.c
++ */
++struct pxafb_mode_info {
++	u_long		pixclock;
++
++	u_short		xres;
++	u_short		yres;
++
++	u_char		bpp;
++	u_char		hsync_len;
++	u_char		left_margin;
++	u_char		right_margin;
++
++	u_char		vsync_len;
++	u_char		upper_margin;
++	u_char		lower_margin;
++	u_char		sync;
++
++	u_int		cmap_greyscale:1,
++			unused:31;
++};
++
++struct pxafb_mach_info {
++	struct pxafb_mode_info *modes;
++	unsigned int num_modes;
++
++	u_int		fixed_modes:1,
++			cmap_inverse:1,
++			cmap_static:1,
++			unused:29;
++
++	/* The following should be defined in LCCR0
++	 *      LCCR0_Act or LCCR0_Pas          Active or Passive
++	 *      LCCR0_Sngl or LCCR0_Dual        Single/Dual panel
++	 *      LCCR0_Mono or LCCR0_Color       Mono/Color
++	 *      LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
++	 *      LCCR0_DMADel(Tcpu) (optional)   DMA request delay
++	 *
++	 * The following should not be defined in LCCR0:
++	 *      LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
++	 *      LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
++	 */
++	u_int		lccr0;
++	/* The following should be defined in LCCR3
++	 *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
++	 *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
++	 *      LCCR3_Acb(X)                    AB Bias pin frequency
++	 *      LCCR3_DPC (optional)            Double Pixel Clock mode (untested)
++	 *
++	 * The following should not be defined in LCCR3
++	 *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
++	 */
++	u_int		lccr3;
++	/* The following should be defined in LCCR4
++	 *	LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
++	 *
++	 * All other bits in LCCR4 should be left alone.
++	 */
++	u_int		lccr4;
++	void (*pxafb_backlight_power)(int);
++	void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
++
++};
++void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
++void set_pxa_fb_parent(struct device *parent_dev);
++unsigned long pxafb_get_hsync_time(struct device *dev);
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa-regs.h linux-2.6.25-rc4/include/asm-arm/arch/pxa-regs.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa-regs.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa-regs.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,2150 @@
++/*
++ *  linux/include/asm-arm/arch-pxa/pxa-regs.h
++ *
++ *  Author:	Nicolas Pitre
++ *  Created:	Jun 15, 2001
++ *  Copyright:	MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __PXA_REGS_H
++#define __PXA_REGS_H
++
++
++/*
++ * PXA Chip selects
++ */
++
++#define PXA_CS0_PHYS	0x00000000
++#define PXA_CS1_PHYS	0x04000000
++#define PXA_CS2_PHYS	0x08000000
++#define PXA_CS3_PHYS	0x0C000000
++#define PXA_CS4_PHYS	0x10000000
++#define PXA_CS5_PHYS	0x14000000
++
++
++/*
++ * Personal Computer Memory Card International Association (PCMCIA) sockets
++ */
++
++#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
++#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
++#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
++#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
++#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */
++
++#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
++#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
++#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
++#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */
++
++#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
++#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
++#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
++#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */
++
++#define _PCMCIA(Nb)	        	/* PCMCIA [0..1]                   */ \
++                	(0x20000000 + (Nb)*PCMCIASp)
++#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]               */
++#define _PCMCIAAttr(Nb)	        	/* PCMCIA Attribute [0..1]         */ \
++                	(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
++#define _PCMCIAMem(Nb)	        	/* PCMCIA Memory [0..1]            */ \
++                	(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
++
++#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0                        */
++#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O                    */
++#define _PCMCIA0Attr	_PCMCIAAttr (0)	/* PCMCIA 0 Attribute              */
++#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory                 */
++
++#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1                        */
++#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O                    */
++#define _PCMCIA1Attr	_PCMCIAAttr (1)	/* PCMCIA 1 Attribute              */
++#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory                 */
++
++
++
++/*
++ * DMA Controller
++ */
++
++#define DCSR0		__REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
++#define DCSR1		__REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
++#define DCSR2		__REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
++#define DCSR3		__REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
++#define DCSR4		__REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
++#define DCSR5		__REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
++#define DCSR6		__REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
++#define DCSR7		__REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
++#define DCSR8		__REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
++#define DCSR9		__REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
++#define DCSR10		__REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
++#define DCSR11		__REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
++#define DCSR12		__REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
++#define DCSR13		__REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
++#define DCSR14		__REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
++#define DCSR15		__REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
++
++#define DCSR(x)		__REG2(0x40000000, (x) << 2)
++
++#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
++#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
++#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
++#ifdef CONFIG_PXA27x
++#define DCSR_EORIRQEN	(1 << 28)       /* End of Receive Interrupt Enable (R/W) */
++#define DCSR_EORJMPEN	(1 << 27)       /* Jump to next descriptor on EOR */
++#define DCSR_EORSTOPEN	(1 << 26)       /* STOP on an EOR */
++#define DCSR_SETCMPST	(1 << 25)       /* Set Descriptor Compare Status */
++#define DCSR_CLRCMPST	(1 << 24)       /* Clear Descriptor Compare Status */
++#define DCSR_CMPST	(1 << 10)       /* The Descriptor Compare Status */
++#define DCSR_EORINTR	(1 << 9)        /* The end of Receive */
++#endif
++#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
++#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
++#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
++#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
++#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
++
++#define DALGN		__REG(0x400000a0)  /* DMA Alignment Register */
++#define DINT		__REG(0x400000f0)  /* DMA Interrupt Register */
++
++#define DRCMR(n)	(*(((n) < 64) ? \
++			&__REG2(0x40000100, ((n) & 0x3f) << 2) : \
++			&__REG2(0x40001100, ((n) & 0x3f) << 2)))
++
++#define DRCMR0		__REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
++#define DRCMR1		__REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
++#define DRCMR2		__REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
++#define DRCMR3		__REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */
++#define DRCMR4		__REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */
++#define DRCMR5		__REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */
++#define DRCMR6		__REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */
++#define DRCMR7		__REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */
++#define DRCMR8		__REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */
++#define DRCMR9		__REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */
++#define DRCMR10		__REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */
++#define DRCMR11		__REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */
++#define DRCMR12		__REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
++#define DRCMR13		__REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
++#define DRCMR14		__REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
++#define DRCMR15		__REG(0x4000013c)  /* Request to Channel Map Register for SSP2 receive Request */
++#define DRCMR16		__REG(0x40000140)  /* Request to Channel Map Register for SSP2 transmit Request */
++#define DRCMR17		__REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
++#define DRCMR18		__REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
++#define DRCMR19		__REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
++#define DRCMR20		__REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */
++#define DRCMR21		__REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */
++#define DRCMR22		__REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */
++#define DRCMR23		__REG(0x4000015c)  /* Reserved */
++#define DRCMR24		__REG(0x40000160)  /* Reserved */
++#define DRCMR25		__REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */
++#define DRCMR26		__REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */
++#define DRCMR27		__REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */
++#define DRCMR28		__REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */
++#define DRCMR29		__REG(0x40000174)  /* Reserved */
++#define DRCMR30		__REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */
++#define DRCMR31		__REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */
++#define DRCMR32		__REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */
++#define DRCMR33		__REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */
++#define DRCMR34		__REG(0x40000188)  /* Reserved */
++#define DRCMR35		__REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */
++#define DRCMR36		__REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */
++#define DRCMR37		__REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
++#define DRCMR38		__REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
++#define DRCMR39		__REG(0x4000019C)  /* Reserved */
++#define DRCMR66		__REG(0x40001108)  /* Request to Channel Map Register for SSP3 receive Request */
++#define DRCMR67		__REG(0x4000110C)  /* Request to Channel Map Register for SSP3 transmit Request */
++#define DRCMR68		__REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
++#define DRCMR69		__REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
++#define DRCMR70		__REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
++
++#define DRCMRRXSADR	DRCMR2
++#define DRCMRTXSADR	DRCMR3
++#define DRCMRRXBTRBR	DRCMR4
++#define DRCMRTXBTTHR	DRCMR5
++#define DRCMRRXFFRBR	DRCMR6
++#define DRCMRTXFFTHR	DRCMR7
++#define DRCMRRXMCDR	DRCMR8
++#define DRCMRRXMODR	DRCMR9
++#define DRCMRTXMODR	DRCMR10
++#define DRCMRRXPCDR	DRCMR11
++#define DRCMRTXPCDR	DRCMR12
++#define DRCMRRXSSDR	DRCMR13
++#define DRCMRTXSSDR	DRCMR14
++#define DRCMRRXSS2DR   DRCMR15
++#define DRCMRTXSS2DR   DRCMR16
++#define DRCMRRXICDR	DRCMR17
++#define DRCMRTXICDR	DRCMR18
++#define DRCMRRXSTRBR	DRCMR19
++#define DRCMRTXSTTHR	DRCMR20
++#define DRCMRRXMMC	DRCMR21
++#define DRCMRTXMMC	DRCMR22
++#define DRCMRRXSS3DR   DRCMR66
++#define DRCMRTXSS3DR   DRCMR67
++#define DRCMRUDC(x)	DRCMR((x) + 24)
++
++#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
++#define DRCMR_CHLNUM	0x1f		/* mask for Channel Number (read / write) */
++
++#define DDADR0		__REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */
++#define DSADR0		__REG(0x40000204)  /* DMA Source Address Register Channel 0 */
++#define DTADR0		__REG(0x40000208)  /* DMA Target Address Register Channel 0 */
++#define DCMD0		__REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
++#define DDADR1		__REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */
++#define DSADR1		__REG(0x40000214)  /* DMA Source Address Register Channel 1 */
++#define DTADR1		__REG(0x40000218)  /* DMA Target Address Register Channel 1 */
++#define DCMD1		__REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
++#define DDADR2		__REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */
++#define DSADR2		__REG(0x40000224)  /* DMA Source Address Register Channel 2 */
++#define DTADR2		__REG(0x40000228)  /* DMA Target Address Register Channel 2 */
++#define DCMD2		__REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
++#define DDADR3		__REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */
++#define DSADR3		__REG(0x40000234)  /* DMA Source Address Register Channel 3 */
++#define DTADR3		__REG(0x40000238)  /* DMA Target Address Register Channel 3 */
++#define DCMD3		__REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
++#define DDADR4		__REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */
++#define DSADR4		__REG(0x40000244)  /* DMA Source Address Register Channel 4 */
++#define DTADR4		__REG(0x40000248)  /* DMA Target Address Register Channel 4 */
++#define DCMD4		__REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
++#define DDADR5		__REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */
++#define DSADR5		__REG(0x40000254)  /* DMA Source Address Register Channel 5 */
++#define DTADR5		__REG(0x40000258)  /* DMA Target Address Register Channel 5 */
++#define DCMD5		__REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
++#define DDADR6		__REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */
++#define DSADR6		__REG(0x40000264)  /* DMA Source Address Register Channel 6 */
++#define DTADR6		__REG(0x40000268)  /* DMA Target Address Register Channel 6 */
++#define DCMD6		__REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
++#define DDADR7		__REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */
++#define DSADR7		__REG(0x40000274)  /* DMA Source Address Register Channel 7 */
++#define DTADR7		__REG(0x40000278)  /* DMA Target Address Register Channel 7 */
++#define DCMD7		__REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
++#define DDADR8		__REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */
++#define DSADR8		__REG(0x40000284)  /* DMA Source Address Register Channel 8 */
++#define DTADR8		__REG(0x40000288)  /* DMA Target Address Register Channel 8 */
++#define DCMD8		__REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
++#define DDADR9		__REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */
++#define DSADR9		__REG(0x40000294)  /* DMA Source Address Register Channel 9 */
++#define DTADR9		__REG(0x40000298)  /* DMA Target Address Register Channel 9 */
++#define DCMD9		__REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
++#define DDADR10		__REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */
++#define DSADR10		__REG(0x400002a4)  /* DMA Source Address Register Channel 10 */
++#define DTADR10		__REG(0x400002a8)  /* DMA Target Address Register Channel 10 */
++#define DCMD10		__REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
++#define DDADR11		__REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */
++#define DSADR11		__REG(0x400002b4)  /* DMA Source Address Register Channel 11 */
++#define DTADR11		__REG(0x400002b8)  /* DMA Target Address Register Channel 11 */
++#define DCMD11		__REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
++#define DDADR12		__REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */
++#define DSADR12		__REG(0x400002c4)  /* DMA Source Address Register Channel 12 */
++#define DTADR12		__REG(0x400002c8)  /* DMA Target Address Register Channel 12 */
++#define DCMD12		__REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
++#define DDADR13		__REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */
++#define DSADR13		__REG(0x400002d4)  /* DMA Source Address Register Channel 13 */
++#define DTADR13		__REG(0x400002d8)  /* DMA Target Address Register Channel 13 */
++#define DCMD13		__REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
++#define DDADR14		__REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */
++#define DSADR14		__REG(0x400002e4)  /* DMA Source Address Register Channel 14 */
++#define DTADR14		__REG(0x400002e8)  /* DMA Target Address Register Channel 14 */
++#define DCMD14		__REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
++#define DDADR15		__REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */
++#define DSADR15		__REG(0x400002f4)  /* DMA Source Address Register Channel 15 */
++#define DTADR15		__REG(0x400002f8)  /* DMA Target Address Register Channel 15 */
++#define DCMD15		__REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
++
++#define DDADR(x)	__REG2(0x40000200, (x) << 4)
++#define DSADR(x)	__REG2(0x40000204, (x) << 4)
++#define DTADR(x)	__REG2(0x40000208, (x) << 4)
++#define DCMD(x)		__REG2(0x4000020c, (x) << 4)
++
++#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
++#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
++
++#define DCMD_INCSRCADDR	(1 << 31)	/* Source Address Increment Setting. */
++#define DCMD_INCTRGADDR	(1 << 30)	/* Target Address Increment Setting. */
++#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
++#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
++#define DCMD_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
++#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
++#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
++#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
++#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
++#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
++#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
++#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
++#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
++#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
++
++
++/*
++ * UARTs
++ */
++
++/* Full Function UART (FFUART) */
++#define FFUART		FFRBR
++#define FFRBR		__REG(0x40100000)  /* Receive Buffer Register (read only) */
++#define FFTHR		__REG(0x40100000)  /* Transmit Holding Register (write only) */
++#define FFIER		__REG(0x40100004)  /* Interrupt Enable Register (read/write) */
++#define FFIIR		__REG(0x40100008)  /* Interrupt ID Register (read only) */
++#define FFFCR		__REG(0x40100008)  /* FIFO Control Register (write only) */
++#define FFLCR		__REG(0x4010000C)  /* Line Control Register (read/write) */
++#define FFMCR		__REG(0x40100010)  /* Modem Control Register (read/write) */
++#define FFLSR		__REG(0x40100014)  /* Line Status Register (read only) */
++#define FFMSR		__REG(0x40100018)  /* Modem Status Register (read only) */
++#define FFSPR		__REG(0x4010001C)  /* Scratch Pad Register (read/write) */
++#define FFISR		__REG(0x40100020)  /* Infrared Selection Register (read/write) */
++#define FFDLL		__REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
++#define FFDLH		__REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
++
++/* Bluetooth UART (BTUART) */
++#define BTUART		BTRBR
++#define BTRBR		__REG(0x40200000)  /* Receive Buffer Register (read only) */
++#define BTTHR		__REG(0x40200000)  /* Transmit Holding Register (write only) */
++#define BTIER		__REG(0x40200004)  /* Interrupt Enable Register (read/write) */
++#define BTIIR		__REG(0x40200008)  /* Interrupt ID Register (read only) */
++#define BTFCR		__REG(0x40200008)  /* FIFO Control Register (write only) */
++#define BTLCR		__REG(0x4020000C)  /* Line Control Register (read/write) */
++#define BTMCR		__REG(0x40200010)  /* Modem Control Register (read/write) */
++#define BTLSR		__REG(0x40200014)  /* Line Status Register (read only) */
++#define BTMSR		__REG(0x40200018)  /* Modem Status Register (read only) */
++#define BTSPR		__REG(0x4020001C)  /* Scratch Pad Register (read/write) */
++#define BTISR		__REG(0x40200020)  /* Infrared Selection Register (read/write) */
++#define BTDLL		__REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
++#define BTDLH		__REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
++
++/* Standard UART (STUART) */
++#define STUART		STRBR
++#define STRBR		__REG(0x40700000)  /* Receive Buffer Register (read only) */
++#define STTHR		__REG(0x40700000)  /* Transmit Holding Register (write only) */
++#define STIER		__REG(0x40700004)  /* Interrupt Enable Register (read/write) */
++#define STIIR		__REG(0x40700008)  /* Interrupt ID Register (read only) */
++#define STFCR		__REG(0x40700008)  /* FIFO Control Register (write only) */
++#define STLCR		__REG(0x4070000C)  /* Line Control Register (read/write) */
++#define STMCR		__REG(0x40700010)  /* Modem Control Register (read/write) */
++#define STLSR		__REG(0x40700014)  /* Line Status Register (read only) */
++#define STMSR		__REG(0x40700018)  /* Reserved */
++#define STSPR		__REG(0x4070001C)  /* Scratch Pad Register (read/write) */
++#define STISR		__REG(0x40700020)  /* Infrared Selection Register (read/write) */
++#define STDLL		__REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
++#define STDLH		__REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
++
++/* Hardware UART (HWUART) */
++#define HWUART		HWRBR
++#define HWRBR		__REG(0x41600000)  /* Receive Buffer Register (read only) */
++#define HWTHR		__REG(0x41600000)  /* Transmit Holding Register (write only) */
++#define HWIER		__REG(0x41600004)  /* Interrupt Enable Register (read/write) */
++#define HWIIR		__REG(0x41600008)  /* Interrupt ID Register (read only) */
++#define HWFCR		__REG(0x41600008)  /* FIFO Control Register (write only) */
++#define HWLCR		__REG(0x4160000C)  /* Line Control Register (read/write) */
++#define HWMCR		__REG(0x41600010)  /* Modem Control Register (read/write) */
++#define HWLSR		__REG(0x41600014)  /* Line Status Register (read only) */
++#define HWMSR		__REG(0x41600018)  /* Modem Status Register (read only) */
++#define HWSPR		__REG(0x4160001C)  /* Scratch Pad Register (read/write) */
++#define HWISR		__REG(0x41600020)  /* Infrared Selection Register (read/write) */
++#define HWFOR		__REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
++#define HWABR		__REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
++#define HWACR		__REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
++#define HWDLL		__REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
++#define HWDLH		__REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
++
++#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
++#define IER_UUE		(1 << 6)	/* UART Unit Enable */
++#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
++#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
++#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
++#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
++#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
++#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
++
++#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
++#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
++#define IIR_TOD		(1 << 3)	/* Time Out Detected */
++#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
++#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
++#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
++
++#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
++#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
++#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
++#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
++#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
++#define FCR_ITL_1	(0)
++#define FCR_ITL_8	(FCR_ITL1)
++#define FCR_ITL_16	(FCR_ITL2)
++#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
++
++#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
++#define LCR_SB		(1 << 6)	/* Set Break */
++#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
++#define LCR_EPS		(1 << 4)	/* Even Parity Select */
++#define LCR_PEN		(1 << 3)	/* Parity Enable */
++#define LCR_STB		(1 << 2)	/* Stop Bit */
++#define LCR_WLS1	(1 << 1)	/* Word Length Select */
++#define LCR_WLS0	(1 << 0)	/* Word Length Select */
++
++#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
++#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
++#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
++#define LSR_BI		(1 << 4)	/* Break Interrupt */
++#define LSR_FE		(1 << 3)	/* Framing Error */
++#define LSR_PE		(1 << 2)	/* Parity Error */
++#define LSR_OE		(1 << 1)	/* Overrun Error */
++#define LSR_DR		(1 << 0)	/* Data Ready */
++
++#define MCR_LOOP	(1 << 4)
++#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
++#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
++#define MCR_RTS		(1 << 1)	/* Request to Send */
++#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
++
++#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
++#define MSR_RI		(1 << 6)	/* Ring Indicator */
++#define MSR_DSR		(1 << 5)	/* Data Set Ready */
++#define MSR_CTS		(1 << 4)	/* Clear To Send */
++#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
++#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
++#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
++#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
++
++/*
++ * IrSR (Infrared Selection Register)
++ */
++#define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
++#define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
++#define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
++#define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
++#define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
++
++
++/*
++ * I2C registers
++ */
++
++#define IBMR		__REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
++#define IDBR		__REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
++#define ICR		__REG(0x40301690)  /* I2C Control Register - ICR */
++#define ISR		__REG(0x40301698)  /* I2C Status Register - ISR */
++#define ISAR		__REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
++
++#define PWRIBMR    __REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
++#define PWRIDBR    __REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
++#define PWRICR __REG(0x40f00190)  /* Power I2C Control Register - ICR */
++#define PWRISR __REG(0x40f00198)  /* Power I2C Status Register - ISR */
++#define PWRISAR    __REG(0x40f001A0)  /*Power I2C Slave Address Register-ISAR */
++
++#define ICR_START	(1 << 0)	   /* start bit */
++#define ICR_STOP	(1 << 1)	   /* stop bit */
++#define ICR_ACKNAK	(1 << 2)	   /* send ACK(0) or NAK(1) */
++#define ICR_TB		(1 << 3)	   /* transfer byte bit */
++#define ICR_MA		(1 << 4)	   /* master abort */
++#define ICR_SCLE	(1 << 5)	   /* master clock enable */
++#define ICR_IUE		(1 << 6)	   /* unit enable */
++#define ICR_GCD		(1 << 7)	   /* general call disable */
++#define ICR_ITEIE	(1 << 8)	   /* enable tx interrupts */
++#define ICR_IRFIE	(1 << 9)	   /* enable rx interrupts */
++#define ICR_BEIE	(1 << 10)	   /* enable bus error ints */
++#define ICR_SSDIE	(1 << 11)	   /* slave STOP detected int enable */
++#define ICR_ALDIE	(1 << 12)	   /* enable arbitration interrupt */
++#define ICR_SADIE	(1 << 13)	   /* slave address detected int enable */
++#define ICR_UR		(1 << 14)	   /* unit reset */
++
++#define ISR_RWM		(1 << 0)	   /* read/write mode */
++#define ISR_ACKNAK	(1 << 1)	   /* ack/nak status */
++#define ISR_UB		(1 << 2)	   /* unit busy */
++#define ISR_IBB		(1 << 3)	   /* bus busy */
++#define ISR_SSD		(1 << 4)	   /* slave stop detected */
++#define ISR_ALD		(1 << 5)	   /* arbitration loss detected */
++#define ISR_ITE		(1 << 6)	   /* tx buffer empty */
++#define ISR_IRF		(1 << 7)	   /* rx buffer full */
++#define ISR_GCAD	(1 << 8)	   /* general call address detected */
++#define ISR_SAD		(1 << 9)	   /* slave address detected */
++#define ISR_BED		(1 << 10)	   /* bus error no ACK/NAK */
++
++
++/*
++ * Serial Audio Controller
++ */
++
++#define SACR0		__REG(0x40400000)  /* Global Control Register */
++#define SACR1		__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
++#define SASR0		__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
++#define SAIMR		__REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
++#define SAICR		__REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
++#define SADIV		__REG(0x40400060)  /* Audio Clock Divider Register. */
++#define SADR		__REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
++
++#define SACR0_RFTH(x)	((x) << 12)	/* Rx FIFO Interrupt or DMA Trigger Threshold */
++#define SACR0_TFTH(x)	((x) << 8)	/* Tx FIFO Interrupt or DMA Trigger Threshold */
++#define SACR0_STRF	(1 << 5)	/* FIFO Select for EFWR Special Function */
++#define SACR0_EFWR	(1 << 4)	/* Enable EFWR Function  */
++#define SACR0_RST	(1 << 3)	/* FIFO, i2s Register Reset */
++#define SACR0_BCKD	(1 << 2) 	/* Bit Clock Direction */
++#define SACR0_ENB	(1 << 0)	/* Enable I2S Link */
++#define SACR1_ENLBF	(1 << 5)	/* Enable Loopback */
++#define SACR1_DRPL	(1 << 4) 	/* Disable Replaying Function */
++#define SACR1_DREC	(1 << 3)	/* Disable Recording Function */
++#define SACR1_AMSL	(1 << 0)	/* Specify Alternate Mode */
++
++#define SASR0_I2SOFF	(1 << 7)	/* Controller Status */
++#define SASR0_ROR	(1 << 6)	/* Rx FIFO Overrun */
++#define SASR0_TUR	(1 << 5)	/* Tx FIFO Underrun */
++#define SASR0_RFS	(1 << 4)	/* Rx FIFO Service Request */
++#define SASR0_TFS	(1 << 3)	/* Tx FIFO Service Request */
++#define SASR0_BSY	(1 << 2)	/* I2S Busy */
++#define SASR0_RNE	(1 << 1)	/* Rx FIFO Not Empty */
++#define SASR0_TNF	(1 << 0) 	/* Tx FIFO Not Empty */
++
++#define SAICR_ROR	(1 << 6)	/* Clear Rx FIFO Overrun Interrupt */
++#define SAICR_TUR	(1 << 5)	/* Clear Tx FIFO Underrun Interrupt */
++
++#define SAIMR_ROR	(1 << 6)	/* Enable Rx FIFO Overrun Condition Interrupt */
++#define SAIMR_TUR	(1 << 5)	/* Enable Tx FIFO Underrun Condition Interrupt */
++#define SAIMR_RFS	(1 << 4)	/* Enable Rx FIFO Service Interrupt */
++#define SAIMR_TFS	(1 << 3)	/* Enable Tx FIFO Service Interrupt */
++
++/*
++ * AC97 Controller registers
++ */
++
++#define POCR		__REG(0x40500000)  /* PCM Out Control Register */
++#define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
++#define POCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
++
++#define PICR		__REG(0x40500004)  /* PCM In Control Register */
++#define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
++#define PICR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
++
++#define MCCR		__REG(0x40500008)  /* Mic In Control Register */
++#define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
++#define MCCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
++
++#define GCR		__REG(0x4050000C)  /* Global Control Register */
++#ifdef CONFIG_PXA3xx
++#define GCR_CLKBPB	(1 << 31)	/* Internal clock enable */
++#endif
++#define GCR_nDMAEN	(1 << 24)	/* non DMA Enable */
++#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
++#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
++#define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
++#define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
++#define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
++#define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
++#define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
++#define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */
++#define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
++#define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
++
++#define POSR		__REG(0x40500010)  /* PCM Out Status Register */
++#define POSR_FIFOE	(1 << 4)	/* FIFO error */
++#define POSR_FSR	(1 << 2)	/* FIFO Service Request */
++
++#define PISR		__REG(0x40500014)  /* PCM In Status Register */
++#define PISR_FIFOE	(1 << 4)	/* FIFO error */
++#define PISR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
++#define PISR_FSR	(1 << 2)	/* FIFO Service Request */
++
++#define MCSR		__REG(0x40500018)  /* Mic In Status Register */
++#define MCSR_FIFOE	(1 << 4)	/* FIFO error */
++#define MCSR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
++#define MCSR_FSR	(1 << 2)	/* FIFO Service Request */
++
++#define GSR		__REG(0x4050001C)  /* Global Status Register */
++#define GSR_CDONE	(1 << 19)	/* Command Done */
++#define GSR_SDONE	(1 << 18)	/* Status Done */
++#define GSR_RDCS	(1 << 15)	/* Read Completion Status */
++#define GSR_BIT3SLT12	(1 << 14)	/* Bit 3 of slot 12 */
++#define GSR_BIT2SLT12	(1 << 13)	/* Bit 2 of slot 12 */
++#define GSR_BIT1SLT12	(1 << 12)	/* Bit 1 of slot 12 */
++#define GSR_SECRES	(1 << 11)	/* Secondary Resume Interrupt */
++#define GSR_PRIRES	(1 << 10)	/* Primary Resume Interrupt */
++#define GSR_SCR		(1 << 9)	/* Secondary Codec Ready */
++#define GSR_PCR		(1 << 8)	/*  Primary Codec Ready */
++#define GSR_MCINT	(1 << 7)	/* Mic In Interrupt */
++#define GSR_POINT	(1 << 6)	/* PCM Out Interrupt */
++#define GSR_PIINT	(1 << 5)	/* PCM In Interrupt */
++#define GSR_ACOFFD	(1 << 3)	/* AC-link Shut Off Done */
++#define GSR_MOINT	(1 << 2)	/* Modem Out Interrupt */
++#define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
++#define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
++
++#define CAR		__REG(0x40500020)  /* CODEC Access Register */
++#define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */
++
++#define PCDR		__REG(0x40500040)  /* PCM FIFO Data Register */
++#define MCDR		__REG(0x40500060)  /* Mic-in FIFO Data Register */
++
++#define MOCR		__REG(0x40500100)  /* Modem Out Control Register */
++#define MOCR_FEIE	(1 << 3)	/* FIFO Error */
++#define MOCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
++
++#define MICR		__REG(0x40500108)  /* Modem In Control Register */
++#define MICR_FEIE	(1 << 3)	/* FIFO Error */
++#define MICR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
++
++#define MOSR		__REG(0x40500110)  /* Modem Out Status Register */
++#define MOSR_FIFOE	(1 << 4)	/* FIFO error */
++#define MOSR_FSR	(1 << 2)	/* FIFO Service Request */
++
++#define MISR		__REG(0x40500118)  /* Modem In Status Register */
++#define MISR_FIFOE	(1 << 4)	/* FIFO error */
++#define MISR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
++#define MISR_FSR	(1 << 2)	/* FIFO Service Request */
++
++#define MODR		__REG(0x40500140)  /* Modem FIFO Data Register */
++
++#define PAC_REG_BASE	__REG(0x40500200)  /* Primary Audio Codec */
++#define SAC_REG_BASE	__REG(0x40500300)  /* Secondary Audio Codec */
++#define PMC_REG_BASE	__REG(0x40500400)  /* Primary Modem Codec */
++#define SMC_REG_BASE	__REG(0x40500500)  /* Secondary Modem Codec */
++
++
++/*
++ * USB Device Controller
++ * PXA25x and PXA27x USB device controller registers are different.
++ */
++#if defined(CONFIG_PXA25x)
++
++#define UDC_RES1	__REG(0x40600004)  /* UDC Undocumented - Reserved1 */
++#define UDC_RES2	__REG(0x40600008)  /* UDC Undocumented - Reserved2 */
++#define UDC_RES3	__REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
++
++#define UDCCR		__REG(0x40600000)  /* UDC Control Register */
++#define UDCCR_UDE	(1 << 0)	/* UDC enable */
++#define UDCCR_UDA	(1 << 1)	/* UDC active */
++#define UDCCR_RSM	(1 << 2)	/* Device resume */
++#define UDCCR_RESIR	(1 << 3)	/* Resume interrupt request */
++#define UDCCR_SUSIR	(1 << 4)	/* Suspend interrupt request */
++#define UDCCR_SRM	(1 << 5)	/* Suspend/resume interrupt mask */
++#define UDCCR_RSTIR	(1 << 6)	/* Reset interrupt request */
++#define UDCCR_REM	(1 << 7)	/* Reset interrupt mask */
++
++#define UDCCS0		__REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
++#define UDCCS0_OPR	(1 << 0)	/* OUT packet ready */
++#define UDCCS0_IPR	(1 << 1)	/* IN packet ready */
++#define UDCCS0_FTF	(1 << 2)	/* Flush Tx FIFO */
++#define UDCCS0_DRWF	(1 << 3)	/* Device remote wakeup feature */
++#define UDCCS0_SST	(1 << 4)	/* Sent stall */
++#define UDCCS0_FST	(1 << 5)	/* Force stall */
++#define UDCCS0_RNE	(1 << 6)	/* Receive FIFO no empty */
++#define UDCCS0_SA	(1 << 7)	/* Setup active */
++
++/* Bulk IN - Endpoint 1,6,11 */
++#define UDCCS1		__REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
++#define UDCCS6		__REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
++#define UDCCS11		__REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
++
++#define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
++#define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
++#define UDCCS_BI_FTF	(1 << 2)	/* Flush Tx FIFO */
++#define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
++#define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
++#define UDCCS_BI_FST	(1 << 5)	/* Force stall */
++#define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
++
++/* Bulk OUT - Endpoint 2,7,12 */
++#define UDCCS2		__REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
++#define UDCCS7		__REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
++#define UDCCS12		__REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
++
++#define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
++#define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
++#define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
++#define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
++#define UDCCS_BO_FST	(1 << 5)	/* Force stall */
++#define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
++#define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
++
++/* Isochronous IN - Endpoint 3,8,13 */
++#define UDCCS3		__REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
++#define UDCCS8		__REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
++#define UDCCS13		__REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
++
++#define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
++#define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
++#define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
++#define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
++#define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
++
++/* Isochronous OUT - Endpoint 4,9,14 */
++#define UDCCS4		__REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
++#define UDCCS9		__REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
++#define UDCCS14		__REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
++
++#define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
++#define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
++#define UDCCS_IO_ROF	(1 << 2)	/* Receive overflow */
++#define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
++#define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
++#define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
++
++/* Interrupt IN - Endpoint 5,10,15 */
++#define UDCCS5		__REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
++#define UDCCS10		__REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
++#define UDCCS15		__REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
++
++#define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
++#define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
++#define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
++#define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
++#define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
++#define UDCCS_INT_FST	(1 << 5)	/* Force stall */
++#define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
++
++#define UFNRH		__REG(0x40600060)  /* UDC Frame Number Register High */
++#define UFNRL		__REG(0x40600064)  /* UDC Frame Number Register Low */
++#define UBCR2		__REG(0x40600068)  /* UDC Byte Count Reg 2 */
++#define UBCR4		__REG(0x4060006c)  /* UDC Byte Count Reg 4 */
++#define UBCR7		__REG(0x40600070)  /* UDC Byte Count Reg 7 */
++#define UBCR9		__REG(0x40600074)  /* UDC Byte Count Reg 9 */
++#define UBCR12		__REG(0x40600078)  /* UDC Byte Count Reg 12 */
++#define UBCR14		__REG(0x4060007c)  /* UDC Byte Count Reg 14 */
++#define UDDR0		__REG(0x40600080)  /* UDC Endpoint 0 Data Register */
++#define UDDR1		__REG(0x40600100)  /* UDC Endpoint 1 Data Register */
++#define UDDR2		__REG(0x40600180)  /* UDC Endpoint 2 Data Register */
++#define UDDR3		__REG(0x40600200)  /* UDC Endpoint 3 Data Register */
++#define UDDR4		__REG(0x40600400)  /* UDC Endpoint 4 Data Register */
++#define UDDR5		__REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
++#define UDDR6		__REG(0x40600600)  /* UDC Endpoint 6 Data Register */
++#define UDDR7		__REG(0x40600680)  /* UDC Endpoint 7 Data Register */
++#define UDDR8		__REG(0x40600700)  /* UDC Endpoint 8 Data Register */
++#define UDDR9		__REG(0x40600900)  /* UDC Endpoint 9 Data Register */
++#define UDDR10		__REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
++#define UDDR11		__REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
++#define UDDR12		__REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
++#define UDDR13		__REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
++#define UDDR14		__REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
++#define UDDR15		__REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
++
++#define UICR0		__REG(0x40600050)  /* UDC Interrupt Control Register 0 */
++
++#define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
++#define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
++#define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
++#define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
++#define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
++#define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
++#define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
++#define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
++
++#define UICR1		__REG(0x40600054)  /* UDC Interrupt Control Register 1 */
++
++#define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
++#define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
++#define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
++#define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
++#define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
++#define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
++#define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
++#define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
++
++#define USIR0		__REG(0x40600058)  /* UDC Status Interrupt Register 0 */
++
++#define USIR0_IR0	(1 << 0)	/* Interrupt request ep 0 */
++#define USIR0_IR1	(1 << 1)	/* Interrupt request ep 1 */
++#define USIR0_IR2	(1 << 2)	/* Interrupt request ep 2 */
++#define USIR0_IR3	(1 << 3)	/* Interrupt request ep 3 */
++#define USIR0_IR4	(1 << 4)	/* Interrupt request ep 4 */
++#define USIR0_IR5	(1 << 5)	/* Interrupt request ep 5 */
++#define USIR0_IR6	(1 << 6)	/* Interrupt request ep 6 */
++#define USIR0_IR7	(1 << 7)	/* Interrupt request ep 7 */
++
++#define USIR1		__REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
++
++#define USIR1_IR8	(1 << 0)	/* Interrupt request ep 8 */
++#define USIR1_IR9	(1 << 1)	/* Interrupt request ep 9 */
++#define USIR1_IR10	(1 << 2)	/* Interrupt request ep 10 */
++#define USIR1_IR11	(1 << 3)	/* Interrupt request ep 11 */
++#define USIR1_IR12	(1 << 4)	/* Interrupt request ep 12 */
++#define USIR1_IR13	(1 << 5)	/* Interrupt request ep 13 */
++#define USIR1_IR14	(1 << 6)	/* Interrupt request ep 14 */
++#define USIR1_IR15	(1 << 7)	/* Interrupt request ep 15 */
++
++#elif defined(CONFIG_PXA27x)
++
++#define UDCCR           __REG(0x40600000) /* UDC Control Register */
++#define UDCCR_OEN	(1 << 31)	/* On-the-Go Enable */
++#define UDCCR_AALTHNP	(1 << 30)	/* A-device Alternate Host Negotiation
++					   Protocol Port Support */
++#define UDCCR_AHNP	(1 << 29)	/* A-device Host Negotiation Protocol
++					   Support */
++#define UDCCR_BHNP	(1 << 28)	/* B-device Host Negotiation Protocol
++					   Enable */
++#define UDCCR_DWRE	(1 << 16)	/* Device Remote Wake-up Enable */
++#define UDCCR_ACN	(0x03 << 11)	/* Active UDC configuration Number */
++#define UDCCR_ACN_S	11
++#define UDCCR_AIN	(0x07 << 8)	/* Active UDC interface Number */
++#define UDCCR_AIN_S	8
++#define UDCCR_AAISN	(0x07 << 5)	/* Active UDC Alternate Interface
++					   Setting Number */
++#define UDCCR_AAISN_S	5
++#define UDCCR_SMAC	(1 << 4)	/* Switch Endpoint Memory to Active
++					   Configuration */
++#define UDCCR_EMCE	(1 << 3)	/* Endpoint Memory Configuration
++					   Error */
++#define UDCCR_UDR	(1 << 2)	/* UDC Resume */
++#define UDCCR_UDA	(1 << 1)	/* UDC Active */
++#define UDCCR_UDE	(1 << 0)	/* UDC Enable */
++
++#define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
++#define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
++#define UDCICR_FIFOERR	(1 << 1)	/* FIFO Error interrupt for EP */
++#define UDCICR_PKTCOMPL (1 << 0)	/* Packet Complete interrupt for EP */
++
++#define UDC_INT_FIFOERROR  (0x2)
++#define UDC_INT_PACKETCMP  (0x1)
++
++#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
++#define UDCICR1_IECC	(1 << 31)	/* IntEn - Configuration Change */
++#define UDCICR1_IESOF	(1 << 30)	/* IntEn - Start of Frame */
++#define UDCICR1_IERU	(1 << 29)	/* IntEn - Resume */
++#define UDCICR1_IESU	(1 << 28)	/* IntEn - Suspend */
++#define UDCICR1_IERS	(1 << 27)	/* IntEn - Reset */
++
++#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
++#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
++#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
++#define UDCISR1_IRCC	(1 << 31)	/* IntReq - Configuration Change */
++#define UDCISR1_IRSOF	(1 << 30)	/* IntReq - Start of Frame */
++#define UDCISR1_IRRU	(1 << 29)	/* IntReq - Resume */
++#define UDCISR1_IRSU	(1 << 28)	/* IntReq - Suspend */
++#define UDCISR1_IRRS	(1 << 27)	/* IntReq - Reset */
++
++#define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
++#define UDCOTGICR	__REG(0x40600018) /* UDC On-The-Go interrupt control */
++#define UDCOTGICR_IESF	(1 << 24)	/* OTG SET_FEATURE command recvd */
++#define UDCOTGICR_IEXR	(1 << 17)	/* Extra Transciever Interrupt
++					   Rising Edge Interrupt Enable */
++#define UDCOTGICR_IEXF	(1 << 16)	/* Extra Transciever Interrupt
++					   Falling Edge Interrupt Enable */
++#define UDCOTGICR_IEVV40R (1 << 9)	/* OTG Vbus Valid 4.0V Rising Edge
++					   Interrupt Enable */
++#define UDCOTGICR_IEVV40F (1 << 8)	/* OTG Vbus Valid 4.0V Falling Edge
++					   Interrupt Enable */
++#define UDCOTGICR_IEVV44R (1 << 7)	/* OTG Vbus Valid 4.4V Rising Edge
++					   Interrupt Enable */
++#define UDCOTGICR_IEVV44F (1 << 6)	/* OTG Vbus Valid 4.4V Falling Edge
++					   Interrupt Enable */
++#define UDCOTGICR_IESVR	(1 << 5)	/* OTG Session Valid Rising Edge
++					   Interrupt Enable */
++#define UDCOTGICR_IESVF	(1 << 4)	/* OTG Session Valid Falling Edge
++					   Interrupt Enable */
++#define UDCOTGICR_IESDR	(1 << 3)	/* OTG A-Device SRP Detect Rising
++					   Edge Interrupt Enable */
++#define UDCOTGICR_IESDF	(1 << 2)	/* OTG A-Device SRP Detect Falling
++					   Edge Interrupt Enable */
++#define UDCOTGICR_IEIDR	(1 << 1)	/* OTG ID Change Rising Edge
++					   Interrupt Enable */
++#define UDCOTGICR_IEIDF	(1 << 0)	/* OTG ID Change Falling Edge
++					   Interrupt Enable */
++
++#define UP2OCR		  __REG(0x40600020)  /* USB Port 2 Output Control register */
++
++#define UP2OCR_CPVEN	(1 << 0)	/* Charge Pump Vbus Enable */
++#define UP2OCR_CPVPE	(1 << 1)	/* Charge Pump Vbus Pulse Enable */
++#define UP2OCR_DPPDE	(1 << 2)	/* Host Port 2 Transceiver D+ Pull Down Enable */
++#define UP2OCR_DMPDE	(1 << 3)	/* Host Port 2 Transceiver D- Pull Down Enable */
++#define UP2OCR_DPPUE	(1 << 4)	/* Host Port 2 Transceiver D+ Pull Up Enable */
++#define UP2OCR_DMPUE	(1 << 5)	/* Host Port 2 Transceiver D- Pull Up Enable */
++#define UP2OCR_DPPUBE	(1 << 6)	/* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
++#define UP2OCR_DMPUBE	(1 << 7)	/* Host Port 2 Transceiver D- Pull Up Bypass Enable */
++#define UP2OCR_EXSP		(1 << 8)	/* External Transceiver Speed Control */
++#define UP2OCR_EXSUS	(1 << 9)	/* External Transceiver Speed Enable */
++#define UP2OCR_IDON		(1 << 10)	/* OTG ID Read Enable */
++#define UP2OCR_HXS		(1 << 16)	/* Host Port 2 Transceiver Output Select */
++#define UP2OCR_HXOE		(1 << 17)	/* Host Port 2 Transceiver Output Enable */
++#define UP2OCR_SEOS		(1 << 24)	/* Single-Ended Output Select */
++
++#define UDCCSN(x)	__REG2(0x40600100, (x) << 2)
++#define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
++#define UDCCSR0_SA	(1 << 7)	/* Setup Active */
++#define UDCCSR0_RNE	(1 << 6)	/* Receive FIFO Not Empty */
++#define UDCCSR0_FST	(1 << 5)	/* Force Stall */
++#define UDCCSR0_SST	(1 << 4)	/* Sent Stall */
++#define UDCCSR0_DME	(1 << 3)	/* DMA Enable */
++#define UDCCSR0_FTF	(1 << 2)	/* Flush Transmit FIFO */
++#define UDCCSR0_IPR	(1 << 1)	/* IN Packet Ready */
++#define UDCCSR0_OPC	(1 << 0)	/* OUT Packet Complete */
++
++#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
++#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
++#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
++#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
++#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
++#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
++#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
++#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
++#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
++#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
++#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
++#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
++#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
++#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
++#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
++#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
++#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
++#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
++#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
++#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
++#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
++#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
++#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
++
++#define UDCCSR_DPE	(1 << 9)	/* Data Packet Error */
++#define UDCCSR_FEF	(1 << 8)	/* Flush Endpoint FIFO */
++#define UDCCSR_SP	(1 << 7)	/* Short Packet Control/Status */
++#define UDCCSR_BNE	(1 << 6)	/* Buffer Not Empty (IN endpoints) */
++#define UDCCSR_BNF	(1 << 6)	/* Buffer Not Full (OUT endpoints) */
++#define UDCCSR_FST	(1 << 5)	/* Force STALL */
++#define UDCCSR_SST	(1 << 4)	/* Sent STALL */
++#define UDCCSR_DME	(1 << 3)	/* DMA Enable */
++#define UDCCSR_TRN	(1 << 2)	/* Tx/Rx NAK */
++#define UDCCSR_PC	(1 << 1)	/* Packet Complete */
++#define UDCCSR_FS	(1 << 0)	/* FIFO needs service */
++
++#define UDCBCN(x)	__REG2(0x40600200, (x)<<2)
++#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
++#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
++#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
++#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
++#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
++#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
++#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
++#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
++#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
++#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
++#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
++#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
++#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
++#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
++#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
++#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
++#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
++#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
++#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
++#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
++#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
++#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
++#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
++#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
++
++#define UDCDN(x)	__REG2(0x40600300, (x)<<2)
++#define PHYS_UDCDN(x)	(0x40600300 + ((x)<<2))
++#define PUDCDN(x)	(volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
++#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
++#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
++#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
++#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
++#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
++#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
++#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
++#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
++#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
++#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
++#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
++#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
++#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
++#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
++#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
++#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
++#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
++#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
++#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
++#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
++#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
++#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
++#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
++#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
++
++#define UDCCN(x)       __REG2(0x40600400, (x)<<2)
++#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
++#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
++#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
++#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
++#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
++#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
++#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
++#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
++#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
++#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
++#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
++#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
++#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
++#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
++#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
++#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
++#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
++#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
++#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
++#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
++#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
++#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
++#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
++
++#define UDCCONR_CN	(0x03 << 25)	/* Configuration Number */
++#define UDCCONR_CN_S	(25)
++#define UDCCONR_IN	(0x07 << 22)	/* Interface Number */
++#define UDCCONR_IN_S	(22)
++#define UDCCONR_AISN	(0x07 << 19)	/* Alternate Interface Number */
++#define UDCCONR_AISN_S	(19)
++#define UDCCONR_EN	(0x0f << 15)	/* Endpoint Number */
++#define UDCCONR_EN_S	(15)
++#define UDCCONR_ET	(0x03 << 13)	/* Endpoint Type: */
++#define UDCCONR_ET_S	(13)
++#define UDCCONR_ET_INT	(0x03 << 13)	/*   Interrupt */
++#define UDCCONR_ET_BULK	(0x02 << 13)	/*   Bulk */
++#define UDCCONR_ET_ISO	(0x01 << 13)	/*   Isochronous */
++#define UDCCONR_ET_NU	(0x00 << 13)	/*   Not used */
++#define UDCCONR_ED	(1 << 12)	/* Endpoint Direction */
++#define UDCCONR_MPS	(0x3ff << 2)	/* Maximum Packet Size */
++#define UDCCONR_MPS_S	(2)
++#define UDCCONR_DE	(1 << 1)	/* Double Buffering Enable */
++#define UDCCONR_EE	(1 << 0)	/* Endpoint Enable */
++
++
++#define UDC_INT_FIFOERROR  (0x2)
++#define UDC_INT_PACKETCMP  (0x1)
++
++#define UDC_FNR_MASK     (0x7ff)
++
++#define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
++#define UDC_BCR_MASK    (0x3ff)
++#endif
++
++/*
++ * Fast Infrared Communication Port
++ */
++
++#define FICP		__REG(0x40800000)  /* Start of FICP area */
++#define ICCR0		__REG(0x40800000)  /* ICP Control Register 0 */
++#define ICCR1		__REG(0x40800004)  /* ICP Control Register 1 */
++#define ICCR2		__REG(0x40800008)  /* ICP Control Register 2 */
++#define ICDR		__REG(0x4080000c)  /* ICP Data Register */
++#define ICSR0		__REG(0x40800014)  /* ICP Status Register 0 */
++#define ICSR1		__REG(0x40800018)  /* ICP Status Register 1 */
++
++#define ICCR0_AME	(1 << 7)	/* Address match enable */
++#define ICCR0_TIE	(1 << 6)	/* Transmit FIFO interrupt enable */
++#define ICCR0_RIE	(1 << 5)	/* Recieve FIFO interrupt enable */
++#define ICCR0_RXE	(1 << 4)	/* Receive enable */
++#define ICCR0_TXE	(1 << 3)	/* Transmit enable */
++#define ICCR0_TUS	(1 << 2)	/* Transmit FIFO underrun select */
++#define ICCR0_LBM	(1 << 1)	/* Loopback mode */
++#define ICCR0_ITR	(1 << 0)	/* IrDA transmission */
++
++#define ICCR2_RXP       (1 << 3)	/* Receive Pin Polarity select */
++#define ICCR2_TXP       (1 << 2)	/* Transmit Pin Polarity select */
++#define ICCR2_TRIG	(3 << 0)	/* Receive FIFO Trigger threshold */
++#define ICCR2_TRIG_8    (0 << 0)	/* 	>= 8 bytes */
++#define ICCR2_TRIG_16   (1 << 0)	/*	>= 16 bytes */
++#define ICCR2_TRIG_32   (2 << 0)	/*	>= 32 bytes */
++
++#ifdef CONFIG_PXA27x
++#define ICSR0_EOC	(1 << 6)	/* DMA End of Descriptor Chain */
++#endif
++#define ICSR0_FRE	(1 << 5)	/* Framing error */
++#define ICSR0_RFS	(1 << 4)	/* Receive FIFO service request */
++#define ICSR0_TFS	(1 << 3)	/* Transnit FIFO service request */
++#define ICSR0_RAB	(1 << 2)	/* Receiver abort */
++#define ICSR0_TUR	(1 << 1)	/* Trunsmit FIFO underun */
++#define ICSR0_EIF	(1 << 0)	/* End/Error in FIFO */
++
++#define ICSR1_ROR	(1 << 6)	/* Receiver FIFO underrun  */
++#define ICSR1_CRE	(1 << 5)	/* CRC error */
++#define ICSR1_EOF	(1 << 4)	/* End of frame */
++#define ICSR1_TNF	(1 << 3)	/* Transmit FIFO not full */
++#define ICSR1_RNE	(1 << 2)	/* Receive FIFO not empty */
++#define ICSR1_TBY	(1 << 1)	/* Tramsmiter busy flag */
++#define ICSR1_RSY	(1 << 0)	/* Recevier synchronized flag */
++
++
++/*
++ * Real Time Clock
++ */
++
++#define RCNR		__REG(0x40900000)  /* RTC Count Register */
++#define RTAR		__REG(0x40900004)  /* RTC Alarm Register */
++#define RTSR		__REG(0x40900008)  /* RTC Status Register */
++#define RTTR		__REG(0x4090000C)  /* RTC Timer Trim Register */
++#define PIAR		__REG(0x40900038)  /* Periodic Interrupt Alarm Register */
++
++#define RTSR_PICE	(1 << 15)	/* Periodic interrupt count enable */
++#define RTSR_PIALE	(1 << 14)	/* Periodic interrupt Alarm enable */
++#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
++#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
++#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
++#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
++
++
++/*
++ * OS Timer & Match Registers
++ */
++
++#define OSMR0		__REG(0x40A00000)  /* */
++#define OSMR1		__REG(0x40A00004)  /* */
++#define OSMR2		__REG(0x40A00008)  /* */
++#define OSMR3		__REG(0x40A0000C)  /* */
++#define OSMR4		__REG(0x40A00080)  /* */
++#define OSCR		__REG(0x40A00010)  /* OS Timer Counter Register */
++#define OSCR4		__REG(0x40A00040)  /* OS Timer Counter Register */
++#define OMCR4		__REG(0x40A000C0)  /* */
++#define OSSR		__REG(0x40A00014)  /* OS Timer Status Register */
++#define OWER		__REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
++#define OIER		__REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
++
++#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
++#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
++#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
++#define OSSR_M0		(1 << 0)	/* Match status channel 0 */
++
++#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */
++
++#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
++#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
++#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
++#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
++
++
++/*
++ * Pulse Width Modulator
++ */
++
++#define PWM_CTRL0	__REG(0x40B00000)  /* PWM 0 Control Register */
++#define PWM_PWDUTY0	__REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
++#define PWM_PERVAL0	__REG(0x40B00008)  /* PWM 0 Period Control Register */
++
++#define PWM_CTRL1	__REG(0x40C00000)  /* PWM 1Control Register */
++#define PWM_PWDUTY1	__REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
++#define PWM_PERVAL1	__REG(0x40C00008)  /* PWM 1 Period Control Register */
++
++
++/*
++ * Interrupt Controller
++ */
++
++#define ICIP		__REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
++#define ICMR		__REG(0x40D00004)  /* Interrupt Controller Mask Register */
++#define ICLR		__REG(0x40D00008)  /* Interrupt Controller Level Register */
++#define ICFP		__REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
++#define ICPR		__REG(0x40D00010)  /* Interrupt Controller Pending Register */
++#define ICCR		__REG(0x40D00014)  /* Interrupt Controller Control Register */
++
++
++/*
++ * General Purpose I/O
++ */
++
++#define GPIO0_BASE	((void __iomem *)io_p2v(0x40E00000))
++#define GPIO1_BASE	((void __iomem *)io_p2v(0x40E00004))
++#define GPIO2_BASE	((void __iomem *)io_p2v(0x40E00008))
++#define GPIO3_BASE	((void __iomem *)io_p2v(0x40E00100))
++
++#define GPLR_OFFSET	0x00
++#define GPDR_OFFSET	0x0C
++#define GPSR_OFFSET	0x18
++#define GPCR_OFFSET	0x24
++#define GRER_OFFSET	0x30
++#define GFER_OFFSET	0x3C
++#define GEDR_OFFSET	0x48
++
++#define GPLR0		__REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
++#define GPLR1		__REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
++#define GPLR2		__REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
++
++#define GPDR0		__REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
++#define GPDR1		__REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
++#define GPDR2		__REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
++
++#define GPSR0		__REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
++#define GPSR1		__REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
++#define GPSR2		__REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
++
++#define GPCR0		__REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
++#define GPCR1		__REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
++#define GPCR2		__REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
++
++#define GRER0		__REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
++#define GRER1		__REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
++#define GRER2		__REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
++
++#define GFER0		__REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
++#define GFER1		__REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
++#define GFER2		__REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
++
++#define GEDR0		__REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
++#define GEDR1		__REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
++#define GEDR2		__REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
++
++#define GAFR0_L		__REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
++#define GAFR0_U		__REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
++#define GAFR1_L		__REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
++#define GAFR1_U		__REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
++#define GAFR2_L		__REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
++#define GAFR2_U		__REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO<95-80> */
++#define GAFR3_L		__REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
++#define GAFR3_U		__REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
++
++#define GPLR3		__REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
++#define GPDR3		__REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
++#define GPSR3		__REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
++#define GPCR3		__REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
++#define GRER3		__REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
++#define GFER3		__REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
++#define GEDR3		__REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
++
++/* More handy macros.  The argument is a literal GPIO number. */
++
++#define GPIO_bit(x)	(1 << ((x) & 0x1f))
++
++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
++
++/* Interrupt Controller */
++
++#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
++#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
++#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
++#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
++#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
++
++#define _GPLR(x)	__REG2(0x40E00000, ((x) & 0x60) >> 3)
++#define _GPDR(x)	__REG2(0x40E0000C, ((x) & 0x60) >> 3)
++#define _GPSR(x)	__REG2(0x40E00018, ((x) & 0x60) >> 3)
++#define _GPCR(x)	__REG2(0x40E00024, ((x) & 0x60) >> 3)
++#define _GRER(x)	__REG2(0x40E00030, ((x) & 0x60) >> 3)
++#define _GFER(x)	__REG2(0x40E0003C, ((x) & 0x60) >> 3)
++#define _GEDR(x)	__REG2(0x40E00048, ((x) & 0x60) >> 3)
++#define _GAFR(x)	__REG2(0x40E00054, ((x) & 0x70) >> 2)
++
++#define GPLR(x) 	(*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
++#define GPDR(x)		(*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
++#define GPSR(x)		(*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
++#define GPCR(x)		(*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
++#define GRER(x)		(*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
++#define GFER(x)		(*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
++#define GEDR(x)		(*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
++#define GAFR(x)		(*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
++			 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
++#else
++
++#define GPLR(x)		__REG2(0x40E00000, ((x) & 0x60) >> 3)
++#define GPDR(x)		__REG2(0x40E0000C, ((x) & 0x60) >> 3)
++#define GPSR(x)		__REG2(0x40E00018, ((x) & 0x60) >> 3)
++#define GPCR(x)		__REG2(0x40E00024, ((x) & 0x60) >> 3)
++#define GRER(x)		__REG2(0x40E00030, ((x) & 0x60) >> 3)
++#define GFER(x)		__REG2(0x40E0003C, ((x) & 0x60) >> 3)
++#define GEDR(x)		__REG2(0x40E00048, ((x) & 0x60) >> 3)
++#define GAFR(x)		__REG2(0x40E00054, ((x) & 0x70) >> 2)
++
++#endif
++
++
++/* GPIO alternate function assignments */
++
++#define GPIO1_RST		1	/* reset */
++#define GPIO6_MMCCLK		6	/* MMC Clock */
++#define GPIO7_48MHz		7	/* 48 MHz clock output */
++#define GPIO8_MMCCS0		8	/* MMC Chip Select 0 */
++#define GPIO9_MMCCS1		9	/* MMC Chip Select 1 */
++#define GPIO10_RTCCLK		10	/* real time clock (1 Hz) */
++#define GPIO11_3_6MHz		11	/* 3.6 MHz oscillator out */
++#define GPIO12_32KHz		12	/* 32 kHz out */
++#define GPIO13_MBGNT		13	/* memory controller grant */
++#define GPIO14_MBREQ		14	/* alternate bus master request */
++#define GPIO15_nCS_1		15	/* chip select 1 */
++#define GPIO16_PWM0		16	/* PWM0 output */
++#define GPIO17_PWM1		17	/* PWM1 output */
++#define GPIO18_RDY		18	/* Ext. Bus Ready */
++#define GPIO19_DREQ1		19	/* External DMA Request */
++#define GPIO20_DREQ0		20	/* External DMA Request */
++#define GPIO23_SCLK		23	/* SSP clock */
++#define GPIO24_SFRM		24	/* SSP Frame */
++#define GPIO25_STXD		25	/* SSP transmit */
++#define GPIO26_SRXD		26	/* SSP receive */
++#define GPIO27_SEXTCLK		27	/* SSP ext_clk */
++#define GPIO28_BITCLK		28	/* AC97/I2S bit_clk */
++#define GPIO29_SDATA_IN		29	/* AC97 Sdata_in0 / I2S Sdata_in */
++#define GPIO30_SDATA_OUT	30	/* AC97/I2S Sdata_out */
++#define GPIO31_SYNC		31	/* AC97/I2S sync */
++#define GPIO32_SDATA_IN1	32	/* AC97 Sdata_in1 */
++#define GPIO32_SYSCLK		32	/* I2S System Clock */
++#define GPIO32_MMCCLK		32	/* MMC Clock (PXA270) */
++#define GPIO33_nCS_5		33	/* chip select 5 */
++#define GPIO34_FFRXD		34	/* FFUART receive */
++#define GPIO34_MMCCS0		34	/* MMC Chip Select 0 */
++#define GPIO35_FFCTS		35	/* FFUART Clear to send */
++#define GPIO36_FFDCD		36	/* FFUART Data carrier detect */
++#define GPIO37_FFDSR		37	/* FFUART data set ready */
++#define GPIO38_FFRI		38	/* FFUART Ring Indicator */
++#define GPIO39_MMCCS1		39	/* MMC Chip Select 1 */
++#define GPIO39_FFTXD		39	/* FFUART transmit data */
++#define GPIO40_FFDTR		40	/* FFUART data terminal Ready */
++#define GPIO41_FFRTS		41	/* FFUART request to send */
++#define GPIO42_BTRXD		42	/* BTUART receive data */
++#define GPIO42_HWRXD		42	/* HWUART receive data */
++#define GPIO43_BTTXD		43	/* BTUART transmit data */
++#define GPIO43_HWTXD		43	/* HWUART transmit data */
++#define GPIO44_BTCTS		44	/* BTUART clear to send */
++#define GPIO44_HWCTS		44	/* HWUART clear to send */
++#define GPIO45_BTRTS		45	/* BTUART request to send */
++#define GPIO45_HWRTS		45	/* HWUART request to send */
++#define GPIO45_AC97_SYSCLK	45	/* AC97 System Clock */
++#define GPIO46_ICPRXD		46	/* ICP receive data */
++#define GPIO46_STRXD		46	/* STD_UART receive data */
++#define GPIO47_ICPTXD		47	/* ICP transmit data */
++#define GPIO47_STTXD		47	/* STD_UART transmit data */
++#define GPIO48_nPOE		48	/* Output Enable for Card Space */
++#define GPIO49_nPWE		49	/* Write Enable for Card Space */
++#define GPIO50_nPIOR		50	/* I/O Read for Card Space */
++#define GPIO51_nPIOW		51	/* I/O Write for Card Space */
++#define GPIO52_nPCE_1		52	/* Card Enable for Card Space */
++#define GPIO53_nPCE_2		53	/* Card Enable for Card Space */
++#define GPIO53_MMCCLK		53	/* MMC Clock */
++#define GPIO54_MMCCLK		54	/* MMC Clock */
++#define GPIO54_pSKTSEL		54	/* Socket Select for Card Space */
++#define GPIO54_nPCE_2		54	/* Card Enable for Card Space (PXA27x) */
++#define GPIO55_nPREG		55	/* Card Address bit 26 */
++#define GPIO56_nPWAIT		56	/* Wait signal for Card Space */
++#define GPIO57_nIOIS16		57	/* Bus Width select for I/O Card Space */
++#define GPIO58_LDD_0		58	/* LCD data pin 0 */
++#define GPIO59_LDD_1		59	/* LCD data pin 1 */
++#define GPIO60_LDD_2		60	/* LCD data pin 2 */
++#define GPIO61_LDD_3		61	/* LCD data pin 3 */
++#define GPIO62_LDD_4		62	/* LCD data pin 4 */
++#define GPIO63_LDD_5		63	/* LCD data pin 5 */
++#define GPIO64_LDD_6		64	/* LCD data pin 6 */
++#define GPIO65_LDD_7		65	/* LCD data pin 7 */
++#define GPIO66_LDD_8		66	/* LCD data pin 8 */
++#define GPIO66_MBREQ		66	/* alternate bus master req */
++#define GPIO67_LDD_9		67	/* LCD data pin 9 */
++#define GPIO67_MMCCS0		67	/* MMC Chip Select 0 */
++#define GPIO68_LDD_10		68	/* LCD data pin 10 */
++#define GPIO68_MMCCS1		68	/* MMC Chip Select 1 */
++#define GPIO69_LDD_11		69	/* LCD data pin 11 */
++#define GPIO69_MMCCLK		69	/* MMC_CLK */
++#define GPIO70_LDD_12		70	/* LCD data pin 12 */
++#define GPIO70_RTCCLK		70	/* Real Time clock (1 Hz) */
++#define GPIO71_LDD_13		71	/* LCD data pin 13 */
++#define GPIO71_3_6MHz		71	/* 3.6 MHz Oscillator clock */
++#define GPIO72_LDD_14		72	/* LCD data pin 14 */
++#define GPIO72_32kHz		72	/* 32 kHz clock */
++#define GPIO73_LDD_15		73	/* LCD data pin 15 */
++#define GPIO73_MBGNT		73	/* Memory controller grant */
++#define GPIO74_LCD_FCLK		74	/* LCD Frame clock */
++#define GPIO75_LCD_LCLK		75	/* LCD line clock */
++#define GPIO76_LCD_PCLK		76	/* LCD Pixel clock */
++#define GPIO77_LCD_ACBIAS	77	/* LCD AC Bias */
++#define GPIO78_nCS_2		78	/* chip select 2 */
++#define GPIO79_nCS_3		79	/* chip select 3 */
++#define GPIO80_nCS_4		80	/* chip select 4 */
++#define GPIO81_NSCLK		81	/* NSSP clock */
++#define GPIO82_NSFRM		82	/* NSSP Frame */
++#define GPIO83_NSTXD		83	/* NSSP transmit */
++#define GPIO84_NSRXD		84	/* NSSP receive */
++#define GPIO85_nPCE_1		85	/* Card Enable for Card Space (PXA27x) */
++#define GPIO92_MMCDAT0		92	/* MMC DAT0 (PXA27x) */
++#define GPIO102_nPCE_1		102	/* PCMCIA (PXA27x) */
++#define GPIO109_MMCDAT1		109	/* MMC DAT1 (PXA27x) */
++#define GPIO110_MMCDAT2		110	/* MMC DAT2 (PXA27x) */
++#define GPIO110_MMCCS0		110	/* MMC Chip Select 0 (PXA27x) */
++#define GPIO111_MMCDAT3		111	/* MMC DAT3 (PXA27x) */
++#define GPIO111_MMCCS1		111	/* MMC Chip Select 1 (PXA27x) */
++#define GPIO112_MMCCMD		112	/* MMC CMD (PXA27x) */
++#define GPIO113_I2S_SYSCLK	113	/* I2S System Clock (PXA27x) */
++#define GPIO113_AC97_RESET_N	113	/* AC97 NRESET on (PXA27x) */
++
++/* GPIO alternate function mode & direction */
++
++#define GPIO_IN			0x000
++#define GPIO_OUT		0x080
++#define GPIO_ALT_FN_1_IN	0x100
++#define GPIO_ALT_FN_1_OUT	0x180
++#define GPIO_ALT_FN_2_IN	0x200
++#define GPIO_ALT_FN_2_OUT	0x280
++#define GPIO_ALT_FN_3_IN	0x300
++#define GPIO_ALT_FN_3_OUT	0x380
++#define GPIO_MD_MASK_NR		0x07f
++#define GPIO_MD_MASK_DIR	0x080
++#define GPIO_MD_MASK_FN		0x300
++#define GPIO_DFLT_LOW		0x400
++#define GPIO_DFLT_HIGH		0x800
++
++#define GPIO1_RTS_MD		( 1 | GPIO_ALT_FN_1_IN)
++#define GPIO6_MMCCLK_MD		( 6 | GPIO_ALT_FN_1_OUT)
++#define GPIO7_48MHz_MD		( 7 | GPIO_ALT_FN_1_OUT)
++#define GPIO8_MMCCS0_MD		( 8 | GPIO_ALT_FN_1_OUT)
++#define GPIO9_MMCCS1_MD		( 9 | GPIO_ALT_FN_1_OUT)
++#define GPIO10_RTCCLK_MD	(10 | GPIO_ALT_FN_1_OUT)
++#define GPIO11_3_6MHz_MD	(11 | GPIO_ALT_FN_1_OUT)
++#define GPIO12_32KHz_MD		(12 | GPIO_ALT_FN_1_OUT)
++#define GPIO13_MBGNT_MD		(13 | GPIO_ALT_FN_2_OUT)
++#define GPIO14_MBREQ_MD		(14 | GPIO_ALT_FN_1_IN)
++#define GPIO15_nCS_1_MD		(15 | GPIO_ALT_FN_2_OUT)
++#define GPIO16_PWM0_MD		(16 | GPIO_ALT_FN_2_OUT)
++#define GPIO17_PWM1_MD		(17 | GPIO_ALT_FN_2_OUT)
++#define GPIO18_RDY_MD		(18 | GPIO_ALT_FN_1_IN)
++#define GPIO19_DREQ1_MD		(19 | GPIO_ALT_FN_1_IN)
++#define GPIO20_DREQ0_MD		(20 | GPIO_ALT_FN_1_IN)
++#define GPIO23_SCLK_MD		(23 | GPIO_ALT_FN_2_OUT)
++#define GPIO24_SFRM_MD		(24 | GPIO_ALT_FN_2_OUT)
++#define GPIO25_STXD_MD		(25 | GPIO_ALT_FN_2_OUT)
++#define GPIO26_SRXD_MD		(26 | GPIO_ALT_FN_1_IN)
++#define GPIO27_SEXTCLK_MD	(27 | GPIO_ALT_FN_1_IN)
++#define GPIO28_BITCLK_AC97_MD	(28 | GPIO_ALT_FN_1_IN)
++#define GPIO28_BITCLK_IN_I2S_MD	(28 | GPIO_ALT_FN_2_IN)
++#define GPIO28_BITCLK_OUT_I2S_MD	(28 | GPIO_ALT_FN_1_OUT)
++#define GPIO29_SDATA_IN_AC97_MD	(29 | GPIO_ALT_FN_1_IN)
++#define GPIO29_SDATA_IN_I2S_MD	(29 | GPIO_ALT_FN_2_IN)
++#define GPIO30_SDATA_OUT_AC97_MD	(30 | GPIO_ALT_FN_2_OUT)
++#define GPIO30_SDATA_OUT_I2S_MD	(30 | GPIO_ALT_FN_1_OUT)
++#define GPIO31_SYNC_I2S_MD	(31 | GPIO_ALT_FN_1_OUT)
++#define GPIO31_SYNC_AC97_MD	(31 | GPIO_ALT_FN_2_OUT)
++#define GPIO32_SDATA_IN1_AC97_MD	(32 | GPIO_ALT_FN_1_IN)
++#define GPIO32_SYSCLK_I2S_MD	(32 | GPIO_ALT_FN_1_OUT)
++#define GPIO32_MMCCLK_MD		( 32 | GPIO_ALT_FN_2_OUT)
++#define GPIO33_nCS_5_MD		(33 | GPIO_ALT_FN_2_OUT)
++#define GPIO34_FFRXD_MD		(34 | GPIO_ALT_FN_1_IN)
++#define GPIO34_MMCCS0_MD	(34 | GPIO_ALT_FN_2_OUT)
++#define GPIO35_FFCTS_MD		(35 | GPIO_ALT_FN_1_IN)
++#define GPIO36_FFDCD_MD		(36 | GPIO_ALT_FN_1_IN)
++#define GPIO37_FFDSR_MD		(37 | GPIO_ALT_FN_1_IN)
++#define GPIO38_FFRI_MD		(38 | GPIO_ALT_FN_1_IN)
++#define GPIO39_MMCCS1_MD	(39 | GPIO_ALT_FN_1_OUT)
++#define GPIO39_FFTXD_MD		(39 | GPIO_ALT_FN_2_OUT)
++#define GPIO40_FFDTR_MD		(40 | GPIO_ALT_FN_2_OUT)
++#define GPIO41_FFRTS_MD		(41 | GPIO_ALT_FN_2_OUT)
++#define GPIO42_BTRXD_MD		(42 | GPIO_ALT_FN_1_IN)
++#define GPIO42_HWRXD_MD		(42 | GPIO_ALT_FN_3_IN)
++#define GPIO43_BTTXD_MD		(43 | GPIO_ALT_FN_2_OUT)
++#define GPIO43_HWTXD_MD		(43 | GPIO_ALT_FN_3_OUT)
++#define GPIO44_BTCTS_MD		(44 | GPIO_ALT_FN_1_IN)
++#define GPIO44_HWCTS_MD		(44 | GPIO_ALT_FN_3_IN)
++#define GPIO45_BTRTS_MD		(45 | GPIO_ALT_FN_2_OUT)
++#define GPIO45_HWRTS_MD		(45 | GPIO_ALT_FN_3_OUT)
++#define GPIO45_SYSCLK_AC97_MD		(45 | GPIO_ALT_FN_1_OUT)
++#define GPIO46_ICPRXD_MD	(46 | GPIO_ALT_FN_1_IN)
++#define GPIO46_STRXD_MD		(46 | GPIO_ALT_FN_2_IN)
++#define GPIO47_ICPTXD_MD	(47 | GPIO_ALT_FN_2_OUT)
++#define GPIO47_STTXD_MD		(47 | GPIO_ALT_FN_1_OUT)
++#define GPIO48_nPOE_MD		(48 | GPIO_ALT_FN_2_OUT)
++#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
++#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
++#define GPIO49_HWRXD_MD		(49 | GPIO_ALT_FN_1_IN)
++#define GPIO49_nPWE_MD		(49 | GPIO_ALT_FN_2_OUT)
++#define GPIO50_nPIOR_MD		(50 | GPIO_ALT_FN_2_OUT)
++#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
++#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
++#define GPIO51_nPIOW_MD		(51 | GPIO_ALT_FN_2_OUT)
++#define GPIO52_nPCE_1_MD	(52 | GPIO_ALT_FN_2_OUT)
++#define GPIO53_nPCE_2_MD	(53 | GPIO_ALT_FN_2_OUT)
++#define GPIO53_MMCCLK_MD	(53 | GPIO_ALT_FN_1_OUT)
++#define GPIO54_MMCCLK_MD	(54 | GPIO_ALT_FN_1_OUT)
++#define GPIO54_nPCE_2_MD	(54 | GPIO_ALT_FN_2_OUT)
++#define GPIO54_pSKTSEL_MD	(54 | GPIO_ALT_FN_2_OUT)
++#define GPIO55_nPREG_MD		(55 | GPIO_ALT_FN_2_OUT)
++#define GPIO56_nPWAIT_MD	(56 | GPIO_ALT_FN_1_IN)
++#define GPIO57_nIOIS16_MD	(57 | GPIO_ALT_FN_1_IN)
++#define GPIO58_LDD_0_MD		(58 | GPIO_ALT_FN_2_OUT)
++#define GPIO59_LDD_1_MD		(59 | GPIO_ALT_FN_2_OUT)
++#define GPIO60_LDD_2_MD		(60 | GPIO_ALT_FN_2_OUT)
++#define GPIO61_LDD_3_MD		(61 | GPIO_ALT_FN_2_OUT)
++#define GPIO62_LDD_4_MD		(62 | GPIO_ALT_FN_2_OUT)
++#define GPIO63_LDD_5_MD		(63 | GPIO_ALT_FN_2_OUT)
++#define GPIO64_LDD_6_MD		(64 | GPIO_ALT_FN_2_OUT)
++#define GPIO65_LDD_7_MD		(65 | GPIO_ALT_FN_2_OUT)
++#define GPIO66_LDD_8_MD		(66 | GPIO_ALT_FN_2_OUT)
++#define GPIO66_MBREQ_MD		(66 | GPIO_ALT_FN_1_IN)
++#define GPIO67_LDD_9_MD		(67 | GPIO_ALT_FN_2_OUT)
++#define GPIO67_MMCCS0_MD	(67 | GPIO_ALT_FN_1_OUT)
++#define GPIO68_LDD_10_MD	(68 | GPIO_ALT_FN_2_OUT)
++#define GPIO68_MMCCS1_MD	(68 | GPIO_ALT_FN_1_OUT)
++#define GPIO69_LDD_11_MD	(69 | GPIO_ALT_FN_2_OUT)
++#define GPIO69_MMCCLK_MD	(69 | GPIO_ALT_FN_1_OUT)
++#define GPIO70_LDD_12_MD	(70 | GPIO_ALT_FN_2_OUT)
++#define GPIO70_RTCCLK_MD	(70 | GPIO_ALT_FN_1_OUT)
++#define GPIO71_LDD_13_MD	(71 | GPIO_ALT_FN_2_OUT)
++#define GPIO71_3_6MHz_MD	(71 | GPIO_ALT_FN_1_OUT)
++#define GPIO72_LDD_14_MD	(72 | GPIO_ALT_FN_2_OUT)
++#define GPIO72_32kHz_MD		(72 | GPIO_ALT_FN_1_OUT)
++#define GPIO73_LDD_15_MD	(73 | GPIO_ALT_FN_2_OUT)
++#define GPIO73_MBGNT_MD		(73 | GPIO_ALT_FN_1_OUT)
++#define GPIO74_LCD_FCLK_MD	(74 | GPIO_ALT_FN_2_OUT)
++#define GPIO75_LCD_LCLK_MD	(75 | GPIO_ALT_FN_2_OUT)
++#define GPIO76_LCD_PCLK_MD	(76 | GPIO_ALT_FN_2_OUT)
++#define GPIO77_LCD_ACBIAS_MD	(77 | GPIO_ALT_FN_2_OUT)
++#define GPIO78_nCS_2_MD		(78 | GPIO_ALT_FN_2_OUT)
++#define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
++#define GPIO79_pSKTSEL_MD	(79 | GPIO_ALT_FN_1_OUT)
++#define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
++#define GPIO81_NSSP_CLK_OUT 	(81 | GPIO_ALT_FN_1_OUT)
++#define GPIO81_NSSP_CLK_IN  	(81 | GPIO_ALT_FN_1_IN)
++#define GPIO82_NSSP_FRM_OUT 	(82 | GPIO_ALT_FN_1_OUT)
++#define GPIO82_NSSP_FRM_IN  	(82 | GPIO_ALT_FN_1_IN)
++#define GPIO83_NSSP_TX      	(83 | GPIO_ALT_FN_1_OUT)
++#define GPIO83_NSSP_RX      	(83 | GPIO_ALT_FN_2_IN)
++#define GPIO84_NSSP_TX      	(84 | GPIO_ALT_FN_1_OUT)
++#define GPIO84_NSSP_RX      	(84 | GPIO_ALT_FN_2_IN)
++#define GPIO85_nPCE_1_MD	(85 | GPIO_ALT_FN_1_OUT)
++#define GPIO92_MMCDAT0_MD	(92 | GPIO_ALT_FN_1_OUT)
++#define GPIO102_nPCE_1_MD	(102 | GPIO_ALT_FN_1_OUT)
++#define GPIO104_pSKTSEL_MD	(104 | GPIO_ALT_FN_1_OUT)
++#define GPIO109_MMCDAT1_MD	(109 | GPIO_ALT_FN_1_OUT)
++#define GPIO110_MMCDAT2_MD	(110 | GPIO_ALT_FN_1_OUT)
++#define GPIO110_MMCCS0_MD	(110 | GPIO_ALT_FN_1_OUT)
++#define GPIO111_MMCDAT3_MD	(111 | GPIO_ALT_FN_1_OUT)
++#define GPIO110_MMCCS1_MD	(111 | GPIO_ALT_FN_1_OUT)
++#define GPIO112_MMCCMD_MD	(112 | GPIO_ALT_FN_1_OUT)
++#define GPIO113_I2S_SYSCLK_MD	(113 | GPIO_ALT_FN_1_OUT)
++#define GPIO113_AC97_RESET_N_MD	(113 | GPIO_ALT_FN_2_OUT)
++#define GPIO117_I2CSCL_MD	(117 | GPIO_ALT_FN_1_IN)
++#define GPIO118_I2CSDA_MD	(118 | GPIO_ALT_FN_1_IN)
++
++/*
++ * Power Manager
++ */
++
++#define PMCR		__REG(0x40F00000)  /* Power Manager Control Register */
++#define PSSR		__REG(0x40F00004)  /* Power Manager Sleep Status Register */
++#define PSPR		__REG(0x40F00008)  /* Power Manager Scratch Pad Register */
++#define PWER		__REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
++#define PRER		__REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
++#define PFER		__REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
++#define PEDR		__REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
++#define PCFR		__REG(0x40F0001C)  /* Power Manager General Configuration Register */
++#define PGSR0		__REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
++#define PGSR1		__REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
++#define PGSR2		__REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
++#define PGSR3		__REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
++#define RCSR		__REG(0x40F00030)  /* Reset Controller Status Register */
++
++#define PSLR		__REG(0x40F00034)	/* Power Manager Sleep Config Register */
++#define PSTR		__REG(0x40F00038)	/*Power Manager Standby Config Register */
++#define PSNR		__REG(0x40F0003C)	/*Power Manager Sense Config Register */
++#define PVCR		__REG(0x40F00040)	/*Power Manager VoltageControl Register */
++#define PKWR		__REG(0x40F00050)	/* Power Manager KB Wake-up Enable Reg */
++#define PKSR		__REG(0x40F00054)	/* Power Manager KB Level-Detect Register */
++#define PCMD(x)	__REG2(0x40F00080, (x)<<2)
++#define PCMD0	__REG(0x40F00080 + 0 * 4)
++#define PCMD1	__REG(0x40F00080 + 1 * 4)
++#define PCMD2	__REG(0x40F00080 + 2 * 4)
++#define PCMD3	__REG(0x40F00080 + 3 * 4)
++#define PCMD4	__REG(0x40F00080 + 4 * 4)
++#define PCMD5	__REG(0x40F00080 + 5 * 4)
++#define PCMD6	__REG(0x40F00080 + 6 * 4)
++#define PCMD7	__REG(0x40F00080 + 7 * 4)
++#define PCMD8	__REG(0x40F00080 + 8 * 4)
++#define PCMD9	__REG(0x40F00080 + 9 * 4)
++#define PCMD10	__REG(0x40F00080 + 10 * 4)
++#define PCMD11	__REG(0x40F00080 + 11 * 4)
++#define PCMD12	__REG(0x40F00080 + 12 * 4)
++#define PCMD13	__REG(0x40F00080 + 13 * 4)
++#define PCMD14	__REG(0x40F00080 + 14 * 4)
++#define PCMD15	__REG(0x40F00080 + 15 * 4)
++#define PCMD16	__REG(0x40F00080 + 16 * 4)
++#define PCMD17	__REG(0x40F00080 + 17 * 4)
++#define PCMD18	__REG(0x40F00080 + 18 * 4)
++#define PCMD19	__REG(0x40F00080 + 19 * 4)
++#define PCMD20	__REG(0x40F00080 + 20 * 4)
++#define PCMD21	__REG(0x40F00080 + 21 * 4)
++#define PCMD22	__REG(0x40F00080 + 22 * 4)
++#define PCMD23	__REG(0x40F00080 + 23 * 4)
++#define PCMD24	__REG(0x40F00080 + 24 * 4)
++#define PCMD25	__REG(0x40F00080 + 25 * 4)
++#define PCMD26	__REG(0x40F00080 + 26 * 4)
++#define PCMD27	__REG(0x40F00080 + 27 * 4)
++#define PCMD28	__REG(0x40F00080 + 28 * 4)
++#define PCMD29	__REG(0x40F00080 + 29 * 4)
++#define PCMD30	__REG(0x40F00080 + 30 * 4)
++#define PCMD31	__REG(0x40F00080 + 31 * 4)
++
++#define PCMD_MBC	(1<<12)
++#define PCMD_DCE	(1<<11)
++#define PCMD_LC	(1<<10)
++/* FIXME:  PCMD_SQC need be checked.   */
++#define PCMD_SQC	(3<<8)	/* currently only bit 8 is changeable,
++				   bit 9 should be 0 all day. */
++#define PVCR_VCSA	(0x1<<14)
++#define PVCR_CommandDelay (0xf80)
++#define PCFR_PI2C_EN	(0x1 << 6)
++
++#define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
++#define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
++#define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
++#define PSSR_STS	(1 << 3)	/* Standby Mode Status */
++#define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
++#define PSSR_BFS	(1 << 1)	/* Battery Fault Status */
++#define PSSR_SSS	(1 << 0)	/* Software Sleep Status */
++
++#define PSLR_SL_ROD	(1 << 20)	/* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
++
++#define PCFR_RO		(1 << 15)	/* RDH Override */
++#define PCFR_PO		(1 << 14)	/* PH Override */
++#define PCFR_GPROD	(1 << 12)	/* GPIO nRESET_OUT Disable */
++#define PCFR_L1_EN	(1 << 11)	/* Sleep Mode L1 converter Enable */
++#define PCFR_FVC	(1 << 10)	/* Frequency/Voltage Change */
++#define PCFR_DC_EN	(1 << 7)	/* Sleep/deep-sleep DC-DC Converter Enable */
++#define PCFR_PI2CEN	(1 << 6)	/* Enable PI2C controller */
++#define PCFR_GPR_EN	(1 << 4)	/* nRESET_GPIO Pin Enable */
++#define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */
++#define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */
++#define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */
++#define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */
++
++#define RCSR_GPR	(1 << 3)	/* GPIO Reset */
++#define RCSR_SMR	(1 << 2)	/* Sleep Mode */
++#define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
++#define RCSR_HWR	(1 << 0)	/* Hardware Reset */
++
++#define PWER_GPIO(Nb)	(1 << Nb)	/* GPIO [0..15] wake-up enable     */
++#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable        */
++#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable        */
++#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable        */
++#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable        */
++#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable        */
++#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable        */
++#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable        */
++#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable        */
++#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable        */
++#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable        */
++#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable        */
++#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable        */
++#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable        */
++#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable        */
++#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable        */
++#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */
++#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */
++
++/*
++ * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
++ */
++
++/*
++ * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
++ */
++
++/*
++ * Core Clock
++ */
++
++#define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */
++#define CKEN		__REG(0x41300004)  /* Clock Enable Register */
++#define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */
++#define CCSR		__REG(0x4130000C)  /* Core Clock Status Register */
++
++#define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
++#define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
++#define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
++
++#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
++#define CKEN_CAMERA	(24)	/* Camera Interface Clock Enable */
++#define CKEN_SSP1	(23)	/* SSP1 Unit Clock Enable */
++#define CKEN_MEMC	(22)	/* Memory Controller Clock Enable */
++#define CKEN_MEMSTK	(21)	/* Memory Stick Host Controller */
++#define CKEN_IM		(20)	/* Internal Memory Clock Enable */
++#define CKEN_KEYPAD	(19)	/* Keypad Interface Clock Enable */
++#define CKEN_USIM	(18)	/* USIM Unit Clock Enable */
++#define CKEN_MSL	(17)	/* MSL Unit Clock Enable */
++#define CKEN_LCD	(16)	/* LCD Unit Clock Enable */
++#define CKEN_PWRI2C	(15)	/* PWR I2C Unit Clock Enable */
++#define CKEN_I2C	(14)	/* I2C Unit Clock Enable */
++#define CKEN_FICP	(13)	/* FICP Unit Clock Enable */
++#define CKEN_MMC	(12)	/* MMC Unit Clock Enable */
++#define CKEN_USB	(11)	/* USB Unit Clock Enable */
++#define CKEN_ASSP	(10)	/* ASSP (SSP3) Clock Enable */
++#define CKEN_USBHOST	(10)	/* USB Host Unit Clock Enable */
++#define CKEN_OSTIMER	(9)	/* OS Timer Unit Clock Enable */
++#define CKEN_NSSP	(9)	/* NSSP (SSP2) Clock Enable */
++#define CKEN_I2S	(8)	/* I2S Unit Clock Enable */
++#define CKEN_BTUART	(7)	/* BTUART Unit Clock Enable */
++#define CKEN_FFUART	(6)	/* FFUART Unit Clock Enable */
++#define CKEN_STUART	(5)	/* STUART Unit Clock Enable */
++#define CKEN_HWUART	(4)	/* HWUART Unit Clock Enable */
++#define CKEN_SSP3	(4)	/* SSP3 Unit Clock Enable */
++#define CKEN_SSP	(3)	/* SSP Unit Clock Enable */
++#define CKEN_SSP2	(3)	/* SSP2 Unit Clock Enable */
++#define CKEN_AC97	(2)	/* AC97 Unit Clock Enable */
++#define CKEN_PWM1	(1)	/* PWM1 Clock Enable */
++#define CKEN_PWM0	(0)	/* PWM0 Clock Enable */
++
++#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
++#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
++
++
++/*
++ * LCD
++ */
++
++#define LCCR0		__REG(0x44000000)  /* LCD Controller Control Register 0 */
++#define LCCR1		__REG(0x44000004)  /* LCD Controller Control Register 1 */
++#define LCCR2		__REG(0x44000008)  /* LCD Controller Control Register 2 */
++#define LCCR3		__REG(0x4400000C)  /* LCD Controller Control Register 3 */
++#define LCCR4		__REG(0x44000010)  /* LCD Controller Control Register 3 */
++#define DFBR0		__REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
++#define DFBR1		__REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
++#define LCSR		__REG(0x44000038)  /* LCD Controller Status Register */
++#define LIIDR		__REG(0x4400003C)  /* LCD Controller Interrupt ID Register */
++#define TMEDRGBR	__REG(0x44000040)  /* TMED RGB Seed Register */
++#define TMEDCR		__REG(0x44000044)  /* TMED Control Register */
++
++#define LCCR3_1BPP (0 << 24)
++#define LCCR3_2BPP (1 << 24)
++#define LCCR3_4BPP (2 << 24)
++#define LCCR3_8BPP (3 << 24)
++#define LCCR3_16BPP (4 << 24)
++
++#define LCCR3_PDFOR_0 (0 << 30)
++#define LCCR3_PDFOR_1 (1 << 30)
++#define LCCR3_PDFOR_2 (2 << 30)
++#define LCCR3_PDFOR_3 (3 << 30)
++
++#define LCCR4_PAL_FOR_0 (0 << 15)
++#define LCCR4_PAL_FOR_1 (1 << 15)
++#define LCCR4_PAL_FOR_2 (2 << 15)
++#define LCCR4_PAL_FOR_MASK (3 << 15)
++
++#define FDADR0		__REG(0x44000200)  /* DMA Channel 0 Frame Descriptor Address Register */
++#define FSADR0		__REG(0x44000204)  /* DMA Channel 0 Frame Source Address Register */
++#define FIDR0		__REG(0x44000208)  /* DMA Channel 0 Frame ID Register */
++#define LDCMD0		__REG(0x4400020C)  /* DMA Channel 0 Command Register */
++#define FDADR1		__REG(0x44000210)  /* DMA Channel 1 Frame Descriptor Address Register */
++#define FSADR1		__REG(0x44000214)  /* DMA Channel 1 Frame Source Address Register */
++#define FIDR1		__REG(0x44000218)  /* DMA Channel 1 Frame ID Register */
++#define LDCMD1		__REG(0x4400021C)  /* DMA Channel 1 Command Register */
++
++#define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
++#define LCCR0_CMS	(1 << 1)	/* Color/Monochrome Display Select */
++#define LCCR0_Color     (LCCR0_CMS*0)   /*  Color display                  */
++#define LCCR0_Mono      (LCCR0_CMS*1)   /*  Monochrome display             */
++#define LCCR0_SDS	(1 << 2)	/* Single/Dual Panel Display       */
++                                        /* Select                          */
++#define LCCR0_Sngl      (LCCR0_SDS*0)   /*  Single panel display           */
++#define LCCR0_Dual      (LCCR0_SDS*1)   /*  Dual panel display             */
++
++#define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
++#define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
++#define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
++#define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
++#define LCCR0_PAS	(1 << 7)	/* Passive/Active display Select   */
++#define LCCR0_Pas       (LCCR0_PAS*0)   /*  Passive display (STN)          */
++#define LCCR0_Act       (LCCR0_PAS*1)   /*  Active display (TFT)           */
++#define LCCR0_DPD	(1 << 9)	/* Double Pixel Data (monochrome   */
++                                        /* display mode)                   */
++#define LCCR0_4PixMono  (LCCR0_DPD*0)   /*  4-Pixel/clock Monochrome       */
++                                        /*  display                        */
++#define LCCR0_8PixMono  (LCCR0_DPD*1)   /*  8-Pixel/clock Monochrome       */
++                                        /*  display                        */
++#define LCCR0_DIS	(1 << 10)	/* LCD Disable */
++#define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
++#define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
++#define LCCR0_PDD_S	12
++#define LCCR0_BM	(1 << 20) 	/* Branch mask */
++#define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
++#define LCCR0_LCDT      (1 << 22)       /* LCD panel type */
++#define LCCR0_RDSTM     (1 << 23)       /* Read status interrupt mask */
++#define LCCR0_CMDIM     (1 << 24)       /* Command interrupt mask */
++#define LCCR0_OUC       (1 << 25)       /* Overlay Underlay control bit */
++#define LCCR0_LDDALT    (1 << 26)       /* LDD alternate mapping control */
++
++#define LCCR1_PPL       Fld (10, 0)      /* Pixels Per Line - 1 */
++#define LCCR1_DisWdth(Pixel)            /* Display Width [1..800 pix.]  */ \
++                        (((Pixel) - 1) << FShft (LCCR1_PPL))
++
++#define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization     */
++#define LCCR1_HorSnchWdth(Tpix)         /* Horizontal Synchronization     */ \
++                                        /* pulse Width [1..64 Tpix]       */ \
++                        (((Tpix) - 1) << FShft (LCCR1_HSW))
++
++#define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait    */
++                                        /* count - 1 [Tpix]                */
++#define LCCR1_EndLnDel(Tpix)            /*  End-of-Line Delay              */ \
++                                        /*  [1..256 Tpix]                  */ \
++                        (((Tpix) - 1) << FShft (LCCR1_ELW))
++
++#define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock   */
++                                        /* Wait count - 1 [Tpix]           */
++#define LCCR1_BegLnDel(Tpix)            /*  Beginning-of-Line Delay        */ \
++                                        /*  [1..256 Tpix]                  */ \
++                        (((Tpix) - 1) << FShft (LCCR1_BLW))
++
++
++#define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1              */
++#define LCCR2_DisHght(Line)             /*  Display Height [1..1024 lines] */ \
++                        (((Line) - 1) << FShft (LCCR2_LPP))
++
++#define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse  */
++                                        /* Width - 1 [Tln] (L_FCLK)        */
++#define LCCR2_VrtSnchWdth(Tln)          /*  Vertical Synchronization pulse */ \
++                                        /*  Width [1..64 Tln]              */ \
++                        (((Tln) - 1) << FShft (LCCR2_VSW))
++
++#define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait    */
++                                        /* count [Tln]                     */
++#define LCCR2_EndFrmDel(Tln)            /*  End-of-Frame Delay             */ \
++                                        /*  [0..255 Tln]                   */ \
++                        ((Tln) << FShft (LCCR2_EFW))
++
++#define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock   */
++                                        /* Wait count [Tln]                */
++#define LCCR2_BegFrmDel(Tln)            /*  Beginning-of-Frame Delay       */ \
++                                        /*  [0..255 Tln]                   */ \
++                        ((Tln) << FShft (LCCR2_BFW))
++
++#if 0
++#define LCCR3_PCD	(0xff)		/* Pixel clock divisor */
++#define LCCR3_ACB	(0xff << 8)	/* AC Bias pin frequency */
++#define LCCR3_ACB_S	8
++#endif
++
++#define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
++#define LCCR3_API_S	16
++#define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
++#define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
++#define LCCR3_PCP	(1 << 22)	/* Pixel Clock Polarity (L_PCLK)   */
++#define LCCR3_PixRsEdg  (LCCR3_PCP*0)   /*  Pixel clock Rising-Edge        */
++#define LCCR3_PixFlEdg  (LCCR3_PCP*1)   /*  Pixel clock Falling-Edge       */
++
++#define LCCR3_OEP       (1 << 23)       /* Output Enable Polarity (L_BIAS, */
++                                        /* active display mode)            */
++#define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High      */
++#define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low       */
++
++#if 0
++#define LCCR3_BPP	(7 << 24)	/* bits per pixel */
++#define LCCR3_BPP_S	24
++#endif
++#define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
++
++
++#define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
++#define LCCR3_PixClkDiv(Div)            /* Pixel Clock Divisor */ \
++                        (((Div) << FShft (LCCR3_PCD)))
++
++
++#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
++#define LCCR3_Bpp(Bpp)                  /* Bit Per Pixel */ \
++                        (((Bpp) << FShft (LCCR3_BPP)))
++
++#define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
++#define LCCR3_Acb(Acb)                  /* BAC Bias */ \
++                        (((Acb) << FShft (LCCR3_ACB)))
++
++#define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  Horizontal Synchronization     */
++                                        /*  pulse active High              */
++#define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  Horizontal Synchronization     */
++
++#define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  Vertical Synchronization pulse */
++                                        /*  active High                    */
++#define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  Vertical Synchronization pulse */
++                                        /*  active Low                     */
++
++#define LCSR_LDD	(1 << 0)	/* LCD Disable Done */
++#define LCSR_SOF	(1 << 1)	/* Start of frame */
++#define LCSR_BER	(1 << 2)	/* Bus error */
++#define LCSR_ABC	(1 << 3)	/* AC Bias count */
++#define LCSR_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
++#define LCSR_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
++#define LCSR_OU		(1 << 6)	/* output FIFO underrun */
++#define LCSR_QD		(1 << 7)	/* quick disable */
++#define LCSR_EOF	(1 << 8)	/* end of frame */
++#define LCSR_BS		(1 << 9)	/* branch status */
++#define LCSR_SINT	(1 << 10)	/* subsequent interrupt */
++
++#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
++
++#define LCSR_LDD	(1 << 0)	/* LCD Disable Done */
++#define LCSR_SOF	(1 << 1)	/* Start of frame */
++#define LCSR_BER	(1 << 2)	/* Bus error */
++#define LCSR_ABC	(1 << 3)	/* AC Bias count */
++#define LCSR_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
++#define LCSR_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
++#define LCSR_OU		(1 << 6)	/* output FIFO underrun */
++#define LCSR_QD		(1 << 7)	/* quick disable */
++#define LCSR_EOF	(1 << 8)	/* end of frame */
++#define LCSR_BS		(1 << 9)	/* branch status */
++#define LCSR_SINT	(1 << 10)	/* subsequent interrupt */
++
++#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
++
++#ifdef CONFIG_PXA27x
++
++/*
++ * Keypad
++ */
++#define KPC             __REG(0x41500000) /* Keypad Interface Control register */
++#define KPDK            __REG(0x41500008) /* Keypad Interface Direct Key register */
++#define KPREC           __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
++#define KPMK            __REG(0x41500018) /* Keypad Interface Matrix Key register */
++#define KPAS            __REG(0x41500020) /* Keypad Interface Automatic Scan register */
++#define KPASMKP0        __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
++#define KPASMKP1        __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
++#define KPASMKP2        __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
++#define KPASMKP3        __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
++#define KPKDI           __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
++
++#define KPC_AS          (0x1 << 30)  /* Automatic Scan bit */
++#define KPC_ASACT       (0x1 << 29)  /* Automatic Scan on Activity */
++#define KPC_MI          (0x1 << 22)  /* Matrix interrupt bit */
++#define KPC_IMKP        (0x1 << 21)  /* Ignore Multiple Key Press */
++#define KPC_MS7         (0x1 << 20)  /* Matrix scan line 7 */
++#define KPC_MS6         (0x1 << 19)  /* Matrix scan line 6 */
++#define KPC_MS5         (0x1 << 18)  /* Matrix scan line 5 */
++#define KPC_MS4         (0x1 << 17)  /* Matrix scan line 4 */
++#define KPC_MS3         (0x1 << 16)  /* Matrix scan line 3 */
++#define KPC_MS2         (0x1 << 15)  /* Matrix scan line 2 */
++#define KPC_MS1         (0x1 << 14)  /* Matrix scan line 1 */
++#define KPC_MS0         (0x1 << 13)  /* Matrix scan line 0 */
++#define KPC_MS_ALL      (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
++#define KPC_ME          (0x1 << 12)  /* Matrix Keypad Enable */
++#define KPC_MIE         (0x1 << 11)  /* Matrix Interrupt Enable */
++#define KPC_DK_DEB_SEL	(0x1 <<  9)  /* Direct Keypad Debounce Select */
++#define KPC_DI          (0x1 <<  5)  /* Direct key interrupt bit */
++#define KPC_RE_ZERO_DEB (0x1 <<  4)  /* Rotary Encoder Zero Debounce */
++#define KPC_REE1        (0x1 <<  3)  /* Rotary Encoder1 Enable */
++#define KPC_REE0        (0x1 <<  2)  /* Rotary Encoder0 Enable */
++#define KPC_DE          (0x1 <<  1)  /* Direct Keypad Enable */
++#define KPC_DIE         (0x1 <<  0)  /* Direct Keypad interrupt Enable */
++
++#define KPDK_DKP        (0x1 << 31)
++#define KPDK_DK7        (0x1 <<  7)
++#define KPDK_DK6        (0x1 <<  6)
++#define KPDK_DK5        (0x1 <<  5)
++#define KPDK_DK4        (0x1 <<  4)
++#define KPDK_DK3        (0x1 <<  3)
++#define KPDK_DK2        (0x1 <<  2)
++#define KPDK_DK1        (0x1 <<  1)
++#define KPDK_DK0        (0x1 <<  0)
++
++#define KPREC_OF1       (0x1 << 31)
++#define kPREC_UF1       (0x1 << 30)
++#define KPREC_OF0       (0x1 << 15)
++#define KPREC_UF0       (0x1 << 14)
++
++#define KPMK_MKP        (0x1 << 31)
++#define KPAS_SO         (0x1 << 31)
++#define KPASMKPx_SO     (0x1 << 31)
++
++/* Camera Interface */
++#define CICR0		__REG(0x50000000)
++#define CICR1		__REG(0x50000004)
++#define CICR2		__REG(0x50000008)
++#define CICR3		__REG(0x5000000C)
++#define CICR4		__REG(0x50000010)
++#define CISR		__REG(0x50000014)
++#define CIFR		__REG(0x50000018)
++#define CITOR		__REG(0x5000001C)
++#define CIBR0		__REG(0x50000028)
++#define CIBR1		__REG(0x50000030)
++#define CIBR2		__REG(0x50000038)
++
++#define CICR0_DMAEN	(1 << 31)	/* DMA request enable */
++#define CICR0_PAR_EN	(1 << 30)	/* Parity enable */
++#define CICR0_SL_CAP_EN	(1 << 29)	/* Capture enable for slave mode */
++#define CICR0_ENB	(1 << 28)	/* Camera interface enable */
++#define CICR0_DIS	(1 << 27)	/* Camera interface disable */
++#define CICR0_SIM	(0x7 << 24)	/* Sensor interface mode mask */
++#define CICR0_TOM	(1 << 9)	/* Time-out mask */
++#define CICR0_RDAVM	(1 << 8)	/* Receive-data-available mask */
++#define CICR0_FEM	(1 << 7)	/* FIFO-empty mask */
++#define CICR0_EOLM	(1 << 6)	/* End-of-line mask */
++#define CICR0_PERRM	(1 << 5)	/* Parity-error mask */
++#define CICR0_QDM	(1 << 4)	/* Quick-disable mask */
++#define CICR0_CDM	(1 << 3)	/* Disable-done mask */
++#define CICR0_SOFM	(1 << 2)	/* Start-of-frame mask */
++#define CICR0_EOFM	(1 << 1)	/* End-of-frame mask */
++#define CICR0_FOM	(1 << 0)	/* FIFO-overrun mask */
++
++#define CICR1_TBIT	(1 << 31)	/* Transparency bit */
++#define CICR1_RGBT_CONV	(0x3 << 30)	/* RGBT conversion mask */
++#define CICR1_PPL	(0x7ff << 15)	/* Pixels per line mask */
++#define CICR1_RGB_CONV	(0x7 << 12)	/* RGB conversion mask */
++#define CICR1_RGB_F	(1 << 11)	/* RGB format */
++#define CICR1_YCBCR_F	(1 << 10)	/* YCbCr format */
++#define CICR1_RGB_BPP	(0x7 << 7)	/* RGB bis per pixel mask */
++#define CICR1_RAW_BPP	(0x3 << 5)	/* Raw bis per pixel mask */
++#define CICR1_COLOR_SP	(0x3 << 3)	/* Color space mask */
++#define CICR1_DW	(0x7 << 0)	/* Data width mask */
++
++#define CICR2_BLW	(0xff << 24)	/* Beginning-of-line pixel clock
++					   wait count mask */
++#define CICR2_ELW	(0xff << 16)	/* End-of-line pixel clock
++					   wait count mask */
++#define CICR2_HSW	(0x3f << 10)	/* Horizontal sync pulse width mask */
++#define CICR2_BFPW	(0x3f << 3)	/* Beginning-of-frame pixel clock
++					   wait count mask */
++#define CICR2_FSW	(0x7 << 0)	/* Frame stabilization
++					   wait count mask */
++
++#define CICR3_BFW	(0xff << 24)	/* Beginning-of-frame line clock
++					   wait count mask */
++#define CICR3_EFW	(0xff << 16)	/* End-of-frame line clock
++					   wait count mask */
++#define CICR3_VSW	(0x3f << 10)	/* Vertical sync pulse width mask */
++#define CICR3_BFPW	(0x3f << 3)	/* Beginning-of-frame pixel clock
++					   wait count mask */
++#define CICR3_LPF	(0x7ff << 0)	/* Lines per frame mask */
++
++#define CICR4_MCLK_DLY	(0x3 << 24)	/* MCLK Data Capture Delay mask */
++#define CICR4_PCLK_EN	(1 << 23)	/* Pixel clock enable */
++#define CICR4_PCP	(1 << 22)	/* Pixel clock polarity */
++#define CICR4_HSP	(1 << 21)	/* Horizontal sync polarity */
++#define CICR4_VSP	(1 << 20)	/* Vertical sync polarity */
++#define CICR4_MCLK_EN	(1 << 19)	/* MCLK enable */
++#define CICR4_FR_RATE	(0x7 << 8)	/* Frame rate mask */
++#define CICR4_DIV	(0xff << 0)	/* Clock divisor mask */
++
++#define CISR_FTO	(1 << 15)	/* FIFO time-out */
++#define CISR_RDAV_2	(1 << 14)	/* Channel 2 receive data available */
++#define CISR_RDAV_1	(1 << 13)	/* Channel 1 receive data available */
++#define CISR_RDAV_0	(1 << 12)	/* Channel 0 receive data available */
++#define CISR_FEMPTY_2	(1 << 11)	/* Channel 2 FIFO empty */
++#define CISR_FEMPTY_1	(1 << 10)	/* Channel 1 FIFO empty */
++#define CISR_FEMPTY_0	(1 << 9)	/* Channel 0 FIFO empty */
++#define CISR_EOL	(1 << 8)	/* End of line */
++#define CISR_PAR_ERR	(1 << 7)	/* Parity error */
++#define CISR_CQD	(1 << 6)	/* Camera interface quick disable */
++#define CISR_CDD	(1 << 5)	/* Camera interface disable done */
++#define CISR_SOF	(1 << 4)	/* Start of frame */
++#define CISR_EOF	(1 << 3)	/* End of frame */
++#define CISR_IFO_2	(1 << 2)	/* FIFO overrun for Channel 2 */
++#define CISR_IFO_1	(1 << 1)	/* FIFO overrun for Channel 1 */
++#define CISR_IFO_0	(1 << 0)	/* FIFO overrun for Channel 0 */
++
++#define CIFR_FLVL2	(0x7f << 23)	/* FIFO 2 level mask */
++#define CIFR_FLVL1	(0x7f << 16)	/* FIFO 1 level mask */
++#define CIFR_FLVL0	(0xff << 8)	/* FIFO 0 level mask */
++#define CIFR_THL_0	(0x3 << 4)	/* Threshold Level for Channel 0 FIFO */
++#define CIFR_RESET_F	(1 << 3)	/* Reset input FIFOs */
++#define CIFR_FEN2	(1 << 2)	/* FIFO enable for channel 2 */
++#define CIFR_FEN1	(1 << 1)	/* FIFO enable for channel 1 */
++#define CIFR_FEN0	(1 << 0)	/* FIFO enable for channel 0 */
++
++#define SRAM_SIZE		0x40000 /* 4x64K  */
++
++#define SRAM_MEM_PHYS		0x5C000000
++
++#define IMPMCR		__REG(0x58000000) /* IM Power Management Control Reg */
++#define IMPMSR		__REG(0x58000008) /* IM Power Management Status Reg */
++
++#define IMPMCR_PC3		(0x3 << 22) /* Bank 3 Power Control */
++#define IMPMCR_PC3_RUN_MODE	(0x0 << 22) /*   Run mode */
++#define IMPMCR_PC3_STANDBY_MODE	(0x1 << 22) /*   Standby mode */
++#define IMPMCR_PC3_AUTO_MODE	(0x3 << 22) /*   Automatically controlled */
++
++#define IMPMCR_PC2		(0x3 << 20) /* Bank 2 Power Control */
++#define IMPMCR_PC2_RUN_MODE	(0x0 << 20) /*   Run mode */
++#define IMPMCR_PC2_STANDBY_MODE	(0x1 << 20) /*   Standby mode */
++#define IMPMCR_PC2_AUTO_MODE	(0x3 << 20) /*   Automatically controlled */
++
++#define IMPMCR_PC1		(0x3 << 18) /* Bank 1 Power Control */
++#define IMPMCR_PC1_RUN_MODE	(0x0 << 18) /*   Run mode */
++#define IMPMCR_PC1_STANDBY_MODE	(0x1 << 18) /*   Standby mode */
++#define IMPMCR_PC1_AUTO_MODE	(0x3 << 18) /*   Automatically controlled */
++
++#define IMPMCR_PC0		(0x3 << 16) /* Bank 0 Power Control */
++#define IMPMCR_PC0_RUN_MODE	(0x0 << 16) /*   Run mode */
++#define IMPMCR_PC0_STANDBY_MODE	(0x1 << 16) /*   Standby mode */
++#define IMPMCR_PC0_AUTO_MODE	(0x3 << 16) /*   Automatically controlled */
++
++#define IMPMCR_AW3		(1 << 11) /* Bank 3 Automatic Wake-up enable */
++#define IMPMCR_AW2		(1 << 10) /* Bank 2 Automatic Wake-up enable */
++#define IMPMCR_AW1		(1 << 9)  /* Bank 1 Automatic Wake-up enable */
++#define IMPMCR_AW0		(1 << 8)  /* Bank 0 Automatic Wake-up enable */
++
++#define IMPMCR_DST		(0xFF << 0) /* Delay Standby Time, ms */
++
++#define IMPMSR_PS3		(0x3 << 6) /* Bank 3 Power Status: */
++#define IMPMSR_PS3_RUN_MODE	(0x0 << 6) /*    Run mode */
++#define IMPMSR_PS3_STANDBY_MODE	(0x1 << 6) /*    Standby mode */
++
++#define IMPMSR_PS2		(0x3 << 4) /* Bank 2 Power Status: */
++#define IMPMSR_PS2_RUN_MODE	(0x0 << 4) /*    Run mode */
++#define IMPMSR_PS2_STANDBY_MODE	(0x1 << 4) /*    Standby mode */
++
++#define IMPMSR_PS1		(0x3 << 2) /* Bank 1 Power Status: */
++#define IMPMSR_PS1_RUN_MODE	(0x0 << 2) /*    Run mode */
++#define IMPMSR_PS1_STANDBY_MODE	(0x1 << 2) /*    Standby mode */
++
++#define IMPMSR_PS0		(0x3 << 0) /* Bank 0 Power Status: */
++#define IMPMSR_PS0_RUN_MODE	(0x0 << 0) /*    Run mode */
++#define IMPMSR_PS0_STANDBY_MODE	(0x1 << 0) /*    Standby mode */
++
++#endif
++
++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
++/*
++ * UHC: USB Host Controller (OHCI-like) register definitions
++ */
++#define UHC_BASE_PHYS	(0x4C000000)
++#define UHCREV		__REG(0x4C000000) /* UHC HCI Spec Revision */
++#define UHCHCON		__REG(0x4C000004) /* UHC Host Control Register */
++#define UHCCOMS		__REG(0x4C000008) /* UHC Command Status Register */
++#define UHCINTS		__REG(0x4C00000C) /* UHC Interrupt Status Register */
++#define UHCINTE		__REG(0x4C000010) /* UHC Interrupt Enable */
++#define UHCINTD		__REG(0x4C000014) /* UHC Interrupt Disable */
++#define UHCHCCA		__REG(0x4C000018) /* UHC Host Controller Comm. Area */
++#define UHCPCED		__REG(0x4C00001C) /* UHC Period Current Endpt Descr */
++#define UHCCHED		__REG(0x4C000020) /* UHC Control Head Endpt Descr */
++#define UHCCCED		__REG(0x4C000024) /* UHC Control Current Endpt Descr */
++#define UHCBHED		__REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
++#define UHCBCED		__REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
++#define UHCDHEAD	__REG(0x4C000030) /* UHC Done Head */
++#define UHCFMI		__REG(0x4C000034) /* UHC Frame Interval */
++#define UHCFMR		__REG(0x4C000038) /* UHC Frame Remaining */
++#define UHCFMN		__REG(0x4C00003C) /* UHC Frame Number */
++#define UHCPERS		__REG(0x4C000040) /* UHC Periodic Start */
++#define UHCLS		__REG(0x4C000044) /* UHC Low Speed Threshold */
++
++#define UHCRHDA		__REG(0x4C000048) /* UHC Root Hub Descriptor A */
++#define UHCRHDA_NOCP	(1 << 12)	/* No over current protection */
++
++#define UHCRHDB		__REG(0x4C00004C) /* UHC Root Hub Descriptor B */
++#define UHCRHS		__REG(0x4C000050) /* UHC Root Hub Status */
++#define UHCRHPS1	__REG(0x4C000054) /* UHC Root Hub Port 1 Status */
++#define UHCRHPS2	__REG(0x4C000058) /* UHC Root Hub Port 2 Status */
++#define UHCRHPS3	__REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
++
++#define UHCSTAT		__REG(0x4C000060) /* UHC Status Register */
++#define UHCSTAT_UPS3	(1 << 16)	/* USB Power Sense Port3 */
++#define UHCSTAT_SBMAI	(1 << 15)	/* System Bus Master Abort Interrupt*/
++#define UHCSTAT_SBTAI	(1 << 14)	/* System Bus Target Abort Interrupt*/
++#define UHCSTAT_UPRI	(1 << 13)	/* USB Port Resume Interrupt */
++#define UHCSTAT_UPS2	(1 << 12)	/* USB Power Sense Port 2 */
++#define UHCSTAT_UPS1	(1 << 11)	/* USB Power Sense Port 1 */
++#define UHCSTAT_HTA	(1 << 10)	/* HCI Target Abort */
++#define UHCSTAT_HBA	(1 << 8)	/* HCI Buffer Active */
++#define UHCSTAT_RWUE	(1 << 7)	/* HCI Remote Wake Up Event */
++
++#define UHCHR           __REG(0x4C000064) /* UHC Reset Register */
++#define UHCHR_SSEP3	(1 << 11)	/* Sleep Standby Enable for Port3 */
++#define UHCHR_SSEP2	(1 << 10)	/* Sleep Standby Enable for Port2 */
++#define UHCHR_SSEP1	(1 << 9)	/* Sleep Standby Enable for Port1 */
++#define UHCHR_PCPL	(1 << 7)	/* Power control polarity low */
++#define UHCHR_PSPL	(1 << 6)	/* Power sense polarity low */
++#define UHCHR_SSE	(1 << 5)	/* Sleep Standby Enable */
++#define UHCHR_UIT	(1 << 4)	/* USB Interrupt Test */
++#define UHCHR_SSDC	(1 << 3)	/* Simulation Scale Down Clock */
++#define UHCHR_CGR	(1 << 2)	/* Clock Generation Reset */
++#define UHCHR_FHR	(1 << 1)	/* Force Host Controller Reset */
++#define UHCHR_FSBIR	(1 << 0)	/* Force System Bus Iface Reset */
++
++#define UHCHIE          __REG(0x4C000068) /* UHC Interrupt Enable Register*/
++#define UHCHIE_UPS3IE	(1 << 14)	/* Power Sense Port3 IntEn */
++#define UHCHIE_UPRIE	(1 << 13)	/* Port Resume IntEn */
++#define UHCHIE_UPS2IE	(1 << 12)	/* Power Sense Port2 IntEn */
++#define UHCHIE_UPS1IE	(1 << 11)	/* Power Sense Port1 IntEn */
++#define UHCHIE_TAIE	(1 << 10)	/* HCI Interface Transfer Abort
++					   Interrupt Enable*/
++#define UHCHIE_HBAIE	(1 << 8)	/* HCI Buffer Active IntEn */
++#define UHCHIE_RWIE	(1 << 7)	/* Remote Wake-up IntEn */
++
++#define UHCHIT          __REG(0x4C00006C) /* UHC Interrupt Test register */
++
++#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
++
++/* PWRMODE register M field values */
++
++#define PWRMODE_IDLE		0x1
++#define PWRMODE_STANDBY		0x2
++#define PWRMODE_SLEEP		0x3
++#define PWRMODE_DEEPSLEEP	0x7
++
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/regs-ssp.h linux-2.6.25-rc4/include/asm-arm/arch/regs-ssp.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/regs-ssp.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/regs-ssp.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,113 @@
++#ifndef __ASM_ARCH_REGS_SSP_H
++#define __ASM_ARCH_REGS_SSP_H
++
++/*
++ * SSP Serial Port Registers
++ * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
++ * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
++ */
++
++#define SSCR0		(0x00)  /* SSP Control Register 0 */
++#define SSCR1		(0x04)  /* SSP Control Register 1 */
++#define SSSR		(0x08)  /* SSP Status Register */
++#define SSITR		(0x0C)  /* SSP Interrupt Test Register */
++#define SSDR		(0x10)  /* SSP Data Write/Data Read Register */
++
++#define SSTO		(0x28)  /* SSP Time Out Register */
++#define SSPSP		(0x2C)  /* SSP Programmable Serial Protocol */
++#define SSTSA		(0x30)  /* SSP Tx Timeslot Active */
++#define SSRSA		(0x34)  /* SSP Rx Timeslot Active */
++#define SSTSS		(0x38)  /* SSP Timeslot Status */
++#define SSACD		(0x3C)  /* SSP Audio Clock Divider */
++
++/* Common PXA2xx bits first */
++#define SSCR0_DSS	(0x0000000f)	/* Data Size Select (mask) */
++#define SSCR0_DataSize(x)  ((x) - 1)	/* Data Size Select [4..16] */
++#define SSCR0_FRF	(0x00000030)	/* FRame Format (mask) */
++#define SSCR0_Motorola	(0x0 << 4)	/* Motorola's Serial Peripheral Interface (SPI) */
++#define SSCR0_TI	(0x1 << 4)	/* Texas Instruments' Synchronous Serial Protocol (SSP) */
++#define SSCR0_National	(0x2 << 4)	/* National Microwire */
++#define SSCR0_ECS	(1 << 6)	/* External clock select */
++#define SSCR0_SSE	(1 << 7)	/* Synchronous Serial Port Enable */
++#if defined(CONFIG_PXA25x)
++#define SSCR0_SCR	(0x0000ff00)	/* Serial Clock Rate (mask) */
++#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
++#elif defined(CONFIG_PXA27x)
++#define SSCR0_SCR	(0x000fff00)	/* Serial Clock Rate (mask) */
++#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
++#define SSCR0_EDSS	(1 << 20)	/* Extended data size select */
++#define SSCR0_NCS	(1 << 21)	/* Network clock select */
++#define SSCR0_RIM	(1 << 22)	/* Receive FIFO overrrun interrupt mask */
++#define SSCR0_TUM	(1 << 23)	/* Transmit FIFO underrun interrupt mask */
++#define SSCR0_FRDC	(0x07000000)	/* Frame rate divider control (mask) */
++#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)	/* Time slots per frame [1..8] */
++#define SSCR0_ADC	(1 << 30)	/* Audio clock select */
++#define SSCR0_MOD	(1 << 31)	/* Mode (normal or network) */
++#endif
++
++#define SSCR1_RIE	(1 << 0)	/* Receive FIFO Interrupt Enable */
++#define SSCR1_TIE	(1 << 1)	/* Transmit FIFO Interrupt Enable */
++#define SSCR1_LBM	(1 << 2)	/* Loop-Back Mode */
++#define SSCR1_SPO	(1 << 3)	/* Motorola SPI SSPSCLK polarity setting */
++#define SSCR1_SPH	(1 << 4)	/* Motorola SPI SSPSCLK phase setting */
++#define SSCR1_MWDS	(1 << 5)	/* Microwire Transmit Data Size */
++#define SSCR1_TFT	(0x000003c0)	/* Transmit FIFO Threshold (mask) */
++#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
++#define SSCR1_RFT	(0x00003c00)	/* Receive FIFO Threshold (mask) */
++#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
++
++#define SSSR_TNF	(1 << 2)	/* Transmit FIFO Not Full */
++#define SSSR_RNE	(1 << 3)	/* Receive FIFO Not Empty */
++#define SSSR_BSY	(1 << 4)	/* SSP Busy */
++#define SSSR_TFS	(1 << 5)	/* Transmit FIFO Service Request */
++#define SSSR_RFS	(1 << 6)	/* Receive FIFO Service Request */
++#define SSSR_ROR	(1 << 7)	/* Receive FIFO Overrun */
++
++#define SSCR0_TIM		(1 << 23)	/* Transmit FIFO Under Run Interrupt Mask */
++#define SSCR0_RIM		(1 << 22)	/* Receive FIFO Over Run interrupt Mask */
++#define SSCR0_NCS		(1 << 21)	/* Network Clock Select */
++#define SSCR0_EDSS		(1 << 20)	/* Extended Data Size Select */
++
++/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
++#define SSCR0_TISSP		(1 << 4)	/* TI Sync Serial Protocol */
++#define SSCR0_PSP		(3 << 4)	/* PSP - Programmable Serial Protocol */
++#define SSCR1_TTELP		(1 << 31)	/* TXD Tristate Enable Last Phase */
++#define SSCR1_TTE		(1 << 30)	/* TXD Tristate Enable */
++#define SSCR1_EBCEI		(1 << 29)	/* Enable Bit Count Error interrupt */
++#define SSCR1_SCFR		(1 << 28)	/* Slave Clock free Running */
++#define SSCR1_ECRA		(1 << 27)	/* Enable Clock Request A */
++#define SSCR1_ECRB		(1 << 26)	/* Enable Clock request B */
++#define SSCR1_SCLKDIR		(1 << 25)	/* Serial Bit Rate Clock Direction */
++#define SSCR1_SFRMDIR		(1 << 24)	/* Frame Direction */
++#define SSCR1_RWOT		(1 << 23)	/* Receive Without Transmit */
++#define SSCR1_TRAIL		(1 << 22)	/* Trailing Byte */
++#define SSCR1_TSRE		(1 << 21)	/* Transmit Service Request Enable */
++#define SSCR1_RSRE		(1 << 20)	/* Receive Service Request Enable */
++#define SSCR1_TINTE		(1 << 19)	/* Receiver Time-out Interrupt enable */
++#define SSCR1_PINTE		(1 << 18)	/* Peripheral Trailing Byte Interupt Enable */
++#define SSCR1_IFS		(1 << 16)	/* Invert Frame Signal */
++#define SSCR1_STRF		(1 << 15)	/* Select FIFO or EFWR */
++#define SSCR1_EFWR		(1 << 14)	/* Enable FIFO Write/Read */
++
++#define SSSR_BCE		(1 << 23)	/* Bit Count Error */
++#define SSSR_CSS		(1 << 22)	/* Clock Synchronisation Status */
++#define SSSR_TUR		(1 << 21)	/* Transmit FIFO Under Run */
++#define SSSR_EOC		(1 << 20)	/* End Of Chain */
++#define SSSR_TINT		(1 << 19)	/* Receiver Time-out Interrupt */
++#define SSSR_PINT		(1 << 18)	/* Peripheral Trailing Byte Interrupt */
++
++#define SSPSP_FSRT		(1 << 25)	/* Frame Sync Relative Timing */
++#define SSPSP_DMYSTOP(x)	((x) << 23)	/* Dummy Stop */
++#define SSPSP_SFRMWDTH(x)	((x) << 16)	/* Serial Frame Width */
++#define SSPSP_SFRMDLY(x)	((x) << 9)	/* Serial Frame Delay */
++#define SSPSP_DMYSTRT(x)	((x) << 7)	/* Dummy Start */
++#define SSPSP_STRTDLY(x)	((x) << 4)	/* Start Delay */
++#define SSPSP_ETDS		(1 << 3)	/* End of Transfer data State */
++#define SSPSP_SFRMP		(1 << 2)	/* Serial Frame Polarity */
++#define SSPSP_SCMODE(x)		((x) << 0)	/* Serial Bit Rate Clock Mode */
++
++#define SSACD_SCDB		(1 << 3)	/* SSPSYSCLK Divider Bypass */
++#define SSACD_ACPS(x)		((x) << 4)	/* Audio clock PLL select */
++#define SSACD_ACDS(x)		((x) << 0)	/* Audio clock divider select */
++
++#endif /* __ASM_ARCH_REGS_SSP_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/sharpsl.h linux-2.6.25-rc4/include/asm-arm/arch/sharpsl.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/sharpsl.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/sharpsl.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,34 @@
++/*
++ * SharpSL SSP Driver
++ */
++
++unsigned long corgi_ssp_ads7846_putget(unsigned long);
++unsigned long corgi_ssp_ads7846_get(void);
++void corgi_ssp_ads7846_put(unsigned long data);
++void corgi_ssp_ads7846_lock(void);
++void corgi_ssp_ads7846_unlock(void);
++void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data);
++void corgi_ssp_blduty_set(int duty);
++int corgi_ssp_max1111_get(unsigned long data);
++
++/*
++ * SharpSL Touchscreen Driver
++ */
++
++struct corgits_machinfo {
++	unsigned long (*get_hsync_invperiod)(void);
++	void (*put_hsync)(void);
++	void (*wait_hsync)(void);
++};
++
++
++/*
++ * SharpSL Backlight
++ */
++extern void corgibl_limit_intensity(int limit);
++
++
++/*
++ * SharpSL Battery/PM Driver
++ */
++extern void sharpsl_battery_kick(void);
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/spitz.h linux-2.6.25-rc4/include/asm-arm/arch/spitz.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/spitz.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/spitz.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,158 @@
++/*
++ * Hardware specific definitions for SL-Cx000 series of PDAs
++ *
++ * Copyright (c) 2005 Alexander Wykes
++ * Copyright (c) 2005 Richard Purdie
++ *
++ * Based on Sharp's 2.4 kernel patches
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#ifndef __ASM_ARCH_SPITZ_H
++#define __ASM_ARCH_SPITZ_H  1
++#endif
++
++#include <linux/fb.h>
++
++/* Spitz/Akita GPIOs */
++
++#define SPITZ_GPIO_KEY_INT         (0) /* Key Interrupt */
++#define SPITZ_GPIO_RESET           (1)
++#define SPITZ_GPIO_nSD_DETECT      (9)
++#define SPITZ_GPIO_TP_INT          (11) /* Touch Panel interrupt */
++#define SPITZ_GPIO_AK_INT          (13) /* Remote Control */
++#define SPITZ_GPIO_ADS7846_CS      (14)
++#define SPITZ_GPIO_SYNC            (16)
++#define SPITZ_GPIO_MAX1111_CS      (20)
++#define SPITZ_GPIO_FATAL_BAT       (21)
++#define SPITZ_GPIO_HSYNC           (22)
++#define SPITZ_GPIO_nSD_CLK         (32)
++#define SPITZ_GPIO_USB_DEVICE      (35)
++#define SPITZ_GPIO_USB_HOST        (37)
++#define SPITZ_GPIO_USB_CONNECT     (41)
++#define SPITZ_GPIO_LCDCON_CS       (53)
++#define SPITZ_GPIO_nPCE            (54)
++#define SPITZ_GPIO_nSD_WP          (81)
++#define SPITZ_GPIO_ON_RESET        (89)
++#define SPITZ_GPIO_BAT_COVER       (90)
++#define SPITZ_GPIO_CF_CD           (94)
++#define SPITZ_GPIO_ON_KEY          (95)
++#define SPITZ_GPIO_SWA             (97)
++#define SPITZ_GPIO_SWB             (96)
++#define SPITZ_GPIO_CHRG_FULL       (101)
++#define SPITZ_GPIO_CO              (101)
++#define SPITZ_GPIO_CF_IRQ          (105)
++#define SPITZ_GPIO_AC_IN           (115)
++#define SPITZ_GPIO_HP_IN           (116)
++
++/* Spitz Only GPIOs */
++
++#define SPITZ_GPIO_CF2_IRQ         (106) /* CF slot1 Ready */
++#define SPITZ_GPIO_CF2_CD          (93)
++
++
++/* Spitz/Akita Keyboard Definitions */
++
++#define SPITZ_KEY_STROBE_NUM         (11)
++#define SPITZ_KEY_SENSE_NUM          (7)
++#define SPITZ_GPIO_G0_STROBE_BIT     0x0f800000
++#define SPITZ_GPIO_G1_STROBE_BIT     0x00100000
++#define SPITZ_GPIO_G2_STROBE_BIT     0x01000000
++#define SPITZ_GPIO_G3_STROBE_BIT     0x00041880
++#define SPITZ_GPIO_G0_SENSE_BIT      0x00021000
++#define SPITZ_GPIO_G1_SENSE_BIT      0x000000d4
++#define SPITZ_GPIO_G2_SENSE_BIT      0x08000000
++#define SPITZ_GPIO_G3_SENSE_BIT      0x00000000
++
++#define SPITZ_GPIO_KEY_STROBE0       88
++#define SPITZ_GPIO_KEY_STROBE1       23
++#define SPITZ_GPIO_KEY_STROBE2       24
++#define SPITZ_GPIO_KEY_STROBE3       25
++#define SPITZ_GPIO_KEY_STROBE4       26
++#define SPITZ_GPIO_KEY_STROBE5       27
++#define SPITZ_GPIO_KEY_STROBE6       52
++#define SPITZ_GPIO_KEY_STROBE7       103
++#define SPITZ_GPIO_KEY_STROBE8       107
++#define SPITZ_GPIO_KEY_STROBE9       108
++#define SPITZ_GPIO_KEY_STROBE10      114
++
++#define SPITZ_GPIO_KEY_SENSE0        12
++#define SPITZ_GPIO_KEY_SENSE1        17
++#define SPITZ_GPIO_KEY_SENSE2        91
++#define SPITZ_GPIO_KEY_SENSE3        34
++#define SPITZ_GPIO_KEY_SENSE4        36
++#define SPITZ_GPIO_KEY_SENSE5        38
++#define SPITZ_GPIO_KEY_SENSE6        39
++
++
++/* Spitz Scoop Device (No. 1) GPIOs */
++/* Suspend States in comments */
++#define SPITZ_SCP_LED_GREEN     SCOOP_GPCR_PA11  /* Keep */
++#define SPITZ_SCP_JK_B          SCOOP_GPCR_PA12  /* Keep */
++#define SPITZ_SCP_CHRG_ON       SCOOP_GPCR_PA13  /* Keep */
++#define SPITZ_SCP_MUTE_L        SCOOP_GPCR_PA14  /* Low */
++#define SPITZ_SCP_MUTE_R        SCOOP_GPCR_PA15  /* Low */
++#define SPITZ_SCP_CF_POWER      SCOOP_GPCR_PA16  /* Keep */
++#define SPITZ_SCP_LED_ORANGE    SCOOP_GPCR_PA17  /* Keep */
++#define SPITZ_SCP_JK_A          SCOOP_GPCR_PA18  /* Low */
++#define SPITZ_SCP_ADC_TEMP_ON   SCOOP_GPCR_PA19  /* Low */
++
++#define SPITZ_SCP_IO_DIR      (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
++                               SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \
++                               SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
++#define SPITZ_SCP_IO_OUT      (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
++#define SPITZ_SCP_SUS_CLR     (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
++#define SPITZ_SCP_SUS_SET     0
++
++/* Spitz Scoop Device (No. 2) GPIOs */
++/* Suspend States in comments */
++#define SPITZ_SCP2_IR_ON           SCOOP_GPCR_PA11  /* High */
++#define SPITZ_SCP2_AKIN_PULLUP     SCOOP_GPCR_PA12  /* Keep */
++#define SPITZ_SCP2_RESERVED_1      SCOOP_GPCR_PA13  /* High */
++#define SPITZ_SCP2_RESERVED_2      SCOOP_GPCR_PA14  /* Low */
++#define SPITZ_SCP2_RESERVED_3      SCOOP_GPCR_PA15  /* Low */
++#define SPITZ_SCP2_RESERVED_4      SCOOP_GPCR_PA16  /* Low */
++#define SPITZ_SCP2_BACKLIGHT_CONT  SCOOP_GPCR_PA17  /* Low */
++#define SPITZ_SCP2_BACKLIGHT_ON    SCOOP_GPCR_PA18  /* Low */
++#define SPITZ_SCP2_MIC_BIAS        SCOOP_GPCR_PA19  /* Low */
++
++#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
++                           SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
++                           SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
++
++#define SPITZ_SCP2_IO_OUT   (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
++#define SPITZ_SCP2_SUS_CLR  (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
++                             SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
++#define SPITZ_SCP2_SUS_SET  (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
++
++
++/* Spitz IRQ Definitions */
++
++#define SPITZ_IRQ_GPIO_KEY_INT        IRQ_GPIO(SPITZ_GPIO_KEY_INT)
++#define SPITZ_IRQ_GPIO_AC_IN          IRQ_GPIO(SPITZ_GPIO_AC_IN)
++#define SPITZ_IRQ_GPIO_AK_INT         IRQ_GPIO(SPITZ_GPIO_AK_INT)
++#define SPITZ_IRQ_GPIO_HP_IN          IRQ_GPIO(SPITZ_GPIO_HP_IN)
++#define SPITZ_IRQ_GPIO_TP_INT         IRQ_GPIO(SPITZ_GPIO_TP_INT)
++#define SPITZ_IRQ_GPIO_SYNC           IRQ_GPIO(SPITZ_GPIO_SYNC)
++#define SPITZ_IRQ_GPIO_ON_KEY         IRQ_GPIO(SPITZ_GPIO_ON_KEY)
++#define SPITZ_IRQ_GPIO_SWA            IRQ_GPIO(SPITZ_GPIO_SWA)
++#define SPITZ_IRQ_GPIO_SWB            IRQ_GPIO(SPITZ_GPIO_SWB)
++#define SPITZ_IRQ_GPIO_BAT_COVER      IRQ_GPIO(SPITZ_GPIO_BAT_COVER)
++#define SPITZ_IRQ_GPIO_FATAL_BAT      IRQ_GPIO(SPITZ_GPIO_FATAL_BAT)
++#define SPITZ_IRQ_GPIO_CO             IRQ_GPIO(SPITZ_GPIO_CO)
++#define SPITZ_IRQ_GPIO_CF_IRQ         IRQ_GPIO(SPITZ_GPIO_CF_IRQ)
++#define SPITZ_IRQ_GPIO_CF_CD          IRQ_GPIO(SPITZ_GPIO_CF_CD)
++#define SPITZ_IRQ_GPIO_CF2_IRQ        IRQ_GPIO(SPITZ_GPIO_CF2_IRQ)
++#define SPITZ_IRQ_GPIO_nSD_INT        IRQ_GPIO(SPITZ_GPIO_nSD_INT)
++#define SPITZ_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(SPITZ_GPIO_nSD_DETECT)
++
++/*
++ * Shared data structures
++ */
++extern struct platform_device spitzscoop_device;
++extern struct platform_device spitzscoop2_device;
++extern struct platform_device spitzssp_device;
++extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/ssp.h linux-2.6.25-rc4/include/asm-arm/arch/ssp.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/ssp.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/ssp.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,83 @@
++/*
++ *  ssp.h
++ *
++ *  Copyright (C) 2003 Russell King, All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This driver supports the following PXA CPU/SSP ports:-
++ *
++ *       PXA250     SSP
++ *       PXA255     SSP, NSSP
++ *       PXA26x     SSP, NSSP, ASSP
++ *       PXA27x     SSP1, SSP2, SSP3
++ *       PXA3xx     SSP1, SSP2, SSP3, SSP4
++ */
++
++#ifndef __ASM_ARCH_SSP_H
++#define __ASM_ARCH_SSP_H
++
++#include <linux/list.h>
++
++enum pxa_ssp_type {
++	SSP_UNDEFINED = 0,
++	PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
++	PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
++	PXA27x_SSP,
++};
++
++struct ssp_device {
++	struct platform_device *pdev;
++	struct list_head	node;
++
++	struct clk	*clk;
++	void __iomem	*mmio_base;
++	unsigned long	phys_base;
++
++	const char	*label;
++	int		port_id;
++	int		type;
++	int		use_count;
++	int		irq;
++	int		drcmr_rx;
++	int		drcmr_tx;
++};
++
++/*
++ * SSP initialisation flags
++ */
++#define SSP_NO_IRQ	0x1		/* don't register an irq handler in SSP driver */
++
++struct ssp_state {
++	u32	cr0;
++	u32 cr1;
++	u32 to;
++	u32 psp;
++};
++
++struct ssp_dev {
++	struct ssp_device *ssp;
++	u32 port;
++	u32 mode;
++	u32 flags;
++	u32 psp_flags;
++	u32 speed;
++	int irq;
++};
++
++int ssp_write_word(struct ssp_dev *dev, u32 data);
++int ssp_read_word(struct ssp_dev *dev, u32 *data);
++int ssp_flush(struct ssp_dev *dev);
++void ssp_enable(struct ssp_dev *dev);
++void ssp_disable(struct ssp_dev *dev);
++void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
++void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
++int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
++int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
++void ssp_exit(struct ssp_dev *dev);
++
++struct ssp_device *ssp_request(int port, const char *label);
++void ssp_free(struct ssp_device *);
++#endif /* __ASM_ARCH_SSP_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/system.h linux-2.6.25-rc4/include/asm-arm/arch/system.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/system.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/system.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,35 @@
++/*
++ * linux/include/asm-arm/arch-pxa/system.h
++ *
++ * Author:	Nicolas Pitre
++ * Created:	Jun 15, 2001
++ * Copyright:	MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <asm/proc-fns.h>
++#include "hardware.h"
++#include "pxa-regs.h"
++
++static inline void arch_idle(void)
++{
++	cpu_do_idle();
++}
++
++
++static inline void arch_reset(char mode)
++{
++	if (mode == 's') {
++		/* Jump into ROM at address 0 */
++		cpu_reset(0);
++	} else {
++		/* Initialize the watchdog and let it fire */
++		OWER = OWER_WME;
++		OSSR = OSSR_M3;
++		OSMR3 = OSCR + 368640;	/* ... in 100 ms */
++	}
++}
++
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/timex.h linux-2.6.25-rc4/include/asm-arm/arch/timex.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/timex.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/timex.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,26 @@
++/*
++ * linux/include/asm-arm/arch-pxa/timex.h
++ *
++ * Author:	Nicolas Pitre
++ * Created:	Jun 15, 2001
++ * Copyright:	MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++#if defined(CONFIG_PXA25x)
++/* PXA250/210 timer base */
++#define CLOCK_TICK_RATE 3686400
++#elif defined(CONFIG_PXA27x)
++/* PXA27x timer base */
++#ifdef CONFIG_MACH_MAINSTONE
++#define CLOCK_TICK_RATE 3249600
++#else
++#define CLOCK_TICK_RATE 3250000
++#endif
++#else
++#define CLOCK_TICK_RATE 3250000
++#endif
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/tosa.h linux-2.6.25-rc4/include/asm-arm/arch/tosa.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/tosa.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/tosa.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,196 @@
++/*
++ * Hardware specific definitions for Sharp SL-C6000x series of PDAs
++ *
++ * Copyright (c) 2005 Dirk Opfer
++ *
++ * Based on Sharp's 2.4 kernel patches
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#ifndef _ASM_ARCH_TOSA_H_
++#define _ASM_ARCH_TOSA_H_ 1
++
++/*  TOSA Chip selects  */
++#define TOSA_LCDC_PHYS		PXA_CS4_PHYS
++/* Internel Scoop */
++#define TOSA_CF_PHYS		(PXA_CS2_PHYS + 0x00800000)
++/* Jacket Scoop */
++#define TOSA_SCOOP_PHYS  	(PXA_CS5_PHYS + 0x00800000)
++
++/*
++ * SCOOP2 internal GPIOs
++ */
++#define TOSA_SCOOP_PXA_VCORE1		SCOOP_GPCR_PA11
++#define TOSA_SCOOP_TC6393_REST_IN	SCOOP_GPCR_PA12
++#define TOSA_SCOOP_IR_POWERDWN		SCOOP_GPCR_PA13
++#define TOSA_SCOOP_SD_WP		SCOOP_GPCR_PA14
++#define TOSA_SCOOP_PWR_ON		SCOOP_GPCR_PA15
++#define TOSA_SCOOP_AUD_PWR_ON		SCOOP_GPCR_PA16
++#define TOSA_SCOOP_BT_RESET		SCOOP_GPCR_PA17
++#define TOSA_SCOOP_BT_PWR_EN		SCOOP_GPCR_PA18
++#define TOSA_SCOOP_AC_IN_OL		SCOOP_GPCR_PA19
++
++/* GPIO Direction   1 : output mode / 0:input mode */
++#define TOSA_SCOOP_IO_DIR     ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \
++		TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\
++		TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
++/* GPIO out put level when init   1: Hi */
++#define TOSA_SCOOP_IO_OUT     ( TOSA_SCOOP_TC6393_REST_IN )
++
++/*
++ * SCOOP2 jacket GPIOs
++ */
++#define TOSA_SCOOP_JC_BT_LED		SCOOP_GPCR_PA11
++#define TOSA_SCOOP_JC_NOTE_LED		SCOOP_GPCR_PA12
++#define TOSA_SCOOP_JC_CHRG_ERR_LED	SCOOP_GPCR_PA13
++#define TOSA_SCOOP_JC_USB_PULLUP	SCOOP_GPCR_PA14
++#define TOSA_SCOOP_JC_TC6393_SUSPEND	SCOOP_GPCR_PA15
++#define TOSA_SCOOP_JC_TC3693_L3V_ON	SCOOP_GPCR_PA16
++#define TOSA_SCOOP_JC_WLAN_DETECT	SCOOP_GPCR_PA17
++#define TOSA_SCOOP_JC_WLAN_LED		SCOOP_GPCR_PA18
++#define TOSA_SCOOP_JC_CARD_LIMIT_SEL	SCOOP_GPCR_PA19
++
++/* GPIO Direction   1 : output mode / 0:input mode */
++#define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \
++		TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \
++		TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \
++		TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL )
++/* GPIO out put level when init   1: Hi */
++#define TOSA_SCOOP_JC_IO_OUT ( 0 )
++
++/*
++ * Timing Generator
++ */
++#define TG_PNLCTL 			0x00
++#define TG_TPOSCTL 			0x01
++#define TG_DUTYCTL 			0x02
++#define TG_GPOSR 			0x03
++#define TG_GPODR1 			0x04
++#define TG_GPODR2 			0x05
++#define TG_PINICTL 			0x06
++#define TG_HPOSCTL 			0x07
++
++/*
++ * LED
++ */
++#define TOSA_SCOOP_LED_BLUE   		TOSA_SCOOP_GPCR_PA11
++#define TOSA_SCOOP_LED_GREEN  		TOSA_SCOOP_GPCR_PA12
++#define TOSA_SCOOP_LED_ORANGE		TOSA_SCOOP_GPCR_PA13
++#define TOSA_SCOOP_LED_WLAN		TOSA_SCOOP_GPCR_PA18
++
++
++/*
++ * PXA GPIOs
++ */
++#define TOSA_GPIO_POWERON		(0)
++#define TOSA_GPIO_RESET			(1)
++#define TOSA_GPIO_AC_IN			(2)
++#define TOSA_GPIO_RECORD_BTN		(3)
++#define TOSA_GPIO_SYNC			(4)	/* Cradle SYNC Button */
++#define TOSA_GPIO_USB_IN		(5)
++#define TOSA_GPIO_JACKET_DETECT		(7)
++#define TOSA_GPIO_nSD_DETECT		(9)
++#define TOSA_GPIO_nSD_INT		(10)
++#define TOSA_GPIO_TC6393_CLK		(11)
++#define TOSA_GPIO_BAT1_CRG		(12)
++#define TOSA_GPIO_CF_CD			(13)
++#define TOSA_GPIO_BAT0_CRG		(14)
++#define TOSA_GPIO_TC6393_INT		(15)
++#define TOSA_GPIO_BAT0_LOW		(17)
++#define TOSA_GPIO_TC6393_RDY		(18)
++#define TOSA_GPIO_ON_RESET		(19)
++#define TOSA_GPIO_EAR_IN		(20)
++#define TOSA_GPIO_CF_IRQ		(21)	/* CF slot0 Ready */
++#define TOSA_GPIO_ON_KEY		(22)
++#define TOSA_GPIO_VGA_LINE		(27)
++#define TOSA_GPIO_TP_INT		(32)	/* Touch Panel pen down interrupt */
++#define TOSA_GPIO_JC_CF_IRQ		(36)	/* CF slot1 Ready */
++#define TOSA_GPIO_BAT_LOCKED		(38)	/* Battery locked */
++#define TOSA_GPIO_TG_SPI_SCLK		(81)
++#define TOSA_GPIO_TG_SPI_CS		(82)
++#define TOSA_GPIO_TG_SPI_MOSI		(83)
++#define TOSA_GPIO_BAT1_LOW		(84)
++
++#define TOSA_GPIO_HP_IN			GPIO_EAR_IN
++
++#define TOSA_GPIO_MAIN_BAT_LOW		GPIO_BAT0_LOW
++
++#define TOSA_KEY_STROBE_NUM		(11)
++#define TOSA_KEY_SENSE_NUM		(7)
++
++#define TOSA_GPIO_HIGH_STROBE_BIT	(0xfc000000)
++#define TOSA_GPIO_LOW_STROBE_BIT	(0x0000001f)
++#define TOSA_GPIO_ALL_SENSE_BIT		(0x00000fe0)
++#define TOSA_GPIO_ALL_SENSE_RSHIFT	(5)
++#define TOSA_GPIO_STROBE_BIT(a)		GPIO_bit(58+(a))
++#define TOSA_GPIO_SENSE_BIT(a)		GPIO_bit(69+(a))
++#define TOSA_GAFR_HIGH_STROBE_BIT	(0xfff00000)
++#define TOSA_GAFR_LOW_STROBE_BIT	(0x000003ff)
++#define TOSA_GAFR_ALL_SENSE_BIT		(0x00fffc00)
++#define TOSA_GPIO_KEY_SENSE(a) 		(69+(a))
++#define TOSA_GPIO_KEY_STROBE(a)		(58+(a))
++
++/*
++ * Interrupts
++ */
++#define TOSA_IRQ_GPIO_WAKEUP        	IRQ_GPIO(TOSA_GPIO_WAKEUP)
++#define TOSA_IRQ_GPIO_AC_IN         	IRQ_GPIO(TOSA_GPIO_AC_IN)
++#define TOSA_IRQ_GPIO_RECORD_BTN    	IRQ_GPIO(TOSA_GPIO_RECORD_BTN)
++#define TOSA_IRQ_GPIO_SYNC          	IRQ_GPIO(TOSA_GPIO_SYNC)
++#define TOSA_IRQ_GPIO_USB_IN        	IRQ_GPIO(TOSA_GPIO_USB_IN)
++#define TOSA_IRQ_GPIO_JACKET_DETECT 	IRQ_GPIO(TOSA_GPIO_JACKET_DETECT)
++#define TOSA_IRQ_GPIO_nSD_INT       	IRQ_GPIO(TOSA_GPIO_nSD_INT)
++#define TOSA_IRQ_GPIO_nSD_DETECT    	IRQ_GPIO(TOSA_GPIO_nSD_DETECT)
++#define TOSA_IRQ_GPIO_BAT1_CRG      	IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
++#define TOSA_IRQ_GPIO_CF_CD         	IRQ_GPIO(TOSA_GPIO_CF_CD)
++#define TOSA_IRQ_GPIO_BAT0_CRG      	IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
++#define TOSA_IRQ_GPIO_TC6393_INT    	IRQ_GPIO(TOSA_GPIO_TC6393_INT)
++#define TOSA_IRQ_GPIO_BAT0_LOW      	IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
++#define TOSA_IRQ_GPIO_EAR_IN        	IRQ_GPIO(TOSA_GPIO_EAR_IN)
++#define TOSA_IRQ_GPIO_CF_IRQ        	IRQ_GPIO(TOSA_GPIO_CF_IRQ)
++#define TOSA_IRQ_GPIO_ON_KEY        	IRQ_GPIO(TOSA_GPIO_ON_KEY)
++#define TOSA_IRQ_GPIO_VGA_LINE      	IRQ_GPIO(TOSA_GPIO_VGA_LINE)
++#define TOSA_IRQ_GPIO_TP_INT        	IRQ_GPIO(TOSA_GPIO_TP_INT)
++#define TOSA_IRQ_GPIO_JC_CF_IRQ     	IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ)
++#define TOSA_IRQ_GPIO_BAT_LOCKED    	IRQ_GPIO(TOSA_GPIO_BAT_LOCKED)
++#define TOSA_IRQ_GPIO_BAT1_LOW      	IRQ_GPIO(TOSA_GPIO_BAT1_LOW)
++#define TOSA_IRQ_GPIO_KEY_SENSE(a)  	IRQ_GPIO(69+(a))
++
++#define TOSA_IRQ_GPIO_MAIN_BAT_LOW 	IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
++
++extern struct platform_device tosascoop_jc_device;
++extern struct platform_device tosascoop_device;
++
++#define TOSA_KEY_SYNC		KEY_102ND /* ??? */
++
++
++#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES
++#define TOSA_KEY_RECORD		KEY_YEN
++#define TOSA_KEY_ADDRESSBOOK	KEY_KATAKANA
++#define TOSA_KEY_CANCEL		KEY_ESC
++#define TOSA_KEY_CENTER		KEY_HIRAGANA
++#define TOSA_KEY_OK		KEY_HENKAN
++#define TOSA_KEY_CALENDAR	KEY_KATAKANAHIRAGANA
++#define TOSA_KEY_HOMEPAGE	KEY_HANGEUL
++#define TOSA_KEY_LIGHT		KEY_MUHENKAN
++#define TOSA_KEY_MENU		KEY_HANJA
++#define TOSA_KEY_FN		KEY_RIGHTALT
++#define TOSA_KEY_MAIL		KEY_ZENKAKUHANKAKU
++#else
++#define TOSA_KEY_RECORD		KEY_RECORD
++#define TOSA_KEY_ADDRESSBOOK	KEY_ADDRESSBOOK
++#define TOSA_KEY_CANCEL		KEY_CANCEL
++#define TOSA_KEY_CENTER		KEY_SELECT /* ??? */
++#define TOSA_KEY_OK		KEY_OK
++#define TOSA_KEY_CALENDAR	KEY_CALENDAR
++#define TOSA_KEY_HOMEPAGE	KEY_HOMEPAGE
++#define TOSA_KEY_LIGHT		KEY_KBDILLUMTOGGLE
++#define TOSA_KEY_MENU		KEY_MENU
++#define TOSA_KEY_FN		KEY_FN
++#define TOSA_KEY_MAIL		KEY_MAIL
++#endif
++
++#endif /* _ASM_ARCH_TOSA_H_ */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/trizeps4.h linux-2.6.25-rc4/include/asm-arm/arch/trizeps4.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/trizeps4.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/trizeps4.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,106 @@
++/************************************************************************
++ * Include file for TRIZEPS4 SoM and ConXS eval-board
++ * Copyright (c) Jürgen Schindele
++ * 2006
++ ************************************************************************/
++
++/*
++ * Includes/Defines
++ */
++#ifndef _TRIPEPS4_H_
++#define _TRIPEPS4_H_
++
++/* physical memory regions */
++#define TRIZEPS4_FLASH_PHYS	(PXA_CS0_PHYS)  /* Flash region */
++#define TRIZEPS4_DISK_PHYS	(PXA_CS1_PHYS)  /* Disk On Chip region */
++#define TRIZEPS4_ETH_PHYS	(PXA_CS2_PHYS)  /* Ethernet DM9000 region */
++#define TRIZEPS4_PIC_PHYS	(PXA_CS3_PHYS)	/* Logic chip on ConXS-Board */
++#define TRIZEPS4_SDRAM_BASE	0xa0000000      /* SDRAM region */
++
++#define TRIZEPS4_CFSR_PHYS	(PXA_CS3_PHYS)			/* Logic chip on ConXS-Board CSFR register */
++#define TRIZEPS4_BOCR_PHYS	(PXA_CS3_PHYS+0x02000000)	/* Logic chip on ConXS-Board BOCR register */
++#define TRIZEPS4_IRCR_PHYS	(PXA_CS3_PHYS+0x02400000)	/* Logic chip on ConXS-Board IRCR register*/
++#define TRIZEPS4_UPSR_PHYS	(PXA_CS3_PHYS+0x02800000)	/* Logic chip on ConXS-Board UPSR register*/
++#define TRIZEPS4_DICR_PHYS	(PXA_CS3_PHYS+0x03800000)	/* Logic chip on ConXS-Board DICR register*/
++
++/* virtual memory regions */
++#define TRIZEPS4_DISK_VIRT	0xF0000000	/* Disk On Chip region */
++
++#define TRIZEPS4_PIC_VIRT	0xF0100000	/* not used */
++#define TRIZEPS4_CFSR_VIRT	0xF0100000
++#define TRIZEPS4_BOCR_VIRT	0xF0200000
++#define TRIZEPS4_DICR_VIRT	0xF0300000
++#define TRIZEPS4_IRCR_VIRT	0xF0400000
++#define TRIZEPS4_UPSR_VIRT	0xF0500000
++
++/* size of flash */
++#define TRIZEPS4_FLASH_SIZE	0x02000000	/* Flash size 32 MB */
++
++/* Ethernet Controller Davicom DM9000 */
++#define GPIO_DM9000		101
++#define TRIZEPS4_ETH_IRQ	IRQ_GPIO(GPIO_DM9000)
++
++/* UCB1400 audio / TS-controller */
++#define GPIO_UCB1400		1
++#define TRIZEPS4_UCB1400_IRQ	IRQ_GPIO(GPIO_UCB1400)
++
++/* PCMCIA socket Compact Flash */
++#define GPIO_PCD		11		/* PCMCIA Card Detect */
++#define TRIZEPS4_CD_IRQ		IRQ_GPIO(GPIO_PCD)
++#define GPIO_PRDY		13		/* READY / nINT */
++#define TRIZEPS4_READY_NINT	IRQ_GPIO(GPIO_PRDY)
++
++/* MMC socket */
++#define GPIO_MMC_DET		12
++#define TRIZEPS4_MMC_IRQ	IRQ_GPIO(GPIO_MMC_DET)
++
++/* LEDS using tx2 / rx2 */
++#define GPIO_SYS_BUSY_LED	46
++#define GPIO_HEARTBEAT_LED	47
++
++/* Off-module PIC on ConXS board */
++#define GPIO_PIC		0
++#define TRIZEPS4_PIC_IRQ	IRQ_GPIO(GPIO_PIC)
++
++#define CFSR_P2V(x)		((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
++#define CFSR_V2P(x)		((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
++
++#define BCR_P2V(x)		((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
++#define BCR_V2P(x)		((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
++
++#define DCR_P2V(x)		((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
++#define DCR_V2P(x)		((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
++
++#ifndef __ASSEMBLY__
++#define ConXS_CFSR		(*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
++#define ConXS_BCR		(*((volatile unsigned short *)BCR_P2V(0x0E000000)))
++#define ConXS_DCR		(*((volatile unsigned short *)DCR_P2V(0x0F800000)))
++#else
++#define ConXS_CFSR		CFSR_P2V(0x0C000000)
++#define ConXS_BCR		BCR_P2V(0x0E000000)
++#define ConXS_DCR		DCR_P2V(0x0F800000)
++#endif
++
++#define ConXS_CFSR_BVD_MASK	0x0003
++#define ConXS_CFSR_BVD1		(1 << 0)
++#define ConXS_CFSR_BVD2		(1 << 1)
++#define ConXS_CFSR_VS_MASK	0x000C
++#define ConXS_CFSR_VS1		(1 << 2)
++#define ConXS_CFSR_VS2		(1 << 3)
++#define ConXS_CFSR_VS_5V	(0x3 << 2)
++#define ConXS_CFSR_VS_3V3	0x0
++
++#define ConXS_BCR_S0_POW_EN0	(1 << 0)
++#define ConXS_BCR_S0_POW_EN1	(1 << 1)
++#define ConXS_BCR_L_DISP	(1 << 4)
++#define ConXS_BCR_CF_BUF_EN	(1 << 5)
++#define ConXS_BCR_CF_RESET	(1 << 7)
++#define ConXS_BCR_S0_VCC_3V3	0x1
++#define ConXS_BCR_S0_VCC_5V0	0x2
++#define ConXS_BCR_S0_VPP_12V	0x4
++#define ConXS_BCR_S0_VPP_3V3	0x8
++
++#define ConXS_IRCR_MODE		(1 << 0)
++#define ConXS_IRCR_SD		(1 << 1)
++
++#endif /* _TRIPEPS4_H_ */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/udc.h linux-2.6.25-rc4/include/asm-arm/arch/udc.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/udc.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/udc.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,8 @@
++/*
++ * linux/include/asm-arm/arch-pxa/udc.h
++ *
++ */
++#include <asm/mach/udc_pxa2xx.h>
++
++extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
++
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/uncompress.h linux-2.6.25-rc4/include/asm-arm/arch/uncompress.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/uncompress.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/uncompress.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,40 @@
++/*
++ * linux/include/asm-arm/arch-pxa/uncompress.h
++ *
++ * Author:	Nicolas Pitre
++ * Copyright:	(C) 2001 MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/serial_reg.h>
++#include <asm/arch/pxa-regs.h>
++
++#define __REG(x)	((volatile unsigned long *)x)
++
++#define UART		FFUART
++
++
++static inline void putc(char c)
++{
++	if (!(UART[UART_IER] & IER_UUE))
++		return;
++	while (!(UART[UART_LSR] & LSR_TDRQ))
++		barrier();
++	UART[UART_TX] = c;
++}
++
++/*
++ * This does not append a newline
++ */
++static inline void flush(void)
++{
++}
++
++/*
++ * nothing to do
++ */
++#define arch_decomp_setup()
++#define arch_decomp_wdog()
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/vmalloc.h linux-2.6.25-rc4/include/asm-arm/arch/vmalloc.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/vmalloc.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/vmalloc.h	2008-02-26 01:20:20.000000000 +0100
+@@ -0,0 +1,11 @@
++/*
++ * linux/include/asm-arm/arch-pxa/vmalloc.h
++ *
++ * Author:	Nicolas Pitre
++ * Copyright:	(C) 2001 MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#define VMALLOC_END       (0xe8000000)
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/zylonite.h linux-2.6.25-rc4/include/asm-arm/arch/zylonite.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch/zylonite.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch/zylonite.h	2008-03-08 16:11:19.000000000 +0100
+@@ -0,0 +1,44 @@
++#ifndef __ASM_ARCH_ZYLONITE_H
++#define __ASM_ARCH_ZYLONITE_H
++
++#define ZYLONITE_ETH_PHYS	0x14000000
++
++#define EXT_GPIO(x)		(128 + (x))
++
++/* the following variables are processor specific and initialized
++ * by the corresponding zylonite_pxa3xx_init()
++ */
++struct platform_mmc_slot {
++	int gpio_cd;
++	int gpio_wp;
++};
++
++extern struct platform_mmc_slot zylonite_mmc_slot[];
++
++extern int gpio_backlight;
++extern int gpio_eth_irq;
++
++extern int lcd_id;
++extern int lcd_orientation;
++
++#ifdef CONFIG_CPU_PXA300
++extern void zylonite_pxa300_init(void);
++#else
++static inline void zylonite_pxa300_init(void)
++{
++	if (cpu_is_pxa300() || cpu_is_pxa310())
++		panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__);
++}
++#endif
++
++#ifdef CONFIG_CPU_PXA320
++extern void zylonite_pxa320_init(void);
++#else
++static inline void zylonite_pxa320_init(void)
++{
++	if (cpu_is_pxa320())
++		panic("%s: PXA320 not supported\n", __FUNCTION__);
++}
++#endif
++
++#endif /* __ASM_ARCH_ZYLONITE_H */
+diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch-pxa/pxa27x_keypad.h linux-2.6.25-rc4/include/asm-arm/arch-pxa/pxa27x_keypad.h
+--- linux-2.6.25-rc4-orig/include/asm-arm/arch-pxa/pxa27x_keypad.h	2008-03-08 18:26:06.000000000 +0100
++++ linux-2.6.25-rc4/include/asm-arm/arch-pxa/pxa27x_keypad.h	2008-03-08 16:22:35.000000000 +0100
+@@ -53,4 +53,6 @@
+ 
+ #define KEY(row, col, val)	(((row) << 28) | ((col) << 24) | (val))
+ 
++extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
++
+ #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
+
diff --git a/packages/linux/linux-mainstone/mainstone/.mtn2git_empty b/packages/linux/linux-mainstone/mainstone/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/linux/linux-mainstone/mainstone/.mtn2git_empty
diff --git a/packages/linux/linux-mainstone/mainstone/defconfig b/packages/linux/linux-mainstone/mainstone/defconfig
new file mode 100644
index 0000000000..cbea28d485
--- /dev/null
+++ b/packages/linux/linux-mainstone/mainstone/defconfig
@@ -0,0 +1,1608 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc4
+# Sat Mar  8 18:03:28 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+CONFIG_MACH_MAINSTONE=y
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+CONFIG_PXA27x=y
+CONFIG_PXA_SSP=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+CONFIG_PCMCIA_PXA2XX=m
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200 mem=64M console=ttyS0 debug "
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_PM_LEGACY=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+# CONFIG_IPV6_ROUTE_INFO is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+# CONFIG_IRLAN is not set
+# CONFIG_IRNET is not set
+# CONFIG_IRCOMM is not set
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_PXA_FICP is not set
+# CONFIG_MCS_FIR is not set
+CONFIG_BT=m
+# CONFIG_BT_L2CAP is not set
+# CONFIG_BT_SCO is not set
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIUSB is not set
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=m
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+# CONFIG_MTD_CFI_I1 is not set
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_IDE_MAX_HWIFS=4
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_PROC_FS is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_PCMCIA_RAYCS=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_CS is not set
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_HERMES=m
+CONFIG_PCMCIA_HERMES=m
+CONFIG_PCMCIA_SPECTRUM=m
+CONFIG_ATMEL=m
+CONFIG_PCMCIA_ATMEL=m
+CONFIG_AIRO_CS=m
+CONFIG_PCMCIA_WL3501=m
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_HOSTAP_CS=m
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_APMPOWER=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_UCB1400=y
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+CONFIG_CARDMAN_4000=m
+CONFIG_CARDMAN_4040=m
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_PXA=y
+CONFIG_I2C_PXA_SLAVE=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_PXA2XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+# CONFIG_DEBUG_GPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MCP23S08 is not set
+CONFIG_W1=y
+CONFIG_W1_CON=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2490 is not set
+# CONFIG_W1_MASTER_DS2482 is not set
+# CONFIG_W1_MASTER_DS1WM is not set
+# CONFIG_W1_MASTER_GPIO is not set
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+CONFIG_W1_SLAVE_DS2760=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+CONFIG_APM_POWER=y
+CONFIG_BATTERY_DS2760=y
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+CONFIG_SND_PXA2XX_PCM=y
+CONFIG_SND_PXA2XX_AC97=y
+
+#
+# SPI devices
+#
+
+#
+# USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+
+#
+# PCMCIA devices
+#
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# SoC Audio support for SuperH
+#
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+CONFIG_USB_GADGET_DUMMY_HCD=y
+CONFIG_USB_DUMMY_HCD=m
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=m
+# CONFIG_MMC_SPI is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=m
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_HMAC=m
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/packages/linux/linux-mainstone_2.6.25-rc4.bb b/packages/linux/linux-mainstone_2.6.25-rc4.bb
new file mode 100644
index 0000000000..fd5c30e37f
--- /dev/null
+++ b/packages/linux/linux-mainstone_2.6.25-rc4.bb
@@ -0,0 +1,25 @@
+require linux.inc 
+
+SECTION = "kernel"
+DESCRIPTION = "Linux kernel for the Mainstone (PXA270 ref design)"
+LICENSE = "GPL"
+PR = "r0"
+
+SRC_URI = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-2.6.24.tar.bz2 \
+           ${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/testing/patch-2.6.25-rc4.bz2;patch=1 \
+           file://mainstone-keypad.patch;patch=1 \
+           file://defconfig"
+
+S = "${WORKDIR}/linux-2.6.24"
+
+COMPATIBLE_HOST = 'arm.*-linux'
+
+ARCH = "arm"
+
+CMDLINE_CONSOLE ?= "ttyS0,115200n8"
+#CMDLINE_ROOT = "root=/dev/slug rootfstype=ext2,jffs2 initrd=0x01000000,10M mem=32M@0x00000000"
+#CMDLINE_ROOT = "root=/dev/ram0 rw rootfstype=ext2,jffs2 initrd=0x01000000,10M init=/linuxrc mem=32M@0x00000000"
+CMDLINE_ROOT = "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200 mem=64M"
+CMDLINE = "${CMDLINE_ROOT} ${CMDLINE_CONSOLE}"
+
+COMPATIBLE_MACHINE = "mainstone"
diff --git a/packages/linux/linux-rp-2.6.24/htcuni.patch b/packages/linux/linux-rp-2.6.24/htcuni.patch
index aa08ca4691..8448c4ec06 100644
--- a/packages/linux/linux-rp-2.6.24/htcuni.patch
+++ b/packages/linux/linux-rp-2.6.24/htcuni.patch
@@ -60,7 +60,7 @@
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/Makefile
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/Makefile	2008-02-24 02:40:56.640036018 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/Makefile	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,19 @@
 +#
 +# Makefile for HTC Universal
@@ -84,7 +84,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/Makefile
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal.c	2008-02-24 02:40:56.644036684 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,468 @@
 +/*
 + * Hardware definitions for HTC Universal
@@ -557,7 +557,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c	2008-02-24 02:40:56.644036684 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,917 @@
 +/*
 + * Audio support for codec Asahi Kasei AK4641
@@ -1479,7 +1479,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h	2008-02-24 02:40:56.644036684 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,65 @@
 +/*
 + * Audio support for codec Asahi Kasei AK4641
@@ -1549,7 +1549,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c	2008-02-24 02:40:56.644036684 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,143 @@
 +/*
 + * LEDs support for the HP iPaq hx4700
@@ -1697,7 +1697,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c	2008-02-24 02:40:56.644036684 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,61 @@
 +/*
 + * Use consistent with the GNU GPL is permitted,
@@ -1763,7 +1763,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c	2008-02-24 02:40:56.644036684 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,135 @@
 +/* Bluetooth interface driver for TI BRF6150 on HX4700
 + *
@@ -1903,7 +1903,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h	2008-02-24 02:40:56.644036684 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,17 @@
 +/*
 + * Bluetooth support file for calling bluetooth configuration functions
@@ -1925,7 +1925,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c	2008-02-24 02:40:56.644036684 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,87 @@
 +/*
 + * Buttons driver for HTC Universal
@@ -2017,7 +2017,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,226 @@
 +/* Core Hardware driver for Hx4700 (Serial, ASIC3, EGPIOs)
 + *
@@ -2248,7 +2248,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,212 @@
 +/*
 + * Use consistent with the GNU GPL is permitted,
@@ -2465,7 +2465,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,167 @@
 +
 +/* Phone interface driver for Qualcomm MSM6250 on HTC Universal
@@ -2637,7 +2637,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,16 @@
 +/*
 + * Bluetooth support file for calling bluetooth configuration functions
@@ -2658,7 +2658,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,69 @@
 +/*
 + * MyPal 716 power management support for the original HTC IPL in DoC G3
@@ -2732,7 +2732,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,97 @@
 +/*
 + * pda_power driver for HTC Universal
@@ -2834,7 +2834,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,490 @@
 +/* Touch screen driver for the TI something-or-other
 + *
@@ -3329,7 +3329,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,71 @@
 +
 +/*
@@ -3405,7 +3405,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c
 Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h	2008-02-24 02:40:56.648035744 +0300
++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,20 @@
 +/*
 + * temporary TSC2046 touchscreen hack
@@ -3429,9 +3429,9 @@ Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h
 +#endif
 Index: linux-2.6.24/arch/arm/mach-pxa/Kconfig
 ===================================================================
---- linux-2.6.24.orig/arch/arm/mach-pxa/Kconfig	2008-02-24 02:40:23.789035215 +0300
-+++ linux-2.6.24/arch/arm/mach-pxa/Kconfig	2008-02-24 02:40:56.652035294 +0300
-@@ -92,6 +92,14 @@ config PXA_SHARPSL_27x
+--- linux-2.6.24.orig/arch/arm/mach-pxa/Kconfig	2008-03-10 16:08:01.000000000 +0000
++++ linux-2.6.24/arch/arm/mach-pxa/Kconfig	2008-03-10 16:09:23.000000000 +0000
+@@ -92,6 +92,14 @@
  	bool "Sharp PXA270 models (SL-Cxx00)"
  	select PXA27x
  
@@ -3446,7 +3446,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/Kconfig
  endchoice
  
  endif
-@@ -111,6 +119,86 @@ endchoice
+@@ -111,6 +119,86 @@
  
  endif
  
@@ -3533,17 +3533,17 @@ Index: linux-2.6.24/arch/arm/mach-pxa/Kconfig
  endmenu
  
  config MACH_POODLE
-@@ -196,4 +284,3 @@ config PXA_KEYS
+@@ -196,4 +284,3 @@
  	depends on (PXA25x || PXA27x) && INPUT
  
  endif
 -
 Index: linux-2.6.24/arch/arm/mach-pxa/Makefile
 ===================================================================
---- linux-2.6.24.orig/arch/arm/mach-pxa/Makefile	2008-02-24 02:40:23.797034872 +0300
-+++ linux-2.6.24/arch/arm/mach-pxa/Makefile	2008-02-24 02:40:56.652035294 +0300
-@@ -23,6 +23,7 @@ obj-$(CONFIG_MACH_POODLE)	+= poodle.o co
- obj-$(CONFIG_MACH_TOSA)		+= tosa.o tosa_power.o
+--- linux-2.6.24.orig/arch/arm/mach-pxa/Makefile	2008-03-10 16:08:01.000000000 +0000
++++ linux-2.6.24/arch/arm/mach-pxa/Makefile	2008-03-10 16:09:23.000000000 +0000
+@@ -23,6 +23,7 @@
+ obj-$(CONFIG_MACH_TOSA)		+= tosa.o
  obj-$(CONFIG_MACH_EM_X270)	+= em-x270.o
  obj-$(CONFIG_MACH_HX2750)	+= hx2750.o hx2750_test.o
 +obj-$(CONFIG_MACH_HTCUNIVERSAL) += htcuniversal/
@@ -3552,9 +3552,9 @@ Index: linux-2.6.24/arch/arm/mach-pxa/Makefile
    obj-y				+= zylonite.o
 Index: linux-2.6.24/drivers/leds/Kconfig
 ===================================================================
---- linux-2.6.24.orig/drivers/leds/Kconfig	2008-02-24 02:40:23.817034852 +0300
-+++ linux-2.6.24/drivers/leds/Kconfig	2008-02-24 02:40:56.652035294 +0300
-@@ -114,6 +114,13 @@ config LEDS_CM_X270
+--- linux-2.6.24.orig/drivers/leds/Kconfig	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/drivers/leds/Kconfig	2008-03-10 16:09:23.000000000 +0000
+@@ -114,6 +114,13 @@
  	help
  	  This option enables support for the CM-X270 LEDs.
  
@@ -3571,7 +3571,7 @@ Index: linux-2.6.24/drivers/leds/Kconfig
 Index: linux-2.6.24/drivers/leds/leds-asic3.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/drivers/leds/leds-asic3.c	2008-02-24 02:40:56.652035294 +0300
++++ linux-2.6.24/drivers/leds/leds-asic3.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,189 @@
 +/*
 + * LEDs support for HTC ASIC3 devices.
@@ -3764,9 +3764,9 @@ Index: linux-2.6.24/drivers/leds/leds-asic3.c
 +MODULE_LICENSE("GPL");
 Index: linux-2.6.24/drivers/mfd/Kconfig
 ===================================================================
---- linux-2.6.24.orig/drivers/mfd/Kconfig	2008-02-24 02:40:23.841034801 +0300
-+++ linux-2.6.24/drivers/mfd/Kconfig	2008-02-24 02:40:56.652035294 +0300
-@@ -43,6 +43,16 @@ config MFD_TSC2101
+--- linux-2.6.24.orig/drivers/mfd/Kconfig	2008-03-10 16:07:51.000000000 +0000
++++ linux-2.6.24/drivers/mfd/Kconfig	2008-03-10 16:09:23.000000000 +0000
+@@ -21,6 +21,16 @@
  	help
  	  Support for TI TSC2101 Touchscreen and Audio Codec
  
@@ -3785,8 +3785,8 @@ Index: linux-2.6.24/drivers/mfd/Kconfig
  menu "Multimedia Capabilities Port drivers"
 Index: linux-2.6.24/drivers/mfd/Makefile
 ===================================================================
---- linux-2.6.24.orig/drivers/mfd/Makefile	2008-02-24 02:40:23.849034737 +0300
-+++ linux-2.6.24/drivers/mfd/Makefile	2008-02-24 02:40:56.652035294 +0300
+--- linux-2.6.24.orig/drivers/mfd/Makefile	2008-03-10 16:07:51.000000000 +0000
++++ linux-2.6.24/drivers/mfd/Makefile	2008-03-10 16:09:23.000000000 +0000
 @@ -2,6 +2,8 @@
  # Makefile for multifunction miscellaneous devices
  #
@@ -3795,11 +3795,11 @@ Index: linux-2.6.24/drivers/mfd/Makefile
 +
  obj-$(CONFIG_MFD_SM501)		+= sm501.o
  
- obj-$(CONFIG_MFD_CORE)		+= mfd-core.o
+ obj-$(CONFIG_MCP)		+= mcp-core.o
 Index: linux-2.6.24/drivers/mfd/asic3_base.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/drivers/mfd/asic3_base.c	2008-02-24 02:40:56.652035294 +0300
++++ linux-2.6.24/drivers/mfd/asic3_base.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,1208 @@
 +/*
 + * Driver interface to HTC "ASIC3"
@@ -5012,7 +5012,7 @@ Index: linux-2.6.24/drivers/mfd/asic3_base.c
 Index: linux-2.6.24/drivers/mfd/soc-core.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/drivers/mfd/soc-core.c	2008-02-24 02:40:56.652035294 +0300
++++ linux-2.6.24/drivers/mfd/soc-core.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,106 @@
 +/*
 + * drivers/soc/soc-core.c
@@ -5123,7 +5123,7 @@ Index: linux-2.6.24/drivers/mfd/soc-core.c
 Index: linux-2.6.24/drivers/mfd/soc-core.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/drivers/mfd/soc-core.h	2008-02-24 02:40:56.652035294 +0300
++++ linux-2.6.24/drivers/mfd/soc-core.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,30 @@
 +/*
 + * drivers/soc/soc-core.h
@@ -5158,7 +5158,7 @@ Index: linux-2.6.24/drivers/mfd/soc-core.h
 Index: linux-2.6.24/include/asm-arm/arch-pxa/clock.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/arch-pxa/clock.h	2008-02-24 02:40:56.656035541 +0300
++++ linux-2.6.24/include/asm-arm/arch-pxa/clock.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,27 @@
 +/*
 + *  linux/include/asm-arm/arch-pxa/clock.h
@@ -5190,7 +5190,7 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/clock.h
 Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-asic.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-asic.h	2008-02-24 02:40:56.656035541 +0300
++++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-asic.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,213 @@
 +/*
 + * include/asm/arm/arch-pxa/htcuniversal-asic.h
@@ -5408,7 +5408,7 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-asic.h
 Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-gpio.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-gpio.h	2008-02-24 02:40:56.656035541 +0300
++++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-gpio.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,220 @@
 +/*
 + * include/asm-arm/arch-pxa/htcuniversal-gpio.h
@@ -5633,7 +5633,7 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-gpio.h
 Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-init.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-init.h	2008-02-24 02:40:56.656035541 +0300
++++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-init.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,14 @@
 +/*
 + * include/asm/arm/arch-pxa/htcuniversal-init.h
@@ -5652,7 +5652,7 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-init.h
 Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal.h	2008-02-24 02:40:56.656035541 +0300
++++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,3 @@
 +#include <asm/arch/irqs.h>
 +
@@ -5660,7 +5660,7 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal.h
 Index: linux-2.6.24/include/asm-arm/arch-pxa/pxa-pm_ll.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/arch-pxa/pxa-pm_ll.h	2008-02-24 02:40:56.656035541 +0300
++++ linux-2.6.24/include/asm-arm/arch-pxa/pxa-pm_ll.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,6 @@
 +struct pxa_ll_pm_ops {
 +	void (*suspend)(unsigned long);
@@ -5671,7 +5671,7 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/pxa-pm_ll.h
 Index: linux-2.6.24/include/asm-arm/hardware/asic3_keys.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/hardware/asic3_keys.h	2008-02-24 02:40:56.660035858 +0300
++++ linux-2.6.24/include/asm-arm/hardware/asic3_keys.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,18 @@
 +#include <linux/input.h>
 +
@@ -5694,7 +5694,7 @@ Index: linux-2.6.24/include/asm-arm/hardware/asic3_keys.h
 Index: linux-2.6.24/include/asm-arm/hardware/asic3_leds.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/hardware/asic3_leds.h	2008-02-24 02:40:56.660035858 +0300
++++ linux-2.6.24/include/asm-arm/hardware/asic3_leds.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,34 @@
 +/*
 + * LEDs support for HTC ASIC3 devices.
@@ -5733,7 +5733,7 @@ Index: linux-2.6.24/include/asm-arm/hardware/asic3_leds.h
 Index: linux-2.6.24/include/asm-arm/hardware/ipaq-asic3.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/hardware/ipaq-asic3.h	2008-02-24 02:40:56.660035858 +0300
++++ linux-2.6.24/include/asm-arm/hardware/ipaq-asic3.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,602 @@
 +/*
 + *
@@ -6340,7 +6340,7 @@ Index: linux-2.6.24/include/asm-arm/hardware/ipaq-asic3.h
 Index: linux-2.6.24/include/linux/gpiodev.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/linux/gpiodev.h	2008-02-24 02:40:56.660035858 +0300
++++ linux-2.6.24/include/linux/gpiodev.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,44 @@
 +#ifndef __GPIODEV_H
 +#define __GPIODEV_H
@@ -6389,7 +6389,7 @@ Index: linux-2.6.24/include/linux/gpiodev.h
 Index: linux-2.6.24/include/linux/input_pda.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/linux/input_pda.h	2008-02-24 02:40:56.660035858 +0300
++++ linux-2.6.24/include/linux/input_pda.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,47 @@
 +#ifndef _INPUT_PDA_H
 +#define _INPUT_PDA_H
@@ -6441,7 +6441,7 @@ Index: linux-2.6.24/include/linux/input_pda.h
 Index: linux-2.6.24/include/linux/soc/asic3_base.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/linux/soc/asic3_base.h	2008-02-24 02:40:56.660035858 +0300
++++ linux-2.6.24/include/linux/soc/asic3_base.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,104 @@
 +#include <asm/types.h>
 +#include <linux/gpiodev.h>
@@ -6550,7 +6550,7 @@ Index: linux-2.6.24/include/linux/soc/asic3_base.h
 Index: linux-2.6.24/include/linux/soc/tmio_mmc.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/linux/soc/tmio_mmc.h	2008-02-24 02:40:56.660035858 +0300
++++ linux-2.6.24/include/linux/soc/tmio_mmc.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,17 @@
 +#include <linux/platform_device.h>
 +
@@ -6571,8 +6571,8 @@ Index: linux-2.6.24/include/linux/soc/tmio_mmc.h
 +};
 Index: linux-2.6.24/include/asm-arm/arch-pxa/pxa-regs.h
 ===================================================================
---- linux-2.6.24.orig/include/asm-arm/arch-pxa/pxa-regs.h	2008-02-24 02:40:23.965046594 +0300
-+++ linux-2.6.24/include/asm-arm/arch-pxa/pxa-regs.h	2008-02-24 02:40:56.664035757 +0300
+--- linux-2.6.24.orig/include/asm-arm/arch-pxa/pxa-regs.h	2008-03-10 16:07:59.000000000 +0000
++++ linux-2.6.24/include/asm-arm/arch-pxa/pxa-regs.h	2008-03-10 16:09:23.000000000 +0000
 @@ -2058,6 +2058,8 @@
  #define LDCMD_SOFINT	(1 << 22)
  #define LDCMD_EOFINT	(1 << 21)
@@ -6584,9 +6584,9 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/pxa-regs.h
  #define LCCR5_SOFM2	(1<<1)		/* Start Of Frame Mask for Overlay 2 (channel 2) */
 Index: linux-2.6.24/drivers/mmc/host/Makefile
 ===================================================================
---- linux-2.6.24.orig/drivers/mmc/host/Makefile	2008-02-24 02:40:23.885035847 +0300
-+++ linux-2.6.24/drivers/mmc/host/Makefile	2008-02-24 02:40:56.664035757 +0300
-@@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_SDHCI)		+= sdhci.o
+--- linux-2.6.24.orig/drivers/mmc/host/Makefile	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/drivers/mmc/host/Makefile	2008-03-10 16:09:23.000000000 +0000
+@@ -13,6 +13,7 @@
  obj-$(CONFIG_MMC_RICOH_MMC)	+= ricoh_mmc.o
  obj-$(CONFIG_MMC_WBSD)		+= wbsd.o
  obj-$(CONFIG_MMC_AU1X)		+= au1xmmc.o
@@ -6597,7 +6597,7 @@ Index: linux-2.6.24/drivers/mmc/host/Makefile
 Index: linux-2.6.24/drivers/mmc/host/asic3_mmc.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/drivers/mmc/host/asic3_mmc.c	2008-02-24 02:40:56.664035757 +0300
++++ linux-2.6.24/drivers/mmc/host/asic3_mmc.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,900 @@
 +/* Note that this driver can likely be merged into the tmio driver, so
 + * consider this code temporary.  It works, though.
@@ -7502,7 +7502,7 @@ Index: linux-2.6.24/drivers/mmc/host/asic3_mmc.c
 Index: linux-2.6.24/drivers/mmc/host/asic3_mmc.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/drivers/mmc/host/asic3_mmc.h	2008-02-24 02:40:56.664035757 +0300
++++ linux-2.6.24/drivers/mmc/host/asic3_mmc.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,25 @@
 +#ifndef __ASIC3_MMC_H
 +#define __ASIC3_MMC_H
@@ -7529,22 +7529,10 @@ Index: linux-2.6.24/drivers/mmc/host/asic3_mmc.h
 +#define DONT_CARE_BUFFER_BITS ( SD_CTRL_INTMASKBUFFER_UNK7 | SD_CTRL_INTMASKBUFFER_CMD_BUSY )
 +
 +#endif // __ASIC3_MMC_H
-Index: linux-2.6.24/drivers/input/keyboard/Makefile
-===================================================================
---- linux-2.6.24.orig/drivers/input/keyboard/Makefile	2008-02-24 02:40:23.905037294 +0300
-+++ linux-2.6.24/drivers/input/keyboard/Makefile	2008-02-24 02:40:56.664035757 +0300
-@@ -16,6 +16,7 @@ obj-$(CONFIG_KEYBOARD_STOWAWAY)		+= stow
- obj-$(CONFIG_KEYBOARD_CORGI)		+= corgikbd.o
- obj-$(CONFIG_KEYBOARD_SPITZ)		+= spitzkbd.o
- obj-$(CONFIG_KEYBOARD_TOSA)		+= tosakbd.o
-+obj-$(CONFIG_KEYBOARD_ASIC3)		+= asic3_keys.o
- obj-$(CONFIG_KEYBOARD_HIL)		+= hil_kbd.o
- obj-$(CONFIG_KEYBOARD_HIL_OLD)		+= hilkbd.o
- obj-$(CONFIG_KEYBOARD_OMAP)		+= omap-keypad.o
 Index: linux-2.6.24/drivers/input/keyboard/asic3_keys.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/drivers/input/keyboard/asic3_keys.c	2008-02-24 02:40:56.668036144 +0300
++++ linux-2.6.24/drivers/input/keyboard/asic3_keys.c	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,131 @@
 +/*
 + * Generic buttons driver for ASIC3 SoC.
@@ -7679,10 +7667,10 @@ Index: linux-2.6.24/drivers/input/keyboard/asic3_keys.c
 +MODULE_LICENSE("GPL");
 Index: linux-2.6.24/include/asm-arm/arch-pxa/irqs.h
 ===================================================================
---- linux-2.6.24.orig/include/asm-arm/arch-pxa/irqs.h	2008-02-24 02:40:23.973034657 +0300
-+++ linux-2.6.24/include/asm-arm/arch-pxa/irqs.h	2008-02-24 02:40:56.668036144 +0300
-@@ -183,6 +183,8 @@
-       defined(CONFIG_MACH_TOSA) || \
+--- linux-2.6.24.orig/include/asm-arm/arch-pxa/irqs.h	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/include/asm-arm/arch-pxa/irqs.h	2008-03-10 16:09:23.000000000 +0000
+@@ -182,6 +182,8 @@
+       defined(CONFIG_MACH_LOGICPD_PXA270) || \
        defined(CONFIG_MACH_MAINSTONE)
  #define NR_IRQS			(IRQ_BOARD_END)
 +#elif defined(CONFIG_MACH_HTCUNIVERSAL)
@@ -7693,7 +7681,7 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/irqs.h
 Index: linux-2.6.24/include/asm-arm/arch-pxa/serial.h
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/arch-pxa/serial.h	2008-02-24 02:40:56.668036144 +0300
++++ linux-2.6.24/include/asm-arm/arch-pxa/serial.h	2008-03-10 16:09:23.000000000 +0000
 @@ -0,0 +1,78 @@
 +/*
 + *  linux/include/asm-arm/arch-pxa/serial.h
@@ -7775,8 +7763,8 @@ Index: linux-2.6.24/include/asm-arm/arch-pxa/serial.h
 +void pxa_set_hwuart_info(struct platform_pxa_serial_funcs *hwuart_funcs);
 Index: linux-2.6.24/drivers/serial/pxa.c
 ===================================================================
---- linux-2.6.24.orig/drivers/serial/pxa.c	2008-02-24 02:40:23.925046354 +0300
-+++ linux-2.6.24/drivers/serial/pxa.c	2008-02-24 02:40:56.668036144 +0300
+--- linux-2.6.24.orig/drivers/serial/pxa.c	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/drivers/serial/pxa.c	2008-03-10 16:09:23.000000000 +0000
 @@ -47,6 +47,7 @@
  #include <asm/io.h>
  #include <asm/hardware.h>
@@ -7785,7 +7773,7 @@ Index: linux-2.6.24/drivers/serial/pxa.c
  #include <asm/arch/pxa-regs.h>
  
  
-@@ -60,6 +61,14 @@ struct uart_pxa_port {
+@@ -60,6 +61,14 @@
  	char			*name;
  };
  
@@ -7800,7 +7788,7 @@ Index: linux-2.6.24/drivers/serial/pxa.c
  static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
  {
  	offset <<= 2;
-@@ -347,6 +356,9 @@ static int serial_pxa_startup(struct uar
+@@ -347,6 +356,9 @@
  	unsigned long flags;
  	int retval;
  
@@ -7810,7 +7798,7 @@ Index: linux-2.6.24/drivers/serial/pxa.c
  	if (port->line == 3) /* HWUART */
  		up->mcr |= UART_MCR_AFE;
  	else
-@@ -404,6 +416,12 @@ static int serial_pxa_startup(struct uar
+@@ -404,6 +416,12 @@
  	(void) serial_in(up, UART_IIR);
  	(void) serial_in(up, UART_MSR);
  
@@ -7823,7 +7811,7 @@ Index: linux-2.6.24/drivers/serial/pxa.c
  	return 0;
  }
  
-@@ -412,6 +430,8 @@ static void serial_pxa_shutdown(struct u
+@@ -412,6 +430,8 @@
  	struct uart_pxa_port *up = (struct uart_pxa_port *)port;
  	unsigned long flags;
  
@@ -7832,7 +7820,7 @@ Index: linux-2.6.24/drivers/serial/pxa.c
  	free_irq(up->port.irq, up);
  
  	/*
-@@ -433,6 +453,8 @@ static void serial_pxa_shutdown(struct u
+@@ -433,6 +453,8 @@
  				  UART_FCR_CLEAR_RCVR |
  				  UART_FCR_CLEAR_XMIT);
  	serial_out(up, UART_FCR, 0);
@@ -7843,8 +7831,8 @@ Index: linux-2.6.24/drivers/serial/pxa.c
  static void
 Index: linux-2.6.24/arch/arm/mach-pxa/generic.c
 ===================================================================
---- linux-2.6.24.orig/arch/arm/mach-pxa/generic.c	2008-02-24 02:40:23.809034497 +0300
-+++ linux-2.6.24/arch/arm/mach-pxa/generic.c	2008-02-24 02:40:56.668036144 +0300
+--- linux-2.6.24.orig/arch/arm/mach-pxa/generic.c	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/arch/arm/mach-pxa/generic.c	2008-03-10 16:09:23.000000000 +0000
 @@ -38,6 +38,7 @@
  #include <asm/arch/mmc.h>
  #include <asm/arch/irda.h>
@@ -7853,7 +7841,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/generic.c
  
  #include "devices.h"
  #include "generic.h"
-@@ -412,6 +413,18 @@ struct platform_device pxa_device_hwuart
+@@ -412,6 +413,18 @@
  	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
  };
  
@@ -7874,9 +7862,9 @@ Index: linux-2.6.24/arch/arm/mach-pxa/generic.c
  		.start	= 0x40301680,
 Index: linux-2.6.24/drivers/leds/Makefile
 ===================================================================
---- linux-2.6.24.orig/drivers/leds/Makefile	2008-02-24 02:40:23.833034725 +0300
-+++ linux-2.6.24/drivers/leds/Makefile	2008-02-24 02:40:56.668036144 +0300
-@@ -15,6 +15,7 @@ obj-$(CONFIG_LEDS_AMS_DELTA)		+= leds-am
+--- linux-2.6.24.orig/drivers/leds/Makefile	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/drivers/leds/Makefile	2008-03-10 16:09:23.000000000 +0000
+@@ -15,6 +15,7 @@
  obj-$(CONFIG_LEDS_NET48XX)		+= leds-net48xx.o
  obj-$(CONFIG_LEDS_WRAP)			+= leds-wrap.o
  obj-$(CONFIG_LEDS_H1940)		+= leds-h1940.o
@@ -7886,9 +7874,9 @@ Index: linux-2.6.24/drivers/leds/Makefile
  obj-$(CONFIG_LEDS_GPIO)			+= leds-gpio.o
 Index: linux-2.6.24/drivers/input/keyboard/Kconfig
 ===================================================================
---- linux-2.6.24.orig/drivers/input/keyboard/Kconfig	2008-02-24 02:40:23.917037268 +0300
-+++ linux-2.6.24/drivers/input/keyboard/Kconfig	2008-02-24 02:40:56.676035032 +0300
-@@ -314,4 +314,11 @@ config KEYBOARD_BFIN
+--- linux-2.6.24.orig/drivers/input/keyboard/Kconfig	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/drivers/input/keyboard/Kconfig	2008-03-10 16:09:23.000000000 +0000
+@@ -293,4 +293,11 @@
  	  To compile this driver as a module, choose M here: the
  	  module will be called bf54x-keys.
  
@@ -7902,16 +7890,31 @@ Index: linux-2.6.24/drivers/input/keyboard/Kconfig
  endif
 Index: linux-2.6.24/drivers/mmc/host/Kconfig
 ===================================================================
---- linux-2.6.24.orig/drivers/mmc/host/Kconfig	2008-02-24 02:41:04.868035778 +0300
-+++ linux-2.6.24/drivers/mmc/host/Kconfig	2008-02-24 02:41:46.328053402 +0300
-@@ -136,3 +136,10 @@ config MMC_TMIO
- 	help
- 	  This provides support for the SD/MMC cell found in TC6393XB,
- 	  T7L66XB and also ipaq ASIC3
-+
+--- linux-2.6.24.orig/drivers/mmc/host/Kconfig	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/drivers/mmc/host/Kconfig	2008-03-10 16:09:59.000000000 +0000
+@@ -24,6 +24,13 @@
+ 
+ 	  If unsure, say N.
+ 
 +config MMC_ASIC3
 +	tristate "HTC ASIC3 SD/MMC support"
 +	depends on MMC && HTC_ASIC3
 +	help
 +	  This provides support for the ASIC3 SD/MMC controller, used
 +	  in the iPAQ hx4700 and others.
++
+ config MMC_SDHCI
+ 	tristate "Secure Digital Host Controller Interface support  (EXPERIMENTAL)"
+ 	depends on PCI && EXPERIMENTAL
+Index: linux-2.6.24/drivers/input/keyboard/Makefile
+===================================================================
+--- linux-2.6.24.orig/drivers/input/keyboard/Makefile	2008-01-24 22:58:37.000000000 +0000
++++ linux-2.6.24/drivers/input/keyboard/Makefile	2008-03-10 16:10:28.000000000 +0000
+@@ -6,6 +6,7 @@
+ 
+ obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
+ obj-$(CONFIG_KEYBOARD_SUNKBD)		+= sunkbd.o
++obj-$(CONFIG_KEYBOARD_ASIC3)		+= asic3_keys.o
+ obj-$(CONFIG_KEYBOARD_LKKBD)		+= lkkbd.o
+ obj-$(CONFIG_KEYBOARD_XTKBD)		+= xtkbd.o
+ obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
diff --git a/packages/linux/linux-rp-2.6.24/sharpsl-rc-r1.patch b/packages/linux/linux-rp-2.6.24/sharpsl-rc-r1.patch
index 453010a197..32a94c7cea 100644
--- a/packages/linux/linux-rp-2.6.24/sharpsl-rc-r1.patch
+++ b/packages/linux/linux-rp-2.6.24/sharpsl-rc-r1.patch
@@ -1,7 +1,7 @@
 Index: linux-2.6.24/arch/arm/mach-pxa/spitz.c
 ===================================================================
---- linux-2.6.24.orig/arch/arm/mach-pxa/spitz.c	2008-01-27 02:10:17.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/spitz.c	2008-01-27 02:10:52.000000000 +0000
+--- linux-2.6.24.orig/arch/arm/mach-pxa/spitz.c	2008-03-10 17:05:37.000000000 +0000
++++ linux-2.6.24/arch/arm/mach-pxa/spitz.c	2008-03-10 17:05:55.000000000 +0000
 @@ -259,6 +259,13 @@
  	.id		= -1,
  };
@@ -26,8 +26,8 @@ Index: linux-2.6.24/arch/arm/mach-pxa/spitz.c
  	&spitzled_device,
 Index: linux-2.6.24/drivers/input/keyboard/Kconfig
 ===================================================================
---- linux-2.6.24.orig/drivers/input/keyboard/Kconfig	2008-01-27 02:10:20.000000000 +0000
-+++ linux-2.6.24/drivers/input/keyboard/Kconfig	2008-01-27 02:10:52.000000000 +0000
+--- linux-2.6.24.orig/drivers/input/keyboard/Kconfig	2008-03-10 17:05:40.000000000 +0000
++++ linux-2.6.24/drivers/input/keyboard/Kconfig	2008-03-10 17:05:55.000000000 +0000
 @@ -154,6 +154,17 @@
  	  To compile this driver as a module, choose M here: the
  	  module will be called spitzkbd.
@@ -48,20 +48,18 @@ Index: linux-2.6.24/drivers/input/keyboard/Kconfig
  	depends on AMIGA
 Index: linux-2.6.24/drivers/input/keyboard/Makefile
 ===================================================================
---- linux-2.6.24.orig/drivers/input/keyboard/Makefile	2008-01-27 02:10:20.000000000 +0000
-+++ linux-2.6.24/drivers/input/keyboard/Makefile	2008-01-27 02:11:43.000000000 +0000
-@@ -15,6 +15,7 @@
- obj-$(CONFIG_KEYBOARD_STOWAWAY)		+= stowaway.o
- obj-$(CONFIG_KEYBOARD_CORGI)		+= corgikbd.o
- obj-$(CONFIG_KEYBOARD_SPITZ)		+= spitzkbd.o
+--- linux-2.6.24.orig/drivers/input/keyboard/Makefile	2008-03-10 17:05:40.000000000 +0000
++++ linux-2.6.24/drivers/input/keyboard/Makefile	2008-03-10 17:06:17.000000000 +0000
+@@ -26,3 +26,5 @@
+ obj-$(CONFIG_KEYBOARD_HP7XX)		+= jornada720_kbd.o
+ obj-$(CONFIG_KEYBOARD_MAPLE)		+= maple_keyb.o
+ obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
 +obj-$(CONFIG_SHARPSL_RC)		+= sharpsl_rc.o
- obj-$(CONFIG_KEYBOARD_ASIC3)		+= asic3_keys.o
- obj-$(CONFIG_KEYBOARD_HIL)		+= hil_kbd.o
- obj-$(CONFIG_KEYBOARD_HIL_OLD)		+= hilkbd.o
++
 Index: linux-2.6.24/drivers/input/keyboard/sharpsl_rc.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.24/drivers/input/keyboard/sharpsl_rc.c	2008-01-27 02:10:52.000000000 +0000
++++ linux-2.6.24/drivers/input/keyboard/sharpsl_rc.c	2008-03-10 17:05:55.000000000 +0000
 @@ -0,0 +1,291 @@
 +/*
 + *  Keyboard driver for Sharp Clamshell Models (SL-Cxx00)
@@ -357,7 +355,7 @@ Index: linux-2.6.24/drivers/input/keyboard/sharpsl_rc.c
 Index: linux-2.6.24/drivers/input/keyboard/spitzkbd.c
 ===================================================================
 --- linux-2.6.24.orig/drivers/input/keyboard/spitzkbd.c	2008-01-24 22:58:37.000000000 +0000
-+++ linux-2.6.24/drivers/input/keyboard/spitzkbd.c	2008-01-27 02:10:52.000000000 +0000
++++ linux-2.6.24/drivers/input/keyboard/spitzkbd.c	2008-03-10 17:05:55.000000000 +0000
 @@ -19,6 +19,7 @@
  #include <linux/jiffies.h>
  #include <linux/module.h>
@@ -440,8 +438,8 @@ Index: linux-2.6.24/drivers/input/keyboard/spitzkbd.c
  	del_timer_sync(&spitzkbd->htimer);
 Index: linux-2.6.24/arch/arm/mach-pxa/sharpsl.h
 ===================================================================
---- linux-2.6.24.orig/arch/arm/mach-pxa/sharpsl.h	2008-01-27 02:10:15.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/sharpsl.h	2008-01-27 02:10:52.000000000 +0000
+--- linux-2.6.24.orig/arch/arm/mach-pxa/sharpsl.h	2008-03-10 17:05:35.000000000 +0000
++++ linux-2.6.24/arch/arm/mach-pxa/sharpsl.h	2008-03-10 17:05:55.000000000 +0000
 @@ -37,15 +37,10 @@
   */
  #define READ_GPIO_BIT(x)    (GPLR(x) & GPIO_bit(x))
@@ -462,7 +460,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/sharpsl.h
 Index: linux-2.6.24/arch/arm/mach-pxa/sharpsl_pm.c
 ===================================================================
 --- linux-2.6.24.orig/arch/arm/mach-pxa/sharpsl_pm.c	2008-01-24 22:58:37.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/sharpsl_pm.c	2008-01-27 02:10:52.000000000 +0000
++++ linux-2.6.24/arch/arm/mach-pxa/sharpsl_pm.c	2008-03-10 17:05:55.000000000 +0000
 @@ -135,6 +135,8 @@
  			| MAXCTRL_SGL | MAXCTRL_UNI | MAXCTRL_STR);
  }
@@ -475,7 +473,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/sharpsl_pm.c
 Index: linux-2.6.24/include/asm-arm/hardware/sharpsl_pm.h
 ===================================================================
 --- linux-2.6.24.orig/include/asm-arm/hardware/sharpsl_pm.h	2008-01-24 22:58:37.000000000 +0000
-+++ linux-2.6.24/include/asm-arm/hardware/sharpsl_pm.h	2008-01-27 02:10:52.000000000 +0000
++++ linux-2.6.24/include/asm-arm/hardware/sharpsl_pm.h	2008-03-10 17:05:55.000000000 +0000
 @@ -104,3 +104,10 @@
  irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id);
  irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id);
@@ -490,7 +488,7 @@ Index: linux-2.6.24/include/asm-arm/hardware/sharpsl_pm.h
 Index: linux-2.6.24/include/linux/input.h
 ===================================================================
 --- linux-2.6.24.orig/include/linux/input.h	2008-01-24 22:58:37.000000000 +0000
-+++ linux-2.6.24/include/linux/input.h	2008-01-27 02:10:52.000000000 +0000
++++ linux-2.6.24/include/linux/input.h	2008-03-10 17:05:55.000000000 +0000
 @@ -636,6 +636,7 @@
  #define SW_TABLET_MODE		0x01  /* set = tablet mode */
  #define SW_HEADPHONE_INSERT	0x02  /* set = inserted */
@@ -501,8 +499,8 @@ Index: linux-2.6.24/include/linux/input.h
  
 Index: linux-2.6.24/arch/arm/mach-pxa/spitz_pm.c
 ===================================================================
---- linux-2.6.24.orig/arch/arm/mach-pxa/spitz_pm.c	2008-01-24 22:58:37.000000000 +0000
-+++ linux-2.6.24/arch/arm/mach-pxa/spitz_pm.c	2008-01-27 02:10:52.000000000 +0000
+--- linux-2.6.24.orig/arch/arm/mach-pxa/spitz_pm.c	2008-03-10 17:05:40.000000000 +0000
++++ linux-2.6.24/arch/arm/mach-pxa/spitz_pm.c	2008-03-10 17:05:55.000000000 +0000
 @@ -162,6 +162,13 @@
  	if (resume_on_alarm && (PEDR & PWER_RTC))
  		is_resume |= PWER_RTC;
diff --git a/packages/mplayer/mplayer_0.0+1.0rc2.bb b/packages/mplayer/mplayer_0.0+1.0rc2.bb
index d963ac03cf..ae8de7caf4 100644
--- a/packages/mplayer/mplayer_0.0+1.0rc2.bb
+++ b/packages/mplayer/mplayer_0.0+1.0rc2.bb
@@ -40,7 +40,7 @@ PACKAGE_ARCH_hx4700 = "hx4700"
 RCONFLICTS_${PN} = "mplayer-atty"
 RREPLACES_${PN} = "mplayer-atty"
 
-PR = "r6"
+PR = "r7"
 
 PARALLEL_MAKE = ""
 
@@ -187,6 +187,10 @@ TARGET_CC_ARCH = "${@base_contains('MACHINE_FEATURES', 'iwmmxt', '-march=iwmmxt
 EXTRA_OECONF_append = " ${@base_contains('MACHINE_FEATURES', 'iwmmxt', '--enable-pxa --enable-iwmmxt', '',d)} "
 EXTRA_OECONF_append = " ${@base_contains('MACHINE_FEATURES', 'x86', '--enable-runtime-cpudetection', '',d)} "
 
+FULL_OPTIMIZATION = "-fexpensive-optimizations -fomit-frame-pointer -frename-registers -O4 -ffast-math"
+BUILD_OPTIMIZATION = "${FULL_OPTIMIZATION}"
+
+
 do_configure() {
 	cp ${WORKDIR}/vo_w100.c ${S}/libvo
 	cp ${WORKDIR}/vo_w100_api.h ${S}/libvo
diff --git a/packages/nano/files/.mtn2git_empty b/packages/nano/files/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/nano/files/.mtn2git_empty
diff --git a/packages/nano/nano-1.2.1/glib.m4 b/packages/nano/files/glib.m4
index b8094bbfe0..b8094bbfe0 100644
--- a/packages/nano/nano-1.2.1/glib.m4
+++ b/packages/nano/files/glib.m4
diff --git a/packages/nano/nano-1.2.1/configure.patch b/packages/nano/nano-1.2.1/configure.patch
deleted file mode 100644
index c8008221a0..0000000000
--- a/packages/nano/nano-1.2.1/configure.patch
+++ /dev/null
@@ -1,1116 +0,0 @@
-
-#
-# Patch managed by http://www.mn-logistik.de/unsupported/pxa250/patcher
-#
-
---- nano-1.2.1/configure.ac~configure
-+++ nano-1.2.1/configure.ac
-@@ -19,12 +19,12 @@
- #
- # $Id: configure.ac,v 1.44 2003/03/11 03:50:39 astyanax Exp $
- 
--AC_INIT([GNU Nano], [1.2.1], [nano-devel@gnu.org], [nano])
-+AC_INIT([GNU Nano],[1.2.1],[nano-devel@gnu.org],[nano])
- AC_CONFIG_SRCDIR([nano.c])
- AM_INIT_AUTOMAKE
- AM_CONFIG_HEADER([config.h:config.h.in])
- 
--AC_PREREQ(2.52)
-+AC_PREREQ(2.57)
- 
- dnl Checks for programs.
- AC_PROG_CC
-@@ -38,14 +38,15 @@
- dnl Checks for header files.
- AC_HEADER_STDC
- AC_CHECK_HEADERS(fcntl.h getopt.h libintl.h limits.h regex.h termio.h termios.h unistd.h)
-+
- AC_CHECK_HEADER(regex.h,
--    AC_MSG_CHECKING([for broken regexec])
--    AC_TRY_RUN([
-+    AC_CACHE_CHECK([for broken regexec],
-+            ac_cv_regexec_segfault_emptystr,
-+            AC_RUN_IFELSE([AC_LANG_SOURCE([[
- #include <sys/types.h>
- #include <regex.h>
--int main() { regex_t reg; size_t n; regmatch_t r; regcomp(&reg, ".", 0); regexec(&reg, "", n, &r, 0); return 0; }],
--	AC_MSG_RESULT(no),
--	AC_MSG_RESULT(yes); AC_DEFINE(BROKEN_REGEXEC, 1, [Define this if your regexec() function segfaults when passed an empty string.])
-+int main() { regex_t reg; size_t n; regmatch_t r; regcomp(&reg, ".", 0); regexec(&reg, "", n, &r, 0); return 0; }]])],[AC_MSG_RESULT(no)],[AC_MSG_RESULT(yes); AC_DEFINE(BROKEN_REGEXEC, 1, Define this if your regexec() function segfaults when passed an empty string.)
-+            ],[])
-     )
- )
- 
-@@ -198,11 +199,10 @@
- 	    AC_MSG_CHECKING([for SLtt_initialize in -lslang])
- 	    _libs=$LIBS
- 	    LIBS="$LIBS -lslang"
--	    AC_TRY_RUN([
-+	    AC_RUN_IFELSE([AC_LANG_SOURCE([[
- #include <stdio.h>
- #include <slcurses.h>
--int main () { SLtt_initialize (NULL); return 0; }],
--		[AC_MSG_RESULT(yes)
-+int main () { SLtt_initialize (NULL); return 0; }]])],[AC_MSG_RESULT(yes)
- 		AC_DEFINE(USE_SLANG, 1, [Define to use the slang wrappers for curses instead of native curses.])
- 		slang_support=yes
- 		if test "$with_slang" != "yes"; then
-@@ -210,7 +210,7 @@
- 		else
- 		    CURSES_LIB="-lslang"
- 		fi
--		CURSES_LIB_NAME=slang], [
-+		CURSES_LIB_NAME=slang],[
- 		AC_MSG_RESULT(no)
- 		# We might need the term library
- 		for termlib in ncurses curses termcap terminfo termlib; do
-@@ -220,7 +220,7 @@
- 
- 		AC_MSG_CHECKING([for SLtt_initialize in -lslang $tcap])
- 		LIBS="$LIBS $tcap"
--		AC_TRY_RUN([
-+AC_TRY_RUN([
- #include <stdio.h>
- #include <slcurses.h>
- int main () { SLtt_initialize (NULL); return 0; }],
-@@ -237,7 +237,7 @@
- 		    # We might need the math library
- 		    AC_MSG_CHECKING([for SLtt_initialize in -lslang $tcap -lm])
- 		    LIBS="$LIBS -lm"
--		    AC_TRY_RUN([
-+AC_TRY_RUN([
- #include <stdio.h>
- #include <slcurses.h>
- int main () { SLtt_initialize (NULL); return 0; }],
-@@ -252,8 +252,7 @@
- 			CURSES_LIB_NAME=slang],
- 			[AC_MSG_RESULT(no)],
- AC_MSG_WARN([*** Can not use slang when cross-compiling]))],
--AC_MSG_WARN([*** Can not use slang when cross-compiling]))], 
--AC_MSG_WARN([*** Can not use slang when cross-compiling])),
-+AC_MSG_WARN([*** Can not use slang when cross-compiling]))],[AC_MSG_WARN(*** Can not use slang when cross-compiling)]),
- 	    AC_MSG_ERROR([
- *** The header file slcurses.h was not found. If you wish to use
- *** slang support this header file is required. Please either
-@@ -334,12 +333,11 @@
-     # Taken from aumix (can't tell from the variable name?)
-     AC_CACHE_CHECK([for private member _use_keypad in WINDOW],
-     aumix_cv_struct_window_usekeypad,
--    [AC_TRY_COMPILE([#ifdef HAVE_NCURSES_H
-+    [AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#ifdef HAVE_NCURSES_H
- #include <ncurses.h>
- #else
- #include <curses.h>
--#endif], [WINDOW w; w._use_keypad;],
--    aumix_cv_struct_window_usekeypad=yes, aumix_cv_struct_window_usekeypad=no)])
-+#endif]], [[WINDOW w; w._use_keypad;]])],[aumix_cv_struct_window_usekeypad=yes],[aumix_cv_struct_window_usekeypad=no])])
-     
-     if test $aumix_cv_struct_window_usekeypad = yes; then
- 	AC_DEFINE(HAVE_USEKEYPAD, 1, [Define this if your curses lib has the _use_keypad flag.])
---- nano-1.2.1/configure~configure
-+++ nano-1.2.1/configure
-@@ -310,7 +310,7 @@
- # include <unistd.h>
- #endif"
- 
--ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO AMTAR install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM AWK SET_MAKE CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE MKINSTALLDIRS MSGFMT GMSGFMT XGETTEXT MSGMERGE build build_cpu build_vendor build_os host host_cpu host_vendor host_os USE_NLS LIBICONV LTLIBICONV INTLLIBS LIBINTL LTLIBINTL POSUB CPP EGREP GLIB_CONFIG GLIB_CFLAGS GLIB_LIBS CURSES_LIB LIBOBJS LTLIBOBJS'
-+ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO AMTAR install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM AWK SET_MAKE am__leading_dot CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE MKINSTALLDIRS MSGFMT GMSGFMT XGETTEXT MSGMERGE build build_cpu build_vendor build_os host host_cpu host_vendor host_os USE_NLS LIBICONV LTLIBICONV INTLLIBS LIBINTL LTLIBINTL POSUB CPP EGREP GLIB_CONFIG GLIB_CFLAGS GLIB_LIBS CURSES_LIB LIBOBJS LTLIBOBJS'
- ac_subst_files=''
- 
- # Initialize some variables set by options.
-@@ -1314,7 +1314,7 @@
- 
- 
- 
--am__api_version="1.6"
-+am__api_version="1.7"
- ac_aux_dir=
- for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do
-   if test -f $ac_dir/install-sh; then
-@@ -1558,6 +1558,15 @@
-   SET_MAKE="MAKE=${MAKE-make}"
- fi
- 
-+rm -rf .tst 2>/dev/null
-+mkdir .tst 2>/dev/null
-+if test -d .tst; then
-+  am__leading_dot=.
-+else
-+  am__leading_dot=_
-+fi
-+rmdir .tst 2>/dev/null
-+
-  # test to see if srcdir already configured
- if test "`cd $srcdir && pwd`" != "`pwd`" &&
-    test -f $srcdir/config.status; then
-@@ -1566,9 +1575,19 @@
-    { (exit 1); exit 1; }; }
- fi
- 
-+# test whether we have cygpath
-+if test -z "$CYGPATH_W"; then
-+  if (cygpath --version) >/dev/null 2>/dev/null; then
-+    CYGPATH_W='cygpath -w'
-+  else
-+    CYGPATH_W=echo
-+  fi
-+fi
-+
-+
- # Define the identity of the package.
-- PACKAGE=nano
-- VERSION=1.2.1
-+ PACKAGE='nano'
-+ VERSION='1.2.1'
- 
- 
- cat >>confdefs.h <<_ACEOF
-@@ -1694,15 +1713,11 @@
- 
- 
- 
--# Add the stamp file to the list of files AC keeps track of,
--# along with our hook.
-           ac_config_headers="$ac_config_headers config.h:config.h.in"
- 
- 
- 
- 
--
--
- ac_ext=c
- ac_cpp='$CPP $CPPFLAGS'
- ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-@@ -2570,24 +2585,16 @@
- ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
- ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
- ac_compiler_gnu=$ac_cv_c_compiler_gnu
--rm -f .deps 2>/dev/null
--mkdir .deps 2>/dev/null
--if test -d .deps; then
--  DEPDIR=.deps
--else
--  # MS-DOS does not allow filenames that begin with a dot.
--  DEPDIR=_deps
--fi
--rmdir .deps 2>/dev/null
--
-+DEPDIR="${am__leading_dot}deps"
- 
-           ac_config_commands="$ac_config_commands depfiles"
- 
- 
- am_make=${MAKE-make}
- cat > confinc << 'END'
--doit:
-+am__doit:
- 	@echo done
-+.PHONY: am__doit
- END
- # If we don't find an include directive, just comment out the code.
- echo "$as_me:$LINENO: checking for style of include used by $am_make" >&5
-@@ -2602,7 +2609,7 @@
- # In particular we don't look at `^make:' because GNU make might
- # be invoked under some other name (usually "gmake"), in which
- # case it prints its new name instead of `make'.
--if test "`$am_make -s -f confmf 2> /dev/null | fgrep -v 'ing directory'`" = "done"; then
-+if test "`$am_make -s -f confmf 2> /dev/null | grep -v 'ing directory'`" = "done"; then
-    am__include=include
-    am__quote=
-    _am_result=GNU
-@@ -2662,18 +2669,32 @@
-   # using a relative directory.
-   cp "$am_depcomp" conftest.dir
-   cd conftest.dir
-+  # We will build objects and dependencies in a subdirectory because
-+  # it helps to detect inapplicable dependency modes.  For instance
-+  # both Tru64's cc and ICC support -MD to output dependencies as a
-+  # side effect of compilation, but ICC will put the dependencies in
-+  # the current directory while Tru64 will put them in the object
-+  # directory.
-+  mkdir sub
- 
-   am_cv_CC_dependencies_compiler_type=none
-   if test "$am_compiler_list" = ""; then
-      am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp`
-   fi
-   for depmode in $am_compiler_list; do
-+    # Setup a source with many dependencies, because some compilers
-+    # like to wrap large dependency lists on column 80 (with \), and
-+    # we should not choose a depcomp mode which is confused by this.
-+    #
-     # We need to recreate these files for each test, as the compiler may
-     # overwrite some of them when testing with obscure command lines.
-     # This happens at least with the AIX C compiler.
--    echo '#include "conftest.h"' > conftest.c
--    echo 'int i;' > conftest.h
--    echo "${am__include} ${am__quote}conftest.Po${am__quote}" > confmf
-+    : > sub/conftest.c
-+    for i in 1 2 3 4 5 6; do
-+      echo '#include "conftst'$i'.h"' >> sub/conftest.c
-+      : > sub/conftst$i.h
-+    done
-+    echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf
- 
-     case $depmode in
-     nosideeffect)
-@@ -2691,13 +2712,20 @@
-     # mode.  It turns out that the SunPro C++ compiler does not properly
-     # handle `-M -o', and we need to detect this.
-     if depmode=$depmode \
--       source=conftest.c object=conftest.o \
--       depfile=conftest.Po tmpdepfile=conftest.TPo \
--       $SHELL ./depcomp $depcc -c conftest.c -o conftest.o >/dev/null 2>&1 &&
--       grep conftest.h conftest.Po > /dev/null 2>&1 &&
-+       source=sub/conftest.c object=sub/conftest.${OBJEXT-o} \
-+       depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \
-+       $SHELL ./depcomp $depcc -c -o sub/conftest.${OBJEXT-o} sub/conftest.c \
-+         >/dev/null 2>conftest.err &&
-+       grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 &&
-+       grep sub/conftest.${OBJEXT-o} sub/conftest.Po > /dev/null 2>&1 &&
-        ${MAKE-make} -s -f confmf > /dev/null 2>&1; then
--      am_cv_CC_dependencies_compiler_type=$depmode
--      break
-+      # icc doesn't choke on unknown options, it will just issue warnings
-+      # (even with -Werror).  So we grep stderr for any message
-+      # that says an option was ignored.
-+      if grep 'ignoring option' conftest.err >/dev/null 2>&1; then :; else
-+        am_cv_CC_dependencies_compiler_type=$depmode
-+        break
-+      fi
-     fi
-   done
- 
-@@ -2714,6 +2742,18 @@
- 
- 
- 
-+if
-+  test "x$enable_dependency_tracking" != xno \
-+  && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then
-+  am__fastdepCC_TRUE=
-+  am__fastdepCC_FALSE='#'
-+else
-+  am__fastdepCC_TRUE='#'
-+  am__fastdepCC_FALSE=
-+fi
-+
-+
-+
- 
-         echo "$as_me:$LINENO: checking for strerror in -lcposix" >&5
- echo $ECHO_N "checking for strerror in -lcposix... $ECHO_C" >&6
-@@ -5290,6 +5330,7 @@
- 
- done
- 
-+
- if test "${ac_cv_header_regex_h+set}" = set; then
-   echo "$as_me:$LINENO: checking for regex.h" >&5
- echo $ECHO_N "checking for regex.h... $ECHO_C" >&6
-@@ -5422,7 +5463,10 @@
- if test $ac_cv_header_regex_h = yes; then
-   echo "$as_me:$LINENO: checking for broken regexec" >&5
- echo $ECHO_N "checking for broken regexec... $ECHO_C" >&6
--    if test "$cross_compiling" = yes; then
-+if test "${ac_cv_regexec_segfault_emptystr+set}" = set; then
-+  echo $ECHO_N "(cached) $ECHO_C" >&6
-+else
-+  if test "$cross_compiling" = yes; then
-   { { echo "$as_me:$LINENO: error: cannot run test program while cross compiling
- See \`config.log' for more details." >&5
- echo "$as_me: error: cannot run test program while cross compiling
-@@ -5472,6 +5516,10 @@
- fi
- 
- fi
-+echo "$as_me:$LINENO: result: $ac_cv_regexec_segfault_emptystr" >&5
-+echo "${ECHO_T}$ac_cv_regexec_segfault_emptystr" >&6
-+
-+fi
- 
- 
- 
-@@ -6037,7 +6085,7 @@
- 		echo "$as_me:$LINENO: checking for SLtt_initialize in -lslang $tcap" >&5
- echo $ECHO_N "checking for SLtt_initialize in -lslang $tcap... $ECHO_C" >&6
- 		LIBS="$LIBS $tcap"
--		if test "$cross_compiling" = yes; then
-+if test "$cross_compiling" = yes; then
-   { echo "$as_me:$LINENO: WARNING: *** Can not use slang when cross-compiling" >&5
- echo "$as_me: WARNING: *** Can not use slang when cross-compiling" >&2;}
- else
-@@ -6091,7 +6139,7 @@
- 		    echo "$as_me:$LINENO: checking for SLtt_initialize in -lslang $tcap -lm" >&5
- echo $ECHO_N "checking for SLtt_initialize in -lslang $tcap -lm... $ECHO_C" >&6
- 		    LIBS="$LIBS -lm"
--		    if test "$cross_compiling" = yes; then
-+if test "$cross_compiling" = yes; then
-   { echo "$as_me:$LINENO: WARNING: *** Can not use slang when cross-compiling" >&5
- echo "$as_me: WARNING: *** Can not use slang when cross-compiling" >&2;}
- else
-@@ -7671,6 +7719,13 @@
- Usually this means the macro was only invoked conditionally." >&2;}
-    { (exit 1); exit 1; }; }
- fi
-+if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then
-+  { { echo "$as_me:$LINENO: error: conditional \"am__fastdepCC\" was never defined.
-+Usually this means the macro was only invoked conditionally." >&5
-+echo "$as_me: error: conditional \"am__fastdepCC\" was never defined.
-+Usually this means the macro was only invoked conditionally." >&2;}
-+   { (exit 1); exit 1; }; }
-+fi
- 
- : ${CONFIG_STATUS=./config.status}
- ac_clean_files_save=$ac_clean_files
-@@ -8104,7 +8159,7 @@
- #
- 
- AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"
--# Capture the value of obsolete ALL_LINGUAS because we need it to compute
-+# Capture the value of obsolete $ALL_LINGUAS because we need it to compute
-     # POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES, CATALOGS. But hide it
-     # from automake.
-     eval 'ALL_LINGUAS''="$ALL_LINGUAS"'
-@@ -8216,6 +8271,7 @@
- s,@INSTALL_PROGRAM@,$INSTALL_PROGRAM,;t t
- s,@INSTALL_SCRIPT@,$INSTALL_SCRIPT,;t t
- s,@INSTALL_DATA@,$INSTALL_DATA,;t t
-+s,@CYGPATH_W@,$CYGPATH_W,;t t
- s,@PACKAGE@,$PACKAGE,;t t
- s,@VERSION@,$VERSION,;t t
- s,@ACLOCAL@,$ACLOCAL,;t t
-@@ -8230,6 +8286,7 @@
- s,@INSTALL_STRIP_PROGRAM@,$INSTALL_STRIP_PROGRAM,;t t
- s,@AWK@,$AWK,;t t
- s,@SET_MAKE@,$SET_MAKE,;t t
-+s,@am__leading_dot@,$am__leading_dot,;t t
- s,@CC@,$CC,;t t
- s,@CFLAGS@,$CFLAGS,;t t
- s,@LDFLAGS@,$LDFLAGS,;t t
-@@ -8244,6 +8301,8 @@
- s,@AMDEP_FALSE@,$AMDEP_FALSE,;t t
- s,@AMDEPBACKSLASH@,$AMDEPBACKSLASH,;t t
- s,@CCDEPMODE@,$CCDEPMODE,;t t
-+s,@am__fastdepCC_TRUE@,$am__fastdepCC_TRUE,;t t
-+s,@am__fastdepCC_FALSE@,$am__fastdepCC_FALSE,;t t
- s,@MKINSTALLDIRS@,$MKINSTALLDIRS,;t t
- s,@MSGFMT@,$MSGFMT,;t t
- s,@GMSGFMT@,$GMSGFMT,;t t
-@@ -8697,13 +8756,29 @@
-     cat $tmp/config.h
-     rm -f $tmp/config.h
-   fi
--  # Run the commands associated with the file.
--  case $ac_file in
--    config.h ) # update the timestamp
--echo 'timestamp for config.h:config.h.in' >"./stamp-h1"
-- ;;
-+# Compute $ac_file's index in $config_headers.
-+_am_stamp_count=1
-+for _am_header in $config_headers :; do
-+  case $_am_header in
-+    $ac_file | $ac_file:* )
-+      break ;;
-+    * )
-+      _am_stamp_count=`expr $_am_stamp_count + 1` ;;
-   esac
- done
-+echo "timestamp for $ac_file" >`(dirname $ac_file) 2>/dev/null ||
-+$as_expr X$ac_file : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-+         X$ac_file : 'X\(//\)[^/]' \| \
-+         X$ac_file : 'X\(//\)$' \| \
-+         X$ac_file : 'X\(/\)' \| \
-+         .     : '\(.\)' 2>/dev/null ||
-+echo X$ac_file |
-+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-+  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-+  	  /^X\(\/\/\)$/{ s//\1/; q; }
-+  	  /^X\(\/\).*/{ s//\1/; q; }
-+  	  s/.*/./; q'`/stamp-h$_am_stamp_count
-+done
- _ACEOF
- cat >>$CONFIG_STATUS <<\_ACEOF
- 
---- nano-1.2.1/Makefile.am~configure
-+++ nano-1.2.1/Makefile.am
-@@ -31,6 +31,6 @@
- SUBDIRS = po m4
- 
- localedir = $(datadir)/locale
--INCLUDES = -Iintl -DLOCALEDIR=\"$(localedir)\" -I@includedir@
-+INCLUDES = -Iintl -DLOCALEDIR=\"$(localedir)\"
- 
- ACLOCAL_AMFLAGS = -I m4
---- nano-1.2.1/Makefile.in~configure
-+++ nano-1.2.1/Makefile.in
-@@ -1,7 +1,7 @@
--# Makefile.in generated by automake 1.6.3 from Makefile.am.
-+# Makefile.in generated by automake 1.7.7 from Makefile.am.
- # @configure_input@
- 
--# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
-+# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
- # Free Software Foundation, Inc.
- # This Makefile.in is free software; the Free Software Foundation
- # gives unlimited permission to copy and/or distribute it,
-@@ -13,100 +13,124 @@
- # PARTICULAR PURPOSE.
- 
- @SET_MAKE@
--SHELL = @SHELL@
- 
- srcdir = @srcdir@
- top_srcdir = @top_srcdir@
- VPATH = @srcdir@
--prefix = @prefix@
--exec_prefix = @exec_prefix@
--
--bindir = @bindir@
--sbindir = @sbindir@
--libexecdir = @libexecdir@
--datadir = @datadir@
--sysconfdir = @sysconfdir@
--sharedstatedir = @sharedstatedir@
--localstatedir = @localstatedir@
--libdir = @libdir@
--infodir = @infodir@
--mandir = @mandir@
--includedir = @includedir@
--oldincludedir = /usr/include
- pkgdatadir = $(datadir)/@PACKAGE@
- pkglibdir = $(libdir)/@PACKAGE@
- pkgincludedir = $(includedir)/@PACKAGE@
- top_builddir = .
- 
--ACLOCAL = @ACLOCAL@
--AUTOCONF = @AUTOCONF@
--AUTOMAKE = @AUTOMAKE@
--AUTOHEADER = @AUTOHEADER@
--
- am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
- INSTALL = @INSTALL@
--INSTALL_PROGRAM = @INSTALL_PROGRAM@
--INSTALL_DATA = @INSTALL_DATA@
- install_sh_DATA = $(install_sh) -c -m 644
- install_sh_PROGRAM = $(install_sh) -c
- install_sh_SCRIPT = $(install_sh) -c
--INSTALL_SCRIPT = @INSTALL_SCRIPT@
- INSTALL_HEADER = $(INSTALL_DATA)
--transform = @program_transform_name@
-+transform = $(program_transform_name)
- NORMAL_INSTALL = :
- PRE_INSTALL = :
- POST_INSTALL = :
- NORMAL_UNINSTALL = :
- PRE_UNINSTALL = :
- POST_UNINSTALL = :
--host_alias = @host_alias@
- host_triplet = @host@
--
--EXEEXT = @EXEEXT@
--OBJEXT = @OBJEXT@
--PATH_SEPARATOR = @PATH_SEPARATOR@
-+ACLOCAL = @ACLOCAL@
-+AMDEP_FALSE = @AMDEP_FALSE@
-+AMDEP_TRUE = @AMDEP_TRUE@
- AMTAR = @AMTAR@
-+AUTOCONF = @AUTOCONF@
-+AUTOHEADER = @AUTOHEADER@
-+AUTOMAKE = @AUTOMAKE@
- AWK = @AWK@
--BUILD_INCLUDED_LIBINTL = @BUILD_INCLUDED_LIBINTL@
--CATOBJEXT = @CATOBJEXT@
- CC = @CC@
-+CCDEPMODE = @CCDEPMODE@
-+CFLAGS = @CFLAGS@
-+CPP = @CPP@
-+CPPFLAGS = @CPPFLAGS@
- CURSES_LIB = @CURSES_LIB@
--DATADIRNAME = @DATADIRNAME@
-+CYGPATH_W = @CYGPATH_W@
-+
-+DEFS = -DSYSCONFDIR=\"$(sysconfdir)\"
- DEPDIR = @DEPDIR@
--GENCAT = @GENCAT@
--GLIBC21 = @GLIBC21@
-+ECHO_C = @ECHO_C@
-+ECHO_N = @ECHO_N@
-+ECHO_T = @ECHO_T@
-+EGREP = @EGREP@
-+EXEEXT = @EXEEXT@
- GLIB_CFLAGS = @GLIB_CFLAGS@
- GLIB_CONFIG = @GLIB_CONFIG@
- GLIB_LIBS = @GLIB_LIBS@
- GMSGFMT = @GMSGFMT@
--HAVE_LIB = @HAVE_LIB@
-+INSTALL_DATA = @INSTALL_DATA@
-+INSTALL_PROGRAM = @INSTALL_PROGRAM@
-+INSTALL_SCRIPT = @INSTALL_SCRIPT@
- INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
--INSTOBJEXT = @INSTOBJEXT@
--INTLBISON = @INTLBISON@
- INTLLIBS = @INTLLIBS@
--INTLOBJS = @INTLOBJS@
--INTL_LIBTOOL_SUFFIX_PREFIX = @INTL_LIBTOOL_SUFFIX_PREFIX@
--LIB = @LIB@
-+LDFLAGS = @LDFLAGS@
- LIBICONV = @LIBICONV@
- LIBINTL = @LIBINTL@
--LTLIB = @LTLIB@
-+LIBOBJS = @LIBOBJS@
-+LIBS = @LIBS@
- LTLIBICONV = @LTLIBICONV@
- LTLIBINTL = @LTLIBINTL@
-+LTLIBOBJS = @LTLIBOBJS@
-+MAKEINFO = makeinfo --no-split
- MKINSTALLDIRS = @MKINSTALLDIRS@
-+MSGFMT = @MSGFMT@
-+MSGMERGE = @MSGMERGE@
-+OBJEXT = @OBJEXT@
- PACKAGE = @PACKAGE@
-+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
-+PACKAGE_NAME = @PACKAGE_NAME@
-+PACKAGE_STRING = @PACKAGE_STRING@
-+PACKAGE_TARNAME = @PACKAGE_TARNAME@
-+PACKAGE_VERSION = @PACKAGE_VERSION@
-+PATH_SEPARATOR = @PATH_SEPARATOR@
- POSUB = @POSUB@
--RANLIB = @RANLIB@
-+SET_MAKE = @SET_MAKE@
-+SHELL = @SHELL@
- STRIP = @STRIP@
--USE_INCLUDED_LIBINTL = @USE_INCLUDED_LIBINTL@
- USE_NLS = @USE_NLS@
- VERSION = @VERSION@
-+XGETTEXT = @XGETTEXT@
-+ac_ct_CC = @ac_ct_CC@
-+ac_ct_STRIP = @ac_ct_STRIP@
-+am__fastdepCC_FALSE = @am__fastdepCC_FALSE@
-+am__fastdepCC_TRUE = @am__fastdepCC_TRUE@
- am__include = @am__include@
-+am__leading_dot = @am__leading_dot@
- am__quote = @am__quote@
-+bindir = @bindir@
-+build = @build@
-+build_alias = @build_alias@
-+build_cpu = @build_cpu@
-+build_os = @build_os@
-+build_vendor = @build_vendor@
-+datadir = @datadir@
-+exec_prefix = @exec_prefix@
-+host = @host@
-+host_alias = @host_alias@
-+host_cpu = @host_cpu@
-+host_os = @host_os@
-+host_vendor = @host_vendor@
-+includedir = @includedir@
-+infodir = @infodir@
- install_sh = @install_sh@
-+libdir = @libdir@
-+libexecdir = @libexecdir@
-+localstatedir = @localstatedir@
-+mandir = @mandir@
-+oldincludedir = @oldincludedir@
-+prefix = @prefix@
-+program_transform_name = @program_transform_name@
-+sbindir = @sbindir@
-+sharedstatedir = @sharedstatedir@
-+sysconfdir = @sysconfdir@
-+target_alias = @target_alias@
- AUTOMAKE_OPTIONS = gnu no-dependencies
- 
--DEFS = -DSYSCONFDIR=\"$(sysconfdir)\"
--
- bin_PROGRAMS = nano
- nano_SOURCES = color.c \
- 		cut.c \
-@@ -126,7 +150,6 @@
- nano_LDADD = @GLIB_LIBS@ @LIBINTL@
- 
- info_TEXINFOS = nano.texi
--MAKEINFO = makeinfo --no-split
- 
- EXTRA_DIST = ABOUT-NLS AUTHORS BUGS COPYING ChangeLog INSTALL NEWS \
- 		README THANKS TODO UPGRADE config.rpath install-sh missing \
-@@ -137,7 +160,7 @@
- SUBDIRS = po m4
- 
- localedir = $(datadir)/locale
--INCLUDES = -Iintl -DLOCALEDIR=\"$(localedir)\" -I@includedir@
-+INCLUDES = -Iintl -DLOCALEDIR=\"$(localedir)\"
- 
- ACLOCAL_AMFLAGS = -I m4
- subdir = .
-@@ -154,34 +177,35 @@
- nano_OBJECTS = $(am_nano_OBJECTS)
- nano_DEPENDENCIES =
- nano_LDFLAGS =
-+
- DEFAULT_INCLUDES =  -I. -I$(srcdir) -I.
--CPPFLAGS = @CPPFLAGS@
--LDFLAGS = @LDFLAGS@
--LIBS = @LIBS@
- depcomp =
- am__depfiles_maybe =
- COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
- 	$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
- CCLD = $(CC)
- LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
--CFLAGS = @CFLAGS@
- DIST_SOURCES = $(nano_SOURCES)
-+am__TEXINFO_TEX_DIR = $(srcdir)
- INFO_DEPS = nano.info
- DVIS = nano.dvi
-+PDFS = nano.pdf
-+PSS = nano.ps
- TEXINFOS = nano.texi
- 
- NROFF = nroff
- MANS = $(man_MANS)
- 
--RECURSIVE_TARGETS = info-recursive dvi-recursive install-info-recursive \
--	uninstall-info-recursive all-recursive install-data-recursive \
--	install-exec-recursive installdirs-recursive install-recursive \
--	uninstall-recursive check-recursive installcheck-recursive
--DIST_COMMON = README ABOUT-NLS AUTHORS COPYING ChangeLog INSTALL \
--	Makefile.am Makefile.in NEWS THANKS TODO aclocal.m4 \
--	config.guess config.h.in config.rpath config.sub configure \
--	configure.ac install-sh missing mkinstalldirs nano.spec.in \
--	texinfo.tex
-+RECURSIVE_TARGETS = info-recursive dvi-recursive pdf-recursive \
-+	ps-recursive install-info-recursive uninstall-info-recursive \
-+	all-recursive install-data-recursive install-exec-recursive \
-+	installdirs-recursive install-recursive uninstall-recursive \
-+	check-recursive installcheck-recursive
-+DIST_COMMON = README $(srcdir)/Makefile.in $(srcdir)/configure \
-+	ABOUT-NLS AUTHORS COPYING ChangeLog INSTALL Makefile.am NEWS \
-+	THANKS TODO aclocal.m4 config.guess config.h.in config.rpath \
-+	config.sub configure configure.ac install-sh missing \
-+	mkinstalldirs nano.spec.in texinfo.tex
- DIST_SUBDIRS = $(SUBDIRS)
- SOURCES = $(nano_SOURCES)
- 
-@@ -189,7 +213,7 @@
- 	$(MAKE) $(AM_MAKEFLAGS) all-recursive
- 
- .SUFFIXES:
--.SUFFIXES: .c .dvi .info .o .obj .ps .texi
-+.SUFFIXES: .c .dvi .info .o .obj .pdf .ps .texi
- 
- am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
-  configure.lineno
-@@ -235,7 +259,7 @@
- 	  ; then \
- 	    f=`echo "$$p1" | sed 's,^.*/,,;$(transform);s/$$/$(EXEEXT)/'`; \
- 	   echo " $(INSTALL_PROGRAM_ENV) $(binPROGRAMS_INSTALL) $$p $(DESTDIR)$(bindir)/$$f"; \
--	   $(INSTALL_PROGRAM_ENV) $(binPROGRAMS_INSTALL) $$p $(DESTDIR)$(bindir)/$$f; \
-+	   $(INSTALL_PROGRAM_ENV) $(binPROGRAMS_INSTALL) $$p $(DESTDIR)$(bindir)/$$f || exit 1; \
- 	  else :; fi; \
- 	done
- 
-@@ -263,55 +287,58 @@
- 	$(COMPILE) -c `test -f '$<' || echo '$(srcdir)/'`$<
- 
- .c.obj:
--	$(COMPILE) -c `cygpath -w $<`
--
--nano.info: nano.texi
--nano.dvi: nano.texi
-+	$(COMPILE) -c `if test -f '$<'; then $(CYGPATH_W) '$<'; else $(CYGPATH_W) '$(srcdir)/$<'; fi`
- 
- .texi.info:
--	@cd $(srcdir) && rm -f $@ $@-[0-9] $@-[0-9][0-9]
--	cd $(srcdir) \
--	  && $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) \
--	       `echo $< | sed 's,.*/,,'`
-+	@rm -f $@ $@-[0-9] $@-[0-9][0-9] $(@:.info=).i[0-9] $(@:.info=).i[0-9][0-9]
-+	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
-+	 -o $@ `test -f '$<' || echo '$(srcdir)/'`$<
- 
- .texi.dvi:
--	TEXINPUTS="$(srcdir)$(PATH_SEPARATOR)$$TEXINPUTS" \
-+	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
- 	MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
--	$(TEXI2DVI) $<
-+	$(TEXI2DVI) `test -f '$<' || echo '$(srcdir)/'`$<
- 
--.texi:
--	@cd $(srcdir) && rm -f $@ $@-[0-9] $@-[0-9][0-9]
--	cd $(srcdir) \
--	  && $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) \
--	       `echo $< | sed 's,.*/,,'`
-+.texi.pdf:
-+	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
-+	MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
-+	$(TEXI2PDF) `test -f '$<' || echo '$(srcdir)/'`$<
-+nano.info: nano.texi 
-+nano.dvi: nano.texi 
-+nano.pdf: nano.texi 
- TEXI2DVI = texi2dvi
-+
-+TEXI2PDF = $(TEXI2DVI) --pdf --batch
- DVIPS = dvips
- .dvi.ps:
--	$(DVIPS) $< -o $@
-+	$(DVIPS) -o $@ $<
- 
- uninstall-info-am:
- 	$(PRE_UNINSTALL)
- 	@if (install-info --version && \
--	     install-info --version | fgrep -i -v debian) >/dev/null 2>&1; then \
-+	     install-info --version | grep -i -v debian) >/dev/null 2>&1; then \
- 	  list='$(INFO_DEPS)'; \
- 	  for file in $$list; do \
--	    echo " install-info --info-dir=$(DESTDIR)$(infodir) --remove $(DESTDIR)$(infodir)/$$file"; \
--	    install-info --info-dir=$(DESTDIR)$(infodir) --remove $(DESTDIR)$(infodir)/$$file; \
-+	    relfile=`echo "$$file" | sed 's|^.*/||'`; \
-+	    echo " install-info --info-dir=$(DESTDIR)$(infodir) --remove $(DESTDIR)$(infodir)/$$relfile"; \
-+	    install-info --info-dir=$(DESTDIR)$(infodir) --remove $(DESTDIR)$(infodir)/$$relfile; \
- 	  done; \
- 	else :; fi
- 	@$(NORMAL_UNINSTALL)
- 	@list='$(INFO_DEPS)'; \
- 	for file in $$list; do \
-+	  relfile=`echo "$$file" | sed 's|^.*/||'`; \
-+	  relfile_i=`echo "$$relfile" | sed 's|\.info$$||;s|$$|.i|'`; \
- 	  (if cd $(DESTDIR)$(infodir); then \
--	     echo " rm -f $$file $$file-[0-9] $$file-[0-9][0-9])"; \
--	     rm -f $$file $$file-[0-9] $$file-[0-9][0-9]; \
-+	     echo " rm -f $$relfile $$relfile-[0-9] $$relfile-[0-9][0-9] $$relfile_i[0-9] $$relfile_i[0-9][0-9])"; \
-+	     rm -f $$relfile $$relfile-[0-9] $$relfile-[0-9][0-9] $$relfile_i[0-9] $$relfile_i[0-9][0-9]; \
- 	   else :; fi); \
- 	done
- 
- dist-info: $(INFO_DEPS)
- 	list='$(INFO_DEPS)'; \
- 	for base in $$list; do \
--	  d=$(srcdir); \
-+	  if test -f $$base; then d=.; else d=$(srcdir); fi; \
- 	  for file in $$d/$$base*; do \
- 	    relfile=`expr "$$file" : "$$d/\(.*\)"`; \
- 	    test -f $(distdir)/$$relfile || \
-@@ -320,16 +347,15 @@
- 	done
- 
- mostlyclean-aminfo:
--	-rm -f nano.aux nano.cp nano.dvi nano.fn nano.ky nano.log nano.pg nano.ps \
--	  nano.tmp nano.toc nano.tp nano.vr
-+	-rm -f nano.aux nano.cp nano.cps nano.fn nano.fns nano.ky nano.kys nano.log \
-+	  nano.pg nano.pgs nano.tmp nano.toc nano.tp nano.tps nano.vr \
-+	  nano.vrs nano.dvi nano.pdf nano.ps
- 
- maintainer-clean-aminfo:
--	cd $(srcdir) && \
--	list='$(INFO_DEPS)'; for i in $$list; do \
--	  rm -f $$i; \
--	  if test "`echo $$i-[0-9]*`" != "$$i-[0-9]*"; then \
--	    rm -f $$i-[0-9]*; \
--	  fi; \
-+	@list='$(INFO_DEPS)'; for i in $$list; do \
-+	  i_i=`echo "$$i" | sed 's|\.info$$||;s|$$|.i|'`; \
-+	  echo " rm -f $$i $$i-[0-9] $$i-[0-9][0-9] $$i_i[0-9] $$i_i[0-9][0-9]"; \
-+	  rm -f $$i $$i-[0-9] $$i-[0-9][0-9] $$i_i[0-9] $$i_i[0-9][0-9]; \
- 	done
- 
- man1dir = $(mandir)/man1
-@@ -368,6 +394,10 @@
- 	done; \
- 	for i in $$list; do \
- 	  ext=`echo $$i | sed -e 's/^.*\\.//'`; \
-+	  case "$$ext" in \
-+	    1*) ;; \
-+	    *) ext='1' ;; \
-+	  esac; \
- 	  inst=`echo $$i | sed -e 's/\\.[0-9a-z]*$$//'`; \
- 	  inst=`echo $$inst | sed -e 's/^.*\///'`; \
- 	  inst=`echo $$inst | sed '$(transform)'`.$$ext; \
-@@ -411,6 +441,10 @@
- 	done; \
- 	for i in $$list; do \
- 	  ext=`echo $$i | sed -e 's/^.*\\.//'`; \
-+	  case "$$ext" in \
-+	    5*) ;; \
-+	    *) ext='5' ;; \
-+	  esac; \
- 	  inst=`echo $$i | sed -e 's/\\.[0-9a-z]*$$//'`; \
- 	  inst=`echo $$inst | sed -e 's/^.*\///'`; \
- 	  inst=`echo $$inst | sed '$(transform)'`.$$ext; \
-@@ -472,10 +506,17 @@
- 	list='$(SUBDIRS)'; for subdir in $$list; do \
- 	  test "$$subdir" = . || (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
- 	done
-+ctags-recursive:
-+	list='$(SUBDIRS)'; for subdir in $$list; do \
-+	  test "$$subdir" = . || (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
-+	done
- 
- ETAGS = etags
- ETAGSFLAGS =
- 
-+CTAGS = ctags
-+CTAGSFLAGS =
-+
- tags: TAGS
- 
- ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
-@@ -491,9 +532,15 @@
- 		$(TAGS_FILES) $(LISP)
- 	tags=; \
- 	here=`pwd`; \
-+	if (etags --etags-include --version) >/dev/null 2>&1; then \
-+	  include_option=--etags-include; \
-+	else \
-+	  include_option=--include; \
-+	fi; \
- 	list='$(SUBDIRS)'; for subdir in $$list; do \
- 	  if test "$$subdir" = .; then :; else \
--	    test -f $$subdir/TAGS && tags="$$tags -i $$here/$$subdir/TAGS"; \
-+	    test -f $$subdir/TAGS && \
-+	      tags="$$tags $$include_option=$$here/$$subdir/TAGS"; \
- 	  fi; \
- 	done; \
- 	list='$(SOURCES) $(HEADERS) config.h.in $(LISP) $(TAGS_FILES)'; \
-@@ -506,13 +553,28 @@
- 	  || $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
- 	     $$tags $$unique
- 
-+ctags: CTAGS
-+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) config.h.in $(TAGS_DEPENDENCIES) \
-+		$(TAGS_FILES) $(LISP)
-+	tags=; \
-+	here=`pwd`; \
-+	list='$(SOURCES) $(HEADERS) config.h.in $(LISP) $(TAGS_FILES)'; \
-+	unique=`for i in $$list; do \
-+	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
-+	  done | \
-+	  $(AWK) '    { files[$$0] = 1; } \
-+	       END { for (i in files) print i; }'`; \
-+	test -z "$(CTAGS_ARGS)$$tags$$unique" \
-+	  || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
-+	     $$tags $$unique
-+
- GTAGS:
- 	here=`$(am__cd) $(top_builddir) && pwd` \
- 	  && cd $(top_srcdir) \
- 	  && gtags -i $(GTAGS_ARGS) $$here
- 
- distclean-tags:
--	-rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH
-+	-rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
- DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
- 
- top_distdir = .
-@@ -524,13 +586,20 @@
-          && rm -fr $(distdir); }; }
- 
- GZIP_ENV = --best
-+distuninstallcheck_listfiles = find . -type f -print
- distcleancheck_listfiles = find . -type f -print
- 
- distdir: $(DISTFILES)
- 	$(am__remove_distdir)
- 	mkdir $(distdir)
- 	$(mkinstalldirs) $(distdir)/. $(distdir)/po
--	@list='$(DISTFILES)'; for file in $$list; do \
-+	@srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \
-+	topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \
-+	list='$(DISTFILES)'; for file in $$list; do \
-+	  case $$file in \
-+	    $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \
-+	    $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \
-+	  esac; \
- 	  if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
- 	  dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \
- 	  if test "$$dir" != "$$file" && test "$$dir" != "."; then \
-@@ -564,7 +633,7 @@
- 	  fi; \
- 	done
- 	$(MAKE) $(AM_MAKEFLAGS) \
--	  top_distdir="${top_distdir}" distdir="$(distdir)" \
-+	  top_distdir="$(top_distdir)" distdir="$(distdir)" \
- 	  dist-info
- 	-find $(distdir) -type d ! -perm -777 -exec chmod a+rwx {} \; -o \
- 	  ! -type d ! -perm -444 -links 1 -exec chmod a+r {} \; -o \
-@@ -586,13 +655,13 @@
- 	$(am__remove_distdir)
- 	GZIP=$(GZIP_ENV) gunzip -c $(distdir).tar.gz | $(AMTAR) xf -
- 	chmod -R a-w $(distdir); chmod a+w $(distdir)
--	mkdir $(distdir)/=build
--	mkdir $(distdir)/=inst
-+	mkdir $(distdir)/_build
-+	mkdir $(distdir)/_inst
- 	chmod a-w $(distdir)
--	dc_install_base=`$(am__cd) $(distdir)/=inst && pwd` \
--	  && cd $(distdir)/=build \
--	  && ../configure --srcdir=.. --prefix=$$dc_install_base \
--	    --with-included-gettext \
-+	dc_install_base=`$(am__cd) $(distdir)/_inst && pwd | sed -e 's,^[^:\\/]:[\\/],/,'` \
-+	  && dc_destdir="$${TMPDIR-/tmp}/am-dc-$$$$/" \
-+	  && cd $(distdir)/_build \
-+	  && ../configure --srcdir=.. --prefix="$$dc_install_base" \
- 	    $(DISTCHECK_CONFIGURE_FLAGS) \
- 	  && $(MAKE) $(AM_MAKEFLAGS) \
- 	  && $(MAKE) $(AM_MAKEFLAGS) dvi \
-@@ -600,23 +669,39 @@
- 	  && $(MAKE) $(AM_MAKEFLAGS) install \
- 	  && $(MAKE) $(AM_MAKEFLAGS) installcheck \
- 	  && $(MAKE) $(AM_MAKEFLAGS) uninstall \
--	  && (test `find $$dc_install_base -type f -print | wc -l` -le 1 \
--	      || { echo "ERROR: files left after uninstall:" ; \
--	           find $$dc_install_base -type f -print ; \
--	           exit 1; } >&2 ) \
-+	  && $(MAKE) $(AM_MAKEFLAGS) distuninstallcheck_dir="$$dc_install_base" \
-+	        distuninstallcheck \
-+	  && chmod -R a-w "$$dc_install_base" \
-+	  && ({ \
-+	       (cd ../.. && $(mkinstalldirs) "$$dc_destdir") \
-+	       && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" install \
-+	       && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" uninstall \
-+	       && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" \
-+	            distuninstallcheck_dir="$$dc_destdir" distuninstallcheck; \
-+	      } || { rm -rf "$$dc_destdir"; exit 1; }) \
-+	  && rm -rf "$$dc_destdir" \
- 	  && $(MAKE) $(AM_MAKEFLAGS) dist-gzip \
- 	  && rm -f $(distdir).tar.gz \
- 	  && $(MAKE) $(AM_MAKEFLAGS) distcleancheck
- 	$(am__remove_distdir)
- 	@echo "$(distdir).tar.gz is ready for distribution" | \
- 	  sed 'h;s/./=/g;p;x;p;x'
-+distuninstallcheck:
-+	@cd $(distuninstallcheck_dir) \
-+	&& test `$(distuninstallcheck_listfiles) | wc -l` -le 1 \
-+	   || { echo "ERROR: files left after uninstall:" ; \
-+	        if test -n "$(DESTDIR)"; then \
-+	          echo "  (check DESTDIR support)"; \
-+	        fi ; \
-+	        $(distuninstallcheck_listfiles) ; \
-+	        exit 1; } >&2
- distcleancheck: distclean
--	if test '$(srcdir)' = . ; then \
-+	@if test '$(srcdir)' = . ; then \
- 	  echo "ERROR: distcleancheck can only run from a VPATH build" ; \
- 	  exit 1 ; \
- 	fi
--	test `$(distcleancheck_listfiles) | wc -l` -eq 0 \
--	  || { echo "ERROR: files left after distclean:" ; \
-+	@test `$(distcleancheck_listfiles) | wc -l` -eq 0 \
-+	  || { echo "ERROR: files left in build directory after distclean:" ; \
- 	       $(distcleancheck_listfiles) ; \
- 	       exit 1; } >&2
- check-am: all-am
-@@ -645,7 +730,7 @@
- clean-generic:
- 
- distclean-generic:
--	-rm -f Makefile $(CONFIG_CLEAN_FILES)
-+	-rm -f $(CONFIG_CLEAN_FILES)
- 
- maintainer-clean-generic:
- 	@echo "This command is intended for maintainers to use"
-@@ -656,6 +741,8 @@
- 
- distclean: distclean-recursive
- 	-rm -f $(am__CONFIG_DISTCLEAN_FILES)
-+
-+	-rm -f Makefile
- distclean-am: clean-am distclean-compile distclean-generic distclean-hdr \
- 	distclean-tags
- 
-@@ -678,10 +765,12 @@
- 	$(mkinstalldirs) $(DESTDIR)$(infodir)
- 	@list='$(INFO_DEPS)'; \
- 	for file in $$list; do \
--	  d=$(srcdir); \
--	  for ifile in echo $$d/$$file $$d/$$file-[0-9] $$d/$$file-[0-9][0-9]; do \
-+	  if test -f $$file; then d=.; else d=$(srcdir); fi; \
-+	  file_i=`echo "$$file" | sed 's|\.info$$||;s|$$|.i|'`; \
-+	  for ifile in $$d/$$file $$d/$$file-[0-9] $$d/$$file-[0-9][0-9] \
-+                       $$d/$$file_i[0-9] $$d/$$file_i[0-9][0-9] ; do \
- 	    if test -f $$ifile; then \
--	      relfile=`expr "$$ifile" : "$$d/\(.*\)"`; \
-+	      relfile=`echo "$$ifile" | sed 's|^.*/||'`; \
- 	      echo " $(INSTALL_DATA) $$ifile $(DESTDIR)$(infodir)/$$relfile"; \
- 	      $(INSTALL_DATA) $$ifile $(DESTDIR)$(infodir)/$$relfile; \
- 	    else : ; fi; \
-@@ -689,11 +778,12 @@
- 	done
- 	@$(POST_INSTALL)
- 	@if (install-info --version && \
--	     install-info --version | fgrep -i -v debian) >/dev/null 2>&1; then \
-+	     install-info --version | grep -i -v debian) >/dev/null 2>&1; then \
- 	  list='$(INFO_DEPS)'; \
- 	  for file in $$list; do \
--	    echo " install-info --info-dir=$(DESTDIR)$(infodir) $(DESTDIR)$(infodir)/$$file";\
--	    install-info --info-dir=$(DESTDIR)$(infodir) $(DESTDIR)$(infodir)/$$file || :;\
-+	    relfile=`echo "$$file" | sed 's|^.*/||'`; \
-+	    echo " install-info --info-dir=$(DESTDIR)$(infodir) $(DESTDIR)$(infodir)/$$relfile";\
-+	    install-info --info-dir=$(DESTDIR)$(infodir) $(DESTDIR)$(infodir)/$$relfile || :;\
- 	  done; \
- 	else : ; fi
- install-man: install-man1 install-man5
-@@ -702,7 +792,9 @@
- 
- maintainer-clean: maintainer-clean-recursive
- 	-rm -f $(am__CONFIG_DISTCLEAN_FILES)
--	-rm -rf autom4te.cache
-+	-rm -rf $(top_srcdir)/autom4te.cache
-+
-+	-rm -f Makefile
- maintainer-clean-am: distclean-am maintainer-clean-aminfo \
- 	maintainer-clean-generic
- 
-@@ -711,29 +803,38 @@
- mostlyclean-am: mostlyclean-aminfo mostlyclean-compile \
- 	mostlyclean-generic
- 
-+pdf: pdf-recursive
-+
-+pdf-am: $(PDFS)
-+
-+ps: ps-recursive
-+
-+ps-am: $(PSS)
-+
- uninstall-am: uninstall-binPROGRAMS uninstall-info-am uninstall-man
- 
- uninstall-info: uninstall-info-recursive
- 
- uninstall-man: uninstall-man1 uninstall-man5
- 
--.PHONY: $(RECURSIVE_TARGETS) GTAGS all all-am check check-am clean \
--	clean-binPROGRAMS clean-generic clean-recursive dist dist-all \
--	dist-gzip dist-info distcheck distclean distclean-compile \
--	distclean-generic distclean-hdr distclean-recursive \
--	distclean-tags distcleancheck distdir dvi dvi-am dvi-recursive \
--	info info-am info-recursive install install-am \
--	install-binPROGRAMS install-data install-data-am \
--	install-data-recursive install-exec install-exec-am \
--	install-exec-recursive install-info install-info-am \
--	install-info-recursive install-man install-man1 install-man5 \
--	install-recursive install-strip installcheck installcheck-am \
--	installdirs installdirs-am installdirs-recursive \
--	maintainer-clean maintainer-clean-aminfo \
-+.PHONY: $(RECURSIVE_TARGETS) CTAGS GTAGS all all-am check check-am clean \
-+	clean-binPROGRAMS clean-generic clean-recursive ctags \
-+	ctags-recursive dist dist-all dist-gzip dist-info distcheck \
-+	distclean distclean-compile distclean-generic distclean-hdr \
-+	distclean-recursive distclean-tags distcleancheck distdir \
-+	distuninstallcheck dvi dvi-am dvi-recursive info info-am \
-+	info-recursive install install-am install-binPROGRAMS \
-+	install-data install-data-am install-data-recursive \
-+	install-exec install-exec-am install-exec-recursive \
-+	install-info install-info-am install-info-recursive install-man \
-+	install-man1 install-man5 install-recursive install-strip \
-+	installcheck installcheck-am installdirs installdirs-am \
-+	installdirs-recursive maintainer-clean maintainer-clean-aminfo \
- 	maintainer-clean-generic maintainer-clean-recursive mostlyclean \
- 	mostlyclean-aminfo mostlyclean-compile mostlyclean-generic \
--	mostlyclean-recursive tags tags-recursive uninstall \
--	uninstall-am uninstall-binPROGRAMS uninstall-info-am \
-+	mostlyclean-recursive pdf pdf-am pdf-recursive ps ps-am \
-+	ps-recursive tags tags-recursive uninstall uninstall-am \
-+	uninstall-binPROGRAMS uninstall-info-am \
- 	uninstall-info-recursive uninstall-man uninstall-man1 \
- 	uninstall-man5 uninstall-recursive
- 
diff --git a/packages/nano/nano-2.0.6/glib.m4 b/packages/nano/nano-2.0.6/glib.m4
deleted file mode 100644
index b8094bbfe0..0000000000
--- a/packages/nano/nano-2.0.6/glib.m4
+++ /dev/null
@@ -1,196 +0,0 @@
-# Configure paths for GLIB
-# Owen Taylor     97-11-3
-
-dnl AM_PATH_GLIB([MINIMUM-VERSION, [ACTION-IF-FOUND [, ACTION-IF-NOT-FOUND [, MODULES]]]])
-dnl Test for GLIB, and define GLIB_CFLAGS and GLIB_LIBS, if "gmodule" or 
-dnl gthread is specified in MODULES, pass to glib-config
-dnl
-AC_DEFUN(AM_PATH_GLIB,
-[dnl 
-dnl Get the cflags and libraries from the glib-config script
-dnl
-AC_ARG_WITH(glib-prefix,[  --with-glib-prefix=PFX   Prefix where GLIB is installed (optional)],
-            glib_config_prefix="$withval", glib_config_prefix="")
-AC_ARG_WITH(glib-exec-prefix,[  --with-glib-exec-prefix=PFX Exec prefix where GLIB is installed (optional)],
-            glib_config_exec_prefix="$withval", glib_config_exec_prefix="")
-AC_ARG_ENABLE(glibtest, [  --disable-glibtest       Do not try to compile and run a test GLIB program],
-		    , enable_glibtest=yes)
-
-  if test x$glib_config_exec_prefix != x ; then
-     glib_config_args="$glib_config_args --exec-prefix=$glib_config_exec_prefix"
-     if test x${GLIB_CONFIG+set} != xset ; then
-        GLIB_CONFIG=$glib_config_exec_prefix/bin/glib-config
-     fi
-  fi
-  if test x$glib_config_prefix != x ; then
-     glib_config_args="$glib_config_args --prefix=$glib_config_prefix"
-     if test x${GLIB_CONFIG+set} != xset ; then
-        GLIB_CONFIG=$glib_config_prefix/bin/glib-config
-     fi
-  fi
-
-  for module in . $4
-  do
-      case "$module" in
-         gmodule) 
-             glib_config_args="$glib_config_args gmodule"
-         ;;
-         gthread) 
-             glib_config_args="$glib_config_args gthread"
-         ;;
-      esac
-  done
-
-  AC_PATH_PROG(GLIB_CONFIG, glib-config, no)
-  min_glib_version=ifelse([$1], ,0.99.7,$1)
-  AC_MSG_CHECKING(for GLIB - version >= $min_glib_version)
-  no_glib=""
-  if test "$GLIB_CONFIG" = "no" ; then
-    no_glib=yes
-  else
-    GLIB_CFLAGS=`$GLIB_CONFIG $glib_config_args --cflags`
-    GLIB_LIBS=`$GLIB_CONFIG $glib_config_args --libs`
-    glib_config_major_version=`$GLIB_CONFIG $glib_config_args --version | \
-           sed 's/\([[0-9]]*\).\([[0-9]]*\).\([[0-9]]*\)/\1/'`
-    glib_config_minor_version=`$GLIB_CONFIG $glib_config_args --version | \
-           sed 's/\([[0-9]]*\).\([[0-9]]*\).\([[0-9]]*\)/\2/'`
-    glib_config_micro_version=`$GLIB_CONFIG $glib_config_args --version | \
-           sed 's/\([[0-9]]*\).\([[0-9]]*\).\([[0-9]]*\)/\3/'`
-    if test "x$enable_glibtest" = "xyes" ; then
-      ac_save_CFLAGS="$CFLAGS"
-      ac_save_LIBS="$LIBS"
-      CFLAGS="$CFLAGS $GLIB_CFLAGS"
-      LIBS="$GLIB_LIBS $LIBS"
-dnl
-dnl Now check if the installed GLIB is sufficiently new. (Also sanity
-dnl checks the results of glib-config to some extent
-dnl
-      rm -f conf.glibtest
-      AC_TRY_RUN([
-#include <glib.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-int 
-main ()
-{
-  int major, minor, micro;
-  char *tmp_version;
-
-  system ("touch conf.glibtest");
-
-  /* HP/UX 9 (%@#!) writes to sscanf strings */
-  tmp_version = g_strdup("$min_glib_version");
-  if (sscanf(tmp_version, "%d.%d.%d", &major, &minor, &micro) != 3) {
-     printf("%s, bad version string\n", "$min_glib_version");
-     exit(1);
-   }
-
-  if ((glib_major_version != $glib_config_major_version) ||
-      (glib_minor_version != $glib_config_minor_version) ||
-      (glib_micro_version != $glib_config_micro_version))
-    {
-      printf("\n*** 'glib-config --version' returned %d.%d.%d, but GLIB (%d.%d.%d)\n", 
-             $glib_config_major_version, $glib_config_minor_version, $glib_config_micro_version,
-             glib_major_version, glib_minor_version, glib_micro_version);
-      printf ("*** was found! If glib-config was correct, then it is best\n");
-      printf ("*** to remove the old version of GLIB. You may also be able to fix the error\n");
-      printf("*** by modifying your LD_LIBRARY_PATH enviroment variable, or by editing\n");
-      printf("*** /etc/ld.so.conf. Make sure you have run ldconfig if that is\n");
-      printf("*** required on your system.\n");
-      printf("*** If glib-config was wrong, set the environment variable GLIB_CONFIG\n");
-      printf("*** to point to the correct copy of glib-config, and remove the file config.cache\n");
-      printf("*** before re-running configure\n");
-    } 
-  else if ((glib_major_version != GLIB_MAJOR_VERSION) ||
-	   (glib_minor_version != GLIB_MINOR_VERSION) ||
-           (glib_micro_version != GLIB_MICRO_VERSION))
-    {
-      printf("*** GLIB header files (version %d.%d.%d) do not match\n",
-	     GLIB_MAJOR_VERSION, GLIB_MINOR_VERSION, GLIB_MICRO_VERSION);
-      printf("*** library (version %d.%d.%d)\n",
-	     glib_major_version, glib_minor_version, glib_micro_version);
-    }
-  else
-    {
-      if ((glib_major_version > major) ||
-        ((glib_major_version == major) && (glib_minor_version > minor)) ||
-        ((glib_major_version == major) && (glib_minor_version == minor) && (glib_micro_version >= micro)))
-      {
-        return 0;
-       }
-     else
-      {
-        printf("\n*** An old version of GLIB (%d.%d.%d) was found.\n",
-               glib_major_version, glib_minor_version, glib_micro_version);
-        printf("*** You need a version of GLIB newer than %d.%d.%d. The latest version of\n",
-	       major, minor, micro);
-        printf("*** GLIB is always available from ftp://ftp.gtk.org.\n");
-        printf("***\n");
-        printf("*** If you have already installed a sufficiently new version, this error\n");
-        printf("*** probably means that the wrong copy of the glib-config shell script is\n");
-        printf("*** being found. The easiest way to fix this is to remove the old version\n");
-        printf("*** of GLIB, but you can also set the GLIB_CONFIG environment to point to the\n");
-        printf("*** correct copy of glib-config. (In this case, you will have to\n");
-        printf("*** modify your LD_LIBRARY_PATH enviroment variable, or edit /etc/ld.so.conf\n");
-        printf("*** so that the correct libraries are found at run-time))\n");
-      }
-    }
-  return 1;
-}
-],, no_glib=yes,[echo $ac_n "cross compiling; assumed OK... $ac_c"])
-       CFLAGS="$ac_save_CFLAGS"
-       LIBS="$ac_save_LIBS"
-     fi
-  fi
-  if test "x$no_glib" = x ; then
-     AC_MSG_RESULT(yes)
-     ifelse([$2], , :, [$2])     
-  else
-     AC_MSG_RESULT(no)
-     if test "$GLIB_CONFIG" = "no" ; then
-       echo "*** The glib-config script installed by GLIB could not be found"
-       echo "*** If GLIB was installed in PREFIX, make sure PREFIX/bin is in"
-       echo "*** your path, or set the GLIB_CONFIG environment variable to the"
-       echo "*** full path to glib-config."
-     else
-       if test -f conf.glibtest ; then
-        :
-       else
-          echo "*** Could not run GLIB test program, checking why..."
-          CFLAGS="$CFLAGS $GLIB_CFLAGS"
-          LIBS="$LIBS $GLIB_LIBS"
-          AC_TRY_LINK([
-#include <glib.h>
-#include <stdio.h>
-],      [ return ((glib_major_version) || (glib_minor_version) || (glib_micro_version)); ],
-        [ echo "*** The test program compiled, but did not run. This usually means"
-          echo "*** that the run-time linker is not finding GLIB or finding the wrong"
-          echo "*** version of GLIB. If it is not finding GLIB, you'll need to set your"
-          echo "*** LD_LIBRARY_PATH environment variable, or edit /etc/ld.so.conf to point"
-          echo "*** to the installed location  Also, make sure you have run ldconfig if that"
-          echo "*** is required on your system"
-	  echo "***"
-          echo "*** If you have an old version installed, it is best to remove it, although"
-          echo "*** you may also be able to get things to work by modifying LD_LIBRARY_PATH"
-          echo "***"
-          echo "*** If you have a RedHat 5.0 system, you should remove the GTK package that"
-          echo "*** came with the system with the command"
-          echo "***"
-          echo "***    rpm --erase --nodeps gtk gtk-devel" ],
-        [ echo "*** The test program failed to compile or link. See the file config.log for the"
-          echo "*** exact error that occured. This usually means GLIB was incorrectly installed"
-          echo "*** or that you have moved GLIB since it was installed. In the latter case, you"
-          echo "*** may want to edit the glib-config script: $GLIB_CONFIG" ])
-          CFLAGS="$ac_save_CFLAGS"
-          LIBS="$ac_save_LIBS"
-       fi
-     fi
-     GLIB_CFLAGS=""
-     GLIB_LIBS=""
-     ifelse([$3], , :, [$3])
-  fi
-  AC_SUBST(GLIB_CFLAGS)
-  AC_SUBST(GLIB_LIBS)
-  rm -f conf.glibtest
-])
diff --git a/packages/nano/nano_1.2.1.bb b/packages/nano/nano_1.2.1.bb
deleted file mode 100644
index 1c3728096c..0000000000
--- a/packages/nano/nano_1.2.1.bb
+++ /dev/null
@@ -1,16 +0,0 @@
-DESCRIPTION = "GNU nano (Nano's ANOther editor, or \
-Not ANOther editor) is an enhanced clone of the \
-Pico text editor."
-LICENSE = "GPL"
-SECTION = "console/utils"
-DEPENDS = "ncurses"
-
-SRC_URI = "http://www.nano-editor.org/dist/v1.2/nano-${PV}.tar.gz \
-           file://configure.patch;patch=1 \
-           file://glib.m4"
-
-inherit autotools
-
-do_configure_prepend () {
-	install -m 0644 ${WORKDIR}/glib.m4 m4/
-}
diff --git a/packages/nano/nano_2.0.6.bb b/packages/nano/nano_2.0.7.bb
index f6ef365591..0951466b82 100644
--- a/packages/nano/nano_2.0.6.bb
+++ b/packages/nano/nano_2.0.7.bb
@@ -11,6 +11,9 @@ SRC_URI = "http://www.nano-editor.org/dist/v2.0/nano-${PV}.tar.gz \
 
 inherit autotools
 
+# only 16K more to get everything but the kitchen sink
+EXTRA_OECONF = "--enable-all"
+
 do_configure_prepend () {
 	install -m 0644 ${WORKDIR}/glib.m4 m4/
 }
diff --git a/packages/ncurses/ncurses-native_5.4.bb b/packages/ncurses/ncurses-native_5.4.bb
index 19e379a15c..95ca23f717 100644
--- a/packages/ncurses/ncurses-native_5.4.bb
+++ b/packages/ncurses/ncurses-native_5.4.bb
@@ -1,6 +1,14 @@
-SECTION = "libs"
 require ncurses_${PV}.bb
+
 inherit native
-EXTRA_OEMAKE = '"BUILD_CCFLAGS=${BUILD_CCFLAGS}"'
+
 DEPENDS = ""
+
+EXTRA_OEMAKE = '"BUILD_CCFLAGS=${BUILD_CCFLAGS}"'
+
 FILESPATH = "${FILE_DIRNAME}/local:${FILE_DIRNAME}/ncurses-${PV}-${PR}:${FILE_DIRNAME}/ncurses-${PV}:${FILE_DIRNAME}/ncurses:${FILE_DIRNAME}"
+
+do_install() {
+	:
+}
+
diff --git a/packages/ncurses/ncurses.inc b/packages/ncurses/ncurses.inc
index 2c6cfd05b0..9b4fff50ad 100644
--- a/packages/ncurses/ncurses.inc
+++ b/packages/ncurses/ncurses.inc
@@ -4,7 +4,6 @@ SECTION = "libs"
 LICENSE = "MIT"
 DEPENDS = "ncurses-native"
 RSUGGESTS_${PN} = "ncurses-terminfo"
-RPROVIDES = "libncurses5"
 
 inherit autotools
 
@@ -21,6 +20,7 @@ EXTRA_OECONF = "--with-shared \
 	        --without-cxx-binding \
 	        --with-terminfo-dirs=${sysconfdir}/terminfo:${datadir}/terminfo \
 	        --enable-overwrite"
+
 export BUILD_CCFLAGS = "-I${S}/ncurses -I${S}/include ${BUILD_CFLAGS}"
 export BUILD_LDFLAGS = ""
 export EXTRA_OEMAKE = '"BUILD_LDFLAGS=" "BUILD_CCFLAGS=${BUILD_CCFLAGS}"'
@@ -80,11 +80,29 @@ pkg_prerm_ncurses-tools () {
 	update-alternatives --remove reset reset.${PN}
 }
 
-PACKAGES_prepend = "ncurses-tools "
-PACKAGES_append = " ncurses-terminfo"
-FILES_ncurses_append = " ${datadir}/tabset"
-# This keeps only tput/tset in ncurses
-# clear/reset are in already busybox
-FILES_ncurses-tools = "${bindir}/tic ${bindir}/toe ${bindir}/infotocap ${bindir}/captoinfo ${bindir}/infocmp ${bindir}/clear.${PN} ${bindir}/reset.${PN} ${bindir}/tack "
-FILES_ncurses-terminfo = "${datadir}/terminfo"
-FILES_${PN} = "${bindir}/tput ${bindir}/tset ${libdir}/lib*.so.* §{datadir}/tabset ${sysconfdir}/terminfo"
+
+PACKAGES =+ "${PN}-ncurses ${PN}-panel ${PN}-menu ${PN}-form ${PN}-terminfo ${PN}-tools"
+FILES_${PN}-ncurses = "${libdir}/libncurses.so.*"
+FILES_${PN}-panel = "${libdir}/libpanel.so.*"
+FILES_${PN}-menu = "${libdir}/libmenu.so.*"
+FILES_${PN}-form = "${libdir}/libform.so.*"
+FILES_${PN}-terminfo = "\
+  ${libdir}/terminfo \
+  ${datadir}/terminfo \
+"
+FILES_${PN}-tools = "\
+  ${bindir}/tic \
+  ${bindir}/tack \
+  ${bindir}/toe \
+  ${bindir}/infotocap \
+  ${bindir}/captoinfo \
+  ${bindir}/infocmp \
+  ${bindir}/clear.${PN} \
+  ${bindir}/reset.${PN} \
+"
+FILES_${PN} = "\
+  ${bindir}/tput \
+  ${bindir}/tset \
+  ${datadir}/tabset \
+  ${sysconfdir}/terminfo \
+"
diff --git a/packages/ncurses/ncurses_5.3.bb b/packages/ncurses/ncurses_5.3.bb
deleted file mode 100644
index 0b0897a409..0000000000
--- a/packages/ncurses/ncurses_5.3.bb
+++ /dev/null
@@ -1,11 +0,0 @@
-BaseV := "${PV}"
-SnapV := "20030906"
-PV = "${BaseV}.${SnapV}"
-PR = "r2"
-
-SRC_URI = "${GNU_MIRROR}/ncurses/ncurses-${BaseV}.tar.gz \
-	   file://${SnapV}.patch;patch=1 \
-	   file://configure.patch;patch=1"
-S = "${WORKDIR}/ncurses-${BaseV}"
-
-require ncurses.inc
diff --git a/packages/ncurses/ncurses_5.4.bb b/packages/ncurses/ncurses_5.4.bb
index f361d745b3..00dd7d1d1a 100644
--- a/packages/ncurses/ncurses_5.4.bb
+++ b/packages/ncurses/ncurses_5.4.bb
@@ -1,7 +1,7 @@
-PR = "r11"
+PR = "r13"
 
 SRC_URI = "${GNU_MIRROR}/ncurses/ncurses-${PV}.tar.gz \
-	   file://visibility.patch;patch=1"
+           file://visibility.patch;patch=1"
 S = "${WORKDIR}/ncurses-${PV}"
 
 require ncurses.inc
diff --git a/packages/pv/.mtn2git_empty b/packages/pv/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/pv/.mtn2git_empty
diff --git a/packages/pv/pv_1.1.4.bb b/packages/pv/pv_1.1.4.bb
new file mode 100644
index 0000000000..199b7dfa28
--- /dev/null
+++ b/packages/pv/pv_1.1.4.bb
@@ -0,0 +1,11 @@
+DESCRIPTION = "Pipe Viewer is a terminal-based tool for monitoring the progress of data through a pipeline."
+SECTION = "console/utils"
+HOMEPAGE = "http://www.ivarch.com/programs/pv.shtml"
+LICENSE = "Artistic License 2.0"
+
+inherit autotools
+
+SRC_URI = "http://pipeviewer.googlecode.com/files/pv-${PV}.tar.bz2"
+
+
+EXTRA_OEMAKE = "LD='${LD}'"
diff --git a/packages/pwgen/.mtn2git_empty b/packages/pwgen/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/pwgen/.mtn2git_empty
diff --git a/packages/pwgen/pwgen_2.06.bb b/packages/pwgen/pwgen_2.06.bb
new file mode 100644
index 0000000000..8fe419babb
--- /dev/null
+++ b/packages/pwgen/pwgen_2.06.bb
@@ -0,0 +1,7 @@
+DESCRIPTION = "Password generator which creates passwords which can be easily memorized by a human"
+HOMEPAGE = "http://sf.net/projects/pwgen/"
+LICENSE = "GPL"
+
+SRC_URI = "${SOURCEFORGE_MIRROR}/pwgen/pwgen-${PV}.tar.gz"
+
+inherit autotools
diff --git a/packages/python/python-lightmediascanner_svn.bb b/packages/python/python-lightmediascanner_svn.bb
index 27d0bb62f1..003b718d4b 100644
--- a/packages/python/python-lightmediascanner_svn.bb
+++ b/packages/python/python-lightmediascanner_svn.bb
@@ -3,7 +3,7 @@ SECTION = "devel/python"
 HOMEPAGE = "http://lms.garage.maemo.org/"
 AUTHOR = "Gustavo Barbieri"
 LICENSE = "LGPL"
-DEPENDS = "lightmediascanner"
+DEPENDS = "lightmediascanner python-cython-native"
 PV = "0.1.0+svn${SRCREV}"
 
 SRC_URI = "svn://garage.maemo.org/svn/lms/;module=python-lightmediascanner;proto=https"
diff --git a/packages/qt4/qt4-x11-free.inc b/packages/qt4/qt4-x11-free.inc
index 2650433ec8..60c266bc73 100644
--- a/packages/qt4/qt4-x11-free.inc
+++ b/packages/qt4/qt4-x11-free.inc
@@ -5,7 +5,7 @@ HOMEPAGE = "http://www.trolltech.com"
 LICENSE = "GPL QPL"
 DEPENDS += "virtual/libx11 fontconfig xft libxext libxrender libxrandr libxcursor"
 PROVIDES = "qt4x11"
-PR = "r7"
+PR = "r9"
 
 SRC_URI = "ftp://ftp.trolltech.com/qt/source/qt-x11-opensource-src-${PV}.tar.gz \
            file://0001-cross-compile.patch;patch=1 \
diff --git a/packages/qt4/qt_packaging.inc b/packages/qt4/qt_packaging.inc
index ba2a037f59..1b4faf97d2 100644
--- a/packages/qt4/qt_packaging.inc
+++ b/packages/qt4/qt_packaging.inc
@@ -177,6 +177,15 @@ do_install() {
     rm -rf ${D}/${bindir}/${QT_DIR_NAME}
     rm -rf ${D}/${datadir}/${QT_DIR_NAME}/mkspecs
 
+    # fix some .la and .pc files
+    sed -i s#"moc_location=${STAGING_BINDIR}/moc4$"#"moc_location=${bindir}/moc4"# ${D}/${libdir}/pkgconfig/Qt*.pc
+    sed -i s#"uic_location=${STAGING_BINDIR}/uic4$"#"uic_location=${bindir}/uic4"# ${D}/${libdir}/pkgconfig/Qt*.pc
+    sed -i s#'$(OE_QMAKE_LIBS_X11)'#"${OE_QMAKE_LIBS_X11}"#g ${D}/${libdir}/pkgconfig/Qt*.pc
+    sed -i s#-L${STAGING_LIBDIR}##g ${D}${libdir}/pkgconfig/Qt*.pc
+
+    sed -i s#-L${STAGING_LIBDIR}#-L${libdir}#g ${D}${libdir}/libQt*.la
+    sed -i s#'$(OE_QMAKE_LIBS_X11)'#"${OE_QMAKE_LIBS_X11}"#g ${D}/${libdir}/libQt*.la
+
     install -d ${D}/${libdir}/fonts
     touch ${D}/${libdir}/fonts/fontdir
 }
diff --git a/packages/qt4/qt_staging.inc b/packages/qt4/qt_staging.inc
index 9aa309d3af..1c3d69c1af 100644
--- a/packages/qt4/qt_staging.inc
+++ b/packages/qt4/qt_staging.inc
@@ -2,11 +2,12 @@
 do_stage_append() {
     cd ${STAGING_LIBDIR}/pkgconfig
     sed -i s#"-L${S}/lib"##g Qt*.pc
-    sed -i s#"moc_location=${S}/bin/moc"#moc_location=${STAGING_BINDIR}/moc4# Qt*.pc
-    sed -i s#"uic_location=${S}/bin/uic"#uic_location=${STAGING_BINDIR}/uic4# Qt*.pc
-    sed -i s#libdir=\$\{prefix\}/lib#libdir=\$\{prefix\}/lib/${QT_DIR_NAME}#g Qt*.pc 
+    sed -i s#"moc_location=${STAGING_BINDIR}/moc4$"## Qt*.pc
+    sed -i s#"uic_location=${STAGING_BINDIR}/uic4$"## Qt*.pc
+    sed -i s#"-L${STAGING_LIBDIR}"##g Qt*.pc
+    sed -i s#'$(OE_QMAKE_LIBS_X11)'#"${OE_QMAKE_LIBS_X11}"#g Qt*.pc
 
-    cd ${STAGING_LIBDIR}/${QT_DIR_NAME}
+    cd ${STAGING_LIBDIR}
     sed -i s#"-L${S}/lib"##g libQt*.la
 }
 
@@ -17,23 +18,27 @@ do_stage() {
     oe_runmake install INSTALL_ROOT=${STAGE_TEMP}
 
     install -d ${STAGING_INCDIR}/
-    install -d ${STAGING_LIBDIR}/${QT_DIR_NAME}
+    install -d ${STAGING_LIBDIR}
     cp -pPRf ${STAGE_TEMP}/$includedir/* ${STAGING_INCDIR}/
 
     for i in ${STAGE_TEMP}/${libdir}/*.la
     do
         sed -i s,installed=yes,installed=no, $i
-        cp -fpPR $i ${STAGING_LIBDIR}/${QT_DIR_NAME}/
-        cp -fpPR ${STAGE_TEMP}/${libdir}/$(basename $i .la).prl ${STAGING_LIBDIR}/${QT_DIR_NAME}
-        oe_libinstall -C ${STAGE_TEMP}/${libdir} -so $(basename $i .la) ${STAGING_LIBDIR}/${QT_DIR_NAME}
+        sed -i -e "/^dependency_libs=/s,-L${libdir},-L${STAGING_LIBDIR},g" $i
+        sed -i -e "s,-L${libdir},-L${STAGING_LIBDIR},g" ${STAGE_TEMP}/${libdir}/$(basename $i .la).prl
+        cp -fpPR $i ${STAGING_LIBDIR}
+        cp -fpPR ${STAGE_TEMP}/${libdir}/$(basename $i .la).prl ${STAGING_LIBDIR}
+        oe_libinstall -C ${STAGE_TEMP}/${libdir} -so $(basename $i .la) ${STAGING_LIBDIR}
     done
 
     for i in libQtAssistantClient${QT_LIBINFIX} libQtDesignerComponents${QT_LIBINFIX} libQtUiTools${QT_LIBINFIX} libQtUiTools${QT_LIBINFIX} libQtDesigner${QT_LIBINFIX}
     do
-        cp ${STAGE_TEMP}/${libdir}/$i.prl ${STAGING_LIBDIR}/${QT_DIR_NAME} || true
-        cp ${STAGE_TEMP}/${libdir}/$i.la  ${STAGING_LIBDIR}/${QT_DIR_NAME} || true
-        oe_libinstall -C ${STAGE_TEMP}/${libdir} -so $i ${STAGING_LIBDIR}/${QT_DIR_NAME} || true
-        oe_libinstall -C ${STAGE_TEMP}/${libdir} -a $i ${STAGING_LIBDIR}/${QT_DIR_NAME} || true
+        sed -i -e "s,-L${libdir},-L${STAGING_LIBDIR},g" $i.prl || true
+        cp ${STAGE_TEMP}/${libdir}/$i.prl ${STAGING_LIBDIR} || true
+        sed -i -e "/^dependency_libs=/s,-L${libdir},-L${STAGING_LIBDIR},g" $i.la || true
+        cp ${STAGE_TEMP}/${libdir}/$i.la  ${STAGING_LIBDIR} || true
+        oe_libinstall -C ${STAGE_TEMP}/${libdir} -so $i ${STAGING_LIBDIR} || true
+        oe_libinstall -C ${STAGE_TEMP}/${libdir} -a $i ${STAGING_LIBDIR} || true
     done
 
     rm -rf ${STAGE_TEMP}
diff --git a/packages/qt4/qtopia-core.inc b/packages/qt4/qtopia-core.inc
index 46bec73cd8..eab7e1b3e1 100644
--- a/packages/qt4/qtopia-core.inc
+++ b/packages/qt4/qtopia-core.inc
@@ -4,7 +4,7 @@ LICENSE = "GPL"
 PRIORITY = "optional"
 HOMEPAGE = "http://www.trolltech.com"
 DEPENDS += "tslib"
-PR = "r1"
+PR = "r3"
 
 SRC_URI = "ftp://ftp.trolltech.com/qt/source/qtopia-core-opensource-src-${PV}.tar.gz \
            file://qconfig-oe.h \
diff --git a/packages/speech-dispatcher/files/configure_fix.patch b/packages/speech-dispatcher/files/configure_fix.patch
new file mode 100644
index 0000000000..19feabf379
--- /dev/null
+++ b/packages/speech-dispatcher/files/configure_fix.patch
@@ -0,0 +1,46 @@
+Index: speech-dispatcher-0.6.5/configure.in
+===================================================================
+--- speech-dispatcher-0.6.5.orig/configure.in	2008-03-10 23:11:42.000000000 +0000
++++ speech-dispatcher-0.6.5/configure.in	2008-03-10 23:14:02.000000000 +0000
+@@ -134,12 +134,15 @@
+ AC_SUBST(ibmtts_include)
+ 
+ dnl check for espeak support
++AC_LANG_PUSH([C++])
+ AC_CHECK_LIB(espeak,
+ espeak_Initialize,
+ 		espeak_ok="true"; echo "Compiling with espeak support.",
+ 		espeak_ok="false"; echo "Espeak not found.",
+          	-lpthread -lm)
+ 
++AC_LANG_POP([C++])
++
+ AC_ARG_WITH(espeak, AS_HELP_STRING(--with-espeak, Compile with espeak support),
+ 		 if test $withval = "no"; then 
+ 		    echo "Forced compilation without espeak support."; 
+Index: speech-dispatcher-0.6.5/src/modules/Makefile.am
+===================================================================
+--- speech-dispatcher-0.6.5.orig/src/modules/Makefile.am	2008-03-10 23:18:50.000000000 +0000
++++ speech-dispatcher-0.6.5/src/modules/Makefile.am	2008-03-10 23:25:39.000000000 +0000
+@@ -8,6 +8,7 @@
+ EXTRA_DIST = module_main.c module_utils_addvoice.c festival_client.c festival_client.h
+ 
+ AM_CFLAGS = -Wall -DLOCALEDIR=\"$(localedir)\" $(inc_local) @glib_include@ -L$(top_srcdir)/src/audio -I$(top_srcdir)/src/audio -I../../intl/ $(ibmtts_include) @SNDFILE_CFLAGS@ -Wl,--rpath -Wl,$(spdlibdir)
++AM_CXXFLAGS = -Wall -DLOCALEDIR=\"$(localedir)\" $(inc_local) @glib_include@ -L$(top_srcdir)/src/audio -I$(top_srcdir)/src/audio -I../../intl/ $(ibmtts_include) @SNDFILE_CFLAGS@ -Wl,--rpath -Wl,$(spdlibdir)
+ 
+ if flite_support
+ if ibmtts_support
+@@ -45,6 +46,6 @@
+ sd_cicero_SOURCES = cicero.c module_utils.c module_utils.h
+ sd_cicero_LDADD = -lm -lpthread -ldotconf @glib_libs@
+ 
+-sd_espeak_SOURCES = espeak.c module_utils.c module_utils.h
++sd_espeak_SOURCES = espeak.c module_utils.c module_utils.h dummy.cpp
+ sd_espeak_LDFLAGS = -rpath '$(spdlibdir)'
+ sd_espeak_LDADD = -lsdaudio -lm -lespeak -lpthread -ldotconf @SNDFILE_LIBS@ @gthread_libs@
+Index: speech-dispatcher-0.6.5/src/modules/dummy.cpp
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ speech-dispatcher-0.6.5/src/modules/dummy.cpp	2008-03-10 23:26:50.000000000 +0000
+@@ -0,0 +1 @@
++
diff --git a/packages/speech-dispatcher/speech-dispatcher_0.6.5.bb b/packages/speech-dispatcher/speech-dispatcher_0.6.5.bb
index 3857a1577a..7b8ba73750 100644
--- a/packages/speech-dispatcher/speech-dispatcher_0.6.5.bb
+++ b/packages/speech-dispatcher/speech-dispatcher_0.6.5.bb
@@ -5,13 +5,14 @@ LICENSE = "GPLv2"
 DEPENDS = "espeak flite pulseaudio libdotconf glib-2.0"
 RPROVIDES_${PN} += "speechd"
 
-PR = "r7"
+PR = "r8"
 
 inherit autotools update-rc.d
 
 SRC_URI = "http://www.freebsoft.org/pub/projects/speechd/${PN}-${PV}.tar.gz \
 	   file://speech-dispatcher.init \
            file://srcMakefile.am.patch;patch=1 \
+           file://configure_fix.patch;patch=1 \
 	   file://configSpeechd.conf.in_00.patch;patch=1"
 
 LEAD_SONAME = "libspeechd.so"
diff --git a/packages/starling/starling_0.1.bb b/packages/starling/starling_0.1.bb
deleted file mode 100644
index fab79342ac..0000000000
--- a/packages/starling/starling_0.1.bb
+++ /dev/null
@@ -1,22 +0,0 @@
-LICENSE = "GPL"
-SECTION = "gpe/multimedia"
-PRIORITY = "optional"
-PR = "r1"
-
-inherit gpe autotools
-
-DESCRIPTION = "Starling audio player for GPE"
-DEPENDS = "gtk+ libgpewidget gstreamer gst-plugins-good gst-plugins-bad esound sqlite3 libsoup"
-RDEPENDS = "esd \
-	gst-plugin-audioconvert \
-	gst-plugin-esd \
-	gst-plugin-typefindfunctions \
-        gst-plugin-decodebin \
-	gst-plugin-volume"
-
-RRECOMMENDS = "gst-plugin-mad \
-	gst-plugin-modplug \
-	gst-plugin-ivorbis \
-	gst-plugin-tcp"
-
-SRC_URI = "http://handhelds.org/~skyhusker/${P}.tar.bz2"
diff --git a/packages/starling/starling_0.2.bb b/packages/starling/starling_0.2.bb
deleted file mode 100644
index 32cd1b9025..0000000000
--- a/packages/starling/starling_0.2.bb
+++ /dev/null
@@ -1,21 +0,0 @@
-DESCRIPTION = "Starling audio player for GPE"
-SECTION = "gpe/multimedia"
-PRIORITY = "optional"
-LICENSE = "GPL"
-DEPENDS = "gtk+ gstreamer gst-plugins-good gst-plugins-bad sqlite libsoup gnutls"
-
-RDEPENDS = "esd \
-        gst-plugin-audioconvert \
-        gst-plugin-esd \
-        gst-plugin-typefindfunctions \
-        gst-plugin-decodebin \
-        gst-plugin-volume"
-RRECOMMENDS = "gst-plugin-mad \
-        gst-plugin-modplug \
-        gst-plugin-ivorbis \
-        gst-plugin-tcp"
-
-GPE_TARBALL_SUFFIX = "bz2"
-
-inherit gpe autotools
-
diff --git a/packages/starling/starling_svn.bb b/packages/starling/starling_svn.bb
index 67d98dbd60..7969cd84f0 100644
--- a/packages/starling/starling_svn.bb
+++ b/packages/starling/starling_svn.bb
@@ -2,7 +2,7 @@ DESCRIPTION = "Starling audio player for GPE"
 SECTION = "gpe/multimedia"
 PRIORITY = "optional"
 LICENSE = "GPL"
-DEPENDS = "gtk+ libgpewidget gstreamer gst-plugins-good gst-plugins-bad esound sqlite3 libsoup"
+DEPENDS = "gtk+ gstreamer gst-plugins-good gst-plugins-bad esound sqlite libsoup"
 RDEPENDS = "esd \
         gst-plugin-audioconvert \
         gst-plugin-esd \
diff --git a/packages/subversion/subversion_1.4.5.bb b/packages/subversion/subversion_1.4.5.bb
index 5c15d67daf..d4f290590f 100644
--- a/packages/subversion/subversion_1.4.5.bb
+++ b/packages/subversion/subversion_1.4.5.bb
@@ -21,12 +21,7 @@ inherit autotools
 
 export LDFLAGS += " -L${STAGING_LIBDIR} "
 
-do_configure() {
-	gnu-configize
-	libtoolize --force
-	aclocal -I build/ -I build/ac-macros/ && autoconf
-	oe_runconf
-}
+acpaths = "-I build/ -I build/ac-macros/"
 
 do_stage() {
 	autotools_stage_all
diff --git a/packages/uclibc/uclibc-0.9.29/uClibc-0.9.29-nonposix_bashisms.patch b/packages/uclibc/uclibc-0.9.29/uClibc-0.9.29-nonposix_bashisms.patch
new file mode 100644
index 0000000000..b9294b5471
--- /dev/null
+++ b/packages/uclibc/uclibc-0.9.29/uClibc-0.9.29-nonposix_bashisms.patch
@@ -0,0 +1,13 @@
+Index: uClibc-0.9.29/extra/config/lxdialog/check-lxdialog.sh
+===================================================================
+--- uClibc-0.9.29.orig/extra/config/lxdialog/check-lxdialog.sh	2008-03-09 21:58:29.000000000 +0100
++++ uClibc-0.9.29/extra/config/lxdialog/check-lxdialog.sh	2008-03-09 21:58:39.000000000 +0100
+@@ -57,7 +57,7 @@
+ 	printf "Usage: $0 [-check compiler options|-header|-library]\n"
+ }
+ 
+-if [ $# == 0 ]; then
++if [ $# -eq 0 ]; then
+ 	usage
+ 	exit 1
+ fi
diff --git a/packages/uclibc/uclibc_0.9.29.bb b/packages/uclibc/uclibc_0.9.29.bb
index 9051029cdf..08eac1b7f0 100644
--- a/packages/uclibc/uclibc_0.9.29.bb
+++ b/packages/uclibc/uclibc_0.9.29.bb
@@ -7,7 +7,7 @@
 # on whether the base patches apply to the selected (SRCDATE) svn release.
 #
 UCLIBC_BASE ?= "0.9.29"
-PR = "r9"
+PR = "r11"
 
 require uclibc.inc
 
@@ -23,7 +23,8 @@ SRC_URI += "file://uClibc.machine file://uClibc.distro \
 	    file://uClibc-0.9.29-fix-gethostent_r-failure-retval.patch;patch=1 \
 	    file://uClibc-0.9.29-fix-internal_function-definition.patch;patch=1 \
 	    file://uClibc-0.9.29-rm-whitespace.patch;patch=1 \
-	    "
+	    file://uClibc-0.9.29-nonposix_bashisms.patch;patch=1 \
+"
 
 # mmap-unsigned-shift_bugid1303.patch
 # http://uclibc.org/lists/uclibc-cvs/2007-May/011360.html;patch=1"
diff --git a/packages/wireless-tools/wireless-tools_29.bb b/packages/wireless-tools/wireless-tools_29.bb
new file mode 100644
index 0000000000..7f08db81c7
--- /dev/null
+++ b/packages/wireless-tools/wireless-tools_29.bb
@@ -0,0 +1,3 @@
+require wireless-tools.inc
+
+PR = "r0"
author	Paul Sokolovsky <pmiscml@gmail.com>	2008-03-11 13:48:44 +0000
committer	Paul Sokolovsky <pmiscml@gmail.com>	2008-03-11 13:48:44 +0000
commit	7e8dbb134a4c8488fe533b8611528637930e0a02 (patch)
tree	6408bb8eb701cc38d96deef0090cdbbd831b6c21 /packages
parent	84c5f5d53e3417913c75df26cf33678efe0a148e (diff)
parent	6b6cf4dab96836c4c814ffc79a05fc12ff113a62 (diff)
download	openembedded-7e8dbb134a4c8488fe533b8611528637930e0a02.tar.gz