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| author |   Koen Kooi <k-kooi@ti.com> | 2010-04-06 11:22:31 +0200 |
|---|---|---|
| committer |   Koen Kooi <koen@openembedded.org> | 2010-04-12 19:43:31 +0200 |
| commit | 63348ff7b88c6f64e8dd518a21384e33e0d828f3 (patch) | |
| tree | 57113d4d25ca01b5a5d57855c2a1e1e1fc66509c /recipes/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch | |
| parent | f8cb152e6b9f25332cfc7fd433a584ea5d685c4b (diff) | |
| download | openembedded-63348ff7b88c6f64e8dd518a21384e33e0d828f3.tar.gz | |
linux-omap-psp 2.6.32: add patches from Mans Rullgard to help finding the DM37xx slowdown
Diffstat (limited to 'recipes/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch')
| -rw-r--r-- | recipes/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/recipes/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch b/recipes/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch new file mode 100644 index 0000000000..7fcb5fe082 --- /dev/null +++ b/recipes/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch @@ -0,0 +1,49 @@ +From c6faecfc5916cce9ff104982e7b3ab4b990400bf Mon Sep 17 00:00:00 2001 +From: Mans Rullgard <mans@mansr.com> +Date: Tue, 10 Nov 2009 00:52:56 +0000 +Subject: [PATCH 40/42] ARM: Add option to allow userspace access to performance counters + +This adds an option to allow userspace access to the performance monitor +registers of the Cortex-A8. + +Signed-off-by: Mans Rullgard <mans@mansr.com> +--- + arch/arm/mm/Kconfig | 7 +++++++ + arch/arm/mm/proc-v7.S | 6 ++++++ + 2 files changed, 13 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig +index 564ff7d..fda2e68 100644 +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -793,3 +793,10 @@ config USER_L2_PLE + help + Enable userspace access to the L2 preload engine (PLE) available + in Cortex-A series ARM processors. ++ ++config USER_PMON ++ bool "Enable userspace access to performance counters" ++ depends on CPU_V7 ++ default n ++ help ++ Enable userpsace access to the performance monitor registers. +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +index 3a28521..fec926a 100644 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -270,6 +270,12 @@ __v7_setup: + mcr p15, 0, r5, c10, c2, 0 @ write PRRR + mcr p15, 0, r6, c10, c2, 1 @ write NMRR + #endif ++ ++#ifdef CONFIG_USER_PMON ++ mov r0, #1 ++ mcr p15, 0, r0, c9, c14, 0 ++#endif ++ + adr r5, v7_crval + ldmia r5, {r5, r6} + #ifdef CONFIG_CPU_ENDIAN_BE8 +-- +1.6.6.1 + |