aboutsummaryrefslogtreecommitdiffstats
path: root/recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch
diff options
context:
space:
mode:
Diffstat (limited to 'recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch')
-rw-r--r--recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch30
1 files changed, 30 insertions, 0 deletions
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch
new file mode 100644
index 0000000000..150dc27016
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch
@@ -0,0 +1,30 @@
+this patch adds support for the RTL8201CP PHY
+
+--- ixp400_xscale_sw/src/ethMii/IxEthMii.c 1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethMii/IxEthMii.c 1970-01-01 00:00:00.000000000 +0000
+@@ -119,6 +119,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3
+ || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID)
+ || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID)
+ || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID)
++ || (ixEthMiiPhyId[i] == IX_ETH_MII_RTL8201_PHY_ID)
+ )
+ {
+ /* supported phy */
+@@ -287,6 +288,7 @@ ixEthMiiPhyReset(UINT32 phyAddr)
+ (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) ||
+ (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID) ||
+ (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID) ||
++ (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_RTL8201_PHY_ID) ||
+ (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
+ )
+ {
+--- ixp400_xscale_sw/src/ethMii/IxEthMii_p.h 1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethMii/IxEthMii_p.h 1970-01-01 00:00:00.000000000 +0000
+@@ -179,6 +179,7 @@
+ #define IX_ETH_MII_LXT973A3_PHY_ID 0x00137A11
+ #define IX_ETH_MII_KS8995_PHY_ID 0x00221450
+ #define IX_ETH_MII_LXT9785_PHY_ID 0x001378FF
++#define IX_ETH_MII_RTL8201_PHY_ID 0x00008201
+ #define IX_ETH_MII_RTL8305_FAKE_PHY_ID 0x83058305
+
+ #define IX_ETH_MII_INVALID_PHY_ID 0x00000000