Index: oprofile-0.9.3/ChangeLog =================================================================== --- oprofile-0.9.3.orig/ChangeLog 2007-07-16 20:22:17.000000000 +0200 +++ oprofile-0.9.3/ChangeLog 2008-08-08 15:41:09.194935711 +0200 @@ -1,3 +1,14 @@ + +2008-04-23 Jean Pihet + + * events/arm/armv7/events: + * events/arm/armv7/unit_masks: + * libop/op_cpu_type.c: + * libop/op_cpu_type.h: + * libop/op_events.c: + * utils/ophelp.c: Added ARMv7 support to be consistent with the kernel, + remove some duplicate code and add some extra events + 2007-07-09 Maynard Johnson * doc/opreport.xsd: Index: oprofile-0.9.3/events/arm/armv7/events =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ oprofile-0.9.3/events/arm/armv7/events 2008-08-08 15:41:09.198936463 +0200 @@ -0,0 +1,53 @@ +# ARM V7 events +# From Cortex A8 DDI (ARM DDI 0344B, revision r1p1) +# +event:0x00 counters:1,2,3,4 um:zero minimum:500 name:PMNC_SW_INCR : Software increment of PMNC registers +event:0x01 counters:1,2,3,4 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory +event:0x02 counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB +event:0x03 counters:1,2,3,4 um:zero minimum:500 name:DCACHE_REFILL : Data R/W operation that causes a refill from cache or normal cacheable memory +event:0x04 counters:1,2,3,4 um:zero minimum:500 name:DCACHE_ACCESS : Data R/W from cache +event:0x05 counters:1,2,3,4 um:zero minimum:500 name:DTLB_REFILL : Data R/W that causes a TLB refill +event:0x06 counters:1,2,3,4 um:zero minimum:500 name:DREAD : Data read architecturally executed (note: architecturally executed = for instructions that are unconditional or that pass the condition code) +event:0x07 counters:1,2,3,4 um:zero minimum:500 name:DWRITE : Data write architecturally executed +event:0x08 counters:1,2,3,4 um:zero minimum:500 name:INSTR_EXECUTED : All executed instructions +event:0x09 counters:1,2,3,4 um:zero minimum:500 name:EXC_TAKEN : Exception taken +event:0x0A counters:1,2,3,4 um:zero minimum:500 name:EXC_EXECUTED : Exception return architecturally executed +event:0x0B counters:1,2,3,4 um:zero minimum:500 name:CID_WRITE : Instruction that writes to the Context ID Register architecturally executed +event:0x0C counters:1,2,3,4 um:zero minimum:500 name:PC_WRITE : SW change of PC, architecturally executed (not by exceptions) +event:0x0D counters:1,2,3,4 um:zero minimum:500 name:PC_IMM_BRANCH : Immediate branch instruction executed (taken or not) +event:0x0E counters:1,2,3,4 um:zero minimum:500 name:PC_PROC_RETURN : Procedure return architecturally executed (not by exceptions) +event:0x0F counters:1,2,3,4 um:zero minimum:500 name:UNALIGNED_ACCESS : Unaligned access architecturally executed +event:0x10 counters:1,2,3,4 um:zero minimum:500 name:PC_BRANCH_MIS_PRED : Branch mispredicted or not predicted. Counts pipeline flushes because of misprediction +event:0x12 counters:1,2,3,4 um:zero minimum:500 name:PC_BRANCH_MIS_USED : Branch or change in program flow that could have been predicted +event:0x40 counters:1,2,3,4 um:zero minimum:500 name:WRITE_BUFFER_FULL : Any write buffer full cycle +event:0x41 counters:1,2,3,4 um:zero minimum:500 name:L2_STORE_MERGED : Any store that is merged in L2 cache +event:0x42 counters:1,2,3,4 um:zero minimum:500 name:L2_STORE_BUFF : Any bufferable store from load/store to L2 cache +event:0x43 counters:1,2,3,4 um:zero minimum:500 name:L2_ACCESS : Any access to L2 cache +event:0x44 counters:1,2,3,4 um:zero minimum:500 name:L2_CACH_MISS : Any cacheable miss in L2 cache +event:0x45 counters:1,2,3,4 um:zero minimum:500 name:AXI_READ_CYCLES : Number of cycles for an active AXI read +event:0x46 counters:1,2,3,4 um:zero minimum:500 name:AXI_WRITE_CYCLES : Number of cycles for an active AXI write +event:0x47 counters:1,2,3,4 um:zero minimum:500 name:MEMORY_REPLAY : Any replay event in the memory subsystem +event:0x48 counters:1,2,3,4 um:zero minimum:500 name:UNALIGNED_ACCESS_REPLAY : Unaligned access that causes a replay +event:0x49 counters:1,2,3,4 um:zero minimum:500 name:L1_DATA_MISS : L1 data cache miss as a result of the hashing algorithm +event:0x4A counters:1,2,3,4 um:zero minimum:500 name:L1_INST_MISS : L1 instruction cache miss as a result of the hashing algorithm +event:0x4B counters:1,2,3,4 um:zero minimum:500 name:L1_DATA_COLORING : L1 data access in which a page coloring alias occurs +event:0x4C counters:1,2,3,4 um:zero minimum:500 name:L1_NEON_DATA : NEON data access that hits L1 cache +event:0x4D counters:1,2,3,4 um:zero minimum:500 name:L1_NEON_CACH_DATA : NEON cacheable data access that hits L1 cache +event:0x4E counters:1,2,3,4 um:zero minimum:500 name:L2_NEON : L2 access as a result of NEON memory access +event:0x4F counters:1,2,3,4 um:zero minimum:500 name:L2_NEON_HIT : Any NEON hit in L2 cache +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:L1_INST : Any L1 instruction cache access, excluding CP15 cache accesses +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:PC_RETURN_MIS_PRED : Return stack misprediction at return stack pop (incorrect target address) +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:PC_BRANCH_FAILED : Branch prediction misprediction +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:PC_BRANCH_TAKEN : Any predicted branch that is taken +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:PC_BRANCH_EXECUTED : Any taken branch that is executed +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:OP_EXECUTED : Number of operations executed (in instruction or mutli-cycle instruction) +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_INST_STALL : Cycles where no instruction available +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_INST : Number of instructions issued in a cycle +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_NEON_DATA_STALL : Number of cycles the processor waits on MRC data from NEON +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_NEON_INST_STALL : Number of cycles the processor waits on NEON instruction queue or NEON load queue +event:0x5A counters:1,2,3,4 um:zero minimum:500 name:NEON_CYCLES : Number of cycles NEON and integer processors are not idle +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:PMU0_EVENTS : Number of events from external input source PMUEXTIN[0] +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:PMU1_EVENTS : Number of events from external input source PMUEXTIN[1] +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:PMU_EVENTS : Number of events from both external input sources PMUEXTIN[0] and PMUEXTIN[1] +event:0xFF counters:0 um:zero minimum:500 name:CPU_CYCLES : Number of CPU cycles + Index: oprofile-0.9.3/events/arm/armv7/unit_masks =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ oprofile-0.9.3/events/arm/armv7/unit_masks 2008-08-08 15:41:09.210955689 +0200 @@ -0,0 +1,4 @@ +# ARM V7 PMNC possible unit masks +# +name:zero type:mandatory default:0x00 + 0x00 No unit mask Index: oprofile-0.9.3/libop/op_cpu_type.c =================================================================== --- oprofile-0.9.3.orig/libop/op_cpu_type.c 2007-07-16 20:22:17.000000000 +0200 +++ oprofile-0.9.3/libop/op_cpu_type.c 2008-08-08 15:41:09.242955608 +0200 @@ -71,6 +71,7 @@ { "ppc64 PA6T", "ppc64/pa6t", CPU_PPC64_PA6T, 6 }, { "ARM MPCore", "arm/mpcore", CPU_ARM_MPCORE, 2 }, { "ARM V6 PMU", "arm/armv6", CPU_ARM_V6, 3 }, + { "ARM V7 PMNC", "arm/armv7", CPU_ARM_V7, 5 }, { "ppc64 POWER5++", "ppc64/power5++", CPU_PPC64_POWER5pp, 6 }, }; Index: oprofile-0.9.3/libop/op_cpu_type.h =================================================================== --- oprofile-0.9.3.orig/libop/op_cpu_type.h 2007-07-16 20:22:17.000000000 +0200 +++ oprofile-0.9.3/libop/op_cpu_type.h 2008-08-08 15:41:09.262956072 +0200 @@ -69,6 +69,7 @@ CPU_PPC64_PA6T, /**< ppc64 PA6T */ CPU_ARM_MPCORE, /**< ARM MPCore */ CPU_ARM_V6, /**< ARM V6 */ + CPU_ARM_V7, /**< ARM V7 */ CPU_PPC64_POWER5pp, /**< ppc64 Power5++ family */ MAX_CPU_TYPE } op_cpu; Index: oprofile-0.9.3/libop/op_events.c =================================================================== --- oprofile-0.9.3.orig/libop/op_events.c 2007-07-16 20:22:17.000000000 +0200 +++ oprofile-0.9.3/libop/op_events.c 2008-08-08 15:41:09.278955619 +0200 @@ -788,6 +788,7 @@ case CPU_ARM_XSCALE2: case CPU_ARM_MPCORE: case CPU_ARM_V6: + case CPU_ARM_V7: descr->name = "CPU_CYCLES"; break; Index: oprofile-0.9.3/utils/ophelp.c =================================================================== --- oprofile-0.9.3.orig/utils/ophelp.c 2007-07-16 20:22:17.000000000 +0200 +++ oprofile-0.9.3/utils/ophelp.c 2008-08-08 15:41:09.294934552 +0200 @@ -433,6 +433,11 @@ printf("See ARM11 Technical Reference Manual\n"); break; + case CPU_ARM_V7: + printf("See ARM11 Technical Reference Manual\n" + "Cortex A8 DDI (ARM DDI 0344B, revision r1p1)\n"); + break; + case CPU_PPC64_PA6T: printf("See PA6T Power Implementation Features Book IV\n" "Chapter 7 Performance Counters\n"); Index: oprofile-0.9.3/events/Makefile.am =================================================================== --- oprofile-0.9.3.orig/events/Makefile.am 2008-08-08 15:41:24.746955563 +0200 +++ oprofile-0.9.3/events/Makefile.am 2008-08-08 15:41:43.465544495 +0200 @@ -31,6 +31,7 @@ arm/xscale1/events arm/xscale1/unit_masks \ arm/xscale2/events arm/xscale2/unit_masks \ arm/armv6/events arm/armv6/unit_masks \ + arm/armv7/events arm/armv7/unit_masks \ arm/mpcore/events arm/mpcore/unit_masks \ mips/20K/events mips/20K/unit_masks \ mips/24K/events mips/24K/unit_masks \