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| author |   Khem Raj <raj.khem@gmail.com> | 2022-02-14 15:37:39 -0800 |
|---|---|---|
| committer |   Richard Purdie <richard.purdie@linuxfoundation.org> | 2022-02-16 09:46:25 +0000 |
| commit | 17cd727f333580c6fd7ff20c90ede9ccce9ef60b (patch) | |
| tree | 5c5d1a76b713192e1bd22e11932d3e1b89295b78 /meta/recipes-bsp/u-boot | |
| parent | c48b57aa68149f5bdca80cadbf5b426c209ca94e (diff) | |
| download | openembedded-core-17cd727f333580c6fd7ff20c90ede9ccce9ef60b.tar.gz | |
u-boot: Fix RISCV build with binutils 2.38
Ensure right ABI and march is used which matches OE core settings
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-bsp/u-boot')
3 files changed, 52 insertions, 8 deletions
diff --git a/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch b/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch new file mode 100644 index 0000000000..3598329b99 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch @@ -0,0 +1,40 @@ +From 26a7f6b1e4c5f715c03e59a623f0d620498b92cf Mon Sep 17 00:00:00 2001 +From: Khem Raj <raj.khem@gmail.com> +Date: Sun, 13 Feb 2022 21:11:31 -0800 +Subject: [PATCH] riscv: fix build with binutils 2.38 + +From version 2.38, binutils default to ISA spec version 20191213. This +means that the csr read/write (csrr*/csrw*) instructions and fence.i +instruction has separated from the `I` extension, become two standalone +extensions: Zicsr and Zifencei. + +The fix is to specify those extensions explicitely in -march. However as +older binutils version do not support this, we first need to detect +that. + +Fixes +arch/riscv/lib/cache.c: Assembler messages: +arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i' + +Upstream-Status: Submitted [] +Signed-off-by: Khem Raj <raj.khem@gmail.com> +--- + arch/riscv/Makefile | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -28,7 +28,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany + endif + +-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) -mabi=$(ABI) \ ++# Newer binutils versions default to ISA spec version 20191213 which moves some ++# instructions from the I extension to the Zicsr and Zifencei extensions. ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)_zicsr_zifencei) ++zicsr_zifencei-$(toolchain-need-zicsr-zifencei) := _zicsr_zifencei ++ ++ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)$(zicsr_zifencei-y) -mabi=$(ABI) \ + -mcmodel=$(CMODEL) + + PLATFORM_CPPFLAGS += $(ARCH_FLAGS) diff --git a/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch b/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch index 0ed3de4914..0bf1bef2c9 100644 --- a/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch +++ b/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch @@ -13,11 +13,16 @@ Upstream-Status: Inappropriate [embedded specific] arch/riscv/Makefile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile -index 0b80eb8d86..7324946f48 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile -@@ -9,7 +9,9 @@ ifeq ($(CONFIG_ARCH_RV64I),y) +@@ -5,11 +5,15 @@ + + ifeq ($(CONFIG_ARCH_RV64I),y) + ARCH_BASE = rv64im +- ABI = lp64 ++ ABI = lp64d ++ ARCH_D = d ++ ARCH_F = f endif ifeq ($(CONFIG_ARCH_RV32I),y) ARCH_BASE = rv32im @@ -28,7 +33,7 @@ index 0b80eb8d86..7324946f48 100644 endif ifeq ($(CONFIG_RISCV_ISA_A),y) ARCH_A = a -@@ -24,7 +26,7 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) +@@ -24,7 +28,7 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif @@ -37,6 +42,3 @@ index 0b80eb8d86..7324946f48 100644 -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS) --- -2.30.0 - diff --git a/meta/recipes-bsp/u-boot/u-boot_2022.01.bb b/meta/recipes-bsp/u-boot/u-boot_2022.01.bb index 617827ff08..0d2464d74b 100644 --- a/meta/recipes-bsp/u-boot/u-boot_2022.01.bb +++ b/meta/recipes-bsp/u-boot/u-boot_2022.01.bb @@ -1,7 +1,9 @@ require u-boot-common.inc require u-boot.inc -SRC_URI:append = " file://0001-riscv32-Use-double-float-ABI-for-rv32.patch" +SRC_URI:append = " file://0001-riscv32-Use-double-float-ABI-for-rv32.patch \ + file://0001-riscv-fix-build-with-binutils-2.38.patch \ + " DEPENDS += "bc-native dtc-native python3-setuptools-native" |